mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Fix for RUTX platform
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
ccdb64ad45
commit
59bc57d5d5
7254 changed files with 1810270 additions and 7 deletions
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@ -0,0 +1,49 @@
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#
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# (C) Copyright 2003-2008
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2008
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# Stelian Pop <stelian@popies.net>
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# Lead Tech Design <www.leadtechdesign.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS-y += jadecpu.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(call cmd_link_o_target, $(OBJS) $(SOBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -0,0 +1,173 @@
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/*
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* (c) 2010 Graf-Syteco, Matthias Weisser
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* <weisserm@arcor.de>
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*
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* (C) Copyright 2007, mycable GmbH
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* Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/mb86r0x.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Miscellaneous platform dependent initialisations
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*/
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int board_init(void)
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{
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struct mb86r0x_ccnt * ccnt = (struct mb86r0x_ccnt *)
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MB86R0x_CCNT_BASE;
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/* We select mode 0 for group 2 and mode 1 for group 4 */
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writel(0x00000010, &ccnt->cmux_md);
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gd->flags = 0;
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gd->bd->bi_boot_params = PHYS_SDRAM + PHYS_SDRAM_SIZE - 0x10000;
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icache_enable();
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dcache_enable();
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return 0;
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}
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static void setup_display_power(uint32_t pwr_bit, char *pwm_opts,
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unsigned long pwm_base)
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{
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struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *)
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MB86R0x_GPIO_BASE;
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struct mb86r0x_pwm *pwm = (struct mb86r0x_pwm *) pwm_base;
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const char *e;
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writel(readl(&gpio->gpdr2) | pwr_bit, &gpio->gpdr2);
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e = getenv(pwm_opts);
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if (e != NULL) {
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const char *s;
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uint32_t freq, init;
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freq = 0;
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init = 0;
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s = strchr(e, 'f');
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if (s != NULL)
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freq = simple_strtol(s + 2, NULL, 0);
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s = strchr(e, 'i');
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if (s != NULL)
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init = simple_strtol(s + 2, NULL, 0);
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if (freq > 0) {
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writel(CONFIG_MB86R0x_IOCLK / 1000 / freq,
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&pwm->bcr);
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writel(1002, &pwm->tpr);
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writel(1, &pwm->pr);
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writel(init * 10 + 1, &pwm->dr);
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writel(1, &pwm->cr);
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writel(1, &pwm->sr);
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}
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}
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}
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int board_late_init(void)
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{
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struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *)
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MB86R0x_GPIO_BASE;
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uint32_t in_word;
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#ifdef CONFIG_VIDEO_MB86R0xGDC
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/* Check if we have valid display settings and turn on power if so */
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/* Display 0 */
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if (getenv("gs_dsp_0_param") || getenv("videomode"))
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setup_display_power((1 << 3), "gs_dsp_0_pwm",
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MB86R0x_PWM0_BASE);
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/* The corresponding GPIO is always an output */
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writel(readl(&gpio->gpddr2) | (1 << 3), &gpio->gpddr2);
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/* Display 1 */
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if (getenv("gs_dsp_1_param") || getenv("videomode1"))
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setup_display_power((1 << 4), "gs_dsp_1_pwm",
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MB86R0x_PWM1_BASE);
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/* The corresponding GPIO is always an output */
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writel(readl(&gpio->gpddr2) | (1 << 4), &gpio->gpddr2);
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#endif /* CONFIG_VIDEO_MB86R0xGDC */
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/* 5V enable */
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writel(readl(&gpio->gpdr1) & ~(1 << 5), &gpio->gpdr1);
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writel(readl(&gpio->gpddr1) | (1 << 5), &gpio->gpddr1);
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/* We have special boot options if told by GPIOs */
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in_word = readl(&gpio->gpdr1);
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if ((in_word & 0xC0) == 0xC0) {
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setenv("stdin", "serial");
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setenv("stdout", "serial");
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setenv("stderr", "serial");
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setenv("preboot", "run gs_slow_boot");
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} else if ((in_word & 0xC0) != 0) {
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setenv("stdout", "vga");
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setenv("preboot", "run gs_slow_boot");
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} else {
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setenv("stdin", "serial");
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setenv("stdout", "serial");
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setenv("stderr", "serial");
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if (getenv("gs_devel")) {
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setenv("preboot", "run gs_slow_boot");
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} else {
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setenv("preboot", "run gs_fast_boot");
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}
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}
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return 0;
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}
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int misc_init_r(void)
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{
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return 0;
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}
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/*
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* DRAM configuration
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*/
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
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PHYS_SDRAM_SIZE);
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return 0;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM;
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gd->bd->bi_dram[0].size = gd->ram_size;
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}
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC911X
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
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#endif
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return rc;
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}
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@ -0,0 +1,265 @@
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/*
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* Board specific setup info
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*
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* (C) Copyright 2007, mycable GmbH
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* Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de>
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*
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* (C) Copyright 2003, ARM Ltd.
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* Philippe Robin, <philippe.robin@arm.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/macro.h>
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#include <asm/arch/mb86r0x.h>
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#include <generated/asm-offsets.h>
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/* Set up the platform, once the cpu has been initialized */
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.globl lowlevel_init
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lowlevel_init:
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/*
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* Initialize Clock Reset Generator (CRG)
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*/
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ldr r0, =MB86R0x_CRG_BASE
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/* Not change the initial value that is set by external pin.*/
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WAIT_PLL:
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ldr r2, [r0, #CRG_CRPR] /* Wait for PLLREADY */
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tst r2, #MB86R0x_CRG_CRPR_PLLRDY
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beq WAIT_PLL
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/* Set clock gate control */
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ldr r1, =CONFIG_SYS_CRG_CRHA_INIT
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str r1, [r0, #CRG_CRHA]
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ldr r1, =CONFIG_SYS_CRG_CRPA_INIT
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str r1, [r0, #CRG_CRPA]
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ldr r1, =CONFIG_SYS_CRG_CRPB_INIT
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str r1, [r0, #CRG_CRPB]
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ldr r1, =CONFIG_SYS_CRG_CRHB_INIT
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str r1, [r0, #CRG_CRHB]
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ldr r1, =CONFIG_SYS_CRG_CRAM_INIT
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str r1, [r0, #CRG_CRAM]
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/*
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* Initialize External Bus Interface
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*/
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ldr r0, =MB86R0x_MEMC_BASE
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ldr r1, =CONFIG_SYS_MEMC_MCFMODE0_INIT
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str r1, [r0, #MEMC_MCFMODE0]
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ldr r1, =CONFIG_SYS_MEMC_MCFMODE2_INIT
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str r1, [r0, #MEMC_MCFMODE2]
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ldr r1, =CONFIG_SYS_MEMC_MCFMODE4_INIT
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str r1, [r0, #MEMC_MCFMODE4]
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ldr r1, =CONFIG_SYS_MEMC_MCFTIM0_INIT
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str r1, [r0, #MEMC_MCFTIM0]
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ldr r1, =CONFIG_SYS_MEMC_MCFTIM2_INIT
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str r1, [r0, #MEMC_MCFTIM2]
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ldr r1, =CONFIG_SYS_MEMC_MCFTIM4_INIT
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str r1, [r0, #MEMC_MCFTIM4]
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ldr r1, =CONFIG_SYS_MEMC_MCFAREA0_INIT
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str r1, [r0, #MEMC_MCFAREA0]
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ldr r1, =CONFIG_SYS_MEMC_MCFAREA2_INIT
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str r1, [r0, #MEMC_MCFAREA2]
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ldr r1, =CONFIG_SYS_MEMC_MCFAREA4_INIT
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str r1, [r0, #MEMC_MCFAREA4]
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/*
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* Initialize DDR2 Controller
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*/
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/* Wait for PLL LOCK up time or more */
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wait_timer 20
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/*
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* (2) Initialize DDRIF
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*/
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ldr r0, =MB86R0x_DDR2_BASE
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ldr r1, =CONFIG_SYS_DDR2_DRIMS_INIT
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strh r1, [r0, #DDR2_DRIMS]
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/*
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* (3) Wait for 20MCKPs(120nsec) or more
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*/
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wait_timer 20
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/*
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* (4) IRESET/IUSRRST release
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*/
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ldr r0, =MB86R0x_CCNT_BASE
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ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_1
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str r1, [r0, #CCNT_CDCRC]
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/*
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* (5) Wait for 20MCKPs(120nsec) or more
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*/
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wait_timer 20
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/*
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* (6) IDLLRST release
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*/
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ldr r0, =MB86R0x_CCNT_BASE
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ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_2
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str r1, [r0, #CCNT_CDCRC]
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/*
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* (7+8) Wait for 200us(=200000ns) or more (DDR2 Spec)
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*/
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wait_timer 33536
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/*
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* (9) MCKE ON
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*/
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ldr r0, =MB86R0x_DDR2_BASE
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ldr r1, =CONFIG_SYS_DDR2_DRIC1_INIT
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strh r1, [r0, #DDR2_DRIC1]
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ldr r1, =CONFIG_SYS_DDR2_DRIC2_INIT
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strh r1, [r0, #DDR2_DRIC2]
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ldr r1, =CONFIG_SYS_DDR2_DRCA_INIT
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strh r1, [r0, #DDR2_DRCA]
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ldr r1, =MB86R0x_DDR2_DRCI_INIT
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strh r1, [r0, #DDR2_DRIC]
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/*
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* (10) Initialize SDRAM
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*/
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ldr r1, =MB86R0x_DDR2_DRCI_CMD
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strh r1, [r0, #DDR2_DRIC]
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wait_timer 67 /* 400ns wait */
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_1
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strh r1, [r0, #DDR2_DRIC1]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_1
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strh r1, [r0, #DDR2_DRIC2]
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ldr r1, =MB86R0x_DDR2_DRCI_CMD
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strh r1, [r0, #DDR2_DRIC]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_2
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strh r1, [r0, #DDR2_DRIC1]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_2
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strh r1, [r0, #DDR2_DRIC2]
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ldr r1, =MB86R0x_DDR2_DRCI_CMD
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strh r1, [r0, #DDR2_DRIC]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_3
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strh r1, [r0, #DDR2_DRIC1]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_3
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strh r1, [r0, #DDR2_DRIC2]
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ldr r1, =MB86R0x_DDR2_DRCI_CMD
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strh r1, [r0, #DDR2_DRIC]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_4
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strh r1, [r0, #DDR2_DRIC1]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_4
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strh r1, [r0, #DDR2_DRIC2]
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ldr r1, =MB86R0x_DDR2_DRCI_CMD
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strh r1, [r0, #DDR2_DRIC]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_5
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strh r1, [r0, #DDR2_DRIC1]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_5
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strh r1, [r0, #DDR2_DRIC2]
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ldr r1, =MB86R0x_DDR2_DRCI_CMD
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strh r1, [r0, #DDR2_DRIC]
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wait_timer 200
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_6
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strh r1, [r0, #DDR2_DRIC1]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_6
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strh r1, [r0, #DDR2_DRIC2]
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ldr r1, =MB86R0x_DDR2_DRCI_CMD
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strh r1, [r0, #DDR2_DRIC]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_7
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strh r1, [r0, #DDR2_DRIC1]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_7
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strh r1, [r0, #DDR2_DRIC2]
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ldr r1, =MB86R0x_DDR2_DRCI_CMD
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strh r1, [r0, #DDR2_DRIC]
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wait_timer 18 /* 105ns wait */
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_8
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strh r1, [r0, #DDR2_DRIC1]
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ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_8
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strh r1, [r0, #DDR2_DRIC2]
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ldr r1, =MB86R0x_DDR2_DRCI_CMD
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strh r1, [r0, #DDR2_DRIC]
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wait_timer 200 /* MRS to OCD: 200clock */
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|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_9
|
||||
strh r1, [r0, #DDR2_DRIC1]
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_9
|
||||
strh r1, [r0, #DDR2_DRIC2]
|
||||
ldr r1, =MB86R0x_DDR2_DRCI_CMD
|
||||
strh r1, [r0, #DDR2_DRIC]
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_10
|
||||
strh r1, [r0, #DDR2_DRIC1]
|
||||
ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_10
|
||||
strh r1, [r0, #DDR2_DRIC2]
|
||||
ldr r1, =MB86R0x_DDR2_DRCI_CMD
|
||||
strh r1, [r0, #DDR2_DRIC]
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_DRCM_INIT
|
||||
strh r1, [r0, #DDR2_DRCM]
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_DRCST1_INIT
|
||||
strh r1, [r0, #DDR2_DRCST1]
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_DRCST2_INIT
|
||||
strh r1, [r0, #DDR2_DRCST2]
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_DRCR_INIT
|
||||
strh r1, [r0, #DDR2_DRCR]
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_DRCF_INIT
|
||||
strh r1, [r0, #DDR2_DRCF]
|
||||
|
||||
ldr r1, =CONFIG_SYS_DDR2_DRASR_INIT
|
||||
strh r1, [r0, #DDR2_DRASR]
|
||||
|
||||
/*
|
||||
* (11) ODT setting
|
||||
*/
|
||||
ldr r1, =CONFIG_SYS_DDR2_DROBS_INIT
|
||||
strh r1, [r0, #DDR2_DROBS]
|
||||
ldr r1, =CONFIG_SYS_DDR2_DROABA_INIT
|
||||
strh r1, [r0, #DDR2_DROABA]
|
||||
ldr r1, =CONFIG_SYS_DDR2_DRIBSODT1_INIT
|
||||
strh r1, [r0, #DDR2_DRIBSODT1]
|
||||
|
||||
/*
|
||||
* (12) Shift to ODTCONT ON (SDRAM side) and DDR2 usual operation mode
|
||||
*/
|
||||
ldr r1, =CONFIG_SYS_DDR2_DROS_INIT
|
||||
strh r1, [r0, #DDR2_DROS]
|
||||
ldr r1, =MB86R0x_DDR2_DRCI_NORMAL
|
||||
strh r1, [r0, #DDR2_DRIC]
|
||||
|
||||
mov pc, lr
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
#
|
||||
# (c) 2010 Graf-Syteco, Matthias Weisser
|
||||
# <weisserm@arcor.de>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).o
|
||||
|
||||
COBJS-y += zmx25.o
|
||||
SOBJS := lowlevel_init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS-y))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
@ -0,0 +1,110 @@
|
|||
/*
|
||||
* (C) Copyright 2011
|
||||
* Matthias Weisser <weisserm@arcor.de>
|
||||
*
|
||||
* (C) Copyright 2009 DENX Software Engineering
|
||||
* Author: John Rigby <jrigby@gmail.com>
|
||||
*
|
||||
* Based on U-Boot and RedBoot sources for several different i.mx
|
||||
* platforms.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <asm/macro.h>
|
||||
#include <asm/arch/macro.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <generated/asm-offsets.h>
|
||||
|
||||
/*
|
||||
* clocks
|
||||
*/
|
||||
.macro init_clocks
|
||||
|
||||
/* disable clock output */
|
||||
write32 IMX_CCM_BASE + CCM_MCR, 0x00000000
|
||||
write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000
|
||||
|
||||
/*
|
||||
* enable all implemented clocks in all three
|
||||
* clock control registers
|
||||
*/
|
||||
write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff
|
||||
write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff
|
||||
write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff
|
||||
|
||||
/* Devide NAND clock by 32 */
|
||||
write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F
|
||||
.endm
|
||||
|
||||
/*
|
||||
* sdram controller init
|
||||
*/
|
||||
.macro init_lpddr
|
||||
ldr r0, =IMX_ESDRAMC_BASE
|
||||
ldr r2, =IMX_SDRAM_BANK0_BASE
|
||||
|
||||
/*
|
||||
* reset SDRAM controller
|
||||
* then wait for initialization to complete
|
||||
*/
|
||||
ldr r1, =(1 << 1) | (1 << 2)
|
||||
str r1, [r0, #ESDRAMC_ESDMISC]
|
||||
1: ldr r3, [r0, #ESDRAMC_ESDMISC]
|
||||
tst r3, #(1 << 31)
|
||||
beq 1b
|
||||
ldr r1, =(1 << 2)
|
||||
str r1, [r0, #ESDRAMC_ESDMISC]
|
||||
|
||||
ldr r1, =0x002a7420
|
||||
str r1, [r0, #ESDRAMC_ESDCFG0]
|
||||
|
||||
/* control | precharge */
|
||||
ldr r1, =0x92216008
|
||||
str r1, [r0, #ESDRAMC_ESDCTL0]
|
||||
/* dram command encoded in address */
|
||||
str r1, [r2, #0x400]
|
||||
|
||||
/* auto refresh */
|
||||
ldr r1, =0xa2216008
|
||||
str r1, [r0, #ESDRAMC_ESDCTL0]
|
||||
/* read dram twice to auto refresh */
|
||||
ldr r3, [r2]
|
||||
ldr r3, [r2]
|
||||
|
||||
/* control | load mode */
|
||||
ldr r1, =0xb2216008
|
||||
str r1, [r0, #ESDRAMC_ESDCTL0]
|
||||
|
||||
/* mode register of lpddram */
|
||||
strb r1, [r2, #0x33]
|
||||
|
||||
/* extended mode register of lpddrram */
|
||||
ldr r2, =0x81000000
|
||||
strb r1, [r2]
|
||||
|
||||
/* control | normal */
|
||||
ldr r1, =0x82216008
|
||||
str r1, [r0, #ESDRAMC_ESDCTL0]
|
||||
.endm
|
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init:
|
||||
init_aips
|
||||
init_max
|
||||
init_clocks
|
||||
init_lpddr
|
||||
mov pc, lr
|
||||
|
|
@ -0,0 +1,186 @@
|
|||
/*
|
||||
* (c) 2011 Graf-Syteco, Matthias Weisser
|
||||
* <weisserm@arcor.de>
|
||||
*
|
||||
* Based on tx25.c:
|
||||
* (C) Copyright 2009 DENX Software Engineering
|
||||
* Author: John Rigby <jrigby@gmail.com>
|
||||
*
|
||||
* Based on imx27lite.c:
|
||||
* Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
|
||||
* Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
|
||||
* And:
|
||||
* RedBoot tx25_misc.c Copyright (C) 2009 Red Hat
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/imx25-pinmux.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int board_init()
|
||||
{
|
||||
struct iomuxc_mux_ctl *muxctl;
|
||||
struct iomuxc_pad_ctl *padctl;
|
||||
struct iomuxc_pad_input_select *inputselect;
|
||||
u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION;
|
||||
u32 gpio_mux_mode1 = MX25_PIN_MUX_MODE(1);
|
||||
u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5);
|
||||
u32 gpio_mux_mode6 = MX25_PIN_MUX_MODE(6);
|
||||
u32 input_select1 = MX25_PAD_INPUT_SELECT_DAISY(1);
|
||||
u32 input_select2 = MX25_PAD_INPUT_SELECT_DAISY(2);
|
||||
|
||||
icache_enable();
|
||||
|
||||
muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
|
||||
padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
|
||||
inputselect = (struct iomuxc_pad_input_select *)IMX_IOPADINPUTSEL_BASE;
|
||||
|
||||
/* Setup of core volatage selection pin to run at 1.4V */
|
||||
writel(gpio_mux_mode5, &muxctl->pad_ext_armclk); /* VCORE GPIO3[15] */
|
||||
gpio_direction_output(MXC_GPIO_PORT_TO_NUM(3, 15), 1);
|
||||
|
||||
/* Setup of input daisy chains for SD card pins*/
|
||||
writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_cmd);
|
||||
writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_clk);
|
||||
writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data0);
|
||||
writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data1);
|
||||
writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data2);
|
||||
writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data3);
|
||||
|
||||
/* Setup of digital output for USB power and OC */
|
||||
writel(gpio_mux_mode5, &muxctl->pad_csi_d3); /* USB Power GPIO1[28] */
|
||||
gpio_direction_output(MXC_GPIO_PORT_TO_NUM(1, 28), 1);
|
||||
|
||||
writel(gpio_mux_mode5, &muxctl->pad_csi_d2); /* USB OC GPIO1[27] */
|
||||
gpio_direction_input(MXC_GPIO_PORT_TO_NUM(1, 18));
|
||||
|
||||
/* Setup of digital output control pins */
|
||||
writel(gpio_mux_mode5, &muxctl->pad_csi_d8); /* Ouput 1 Ctrl GPIO1[7] */
|
||||
writel(gpio_mux_mode5, &muxctl->pad_csi_d7); /* Ouput 2 Ctrl GPIO1[6] */
|
||||
writel(gpio_mux_mode5, &muxctl->pad_csi_d6); /* Ouput 1 Stat GPIO1[31]*/
|
||||
writel(gpio_mux_mode5, &muxctl->pad_csi_d5); /* Ouput 2 Stat GPIO1[30]*/
|
||||
|
||||
writel(0, &padctl->pad_csi_d6); /* Ouput 1 Stat pull up off */
|
||||
writel(0, &padctl->pad_csi_d5); /* Ouput 2 Stat pull up off */
|
||||
|
||||
/* Switch both output drivers off */
|
||||
gpio_direction_output(MXC_GPIO_PORT_TO_NUM(1, 7), 0);
|
||||
gpio_direction_output(MXC_GPIO_PORT_TO_NUM(1, 6), 0);
|
||||
|
||||
/* Setup of key input pin GPIO2[29]*/
|
||||
writel(gpio_mux_mode5 | MX25_PIN_MUX_SION, &muxctl->pad_kpp_row0);
|
||||
writel(0, &padctl->pad_kpp_row0); /* Key pull up off */
|
||||
gpio_direction_input(MXC_GPIO_PORT_TO_NUM(2, 29));
|
||||
|
||||
/* Setup of status LED outputs */
|
||||
writel(gpio_mux_mode5, &muxctl->pad_csi_d9); /* GPIO4[21] */
|
||||
writel(gpio_mux_mode5, &muxctl->pad_csi_d4); /* GPIO1[29] */
|
||||
|
||||
/* Switch both LEDs off */
|
||||
gpio_direction_output(MXC_GPIO_PORT_TO_NUM(4, 21), 0);
|
||||
gpio_direction_output(MXC_GPIO_PORT_TO_NUM(1, 29), 0);
|
||||
|
||||
/* Setup of CAN1 and CAN2 signals */
|
||||
writel(gpio_mux_mode6, &muxctl->pad_gpio_a); /* CAN1 TX */
|
||||
writel(gpio_mux_mode6, &muxctl->pad_gpio_b); /* CAN1 RX */
|
||||
writel(gpio_mux_mode6, &muxctl->pad_gpio_c); /* CAN2 TX */
|
||||
writel(gpio_mux_mode6, &muxctl->pad_gpio_d); /* CAN2 RX */
|
||||
|
||||
/* Setup of input daisy chains for CAN signals*/
|
||||
writel(input_select1, &inputselect->can1_ipp_ind_canrx); /* CAN1 RX */
|
||||
writel(input_select1, &inputselect->can2_ipp_ind_canrx); /* CAN2 RX */
|
||||
|
||||
/* Setup of I2C3 signals */
|
||||
writel(gpio_mux_mode1, &muxctl->pad_cspi1_ss1); /* I2C3 SDA */
|
||||
writel(gpio_mux_mode1, &muxctl->pad_gpio_e); /* I2C3 SCL */
|
||||
|
||||
/* Setup of input daisy chains for I2C3 signals*/
|
||||
writel(input_select1, &inputselect->i2c3_ipp_sda_in); /* I2C3 SDA */
|
||||
writel(input_select2, &inputselect->i2c3_ipp_scl_in); /* I2C3 SCL */
|
||||
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
const char *e;
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
struct iomuxc_mux_ctl *muxctl;
|
||||
u32 gpio_mux_mode2 = MX25_PIN_MUX_MODE(2);
|
||||
u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5);
|
||||
|
||||
/*
|
||||
* fec pin init is generic
|
||||
*/
|
||||
mx25_fec_init_pins();
|
||||
|
||||
/*
|
||||
* Set up LAN-RESET and FEC_RX_ERR
|
||||
*
|
||||
* LAN-RESET: GPIO3[16] is ALT 5 mode of pin U20
|
||||
* FEC_RX_ERR: FEC_RX_ERR is ALT 2 mode of pin R2
|
||||
*/
|
||||
muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
|
||||
|
||||
writel(gpio_mux_mode5, &muxctl->pad_upll_bypclk);
|
||||
writel(gpio_mux_mode2, &muxctl->pad_uart2_cts);
|
||||
|
||||
/* assert PHY reset (low) */
|
||||
gpio_direction_output(MXC_GPIO_PORT_TO_NUM(3, 16), 0);
|
||||
|
||||
udelay(5000);
|
||||
|
||||
/* deassert PHY reset */
|
||||
gpio_set_value(MXC_GPIO_PORT_TO_NUM(3, 16), 1);
|
||||
|
||||
udelay(5000);
|
||||
#endif
|
||||
|
||||
e = getenv("gs_base_board");
|
||||
if (e != NULL) {
|
||||
if (strcmp(e, "G283") == 0) {
|
||||
int key = gpio_get_value(MXC_GPIO_PORT_TO_NUM(2, 29));
|
||||
|
||||
if (key) {
|
||||
/* Switch on both LEDs to inidcate boot mode */
|
||||
gpio_set_value(MXC_GPIO_PORT_TO_NUM(1, 29), 0);
|
||||
gpio_set_value(MXC_GPIO_PORT_TO_NUM(4, 21), 0);
|
||||
|
||||
setenv("preboot", "run gs_slow_boot");
|
||||
} else
|
||||
setenv("preboot", "run gs_fast_boot");
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
/* dram_init must store complete ramsize in gd->ram_size */
|
||||
gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
|
||||
PHYS_SDRAM_SIZE);
|
||||
return 0;
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue