mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
修复CM520的op启动
This commit is contained in:
suyuan
parent
db27abcc82
commit
6083c17a63
12 changed files with 5179 additions and 76 deletions
32
.gitignore
vendored
32
.gitignore
vendored
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@ -1,3 +1,29 @@
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sdk
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source
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feeds
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*.o
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.DS_Store
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.*.swp
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/env
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/dl
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/.config
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/.config.old
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/bin
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/build_dir
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/staging_dir
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/tmp
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/logs
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/feeds
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/feeds.conf
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/files
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/overlay
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/package/feeds
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/package/openwrt-packages
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key-build*
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*.orig
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*.rej
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*~
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.#*
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*#
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.emacs.desktop*
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TAGS*~
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git-src
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.git-credentials
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/*.log
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|
|
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44
config
44
config
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@ -38,7 +38,7 @@ CONFIG_BUSYBOX_CONFIG_WATCH=y
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# CONFIG_GDB is not set
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CONFIG_GRUB_SERIAL=""
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CONFIG_GRUB_TIMEOUT="0"
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CONFIG_GRUB_TITLE="OpenMPTCProuter"
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CONFIG_GRUB_TITLE="antrouter"
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CONFIG_KERNEL_AIO=y
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CONFIG_KERNEL_DEBUG_GPIO=y
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# CONFIG_KERNEL_DEBUG_INFO is not set
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@ -206,43 +206,23 @@ CONFIG_KERNEL_MPTCP_REDUNDANT=y
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CONFIG_KERNEL_DEFAULT_SCHEDULER=y
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CONFIG_KERNEL_MPTCP=y
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CONFIG_KERNEL_CRYPTO_SHA256=y
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CONFIG_LUCI_LANG_hu=y
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CONFIG_LUCI_LANG_pt=y
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CONFIG_LUCI_LANG_sk=y
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CONFIG_LUCI_LANG_ro=y
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CONFIG_LUCI_LANG_en=y
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CONFIG_LUCI_LANG_pl=y
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CONFIG_LUCI_LANG_uk=y
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CONFIG_LUCI_LANG_ja=y
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CONFIG_LUCI_LANG_vi=y
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CONFIG_LUCI_LANG_de=y
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CONFIG_LUCI_LANG_no=y
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CONFIG_LUCI_LANG_ms=y
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CONFIG_LUCI_LANG_zh_Hans=y
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CONFIG_LUCI_LANG_zh_Hant=y
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CONFIG_LUCI_LANG_ko=y
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CONFIG_LUCI_LANG_he=y
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CONFIG_LUCI_LANG_zh-tw=y
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CONFIG_LUCI_LANG_tr=y
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CONFIG_LUCI_LANG_sv=y
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CONFIG_LUCI_LANG_ru=y
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CONFIG_LUCI_LANG_el=y
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CONFIG_LUCI_LANG_ca=y
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CONFIG_LUCI_LANG_es=y
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CONFIG_LUCI_LANG_pt_BR=y
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CONFIG_LUCI_LANG_cs=y
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CONFIG_LUCI_LANG_fr=y
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CONFIG_LUCI_LANG_it=y
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CONFIG_LUCI_LANG_ar=y
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CONFIG_LUCI_LANG_bg=y
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CONFIG_LUCI_LANG_bn_BD=y
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CONFIG_LUCI_LANG_fi=y
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CONFIG_LUCI_LANG_hi=y
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CONFIG_LUCI_LANG_mr=y
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CONFIG_LUCI_LANG_nb_NO=y
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CONFIG_TARGET_ROOTFS_PARTSIZE=512
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CONFIG_TARGET_KERNEL_PARTSIZE=64
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CONFIG_OPENSSL_WITH_CHACHA_POLY1305=y
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# CONFIG_LUCI_CSSTIDY is not set
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# CONFIG_LIBCURL_WOLFSSL is not set
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# CONFIG_PACKAGE_libustream-wolfssl is not set
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# CONFIG_PACKAGE_luci-theme-argon=y
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CONFIG_PACKAGE_luci-theme-bootstrap=y
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CONFIG_PACKAGE_luci-theme-openwrt-2020=y
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# CONFIG_PACKAGE_luci-theme-argon is not set
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CONFIG_PACKAGE_luci-app-status=m
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CONFIG_PACKAGE_luci-mod-status=y
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CONFIG_PACKAGE_frpc=y
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CONFIG_PACKAGE_rtty-nossl=y
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CONFIG_PACKAGE_minicom=y
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CONFIG_PACKAGE_irqbalance=y
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CONFIG_PACKAGE_mtr=y
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6
config-cm520-79f
Normal file
6
config-cm520-79f
Normal file
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@ -0,0 +1,6 @@
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CONFIG_TARGET_ipq40xx=y
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CONFIG_TARGET_ipq40xx_generic=y
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CONFIG_TARGET_ipq40xx_generic_DEVICE_mobipromo_cm520-79f=y
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CONFIG_PACKAGE_kmod-6lowpan=y
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# CONFIG_KERNEL_CC_OPTIMIZE_FOR_PERFORMANCE is not set
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CONFIG_KERNEL_CC_OPTIMIZE_FOR_SIZE=y
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@ -15,17 +15,21 @@ generate_static_network() {
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set network.loopback.proto='static'
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set network.loopback.ipaddr='127.0.0.1'
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set network.loopback.netmask='255.0.0.0'
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delete network.globals
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set network.globals='globals'
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set network.globals.ula_prefix='auto'
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EOF
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[ -e /proc/sys/net/ipv6 ] && {
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uci -q batch <<-EOF
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delete network.globals
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set network.globals='globals'
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set network.globals.ula_prefix='auto'
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EOF
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}
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if json_is_a dsl object; then
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json_select dsl
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if json_is_a atmbridge object; then
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json_select atmbridge
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local vpi vci encaps payload
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json_get_vars vpi vci encaps payload
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local vpi vci encaps payload nameprefix
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json_get_vars vpi vci encaps payload nameprefix
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uci -q batch <<-EOF
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delete network.atm
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set network.atm='atm-bridge'
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@ -33,6 +37,7 @@ generate_static_network() {
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set network.atm.vci='$vci'
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set network.atm.encaps='$encaps'
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set network.atm.payload='$payload'
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set network.atm.nameprefix='$nameprefix'
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EOF
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json_select ..
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fi
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@ -67,26 +72,11 @@ generate_network() {
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[ -n "$ifname" ] || return
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case "$1" in
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# hack (see /etc/board.d/02_network)
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none) return ;;
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lan*) proto=${proto:-static} ;;
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wan*) proto=${proto:-dhcp} ;;
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# force bridge for multi-interface devices (and lan)
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case "$1:$ifname" in
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*\ * | lan:*) type="bridge" ;;
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esac
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if [ -n "$macaddr" ]; then
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type=macvlan # useless, only for legacy
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uci -q batch <<-EOF
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delete network.${1}_dev
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set network.${1}_dev='device'
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set network.${1}_dev.name='$1'
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set network.${1}_dev.type='$type'
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set network.${1}_dev.ifname='$ifname'
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set network.${1}_dev.macaddr='$macaddr'
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EOF
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ifname=$1
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fi
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uci -q batch <<-EOF
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delete network.$1
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set network.$1='interface'
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@ -95,11 +85,22 @@ generate_network() {
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set network.$1.proto='none'
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EOF
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if [ -n "$macaddr" ]; then
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for name in $ifname; do
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uci -q batch <<-EOF
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delete network.$1_${name/./_}_dev
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set network.$1_${name/./_}_dev='device'
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set network.$1_${name/./_}_dev.name='$name'
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set network.$1_${name/./_}_dev.macaddr='$macaddr'
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EOF
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done
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fi
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case "$protocol" in
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static)
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local ipad
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case "$1" in
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lan) ipad=${ipaddr:-"192.168.100.1"} ;;
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lan) ipad=${ipaddr:-"192.168.1.1"} ;;
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*) ipad=${ipaddr:-"192.168.$((addr_offset++)).1"} ;;
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esac
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@ -109,17 +110,23 @@ generate_network() {
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set network.$1.proto='static'
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set network.$1.ipaddr='$ipad'
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set network.$1.netmask='$netm'
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set network.$1.ip6assign='60'
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EOF
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[ -e /proc/sys/net/ipv6 ] && uci set network.$1.ip6assign='60'
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;;
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dhcp)
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# fixup IPv6 slave interface if parent is a bridge
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[ "$type" = "bridge" ] && ifname="br-$1"
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uci -q batch <<-EOF
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set network.$1.proto='dhcp'
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EOF
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uci set network.$1.proto='dhcp'
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[ -e /proc/sys/net/ipv6 ] && {
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uci -q batch <<-EOF
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delete network.${1}6
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set network.${1}6='interface'
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set network.${1}6.ifname='$ifname'
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set network.${1}6.proto='dhcpv6'
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EOF
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}
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;;
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pppoe)
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@ -127,12 +134,16 @@ generate_network() {
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set network.$1.proto='pppoe'
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set network.$1.username='username'
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set network.$1.password='password'
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set network.$1.ipv6='1'
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delete network.${1}6
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set network.${1}6='interface'
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set network.${1}6.ifname='@${1}'
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set network.${1}6.proto='dhcpv6'
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EOF
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[ -e /proc/sys/net/ipv6 ] && {
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uci -q batch <<-EOF
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set network.$1.ipv6='1'
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delete network.${1}6
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set network.${1}6='interface'
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set network.${1}6.ifname='@${1}'
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set network.${1}6.proto='dhcpv6'
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EOF
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}
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;;
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esac
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}
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@ -206,7 +217,8 @@ generate_switch() {
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json_select switch
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json_select "$key"
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json_get_vars enable reset blinkrate cpu_port
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json_get_vars enable reset blinkrate cpu_port \
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ar8xxx_mib_type ar8xxx_mib_poll_interval
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uci -q batch <<-EOF
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add network switch
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@ -214,6 +226,8 @@ generate_switch() {
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set network.@switch[-1].reset='$reset'
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set network.@switch[-1].enable_vlan='$enable'
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set network.@switch[-1].blinkrate='$blinkrate'
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set network.@switch[-1].ar8xxx_mib_type='$ar8xxx_mib_type'
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set network.@switch[-1].ar8xxx_mib_poll_interval='$ar8xxx_mib_poll_interval'
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EOF
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generate_switch_vlans_ports "$1"
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@ -227,7 +241,7 @@ generate_static_system() {
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uci -q batch <<-EOF
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delete system.@system[0]
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add system system
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set system.@system[-1].hostname='OpenMPTCProuter'
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set system.@system[-1].hostname='OpenWrt'
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set system.@system[-1].timezone='UTC'
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set system.@system[-1].ttylogin='0'
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set system.@system[-1].log_size='64'
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@ -237,10 +251,10 @@ generate_static_system() {
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set system.ntp='timeserver'
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set system.ntp.enabled='1'
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set system.ntp.enable_server='0'
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add_list system.ntp.server='0.openwrt.pool.ntp.org'
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add_list system.ntp.server='1.openwrt.pool.ntp.org'
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add_list system.ntp.server='2.openwrt.pool.ntp.org'
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add_list system.ntp.server='3.openwrt.pool.ntp.org'
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add_list system.ntp.server='ntp1.aliyun.com'
|
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add_list system.ntp.server='time1.cloud.tencent.com'
|
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add_list system.ntp.server='time.ustc.edu.cn'
|
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add_list system.ntp.server='cn.pool.ntp.org'
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EOF
|
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|
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if json_is_a system object; then
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|
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@ -359,11 +373,12 @@ generate_led() {
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;;
|
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|
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switch)
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local port_mask speed_mask
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json_get_vars port_mask speed_mask
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local port_mask speed_mask mode
|
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json_get_vars port_mask speed_mask mode
|
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uci -q batch <<-EOF
|
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set system.$cfg.port_mask='$port_mask'
|
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set system.$cfg.speed_mask='$speed_mask'
|
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set system.$cfg.mode='$mode'
|
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EOF
|
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;;
|
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|
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|
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@ -411,6 +426,8 @@ generate_gpioswitch() {
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json_init
|
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json_load "$(cat ${CFG})"
|
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|
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umask 077
|
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|
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if [ ! -s /etc/config/network ]; then
|
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touch /etc/config/network
|
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generate_static_network
|
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|
|
|
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|
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@ -10,6 +10,7 @@ board_config_update
|
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json_is_a network object && exit 0
|
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|
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ucidef_set_interface_lan 'eth0'
|
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[ -d /sys/class/net/eth1 ] && ucidef_set_interface_wan 'eth1'
|
||||
|
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board_config_flush
|
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|
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|
|
|
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|
|
@ -0,0 +1,9 @@
|
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#
|
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## Makefile for the Qualcomm Atheros ethernet edma driver
|
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#
|
||||
|
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|
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obj-$(CONFIG_ESSEDMA) += essedma.o
|
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|
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essedma-objs := edma_axi.o edma.o edma_ethtool.o
|
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|
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File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,455 @@
|
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/*
|
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* Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all copies.
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
|
||||
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _EDMA_H_
|
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#define _EDMA_H_
|
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|
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#include <linux/init.h>
|
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#include <linux/interrupt.h>
|
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#include <linux/types.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/etherdevice.h>
|
||||
#include <linux/skbuff.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/vmalloc.h>
|
||||
#include <linux/pagemap.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/sysctl.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/of_net.h>
|
||||
#include <net/checksum.h>
|
||||
#include <net/ip6_checksum.h>
|
||||
#include <asm-generic/bug.h>
|
||||
#include "ess_edma.h"
|
||||
|
||||
#define EDMA_CPU_CORES_SUPPORTED 4
|
||||
#define EDMA_MAX_PORTID_SUPPORTED 5
|
||||
#define EDMA_MAX_VLAN_SUPPORTED EDMA_MAX_PORTID_SUPPORTED
|
||||
#define EDMA_MAX_PORTID_BITMAP_INDEX (EDMA_MAX_PORTID_SUPPORTED + 1)
|
||||
#define EDMA_MAX_PORTID_BITMAP_SUPPORTED 0x1f /* 0001_1111 = 0x1f */
|
||||
#define EDMA_MAX_NETDEV_PER_QUEUE 4 /* 3 Netdev per queue, 1 space for indexing */
|
||||
|
||||
#define EDMA_MAX_RECEIVE_QUEUE 8
|
||||
#define EDMA_MAX_TRANSMIT_QUEUE 16
|
||||
|
||||
/* WAN/LAN adapter number */
|
||||
#define EDMA_WAN 0
|
||||
#define EDMA_LAN 1
|
||||
|
||||
/* VLAN tag */
|
||||
#define EDMA_LAN_DEFAULT_VLAN 1
|
||||
#define EDMA_WAN_DEFAULT_VLAN 2
|
||||
|
||||
#define EDMA_DEFAULT_GROUP1_VLAN 1
|
||||
#define EDMA_DEFAULT_GROUP2_VLAN 2
|
||||
#define EDMA_DEFAULT_GROUP3_VLAN 3
|
||||
#define EDMA_DEFAULT_GROUP4_VLAN 4
|
||||
#define EDMA_DEFAULT_GROUP5_VLAN 5
|
||||
|
||||
/* Queues exposed to linux kernel */
|
||||
#define EDMA_NETDEV_TX_QUEUE 4
|
||||
#define EDMA_NETDEV_RX_QUEUE 4
|
||||
|
||||
/* Number of queues per core */
|
||||
#define EDMA_NUM_TXQ_PER_CORE 4
|
||||
#define EDMA_NUM_RXQ_PER_CORE 2
|
||||
|
||||
#define EDMA_TPD_EOP_SHIFT 31
|
||||
|
||||
#define EDMA_PORT_ID_SHIFT 12
|
||||
#define EDMA_PORT_ID_MASK 0x7
|
||||
|
||||
/* tpd word 3 bit 18-28 */
|
||||
#define EDMA_TPD_PORT_BITMAP_SHIFT 18
|
||||
|
||||
#define EDMA_TPD_FROM_CPU_SHIFT 25
|
||||
|
||||
#define EDMA_FROM_CPU_MASK 0x80
|
||||
#define EDMA_SKB_PRIORITY_MASK 0x38
|
||||
|
||||
/* TX/RX descriptor ring count */
|
||||
/* should be a power of 2 */
|
||||
#define EDMA_RX_RING_SIZE 128
|
||||
#define EDMA_TX_RING_SIZE 128
|
||||
|
||||
/* Flags used in paged/non paged mode */
|
||||
#define EDMA_RX_HEAD_BUFF_SIZE_JUMBO 256
|
||||
#define EDMA_RX_HEAD_BUFF_SIZE 1540
|
||||
|
||||
/* MAX frame size supported by switch */
|
||||
#define EDMA_MAX_JUMBO_FRAME_SIZE 9216
|
||||
|
||||
/* Configurations */
|
||||
#define EDMA_INTR_CLEAR_TYPE 0
|
||||
#define EDMA_INTR_SW_IDX_W_TYPE 0
|
||||
#define EDMA_FIFO_THRESH_TYPE 0
|
||||
#define EDMA_RSS_TYPE 0
|
||||
#define EDMA_RX_IMT 0x0020
|
||||
#define EDMA_TX_IMT 0x0050
|
||||
#define EDMA_TPD_BURST 5
|
||||
#define EDMA_TXF_BURST 0x100
|
||||
#define EDMA_RFD_BURST 8
|
||||
#define EDMA_RFD_THR 16
|
||||
#define EDMA_RFD_LTHR 0
|
||||
|
||||
/* RX/TX per CPU based mask/shift */
|
||||
#define EDMA_TX_PER_CPU_MASK 0xF
|
||||
#define EDMA_RX_PER_CPU_MASK 0x3
|
||||
#define EDMA_TX_PER_CPU_MASK_SHIFT 0x2
|
||||
#define EDMA_RX_PER_CPU_MASK_SHIFT 0x1
|
||||
#define EDMA_TX_CPU_START_SHIFT 0x2
|
||||
#define EDMA_RX_CPU_START_SHIFT 0x1
|
||||
|
||||
/* FLags used in transmit direction */
|
||||
#define EDMA_HW_CHECKSUM 0x00000001
|
||||
#define EDMA_VLAN_TX_TAG_INSERT_FLAG 0x00000002
|
||||
#define EDMA_VLAN_TX_TAG_INSERT_DEFAULT_FLAG 0x00000004
|
||||
|
||||
#define EDMA_SW_DESC_FLAG_LAST 0x1
|
||||
#define EDMA_SW_DESC_FLAG_SKB_HEAD 0x2
|
||||
#define EDMA_SW_DESC_FLAG_SKB_FRAG 0x4
|
||||
#define EDMA_SW_DESC_FLAG_SKB_FRAGLIST 0x8
|
||||
#define EDMA_SW_DESC_FLAG_SKB_NONE 0x10
|
||||
#define EDMA_SW_DESC_FLAG_SKB_REUSE 0x20
|
||||
|
||||
|
||||
#define EDMA_MAX_SKB_FRAGS (MAX_SKB_FRAGS + 1)
|
||||
|
||||
/* Ethtool specific list of EDMA supported features */
|
||||
#define EDMA_SUPPORTED_FEATURES (SUPPORTED_10baseT_Half \
|
||||
| SUPPORTED_10baseT_Full \
|
||||
| SUPPORTED_100baseT_Half \
|
||||
| SUPPORTED_100baseT_Full \
|
||||
| SUPPORTED_1000baseT_Full)
|
||||
|
||||
/* Recevie side atheros Header */
|
||||
#define EDMA_RX_ATH_HDR_VERSION 0x2
|
||||
#define EDMA_RX_ATH_HDR_VERSION_SHIFT 14
|
||||
#define EDMA_RX_ATH_HDR_PRIORITY_SHIFT 11
|
||||
#define EDMA_RX_ATH_PORT_TYPE_SHIFT 6
|
||||
#define EDMA_RX_ATH_HDR_RSTP_PORT_TYPE 0x4
|
||||
|
||||
/* Transmit side atheros Header */
|
||||
#define EDMA_TX_ATH_HDR_PORT_BITMAP_MASK 0x7F
|
||||
#define EDMA_TX_ATH_HDR_FROM_CPU_MASK 0x80
|
||||
#define EDMA_TX_ATH_HDR_FROM_CPU_SHIFT 7
|
||||
|
||||
#define EDMA_TXQ_START_CORE0 8
|
||||
#define EDMA_TXQ_START_CORE1 12
|
||||
#define EDMA_TXQ_START_CORE2 0
|
||||
#define EDMA_TXQ_START_CORE3 4
|
||||
|
||||
#define EDMA_TXQ_IRQ_MASK_CORE0 0x0F00
|
||||
#define EDMA_TXQ_IRQ_MASK_CORE1 0xF000
|
||||
#define EDMA_TXQ_IRQ_MASK_CORE2 0x000F
|
||||
#define EDMA_TXQ_IRQ_MASK_CORE3 0x00F0
|
||||
|
||||
#define EDMA_ETH_HDR_LEN 12
|
||||
#define EDMA_ETH_TYPE_MASK 0xFFFF
|
||||
|
||||
#define EDMA_RX_BUFFER_WRITE 16
|
||||
#define EDMA_RFD_AVAIL_THR 80
|
||||
|
||||
#define EDMA_GMAC_NO_MDIO_PHY PHY_MAX_ADDR
|
||||
|
||||
extern int ssdk_rfs_ipct_rule_set(__be32 ip_src, __be32 ip_dst,
|
||||
__be16 sport, __be16 dport,
|
||||
uint8_t proto, u16 loadbalance, bool action);
|
||||
struct edma_ethtool_statistics {
|
||||
u32 tx_q0_pkt;
|
||||
u32 tx_q1_pkt;
|
||||
u32 tx_q2_pkt;
|
||||
u32 tx_q3_pkt;
|
||||
u32 tx_q4_pkt;
|
||||
u32 tx_q5_pkt;
|
||||
u32 tx_q6_pkt;
|
||||
u32 tx_q7_pkt;
|
||||
u32 tx_q8_pkt;
|
||||
u32 tx_q9_pkt;
|
||||
u32 tx_q10_pkt;
|
||||
u32 tx_q11_pkt;
|
||||
u32 tx_q12_pkt;
|
||||
u32 tx_q13_pkt;
|
||||
u32 tx_q14_pkt;
|
||||
u32 tx_q15_pkt;
|
||||
u32 tx_q0_byte;
|
||||
u32 tx_q1_byte;
|
||||
u32 tx_q2_byte;
|
||||
u32 tx_q3_byte;
|
||||
u32 tx_q4_byte;
|
||||
u32 tx_q5_byte;
|
||||
u32 tx_q6_byte;
|
||||
u32 tx_q7_byte;
|
||||
u32 tx_q8_byte;
|
||||
u32 tx_q9_byte;
|
||||
u32 tx_q10_byte;
|
||||
u32 tx_q11_byte;
|
||||
u32 tx_q12_byte;
|
||||
u32 tx_q13_byte;
|
||||
u32 tx_q14_byte;
|
||||
u32 tx_q15_byte;
|
||||
u32 rx_q0_pkt;
|
||||
u32 rx_q1_pkt;
|
||||
u32 rx_q2_pkt;
|
||||
u32 rx_q3_pkt;
|
||||
u32 rx_q4_pkt;
|
||||
u32 rx_q5_pkt;
|
||||
u32 rx_q6_pkt;
|
||||
u32 rx_q7_pkt;
|
||||
u32 rx_q0_byte;
|
||||
u32 rx_q1_byte;
|
||||
u32 rx_q2_byte;
|
||||
u32 rx_q3_byte;
|
||||
u32 rx_q4_byte;
|
||||
u32 rx_q5_byte;
|
||||
u32 rx_q6_byte;
|
||||
u32 rx_q7_byte;
|
||||
u32 tx_desc_error;
|
||||
u32 rx_alloc_fail_ctr;
|
||||
};
|
||||
|
||||
struct edma_mdio_data {
|
||||
struct mii_bus *mii_bus;
|
||||
void __iomem *membase;
|
||||
int phy_irq[PHY_MAX_ADDR];
|
||||
};
|
||||
|
||||
/* EDMA LINK state */
|
||||
enum edma_link_state {
|
||||
__EDMA_LINKUP, /* Indicate link is UP */
|
||||
__EDMA_LINKDOWN /* Indicate link is down */
|
||||
};
|
||||
|
||||
/* EDMA GMAC state */
|
||||
enum edma_gmac_state {
|
||||
__EDMA_UP /* use to indicate GMAC is up */
|
||||
};
|
||||
|
||||
/* edma transmit descriptor */
|
||||
struct edma_tx_desc {
|
||||
__le16 len; /* full packet including CRC */
|
||||
__le16 svlan_tag; /* vlan tag */
|
||||
__le32 word1; /* byte 4-7 */
|
||||
__le32 addr; /* address of buffer */
|
||||
__le32 word3; /* byte 12 */
|
||||
};
|
||||
|
||||
/* edma receive return descriptor */
|
||||
struct edma_rx_return_desc {
|
||||
u16 rrd0;
|
||||
u16 rrd1;
|
||||
u16 rrd2;
|
||||
u16 rrd3;
|
||||
u16 rrd4;
|
||||
u16 rrd5;
|
||||
u16 rrd6;
|
||||
u16 rrd7;
|
||||
};
|
||||
|
||||
/* RFD descriptor */
|
||||
struct edma_rx_free_desc {
|
||||
__le32 buffer_addr; /* buffer address */
|
||||
};
|
||||
|
||||
/* edma hw specific data */
|
||||
struct edma_hw {
|
||||
u32 __iomem *hw_addr; /* inner register address */
|
||||
struct edma_adapter *adapter; /* netdevice adapter */
|
||||
u32 rx_intr_mask; /*rx interrupt mask */
|
||||
u32 tx_intr_mask; /* tx interrupt nask */
|
||||
u32 misc_intr_mask; /* misc interrupt mask */
|
||||
u32 wol_intr_mask; /* wake on lan interrupt mask */
|
||||
bool intr_clear_type; /* interrupt clear */
|
||||
bool intr_sw_idx_w; /* interrupt software index */
|
||||
u32 rx_head_buff_size; /* Rx buffer size */
|
||||
u8 rss_type; /* rss protocol type */
|
||||
};
|
||||
|
||||
/* edma_sw_desc stores software descriptor
|
||||
* SW descriptor has 1:1 map with HW descriptor
|
||||
*/
|
||||
struct edma_sw_desc {
|
||||
struct sk_buff *skb;
|
||||
dma_addr_t dma; /* dma address */
|
||||
u16 length; /* Tx/Rx buffer length */
|
||||
u32 flags;
|
||||
};
|
||||
|
||||
/* per core related information */
|
||||
struct edma_per_cpu_queues_info {
|
||||
struct napi_struct napi; /* napi associated with the core */
|
||||
u32 tx_mask; /* tx interrupt mask */
|
||||
u32 rx_mask; /* rx interrupt mask */
|
||||
u32 tx_status; /* tx interrupt status */
|
||||
u32 rx_status; /* rx interrupt status */
|
||||
u32 tx_start; /* tx queue start */
|
||||
u32 rx_start; /* rx queue start */
|
||||
struct edma_common_info *edma_cinfo; /* edma common info */
|
||||
};
|
||||
|
||||
/* edma specific common info */
|
||||
struct edma_common_info {
|
||||
struct edma_tx_desc_ring *tpd_ring[16]; /* 16 Tx queues */
|
||||
struct edma_rfd_desc_ring *rfd_ring[8]; /* 8 Rx queues */
|
||||
struct platform_device *pdev; /* device structure */
|
||||
struct net_device *netdev[EDMA_MAX_PORTID_SUPPORTED];
|
||||
struct net_device *portid_netdev_lookup_tbl[EDMA_MAX_PORTID_BITMAP_INDEX];
|
||||
struct ctl_table_header *edma_ctl_table_hdr;
|
||||
int num_gmac;
|
||||
struct edma_ethtool_statistics edma_ethstats; /* ethtool stats */
|
||||
int num_rx_queues; /* number of rx queue */
|
||||
u32 num_tx_queues; /* number of tx queue */
|
||||
u32 tx_irq[16]; /* number of tx irq */
|
||||
u32 rx_irq[8]; /* number of rx irq */
|
||||
u32 from_cpu; /* from CPU TPD field */
|
||||
u32 num_rxq_per_core; /* Rx queues per core */
|
||||
u32 num_txq_per_core; /* Tx queues per core */
|
||||
u16 tx_ring_count; /* Tx ring count */
|
||||
u16 rx_ring_count; /* Rx ring*/
|
||||
u16 rx_head_buffer_len; /* rx buffer length */
|
||||
u16 rx_page_buffer_len; /* rx buffer length */
|
||||
u32 page_mode; /* Jumbo frame supported flag */
|
||||
u32 fraglist_mode; /* fraglist supported flag */
|
||||
struct edma_hw hw; /* edma hw specific structure */
|
||||
struct edma_per_cpu_queues_info edma_percpu_info[CONFIG_NR_CPUS]; /* per cpu information */
|
||||
spinlock_t stats_lock; /* protect edma stats area for updation */
|
||||
struct timer_list edma_stats_timer;
|
||||
bool is_single_phy;
|
||||
void __iomem *ess_hw_addr;
|
||||
struct clk *ess_clk;
|
||||
};
|
||||
|
||||
/* transimit packet descriptor (tpd) ring */
|
||||
struct edma_tx_desc_ring {
|
||||
struct netdev_queue *nq[EDMA_MAX_NETDEV_PER_QUEUE]; /* Linux queue index */
|
||||
struct net_device *netdev[EDMA_MAX_NETDEV_PER_QUEUE];
|
||||
/* Array of netdevs associated with the tpd ring */
|
||||
void *hw_desc; /* descriptor ring virtual address */
|
||||
struct edma_sw_desc *sw_desc; /* buffer associated with ring */
|
||||
int netdev_bmp; /* Bitmap for per-ring netdevs */
|
||||
u32 size; /* descriptor ring length in bytes */
|
||||
u16 count; /* number of descriptors in the ring */
|
||||
dma_addr_t dma; /* descriptor ring physical address */
|
||||
u16 sw_next_to_fill; /* next Tx descriptor to fill */
|
||||
u16 sw_next_to_clean; /* next Tx descriptor to clean */
|
||||
};
|
||||
|
||||
/* receive free descriptor (rfd) ring */
|
||||
struct edma_rfd_desc_ring {
|
||||
void *hw_desc; /* descriptor ring virtual address */
|
||||
struct edma_sw_desc *sw_desc; /* buffer associated with ring */
|
||||
u16 size; /* bytes allocated to sw_desc */
|
||||
u16 count; /* number of descriptors in the ring */
|
||||
dma_addr_t dma; /* descriptor ring physical address */
|
||||
u16 sw_next_to_fill; /* next descriptor to fill */
|
||||
u16 sw_next_to_clean; /* next descriptor to clean */
|
||||
u16 pending_fill; /* fill pending from previous iteration */
|
||||
};
|
||||
|
||||
/* edma_rfs_flter_node - rfs filter node in hash table */
|
||||
struct edma_rfs_filter_node {
|
||||
struct flow_keys keys;
|
||||
u32 flow_id; /* flow_id of filter provided by kernel */
|
||||
u16 filter_id; /* filter id of filter returned by adaptor */
|
||||
u16 rq_id; /* desired rq index */
|
||||
struct hlist_node node; /* edma rfs list node */
|
||||
};
|
||||
|
||||
/* edma_rfs_flow_tbl - rfs flow table */
|
||||
struct edma_rfs_flow_table {
|
||||
u16 max_num_filter; /* Maximum number of filters edma supports */
|
||||
u16 hashtoclean; /* hash table index to clean next */
|
||||
int filter_available; /* Number of free filters available */
|
||||
struct hlist_head hlist_head[EDMA_RFS_FLOW_ENTRIES];
|
||||
spinlock_t rfs_ftab_lock;
|
||||
struct timer_list expire_rfs; /* timer function for edma_rps_may_expire_flow */
|
||||
};
|
||||
|
||||
/* EDMA net device structure */
|
||||
struct edma_adapter {
|
||||
struct net_device *netdev; /* netdevice */
|
||||
struct platform_device *pdev; /* platform device */
|
||||
struct edma_common_info *edma_cinfo; /* edma common info */
|
||||
struct phy_device *phydev; /* Phy device */
|
||||
struct edma_rfs_flow_table rfs; /* edma rfs flow table */
|
||||
struct net_device_stats stats; /* netdev statistics */
|
||||
set_rfs_filter_callback_t set_rfs_rule;
|
||||
u32 flags;/* status flags */
|
||||
unsigned long state_flags; /* GMAC up/down flags */
|
||||
u32 forced_speed; /* link force speed */
|
||||
u32 forced_duplex; /* link force duplex */
|
||||
u32 link_state; /* phy link state */
|
||||
u32 phy_mdio_addr; /* PHY device address on MII interface */
|
||||
u32 poll_required; /* check if link polling is required */
|
||||
u32 tx_start_offset[CONFIG_NR_CPUS]; /* tx queue start */
|
||||
u32 default_vlan_tag; /* vlan tag */
|
||||
u32 dp_bitmap;
|
||||
uint8_t phy_id[MII_BUS_ID_SIZE + 3];
|
||||
};
|
||||
|
||||
int edma_alloc_queues_tx(struct edma_common_info *edma_cinfo);
|
||||
int edma_alloc_queues_rx(struct edma_common_info *edma_cinfo);
|
||||
int edma_open(struct net_device *netdev);
|
||||
int edma_close(struct net_device *netdev);
|
||||
void edma_free_tx_resources(struct edma_common_info *edma_c_info);
|
||||
void edma_free_rx_resources(struct edma_common_info *edma_c_info);
|
||||
int edma_alloc_tx_rings(struct edma_common_info *edma_cinfo);
|
||||
int edma_alloc_rx_rings(struct edma_common_info *edma_cinfo);
|
||||
void edma_free_tx_rings(struct edma_common_info *edma_cinfo);
|
||||
void edma_free_rx_rings(struct edma_common_info *edma_cinfo);
|
||||
void edma_free_queues(struct edma_common_info *edma_cinfo);
|
||||
void edma_irq_disable(struct edma_common_info *edma_cinfo);
|
||||
int edma_reset(struct edma_common_info *edma_cinfo);
|
||||
int edma_poll(struct napi_struct *napi, int budget);
|
||||
netdev_tx_t edma_xmit(struct sk_buff *skb,
|
||||
struct net_device *netdev);
|
||||
int edma_configure(struct edma_common_info *edma_cinfo);
|
||||
void edma_irq_enable(struct edma_common_info *edma_cinfo);
|
||||
void edma_enable_tx_ctrl(struct edma_hw *hw);
|
||||
void edma_enable_rx_ctrl(struct edma_hw *hw);
|
||||
void edma_stop_rx_tx(struct edma_hw *hw);
|
||||
void edma_free_irqs(struct edma_adapter *adapter);
|
||||
irqreturn_t edma_interrupt(int irq, void *dev);
|
||||
void edma_write_reg(u16 reg_addr, u32 reg_value);
|
||||
void edma_read_reg(u16 reg_addr, volatile u32 *reg_value);
|
||||
struct net_device_stats *edma_get_stats(struct net_device *netdev);
|
||||
int edma_set_mac_addr(struct net_device *netdev, void *p);
|
||||
int edma_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
|
||||
u16 rxq, u32 flow_id);
|
||||
int edma_register_rfs_filter(struct net_device *netdev,
|
||||
set_rfs_filter_callback_t set_filter);
|
||||
void edma_flow_may_expire(struct timer_list *t);
|
||||
void edma_set_ethtool_ops(struct net_device *netdev);
|
||||
void edma_set_stp_rstp(bool tag);
|
||||
void edma_assign_ath_hdr_type(int tag);
|
||||
int edma_get_default_vlan_tag(struct net_device *netdev);
|
||||
void edma_adjust_link(struct net_device *netdev);
|
||||
int edma_fill_netdev(struct edma_common_info *edma_cinfo, int qid, int num, int txq_id);
|
||||
void edma_read_append_stats(struct edma_common_info *edma_cinfo);
|
||||
void edma_change_tx_coalesce(int usecs);
|
||||
void edma_change_rx_coalesce(int usecs);
|
||||
void edma_get_tx_rx_coalesce(u32 *reg_val);
|
||||
void edma_clear_irq_status(void);
|
||||
void ess_set_port_status_speed(struct edma_common_info *edma_cinfo,
|
||||
struct phy_device *phydev, uint8_t port_id);
|
||||
#endif /* _EDMA_H_ */
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,384 @@
|
|||
/*
|
||||
* Copyright (c) 2015 - 2016, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all copies.
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
|
||||
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <linux/ethtool.h>
|
||||
#include <linux/netdevice.h>
|
||||
#include <linux/string.h>
|
||||
#include "edma.h"
|
||||
|
||||
struct edma_ethtool_stats {
|
||||
uint8_t stat_string[ETH_GSTRING_LEN];
|
||||
uint32_t stat_offset;
|
||||
};
|
||||
|
||||
#define EDMA_STAT(m) offsetof(struct edma_ethtool_statistics, m)
|
||||
#define DRVINFO_LEN 32
|
||||
|
||||
/* Array of strings describing statistics
|
||||
*/
|
||||
static const struct edma_ethtool_stats edma_gstrings_stats[] = {
|
||||
{"tx_q0_pkt", EDMA_STAT(tx_q0_pkt)},
|
||||
{"tx_q1_pkt", EDMA_STAT(tx_q1_pkt)},
|
||||
{"tx_q2_pkt", EDMA_STAT(tx_q2_pkt)},
|
||||
{"tx_q3_pkt", EDMA_STAT(tx_q3_pkt)},
|
||||
{"tx_q4_pkt", EDMA_STAT(tx_q4_pkt)},
|
||||
{"tx_q5_pkt", EDMA_STAT(tx_q5_pkt)},
|
||||
{"tx_q6_pkt", EDMA_STAT(tx_q6_pkt)},
|
||||
{"tx_q7_pkt", EDMA_STAT(tx_q7_pkt)},
|
||||
{"tx_q8_pkt", EDMA_STAT(tx_q8_pkt)},
|
||||
{"tx_q9_pkt", EDMA_STAT(tx_q9_pkt)},
|
||||
{"tx_q10_pkt", EDMA_STAT(tx_q10_pkt)},
|
||||
{"tx_q11_pkt", EDMA_STAT(tx_q11_pkt)},
|
||||
{"tx_q12_pkt", EDMA_STAT(tx_q12_pkt)},
|
||||
{"tx_q13_pkt", EDMA_STAT(tx_q13_pkt)},
|
||||
{"tx_q14_pkt", EDMA_STAT(tx_q14_pkt)},
|
||||
{"tx_q15_pkt", EDMA_STAT(tx_q15_pkt)},
|
||||
{"tx_q0_byte", EDMA_STAT(tx_q0_byte)},
|
||||
{"tx_q1_byte", EDMA_STAT(tx_q1_byte)},
|
||||
{"tx_q2_byte", EDMA_STAT(tx_q2_byte)},
|
||||
{"tx_q3_byte", EDMA_STAT(tx_q3_byte)},
|
||||
{"tx_q4_byte", EDMA_STAT(tx_q4_byte)},
|
||||
{"tx_q5_byte", EDMA_STAT(tx_q5_byte)},
|
||||
{"tx_q6_byte", EDMA_STAT(tx_q6_byte)},
|
||||
{"tx_q7_byte", EDMA_STAT(tx_q7_byte)},
|
||||
{"tx_q8_byte", EDMA_STAT(tx_q8_byte)},
|
||||
{"tx_q9_byte", EDMA_STAT(tx_q9_byte)},
|
||||
{"tx_q10_byte", EDMA_STAT(tx_q10_byte)},
|
||||
{"tx_q11_byte", EDMA_STAT(tx_q11_byte)},
|
||||
{"tx_q12_byte", EDMA_STAT(tx_q12_byte)},
|
||||
{"tx_q13_byte", EDMA_STAT(tx_q13_byte)},
|
||||
{"tx_q14_byte", EDMA_STAT(tx_q14_byte)},
|
||||
{"tx_q15_byte", EDMA_STAT(tx_q15_byte)},
|
||||
{"rx_q0_pkt", EDMA_STAT(rx_q0_pkt)},
|
||||
{"rx_q1_pkt", EDMA_STAT(rx_q1_pkt)},
|
||||
{"rx_q2_pkt", EDMA_STAT(rx_q2_pkt)},
|
||||
{"rx_q3_pkt", EDMA_STAT(rx_q3_pkt)},
|
||||
{"rx_q4_pkt", EDMA_STAT(rx_q4_pkt)},
|
||||
{"rx_q5_pkt", EDMA_STAT(rx_q5_pkt)},
|
||||
{"rx_q6_pkt", EDMA_STAT(rx_q6_pkt)},
|
||||
{"rx_q7_pkt", EDMA_STAT(rx_q7_pkt)},
|
||||
{"rx_q0_byte", EDMA_STAT(rx_q0_byte)},
|
||||
{"rx_q1_byte", EDMA_STAT(rx_q1_byte)},
|
||||
{"rx_q2_byte", EDMA_STAT(rx_q2_byte)},
|
||||
{"rx_q3_byte", EDMA_STAT(rx_q3_byte)},
|
||||
{"rx_q4_byte", EDMA_STAT(rx_q4_byte)},
|
||||
{"rx_q5_byte", EDMA_STAT(rx_q5_byte)},
|
||||
{"rx_q6_byte", EDMA_STAT(rx_q6_byte)},
|
||||
{"rx_q7_byte", EDMA_STAT(rx_q7_byte)},
|
||||
{"tx_desc_error", EDMA_STAT(tx_desc_error)},
|
||||
{"rx_alloc_fail_ctr", EDMA_STAT(rx_alloc_fail_ctr)},
|
||||
};
|
||||
|
||||
#define EDMA_STATS_LEN ARRAY_SIZE(edma_gstrings_stats)
|
||||
|
||||
/* edma_get_strset_count()
|
||||
* Get strset count
|
||||
*/
|
||||
static int edma_get_strset_count(struct net_device *netdev,
|
||||
int sset)
|
||||
{
|
||||
switch (sset) {
|
||||
case ETH_SS_STATS:
|
||||
return EDMA_STATS_LEN;
|
||||
default:
|
||||
netdev_dbg(netdev, "%s: Invalid string set", __func__);
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* edma_get_strings()
|
||||
* get stats string
|
||||
*/
|
||||
static void edma_get_strings(struct net_device *netdev, uint32_t stringset,
|
||||
uint8_t *data)
|
||||
{
|
||||
uint8_t *p = data;
|
||||
uint32_t i;
|
||||
|
||||
switch (stringset) {
|
||||
case ETH_SS_STATS:
|
||||
for (i = 0; i < EDMA_STATS_LEN; i++) {
|
||||
memcpy(p, edma_gstrings_stats[i].stat_string,
|
||||
min((size_t)ETH_GSTRING_LEN,
|
||||
strlen(edma_gstrings_stats[i].stat_string)
|
||||
+ 1));
|
||||
p += ETH_GSTRING_LEN;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* edma_get_ethtool_stats()
|
||||
* Get ethtool statistics
|
||||
*/
|
||||
static void edma_get_ethtool_stats(struct net_device *netdev,
|
||||
struct ethtool_stats *stats, uint64_t *data)
|
||||
{
|
||||
struct edma_adapter *adapter = netdev_priv(netdev);
|
||||
struct edma_common_info *edma_cinfo = adapter->edma_cinfo;
|
||||
int i;
|
||||
uint8_t *p = NULL;
|
||||
|
||||
edma_read_append_stats(edma_cinfo);
|
||||
|
||||
for(i = 0; i < EDMA_STATS_LEN; i++) {
|
||||
p = (uint8_t *)&(edma_cinfo->edma_ethstats) +
|
||||
edma_gstrings_stats[i].stat_offset;
|
||||
data[i] = *(uint32_t *)p;
|
||||
}
|
||||
}
|
||||
|
||||
/* edma_get_drvinfo()
|
||||
* get edma driver info
|
||||
*/
|
||||
static void edma_get_drvinfo(struct net_device *dev,
|
||||
struct ethtool_drvinfo *info)
|
||||
{
|
||||
strlcpy(info->driver, "ess_edma", DRVINFO_LEN);
|
||||
strlcpy(info->bus_info, "axi", ETHTOOL_BUSINFO_LEN);
|
||||
}
|
||||
|
||||
/* edma_nway_reset()
|
||||
* Reset the phy, if available.
|
||||
*/
|
||||
static int edma_nway_reset(struct net_device *netdev)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* edma_get_wol()
|
||||
* get wake on lan info
|
||||
*/
|
||||
static void edma_get_wol(struct net_device *netdev,
|
||||
struct ethtool_wolinfo *wol)
|
||||
{
|
||||
wol->supported = 0;
|
||||
wol->wolopts = 0;
|
||||
}
|
||||
|
||||
/* edma_get_msglevel()
|
||||
* get message level.
|
||||
*/
|
||||
static uint32_t edma_get_msglevel(struct net_device *netdev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* edma_get_settings()
|
||||
* Get edma settings
|
||||
*/
|
||||
static int edma_get_settings(struct net_device *netdev,
|
||||
struct ethtool_link_ksettings *cmd)
|
||||
{
|
||||
struct edma_adapter *adapter = netdev_priv(netdev);
|
||||
|
||||
if (adapter->poll_required) {
|
||||
struct phy_device *phydev = NULL;
|
||||
uint16_t phyreg;
|
||||
|
||||
if ((adapter->forced_speed != SPEED_UNKNOWN)
|
||||
&& !(adapter->poll_required))
|
||||
return -EPERM;
|
||||
|
||||
phydev = adapter->phydev;
|
||||
|
||||
linkmode_copy(cmd->link_modes.advertising, phydev->advertising);
|
||||
linkmode_copy(cmd->link_modes.supported, phydev->supported);
|
||||
|
||||
cmd->base.autoneg = phydev->autoneg;
|
||||
|
||||
if (adapter->link_state == __EDMA_LINKDOWN) {
|
||||
cmd->base.speed = SPEED_UNKNOWN;
|
||||
cmd->base.duplex = DUPLEX_UNKNOWN;
|
||||
} else {
|
||||
cmd->base.speed = phydev->speed;
|
||||
cmd->base.duplex = phydev->duplex;
|
||||
}
|
||||
|
||||
cmd->base.phy_address = adapter->phy_mdio_addr;
|
||||
|
||||
phyreg = (uint16_t)phy_read(adapter->phydev, MII_LPA);
|
||||
if (phyreg & LPA_10HALF)
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
|
||||
cmd->link_modes.lp_advertising);
|
||||
|
||||
if (phyreg & LPA_10FULL)
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
|
||||
cmd->link_modes.lp_advertising);
|
||||
|
||||
if (phyreg & LPA_100HALF)
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
|
||||
cmd->link_modes.lp_advertising);
|
||||
|
||||
if (phyreg & LPA_100FULL)
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
|
||||
cmd->link_modes.lp_advertising);
|
||||
|
||||
phyreg = (uint16_t)phy_read(adapter->phydev, MII_STAT1000);
|
||||
if (phyreg & LPA_1000HALF)
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
|
||||
cmd->link_modes.lp_advertising);
|
||||
|
||||
if (phyreg & LPA_1000FULL)
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
|
||||
cmd->link_modes.lp_advertising);
|
||||
} else {
|
||||
/* If the speed/duplex for this GMAC is forced and we
|
||||
* are not polling for link state changes, return the
|
||||
* values as specified by platform. This will be true
|
||||
* for GMACs connected to switch, and interfaces that
|
||||
* do not use a PHY.
|
||||
*/
|
||||
if (!(adapter->poll_required)) {
|
||||
if (adapter->forced_speed != SPEED_UNKNOWN) {
|
||||
/* set speed and duplex */
|
||||
cmd->base.speed = SPEED_1000;
|
||||
cmd->base.duplex = DUPLEX_FULL;
|
||||
|
||||
/* Populate capabilities advertised by self */
|
||||
linkmode_zero(cmd->link_modes.advertising);
|
||||
cmd->base.autoneg = 0;
|
||||
cmd->base.port = PORT_TP;
|
||||
cmd->base.transceiver = XCVR_EXTERNAL;
|
||||
} else {
|
||||
/* non link polled and non
|
||||
* forced speed/duplex interface
|
||||
*/
|
||||
return -EIO;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* edma_set_settings()
|
||||
* Set EDMA settings
|
||||
*/
|
||||
static int edma_set_settings(struct net_device *netdev,
|
||||
const struct ethtool_link_ksettings *cmd)
|
||||
{
|
||||
struct edma_adapter *adapter = netdev_priv(netdev);
|
||||
struct phy_device *phydev = NULL;
|
||||
|
||||
if ((adapter->forced_speed != SPEED_UNKNOWN) &&
|
||||
!adapter->poll_required)
|
||||
return -EPERM;
|
||||
|
||||
phydev = adapter->phydev;
|
||||
linkmode_copy(phydev->advertising, cmd->link_modes.advertising);
|
||||
linkmode_copy(phydev->supported, cmd->link_modes.supported);
|
||||
phydev->autoneg = cmd->base.autoneg;
|
||||
phydev->speed = cmd->base.speed;
|
||||
phydev->duplex = cmd->base.duplex;
|
||||
|
||||
genphy_config_aneg(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* edma_get_coalesce
|
||||
* get interrupt mitigation
|
||||
*/
|
||||
static int edma_get_coalesce(struct net_device *netdev,
|
||||
struct ethtool_coalesce *ec)
|
||||
{
|
||||
u32 reg_val;
|
||||
|
||||
edma_get_tx_rx_coalesce(®_val);
|
||||
|
||||
/* We read the Interrupt Moderation Timer(IMT) register value,
|
||||
* use lower 16 bit for rx and higher 16 bit for Tx. We do a
|
||||
* left shift by 1, because IMT resolution timer is 2usecs.
|
||||
* Hence the value given by the register is multiplied by 2 to
|
||||
* get the actual time in usecs.
|
||||
*/
|
||||
ec->tx_coalesce_usecs = (((reg_val >> 16) & 0xffff) << 1);
|
||||
ec->rx_coalesce_usecs = ((reg_val & 0xffff) << 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* edma_set_coalesce
|
||||
* set interrupt mitigation
|
||||
*/
|
||||
static int edma_set_coalesce(struct net_device *netdev,
|
||||
struct ethtool_coalesce *ec)
|
||||
{
|
||||
if (ec->tx_coalesce_usecs)
|
||||
edma_change_tx_coalesce(ec->tx_coalesce_usecs);
|
||||
if (ec->rx_coalesce_usecs)
|
||||
edma_change_rx_coalesce(ec->rx_coalesce_usecs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* edma_set_priv_flags()
|
||||
* Set EDMA private flags
|
||||
*/
|
||||
static int edma_set_priv_flags(struct net_device *netdev, u32 flags)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* edma_get_priv_flags()
|
||||
* get edma driver flags
|
||||
*/
|
||||
static u32 edma_get_priv_flags(struct net_device *netdev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* edma_get_ringparam()
|
||||
* get ring size
|
||||
*/
|
||||
static void edma_get_ringparam(struct net_device *netdev,
|
||||
struct ethtool_ringparam *ring)
|
||||
{
|
||||
struct edma_adapter *adapter = netdev_priv(netdev);
|
||||
struct edma_common_info *edma_cinfo = adapter->edma_cinfo;
|
||||
|
||||
ring->tx_max_pending = edma_cinfo->tx_ring_count;
|
||||
ring->rx_max_pending = edma_cinfo->rx_ring_count;
|
||||
}
|
||||
|
||||
/* Ethtool operations
|
||||
*/
|
||||
static const struct ethtool_ops edma_ethtool_ops = {
|
||||
.get_drvinfo = &edma_get_drvinfo,
|
||||
.get_link = ðtool_op_get_link,
|
||||
.get_msglevel = &edma_get_msglevel,
|
||||
.nway_reset = &edma_nway_reset,
|
||||
.get_wol = &edma_get_wol,
|
||||
.get_link_ksettings = &edma_get_settings,
|
||||
.set_link_ksettings = &edma_set_settings,
|
||||
.get_strings = &edma_get_strings,
|
||||
.get_sset_count = &edma_get_strset_count,
|
||||
.get_ethtool_stats = &edma_get_ethtool_stats,
|
||||
.get_coalesce = &edma_get_coalesce,
|
||||
.set_coalesce = &edma_set_coalesce,
|
||||
.get_priv_flags = edma_get_priv_flags,
|
||||
.set_priv_flags = edma_set_priv_flags,
|
||||
.get_ringparam = edma_get_ringparam,
|
||||
};
|
||||
|
||||
/* edma_set_ethtool_ops
|
||||
* Set ethtool operations
|
||||
*/
|
||||
void edma_set_ethtool_ops(struct net_device *netdev)
|
||||
{
|
||||
netdev->ethtool_ops = &edma_ethtool_ops;
|
||||
}
|
||||
|
|
@ -0,0 +1,389 @@
|
|||
/*
|
||||
* Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for
|
||||
* any purpose with or without fee is hereby granted, provided that the
|
||||
* above copyright notice and this permission notice appear in all copies.
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
|
||||
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _ESS_EDMA_H_
|
||||
#define _ESS_EDMA_H_
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct edma_adapter;
|
||||
struct edma_hw;
|
||||
|
||||
/* register definition */
|
||||
#define EDMA_REG_MAS_CTRL 0x0
|
||||
#define EDMA_REG_TIMEOUT_CTRL 0x004
|
||||
#define EDMA_REG_DBG0 0x008
|
||||
#define EDMA_REG_DBG1 0x00C
|
||||
#define EDMA_REG_SW_CTRL0 0x100
|
||||
#define EDMA_REG_SW_CTRL1 0x104
|
||||
|
||||
/* Interrupt Status Register */
|
||||
#define EDMA_REG_RX_ISR 0x200
|
||||
#define EDMA_REG_TX_ISR 0x208
|
||||
#define EDMA_REG_MISC_ISR 0x210
|
||||
#define EDMA_REG_WOL_ISR 0x218
|
||||
|
||||
#define EDMA_MISC_ISR_RX_URG_Q(x) (1 << x)
|
||||
|
||||
#define EDMA_MISC_ISR_AXIR_TIMEOUT 0x00000100
|
||||
#define EDMA_MISC_ISR_AXIR_ERR 0x00000200
|
||||
#define EDMA_MISC_ISR_TXF_DEAD 0x00000400
|
||||
#define EDMA_MISC_ISR_AXIW_ERR 0x00000800
|
||||
#define EDMA_MISC_ISR_AXIW_TIMEOUT 0x00001000
|
||||
|
||||
#define EDMA_WOL_ISR 0x00000001
|
||||
|
||||
/* Interrupt Mask Register */
|
||||
#define EDMA_REG_MISC_IMR 0x214
|
||||
#define EDMA_REG_WOL_IMR 0x218
|
||||
|
||||
#define EDMA_RX_IMR_NORMAL_MASK 0x1
|
||||
#define EDMA_TX_IMR_NORMAL_MASK 0x1
|
||||
#define EDMA_MISC_IMR_NORMAL_MASK 0x80001FFF
|
||||
#define EDMA_WOL_IMR_NORMAL_MASK 0x1
|
||||
|
||||
/* Edma receive consumer index */
|
||||
#define EDMA_REG_RX_SW_CONS_IDX_Q(x) (0x220 + ((x) << 2)) /* x is the queue id */
|
||||
/* Edma transmit consumer index */
|
||||
#define EDMA_REG_TX_SW_CONS_IDX_Q(x) (0x240 + ((x) << 2)) /* x is the queue id */
|
||||
|
||||
/* IRQ Moderator Initial Timer Register */
|
||||
#define EDMA_REG_IRQ_MODRT_TIMER_INIT 0x280
|
||||
#define EDMA_IRQ_MODRT_TIMER_MASK 0xFFFF
|
||||
#define EDMA_IRQ_MODRT_RX_TIMER_SHIFT 0
|
||||
#define EDMA_IRQ_MODRT_TX_TIMER_SHIFT 16
|
||||
|
||||
/* Interrupt Control Register */
|
||||
#define EDMA_REG_INTR_CTRL 0x284
|
||||
#define EDMA_INTR_CLR_TYP_SHIFT 0
|
||||
#define EDMA_INTR_SW_IDX_W_TYP_SHIFT 1
|
||||
#define EDMA_INTR_CLEAR_TYPE_W1 0
|
||||
#define EDMA_INTR_CLEAR_TYPE_R 1
|
||||
|
||||
/* RX Interrupt Mask Register */
|
||||
#define EDMA_REG_RX_INT_MASK_Q(x) (0x300 + ((x) << 2)) /* x = queue id */
|
||||
|
||||
/* TX Interrupt mask register */
|
||||
#define EDMA_REG_TX_INT_MASK_Q(x) (0x340 + ((x) << 2)) /* x = queue id */
|
||||
|
||||
/* Load Ptr Register
|
||||
* Software sets this bit after the initialization of the head and tail
|
||||
*/
|
||||
#define EDMA_REG_TX_SRAM_PART 0x400
|
||||
#define EDMA_LOAD_PTR_SHIFT 16
|
||||
|
||||
/* TXQ Control Register */
|
||||
#define EDMA_REG_TXQ_CTRL 0x404
|
||||
#define EDMA_TXQ_CTRL_IP_OPTION_EN 0x10
|
||||
#define EDMA_TXQ_CTRL_TXQ_EN 0x20
|
||||
#define EDMA_TXQ_CTRL_ENH_MODE 0x40
|
||||
#define EDMA_TXQ_CTRL_LS_8023_EN 0x80
|
||||
#define EDMA_TXQ_CTRL_TPD_BURST_EN 0x100
|
||||
#define EDMA_TXQ_CTRL_LSO_BREAK_EN 0x200
|
||||
#define EDMA_TXQ_NUM_TPD_BURST_MASK 0xF
|
||||
#define EDMA_TXQ_TXF_BURST_NUM_MASK 0xFFFF
|
||||
#define EDMA_TXQ_NUM_TPD_BURST_SHIFT 0
|
||||
#define EDMA_TXQ_TXF_BURST_NUM_SHIFT 16
|
||||
|
||||
#define EDMA_REG_TXF_WATER_MARK 0x408 /* In 8-bytes */
|
||||
#define EDMA_TXF_WATER_MARK_MASK 0x0FFF
|
||||
#define EDMA_TXF_LOW_WATER_MARK_SHIFT 0
|
||||
#define EDMA_TXF_HIGH_WATER_MARK_SHIFT 16
|
||||
#define EDMA_TXQ_CTRL_BURST_MODE_EN 0x80000000
|
||||
|
||||
/* WRR Control Register */
|
||||
#define EDMA_REG_WRR_CTRL_Q0_Q3 0x40c
|
||||
#define EDMA_REG_WRR_CTRL_Q4_Q7 0x410
|
||||
#define EDMA_REG_WRR_CTRL_Q8_Q11 0x414
|
||||
#define EDMA_REG_WRR_CTRL_Q12_Q15 0x418
|
||||
|
||||
/* Weight round robin(WRR), it takes queue as input, and computes
|
||||
* starting bits where we need to write the weight for a particular
|
||||
* queue
|
||||
*/
|
||||
#define EDMA_WRR_SHIFT(x) (((x) * 5) % 20)
|
||||
|
||||
/* Tx Descriptor Control Register */
|
||||
#define EDMA_REG_TPD_RING_SIZE 0x41C
|
||||
#define EDMA_TPD_RING_SIZE_SHIFT 0
|
||||
#define EDMA_TPD_RING_SIZE_MASK 0xFFFF
|
||||
|
||||
/* Transmit descriptor base address */
|
||||
#define EDMA_REG_TPD_BASE_ADDR_Q(x) (0x420 + ((x) << 2)) /* x = queue id */
|
||||
|
||||
/* TPD Index Register */
|
||||
#define EDMA_REG_TPD_IDX_Q(x) (0x460 + ((x) << 2)) /* x = queue id */
|
||||
|
||||
#define EDMA_TPD_PROD_IDX_BITS 0x0000FFFF
|
||||
#define EDMA_TPD_CONS_IDX_BITS 0xFFFF0000
|
||||
#define EDMA_TPD_PROD_IDX_MASK 0xFFFF
|
||||
#define EDMA_TPD_CONS_IDX_MASK 0xFFFF
|
||||
#define EDMA_TPD_PROD_IDX_SHIFT 0
|
||||
#define EDMA_TPD_CONS_IDX_SHIFT 16
|
||||
|
||||
/* TX Virtual Queue Mapping Control Register */
|
||||
#define EDMA_REG_VQ_CTRL0 0x4A0
|
||||
#define EDMA_REG_VQ_CTRL1 0x4A4
|
||||
|
||||
/* Virtual QID shift, it takes queue as input, and computes
|
||||
* Virtual QID position in virtual qid control register
|
||||
*/
|
||||
#define EDMA_VQ_ID_SHIFT(i) (((i) * 3) % 24)
|
||||
|
||||
/* Virtual Queue Default Value */
|
||||
#define EDMA_VQ_REG_VALUE 0x240240
|
||||
|
||||
/* Tx side Port Interface Control Register */
|
||||
#define EDMA_REG_PORT_CTRL 0x4A8
|
||||
#define EDMA_PAD_EN_SHIFT 15
|
||||
|
||||
/* Tx side VLAN Configuration Register */
|
||||
#define EDMA_REG_VLAN_CFG 0x4AC
|
||||
|
||||
#define EDMA_TX_CVLAN 16
|
||||
#define EDMA_TX_INS_CVLAN 17
|
||||
#define EDMA_TX_CVLAN_TAG_SHIFT 0
|
||||
|
||||
#define EDMA_TX_SVLAN 14
|
||||
#define EDMA_TX_INS_SVLAN 15
|
||||
#define EDMA_TX_SVLAN_TAG_SHIFT 16
|
||||
|
||||
/* Tx Queue Packet Statistic Register */
|
||||
#define EDMA_REG_TX_STAT_PKT_Q(x) (0x700 + ((x) << 3)) /* x = queue id */
|
||||
|
||||
#define EDMA_TX_STAT_PKT_MASK 0xFFFFFF
|
||||
|
||||
/* Tx Queue Byte Statistic Register */
|
||||
#define EDMA_REG_TX_STAT_BYTE_Q(x) (0x704 + ((x) << 3)) /* x = queue id */
|
||||
|
||||
/* Load Balance Based Ring Offset Register */
|
||||
#define EDMA_REG_LB_RING 0x800
|
||||
#define EDMA_LB_RING_ENTRY_MASK 0xff
|
||||
#define EDMA_LB_RING_ID_MASK 0x7
|
||||
#define EDMA_LB_RING_PROFILE_ID_MASK 0x3
|
||||
#define EDMA_LB_RING_ENTRY_BIT_OFFSET 8
|
||||
#define EDMA_LB_RING_ID_OFFSET 0
|
||||
#define EDMA_LB_RING_PROFILE_ID_OFFSET 3
|
||||
#define EDMA_LB_REG_VALUE 0x6040200
|
||||
|
||||
/* Load Balance Priority Mapping Register */
|
||||
#define EDMA_REG_LB_PRI_START 0x804
|
||||
#define EDMA_REG_LB_PRI_END 0x810
|
||||
#define EDMA_LB_PRI_REG_INC 4
|
||||
#define EDMA_LB_PRI_ENTRY_BIT_OFFSET 4
|
||||
#define EDMA_LB_PRI_ENTRY_MASK 0xf
|
||||
|
||||
/* RSS Priority Mapping Register */
|
||||
#define EDMA_REG_RSS_PRI 0x820
|
||||
#define EDMA_RSS_PRI_ENTRY_MASK 0xf
|
||||
#define EDMA_RSS_RING_ID_MASK 0x7
|
||||
#define EDMA_RSS_PRI_ENTRY_BIT_OFFSET 4
|
||||
|
||||
/* RSS Indirection Register */
|
||||
#define EDMA_REG_RSS_IDT(x) (0x840 + ((x) << 2)) /* x = No. of indirection table */
|
||||
#define EDMA_NUM_IDT 16
|
||||
#define EDMA_RSS_IDT_VALUE 0x64206420
|
||||
|
||||
/* Default RSS Ring Register */
|
||||
#define EDMA_REG_DEF_RSS 0x890
|
||||
#define EDMA_DEF_RSS_MASK 0x7
|
||||
|
||||
/* RSS Hash Function Type Register */
|
||||
#define EDMA_REG_RSS_TYPE 0x894
|
||||
#define EDMA_RSS_TYPE_NONE 0x01
|
||||
#define EDMA_RSS_TYPE_IPV4TCP 0x02
|
||||
#define EDMA_RSS_TYPE_IPV6_TCP 0x04
|
||||
#define EDMA_RSS_TYPE_IPV4_UDP 0x08
|
||||
#define EDMA_RSS_TYPE_IPV6UDP 0x10
|
||||
#define EDMA_RSS_TYPE_IPV4 0x20
|
||||
#define EDMA_RSS_TYPE_IPV6 0x40
|
||||
#define EDMA_RSS_HASH_MODE_MASK 0x7f
|
||||
|
||||
#define EDMA_REG_RSS_HASH_VALUE 0x8C0
|
||||
|
||||
#define EDMA_REG_RSS_TYPE_RESULT 0x8C4
|
||||
|
||||
#define EDMA_HASH_TYPE_START 0
|
||||
#define EDMA_HASH_TYPE_END 5
|
||||
#define EDMA_HASH_TYPE_SHIFT 12
|
||||
|
||||
#define EDMA_RFS_FLOW_ENTRIES 1024
|
||||
#define EDMA_RFS_FLOW_ENTRIES_MASK (EDMA_RFS_FLOW_ENTRIES - 1)
|
||||
#define EDMA_RFS_EXPIRE_COUNT_PER_CALL 128
|
||||
|
||||
/* RFD Base Address Register */
|
||||
#define EDMA_REG_RFD_BASE_ADDR_Q(x) (0x950 + ((x) << 2)) /* x = queue id */
|
||||
|
||||
/* RFD Index Register */
|
||||
#define EDMA_REG_RFD_IDX_Q(x) (0x9B0 + ((x) << 2))
|
||||
|
||||
#define EDMA_RFD_PROD_IDX_BITS 0x00000FFF
|
||||
#define EDMA_RFD_CONS_IDX_BITS 0x0FFF0000
|
||||
#define EDMA_RFD_PROD_IDX_MASK 0xFFF
|
||||
#define EDMA_RFD_CONS_IDX_MASK 0xFFF
|
||||
#define EDMA_RFD_PROD_IDX_SHIFT 0
|
||||
#define EDMA_RFD_CONS_IDX_SHIFT 16
|
||||
|
||||
/* Rx Descriptor Control Register */
|
||||
#define EDMA_REG_RX_DESC0 0xA10
|
||||
#define EDMA_RFD_RING_SIZE_MASK 0xFFF
|
||||
#define EDMA_RX_BUF_SIZE_MASK 0xFFFF
|
||||
#define EDMA_RFD_RING_SIZE_SHIFT 0
|
||||
#define EDMA_RX_BUF_SIZE_SHIFT 16
|
||||
|
||||
#define EDMA_REG_RX_DESC1 0xA14
|
||||
#define EDMA_RXQ_RFD_BURST_NUM_MASK 0x3F
|
||||
#define EDMA_RXQ_RFD_PF_THRESH_MASK 0x1F
|
||||
#define EDMA_RXQ_RFD_LOW_THRESH_MASK 0xFFF
|
||||
#define EDMA_RXQ_RFD_BURST_NUM_SHIFT 0
|
||||
#define EDMA_RXQ_RFD_PF_THRESH_SHIFT 8
|
||||
#define EDMA_RXQ_RFD_LOW_THRESH_SHIFT 16
|
||||
|
||||
/* RXQ Control Register */
|
||||
#define EDMA_REG_RXQ_CTRL 0xA18
|
||||
#define EDMA_FIFO_THRESH_TYPE_SHIF 0
|
||||
#define EDMA_FIFO_THRESH_128_BYTE 0x0
|
||||
#define EDMA_FIFO_THRESH_64_BYTE 0x1
|
||||
#define EDMA_RXQ_CTRL_RMV_VLAN 0x00000002
|
||||
#define EDMA_RXQ_CTRL_EN 0x0000FF00
|
||||
|
||||
/* AXI Burst Size Config */
|
||||
#define EDMA_REG_AXIW_CTRL_MAXWRSIZE 0xA1C
|
||||
#define EDMA_AXIW_MAXWRSIZE_VALUE 0x0
|
||||
|
||||
/* Rx Statistics Register */
|
||||
#define EDMA_REG_RX_STAT_BYTE_Q(x) (0xA30 + ((x) << 2)) /* x = queue id */
|
||||
#define EDMA_REG_RX_STAT_PKT_Q(x) (0xA50 + ((x) << 2)) /* x = queue id */
|
||||
|
||||
/* WoL Pattern Length Register */
|
||||
#define EDMA_REG_WOL_PATTERN_LEN0 0xC00
|
||||
#define EDMA_WOL_PT_LEN_MASK 0xFF
|
||||
#define EDMA_WOL_PT0_LEN_SHIFT 0
|
||||
#define EDMA_WOL_PT1_LEN_SHIFT 8
|
||||
#define EDMA_WOL_PT2_LEN_SHIFT 16
|
||||
#define EDMA_WOL_PT3_LEN_SHIFT 24
|
||||
|
||||
#define EDMA_REG_WOL_PATTERN_LEN1 0xC04
|
||||
#define EDMA_WOL_PT4_LEN_SHIFT 0
|
||||
#define EDMA_WOL_PT5_LEN_SHIFT 8
|
||||
#define EDMA_WOL_PT6_LEN_SHIFT 16
|
||||
|
||||
/* WoL Control Register */
|
||||
#define EDMA_REG_WOL_CTRL 0xC08
|
||||
#define EDMA_WOL_WK_EN 0x00000001
|
||||
#define EDMA_WOL_MG_EN 0x00000002
|
||||
#define EDMA_WOL_PT0_EN 0x00000004
|
||||
#define EDMA_WOL_PT1_EN 0x00000008
|
||||
#define EDMA_WOL_PT2_EN 0x00000010
|
||||
#define EDMA_WOL_PT3_EN 0x00000020
|
||||
#define EDMA_WOL_PT4_EN 0x00000040
|
||||
#define EDMA_WOL_PT5_EN 0x00000080
|
||||
#define EDMA_WOL_PT6_EN 0x00000100
|
||||
|
||||
/* MAC Control Register */
|
||||
#define EDMA_REG_MAC_CTRL0 0xC20
|
||||
#define EDMA_REG_MAC_CTRL1 0xC24
|
||||
|
||||
/* WoL Pattern Register */
|
||||
#define EDMA_REG_WOL_PATTERN_START 0x5000
|
||||
#define EDMA_PATTERN_PART_REG_OFFSET 0x40
|
||||
|
||||
|
||||
/* TX descriptor fields */
|
||||
#define EDMA_TPD_HDR_SHIFT 0
|
||||
#define EDMA_TPD_PPPOE_EN 0x00000100
|
||||
#define EDMA_TPD_IP_CSUM_EN 0x00000200
|
||||
#define EDMA_TPD_TCP_CSUM_EN 0x0000400
|
||||
#define EDMA_TPD_UDP_CSUM_EN 0x00000800
|
||||
#define EDMA_TPD_CUSTOM_CSUM_EN 0x00000C00
|
||||
#define EDMA_TPD_LSO_EN 0x00001000
|
||||
#define EDMA_TPD_LSO_V2_EN 0x00002000
|
||||
#define EDMA_TPD_IPV4_EN 0x00010000
|
||||
#define EDMA_TPD_MSS_MASK 0x1FFF
|
||||
#define EDMA_TPD_MSS_SHIFT 18
|
||||
#define EDMA_TPD_CUSTOM_CSUM_SHIFT 18
|
||||
|
||||
/* RRD descriptor fields */
|
||||
#define EDMA_RRD_NUM_RFD_MASK 0x000F
|
||||
#define EDMA_RRD_SVLAN 0x8000
|
||||
#define EDMA_RRD_FLOW_COOKIE_MASK 0x07FF;
|
||||
|
||||
#define EDMA_RRD_PKT_SIZE_MASK 0x3FFF
|
||||
#define EDMA_RRD_CSUM_FAIL_MASK 0xC000
|
||||
#define EDMA_RRD_CVLAN 0x0001
|
||||
#define EDMA_RRD_DESC_VALID 0x8000
|
||||
|
||||
#define EDMA_RRD_PRIORITY_SHIFT 4
|
||||
#define EDMA_RRD_PRIORITY_MASK 0x7
|
||||
#define EDMA_RRD_PORT_TYPE_SHIFT 7
|
||||
#define EDMA_RRD_PORT_TYPE_MASK 0x1F
|
||||
|
||||
#define ESS_RGMII_CTRL 0x0004
|
||||
|
||||
/* Port status registers */
|
||||
#define ESS_PORT0_STATUS 0x007C
|
||||
#define ESS_PORT1_STATUS 0x0080
|
||||
#define ESS_PORT2_STATUS 0x0084
|
||||
#define ESS_PORT3_STATUS 0x0088
|
||||
#define ESS_PORT4_STATUS 0x008C
|
||||
#define ESS_PORT5_STATUS 0x0090
|
||||
|
||||
#define ESS_PORT_STATUS_HDX_FLOW_CTL 0x80
|
||||
#define ESS_PORT_STATUS_DUPLEX_MODE 0x40
|
||||
#define ESS_PORT_STATUS_RX_FLOW_EN 0x20
|
||||
#define ESS_PORT_STATUS_TX_FLOW_EN 0x10
|
||||
#define ESS_PORT_STATUS_RX_MAC_EN 0x08
|
||||
#define ESS_PORT_STATUS_TX_MAC_EN 0x04
|
||||
#define ESS_PORT_STATUS_SPEED_INV 0x03
|
||||
#define ESS_PORT_STATUS_SPEED_1000 0x02
|
||||
#define ESS_PORT_STATUS_SPEED_100 0x01
|
||||
#define ESS_PORT_STATUS_SPEED_10 0x00
|
||||
|
||||
#define ESS_PORT_1G_FDX (ESS_PORT_STATUS_DUPLEX_MODE | ESS_PORT_STATUS_RX_FLOW_EN | \
|
||||
ESS_PORT_STATUS_TX_FLOW_EN | ESS_PORT_STATUS_RX_MAC_EN | \
|
||||
ESS_PORT_STATUS_TX_MAC_EN | ESS_PORT_STATUS_SPEED_1000)
|
||||
|
||||
#define PHY_STATUS_REG 0x11
|
||||
#define PHY_STATUS_SPEED 0xC000
|
||||
#define PHY_STATUS_SPEED_SHIFT 14
|
||||
#define PHY_STATUS_DUPLEX 0x2000
|
||||
#define PHY_STATUS_DUPLEX_SHIFT 13
|
||||
#define PHY_STATUS_SPEED_DUPLEX_RESOLVED 0x0800
|
||||
#define PHY_STATUS_CARRIER 0x0400
|
||||
#define PHY_STATUS_CARRIER_SHIFT 10
|
||||
|
||||
/* Port lookup control registers */
|
||||
#define ESS_PORT0_LOOKUP_CTRL 0x0660
|
||||
#define ESS_PORT1_LOOKUP_CTRL 0x066C
|
||||
#define ESS_PORT2_LOOKUP_CTRL 0x0678
|
||||
#define ESS_PORT3_LOOKUP_CTRL 0x0684
|
||||
#define ESS_PORT4_LOOKUP_CTRL 0x0690
|
||||
#define ESS_PORT5_LOOKUP_CTRL 0x069C
|
||||
|
||||
#define ESS_PORT0_HEADER_CTRL 0x009C
|
||||
|
||||
#define ESS_PORTS_ALL 0x3f
|
||||
|
||||
#define ESS_FWD_CTRL1 0x0624
|
||||
#define ESS_FWD_CTRL1_UC_FLOOD BITS(0, 7)
|
||||
#define ESS_FWD_CTRL1_UC_FLOOD_S 0
|
||||
#define ESS_FWD_CTRL1_MC_FLOOD BITS(8, 7)
|
||||
#define ESS_FWD_CTRL1_MC_FLOOD_S 8
|
||||
#define ESS_FWD_CTRL1_BC_FLOOD BITS(16, 7)
|
||||
#define ESS_FWD_CTRL1_BC_FLOOD_S 16
|
||||
#define ESS_FWD_CTRL1_IGMP BITS(24, 7)
|
||||
#define ESS_FWD_CTRL1_IGMP_S 24
|
||||
|
||||
#endif /* _ESS_EDMA_H_ */
|
||||
|
|
@ -0,0 +1,300 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
#include "qcom-ipq4019.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/soc/qcom,tcsr.h>
|
||||
|
||||
/ {
|
||||
model = "MobiPromo CM520-79F";
|
||||
compatible = "mobipromo,cm520-79f";
|
||||
|
||||
aliases {
|
||||
led-boot = &led_sys;
|
||||
led-failsafe = &led_sys;
|
||||
led-running = &led_sys;
|
||||
led-upgrade = &led_sys;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs-append = " ubi.block=0,1 root=/dev/ubiblock0_1";
|
||||
};
|
||||
|
||||
soc {
|
||||
rng@22000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mdio@90000 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
|
||||
reset-delay-us = <1000>;
|
||||
};
|
||||
|
||||
ess-psgmii@98000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tcsr@1949000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1949000 0x100>;
|
||||
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
|
||||
};
|
||||
|
||||
tcsr@194b000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x194b000 0x100>;
|
||||
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
|
||||
};
|
||||
|
||||
ess_tcsr@1953000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1953000 0x1000>;
|
||||
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
|
||||
};
|
||||
|
||||
tcsr@1957000 {
|
||||
compatible = "qcom,tcsr";
|
||||
reg = <0x1957000 0x100>;
|
||||
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
|
||||
};
|
||||
|
||||
usb2@60f8800 {
|
||||
status = "okay";
|
||||
|
||||
dwc3@6000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
usb2_port1: port@1 {
|
||||
reg = <1>;
|
||||
#trigger-source-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usb3@8af8800 {
|
||||
status = "okay";
|
||||
|
||||
dwc3@8a00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
usb3_port1: port@1 {
|
||||
reg = <1>;
|
||||
#trigger-source-cells = <0>;
|
||||
};
|
||||
|
||||
usb3_port2: port@2 {
|
||||
reg = <2>;
|
||||
#trigger-source-cells = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
crypto@8e3a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@b017000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ess-switch@c000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
edma@c080000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
led_spi {
|
||||
compatible = "spi-gpio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sck-gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
|
||||
mosi-gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>;
|
||||
num-chipselects = <0>;
|
||||
|
||||
led_gpio: led_gpio@0 {
|
||||
compatible = "fairchild,74hc595";
|
||||
reg = <0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
registers-number = <1>;
|
||||
spi-max-frequency = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led_usb: usb {
|
||||
label = "cm520-79f:blue:usb";
|
||||
gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "usbport";
|
||||
trigger-sources = <&usb3_port1>, <&usb3_port2>, <&usb2_port1>;
|
||||
};
|
||||
|
||||
led_sys: can {
|
||||
label = "cm520-79f:blue:can";
|
||||
gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
wan {
|
||||
label = "cm520-79f:blue:wan";
|
||||
gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
lan1 {
|
||||
label = "cm520-79f:blue:lan1";
|
||||
gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
lan2 {
|
||||
label = "cm520-79f:blue:lan2";
|
||||
gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
wlan2g {
|
||||
label = "cm520-79f:blue:wlan2g";
|
||||
gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "phy0tpt";
|
||||
};
|
||||
|
||||
wlan5g {
|
||||
label = "cm520-79f:blue:wlan5g";
|
||||
gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "phy1tpt";
|
||||
};
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&blsp_dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&blsp1_uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cryptobam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
mtd-mac-address = <&art 0x1006>;
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
mtd-mac-address = <&art 0x5006>;
|
||||
};
|
||||
|
||||
&nand {
|
||||
pinctrl-0 = <&nand_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
nand@0 {
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "Bootloader";
|
||||
reg = <0x0 0xb00000>;
|
||||
};
|
||||
|
||||
art: partition@b00000 {
|
||||
label = "ART";
|
||||
reg = <0xb00000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@b80000 {
|
||||
label = "rootfs";
|
||||
reg = <0xb80000 0x7480000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qpic_bam {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tlmm {
|
||||
mdio_pins: mdio_pinmux {
|
||||
mux_1 {
|
||||
pins = "gpio6";
|
||||
function = "mdio";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mux_2 {
|
||||
pins = "gpio7";
|
||||
function = "mdc";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
nand_pins: nand_pins {
|
||||
pullups {
|
||||
pins = "gpio52", "gpio53", "gpio58",
|
||||
"gpio59";
|
||||
function = "qpic";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pulldowns {
|
||||
pins = "gpio54", "gpio55", "gpio56",
|
||||
"gpio57", "gpio60", "gpio61",
|
||||
"gpio62", "gpio63", "gpio64",
|
||||
"gpio65", "gpio66", "gpio67",
|
||||
"gpio68", "gpio69";
|
||||
function = "qpic";
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb3_ss_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_hs_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi0 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "CM520-79F";
|
||||
};
|
||||
|
||||
&wifi1 {
|
||||
status = "okay";
|
||||
qcom,ath10k-calibration-variant = "CM520-79F";
|
||||
};
|
||||
Loading…
Add table
Add a link
Reference in a new issue