From 674cd38ac7ba0c02b262db39e7346d509b10ea0b Mon Sep 17 00:00:00 2001 From: "Ycarus (Yannick Chabanois)" Date: Fri, 29 Sep 2023 19:20:54 +0200 Subject: [PATCH] Remove mediatek 6.1 as already upstream --- .../arch/arm64/boot/dts/mediatek/mt7981.dtsi | 775 ---------- .../dts/mediatek/mt7986a-rfb-spim-nand.dts | 52 - .../dts/mediatek/mt7986a-rfb-spim-nor.dts | 51 - .../arm64/boot/dts/mediatek/mt7986a-rfb.dtsi | 389 ----- .../mediatek/mt7988a-dsa-10g-spim-nand.dts | 200 --- .../dts/mediatek/mt7988a-rfb-spim-nand.dtsi | 70 - .../arm64/boot/dts/mediatek/mt7988a-rfb.dtsi | 175 --- .../arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 853 ----------- .../drivers/clk/mediatek/clk-mt7988-apmixed.c | 113 -- .../drivers/clk/mediatek/clk-mt7988-eth.c | 141 -- .../clk/mediatek/clk-mt7988-infracfg.c | 369 ----- .../clk/mediatek/clk-mt7988-topckgen.c | 446 ------ .../drivers/net/phy/mediatek-2p5ge.c | 262 ---- .../drivers/pinctrl/mediatek/pinctrl-mt7988.c | 1282 ----------------- .../dt-bindings/clock/mediatek,mt7988-clk.h | 276 ---- .../files/drivers/net/phy/rtk/rtl8367s_mdio.c | 309 ---- 6.1/target/linux/mediatek/mt7622/config-6.1 | 515 ------- 6.1/target/linux/mediatek/mt7623/config-6.1 | 609 -------- 6.1/target/linux/mediatek/mt7629/config-6.1 | 349 ----- ...-overlays-to-built-from-.dtso-named-.patch | 44 - ...ek-mt7986-add-support-for-RX-Wireles.patch | 106 -- ...s-mt7986-harmonize-device-node-order.patch | 166 --- ...7986-add-crypto-related-device-nodes.patch | 68 - ...4-v6.2-arm64-dts-mt7986-add-i2c-node.patch | 37 - ...s-mediatek-mt7986-Add-SoC-compatible.patch | 61 - ...-mt7986-add-spi-related-device-nodes.patch | 157 -- ...-mt7986-add-usb-related-device-nodes.patch | 127 -- ...-mt7986-add-mmc-related-device-nodes.patch | 160 -- ...mt7986-add-pcie-related-device-nodes.patch | 118 -- ...6.3-arm64-dts-mt7986-add-Bananapi-R3.patch | 689 --------- ...ropagate-chassis-type-where-possible.patch | 323 ----- .../012-v6.5-arm64-dts-mt7986-add-PWM.patch | 38 - ...5-arm64-dts-mt7986-add-PWM-to-BPI-R3.patch | 43 - ...-set-Wifi-Leds-low-active-for-BPI-R3.patch | 27 - ...-use-size-of-reserved-partition-for-.patch | 46 - ...m64-dts-mt7986-add-thermal-and-efuse.patch | 80 - ...5-arm64-dts-mt7986-add-thermal-zones.patch | 51 - ...-add-pwm-fan-and-cooling-maps-to-BPI.patch | 64 - ...-increase-bl2-partition-on-NAND-of-B.patch | 41 - .../100-dts-update-mt7622-rfb1.patch | 107 -- .../101-dts-update-mt7629-rfb.patch | 60 - .../103-mt7623-enable-arch-timer.patch | 20 - .../patches-6.1/104-mt7622-add-snor-irq.patch | 10 - .../105-dts-mt7622-enable-pstore.patch | 16 - .../110-dts-fix-bpi2-console.patch | 10 - .../111-dts-fix-bpi64-console.patch | 11 - .../112-dts-fix-bpi64-lan-names.patch | 37 - .../113-dts-fix-bpi64-leds-and-buttons.patch | 47 - .../114-dts-bpi64-disable-rtc.patch | 21 - .../115-dts-bpi64-add-snand-support.patch | 50 - .../121-hack-spi-nand-1b-bbm.patch | 20 - .../130-dts-mt7629-add-snand-support.patch | 94 -- .../131-dts-mt7622-add-snand-support.patch | 68 - ...dts-fix-wmac-support-for-mt7622-rfb1.patch | 18 - ...s-mt7623-eip97-inside-secure-support.patch | 24 - .../160-dts-mt7623-bpi-r2-earlycon.patch | 11 - ...1-dts-mt7623-bpi-r2-mmc-device-order.patch | 11 - .../162-dts-mt7623-bpi-r2-led-aliases.patch | 29 - ...163-dts-mt7623-bpi-r2-ethernet-alias.patch | 10 - ...80-dts-mt7622-bpi-r64-add-mt7531-irq.patch | 13 - ...-dts-mediatek-mt7622-fix-GICv2-range.patch | 106 -- .../193-dts-mt7623-thermal_zone_fix.patch | 48 - .../194-dts-mt7968a-add-ramoops.patch | 17 - ...i-r3-leds-port-names-and-wifi-eeprom.patch | 196 --- ...-phy-phy-mtk-tphy-Add-hifsys-support.patch | 66 - ...llow-configuring-uart-rx-tx-and-rts-.patch | 88 -- ...-add-pull_type-attribute-for-mediate.patch | 100 -- ....3-pinctrl-add-mt7981-pinctrl-driver.patch | 1094 -------------- ...-add-missing-options-to-PINCTRL_MT79.patch | 30 - ...-gate-Propagate-struct-device-with-m.patch | 536 ------- ...mux-Propagate-struct-device-where-po.patch | 140 -- ...-mtk-Propagate-struct-device-for-com.patch | 181 --- ...-mux-Propagate-struct-device-for-mtk.patch | 103 -- ...mediatek-clk-mtk-Add-dummy-clock-ops.patch | 74 - ...tch-to-mtk_clk_simple_probe-where-po.patch | 790 ---------- ...-clk-mtk-Extend-mtk_clk_simple_probe.patch | 189 --- ...-mt7986-topckgen-Properly-keep-some-.patch | 97 -- ...-mt7986-topckgen-Migrate-to-mtk_clk_.patch | 88 -- ...986-apmixed-Use-PLL_AO-flag-to-set-c.patch | 38 - ...-clock-mediatek-add-mt7981-clock-IDs.patch | 237 --- ...lk-mediatek-add-MT7981-clock-support.patch | 932 ------------ ...-mediatek-add-support-for-MT7988-SoC.patch | 26 - ...k-mediatek-Add-pcw-chg-shift-control.patch | 24 - ...lk-mediatek-add-mt7988-clock-support.patch | 31 - ...-mediatek-add-support-for-MT7986-SoC.patch | 47 - ...d-Inline-Crypto-Engine-clock-control.patch | 57 - ...fix-two-spelling-mistakes-in-comment.patch | 36 - ...d-open-coding-by-using-mmc_op_tuning.patch | 39 - .../330-snand-mtk-bmt-support.patch | 34 - .../331-mt7622-rfb1-enable-bmt.patch | 10 - ...Add-support-for-the-Fidelix-FM35X1GA.patch | 122 -- ...ypto-add-eip97-inside-secure-support.patch | 27 - ...01-crypto-fix-eip97-cache-incoherent.patch | 26 - ...405-v6.2-mt7986-trng-add-rng-support.patch | 43 - .../patches-6.1/410-bt-mtk-serial-fix.patch | 33 - ...xx-Move-chip_config-to-driver-s-priv.patch | 130 -- ...-Add-support-for-dynamic-calibration.patch | 236 --- ...ers-spi-mem-Add-spi-calibration-hook.patch | 41 - ...xx-Add-controller-s-calibration-para.patch | 43 - ...and-Add-calibration-support-for-spin.patch | 81 -- ...nor-Add-calibration-support-for-spi-.patch | 57 - .../500-gsw-rtl8367s-mt7622-support.patch | 25 - ...ert-PERST-for-100ms-for-power-and-cl.patch | 34 - ...s-mediatek-add-mt7622-pcie-slot-node.patch | 28 - ...diatek-fix-clearing-interrupt-status.patch | 23 - ...ediatek-add-support-for-coherent-DMA.patch | 82 -- .../721-dts-mt7622-mediatek-fix-300mhz.patch | 27 - .../722-remove-300Hz-to-prevent-freeze.patch | 25 - ...er-for-MediaTek-SoC-built-in-GE-PHYs.patch | 1204 ---------------- ...-ge-soc-initialize-MT7988-PHY-LEDs-d.patch | 213 --- ...-don-t-use-SGMII-AN-if-using-phylink.patch | 63 - ...phy-add-driver-for-MediaTek-2.5G-PHY.patch | 39 - .../804-pwm-add-mt7986-support.patch | 23 - ...mtk-use-function-pointer-for-raw_to_.patch | 56 - ...ek-add-support-for-MT7986-and-MT7981.patch | 240 --- ...-extend-pinctrl-moore-to-support-new.patch | 129 -- ...v6.2-i2c-mediatek-add-mt7986-support.patch | 44 - ...evm_platform_get_and_ioremap_resourc.patch | 42 - ...t65xx-drop-of_match_ptr-for-ID-table.patch | 33 - ...-mediatek-add-support-for-MT7981-SoC.patch | 47 - ...mt7622-bpi-r64-aliases-for-dtoverlay.patch | 65 - .../901-arm-add-cmdline-override.patch | 54 - .../910-dts-mt7622-bpi-r64-wifi-eeprom.patch | 31 - .../930-spi-mt65xx-enable-sel-clk.patch | 18 - ..._wed-rename-mtk_wed_get_memory_regio.patch | 44 - ...986-move-cpuboot-in-a-dedicated-node.patch | 66 - ..._wed-move-cpuboot-in-a-dedicated-dts.patch | 89 -- ...tk_wed-move-ilm-a-dedicated-dts-node.patch | 91 -- ...tk_wed-move-dlm-a-dedicated-dts-node.patch | 57 - ...-mt7986-move-ilm-in-a-dedicated-node.patch | 83 -- ...-mt7986-move-dlm-in-a-dedicated-node.patch | 81 -- 131 files changed, 19718 deletions(-) delete mode 100644 6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi delete mode 100644 6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts delete mode 100644 6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts delete mode 100644 6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi delete mode 100644 6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts delete mode 100644 6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtsi delete mode 100644 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6.1/target/linux/mediatek/patches-6.1/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch diff --git a/6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi b/6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi deleted file mode 100644 index 3629a6f6..00000000 --- a/6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7981.dtsi +++ /dev/null @@ -1,775 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (c) 2020 MediaTek Inc. - * Author: Sam.Shih - * Author: Jianhui Zhao - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "mediatek,mt7981"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a53"; - enable-method = "psci"; - reg = <0x1>; - }; - }; - - pwm: pwm@10048000 { - compatible = "mediatek,mt7981-pwm"; - reg = <0 0x10048000 0 0x1000>; - #pwm-cells = <2>; - clocks = <&infracfg CLK_INFRA_PWM_STA>, - <&infracfg CLK_INFRA_PWM_HCK>, - <&infracfg CLK_INFRA_PWM1_CK>, - <&infracfg CLK_INFRA_PWM2_CK>, - <&infracfg CLK_INFRA_PWM3_CK>; - clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; - }; - - fan: pwm-fan { - compatible = "pwm-fan"; - /* cooling level (0, 1, 2, 3) : (0% duty, 50% duty, 75% duty, 100% duty) */ - cooling-levels = <0 128 192 255>; - #cooling-cells = <2>; - status = "disabled"; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <1000>; - thermal-sensors = <&thermal 0>; - trips { - cpu_trip_crit: crit { - temperature = <125000>; - hysteresis = <2000>; - type = "critical"; - }; - - cpu_trip_hot: hot { - temperature = <120000>; - hysteresis = <2000>; - type = "hot"; - }; - - cpu_trip_active_high: active-high { - temperature = <115000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_med: active-med { - temperature = <85000>; - hysteresis = <2000>; - type = "active"; - }; - - cpu_trip_active_low: active-low { - temperature = <60000>; - hysteresis = <2000>; - type = "active"; - }; - }; - - cooling-maps { - cpu-active-high { - /* active: set fan to cooling level 3 */ - cooling-device = <&fan 3 3>; - trip = <&cpu_trip_active_high>; - }; - - cpu-active-med { - /* active: set fan to cooling level 2 */ - cooling-device = <&fan 2 2>; - trip = <&cpu_trip_active_med>; - }; - - cpu-active-low { - /* passive: set fan to cooling level 1 */ - cooling-device = <&fan 1 1>; - trip = <&cpu_trip_active_low>; - }; - }; - }; - }; - - thermal: thermal@1100c800 { - #thermal-sensor-cells = <1>; - compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal"; - reg = <0 0x1100c800 0 0x800>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_THERM_CK>, - <&infracfg CLK_INFRA_ADC_26M_CK>; - clock-names = "therm", "auxadc"; - mediatek,auxadc = <&auxadc>; - mediatek,apmixedsys = <&apmixedsys>; - nvmem-cells = <&thermal_calibration>; - nvmem-cell-names = "calibration-data"; - }; - - auxadc: adc@1100d000 { - compatible = "mediatek,mt7981-auxadc", - "mediatek,mt7986-auxadc", - "mediatek,mt7622-auxadc"; - reg = <0 0x1100d000 0 0x1000>; - clocks = <&infracfg CLK_INFRA_ADC_26M_CK>, - <&infracfg CLK_INFRA_ADC_FRC_CK>; - clock-names = "main", "32k"; - #io-channel-cells = <1>; - }; - - wdma: wdma@15104800 { - compatible = "mediatek,wed-wdma"; - reg = <0 0x15104800 0 0x400>, - <0 0x15104c00 0 0x400>; - }; - - ap2woccif: ap2woccif@151a5000 { - compatible = "mediatek,ap2woccif"; - reg = <0 0x151a5000 0 0x1000>, - <0 0x151ad000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = , - ; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* 64 KiB reserved for ramoops/pstore */ - ramoops@42ff0000 { - compatible = "ramoops"; - reg = <0 0x42ff0000 0 0x10000>; - record-size = <0x1000>; - }; - - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x30000>; - no-map; - }; - - wmcpu_emi: wmcpu-reserved@47c80000 { - reg = <0 0x47c80000 0 0x100000>; - no-map; - }; - - wo_emi0: wo-emi@47d80000 { - reg = <0 0x47d80000 0 0x40000>; - no-map; - }; - - wo_data: wo-data@47dc0000 { - reg = <0 0x47dc0000 0 0x240000>; - no-map; - }; - - wo_ilm0: wo-ilm@151e0000 { - reg = <0 0x151e0000 0 0x8000>; - no-map; - }; - - wo_dlm0: wo-dlm@151e8000 { - reg = <0 0x151e8000 0 0x2000>; - no-map; - }; - - wo_boot: wo-boot@15194000 { - reg = <0 0x15194000 0 0x1000>; - no-map; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - trng { - compatible = "mediatek,mt7981-rng"; - }; - - clk40m: oscillator@0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <40000000>; - clock-output-names = "clkxtal"; - }; - - infracfg: infracfg@10001000 { - compatible = "mediatek,mt7981-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - }; - - topckgen: topckgen@1001B000 { - compatible = "mediatek,mt7981-topckgen", "syscon"; - reg = <0 0x1001B000 0 0x1000>; - #clock-cells = <1>; - }; - - apmixedsys: apmixedsys@1001E000 { - compatible = "mediatek,mt7981-apmixedsys", "mediatek,mt7986-apmixedsys", "syscon"; - reg = <0 0x1001E000 0 0x1000>; - #clock-cells = <1>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - clock-frequency = <13000000>; - interrupts = , - , - , - ; - - }; - - watchdog: watchdog@1001c000 { - compatible = "mediatek,mt7986-wdt", - "mediatek,mt6589-wdt"; - reg = <0 0x1001c000 0 0x1000>; - interrupts = ; - #reset-cells = <1>; - status = "disabled"; - }; - - gic: interrupt-controller@c000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - interrupt-controller; - reg = <0 0x0c000000 0 0x40000>, /* GICD */ - <0 0x0c080000 0 0x200000>; /* GICR */ - - interrupts = ; - }; - - uart0: serial@11002000 { - compatible = "mediatek,mt6577-uart"; - reg = <0 0x11002000 0 0x400>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_UART0_SEL>, - <&infracfg CLK_INFRA_UART0_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_UART0_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, - <&topckgen CLK_TOP_UART_SEL>; - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; - status = "disabled"; - }; - - uart1: serial@11003000 { - compatible = "mediatek,mt6577-uart"; - reg = <0 0x11003000 0 0x400>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_UART1_SEL>, - <&infracfg CLK_INFRA_UART1_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_UART1_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, - <&topckgen CLK_TOP_UART_SEL>; - status = "disabled"; - }; - - uart2: serial@11004000 { - compatible = "mediatek,mt6577-uart"; - reg = <0 0x11004000 0 0x400>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_UART2_SEL>, - <&infracfg CLK_INFRA_UART2_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_UART2_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>, - <&topckgen CLK_TOP_UART_SEL>; - status = "disabled"; - }; - - i2c0: i2c@11007000 { - compatible = "mediatek,mt7981-i2c"; - reg = <0 0x11007000 0 0x1000>, - <0 0x10217080 0 0x80>; - interrupts = ; - clock-div = <1>; - clocks = <&infracfg CLK_INFRA_I2C0_CK>, - <&infracfg CLK_INFRA_AP_DMA_CK>, - <&infracfg CLK_INFRA_I2C_MCK_CK>, - <&infracfg CLK_INFRA_I2C_PCK_CK>; - clock-names = "main", "dma", "arb", "pmic"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - pcie: pcie@11280000 { - compatible = "mediatek,mt7981-pcie", - "mediatek,mt7986-pcie"; - device_type = "pci"; - reg = <0 0x11280000 0 0x4000>; - reg-names = "pcie-mac"; - #address-cells = <3>; - #size-cells = <2>; - interrupts = ; - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 - 0x0 0x20000000 0 0x10000000>; - status = "disabled"; - - clocks = <&infracfg CLK_INFRA_IPCIE_CK>, - <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, - <&infracfg CLK_INFRA_IPCIER_CK>, - <&infracfg CLK_INFRA_IPCIEB_CK>; - - phys = <&u3port0 PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie_intc 0>, - <0 0 0 2 &pcie_intc 1>, - <0 0 0 3 &pcie_intc 2>, - <0 0 0 4 &pcie_intc 3>; - pcie_intc: interrupt-controller { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - - crypto: crypto@10320000 { - compatible = "inside-secure,safexcel-eip97"; - reg = <0 0x10320000 0 0x40000>; - interrupts = , - , - , - ; - interrupt-names = "ring0", "ring1", "ring2", "ring3"; - clocks = <&topckgen CLK_TOP_EIP97B>; - clock-names = "top_eip97_ck"; - assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>; - }; - - pio: pinctrl@11d00000 { - compatible = "mediatek,mt7981-pinctrl"; - reg = <0 0x11d00000 0 0x1000>, - <0 0x11c00000 0 0x1000>, - <0 0x11c10000 0 0x1000>, - <0 0x11d20000 0 0x1000>, - <0 0x11e00000 0 0x1000>, - <0 0x11e20000 0 0x1000>, - <0 0x11f00000 0 0x1000>, - <0 0x11f10000 0 0x1000>, - <0 0x1000b000 0 0x1000>; - reg-names = "gpio", "iocfg_rt", "iocfg_rm", - "iocfg_rb", "iocfg_lb", "iocfg_bl", - "iocfg_tm", "iocfg_tl", "eint"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 56>; - interrupt-controller; - interrupts = ; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - - mdio_pins: mdc-mdio-pins { - mux { - function = "eth"; - groups = "smi_mdc_mdio"; - }; - }; - - uart0_pins: uart0-pins { - mux { - function = "uart"; - groups = "uart0"; - }; - }; - - wifi_dbdc_pins: wifi-dbdc-pins { - mux { - function = "eth"; - groups = "wf0_mode1"; - }; - conf { - pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4", - "WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6", - "WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10", - "WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ", - "WF_CBA_RESETB", "WF_DIG_RESETB"; - drive-strength = <4>; - }; - }; - }; - - ethsys: syscon@15000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mediatek,mt7981-ethsys", - "mediatek,mt7986-ethsys", - "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - wed: wed@15010000 { - compatible = "mediatek,mt7981-wed", - "mediatek,mt7986-wed", - "syscon"; - reg = <0 0x15010000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, - <&wo_data>, <&wo_boot>; - memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", - "wo-data", "wo-boot"; - mediatek,wo-ccif = <&wo_ccif0>; - }; - - eth: ethernet@15100000 { - compatible = "mediatek,mt7981-eth"; - reg = <0 0x15100000 0 0x80000>; - interrupts = , - , - , - ; - clocks = <ðsys CLK_ETH_FE_EN>, - <ðsys CLK_ETH_GP2_EN>, - <ðsys CLK_ETH_GP1_EN>, - <ðsys CLK_ETH_WOCPU0_EN>, - <&sgmiisys0 CLK_SGM0_TX_EN>, - <&sgmiisys0 CLK_SGM0_RX_EN>, - <&sgmiisys0 CLK_SGM0_CK0_EN>, - <&sgmiisys0 CLK_SGM0_CDR_CK0_EN>, - <&sgmiisys1 CLK_SGM1_TX_EN>, - <&sgmiisys1 CLK_SGM1_RX_EN>, - <&sgmiisys1 CLK_SGM1_CK1_EN>, - <&sgmiisys1 CLK_SGM1_CDR_CK1_EN>, - <&topckgen CLK_TOP_SGM_REG>, - <&topckgen CLK_TOP_NETSYS_SEL>, - <&topckgen CLK_TOP_NETSYS_500M_SEL>; - clock-names = "fe", "gp2", "gp1", "wocpu0", - "sgmii_tx250m", "sgmii_rx250m", - "sgmii_cdr_ref", "sgmii_cdr_fb", - "sgmii2_tx250m", "sgmii2_rx250m", - "sgmii2_cdr_ref", "sgmii2_cdr_fb", - "sgmii_ck", "netsys0", "netsys1"; - assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, - <&topckgen CLK_TOP_SGM_325M_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>, - <&topckgen CLK_TOP_CB_SGM_325M>; - mediatek,ethsys = <ðsys>; - mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; - mediatek,infracfg = <&topmisc>; - mediatek,wed = <&wed>; - #reset-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - mdio_bus: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - int_gbe_phy: ethernet-phy@0 { - reg = <0>; - compatible = "ethernet-phy-ieee802.3-c22"; - phy-mode = "gmii"; - phy-is-integrated; - nvmem-cells = <&phy_calibration>; - nvmem-cell-names = "phy-cal-data"; - }; - }; - }; - - wo_ccif0: syscon@151a5000 { - compatible = "mediatek,mt7986-wo-ccif", "syscon"; - reg = <0 0x151a5000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; - }; - - sgmiisys0: syscon@10060000 { - compatible = "mediatek,mt7981-sgmiisys_0", "mediatek,mt7986-sgmiisys_0", "syscon"; - reg = <0 0x10060000 0 0x1000>; - mediatek,pnswap; - #clock-cells = <1>; - }; - - sgmiisys1: syscon@10070000 { - compatible = "mediatek,mt7981-sgmiisys_1", "mediatek,mt7986-sgmiisys_1", "syscon"; - reg = <0 0x10070000 0 0x1000>; - #clock-cells = <1>; - }; - - topmisc: topmisc@11d10000 { - compatible = "mediatek,mt7981-topmisc", "syscon"; - reg = <0 0x11d10000 0 0x10000>; - #clock-cells = <1>; - }; - - snand: snfi@11005000 { - compatible = "mediatek,mt7986-snand"; - reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>; - reg-names = "nfi", "ecc"; - interrupts = ; - clocks = <&infracfg CLK_INFRA_SPINFI1_CK>, - <&infracfg CLK_INFRA_NFI1_CK>, - <&infracfg CLK_INFRA_NFI_HCK_CK>; - clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; - assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>, - <&topckgen CLK_TOP_NFI1X_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>, - <&topckgen CLK_TOP_CB_M_D8>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - mmc0: mmc@11230000 { - compatible = "mediatek,mt7986-mmc", - "mediatek,mt7981-mmc"; - reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_MSDC_CK>, - <&infracfg CLK_INFRA_MSDC_HCK_CK>, - <&infracfg CLK_INFRA_MSDC_66M_CK>, - <&infracfg CLK_INFRA_MSDC_133M_CK>; - assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>, - <&topckgen CLK_TOP_EMMC_400M_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>, - <&topckgen CLK_TOP_CB_NET2_D2>; - clock-names = "source", "hclk", "axi_cg", "ahb_cg"; - status = "disabled"; - }; - - wed_pcie: wed_pcie@10003000 { - compatible = "mediatek,wed_pcie"; - reg = <0 0x10003000 0 0x10>; - }; - - spi0: spi@1100a000 { - compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x1100a000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_CB_M_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_SPI0_CK>, - <&infracfg CLK_INFRA_SPI0_HCK_CK>; - - clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; - status = "disabled"; - }; - - spi1: spi@1100b000 { - compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x1100b000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_CB_M_D2>, - <&topckgen CLK_TOP_SPIM_MST_SEL>, - <&infracfg CLK_INFRA_SPI1_CK>, - <&infracfg CLK_INFRA_SPI1_HCK_CK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; - status = "disabled"; - }; - - spi2: spi@11009000 { - compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0x11009000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_CB_M_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_SPI2_CK>, - <&infracfg CLK_INFRA_SPI2_HCK_CK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; - status = "disabled"; - }; - - consys: consys@10000000 { - compatible = "mediatek,mt7981-consys"; - reg = <0 0x10000000 0 0x8600000>; - memory-region = <&wmcpu_emi>; - }; - - xhci: usb@11200000 { - compatible = "mediatek,mt7986-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x11200000 0 0x2e00>, - <0 0x11203e00 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, - <&infracfg CLK_INFRA_IUSB_CK>, - <&infracfg CLK_INFRA_IUSB_133_CK>, - <&infracfg CLK_INFRA_IUSB_66M_CK>, - <&topckgen CLK_TOP_U2U3_XHCI_SEL>; - clock-names = "sys_ck", - "ref_ck", - "mcu_ck", - "dma_ck", - "xhci_ck"; - phys = <&u2port0 PHY_TYPE_USB2>, - <&u3port0 PHY_TYPE_USB3>; - vusb33-supply = <®_3p3v>; - status = "disabled"; - }; - - usb_phy: usb-phy@11e10000 { - compatible = "mediatek,mt7981", - "mediatek,generic-tphy-v2"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0x11e10000 0x1700>; - status = "disabled"; - - u2port0: usb-phy@0 { - reg = <0x0 0x700>; - clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>; - clock-names = "ref"; - #phy-cells = <1>; - }; - - u3port0: usb-phy@700 { - reg = <0x700 0x900>; - clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; - clock-names = "ref"; - #phy-cells = <1>; - mediatek,syscon-type = <&topmisc 0x218 0>; - status = "okay"; - }; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - efuse: efuse@11f20000 { - compatible = "mediatek,mt7981-efuse", - "mediatek,efuse"; - reg = <0 0x11f20000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - status = "okay"; - - thermal_calibration: thermal-calib@274 { - reg = <0x274 0xc>; - }; - - phy_calibration: phy-calib@8dc { - reg = <0x8dc 0x10>; - }; - - comb_rx_imp_p0: usb3-rx-imp@8c8 { - reg = <0x8c8 1>; - bits = <0 5>; - }; - - comb_tx_imp_p0: usb3-tx-imp@8c8 { - reg = <0x8c8 2>; - bits = <5 5>; - }; - - comb_intr_p0: usb3-intr@8c9 { - reg = <0x8c9 1>; - bits = <2 6>; - }; - }; - - afe: audio-controller@11210000 { - compatible = "mediatek,mt79xx-audio"; - reg = <0 0x11210000 0 0x9000>; - interrupts = ; - clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>, - <&infracfg CLK_INFRA_AUD_26M_CK>, - <&infracfg CLK_INFRA_AUD_L_CK>, - <&infracfg CLK_INFRA_AUD_AUD_CK>, - <&infracfg CLK_INFRA_AUD_EG2_CK>, - <&topckgen CLK_TOP_AUD_SEL>; - clock-names = "aud_bus_ck", - "aud_26m_ck", - "aud_l_ck", - "aud_aud_ck", - "aud_eg2_ck", - "aud_sel"; - assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>, - <&topckgen CLK_TOP_A1SYS_SEL>, - <&topckgen CLK_TOP_AUD_L_SEL>, - <&topckgen CLK_TOP_A_TUNER_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>, - <&topckgen CLK_TOP_APLL2_D4>, - <&topckgen CLK_TOP_CB_APLL2_196M>, - <&topckgen CLK_TOP_APLL2_D4>; - status = "disabled"; - }; - - ice: ice_debug { - compatible = "mediatek,mt7981-ice_debug", - "mediatek,mt2701-ice_debug"; - clocks = <&infracfg CLK_INFRA_DBG_CK>; - clock-names = "ice_dbg"; - }; - - wifi: wifi@18000000 { - compatible = "mediatek,mt7981-wmac"; - resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; - reset-names = "consys"; - pinctrl-0 = <&wifi_dbdc_pins>; - pinctrl-names = "dbdc"; - clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>, - <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; - clock-names = "mcu", "ap2conn"; - reg = <0 0x18000000 0 0x1000000>, - <0 0x10003000 0 0x1000>, - <0 0x11d10000 0 0x1000>; - interrupts = , - , - , - ; - memory-region = <&wmcpu_emi>; - status = "disabled"; - }; -}; diff --git a/6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts b/6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts deleted file mode 100644 index 83a37150..00000000 --- a/6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts +++ /dev/null @@ -1,52 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ - -#include "mt7986a-rfb.dtsi" - -/ { - compatible = "mediatek,mt7986a-rfb-snand"; -}; - -&spi0 { - status = "okay"; - - spi_nand: spi_nand@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "spi-nand"; - reg = <1>; - spi-max-frequency = <10000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "BL2"; - reg = <0x00000 0x0100000>; - read-only; - }; - partition@100000 { - label = "u-boot-env"; - reg = <0x0100000 0x0080000>; - }; - factory: partition@180000 { - label = "Factory"; - reg = <0x180000 0x0200000>; - }; - partition@380000 { - label = "FIP"; - reg = <0x380000 0x0200000>; - }; - partition@580000 { - label = "ubi"; - reg = <0x580000 0x4000000>; - }; - }; - }; -}; - -&wifi { - mediatek,mtd-eeprom = <&factory 0>; -}; diff --git a/6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts b/6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts deleted file mode 100644 index 868365a9..00000000 --- a/6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ - -#include "mt7986a-rfb.dtsi" - -/ { - compatible = "mediatek,mt7986a-rfb-snor"; -}; - -&spi0 { - status = "okay"; - - spi_nor: spi_nor@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <52000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@00000 { - label = "BL2"; - reg = <0x00000 0x0040000>; - }; - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x0010000>; - }; - factory: partition@50000 { - label = "Factory"; - reg = <0x50000 0x00B0000>; - }; - partition@100000 { - label = "FIP"; - reg = <0x100000 0x0080000>; - }; - partition@180000 { - label = "firmware"; - reg = <0x180000 0xE00000>; - }; - }; - }; -}; - -&wifi { - mediatek,mtd-eeprom = <&factory 0>; -}; diff --git a/6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi b/6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi deleted file mode 100644 index 1ab56e37..00000000 --- a/6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi +++ /dev/null @@ -1,389 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2021 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -#include "mt7986a.dtsi" - -/ { - model = "MediaTek MT7986a RFB"; - compatible = "mediatek,mt7986a-rfb"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - memory { - reg = <0 0x40000000 0 0x40000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_5v: regulator-5v { - compatible = "regulator-fixed"; - regulator-name = "fixed-5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -ð { - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "2500base-x"; - }; - - mdio: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - }; -}; - -&wifi { - status = "okay"; - pinctrl-names = "default", "dbdc"; - pinctrl-0 = <&wf_2g_5g_pins>; - pinctrl-1 = <&wf_dbdc_pins>; -}; - -&mdio { - phy5: phy@5 { - compatible = "ethernet-phy-id67c9.de0a"; - reg = <5>; - - reset-gpios = <&pio 6 1>; - reset-deassert-us = <20000>; - }; - - phy6: phy@6 { - compatible = "ethernet-phy-id67c9.de0a"; - reg = <6>; - }; - - switch: switch@0 { - compatible = "mediatek,mt7531"; - reg = <31>; - reset-gpios = <&pio 5 0>; - }; -}; - -&crypto { - status = "okay"; -}; - -&mmc0 { - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_default>; - pinctrl-1 = <&mmc0_pins_uhs>; - bus-width = <8>; - max-frequency = <200000000>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - hs400-ds-delay = <0x14014>; - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - non-removable; - no-sd; - no-sdio; - status = "okay"; -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pins>; - status = "okay"; -}; - -&pcie_phy { - status = "okay"; -}; - -&pio { - mmc0_pins_default: mmc0-pins { - mux { - function = "emmc"; - groups = "emmc_51"; - }; - conf-cmd-dat { - pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", - "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", - "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; - input-enable; - drive-strength = <4>; - mediatek,pull-up-adv = <1>; /* pull-up 10K */ - }; - conf-clk { - pins = "EMMC_CK"; - drive-strength = <6>; - mediatek,pull-down-adv = <2>; /* pull-down 50K */ - }; - conf-ds { - pins = "EMMC_DSL"; - mediatek,pull-down-adv = <2>; /* pull-down 50K */ - }; - conf-rst { - pins = "EMMC_RSTB"; - drive-strength = <4>; - mediatek,pull-up-adv = <1>; /* pull-up 10K */ - }; - }; - - mmc0_pins_uhs: mmc0-uhs-pins { - mux { - function = "emmc"; - groups = "emmc_51"; - }; - conf-cmd-dat { - pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", - "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", - "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; - input-enable; - drive-strength = <4>; - mediatek,pull-up-adv = <1>; /* pull-up 10K */ - }; - conf-clk { - pins = "EMMC_CK"; - drive-strength = <6>; - mediatek,pull-down-adv = <2>; /* pull-down 50K */ - }; - conf-ds { - pins = "EMMC_DSL"; - mediatek,pull-down-adv = <2>; /* pull-down 50K */ - }; - conf-rst { - pins = "EMMC_RSTB"; - drive-strength = <4>; - mediatek,pull-up-adv = <1>; /* pull-up 10K */ - }; - }; - - pcie_pins: pcie-pins { - mux { - function = "pcie"; - groups = "pcie_clk", "pcie_wake", "pcie_pereset"; - }; - }; - - spic_pins_g2: spic-pins-29-to-32 { - mux { - function = "spi"; - groups = "spi1_2"; - }; - }; - - spi_flash_pins: spi-flash-pins-33-to-38 { - mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; - conf-pu { - pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; - drive-strength = <8>; - mediatek,pull-up-adv = <0>; /* bias-disable */ - }; - conf-pd { - pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; - drive-strength = <8>; - mediatek,pull-down-adv = <0>; /* bias-disable */ - }; - }; - - uart1_pins: uart1-pins { - mux { - function = "uart"; - groups = "uart1"; - }; - }; - - uart2_pins: uart2-pins { - mux { - function = "uart"; - groups = "uart2"; - }; - }; - - wf_2g_5g_pins: wf_2g_5g-pins { - mux { - function = "wifi"; - groups = "wf_2g", "wf_5g"; - }; - conf { - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", - "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", - "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", - "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", - "WF1_TOP_CLK", "WF1_TOP_DATA"; - drive-strength = <4>; - }; - }; - - wf_dbdc_pins: wf_dbdc-pins { - mux { - function = "wifi"; - groups = "wf_dbdc"; - }; - conf { - pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", - "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", - "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", - "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", - "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", - "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", - "WF1_TOP_CLK", "WF1_TOP_DATA"; - drive-strength = <4>; - }; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_flash_pins>; - cs-gpios = <0>, <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; -}; - -&spi1 { - pinctrl-names = "default"; - pinctrl-0 = <&spic_pins_g2>; - status = "okay"; - - proslic_spi: proslic_spi@0 { - compatible = "silabs,proslic_spi"; - reg = <0>; - spi-max-frequency = <10000000>; - spi-cpha = <1>; - spi-cpol = <1>; - channel_count = <1>; - debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */ - reset_gpio = <&pio 7 0>; - ig,enable-spi = <1>; /* 1: Enable, 0: Disable */ - }; -}; - -&gmac1 { - phy-mode = "2500base-x"; - phy-connection-type = "2500base-x"; - phy-handle = <&phy6>; -}; - -&switch { - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan1"; - }; - - port@1 { - reg = <1>; - label = "lan2"; - }; - - port@2 { - reg = <2>; - label = "lan3"; - }; - - port@3 { - reg = <3>; - label = "lan4"; - }; - - port@4 { - reg = <4>; - label = "wan"; - }; - - port@5 { - reg = <5>; - label = "lan6"; - - phy-mode = "2500base-x"; - phy-handle = <&phy5>; - }; - - port@6 { - reg = <6>; - ethernet = <&gmac0>; - phy-mode = "2500base-x"; - - fixed-link { - speed = <2500>; - full-duplex; - pause; - }; - }; - }; -}; - -&ssusb { - vusb33-supply = <®_3p3v>; - vbus-supply = <®_5v>; - status = "okay"; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; - status = "okay"; -}; - -&usb_phy { - status = "okay"; -}; diff --git a/6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts b/6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts deleted file mode 100644 index 98dbf8d6..00000000 --- a/6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts +++ /dev/null @@ -1,200 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -#include "mt7988a-rfb-spim-nand.dtsi" -#include - -/ { - model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB"; - compatible = "mediatek,mt7988a-dsa-10g-spim-snand", - "mediatek,mt7988a-rfb-snand", - "mediatek,mt7988"; - - chosen { - bootargs = "console=ttyS0,115200n1 loglevel=8 \ - earlycon=uart8250,mmio32,0x11000000 \ - pci=pcie_bus_perf"; - }; - - memory { - reg = <0 0x40000000 0 0x40000000>; - }; -}; - -ð { - pinctrl-0 = <&mdio0_pins>; - pinctrl-names = "default"; - status = "okay"; - - gmac0: mac@0 { - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "internal"; - - fixed-link { - speed = <10000>; - full-duplex; - pause; - }; - }; - - gmac1: mac@1 { - compatible = "mediatek,eth-mac"; - reg = <1>; - phy-mode = "internal"; - phy-connection-type = "internal"; - phy = <&phy15>; - }; - - gmac2: mac@2 { - compatible = "mediatek,eth-mac"; - reg = <2>; - phy-mode = "10gbase-kr"; - phy-connection-type = "10gbase-kr"; - phy = <&phy8>; - }; - - mdio0: mdio-bus { - #address-cells = <1>; - #size-cells = <0>; - - /* external Aquantia AQR113C */ - phy0: ethernet-phy@0 { - reg = <0>; - compatible = "ethernet-phy-ieee802.3-c45"; - reset-gpios = <&pio 72 1>; - reset-assert-us = <100000>; - reset-deassert-us = <221000>; - }; - - /* external Aquantia AQR113C */ - phy8: ethernet-phy@8 { - reg = <8>; - compatible = "ethernet-phy-ieee802.3-c45"; - reset-gpios = <&pio 71 1>; - reset-assert-us = <100000>; - reset-deassert-us = <221000>; - }; - - /* external Maxlinear GPY211C */ - phy5: ethernet-phy@5 { - reg = <5>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "2500base-x"; - }; - - /* external Maxlinear GPY211C */ - phy13: ethernet-phy@13 { - reg = <13>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "2500base-x"; - }; - - /* internal 2.5G PHY */ - phy15: ethernet-phy@15 { - reg = <15>; - pinctrl-names = "i2p5gbe-led"; - pinctrl-0 = <&i2p5gbe_led0_pins>; - compatible = "ethernet-phy-ieee802.3-c45"; - phy-mode = "internal"; - }; - }; -}; - -&switch { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - label = "lan0"; - phy-mode = "internal"; - phy-handle = <&gsw_phy0>; - }; - - port@1 { - reg = <1>; - label = "lan1"; - phy-mode = "internal"; - phy-handle = <&gsw_phy1>; - }; - - port@2 { - reg = <2>; - label = "lan2"; - phy-mode = "internal"; - phy-handle = <&gsw_phy2>; - }; - - port@3 { - reg = <3>; - label = "lan3"; - phy-mode = "internal"; - phy-handle = <&gsw_phy3>; - }; - - port@6 { - reg = <6>; - ethernet = <&gmac0>; - phy-mode = "internal"; - - fixed-link { - speed = <10000>; - full-duplex; - pause; - }; - }; - }; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - gsw_phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id03a2.9481"; - reg = <0>; - phy-mode = "internal"; - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe0_led0_pins>; - nvmem-cells = <&phy_calibration_p0>; - nvmem-cell-names = "phy-cal-data"; - }; - - gsw_phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id03a2.9481"; - reg = <1>; - phy-mode = "internal"; - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe1_led0_pins>; - nvmem-cells = <&phy_calibration_p1>; - nvmem-cell-names = "phy-cal-data"; - }; - - gsw_phy2: ethernet-phy@2 { - compatible = "ethernet-phy-id03a2.9481"; - reg = <2>; - phy-mode = "internal"; - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe2_led0_pins>; - nvmem-cells = <&phy_calibration_p2>; - nvmem-cell-names = "phy-cal-data"; - }; - - gsw_phy3: ethernet-phy@3 { - compatible = "ethernet-phy-id03a2.9481"; - reg = <3>; - phy-mode = "internal"; - pinctrl-names = "gbe-led"; - pinctrl-0 = <&gbe3_led0_pins>; - nvmem-cells = <&phy_calibration_p3>; - nvmem-cell-names = "phy-cal-data"; - }; - }; -}; diff --git a/6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtsi b/6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtsi deleted file mode 100644 index e4c05712..00000000 --- a/6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtsi +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -#include "mt7988a-rfb.dtsi" - -&pio { - spi0_flash_pins: spi0-pins { - mux { - function = "spi"; - groups = "spi0", "spi0_wp_hold"; - }; - }; -}; - -&spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_flash_pins>; - status = "okay"; - - spi_nand: spi_nand@0 { - compatible = "spi-nand"; - reg = <0>; - spi-max-frequency = <52000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; - }; - -}; - -&spi_nand { - mediatek,nmbm; - mediatek,bmt-max-ratio = <1>; - mediatek,bmt-max-reserved-blocks = <64>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "BL2"; - reg = <0x00000 0x0100000>; - read-only; - }; - - partition@100000 { - label = "u-boot-env"; - reg = <0x0100000 0x0080000>; - }; - - factory: partition@180000 { - label = "Factory"; - reg = <0x180000 0x0400000>; - }; - - partition@580000 { - label = "FIP"; - reg = <0x580000 0x0200000>; - }; - - partition@780000 { - label = "ubi"; - reg = <0x780000 0x7080000>; - }; - }; -}; diff --git a/6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dtsi b/6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dtsi deleted file mode 100644 index 423b3860..00000000 --- a/6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dtsi +++ /dev/null @@ -1,175 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam.Shih - */ - -/dts-v1/; -#include "mt7988a.dtsi" -#include - -&cpu0 { - proc-supply = <&rt5190_buck3>; -}; - -&cpu1 { - proc-supply = <&rt5190_buck3>; -}; - -&cpu2 { - proc-supply = <&rt5190_buck3>; -}; - -&cpu3 { - proc-supply = <&rt5190_buck3>; -}; - -&cci { - proc-supply = <&rt5190_buck3>; -}; - -ð { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - status = "okay"; - - rt5190a_64: rt5190a@64 { - compatible = "richtek,rt5190a"; - reg = <0x64>; - /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/ - vin2-supply = <&rt5190_buck1>; - vin3-supply = <&rt5190_buck1>; - vin4-supply = <&rt5190_buck1>; - - regulators { - rt5190_buck1: buck1 { - regulator-name = "rt5190a-buck1"; - regulator-min-microvolt = <5090000>; - regulator-max-microvolt = <5090000>; - regulator-allowed-modes = - ; - regulator-boot-on; - regulator-always-on; - }; - buck2 { - regulator-name = "vcore"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - regulator-always-on; - }; - rt5190_buck3: buck3 { - regulator-name = "vproc"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1400000>; - regulator-boot-on; - }; - buck4 { - regulator-name = "rt5190a-buck4"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <850000>; - regulator-allowed-modes = - ; - regulator-boot-on; - regulator-always-on; - }; - ldo { - regulator-name = "rt5190a-ldo"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie0_pins>; - status = "okay"; -}; - -&pcie1 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie1_pins>; - status = "okay"; -}; - -&pcie2 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie2_pins>; - status = "disabled"; -}; - -&pcie3 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie3_pins>; - status = "okay"; -}; - -&ssusb0 { - status = "okay"; -}; - -&ssusb1 { - status = "okay"; -}; - -&tphy { - status = "okay"; -}; - -&pio { - pcie0_pins: pcie0-pins { - mux { - function = "pcie"; - groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", - "pcie_wake_n0_0"; - }; - }; - - pcie1_pins: pcie1-pins { - mux { - function = "pcie"; - groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", - "pcie_wake_n1_0"; - }; - }; - - pcie2_pins: pcie2-pins { - mux { - function = "pcie"; - groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", - "pcie_wake_n2_0"; - }; - }; - - pcie3_pins: pcie3-pins { - mux { - function = "pcie"; - groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", - "pcie_wake_n3_0"; - }; - }; -}; - -&spi0 { - status = "disabled"; -}; - -&uart0 { - status = "okay"; -}; - -&watchdog { - status = "okay"; -}; - -&xphy { - status = "okay"; -}; diff --git a/6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi deleted file mode 100644 index 13ad3950..00000000 --- a/6.1/target/linux/mediatek/files-6.1/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ /dev/null @@ -1,853 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2023 MediaTek Inc. - * Author: Sam.Shih - */ - -#include -#include -#include -#include -#include -#include -#include - -/ { - compatible = "mediatek,mt7988"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - clk40m: oscillator@0 { - compatible = "fixed-clock"; - clock-frequency = <40000000>; - #clock-cells = <0>; - clock-output-names = "clkxtal"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu0: cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - enable-method = "psci"; - reg = <0x0>; - clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - mediatek,cci = <&cci>; - }; - - cpu1: cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - enable-method = "psci"; - reg = <0x1>; - clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - mediatek,cci = <&cci>; - }; - - cpu2: cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - enable-method = "psci"; - reg = <0x2>; - clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - mediatek,cci = <&cci>; - }; - - cpu3: cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a73"; - enable-method = "psci"; - reg = <0x3>; - clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cpu", "intermediate"; - operating-points-v2 = <&cluster0_opp>; - mediatek,cci = <&cci>; - }; - - cluster0_opp: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - opp00 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <850000>; - }; - opp01 { - opp-hz = /bits/ 64 <1100000000>; - opp-microvolt = <850000>; - }; - opp02 { - opp-hz = /bits/ 64 <1500000000>; - opp-microvolt = <850000>; - }; - opp03 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <900000>; - }; - }; - }; - - cci: cci { - compatible = "mediatek,mt7988-cci", - "mediatek,mt8183-cci"; - clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, - <&topckgen CLK_TOP_XTAL>; - clock-names = "cci", "intermediate"; - operating-points-v2 = <&cci_opp>; - }; - - cci_opp: opp_table_cci { - compatible = "operating-points-v2"; - opp-shared; - opp00 { - opp-hz = /bits/ 64 <480000000>; - opp-microvolt = <850000>; - }; - opp01 { - opp-hz = /bits/ 64 <660000000>; - opp-microvolt = <850000>; - }; - opp02 { - opp-hz = /bits/ 64 <900000000>; - opp-microvolt = <850000>; - }; - opp03 { - opp-hz = /bits/ 64 <1080000000>; - opp-microvolt = <900000>; - }; - }; - - pmu { - compatible = "arm,cortex-a73-pmu"; - interrupt-parent = <&gic>; - interrupt = ; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x30000>; - no-map; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&gic>; - interrupts = , - , - , - ; - }; - - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - - gic: interrupt-controller@c000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - interrupt-controller; - reg = <0 0x0c000000 0 0x40000>, /* GICD */ - <0 0x0c080000 0 0x200000>, /* GICR */ - <0 0x0c400000 0 0x2000>, /* GICC */ - <0 0x0c410000 0 0x1000>, /* GICH */ - <0 0x0c420000 0 0x2000>; /* GICV */ - - interrupts = ; - }; - - phyfw: phy-firmware@f000000 { - compatible = "mediatek,2p5gphy-fw"; - reg = <0 0x0f000000 0 0x8000>, - <0 0x0f100000 0 0x20000>, - <0 0x0f0f0000 0 0x200>; - }; - - infracfg: infracfg@10001000 { - compatible = "mediatek,mt7988-infracfg", "syscon"; - reg = <0 0x10001000 0 0x1000>; - #clock-cells = <1>; - }; - - topckgen: topckgen@1001b000 { - compatible = "mediatek,mt7988-topckgen", "syscon"; - reg = <0 0x1001b000 0 0x1000>; - #clock-cells = <1>; - }; - - watchdog: watchdog@1001c000 { - compatible = "mediatek,mt7988-wdt", - "mediatek,mt6589-wdt", - "syscon"; - reg = <0 0x1001c000 0 0x1000>; - interrupts = ; - #reset-cells = <1>; - }; - - apmixedsys: apmixedsys@1001e000 { - compatible = "mediatek,mt7988-apmixedsys"; - reg = <0 0x1001e000 0 0x1000>; - #clock-cells = <1>; - }; - - pio: pinctrl@1001f000 { - compatible = "mediatek,mt7988-pinctrl"; - reg = <0 0x1001f000 0 0x1000>, - <0 0x11c10000 0 0x1000>, - <0 0x11d00000 0 0x1000>, - <0 0x11d20000 0 0x1000>, - <0 0x11e00000 0 0x1000>, - <0 0x11f00000 0 0x1000>, - <0 0x1000b000 0 0x1000>; - reg-names = "gpio_base", "iocfg_tr_base", - "iocfg_br_base", "iocfg_rb_base", - "iocfg_lb_base", "iocfg_tl_base", "eint"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pio 0 0 83>; - interrupt-controller; - interrupts = ; - interrupt-parent = <&gic>; - #interrupt-cells = <2>; - - mdio0_pins: mdio0-pins { - mux { - function = "eth"; - groups = "mdc_mdio0"; - }; - - conf { - groups = "mdc_mdio0"; - drive-strength = ; - }; - }; - - i2c0_pins: i2c0-pins-g0 { - mux { - function = "i2c"; - groups = "i2c0_1"; - }; - }; - - i2c1_pins: i2c1-pins-g0 { - mux { - function = "i2c"; - groups = "i2c1_0"; - }; - }; - - i2c2_pins: i2c2-pins-g0 { - mux { - function = "i2c"; - groups = "i2c2_1"; - }; - }; - - gbe0_led0_pins: gbe0-pins { - mux { - function = "led"; - groups = "gbe0_led0"; - }; - }; - - gbe1_led0_pins: gbe1-pins { - mux { - function = "led"; - groups = "gbe1_led0"; - }; - }; - - gbe2_led0_pins: gbe2-pins { - mux { - function = "led"; - groups = "gbe2_led0"; - }; - }; - - gbe3_led0_pins: gbe3-pins { - mux { - function = "led"; - groups = "gbe3_led0"; - }; - }; - - i2p5gbe_led0_pins: 2p5gbe-pins { - mux { - function = "led"; - groups = "2p5gbe_led0"; - }; - }; - }; - - boottrap: boottrap@1001f6f0 { - compatible = "mediatek,boottrap"; - reg = <0 0x1001f6f0 0 0x4>; - }; - - sgmiisys0: syscon@10060000 { - compatible = "mediatek,mt7988-sgmiisys", - "mediatek,mt7988-sgmiisys_0", - "syscon"; - reg = <0 0x10060000 0 0x1000>; - #clock-cells = <1>; - }; - - sgmiisys1: syscon@10070000 { - compatible = "mediatek,mt7988-sgmiisys", - "mediatek,mt7988-sgmiisys_1", - "syscon"; - reg = <0 0x10070000 0 0x1000>; - #clock-cells = <1>; - }; - - usxgmiisys0: usxgmiisys@10080000 { - compatible = "mediatek,mt7988-usxgmiisys", - "mediatek,mt7988-usxgmiisys_0", - "syscon"; - reg = <0 0x10080000 0 0x1000>; - #clock-cells = <1>; - }; - - usxgmiisys1: usxgmiisys@10081000 { - compatible = "mediatek,mt7988-usxgmiisys", - "mediatek,mt7988-usxgmiisys_1", - "syscon"; - reg = <0 0x10081000 0 0x1000>; - #clock-cells = <1>; - }; - - xfi_pextp0: xfi_pextp@11f20000 { - compatible = "mediatek,mt7988-xfi_pextp", - "mediatek,mt7988-xfi_pextp_0", - "syscon"; - reg = <0 0x11f20000 0 0x10000>; - #clock-cells = <1>; - }; - - xfi_pextp1: xfi_pextp@11f30000 { - compatible = "mediatek,mt7988-xfi_pextp", - "mediatek,mt7988-xfi_pextp_1", - "syscon"; - reg = <0 0x11f30000 0 0x10000>; - #clock-cells = <1>; - }; - - xfi_pll: xfi_pll@11f40000 { - compatible = "mediatek,mt7988-xfi_pll", "syscon"; - reg = <0 0x11f40000 0 0x1000>; - #clock-cells = <1>; - }; - - mcusys: mcusys@100e0000 { - compatible = "mediatek,mt7988-mcusys", "syscon"; - reg = <0 0x100e0000 0 0x1000>; - #clock-cells = <1>; - }; - - uart0: serial@11000000 { - compatible = "mediatek,mt7986-uart", - "mediatek,mt6577-uart"; - reg = <0 0x11000000 0 0x100>; - interrupts = ; - /* - * 8250-mtk driver don't control "baud" clock since commit - * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks - * still need to be passed to the driver to prevent probe fail - */ - clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_52M_UART0_CK>; - clock-names = "baud", "bus"; - assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, - <&infracfg CLK_INFRA_MUX_UART0_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, - <&topckgen CLK_TOP_UART_SEL>; - status = "disabled"; - }; - - i2c0: i2c@11003000 { - compatible = "mediatek,mt7988-i2c", - "mediatek,mt7981-i2c"; - reg = <0 0x11003000 0 0x1000>, - <0 0x10217080 0 0x80>; - interrupts = ; - clock-div = <1>; - clocks = <&infracfg CLK_INFRA_I2C_BCK>, - <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@11004000 { - compatible = "mediatek,mt7988-i2c", - "mediatek,mt7981-i2c"; - reg = <0 0x11004000 0 0x1000>, - <0 0x10217100 0 0x80>; - interrupts = ; - clock-div = <1>; - clocks = <&infracfg CLK_INFRA_I2C_BCK>, - <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@11005000 { - compatible = "mediatek,mt7988-i2c", - "mediatek,mt7981-i2c"; - reg = <0 0x11005000 0 0x1000>, - <0 0x10217180 0 0x80>; - interrupts = ; - clock-div = <1>; - clocks = <&infracfg CLK_INFRA_I2C_BCK>, - <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; - clock-names = "main", "dma"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - spi0: spi@11007000 { - compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm"; - reg = <0 0x11007000 0 0x100>; - interrupts = ; - clocks = <&topckgen CLK_TOP_MPLL_D2>, - <&topckgen CLK_TOP_SPI_SEL>, - <&infracfg CLK_INFRA_104M_SPI0>, - <&infracfg CLK_INFRA_66M_SPI0_HCK>; - clock-names = "parent-clk", "sel-clk", "spi-clk", - "spi-hclk"; - - #address-cells = <1>; - #size-cells = <0>; - - status = "disabled"; - }; - - pcie2: pcie@11280000 { - compatible = "mediatek,mt7988-pcie", - "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - reg = <0 0x11280000 0 0x2000>; - reg-names = "pcie-mac"; - linux,pci-domain = <3>; - interrupts = ; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0x00 0x20000000 0x00 - 0x20000000 0x00 0x00200000>, - <0x82000000 0x00 0x20200000 0x00 - 0x20200000 0x00 0x07e00000>; - clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>, - <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>, - <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>, - <&infracfg CLK_INFRA_133M_PCIE_CK_P2>; - clock-names = "pl_250m", "tl_26m", "peri_26m", - "top_133m"; - status = "disabled"; - - phys = <&xphyu3port0 PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc2 0>, - <0 0 0 2 &pcie_intc2 1>, - <0 0 0 3 &pcie_intc2 2>, - <0 0 0 4 &pcie_intc2 3>; - pcie_intc2: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - pcie3: pcie@11290000 { - compatible = "mediatek,mt7988-pcie", - "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - reg = <0 0x11290000 0 0x2000>; - reg-names = "pcie-mac"; - linux,pci-domain = <2>; - interrupts = ; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0x00 0x28000000 0x00 - 0x28000000 0x00 0x00200000>, - <0x82000000 0x00 0x28200000 0x00 - 0x28200000 0x00 0x07e00000>; - clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>, - <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>, - <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>, - <&infracfg CLK_INFRA_133M_PCIE_CK_P3>; - clock-names = "pl_250m", "tl_26m", "peri_26m", - "top_133m"; - status = "disabled"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc3 0>, - <0 0 0 2 &pcie_intc3 1>, - <0 0 0 3 &pcie_intc3 2>, - <0 0 0 4 &pcie_intc3 3>; - pcie_intc3: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - pcie0: pcie@11300000 { - compatible = "mediatek,mt7988-pcie", - "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - reg = <0 0x11300000 0 0x2000>; - reg-names = "pcie-mac"; - linux,pci-domain = <0>; - interrupts = ; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0x00 0x30000000 0x00 - 0x30000000 0x00 0x00200000>, - <0x82000000 0x00 0x30200000 0x00 - 0x30200000 0x00 0x07e00000>; - clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>, - <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>, - <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>, - <&infracfg CLK_INFRA_133M_PCIE_CK_P0>; - clock-names = "pl_250m", "tl_26m", "peri_26m", - "top_133m"; - status = "disabled"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc0 0>, - <0 0 0 2 &pcie_intc0 1>, - <0 0 0 3 &pcie_intc0 2>, - <0 0 0 4 &pcie_intc0 3>; - pcie_intc0: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - pcie1: pcie@11310000 { - compatible = "mediatek,mt7988-pcie", - "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - reg = <0 0x11310000 0 0x2000>; - reg-names = "pcie-mac"; - linux,pci-domain = <1>; - interrupts = ; - bus-range = <0x00 0xff>; - ranges = <0x81000000 0x00 0x38000000 0x00 - 0x38000000 0x00 0x00200000>, - <0x82000000 0x00 0x38200000 0x00 - 0x38200000 0x00 0x07e00000>; - clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>, - <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>, - <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>, - <&infracfg CLK_INFRA_133M_PCIE_CK_P1>; - clock-names = "pl_250m", "tl_26m", "peri_26m", - "top_133m"; - status = "disabled"; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &pcie_intc1 0>, - <0 0 0 2 &pcie_intc1 1>, - <0 0 0 3 &pcie_intc1 2>, - <0 0 0 4 &pcie_intc1 3>; - pcie_intc1: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - ssusb0: usb@11190000 { - compatible = "mediatek,mt7988-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x11190000 0 0x2e00>, - <0 0x11193e00 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - phys = <&xphyu2port0 PHY_TYPE_USB2>, - <&xphyu3port0 PHY_TYPE_USB3>; - clocks = <&infracfg CLK_INFRA_USB_SYS>, - <&infracfg CLK_INFRA_USB_XHCI>, - <&infracfg CLK_INFRA_USB_REF>, - <&infracfg CLK_INFRA_66M_USB_HCK>, - <&infracfg CLK_INFRA_133M_USB_HCK>; - clock-names = "sys_ck", - "xhci_ck", - "ref_ck", - "mcu_ck", - "dma_ck"; - #address-cells = <2>; - #size-cells = <2>; - mediatek,p0_speed_fixup; - status = "disabled"; - }; - - ssusb1: usb@11200000 { - compatible = "mediatek,mt7988-xhci", - "mediatek,mtk-xhci"; - reg = <0 0x11200000 0 0x2e00>, - <0 0x11203e00 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - phys = <&tphyu2port0 PHY_TYPE_USB2>, - <&tphyu3port0 PHY_TYPE_USB3>; - clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>, - <&infracfg CLK_INFRA_USB_XHCI_CK_P1>, - <&infracfg CLK_INFRA_USB_CK_P1>, - <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>, - <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>; - clock-names = "sys_ck", - "xhci_ck", - "ref_ck", - "mcu_ck", - "dma_ck"; - #address-cells = <2>; - #size-cells = <2>; - status = "disabled"; - }; - - tphy: tphy@11c50000 { - compatible = "mediatek,mt7988", - "mediatek,generic-tphy-v2"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - tphyu2port0: usb-phy@11c50000 { - reg = <0 0x11c50000 0 0x700>; - clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>; - clock-names = "ref"; - #phy-cells = <1>; - }; - tphyu3port0: usb-phy@11c50700 { - reg = <0 0x11c50700 0 0x900>; - clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>; - clock-names = "ref"; - #phy-cells = <1>; - mediatek,usb3-pll-ssc-delta; - mediatek,usb3-pll-ssc-delta1; - }; - }; - - topmisc: topmisc@11d10000 { - compatible = "mediatek,mt7988-topmisc", "syscon", - "mediatek,mt7988-power-controller"; - reg = <0 0x11d10000 0 0x10000>; - #clock-cells = <1>; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - - xphy: xphy@11e10000 { - compatible = "mediatek,mt7988", - "mediatek,xsphy"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - status = "disabled"; - - xphyu2port0: usb-phy@11e10000 { - reg = <0 0x11e10000 0 0x400>; - clocks = <&infracfg CLK_INFRA_USB_UTMI>; - clock-names = "ref"; - #phy-cells = <1>; - }; - - xphyu3port0: usb-phy@11e13000 { - reg = <0 0x11e13400 0 0x500>; - clocks = <&infracfg CLK_INFRA_USB_PIPE>; - clock-names = "ref"; - #phy-cells = <1>; - mediatek,syscon-type = <&topmisc 0x218 0>; - }; - }; - - efuse: efuse@11f50000 { - compatible = "mediatek,efuse"; - reg = <0 0x11f50000 0 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - lvts_calibration: calib@918 { - reg = <0x918 0x28>; - }; - phy_calibration_p0: calib@940 { - reg = <0x940 0x10>; - }; - phy_calibration_p1: calib@954 { - reg = <0x954 0x10>; - }; - phy_calibration_p2: calib@968 { - reg = <0x968 0x10>; - }; - phy_calibration_p3: calib@97c { - reg = <0x97c 0x10>; - }; - cpufreq_calibration: calib@278 { - reg = <0x278 0x1>; - }; - }; - - ethsys: syscon@15000000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mediatek,mt7988-ethsys", "syscon"; - reg = <0 0x15000000 0 0x1000>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - - switch: switch@15020000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mediatek,mt7988-switch"; - reg = <0 0x15020000 0 0x8000>; - interrupt-controller; - #interrupt-cells = <1>; - interrupt-parent = <&gic>; - interrupts = ; - resets = <ðrst 0>; - }; - - ethwarp: syscon@15031000 { - compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd"; - reg = <0 0x15031000 0 0x1000>; - #clock-cells = <1>; - - ethrst: reset-controller { - compatible = "ti,syscon-reset"; - #reset-cells = <1>; - ti,reset-bits = < - 0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE) - >; - }; - }; - - eth: ethernet@15100000 { - compatible = "mediatek,mt7988-eth"; - reg = <0 0x15100000 0 0x80000>, - <0 0x15400000 0 0x380000>; - interrupts = , - , - , - ; - clocks = <ðsys CLK_ETHDMA_XGP1_EN>, - <ðsys CLK_ETHDMA_XGP2_EN>, - <ðsys CLK_ETHDMA_XGP3_EN>, - <ðsys CLK_ETHDMA_FE_EN>, - <ðsys CLK_ETHDMA_GP2_EN>, - <ðsys CLK_ETHDMA_GP1_EN>, - <ðsys CLK_ETHDMA_GP3_EN>, - <ðsys CLK_ETHDMA_ESW_EN>, - <ðsys CLK_ETHDMA_CRYPT0_EN>, - <&sgmiisys0 CLK_SGM0_TX_EN>, - <&sgmiisys0 CLK_SGM0_RX_EN>, - <&sgmiisys1 CLK_SGM1_TX_EN>, - <&sgmiisys1 CLK_SGM1_RX_EN>, - <ðwarp CLK_ETHWARP_WOCPU2_EN>, - <ðwarp CLK_ETHWARP_WOCPU1_EN>, - <ðwarp CLK_ETHWARP_WOCPU0_EN>, - <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, - <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>, - <&topckgen CLK_TOP_SGM_0_SEL>, - <&topckgen CLK_TOP_SGM_1_SEL>, - <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>, - <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>, - <&topckgen CLK_TOP_ETH_GMII_SEL>, - <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>, - <&topckgen CLK_TOP_ETH_SYS_200M_SEL>, - <&topckgen CLK_TOP_ETH_SYS_SEL>, - <&topckgen CLK_TOP_ETH_XGMII_SEL>, - <&topckgen CLK_TOP_ETH_MII_SEL>, - <&topckgen CLK_TOP_NETSYS_SEL>, - <&topckgen CLK_TOP_NETSYS_500M_SEL>, - <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>, - <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>, - <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>, - <&topckgen CLK_TOP_NETSYS_WARP_SEL>; - clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1", - "gp3", "esw", "crypto", "sgmii_tx250m", - "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m", - "ethwarp_wocpu2", "ethwarp_wocpu1", - "ethwarp_wocpu0", "top_usxgmii0_sel", - "top_usxgmii1_sel", "top_sgm0_sel", - "top_sgm1_sel", "top_xfi_phy0_xtal_sel", - "top_xfi_phy1_xtal_sel", "top_eth_gmii_sel", - "top_eth_refck_50m_sel", "top_eth_sys_200m_sel", - "top_eth_sys_sel", "top_eth_xgmii_sel", - "top_eth_mii_sel", "top_netsys_sel", - "top_netsys_500m_sel", "top_netsys_pao_2x_sel", - "top_netsys_sync_250m_sel", - "top_netsys_ppefb_250m_sel", - "top_netsys_warp_sel"; - assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, - <&topckgen CLK_TOP_NETSYS_GSW_SEL>, - <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, - <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>, - <&topckgen CLK_TOP_SGM_0_SEL>, - <&topckgen CLK_TOP_SGM_1_SEL>; - assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, - <&topckgen CLK_TOP_NET1PLL_D4>, - <&topckgen CLK_TOP_NET1PLL_D8_D4>, - <&topckgen CLK_TOP_NET1PLL_D8_D4>, - <&apmixedsys CLK_APMIXED_SGMPLL>, - <&apmixedsys CLK_APMIXED_SGMPLL>; - mediatek,ethsys = <ðsys>; - mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; - mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>; - mediatek,xfi_pextp = <&xfi_pextp0>, <&xfi_pextp1>; - mediatek,xfi_pll = <&xfi_pll>; - mediatek,infracfg = <&topmisc>; - mediatek,toprgu = <&watchdog>; - #reset-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - }; -}; diff --git a/6.1/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-apmixed.c b/6.1/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-apmixed.c deleted file mode 100644 index 3f1edc23..00000000 --- a/6.1/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-apmixed.c +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2023 MediaTek Inc. - * Author: Sam Shih - * Author: Xiufeng Li - */ - -#include -#include -#include -#include -#include -#include "clk-mtk.h" -#include "clk-gate.h" -#include "clk-mux.h" -#include "clk-pll.h" -#include - -#define MT7988_PLL_FMAX (2500UL * MHZ) -#define MT7988_PCW_CHG_SHIFT 2 - -#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \ - _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ - _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, \ - _div_table) \ - { \ - .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \ - .en_mask = _en_mask, .flags = _flags, \ - .rst_bar_mask = BIT(_rst_bar_mask), .fmax = MT7988_PLL_FMAX, \ - .pcwbits = _pcwbits, .pd_reg = _pd_reg, \ - .pd_shift = _pd_shift, .tuner_reg = _tuner_reg, \ - .tuner_en_reg = _tuner_en_reg, .tuner_en_bit = _tuner_en_bit, \ - .pcw_reg = _pcw_reg, .pcw_shift = _pcw_shift, \ - .pcw_chg_reg = _pcw_chg_reg, \ - .pcw_chg_shift = MT7988_PCW_CHG_SHIFT, \ - .div_table = _div_table, .parent_name = "clkxtal", \ - } - -#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \ - _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ - _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg) \ - PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \ - _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \ - _tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, NULL) - -static const struct mtk_pll_data plls[] = { - PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0, - 0, 32, 0x0104, 4, 0, 0, 0, 0x0108, 0, 0x0104), - PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR, - 23, 32, 0x0114, 4, 0, 0, 0, 0x0118, 0, 0x0114), - PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001, - HAVE_RST_BAR, 23, 32, 0x0124, 4, 0, 0, 0, 0x0128, 0, 0x0124), - PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32, - 0x0134, 4, 0x0704, 0x0700, 1, 0x0138, 0, 0x0134), - PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001, - HAVE_RST_BAR, 23, 32, 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144), - PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001, - (HAVE_RST_BAR | PLL_AO), 23, 32, 0x0154, 4, 0, 0, 0, 0x0158, 0, - 0x0154), - PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0, - 0, 32, 0x0164, 4, 0, 0, 0, 0x0168, 0, 0x0164), - PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32, - 0x0174, 4, 0, 0, 0, 0x0178, 0, 0x0174), - PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001, - (HAVE_RST_BAR | PLL_AO), 23, 32, 0x0204, 4, 0, 0, 0, 0x0208, 0, - 0x0204), - PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001, - HAVE_RST_BAR, 23, 32, 0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214), - PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001, - HAVE_RST_BAR, 23, 32, 0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304), - PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0, - 32, 0x0314, 4, 0, 0, 0, 0x0318, 0, 0x0314), -}; - -static const struct of_device_id of_match_clk_mt7988_apmixed[] = { - { .compatible = "mediatek,mt7988-apmixedsys", }, - { /* sentinel */ } -}; - -static int clk_mt7988_apmixed_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls)); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_apmixed_data; - } - return r; - -free_apmixed_data: - mtk_free_clk_data(clk_data); - return r; -} - -static struct platform_driver clk_mt7988_apmixed_drv = { - .probe = clk_mt7988_apmixed_probe, - .driver = { - .name = "clk-mt7988-apmixed", - .of_match_table = of_match_clk_mt7988_apmixed, - }, -}; -builtin_platform_driver(clk_mt7988_apmixed_drv); -MODULE_LICENSE("GPL"); diff --git a/6.1/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-eth.c b/6.1/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-eth.c deleted file mode 100644 index 14b877f8..00000000 --- a/6.1/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-eth.c +++ /dev/null @@ -1,141 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2023 MediaTek Inc. - * Author: Sam Shih - * Author: Xiufeng Li - */ - -#include -#include -#include -#include -#include -#include "clk-mtk.h" -#include "clk-gate.h" -#include - -static const struct mtk_gate_regs ethdma_cg_regs = { - .set_ofs = 0x30, - .clr_ofs = 0x30, - .sta_ofs = 0x30, -}; - -#define GATE_ETHDMA(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = ðdma_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate ethdma_clks[] = { - GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0), - GATE_ETHDMA(CLK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "top_xtal", 1), - GATE_ETHDMA(CLK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "top_xtal", 2), - GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6), - GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "top_xtal", 7), - GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "top_xtal", 8), - GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "top_xtal", 10), - GATE_ETHDMA(CLK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw_sel", 16), - GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197_sel", - 29), -}; - -static const struct mtk_clk_desc ethdma_desc = { - .clks = ethdma_clks, - .num_clks = ARRAY_SIZE(ethdma_clks), -}; - -static const struct mtk_gate_regs sgmii0_cg_regs = { - .set_ofs = 0xe4, - .clr_ofs = 0xe4, - .sta_ofs = 0xe4, -}; - -#define GATE_SGMII0(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &sgmii0_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate sgmii0_clks[] = { - GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "top_xtal", 2), - GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3), -}; - -static const struct mtk_clk_desc sgmii0_desc = { - .clks = sgmii0_clks, - .num_clks = ARRAY_SIZE(sgmii0_clks), -}; - -static const struct mtk_gate_regs sgmii1_cg_regs = { - .set_ofs = 0xe4, - .clr_ofs = 0xe4, - .sta_ofs = 0xe4, -}; - -#define GATE_SGMII1(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &sgmii1_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate sgmii1_clks[] = { - GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "top_xtal", 2), - GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3), -}; - -static const struct mtk_clk_desc sgmii1_desc = { - .clks = sgmii1_clks, - .num_clks = ARRAY_SIZE(sgmii1_clks), -}; - -static const struct mtk_gate_regs ethwarp_cg_regs = { - .set_ofs = 0x14, - .clr_ofs = 0x14, - .sta_ofs = 0x14, -}; - -#define GATE_ETHWARP(_id, _name, _parent, _shift) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = ðwarp_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_no_setclr_inv, \ - } - -static const struct mtk_gate ethwarp_clks[] = { - GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en", - "netsys_mcu_sel", 13), - GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en", - "netsys_mcu_sel", 14), - GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en", - "netsys_mcu_sel", 15), -}; - -static const struct mtk_clk_desc ethwarp_desc = { - .clks = ethwarp_clks, - .num_clks = ARRAY_SIZE(ethwarp_clks), -}; - -static const struct of_device_id of_match_clk_mt7986_eth[] = { - { .compatible = "mediatek,mt7988-ethsys", .data = ðdma_desc }, - { .compatible = "mediatek,mt7988-sgmiisys_0", .data = &sgmii0_desc }, - { .compatible = "mediatek,mt7988-sgmiisys_1", .data = &sgmii1_desc }, - { .compatible = "mediatek,mt7988-ethwarp", .data = ðwarp_desc }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_eth); - -static struct platform_driver clk_mt7988_eth_drv = { - .driver = { - .name = "clk-mt7988-eth", - .of_match_table = of_match_clk_mt7986_eth, - }, - .probe = mtk_clk_simple_probe, - .remove = mtk_clk_simple_remove, -}; -module_platform_driver(clk_mt7988_eth_drv); - -MODULE_DESCRIPTION("MediaTek MT7988 Ethernet clocks driver"); -MODULE_LICENSE("GPL"); diff --git a/6.1/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c b/6.1/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c deleted file mode 100644 index 111b516a..00000000 --- a/6.1/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-infracfg.c +++ /dev/null @@ -1,369 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2023 MediaTek Inc. - * Author: Sam Shih - * Author: Xiufeng Li - */ - -#include -#include -#include -#include -#include -#include "clk-mtk.h" -#include "clk-gate.h" -#include "clk-mux.h" -#include - -static DEFINE_SPINLOCK(mt7988_clk_lock); - -static const char *const infra_mux_uart0_parents[] __initconst = { - "csw_infra_f26m_sel", "uart_sel" -}; - -static const char *const infra_mux_uart1_parents[] __initconst = { - "csw_infra_f26m_sel", "uart_sel" -}; - -static const char *const infra_mux_uart2_parents[] __initconst = { - "csw_infra_f26m_sel", "uart_sel" -}; - -static const char *const infra_mux_spi0_parents[] __initconst = { "i2c_sel", - "spi_sel" }; - -static const char *const infra_mux_spi1_parents[] __initconst = { - "i2c_sel", "spim_mst_sel" -}; - -static const char *const infra_pwm_bck_parents[] __initconst = { - "top_rtc_32p7k", "csw_infra_f26m_sel", "sysaxi_sel", "pwm_sel" -}; - -static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = { - "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", - "pextp_tl_sel" -}; - -static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = { - "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", - "pextp_tl_p1_sel" -}; - -static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = { - "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", - "pextp_tl_p2_sel" -}; - -static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = { - "top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel", - "pextp_tl_p3_sel" -}; - -static const struct mtk_mux infra_muxes[] = { - /* MODULE_CLK_SEL_0 */ - MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel", - infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, - 0, 1, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel", - infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, - 1, 1, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel", - infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, - 2, 1, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", - infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 4, - 1, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", - infra_mux_spi1_parents, 0x0018, 0x0010, 0x0014, 5, - 1, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", - infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 6, - 1, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 14, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 16, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 18, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 20, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 22, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 24, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 26, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 28, - 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", - infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 30, - 2, -1, -1, -1), - /* MODULE_CLK_SEL_1 */ - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, - "infra_pcie_gfmux_tl_o_p0_sel", - infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028, - 0x0020, 0x0024, 0, 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, - "infra_pcie_gfmux_tl_o_p1_sel", - infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028, - 0x0020, 0x0024, 2, 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, - "infra_pcie_gfmux_tl_o_p2_sel", - infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028, - 0x0020, 0x0024, 4, 2, -1, -1, -1), - MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, - "infra_pcie_gfmux_tl_o_p3_sel", - infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028, - 0x0020, 0x0024, 6, 2, -1, -1, -1), -}; - -static const struct mtk_gate_regs infra0_cg_regs = { - .set_ofs = 0x10, - .clr_ofs = 0x14, - .sta_ofs = 0x18, -}; - -static const struct mtk_gate_regs infra1_cg_regs = { - .set_ofs = 0x40, - .clr_ofs = 0x44, - .sta_ofs = 0x48, -}; - -static const struct mtk_gate_regs infra2_cg_regs = { - .set_ofs = 0x50, - .clr_ofs = 0x54, - .sta_ofs = 0x58, -}; - -static const struct mtk_gate_regs infra3_cg_regs = { - .set_ofs = 0x60, - .clr_ofs = 0x64, - .sta_ofs = 0x68, -}; - -#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra0_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \ - } - -#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra1_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \ - } - -#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra2_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \ - } - -#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags) \ - { \ - .id = _id, .name = _name, .parent_name = _parent, \ - .regs = &infra3_cg_regs, .shift = _shift, \ - .ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \ - } - -#define GATE_INFRA0(_id, _name, _parent, _shift) \ - GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0) - -#define GATE_INFRA1(_id, _name, _parent, _shift) \ - GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0) - -#define GATE_INFRA2(_id, _name, _parent, _shift) \ - GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0) - -#define GATE_INFRA3(_id, _name, _parent, _shift) \ - GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0) - -static const struct mtk_gate infra_clks[] = { - /* INFRA0 */ - GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0, - "infra_pcie_peri_ck_26m_ck_p0", "csw_infra_f26m_sel", 7), - GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, - "infra_pcie_peri_ck_26m_ck_p1", "csw_infra_f26m_sel", 8), - GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, - "infra_pcie_peri_ck_26m_ck_p2", "csw_infra_f26m_sel", 9), - GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, - "infra_pcie_peri_ck_26m_ck_p3", "csw_infra_f26m_sel", 10), - /* INFRA1 */ - GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck", - "sysaxi_sel", 0), - GATE_INFRA1(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck", - "sysaxi_sel", 1), - GATE_INFRA1(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck", - "infra_pwm_sel", 2), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1", - "infra_pwm_ck1_sel", 3), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2", - "infra_pwm_ck2_sel", 4), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3", - "infra_pwm_ck3_sel", 5), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4", - "infra_pwm_ck4_sel", 6), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5", - "infra_pwm_ck5_sel", 7), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6", - "infra_pwm_ck6_sel", 8), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7", - "infra_pwm_ck7_sel", 9), - GATE_INFRA1(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8", - "infra_pwm_ck8_sel", 10), - GATE_INFRA1(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck", - "sysaxi_sel", 12), - GATE_INFRA1(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck", - "sysaxi_sel", 13), - GATE_INFRA1(CLK_INFRA_AUD_26M, "infra_f_faud_26m", - "csw_infra_f26m_sel", 14), - GATE_INFRA1(CLK_INFRA_AUD_L, "infra_f_faud_l", "aud_l_sel", 15), - GATE_INFRA1(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", "a1sys_sel", 16), - GATE_INFRA1(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", "a_tuner_sel", 18), - GATE_INFRA1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", - "csw_infra_f26m_sel", 19, CLK_IS_CRITICAL), - // JTAG - GATE_INFRA1_FLAGS(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm", - "sysaxi_sel", 20, CLK_IS_CRITICAL), - GATE_INFRA1(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck", - "sysaxi_sel", 21), - GATE_INFRA1(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck", - "sysaxi_sel", 29), - GATE_INFRA1(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m", - "csw_infra_f26m_sel", 30), - /* INFRA2 */ - GATE_INFRA2(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system", - "csw_infra_f26m_sel", 0), - GATE_INFRA2(CLK_INFRA_I2C_BCK, "infra_i2c_bck", "i2c_sel", 1), - GATE_INFRA2(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0", - "infra_mux_uart0_sel", 3), - GATE_INFRA2(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1", - "infra_mux_uart1_sel", 4), - GATE_INFRA2(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2", - "infra_mux_uart2_sel", 5), - GATE_INFRA2(CLK_INFRA_NFI, "infra_f_fnfi", "nfi1x_sel", 9), - GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10), - GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck", - "sysaxi_sel", 11, CLK_IS_CRITICAL), - GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0", - "infra_mux_spi0_sel", 12, CLK_IS_CRITICAL), - GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1", - "infra_mux_spi1_sel", 13), - GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck", - "infra_mux_spi2_sel", 14), - GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck", - "sysaxi_sel", 15, CLK_IS_CRITICAL), - GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck", - "sysaxi_sel", 16), - GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck", - "sysaxi_sel", 17), - GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi", - "sysaxi_sel", 18), - GATE_INFRA2(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", 19), - GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck", - "csw_infra_f26m_sel", 20), - GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck", - 21), - GATE_INFRA2(CLK_INFRA_MSDC400, "infra_f_fmsdc400", "emmc_400m_sel", - 22), - GATE_INFRA2(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", "emmc_250m_sel", - 23), - GATE_INFRA2(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck", - "sysaxi_sel", 24), - GATE_INFRA2(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck", - "sysaxi_sel", 25), - GATE_INFRA2(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck", - "sysaxi_sel", 26), - GATE_INFRA2(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "nfi1x_sel", 27), - GATE_INFRA2(CLK_INFRA_I2C_X16W_MCK_CK_P1, - "infra_hf_i2c_x16w_mck_ck_p1", "sysaxi_sel", 29), - GATE_INFRA2(CLK_INFRA_I2C_X16W_PCK_CK_P1, - "infra_hf_i2c_x16w_pck_ck_p1", "sysaxi_sel", 31), - /* INFRA3 */ - GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel", - 0), - GATE_INFRA3(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1", - "sysaxi_sel", 1), - GATE_INFRA3(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "sysaxi_sel", - 2), - GATE_INFRA3(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1", - "sysaxi_sel", 3), - GATE_INFRA3(CLK_INFRA_USB_SYS, "infra_usb_sys", "usb_sys_sel", 4), - GATE_INFRA3(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1", - "usb_sys_p1_sel", 5), - GATE_INFRA3(CLK_INFRA_USB_REF, "infra_usb_ref", "top_xtal", 6), - GATE_INFRA3(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "top_xtal", 7), - GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt", - "usb_frmcnt_sel", 8, CLK_IS_CRITICAL), - GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1", - "usb_frmcnt_p1_sel", 9, CLK_IS_CRITICAL), - GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10), - GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1", - "usb_phy_sel", 11), - GATE_INFRA3(CLK_INFRA_USB_UTMI, "infra_usb_utmi", "top_xtal", 12), - GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1", - "top_xtal", 13), - GATE_INFRA3(CLK_INFRA_USB_XHCI, "infra_usb_xhci", "usb_xhci_sel", 14), - GATE_INFRA3(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1", - "usb_xhci_p1_sel", 15), - GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0", - "infra_pcie_gfmux_tl_o_p0_sel", 20), - GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1", - "infra_pcie_gfmux_tl_o_p1_sel", 21), - GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2", - "infra_pcie_gfmux_tl_o_p2_sel", 22), - GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3", - "infra_pcie_gfmux_tl_o_p3_sel", 23), - GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0", - "top_xtal", 24), - GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1", - "top_xtal", 25), - GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2", - "top_xtal", 26), - GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3", - "top_xtal", 27), - GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0", - "sysaxi_sel", 28), - GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1", - "sysaxi_sel", 29), - GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2", - "sysaxi_sel", 30), - GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", - "sysaxi_sel", 31), -}; - -static const struct mtk_clk_desc infra_desc = { - .clks = infra_clks, - .num_clks = ARRAY_SIZE(infra_clks), - .mux_clks = infra_muxes, - .num_mux_clks = ARRAY_SIZE(infra_muxes), - .clk_lock = &mt7988_clk_lock, -}; - -static const struct of_device_id of_match_clk_mt7988_infracfg[] = { - { .compatible = "mediatek,mt7988-infracfg", .data = &infra_desc }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_infracfg); - -static struct platform_driver clk_mt7988_infracfg_drv = { - .driver = { - .name = "clk-mt7988-infracfg", - .of_match_table = of_match_clk_mt7988_infracfg, - }, - .probe = mtk_clk_simple_probe, - .remove = mtk_clk_simple_remove, -}; -module_platform_driver(clk_mt7988_infracfg_drv); diff --git a/6.1/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-topckgen.c b/6.1/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-topckgen.c deleted file mode 100644 index b0745d65..00000000 --- a/6.1/target/linux/mediatek/files-6.1/drivers/clk/mediatek/clk-mt7988-topckgen.c +++ /dev/null @@ -1,446 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2023 MediaTek Inc. - * Author: Sam Shih - * Author: Xiufeng Li - */ - -#include -#include -#include -#include -#include -#include "clk-mtk.h" -#include "clk-gate.h" -#include "clk-mux.h" -#include - -static DEFINE_SPINLOCK(mt7988_clk_lock); - -static const struct mtk_fixed_clk top_fixed_clks[] = { - FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000), -}; - -static const struct mtk_fixed_factor top_divs[] = { - FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2), - FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250), - FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220), - FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2), - FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2), - FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4), - FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8), - FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16), - FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2), - FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", "mmpll", 1, 15), - FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4), - FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12), - FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", "mmpll", 1, 8), - FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), - FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", "net1pll", 1, 4), - FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", "net1pll", 1, 5), - FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", "net1pll", 1, 10), - FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", "net1pll", 1, 20), - FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", "net1pll", 1, 8), - FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", "net1pll", 1, 16), - FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", "net1pll", 1, 32), - FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", "net1pll", 1, 64), - FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", "net1pll", 1, 128), - FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", "net2pll", 1, 2), - FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", "net2pll", 1, 4), - FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", "net2pll", 1, 16), - FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", "net2pll", 1, 32), - FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", "net2pll", 1, 6), - FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", "net2pll", 1, 8), -}; - -static const char *const netsys_parents[] = { "top_xtal", "net2pll_d2", - "mmpll_d2" }; - -static const char *const netsys_500m_parents[] = { "top_xtal", "net1pll_d5", - "net1pll_d5_d2" }; - -static const char *const netsys_2x_parents[] = { "top_xtal", "net2pll", - "mmpll" }; - -static const char *const netsys_gsw_parents[] = { "top_xtal", "net1pll_d4", - "net1pll_d5" }; - -static const char *const eth_gmii_parents[] = { "top_xtal", "net1pll_d5_d4" }; - -static const char *const netsys_mcu_parents[] = { "top_xtal", "net2pll", - "mmpll", "net1pll_d4", - "net1pll_d5", "mpll" }; - -static const char *const eip197_parents[] = { "top_xtal", "netsyspll", - "net2pll", "mmpll", - "net1pll_d4", "net1pll_d5" }; - -static const char *const axi_infra_parents[] = { "top_xtal", "net1pll_d8_d2" }; - -static const char *const uart_parents[] = { "top_xtal", "mpll_d8", - "mpll_d8_d2" }; - -static const char *const emmc_250m_parents[] = { "top_xtal", "net1pll_d5_d2", - "mmpll_d4" }; - -static const char *const emmc_400m_parents[] = { "top_xtal", "msdcpll", - "mmpll_d2", "mpll_d2", - "mmpll_d4", "net1pll_d8_d2" }; - -static const char *const spi_parents[] = { "top_xtal", "mpll_d2", - "mmpll_d4", "net1pll_d8_d2", - "net2pll_d6", "net1pll_d5_d4", - "mpll_d4", "net1pll_d8_d4" }; - -static const char *const nfi1x_parents[] = { "top_xtal", "mmpll_d4", - "net1pll_d8_d2", "net2pll_d6", - "mpll_d4", "mmpll_d8", - "net1pll_d8_d4", "mpll_d8" }; - -static const char *const spinfi_parents[] = { "top_xtal_d2", "top_xtal", - "net1pll_d5_d4", "mpll_d4", - "mmpll_d8", "net1pll_d8_d4", - "mmpll_d6_d2", "mpll_d8" }; - -static const char *const pwm_parents[] = { "top_xtal", "net1pll_d8_d2", - "net1pll_d5_d4", "mpll_d4", - "mpll_d8_d2", "top_rtc_32k" }; - -static const char *const i2c_parents[] = { "top_xtal", "net1pll_d5_d4", - "mpll_d4", "net1pll_d8_d4" }; - -static const char *const pcie_mbist_250m_parents[] = { "top_xtal", - "net1pll_d5_d2" }; - -static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6", - "mmpll_d8", "mpll_d8_d2", - "top_rtc_32k" }; - -static const char *const usb_frmcnt_parents[] = { "top_xtal", "mmpll_d3_d5" }; - -static const char *const aud_parents[] = { "top_xtal", "apll2" }; - -static const char *const a1sys_parents[] = { "top_xtal", "apll2_d4" }; - -static const char *const aud_l_parents[] = { "top_xtal", "apll2", - "mpll_d8_d2" }; - -static const char *const sspxtp_parents[] = { "top_xtal_d2", "mpll_d8_d2" }; - -static const char *const usxgmii_sbus_0_parents[] = { "top_xtal", - "net1pll_d8_d4" }; - -static const char *const sgm_0_parents[] = { "top_xtal", "sgmpll" }; - -static const char *const sysapb_parents[] = { "top_xtal", "mpll_d3_d2" }; - -static const char *const eth_refck_50m_parents[] = { "top_xtal", - "net2pll_d4_d4" }; - -static const char *const eth_sys_200m_parents[] = { "top_xtal", "net2pll_d4" }; - -static const char *const eth_xgmii_parents[] = { "top_xtal_d2", - "net1pll_d8_d8", - "net1pll_d8_d16" }; - -static const char *const bus_tops_parents[] = { "top_xtal", "net1pll_d5", - "net2pll_d2" }; - -static const char *const npu_tops_parents[] = { "top_xtal", "net2pll" }; - -static const char *const dramc_md32_parents[] = { "top_xtal", "mpll_d2", - "wedmcupll" }; - -static const char *const da_xtp_glb_p0_parents[] = { "top_xtal", - "net2pll_d8" }; - -static const char *const mcusys_backup_625m_parents[] = { "top_xtal", - "net1pll_d4" }; - -static const char *const macsec_parents[] = { "top_xtal", "sgmpll", - "net1pll_d8" }; - -static const char *const netsys_tops_400m_parents[] = { "top_xtal", - "net2pll_d2" }; - -static const char *const eth_mii_parents[] = { "top_xtal_d2", - "net2pll_d4_d8" }; - -static const struct mtk_mux top_muxes[] = { - /* CLK_CFG_0 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, - 0x000, 0x004, 0x008, 0, 2, 7, 0x1c0, 0), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", - netsys_500m_parents, 0x000, 0x004, 0x008, 8, 2, - 15, 0x1C0, 1), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", - netsys_2x_parents, 0x000, 0x004, 0x008, 16, 2, 23, - 0x1C0, 2), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", - netsys_gsw_parents, 0x000, 0x004, 0x008, 24, 2, - 31, 0x1C0, 3), - /* CLK_CFG_1 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", - eth_gmii_parents, 0x010, 0x014, 0x018, 0, 1, 7, - 0x1C0, 4), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", - netsys_mcu_parents, 0x010, 0x014, 0x018, 8, 3, 15, - 0x1C0, 5), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel", - netsys_mcu_parents, 0x010, 0x014, 0x018, 16, 3, - 23, 0x1C0, 6), - MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents, - 0x010, 0x014, 0x018, 24, 3, 31, 0x1c0, 7), - /* CLK_CFG_2 */ - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel", - axi_infra_parents, 0x020, 0x024, 0x028, 0, - 1, 7, 0x1C0, 8, CLK_IS_CRITICAL), - MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020, - 0x024, 0x028, 8, 2, 15, 0x1c0, 9), - MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel", - emmc_250m_parents, 0x020, 0x024, 0x028, 16, 2, 23, - 0x1C0, 10), - MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", - emmc_400m_parents, 0x020, 0x024, 0x028, 24, 3, 31, - 0x1C0, 11), - /* CLK_CFG_3 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030, - 0x034, 0x038, 0, 3, 7, 0x1c0, 12), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, - 0x030, 0x034, 0x038, 8, 3, 15, 0x1c0, 13), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, - 0x030, 0x034, 0x038, 16, 3, 23, 0x1c0, 14), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, - 0x030, 0x034, 0x038, 24, 3, 31, 0x1c0, 15), - /* CLK_CFG_4 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040, - 0x044, 0x048, 0, 3, 7, 0x1c0, 16), - MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040, - 0x044, 0x048, 8, 2, 15, 0x1c0, 17), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL, - "pcie_mbist_250m_sel", pcie_mbist_250m_parents, - 0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel", - pextp_tl_ck_parents, 0x040, 0x044, 0x048, 24, 3, - 31, 0x1C0, 19), - /* CLK_CFG_5 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel", - pextp_tl_ck_parents, 0x050, 0x054, 0x058, 0, 3, 7, - 0x1C0, 20), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel", - pextp_tl_ck_parents, 0x050, 0x054, 0x058, 8, 3, - 15, 0x1C0, 21), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel", - pextp_tl_ck_parents, 0x050, 0x054, 0x058, 16, 3, - 23, 0x1C0, 22), - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_SEL, "usb_sys_sel", - eth_gmii_parents, 0x050, 0x054, 0x058, 24, 1, 31, - 0x1C0, 23), - /* CLK_CFG_6 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel", - eth_gmii_parents, 0x060, 0x064, 0x068, 0, 1, 7, - 0x1C0, 24), - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel", - eth_gmii_parents, 0x060, 0x064, 0x068, 8, 1, 15, - 0x1C0, 25), - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel", - eth_gmii_parents, 0x060, 0x064, 0x068, 16, 1, 23, - 0x1C0, 26), - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", - usb_frmcnt_parents, 0x060, 0x064, 0x068, 24, 1, - 31, 0x1C0, 27), - /* CLK_CFG_7 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel", - usb_frmcnt_parents, 0x070, 0x074, 0x078, 0, 1, 7, - 0x1C0, 28), - MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070, - 0x074, 0x078, 8, 1, 15, 0x1c0, 29), - MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, - 0x070, 0x074, 0x078, 16, 1, 23, 0x1c0, 30), - MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, - 0x070, 0x074, 0x078, 24, 2, 31, 0x1c4, 0), - /* CLK_CFG_8 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents, - 0x080, 0x084, 0x088, 0, 1, 7, 0x1c4, 1), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents, - 0x080, 0x084, 0x088, 8, 1, 15, 0x1c4, 2), - MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel", - sspxtp_parents, 0x080, 0x084, 0x088, 16, 1, 23, - 0x1c4, 3), - MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel", - usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24, - 1, 31, 0x1C4, 4), - /* CLK_CFG_9 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel", - usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1, - 7, 0x1C4, 5), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents, - 0x090, 0x094, 0x098, 8, 1, 15, 0x1c4, 6), - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel", - usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, - 16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL), - MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents, - 0x090, 0x094, 0x098, 24, 1, 31, 0x1c4, 8), - /* CLK_CFG_10 */ - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel", - usxgmii_sbus_0_parents, 0x0a0, 0x0a4, 0x0a8, - 0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL), - MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel", - sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 8, 1, 15, - 0x1C4, 10), - MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel", - sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 16, 1, 23, - 0x1C4, 11), - /* CLK_CFG_11 */ - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", - axi_infra_parents, 0x0a0, 0x0a4, 0x0a8, 24, - 1, 31, 0x1C4, 12, CLK_IS_CRITICAL), - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", - sysapb_parents, 0x0b0, 0x0b4, 0x0b8, 0, 1, - 7, 0x1c4, 13, CLK_IS_CRITICAL), - MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel", - eth_refck_50m_parents, 0x0b0, 0x0b4, 0x0b8, 8, 1, - 15, 0x1C4, 14), - MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel", - eth_sys_200m_parents, 0x0b0, 0x0b4, 0x0b8, 16, 1, - 23, 0x1C4, 15), - MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel", - pcie_mbist_250m_parents, 0x0b0, 0x0b4, 0x0b8, 24, - 1, 31, 0x1C4, 16), - /* CLK_CFG_12 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel", - eth_xgmii_parents, 0x0c0, 0x0c4, 0x0c8, 0, 2, 7, - 0x1C4, 17), - MUX_GATE_CLR_SET_UPD(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel", - bus_tops_parents, 0x0c0, 0x0c4, 0x0c8, 8, 2, 15, - 0x1C4, 18), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel", - npu_tops_parents, 0x0c0, 0x0c4, 0x0c8, 16, 1, 23, - 0x1C4, 19), - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", - sspxtp_parents, 0x0c0, 0x0c4, 0x0c8, 24, 1, - 31, 0x1C4, 20, CLK_IS_CRITICAL), - /* CLK_CFG_13 */ - MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", - dramc_md32_parents, 0x0d0, 0x0d4, 0x0d8, 0, - 2, 7, 0x1C4, 21, CLK_IS_CRITICAL), - MUX_GATE_CLR_SET_UPD_FLAGS( - CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents, - 0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel", - sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 16, 1, 23, - 0x1C4, 23), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel", - sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 24, 1, 31, - 0x1C4, 24), - /* CLK_CFG_14 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel", - sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7, - 0x1C4, 25), - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel", - sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 8, 1, 15, - 0x1C4, 26), - MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel", - da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 16, 1, - 23, 0x1C4, 27), - MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel", - da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 24, 1, - 31, 0x1C4, 28), - /* CLK_CFG_15 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel", - da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 0, 1, - 7, 0x1C4, 29), - MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel", - da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 8, 1, - 15, 0x1C4, 30), - MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0, - 0x0f4, 0x0f8, 16, 1, 23, 0x1c8, 0), - MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0x0f0, - 0x0f4, 0x0f8, 24, 1, 31, 0x1C8, 1), - /* CLK_CFG_16 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents, - 0x0100, 0x104, 0x108, 0, 1, 7, 0x1c8, 2), - MUX_GATE_CLR_SET_UPD(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel", - sspxtp_parents, 0x0100, 0x104, 0x108, 8, 1, 15, - 0x1C8, 3), - MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUSYS_BACKUP_625M_SEL, - "mcusys_backup_625m_sel", - mcusys_backup_625m_parents, 0x0100, 0x104, 0x108, - 16, 1, 23, 0x1C8, 4), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SYNC_250M_SEL, - "netsys_sync_250m_sel", pcie_mbist_250m_parents, - 0x0100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5), - /* CLK_CFG_17 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents, - 0x0110, 0x114, 0x118, 0, 2, 7, 0x1c8, 6), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_TOPS_400M_SEL, - "netsys_tops_400m_sel", netsys_tops_400m_parents, - 0x0110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PPEFB_250M_SEL, - "netsys_ppefb_250m_sel", pcie_mbist_250m_parents, - 0x0110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel", - netsys_parents, 0x0110, 0x114, 0x118, 24, 2, 31, - 0x1C8, 9), - /* CLK_CFG_18 */ - MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel", - eth_mii_parents, 0x0120, 0x124, 0x128, 0, 1, 7, - 0x1c8, 10), - MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents, - 0x0120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11), -}; - -static const struct mtk_composite top_aud_divs[] = { - DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420, - 8, 8), -}; - -static const struct mtk_clk_desc topck_desc = { - .fixed_clks = top_fixed_clks, - .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), - .factor_clks = top_divs, - .num_factor_clks = ARRAY_SIZE(top_divs), - .mux_clks = top_muxes, - .num_mux_clks = ARRAY_SIZE(top_muxes), - .composite_clks = top_aud_divs, - .num_composite_clks = ARRAY_SIZE(top_aud_divs), - .clk_lock = &mt7988_clk_lock, -}; - -static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b", - "net1pll_d4" }; - -static const char *const mcu_arm_div_parents[] = { "top_xtal", "arm_b", - "net1pll_d4" }; - -static struct mtk_composite mcu_muxes[] = { - /* bus_pll_divider_cfg */ - MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel", - mcu_bus_div_parents, 0x7C0, 9, 2, -1, CLK_IS_CRITICAL), - /* mp2_pll_divider_cfg */ - MUX_GATE_FLAGS(CLK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel", - mcu_arm_div_parents, 0x7A8, 9, 2, -1, CLK_IS_CRITICAL), -}; - -static const struct mtk_clk_desc mcusys_desc = { - .composite_clks = mcu_muxes, - .num_composite_clks = ARRAY_SIZE(mcu_muxes), -}; - -static const struct of_device_id of_match_clk_mt7988_topckgen[] = { - { .compatible = "mediatek,mt7988-topckgen", .data = &topck_desc }, - { .compatible = "mediatek,mt7988-mcusys", .data = &mcusys_desc }, - { /* sentinel */ } -}; -MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_topckgen); - -static struct platform_driver clk_mt7988_topckgen_drv = { - .probe = mtk_clk_simple_probe, - .remove = mtk_clk_simple_remove, - .driver = { - .name = "clk-mt7988-topckgen", - .of_match_table = of_match_clk_mt7988_topckgen, - }, -}; -module_platform_driver(clk_mt7988_topckgen_drv); -MODULE_LICENSE("GPL"); diff --git a/6.1/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c b/6.1/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c deleted file mode 100644 index c12e6b8e..00000000 --- a/6.1/target/linux/mediatek/files-6.1/drivers/net/phy/mediatek-2p5ge.c +++ /dev/null @@ -1,262 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -#include -#include -#include -#include -#include -#include -#include -#include - -#define MEDAITEK_2P5GE_PHY_DMB_FW "mediatek/mediatek-2p5ge-phy-dmb.bin" -#define MEDIATEK_2P5GE_PHY_PMB_FW "mediatek/mediatek-2p5ge-phy-pmb.bin" - -#define MD32_EN_CFG 0x18 -#define MD32_EN BIT(0) - -#define BASE100T_STATUS_EXTEND 0x10 -#define BASE1000T_STATUS_EXTEND 0x11 -#define EXTEND_CTRL_AND_STATUS 0x16 - -#define PHY_AUX_CTRL_STATUS 0x1d -#define PHY_AUX_DPX_MASK GENMASK(5, 5) -#define PHY_AUX_SPEED_MASK GENMASK(4, 2) - -/* Registers on MDIO_MMD_VEND1 */ -#define MTK_PHY_LINK_STATUS_MISC 0xa2 -#define MTK_PHY_FDX_ENABLE BIT(5) - -/* Registers on MDIO_MMD_VEND2 */ -#define MTK_PHY_LED0_ON_CTRL 0x24 -#define MTK_PHY_LED0_ON_LINK1000 BIT(0) -#define MTK_PHY_LED0_ON_LINK100 BIT(1) -#define MTK_PHY_LED0_ON_LINK10 BIT(2) -#define MTK_PHY_LED0_ON_LINK2500 BIT(7) -#define MTK_PHY_LED0_POLARITY BIT(14) - -#define MTK_PHY_LED1_ON_CTRL 0x26 -#define MTK_PHY_LED1_ON_FDX BIT(4) -#define MTK_PHY_LED1_ON_HDX BIT(5) -#define MTK_PHY_LED1_POLARITY BIT(14) - -enum { - PHY_AUX_SPD_10 = 0, - PHY_AUX_SPD_100, - PHY_AUX_SPD_1000, - PHY_AUX_SPD_2500, -}; - -static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev) -{ - int ret; - int i; - const struct firmware *fw; - struct device *dev = &phydev->mdio.dev; - struct device_node *np; - void __iomem *dmb_addr; - void __iomem *pmb_addr; - void __iomem *mcucsr_base; - u16 reg; - struct pinctrl *pinctrl; - - np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw"); - if (!np) - return -ENOENT; - - dmb_addr = of_iomap(np, 0); - if (!dmb_addr) - return -ENOMEM; - pmb_addr = of_iomap(np, 1); - if (!pmb_addr) - return -ENOMEM; - mcucsr_base = of_iomap(np, 2); - if (!mcucsr_base) - return -ENOMEM; - - ret = request_firmware(&fw, MEDAITEK_2P5GE_PHY_DMB_FW, dev); - if (ret) { - dev_err(dev, "failed to load firmware: %s, ret: %d\n", - MEDAITEK_2P5GE_PHY_DMB_FW, ret); - return ret; - } - for (i = 0; i < fw->size - 1; i += 4) - writel(*((uint32_t *)(fw->data + i)), dmb_addr + i); - release_firmware(fw); - - ret = request_firmware(&fw, MEDIATEK_2P5GE_PHY_PMB_FW, dev); - if (ret) { - dev_err(dev, "failed to load firmware: %s, ret: %d\n", - MEDIATEK_2P5GE_PHY_PMB_FW, ret); - return ret; - } - for (i = 0; i < fw->size - 1; i += 4) - writel(*((uint32_t *)(fw->data + i)), pmb_addr + i); - release_firmware(fw); - - reg = readw(mcucsr_base + MD32_EN_CFG); - writew(reg | MD32_EN, mcucsr_base + MD32_EN_CFG); - dev_dbg(dev, "Firmware loading/trigger ok.\n"); - - /* Setup LED */ - phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, - MTK_PHY_LED0_POLARITY); - - phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, - MTK_PHY_LED0_ON_LINK10 | - MTK_PHY_LED0_ON_LINK100 | - MTK_PHY_LED0_ON_LINK1000 | - MTK_PHY_LED0_ON_LINK2500); - - phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, - MTK_PHY_LED1_ON_FDX | MTK_PHY_LED1_ON_HDX); - - pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led"); - if (IS_ERR(pinctrl)) { - dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n"); - return PTR_ERR(pinctrl); - } - - return 0; -} - -static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev) -{ - bool changed = false; - u32 adv; - int ret; - - if (phydev->autoneg == AUTONEG_DISABLE) { - /* Configure half duplex with genphy_setup_forced, - * because genphy_c45_pma_setup_forced does not support. - */ - return phydev->duplex != DUPLEX_FULL - ? genphy_setup_forced(phydev) - : genphy_c45_pma_setup_forced(phydev); - } - - ret = genphy_c45_an_config_aneg(phydev); - if (ret < 0) - return ret; - if (ret > 0) - changed = true; - - adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); - ret = phy_modify_changed(phydev, MII_CTRL1000, - ADVERTISE_1000FULL | ADVERTISE_1000HALF, - adv); - if (ret < 0) - return ret; - if (ret > 0) - changed = true; - - return genphy_c45_check_and_restart_aneg(phydev, changed); -} - -static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev) -{ - int ret; - - ret = genphy_read_abilities(phydev); - if (ret) - return ret; - - /* We don't support HDX at MAC layer on mt798x. - * So mask phy's HDX capabilities, too. - */ - linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, - phydev->supported); - linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, - phydev->supported); - linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, - phydev->supported); - linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, - phydev->supported); - linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); - - return 0; -} - -static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev) -{ - int ret; - - ret = genphy_update_link(phydev); - if (ret) - return ret; - - phydev->speed = SPEED_UNKNOWN; - phydev->duplex = DUPLEX_UNKNOWN; - phydev->pause = 0; - phydev->asym_pause = 0; - - if (!phydev->link) - return 0; - - if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) { - ret = genphy_c45_read_lpa(phydev); - if (ret < 0) - return ret; - - /* Read the link partner's 1G advertisement */ - ret = phy_read(phydev, MII_STAT1000); - if (ret < 0) - return ret; - mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret); - } else if (phydev->autoneg == AUTONEG_DISABLE) { - linkmode_zero(phydev->lp_advertising); - } - - ret = phy_read(phydev, PHY_AUX_CTRL_STATUS); - if (ret < 0) - return ret; - - switch (FIELD_GET(PHY_AUX_SPEED_MASK, ret)) { - case PHY_AUX_SPD_10: - phydev->speed = SPEED_10; - break; - case PHY_AUX_SPD_100: - phydev->speed = SPEED_100; - break; - case PHY_AUX_SPD_1000: - phydev->speed = SPEED_1000; - break; - case PHY_AUX_SPD_2500: - phydev->speed = SPEED_2500; - phydev->duplex = DUPLEX_FULL; /* 2.5G must be FDX */ - break; - } - - ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LINK_STATUS_MISC); - if (ret < 0) - return ret; - - phydev->duplex = (ret & MTK_PHY_FDX_ENABLE) ? DUPLEX_FULL : DUPLEX_HALF; - - return 0; -} - -static struct phy_driver mtk_gephy_driver[] = { - { - PHY_ID_MATCH_EXACT(0x00339c11), - .name = "MediaTek MT798x 2.5GbE PHY", - .config_init = mt798x_2p5ge_phy_config_init, - .config_aneg = mt798x_2p5ge_phy_config_aneg, - .get_features = mt798x_2p5ge_phy_get_features, - .read_status = mt798x_2p5ge_phy_read_status, - }, -}; - -module_phy_driver(mtk_gephy_driver); - -static struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl[] = { - { PHY_ID_MATCH_VENDOR(0x00339c00) }, - { } -}; - -MODULE_DESCRIPTION("MediaTek 2.5Gb Ethernet PHY driver"); -MODULE_AUTHOR("SkyLake Huang "); -MODULE_LICENSE("GPL"); - -MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl); -MODULE_FIRMWARE(MEDAITEK_2P5GE_PHY_DMB_FW); -MODULE_FIRMWARE(MEDIATEK_2P5GE_PHY_PMB_FW); diff --git a/6.1/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c b/6.1/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c deleted file mode 100644 index da0269ed..00000000 --- a/6.1/target/linux/mediatek/files-6.1/drivers/pinctrl/mediatek/pinctrl-mt7988.c +++ /dev/null @@ -1,1282 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * The MT7988 driver based on Linux generic pinctrl binding. - * - * Copyright (C) 2020 MediaTek Inc. - * Author: Sam Shih - */ - -#include "pinctrl-moore.h" - -enum MT7988_PINCTRL_REG_PAGE { - GPIO_BASE, - IOCFG_TR_BASE, - IOCFG_BR_BASE, - IOCFG_RB_BASE, - IOCFG_LB_BASE, - IOCFG_TL_BASE, -}; - -#define MT7988_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4) - -#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ - _x_bits) \ - PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ - _x_bits, 32, 0) - -#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ - _x_bits) \ - PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ - _x_bits, 32, 1) - -static const struct mtk_pin_field_calc mt7988_pin_mode_range[] = { - PIN_FIELD(0, 83, 0x300, 0x10, 0, 4), -}; - -static const struct mtk_pin_field_calc mt7988_pin_dir_range[] = { - PIN_FIELD(0, 83, 0x0, 0x10, 0, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_di_range[] = { - PIN_FIELD(0, 83, 0x200, 0x10, 0, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_do_range[] = { - PIN_FIELD(0, 83, 0x100, 0x10, 0, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = { - PIN_FIELD_BASE(0, 1, 5, 0x30, 0x10, 13, 1), - PIN_FIELD_BASE(2, 3, 5, 0x30, 0x10, 11, 1), - PIN_FIELD_BASE(4, 4, 5, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(5, 6, 5, 0x30, 0x10, 9, 1), - PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 8, 1), - PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 6, 1), - PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 5, 1), - PIN_FIELD_BASE(10, 10, 4, 0x30, 0x10, 3, 1), - PIN_FIELD_BASE(11, 11, 1, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(12, 12, 1, 0x40, 0x10, 21, 1), - PIN_FIELD_BASE(13, 14, 1, 0x40, 0x10, 1, 1), - PIN_FIELD_BASE(15, 16, 5, 0x30, 0x10, 7, 1), - PIN_FIELD_BASE(17, 18, 5, 0x30, 0x10, 3, 1), - PIN_FIELD_BASE(19, 19, 4, 0x30, 0x10, 7, 1), - PIN_FIELD_BASE(20, 20, 4, 0x30, 0x10, 4, 1), - PIN_FIELD_BASE(21, 21, 3, 0x50, 0x10, 17, 1), - PIN_FIELD_BASE(22, 22, 3, 0x50, 0x10, 23, 1), - PIN_FIELD_BASE(23, 23, 3, 0x50, 0x10, 20, 1), - PIN_FIELD_BASE(24, 24, 3, 0x50, 0x10, 19, 1), - PIN_FIELD_BASE(25, 26, 3, 0x50, 0x10, 21, 1), - PIN_FIELD_BASE(27, 27, 3, 0x50, 0x10, 18, 1), - PIN_FIELD_BASE(28, 30, 3, 0x50, 0x10, 25, 1), - PIN_FIELD_BASE(31, 31, 3, 0x50, 0x10, 24, 1), - PIN_FIELD_BASE(32, 32, 3, 0x50, 0x10, 28, 1), - PIN_FIELD_BASE(33, 33, 3, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(34, 34, 3, 0x50, 0x10, 31, 1), - PIN_FIELD_BASE(35, 36, 3, 0x50, 0x10, 29, 1), - PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 1, 1), - PIN_FIELD_BASE(38, 38, 3, 0x50, 0x10, 11, 1), - PIN_FIELD_BASE(39, 39, 3, 0x50, 0x10, 10, 1), - PIN_FIELD_BASE(40, 41, 3, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(42, 42, 3, 0x50, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 3, 0x50, 0x10, 8, 1), - PIN_FIELD_BASE(44, 44, 3, 0x50, 0x10, 7, 1), - PIN_FIELD_BASE(45, 45, 3, 0x50, 0x10, 6, 1), - PIN_FIELD_BASE(46, 46, 3, 0x50, 0x10, 5, 1), - PIN_FIELD_BASE(47, 47, 3, 0x50, 0x10, 4, 1), - PIN_FIELD_BASE(48, 48, 3, 0x50, 0x10, 3, 1), - PIN_FIELD_BASE(49, 49, 3, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(50, 50, 3, 0x50, 0x10, 15, 1), - PIN_FIELD_BASE(51, 53, 3, 0x50, 0x10, 12, 1), - PIN_FIELD_BASE(54, 54, 3, 0x50, 0x10, 16, 1), - PIN_FIELD_BASE(55, 56, 1, 0x40, 0x10, 14, 1), - PIN_FIELD_BASE(57, 57, 1, 0x40, 0x10, 13, 1), - PIN_FIELD_BASE(58, 60, 1, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(61, 61, 1, 0x40, 0x10, 3, 1), - PIN_FIELD_BASE(62, 62, 1, 0x40, 0x10, 7, 1), - PIN_FIELD_BASE(63, 63, 1, 0x40, 0x10, 20, 1), - PIN_FIELD_BASE(64, 68, 1, 0x40, 0x10, 8, 1), - PIN_FIELD_BASE(69, 70, 5, 0x30, 0x10, 1, 1), - PIN_FIELD_BASE(71, 72, 5, 0x30, 0x10, 5, 1), - PIN_FIELD_BASE(73, 73, 4, 0x30, 0x10, 10, 1), - PIN_FIELD_BASE(74, 74, 4, 0x30, 0x10, 1, 1), - PIN_FIELD_BASE(75, 75, 4, 0x30, 0x10, 11, 1), - PIN_FIELD_BASE(76, 76, 4, 0x30, 0x10, 9, 1), - PIN_FIELD_BASE(77, 77, 4, 0x30, 0x10, 2, 1), - PIN_FIELD_BASE(78, 78, 4, 0x30, 0x10, 0, 1), - PIN_FIELD_BASE(79, 79, 4, 0x30, 0x10, 12, 1), - PIN_FIELD_BASE(80, 81, 1, 0x40, 0x10, 18, 1), - PIN_FIELD_BASE(82, 83, 1, 0x40, 0x10, 16, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = { - PIN_FIELD_BASE(0, 1, 5, 0xc0, 0x10, 13, 1), - PIN_FIELD_BASE(2, 3, 5, 0xc0, 0x10, 11, 1), - PIN_FIELD_BASE(4, 4, 5, 0xc0, 0x10, 0, 1), - PIN_FIELD_BASE(5, 6, 5, 0xc0, 0x10, 9, 1), - PIN_FIELD_BASE(7, 7, 4, 0xb0, 0x10, 8, 1), - PIN_FIELD_BASE(8, 8, 4, 0xb0, 0x10, 6, 1), - PIN_FIELD_BASE(9, 9, 4, 0xb0, 0x10, 5, 1), - PIN_FIELD_BASE(10, 10, 4, 0xb0, 0x10, 3, 1), - PIN_FIELD_BASE(11, 11, 1, 0xe0, 0x10, 0, 1), - PIN_FIELD_BASE(12, 12, 1, 0xe0, 0x10, 21, 1), - PIN_FIELD_BASE(13, 14, 1, 0xe0, 0x10, 1, 1), - PIN_FIELD_BASE(15, 16, 5, 0xc0, 0x10, 7, 1), - PIN_FIELD_BASE(17, 18, 5, 0xc0, 0x10, 3, 1), - PIN_FIELD_BASE(19, 19, 4, 0xb0, 0x10, 7, 1), - PIN_FIELD_BASE(20, 20, 4, 0xb0, 0x10, 4, 1), - PIN_FIELD_BASE(21, 21, 3, 0x140, 0x10, 17, 1), - PIN_FIELD_BASE(22, 22, 3, 0x140, 0x10, 23, 1), - PIN_FIELD_BASE(23, 23, 3, 0x140, 0x10, 20, 1), - PIN_FIELD_BASE(24, 24, 3, 0x140, 0x10, 19, 1), - PIN_FIELD_BASE(25, 26, 3, 0x140, 0x10, 21, 1), - PIN_FIELD_BASE(27, 27, 3, 0x140, 0x10, 18, 1), - PIN_FIELD_BASE(28, 30, 3, 0x140, 0x10, 25, 1), - PIN_FIELD_BASE(31, 31, 3, 0x140, 0x10, 24, 1), - PIN_FIELD_BASE(32, 32, 3, 0x140, 0x10, 28, 1), - PIN_FIELD_BASE(33, 33, 3, 0x150, 0x10, 0, 1), - PIN_FIELD_BASE(34, 34, 3, 0x140, 0x10, 31, 1), - PIN_FIELD_BASE(35, 36, 3, 0x140, 0x10, 29, 1), - PIN_FIELD_BASE(37, 37, 3, 0x150, 0x10, 1, 1), - PIN_FIELD_BASE(38, 38, 3, 0x140, 0x10, 11, 1), - PIN_FIELD_BASE(39, 39, 3, 0x140, 0x10, 10, 1), - PIN_FIELD_BASE(40, 41, 3, 0x140, 0x10, 0, 1), - PIN_FIELD_BASE(42, 42, 3, 0x140, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 3, 0x140, 0x10, 8, 1), - PIN_FIELD_BASE(44, 44, 3, 0x140, 0x10, 7, 1), - PIN_FIELD_BASE(45, 45, 3, 0x140, 0x10, 6, 1), - PIN_FIELD_BASE(46, 46, 3, 0x140, 0x10, 5, 1), - PIN_FIELD_BASE(47, 47, 3, 0x140, 0x10, 4, 1), - PIN_FIELD_BASE(48, 48, 3, 0x140, 0x10, 3, 1), - PIN_FIELD_BASE(49, 49, 3, 0x140, 0x10, 2, 1), - PIN_FIELD_BASE(50, 50, 3, 0x140, 0x10, 15, 1), - PIN_FIELD_BASE(51, 53, 3, 0x140, 0x10, 12, 1), - PIN_FIELD_BASE(54, 54, 3, 0x140, 0x10, 16, 1), - PIN_FIELD_BASE(55, 56, 1, 0xe0, 0x10, 14, 1), - PIN_FIELD_BASE(57, 57, 1, 0xe0, 0x10, 13, 1), - PIN_FIELD_BASE(58, 60, 1, 0xe0, 0x10, 4, 1), - PIN_FIELD_BASE(61, 61, 1, 0xe0, 0x10, 3, 1), - PIN_FIELD_BASE(62, 62, 1, 0xe0, 0x10, 7, 1), - PIN_FIELD_BASE(63, 63, 1, 0xe0, 0x10, 20, 1), - PIN_FIELD_BASE(64, 68, 1, 0xe0, 0x10, 8, 1), - PIN_FIELD_BASE(69, 70, 5, 0xc0, 0x10, 1, 1), - PIN_FIELD_BASE(71, 72, 5, 0xc0, 0x10, 5, 1), - PIN_FIELD_BASE(73, 73, 4, 0xb0, 0x10, 10, 1), - PIN_FIELD_BASE(74, 74, 4, 0xb0, 0x10, 1, 1), - PIN_FIELD_BASE(75, 75, 4, 0xb0, 0x10, 11, 1), - PIN_FIELD_BASE(76, 76, 4, 0xb0, 0x10, 9, 1), - PIN_FIELD_BASE(77, 77, 4, 0xb0, 0x10, 2, 1), - PIN_FIELD_BASE(78, 78, 4, 0xb0, 0x10, 0, 1), - PIN_FIELD_BASE(79, 79, 4, 0xb0, 0x10, 12, 1), - PIN_FIELD_BASE(80, 81, 1, 0xe0, 0x10, 18, 1), - PIN_FIELD_BASE(82, 83, 1, 0xe0, 0x10, 16, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = { - PIN_FIELD_BASE(7, 7, 4, 0x60, 0x10, 5, 1), - PIN_FIELD_BASE(8, 8, 4, 0x60, 0x10, 4, 1), - PIN_FIELD_BASE(9, 9, 4, 0x60, 0x10, 3, 1), - PIN_FIELD_BASE(10, 10, 4, 0x60, 0x10, 2, 1), - PIN_FIELD_BASE(13, 14, 1, 0x70, 0x10, 0, 1), - PIN_FIELD_BASE(63, 63, 1, 0x70, 0x10, 2, 1), - PIN_FIELD_BASE(75, 75, 4, 0x60, 0x10, 7, 1), - PIN_FIELD_BASE(76, 76, 4, 0x60, 0x10, 6, 1), - PIN_FIELD_BASE(77, 77, 4, 0x60, 0x10, 1, 1), - PIN_FIELD_BASE(78, 78, 4, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(79, 79, 4, 0x60, 0x10, 8, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = { - PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 5, 1), - PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 3, 1), - PIN_FIELD_BASE(10, 10, 4, 0x40, 0x10, 2, 1), - PIN_FIELD_BASE(13, 14, 1, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(15, 16, 5, 0x40, 0x10, 4, 1), - PIN_FIELD_BASE(17, 18, 5, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(63, 63, 1, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(71, 72, 5, 0x40, 0x10, 2, 1), - PIN_FIELD_BASE(75, 75, 4, 0x40, 0x10, 7, 1), - PIN_FIELD_BASE(76, 76, 4, 0x40, 0x10, 6, 1), - PIN_FIELD_BASE(77, 77, 4, 0x40, 0x10, 1, 1), - PIN_FIELD_BASE(78, 78, 4, 0x40, 0x10, 0, 1), - PIN_FIELD_BASE(79, 79, 4, 0x40, 0x10, 8, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = { - PIN_FIELD_BASE(0, 1, 5, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(2, 3, 5, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(4, 4, 5, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(5, 6, 5, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 28, 3), - PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(10, 10, 4, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(11, 11, 1, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(12, 12, 1, 0x20, 0x10, 3, 3), - PIN_FIELD_BASE(13, 14, 1, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(19, 19, 4, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(20, 20, 4, 0x00, 0x10, 12, 3), - PIN_FIELD_BASE(21, 21, 3, 0x10, 0x10, 21, 3), - PIN_FIELD_BASE(22, 22, 3, 0x20, 0x10, 9, 3), - PIN_FIELD_BASE(23, 23, 3, 0x20, 0x10, 0, 3), - PIN_FIELD_BASE(24, 24, 3, 0x10, 0x10, 27, 3), - PIN_FIELD_BASE(25, 26, 3, 0x20, 0x10, 3, 3), - PIN_FIELD_BASE(27, 27, 3, 0x10, 0x10, 24, 3), - PIN_FIELD_BASE(28, 30, 3, 0x20, 0x10, 15, 3), - PIN_FIELD_BASE(31, 31, 3, 0x20, 0x10, 12, 3), - PIN_FIELD_BASE(32, 32, 3, 0x20, 0x10, 24, 3), - PIN_FIELD_BASE(33, 33, 3, 0x30, 0x10, 6, 3), - PIN_FIELD_BASE(34, 34, 3, 0x30, 0x10, 3, 3), - PIN_FIELD_BASE(35, 35, 3, 0x20, 0x10, 27, 3), - PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 0, 3), - PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 9, 3), - PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 3, 3), - PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(40, 41, 3, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(42, 42, 3, 0x00, 0x10, 27, 3), - PIN_FIELD_BASE(43, 43, 3, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(44, 44, 3, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(45, 45, 3, 0x00, 0x10, 18, 3), - PIN_FIELD_BASE(46, 46, 3, 0x00, 0x10, 15, 3), - PIN_FIELD_BASE(47, 47, 3, 0x00, 0x10, 12, 3), - PIN_FIELD_BASE(48, 48, 3, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(49, 49, 3, 0x00, 0x10, 6, 3), - PIN_FIELD_BASE(50, 50, 3, 0x10, 0x10, 15, 3), - PIN_FIELD_BASE(51, 53, 3, 0x10, 0x10, 6, 3), - PIN_FIELD_BASE(54, 54, 3, 0x10, 0x10, 18, 3), - PIN_FIELD_BASE(55, 56, 1, 0x10, 0x10, 12, 3), - PIN_FIELD_BASE(57, 57, 1, 0x10, 0x10, 9, 3), - PIN_FIELD_BASE(58, 60, 1, 0x00, 0x10, 12, 3), - PIN_FIELD_BASE(61, 61, 1, 0x00, 0x10, 9, 3), - PIN_FIELD_BASE(62, 62, 1, 0x00, 0x10, 21, 3), - PIN_FIELD_BASE(63, 63, 1, 0x20, 0x10, 0, 3), - PIN_FIELD_BASE(64, 65, 1, 0x00, 0x10, 24, 3), - PIN_FIELD_BASE(66, 68, 1, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(69, 70, 5, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(73, 73, 4, 0x10, 0x10, 0, 3), - PIN_FIELD_BASE(74, 74, 4, 0x00, 0x10, 3, 3), - PIN_FIELD_BASE(75, 75, 4, 0x10, 0x10, 3, 3), - PIN_FIELD_BASE(76, 76, 4, 0x00, 0x10, 27, 3), - PIN_FIELD_BASE(77, 77, 4, 0x00, 0x10, 6, 3), - PIN_FIELD_BASE(78, 78, 4, 0x00, 0x10, 0, 3), - PIN_FIELD_BASE(79, 79, 4, 0x10, 0x10, 6, 3), - PIN_FIELD_BASE(80, 81, 1, 0x10, 0x10, 24, 3), - PIN_FIELD_BASE(82, 83, 1, 0x10, 0x10, 18, 3), -}; - -static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = { - PIN_FIELD_BASE(0, 1, 5, 0x50, 0x10, 7, 1), - PIN_FIELD_BASE(2, 3, 5, 0x50, 0x10, 5, 1), - PIN_FIELD_BASE(4, 4, 5, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(5, 6, 5, 0x50, 0x10, 3, 1), - PIN_FIELD_BASE(11, 11, 1, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(12, 12, 1, 0x60, 0x10, 18, 1), - PIN_FIELD_BASE(19, 19, 4, 0x50, 0x10, 2, 1), - PIN_FIELD_BASE(20, 20, 4, 0x50, 0x10, 1, 1), - PIN_FIELD_BASE(21, 21, 3, 0x70, 0x10, 17, 1), - PIN_FIELD_BASE(22, 22, 3, 0x70, 0x10, 23, 1), - PIN_FIELD_BASE(23, 23, 3, 0x70, 0x10, 20, 1), - PIN_FIELD_BASE(24, 24, 3, 0x70, 0x10, 19, 1), - PIN_FIELD_BASE(25, 26, 3, 0x70, 0x10, 21, 1), - PIN_FIELD_BASE(27, 27, 3, 0x70, 0x10, 18, 1), - PIN_FIELD_BASE(28, 30, 3, 0x70, 0x10, 25, 1), - PIN_FIELD_BASE(31, 31, 3, 0x70, 0x10, 24, 1), - PIN_FIELD_BASE(32, 32, 3, 0x70, 0x10, 28, 1), - PIN_FIELD_BASE(33, 33, 3, 0x80, 0x10, 0, 1), - PIN_FIELD_BASE(34, 34, 3, 0x70, 0x10, 31, 1), - PIN_FIELD_BASE(35, 36, 3, 0x70, 0x10, 29, 1), - PIN_FIELD_BASE(37, 37, 3, 0x80, 0x10, 1, 1), - PIN_FIELD_BASE(38, 38, 3, 0x70, 0x10, 11, 1), - PIN_FIELD_BASE(39, 39, 3, 0x70, 0x10, 10, 1), - PIN_FIELD_BASE(40, 41, 3, 0x70, 0x10, 0, 1), - PIN_FIELD_BASE(42, 42, 3, 0x70, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 3, 0x70, 0x10, 8, 1), - PIN_FIELD_BASE(44, 44, 3, 0x70, 0x10, 7, 1), - PIN_FIELD_BASE(45, 45, 3, 0x70, 0x10, 6, 1), - PIN_FIELD_BASE(46, 46, 3, 0x70, 0x10, 5, 1), - PIN_FIELD_BASE(47, 47, 3, 0x70, 0x10, 4, 1), - PIN_FIELD_BASE(48, 48, 3, 0x70, 0x10, 3, 1), - PIN_FIELD_BASE(49, 49, 3, 0x70, 0x10, 2, 1), - PIN_FIELD_BASE(50, 50, 3, 0x70, 0x10, 15, 1), - PIN_FIELD_BASE(51, 53, 3, 0x70, 0x10, 12, 1), - PIN_FIELD_BASE(54, 54, 3, 0x70, 0x10, 16, 1), - PIN_FIELD_BASE(55, 56, 1, 0x60, 0x10, 12, 1), - PIN_FIELD_BASE(57, 57, 1, 0x60, 0x10, 11, 1), - PIN_FIELD_BASE(58, 60, 1, 0x60, 0x10, 2, 1), - PIN_FIELD_BASE(61, 61, 1, 0x60, 0x10, 1, 1), - PIN_FIELD_BASE(62, 62, 1, 0x60, 0x10, 5, 1), - PIN_FIELD_BASE(64, 68, 1, 0x60, 0x10, 6, 1), - PIN_FIELD_BASE(69, 70, 5, 0x50, 0x10, 1, 1), - PIN_FIELD_BASE(73, 73, 4, 0x50, 0x10, 3, 1), - PIN_FIELD_BASE(74, 74, 4, 0x50, 0x10, 0, 1), - PIN_FIELD_BASE(80, 81, 1, 0x60, 0x10, 16, 1), - PIN_FIELD_BASE(82, 83, 1, 0x60, 0x10, 14, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = { - PIN_FIELD_BASE(0, 1, 5, 0x60, 0x10, 7, 1), - PIN_FIELD_BASE(2, 3, 5, 0x60, 0x10, 5, 1), - PIN_FIELD_BASE(4, 4, 5, 0x60, 0x10, 0, 1), - PIN_FIELD_BASE(5, 6, 5, 0x60, 0x10, 3, 1), - PIN_FIELD_BASE(11, 11, 1, 0x80, 0x10, 0, 1), - PIN_FIELD_BASE(12, 12, 1, 0x80, 0x10, 18, 1), - PIN_FIELD_BASE(19, 19, 4, 0x70, 0x10, 2, 1), - PIN_FIELD_BASE(20, 20, 4, 0x70, 0x10, 1, 1), - PIN_FIELD_BASE(21, 21, 3, 0x90, 0x10, 17, 1), - PIN_FIELD_BASE(22, 22, 3, 0x90, 0x10, 23, 1), - PIN_FIELD_BASE(23, 23, 3, 0x90, 0x10, 20, 1), - PIN_FIELD_BASE(24, 24, 3, 0x90, 0x10, 19, 1), - PIN_FIELD_BASE(25, 26, 3, 0x90, 0x10, 21, 1), - PIN_FIELD_BASE(27, 27, 3, 0x90, 0x10, 18, 1), - PIN_FIELD_BASE(28, 30, 3, 0x90, 0x10, 25, 1), - PIN_FIELD_BASE(31, 31, 3, 0x90, 0x10, 24, 1), - PIN_FIELD_BASE(32, 32, 3, 0x90, 0x10, 28, 1), - PIN_FIELD_BASE(33, 33, 3, 0xa0, 0x10, 0, 1), - PIN_FIELD_BASE(34, 34, 3, 0x90, 0x10, 31, 1), - PIN_FIELD_BASE(35, 36, 3, 0x90, 0x10, 29, 1), - PIN_FIELD_BASE(37, 37, 3, 0xa0, 0x10, 1, 1), - PIN_FIELD_BASE(38, 38, 3, 0x90, 0x10, 11, 1), - PIN_FIELD_BASE(39, 39, 3, 0x90, 0x10, 10, 1), - PIN_FIELD_BASE(40, 41, 3, 0x90, 0x10, 0, 1), - PIN_FIELD_BASE(42, 42, 3, 0x90, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 3, 0x90, 0x10, 8, 1), - PIN_FIELD_BASE(44, 44, 3, 0x90, 0x10, 7, 1), - PIN_FIELD_BASE(45, 45, 3, 0x90, 0x10, 6, 1), - PIN_FIELD_BASE(46, 46, 3, 0x90, 0x10, 5, 1), - PIN_FIELD_BASE(47, 47, 3, 0x90, 0x10, 4, 1), - PIN_FIELD_BASE(48, 48, 3, 0x90, 0x10, 3, 1), - PIN_FIELD_BASE(49, 49, 3, 0x90, 0x10, 2, 1), - PIN_FIELD_BASE(50, 50, 3, 0x90, 0x10, 15, 1), - PIN_FIELD_BASE(51, 53, 3, 0x90, 0x10, 12, 1), - PIN_FIELD_BASE(54, 54, 3, 0x90, 0x10, 16, 1), - PIN_FIELD_BASE(55, 56, 1, 0x80, 0x10, 12, 1), - PIN_FIELD_BASE(57, 57, 1, 0x80, 0x10, 11, 1), - PIN_FIELD_BASE(58, 60, 1, 0x80, 0x10, 2, 1), - PIN_FIELD_BASE(61, 61, 1, 0x80, 0x10, 1, 1), - PIN_FIELD_BASE(62, 62, 1, 0x80, 0x10, 5, 1), - PIN_FIELD_BASE(64, 68, 1, 0x80, 0x10, 6, 1), - PIN_FIELD_BASE(69, 70, 5, 0x60, 0x10, 1, 1), - PIN_FIELD_BASE(73, 73, 4, 0x70, 0x10, 3, 1), - PIN_FIELD_BASE(74, 74, 4, 0x70, 0x10, 0, 1), - PIN_FIELD_BASE(80, 81, 1, 0x80, 0x10, 16, 1), - PIN_FIELD_BASE(82, 83, 1, 0x80, 0x10, 14, 1), -}; - -static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = { - PIN_FIELD_BASE(0, 1, 5, 0x70, 0x10, 7, 1), - PIN_FIELD_BASE(2, 3, 5, 0x70, 0x10, 5, 1), - PIN_FIELD_BASE(4, 4, 5, 0x70, 0x10, 0, 1), - PIN_FIELD_BASE(5, 6, 5, 0x70, 0x10, 3, 1), - PIN_FIELD_BASE(11, 11, 1, 0x90, 0x10, 0, 1), - PIN_FIELD_BASE(12, 12, 1, 0x90, 0x10, 18, 1), - PIN_FIELD_BASE(19, 19, 4, 0x80, 0x10, 2, 1), - PIN_FIELD_BASE(20, 20, 4, 0x80, 0x10, 1, 1), - PIN_FIELD_BASE(21, 21, 3, 0xb0, 0x10, 17, 1), - PIN_FIELD_BASE(22, 22, 3, 0xb0, 0x10, 23, 1), - PIN_FIELD_BASE(23, 23, 3, 0xb0, 0x10, 20, 1), - PIN_FIELD_BASE(24, 24, 3, 0xb0, 0x10, 19, 1), - PIN_FIELD_BASE(25, 26, 3, 0xb0, 0x10, 21, 1), - PIN_FIELD_BASE(27, 27, 3, 0xb0, 0x10, 18, 1), - PIN_FIELD_BASE(28, 30, 3, 0xb0, 0x10, 25, 1), - PIN_FIELD_BASE(31, 31, 3, 0xb0, 0x10, 24, 1), - PIN_FIELD_BASE(32, 32, 3, 0xb0, 0x10, 28, 1), - PIN_FIELD_BASE(33, 33, 3, 0xc0, 0x10, 0, 1), - PIN_FIELD_BASE(34, 34, 3, 0xb0, 0x10, 31, 1), - PIN_FIELD_BASE(35, 36, 3, 0xb0, 0x10, 29, 1), - PIN_FIELD_BASE(37, 37, 3, 0xc0, 0x10, 1, 1), - PIN_FIELD_BASE(38, 38, 3, 0xb0, 0x10, 11, 1), - PIN_FIELD_BASE(39, 39, 3, 0xb0, 0x10, 10, 1), - PIN_FIELD_BASE(40, 41, 3, 0xb0, 0x10, 0, 1), - PIN_FIELD_BASE(42, 42, 3, 0xb0, 0x10, 9, 1), - PIN_FIELD_BASE(43, 43, 3, 0xb0, 0x10, 8, 1), - PIN_FIELD_BASE(44, 44, 3, 0xb0, 0x10, 7, 1), - PIN_FIELD_BASE(45, 45, 3, 0xb0, 0x10, 6, 1), - PIN_FIELD_BASE(46, 46, 3, 0xb0, 0x10, 5, 1), - PIN_FIELD_BASE(47, 47, 3, 0xb0, 0x10, 4, 1), - PIN_FIELD_BASE(48, 48, 3, 0xb0, 0x10, 3, 1), - PIN_FIELD_BASE(49, 49, 3, 0xb0, 0x10, 2, 1), - PIN_FIELD_BASE(50, 50, 3, 0xb0, 0x10, 15, 1), - PIN_FIELD_BASE(51, 53, 3, 0xb0, 0x10, 12, 1), - PIN_FIELD_BASE(54, 54, 3, 0xb0, 0x10, 16, 1), - PIN_FIELD_BASE(55, 56, 1, 0x90, 0x10, 12, 1), - PIN_FIELD_BASE(57, 57, 1, 0x90, 0x10, 11, 1), - PIN_FIELD_BASE(58, 60, 1, 0x90, 0x10, 2, 1), - PIN_FIELD_BASE(61, 61, 1, 0x90, 0x10, 1, 1), - PIN_FIELD_BASE(62, 62, 1, 0x90, 0x10, 5, 1), - PIN_FIELD_BASE(64, 68, 1, 0x90, 0x10, 6, 1), - PIN_FIELD_BASE(69, 70, 5, 0x70, 0x10, 1, 1), - PIN_FIELD_BASE(73, 73, 4, 0x80, 0x10, 3, 1), - PIN_FIELD_BASE(74, 74, 4, 0x80, 0x10, 0, 1), - PIN_FIELD_BASE(80, 81, 1, 0x90, 0x10, 16, 1), - PIN_FIELD_BASE(82, 83, 1, 0x90, 0x10, 14, 1), -}; - -static const struct mtk_pin_reg_calc mt7988_reg_cals[] = { - [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range), - [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range), - [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range), - [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7988_pin_do_range), - [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7988_pin_smt_range), - [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7988_pin_ies_range), - [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7988_pin_pu_range), - [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7988_pin_pd_range), - [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7988_pin_drv_range), - [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7988_pin_pupd_range), - [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7988_pin_r0_range), - [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7988_pin_r1_range), -}; - -static const struct mtk_pin_desc mt7988_pins[] = { - MT7988_PIN(0, "UART2_RXD"), - MT7988_PIN(1, "UART2_TXD"), - MT7988_PIN(2, "UART2_CTS"), - MT7988_PIN(3, "UART2_RTS"), - MT7988_PIN(4, "GPIO_A"), - MT7988_PIN(5, "SMI_0_MDC"), - MT7988_PIN(6, "SMI_0_MDIO"), - MT7988_PIN(7, "PCIE30_2L_0_WAKE_N"), - MT7988_PIN(8, "PCIE30_2L_0_CLKREQ_N"), - MT7988_PIN(9, "PCIE30_1L_1_WAKE_N"), - MT7988_PIN(10, "PCIE30_1L_1_CLKREQ_N"), - MT7988_PIN(11, "GPIO_P"), - MT7988_PIN(12, "WATCHDOG"), - MT7988_PIN(13, "GPIO_RESET"), - MT7988_PIN(14, "GPIO_WPS"), - MT7988_PIN(15, "PMIC_I2C_SCL"), - MT7988_PIN(16, "PMIC_I2C_SDA"), - MT7988_PIN(17, "I2C_1_SCL"), - MT7988_PIN(18, "I2C_1_SDA"), - MT7988_PIN(19, "PCIE30_2L_0_PRESET_N"), - MT7988_PIN(20, "PCIE30_1L_1_PRESET_N"), - MT7988_PIN(21, "PWMD1"), - MT7988_PIN(22, "SPI0_WP"), - MT7988_PIN(23, "SPI0_HOLD"), - MT7988_PIN(24, "SPI0_CSB"), - MT7988_PIN(25, "SPI0_MISO"), - MT7988_PIN(26, "SPI0_MOSI"), - MT7988_PIN(27, "SPI0_CLK"), - MT7988_PIN(28, "SPI1_CSB"), - MT7988_PIN(29, "SPI1_MISO"), - MT7988_PIN(30, "SPI1_MOSI"), - MT7988_PIN(31, "SPI1_CLK"), - MT7988_PIN(32, "SPI2_CLK"), - MT7988_PIN(33, "SPI2_MOSI"), - MT7988_PIN(34, "SPI2_MISO"), - MT7988_PIN(35, "SPI2_CSB"), - MT7988_PIN(36, "SPI2_HOLD"), - MT7988_PIN(37, "SPI2_WP"), - MT7988_PIN(38, "EMMC_RSTB"), - MT7988_PIN(39, "EMMC_DSL"), - MT7988_PIN(40, "EMMC_CK"), - MT7988_PIN(41, "EMMC_CMD"), - MT7988_PIN(42, "EMMC_DATA_7"), - MT7988_PIN(43, "EMMC_DATA_6"), - MT7988_PIN(44, "EMMC_DATA_5"), - MT7988_PIN(45, "EMMC_DATA_4"), - MT7988_PIN(46, "EMMC_DATA_3"), - MT7988_PIN(47, "EMMC_DATA_2"), - MT7988_PIN(48, "EMMC_DATA_1"), - MT7988_PIN(49, "EMMC_DATA_0"), - MT7988_PIN(50, "PCM_FS_I2S_LRCK"), - MT7988_PIN(51, "PCM_CLK_I2S_BCLK"), - MT7988_PIN(52, "PCM_DRX_I2S_DIN"), - MT7988_PIN(53, "PCM_DTX_I2S_DOUT"), - MT7988_PIN(54, "PCM_MCK_I2S_MCLK"), - MT7988_PIN(55, "UART0_RXD"), - MT7988_PIN(56, "UART0_TXD"), - MT7988_PIN(57, "PWMD0"), - MT7988_PIN(58, "JTAG_JTDI"), - MT7988_PIN(59, "JTAG_JTDO"), - MT7988_PIN(60, "JTAG_JTMS"), - MT7988_PIN(61, "JTAG_JTCLK"), - MT7988_PIN(62, "JTAG_JTRST_N"), - MT7988_PIN(63, "USB_DRV_VBUS_P1"), - MT7988_PIN(64, "LED_A"), - MT7988_PIN(65, "LED_B"), - MT7988_PIN(66, "LED_C"), - MT7988_PIN(67, "LED_D"), - MT7988_PIN(68, "LED_E"), - MT7988_PIN(69, "GPIO_B"), - MT7988_PIN(70, "GPIO_C"), - MT7988_PIN(71, "I2C_2_SCL"), - MT7988_PIN(72, "I2C_2_SDA"), - MT7988_PIN(73, "PCIE30_2L_1_PRESET_N"), - MT7988_PIN(74, "PCIE30_1L_0_PRESET_N"), - MT7988_PIN(75, "PCIE30_2L_1_WAKE_N"), - MT7988_PIN(76, "PCIE30_2L_1_CLKREQ_N"), - MT7988_PIN(77, "PCIE30_1L_0_WAKE_N"), - MT7988_PIN(78, "PCIE30_1L_0_CLKREQ_N"), - MT7988_PIN(79, "USB_DRV_VBUS_P0"), - MT7988_PIN(80, "UART1_RXD"), - MT7988_PIN(81, "UART1_TXD"), - MT7988_PIN(82, "UART1_CTS"), - MT7988_PIN(83, "UART1_RTS"), -}; - -/* jtag */ -static int mt7988_tops_jtag0_0_pins[] = { 0, 1, 2, 3, 4 }; -static int mt7988_tops_jtag0_0_funcs[] = { 2, 2, 2, 2, 2 }; - -static int mt7988_wo0_jtag_pins[] = { 50, 51, 52, 53, 54 }; -static int mt7988_wo0_jtag_funcs[] = { 3, 3, 3, 3, 3 }; - -static int mt7988_wo1_jtag_pins[] = { 50, 51, 52, 53, 54 }; -static int mt7988_wo1_jtag_funcs[] = { 4, 4, 4, 4, 4 }; - -static int mt7988_wo2_jtag_pins[] = { 50, 51, 52, 53, 54 }; -static int mt7988_wo2_jtag_funcs[] = { 5, 5, 5, 5, 5 }; - -static int mt7988_jtag_pins[] = { 58, 59, 60, 61, 62 }; -static int mt7988_jtag_funcs[] = { 1, 1, 1, 1, 1 }; - -static int mt7988_tops_jtag0_1_pins[] = { 58, 59, 60, 61, 62 }; -static int mt7988_tops_jtag0_1_funcs[] = { 4, 4, 4, 4, 4 }; - -/* int_usxgmii */ -static int mt7988_int_usxgmii_pins[] = { 2, 3 }; -static int mt7988_int_usxgmii_funcs[] = { 3, 3 }; - -/* pwm */ -static int mt7988_pwm0_pins[] = { 57 }; -static int mt7988_pwm0_funcs[] = { 1 }; - -static int mt7988_pwm1_pins[] = { 21 }; -static int mt7988_pwm1_funcs[] = { 1 }; - -static int mt7988_pwm2_pins[] = { 80 }; -static int mt7988_pwm2_funcs[] = { 2 }; - -static int mt7988_pwm3_pins[] = { 81 }; -static int mt7988_pwm3_funcs[] = { 2 }; - -static int mt7988_pwm4_pins[] = { 82 }; -static int mt7988_pwm4_funcs[] = { 2 }; - -static int mt7988_pwm5_pins[] = { 83 }; -static int mt7988_pwm5_funcs[] = { 2 }; - -static int mt7988_pwm6_pins[] = { 69 }; -static int mt7988_pwm6_funcs[] = { 3 }; - -static int mt7988_pwm7_pins[] = { 70 }; -static int mt7988_pwm7_funcs[] = { 3 }; - -/* dfd */ -static int mt7988_dfd_pins[] = { 0, 1, 2, 3, 4 }; -static int mt7988_dfd_funcs[] = { 4, 4, 4, 4, 4 }; - -/* i2c */ -static int mt7988_xfi_phy0_i2c0_pins[] = { 0, 1 }; -static int mt7988_xfi_phy0_i2c0_funcs[] = { 5, 5 }; - -static int mt7988_xfi_phy1_i2c0_pins[] = { 0, 1 }; -static int mt7988_xfi_phy1_i2c0_funcs[] = { 6, 6 }; - -static int mt7988_xfi_phy_pll_i2c0_pins[] = { 3, 4 }; -static int mt7988_xfi_phy_pll_i2c0_funcs[] = { 5, 5 }; - -static int mt7988_xfi_phy_pll_i2c1_pins[] = { 3, 4 }; -static int mt7988_xfi_phy_pll_i2c1_funcs[] = { 6, 6 }; - -static int mt7988_i2c0_0_pins[] = { 5, 6 }; -static int mt7988_i2c0_0_funcs[] = { 2, 2 }; - -static int mt7988_i2c1_sfp_pins[] = { 5, 6 }; -static int mt7988_i2c1_sfp_funcs[] = { 4, 4 }; - -static int mt7988_xfi_pextp_phy0_i2c_pins[] = { 5, 6 }; -static int mt7988_xfi_pextp_phy0_i2c_funcs[] = { 5, 5 }; - -static int mt7988_xfi_pextp_phy1_i2c_pins[] = { 5, 6 }; -static int mt7988_xfi_pextp_phy1_i2c_funcs[] = { 6, 6 }; - -static int mt7988_i2c0_1_pins[] = { 15, 16 }; -static int mt7988_i2c0_1_funcs[] = { 1, 1 }; - -static int mt7988_u30_phy_i2c0_pins[] = { 15, 16 }; -static int mt7988_u30_phy_i2c0_funcs[] = { 2, 2 }; - -static int mt7988_u32_phy_i2c0_pins[] = { 15, 16 }; -static int mt7988_u32_phy_i2c0_funcs[] = { 3, 3 }; - -static int mt7988_xfi_phy0_i2c1_pins[] = { 15, 16 }; -static int mt7988_xfi_phy0_i2c1_funcs[] = { 5, 5 }; - -static int mt7988_xfi_phy1_i2c1_pins[] = { 15, 16 }; -static int mt7988_xfi_phy1_i2c1_funcs[] = { 6, 6 }; - -static int mt7988_xfi_phy_pll_i2c2_pins[] = { 15, 16 }; -static int mt7988_xfi_phy_pll_i2c2_funcs[] = { 7, 7 }; - -static int mt7988_i2c1_0_pins[] = { 17, 18 }; -static int mt7988_i2c1_0_funcs[] = { 1, 1 }; - -static int mt7988_u30_phy_i2c1_pins[] = { 17, 18 }; -static int mt7988_u30_phy_i2c1_funcs[] = { 2, 2 }; - -static int mt7988_u32_phy_i2c1_pins[] = { 17, 18 }; -static int mt7988_u32_phy_i2c1_funcs[] = { 3, 3 }; - -static int mt7988_xfi_phy_pll_i2c3_pins[] = { 17, 18 }; -static int mt7988_xfi_phy_pll_i2c3_funcs[] = { 4, 4 }; - -static int mt7988_sgmii0_i2c_pins[] = { 17, 18 }; -static int mt7988_sgmii0_i2c_funcs[] = { 5, 5 }; - -static int mt7988_sgmii1_i2c_pins[] = { 17, 18 }; -static int mt7988_sgmii1_i2c_funcs[] = { 6, 6 }; - -static int mt7988_i2c1_2_pins[] = { 69, 70 }; -static int mt7988_i2c1_2_funcs[] = { 2, 2 }; - -static int mt7988_i2c2_0_pins[] = { 69, 70 }; -static int mt7988_i2c2_0_funcs[] = { 4, 4 }; - -static int mt7988_i2c2_1_pins[] = { 71, 72 }; -static int mt7988_i2c2_1_funcs[] = { 1, 1 }; - -/* eth */ -static int mt7988_mdc_mdio0_pins[] = { 5, 6 }; -static int mt7988_mdc_mdio0_funcs[] = { 1, 1 }; - -static int mt7988_2p5g_ext_mdio_pins[] = { 28, 29 }; -static int mt7988_2p5g_ext_mdio_funcs[] = { 6, 6 }; - -static int mt7988_gbe_ext_mdio_pins[] = { 30, 31 }; -static int mt7988_gbe_ext_mdio_funcs[] = { 6, 6 }; - -static int mt7988_mdc_mdio1_pins[] = { 69, 70 }; -static int mt7988_mdc_mdio1_funcs[] = { 1, 1 }; - -/* pcie */ -static int mt7988_pcie_wake_n0_0_pins[] = { 7 }; -static int mt7988_pcie_wake_n0_0_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n0_0_pins[] = { 8 }; -static int mt7988_pcie_clk_req_n0_0_funcs[] = { 1 }; - -static int mt7988_pcie_wake_n3_0_pins[] = { 9 }; -static int mt7988_pcie_wake_n3_0_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n3_pins[] = { 10 }; -static int mt7988_pcie_clk_req_n3_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n0_1_pins[] = { 10 }; -static int mt7988_pcie_clk_req_n0_1_funcs[] = { 2 }; - -static int mt7988_pcie_p0_phy_i2c_pins[] = { 7, 8 }; -static int mt7988_pcie_p0_phy_i2c_funcs[] = { 3, 3 }; - -static int mt7988_pcie_p1_phy_i2c_pins[] = { 7, 8 }; -static int mt7988_pcie_p1_phy_i2c_funcs[] = { 4, 4 }; - -static int mt7988_pcie_p3_phy_i2c_pins[] = { 9, 10 }; -static int mt7988_pcie_p3_phy_i2c_funcs[] = { 4, 4 }; - -static int mt7988_pcie_p2_phy_i2c_pins[] = { 7, 8 }; -static int mt7988_pcie_p2_phy_i2c_funcs[] = { 5, 5 }; - -static int mt7988_ckm_phy_i2c_pins[] = { 9, 10 }; -static int mt7988_ckm_phy_i2c_funcs[] = { 5, 5 }; - -static int mt7988_pcie_wake_n0_1_pins[] = { 13 }; -static int mt7988_pcie_wake_n0_1_funcs[] = { 2 }; - -static int mt7988_pcie_wake_n3_1_pins[] = { 14 }; -static int mt7988_pcie_wake_n3_1_funcs[] = { 2 }; - -static int mt7988_pcie_2l_0_pereset_pins[] = { 19 }; -static int mt7988_pcie_2l_0_pereset_funcs[] = { 1 }; - -static int mt7988_pcie_1l_1_pereset_pins[] = { 20 }; -static int mt7988_pcie_1l_1_pereset_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n2_1_pins[] = { 63 }; -static int mt7988_pcie_clk_req_n2_1_funcs[] = { 2 }; - -static int mt7988_pcie_2l_1_pereset_pins[] = { 73 }; -static int mt7988_pcie_2l_1_pereset_funcs[] = { 1 }; - -static int mt7988_pcie_1l_0_pereset_pins[] = { 74 }; -static int mt7988_pcie_1l_0_pereset_funcs[] = { 1 }; - -static int mt7988_pcie_wake_n1_0_pins[] = { 75 }; -static int mt7988_pcie_wake_n1_0_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n1_pins[] = { 76 }; -static int mt7988_pcie_clk_req_n1_funcs[] = { 1 }; - -static int mt7988_pcie_wake_n2_0_pins[] = { 77 }; -static int mt7988_pcie_wake_n2_0_funcs[] = { 1 }; - -static int mt7988_pcie_clk_req_n2_0_pins[] = { 78 }; -static int mt7988_pcie_clk_req_n2_0_funcs[] = { 1 }; - -static int mt7988_pcie_wake_n2_1_pins[] = { 79 }; -static int mt7988_pcie_wake_n2_1_funcs[] = { 2 }; - -/* pmic */ -static int mt7988_pmic_pins[] = { 11 }; -static int mt7988_pmic_funcs[] = { 1 }; - -/* watchdog */ -static int mt7988_watchdog_pins[] = { 12 }; -static int mt7988_watchdog_funcs[] = { 1 }; - -/* spi */ -static int mt7988_spi0_wp_hold_pins[] = { 22, 23 }; -static int mt7988_spi0_wp_hold_funcs[] = { 1, 1 }; - -static int mt7988_spi0_pins[] = { 24, 25, 26, 27 }; -static int mt7988_spi0_funcs[] = { 1, 1, 1, 1 }; - -static int mt7988_spi1_pins[] = { 28, 29, 30, 31 }; -static int mt7988_spi1_funcs[] = { 1, 1, 1, 1 }; - -static int mt7988_spi2_pins[] = { 32, 33, 34, 35 }; -static int mt7988_spi2_funcs[] = { 1, 1, 1, 1 }; - -static int mt7988_spi2_wp_hold_pins[] = { 36, 37 }; -static int mt7988_spi2_wp_hold_funcs[] = { 1, 1 }; - -/* flash */ -static int mt7988_snfi_pins[] = { 22, 23, 24, 25, 26, 27 }; -static int mt7988_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 }; - -static int mt7988_emmc_45_pins[] = { - 21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 -}; -static int mt7988_emmc_45_funcs[] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 }; - -static int mt7988_sdcard_pins[] = { 32, 33, 34, 35, 36, 37 }; -static int mt7988_sdcard_funcs[] = { 5, 5, 5, 5, 5, 5 }; - -static int mt7988_emmc_51_pins[] = { 38, 39, 40, 41, 42, 43, - 44, 45, 46, 47, 48, 49 }; -static int mt7988_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; - -/* uart */ -static int mt7988_uart2_pins[] = { 0, 1, 2, 3 }; -static int mt7988_uart2_funcs[] = { 1, 1, 1, 1 }; - -static int mt7988_tops_uart0_0_pins[] = { 22, 23 }; -static int mt7988_tops_uart0_0_funcs[] = { 3, 3 }; - -static int mt7988_uart2_0_pins[] = { 28, 29, 30, 31 }; -static int mt7988_uart2_0_funcs[] = { 2, 2, 2, 2 }; - -static int mt7988_uart1_0_pins[] = { 32, 33, 34, 35 }; -static int mt7988_uart1_0_funcs[] = { 2, 2, 2, 2 }; - -static int mt7988_uart2_1_pins[] = { 32, 33, 34, 35 }; -static int mt7988_uart2_1_funcs[] = { 3, 3, 3, 3 }; - -static int mt7988_net_wo0_uart_txd_0_pins[] = { 28 }; -static int mt7988_net_wo0_uart_txd_0_funcs[] = { 3 }; - -static int mt7988_net_wo1_uart_txd_0_pins[] = { 29 }; -static int mt7988_net_wo1_uart_txd_0_funcs[] = { 3 }; - -static int mt7988_net_wo2_uart_txd_0_pins[] = { 30 }; -static int mt7988_net_wo2_uart_txd_0_funcs[] = { 3 }; - -static int mt7988_tops_uart1_0_pins[] = { 28, 29 }; -static int mt7988_tops_uart1_0_funcs[] = { 4, 4 }; - -static int mt7988_tops_uart0_1_pins[] = { 30, 31 }; -static int mt7988_tops_uart0_1_funcs[] = { 4, 4 }; - -static int mt7988_tops_uart1_1_pins[] = { 36, 37 }; -static int mt7988_tops_uart1_1_funcs[] = { 3, 3 }; - -static int mt7988_uart0_pins[] = { 55, 56 }; -static int mt7988_uart0_funcs[] = { 1, 1 }; - -static int mt7988_tops_uart0_2_pins[] = { 55, 56 }; -static int mt7988_tops_uart0_2_funcs[] = { 2, 2 }; - -static int mt7988_uart2_2_pins[] = { 50, 51, 52, 53 }; -static int mt7988_uart2_2_funcs[] = { 2, 2, 2, 2 }; - -static int mt7988_uart1_1_pins[] = { 58, 59, 60, 61 }; -static int mt7988_uart1_1_funcs[] = { 2, 2, 2, 2 }; - -static int mt7988_uart2_3_pins[] = { 58, 59, 60, 61 }; -static int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 }; - -static int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 }; -static int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 }; - -static int mt7988_tops_uart1_2_pins[] = { 80, 81 }; -static int mt7988_tops_uart1_2_funcs[] = { - 4, - 4, -}; - -static int mt7988_net_wo0_uart_txd_1_pins[] = { 80 }; -static int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 }; - -static int mt7988_net_wo1_uart_txd_1_pins[] = { 81 }; -static int mt7988_net_wo1_uart_txd_1_funcs[] = { 3 }; - -static int mt7988_net_wo2_uart_txd_1_pins[] = { 82 }; -static int mt7988_net_wo2_uart_txd_1_funcs[] = { 3 }; - -/* udi */ -static int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 }; -static int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 }; - -/* i2s */ -static int mt7988_i2s_pins[] = { 50, 51, 52, 53, 54 }; -static int mt7988_i2s_funcs[] = { 1, 1, 1, 1, 1 }; - -/* pcm */ -static int mt7988_pcm_pins[] = { 50, 51, 52, 53 }; -static int mt7988_pcm_funcs[] = { 1, 1, 1, 1 }; - -/* led */ -static int mt7988_gbe0_led1_pins[] = { 58 }; -static int mt7988_gbe0_led1_funcs[] = { 6 }; -static int mt7988_gbe1_led1_pins[] = { 59 }; -static int mt7988_gbe1_led1_funcs[] = { 6 }; -static int mt7988_gbe2_led1_pins[] = { 60 }; -static int mt7988_gbe2_led1_funcs[] = { 6 }; -static int mt7988_gbe3_led1_pins[] = { 61 }; -static int mt7988_gbe3_led1_funcs[] = { 6 }; - -static int mt7988_2p5gbe_led1_pins[] = { 62 }; -static int mt7988_2p5gbe_led1_funcs[] = { 6 }; - -static int mt7988_gbe0_led0_pins[] = { 64 }; -static int mt7988_gbe0_led0_funcs[] = { 1 }; -static int mt7988_gbe1_led0_pins[] = { 65 }; -static int mt7988_gbe1_led0_funcs[] = { 1 }; -static int mt7988_gbe2_led0_pins[] = { 66 }; -static int mt7988_gbe2_led0_funcs[] = { 1 }; -static int mt7988_gbe3_led0_pins[] = { 67 }; -static int mt7988_gbe3_led0_funcs[] = { 1 }; - -static int mt7988_2p5gbe_led0_pins[] = { 68 }; -static int mt7988_2p5gbe_led0_funcs[] = { 1 }; - -/* usb */ -static int mt7988_drv_vbus_p1_pins[] = { 63 }; -static int mt7988_drv_vbus_p1_funcs[] = { 1 }; - -static int mt7988_drv_vbus_pins[] = { 79 }; -static int mt7988_drv_vbus_funcs[] = { 1 }; - -static const struct group_desc mt7988_groups[] = { - /* @GPIO(0,1,2,3): uart2 */ - PINCTRL_PIN_GROUP("uart2", mt7988_uart2), - /* @GPIO(0,1,2,3,4): tops_jtag0_0 */ - PINCTRL_PIN_GROUP("tops_jtag0_0", mt7988_tops_jtag0_0), - /* @GPIO(2,3): int_usxgmii */ - PINCTRL_PIN_GROUP("int_usxgmii", mt7988_int_usxgmii), - /* @GPIO(0,1,2,3,4): dfd */ - PINCTRL_PIN_GROUP("dfd", mt7988_dfd), - /* @GPIO(0,1): xfi_phy0_i2c0 */ - PINCTRL_PIN_GROUP("xfi_phy0_i2c0", mt7988_xfi_phy0_i2c0), - /* @GPIO(0,1): xfi_phy1_i2c0 */ - PINCTRL_PIN_GROUP("xfi_phy1_i2c0", mt7988_xfi_phy1_i2c0), - /* @GPIO(3,4): xfi_phy_pll_i2c0 */ - PINCTRL_PIN_GROUP("xfi_phy_pll_i2c0", mt7988_xfi_phy_pll_i2c0), - /* @GPIO(3,4): xfi_phy_pll_i2c1 */ - PINCTRL_PIN_GROUP("xfi_phy_pll_i2c1", mt7988_xfi_phy_pll_i2c1), - /* @GPIO(5,6) i2c0_0 */ - PINCTRL_PIN_GROUP("i2c0_0", mt7988_i2c0_0), - /* @GPIO(5,6) i2c1_sfp */ - PINCTRL_PIN_GROUP("i2c1_sfp", mt7988_i2c1_sfp), - /* @GPIO(5,6) xfi_pextp_phy0_i2c */ - PINCTRL_PIN_GROUP("xfi_pextp_phy0_i2c", mt7988_xfi_pextp_phy0_i2c), - /* @GPIO(5,6) xfi_pextp_phy1_i2c */ - PINCTRL_PIN_GROUP("xfi_pextp_phy1_i2c", mt7988_xfi_pextp_phy1_i2c), - /* @GPIO(5,6) mdc_mdio0 */ - PINCTRL_PIN_GROUP("mdc_mdio0", mt7988_mdc_mdio0), - /* @GPIO(7): pcie_wake_n0_0 */ - PINCTRL_PIN_GROUP("pcie_wake_n0_0", mt7988_pcie_wake_n0_0), - /* @GPIO(8): pcie_clk_req_n0_0 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n0_0", mt7988_pcie_clk_req_n0_0), - /* @GPIO(9): pcie_wake_n3_0 */ - PINCTRL_PIN_GROUP("pcie_wake_n3_0", mt7988_pcie_wake_n3_0), - /* @GPIO(10): pcie_clk_req_n3 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n3", mt7988_pcie_clk_req_n3), - /* @GPIO(10): pcie_clk_req_n0_1 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n0_1", mt7988_pcie_clk_req_n0_1), - /* @GPIO(7,8) pcie_p0_phy_i2c */ - PINCTRL_PIN_GROUP("pcie_p0_phy_i2c", mt7988_pcie_p0_phy_i2c), - /* @GPIO(7,8) pcie_p1_phy_i2c */ - PINCTRL_PIN_GROUP("pcie_p1_phy_i2c", mt7988_pcie_p1_phy_i2c), - /* @GPIO(7,8) pcie_p2_phy_i2c */ - PINCTRL_PIN_GROUP("pcie_p2_phy_i2c", mt7988_pcie_p2_phy_i2c), - /* @GPIO(9,10) pcie_p3_phy_i2c */ - PINCTRL_PIN_GROUP("pcie_p3_phy_i2c", mt7988_pcie_p3_phy_i2c), - /* @GPIO(9,10) ckm_phy_i2c */ - PINCTRL_PIN_GROUP("ckm_phy_i2c", mt7988_ckm_phy_i2c), - /* @GPIO(11): pmic */ - PINCTRL_PIN_GROUP("pcie_pmic", mt7988_pmic), - /* @GPIO(12): watchdog */ - PINCTRL_PIN_GROUP("watchdog", mt7988_watchdog), - /* @GPIO(13): pcie_wake_n0_1 */ - PINCTRL_PIN_GROUP("pcie_wake_n0_1", mt7988_pcie_wake_n0_1), - /* @GPIO(14): pcie_wake_n3_1 */ - PINCTRL_PIN_GROUP("pcie_wake_n3_1", mt7988_pcie_wake_n3_1), - /* @GPIO(15,16) i2c0_1 */ - PINCTRL_PIN_GROUP("i2c0_1", mt7988_i2c0_1), - /* @GPIO(15,16) u30_phy_i2c0 */ - PINCTRL_PIN_GROUP("u30_phy_i2c0", mt7988_u30_phy_i2c0), - /* @GPIO(15,16) u32_phy_i2c0 */ - PINCTRL_PIN_GROUP("u32_phy_i2c0", mt7988_u32_phy_i2c0), - /* @GPIO(15,16) xfi_phy0_i2c1 */ - PINCTRL_PIN_GROUP("xfi_phy0_i2c1", mt7988_xfi_phy0_i2c1), - /* @GPIO(15,16) xfi_phy1_i2c1 */ - PINCTRL_PIN_GROUP("xfi_phy1_i2c1", mt7988_xfi_phy1_i2c1), - /* @GPIO(15,16) xfi_phy_pll_i2c2 */ - PINCTRL_PIN_GROUP("xfi_phy_pll_i2c2", mt7988_xfi_phy_pll_i2c2), - /* @GPIO(17,18) i2c1_0 */ - PINCTRL_PIN_GROUP("i2c1_0", mt7988_i2c1_0), - /* @GPIO(17,18) u30_phy_i2c1 */ - PINCTRL_PIN_GROUP("u30_phy_i2c1", mt7988_u30_phy_i2c1), - /* @GPIO(17,18) u32_phy_i2c1 */ - PINCTRL_PIN_GROUP("u32_phy_i2c1", mt7988_u32_phy_i2c1), - /* @GPIO(17,18) xfi_phy_pll_i2c3 */ - PINCTRL_PIN_GROUP("xfi_phy_pll_i2c3", mt7988_xfi_phy_pll_i2c3), - /* @GPIO(17,18) sgmii0_i2c */ - PINCTRL_PIN_GROUP("sgmii0_i2c", mt7988_sgmii0_i2c), - /* @GPIO(17,18) sgmii1_i2c */ - PINCTRL_PIN_GROUP("sgmii1_i2c", mt7988_sgmii1_i2c), - /* @GPIO(19): pcie_2l_0_pereset */ - PINCTRL_PIN_GROUP("pcie_2l_0_pereset", mt7988_pcie_2l_0_pereset), - /* @GPIO(20): pcie_1l_1_pereset */ - PINCTRL_PIN_GROUP("pcie_1l_1_pereset", mt7988_pcie_1l_1_pereset), - /* @GPIO(21): pwm1 */ - PINCTRL_PIN_GROUP("pwm1", mt7988_pwm1), - /* @GPIO(22,23) spi0_wp_hold */ - PINCTRL_PIN_GROUP("spi0_wp_hold", mt7988_spi0_wp_hold), - /* @GPIO(24,25,26,27) spi0 */ - PINCTRL_PIN_GROUP("spi0", mt7988_spi0), - /* @GPIO(28,29,30,31) spi1 */ - PINCTRL_PIN_GROUP("spi1", mt7988_spi1), - /* @GPIO(32,33,34,35) spi2 */ - PINCTRL_PIN_GROUP("spi2", mt7988_spi2), - /* @GPIO(36,37) spi2_wp_hold */ - PINCTRL_PIN_GROUP("spi2_wp_hold", mt7988_spi2_wp_hold), - /* @GPIO(22,23,24,25,26,27) snfi */ - PINCTRL_PIN_GROUP("snfi", mt7988_snfi), - /* @GPIO(22,23) tops_uart0_0 */ - PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart0_0), - /* @GPIO(28,29,30,31) uart2_0 */ - PINCTRL_PIN_GROUP("uart2_0", mt7988_uart2_0), - /* @GPIO(32,33,34,35) uart1_0 */ - PINCTRL_PIN_GROUP("uart1_0", mt7988_uart1_0), - /* @GPIO(32,33,34,35) uart2_1 */ - PINCTRL_PIN_GROUP("uart2_1", mt7988_uart2_1), - /* @GPIO(28) net_wo0_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), - /* @GPIO(29) net_wo1_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), - /* @GPIO(30) net_wo2_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), - /* @GPIO(28,29) tops_uart1_0 */ - PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart1_0), - /* @GPIO(30,31) tops_uart0_1 */ - PINCTRL_PIN_GROUP("tops_uart0_1", mt7988_tops_uart0_1), - /* @GPIO(36,37) tops_uart1_1 */ - PINCTRL_PIN_GROUP("tops_uart1_1", mt7988_tops_uart1_1), - /* @GPIO(32,33,34,35,36) udi */ - PINCTRL_PIN_GROUP("udi", mt7988_udi), - /* @GPIO(21,28,29,30,31,32,33,34,35,36,37) emmc_45 */ - PINCTRL_PIN_GROUP("emmc_45", mt7988_emmc_45), - /* @GPIO(32,33,34,35,36,37) sdcard */ - PINCTRL_PIN_GROUP("sdcard", mt7988_sdcard), - /* @GPIO(38,39,40,41,42,43,44,45,46,47,48,49) emmc_51 */ - PINCTRL_PIN_GROUP("emmc_51", mt7988_emmc_51), - /* @GPIO(28,29) 2p5g_ext_mdio */ - PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio), - /* @GPIO(30,31) gbe_ext_mdio */ - PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio), - /* @GPIO(50,51,52,53,54) i2s */ - PINCTRL_PIN_GROUP("i2s", mt7988_i2s), - /* @GPIO(50,51,52,53) pcm */ - PINCTRL_PIN_GROUP("pcm", mt7988_pcm), - /* @GPIO(55,56) uart0 */ - PINCTRL_PIN_GROUP("uart0", mt7988_uart0), - /* @GPIO(55,56) tops_uart0_2 */ - PINCTRL_PIN_GROUP("tops_uart0_2", mt7988_tops_uart0_2), - /* @GPIO(50,51,52,53) uart2_2 */ - PINCTRL_PIN_GROUP("uart2_2", mt7988_uart2_2), - /* @GPIO(50,51,52,53,54) wo0_jtag */ - PINCTRL_PIN_GROUP("wo0_jtag", mt7988_wo0_jtag), - /* @GPIO(50,51,52,53,54) wo1-wo1_jtag */ - PINCTRL_PIN_GROUP("wo1_jtag", mt7988_wo1_jtag), - /* @GPIO(50,51,52,53,54) wo2_jtag */ - PINCTRL_PIN_GROUP("wo2_jtag", mt7988_wo2_jtag), - /* @GPIO(57) pwm0 */ - PINCTRL_PIN_GROUP("pwm0", mt7988_pwm0), - /* @GPIO(58,59,60,61,62) jtag */ - PINCTRL_PIN_GROUP("jtag", mt7988_jtag), - /* @GPIO(58,59,60,61,62) tops_jtag0_1 */ - PINCTRL_PIN_GROUP("tops_jtag0_1", mt7988_tops_jtag0_1), - /* @GPIO(58,59,60,61) uart2_3 */ - PINCTRL_PIN_GROUP("uart2_3", mt7988_uart2_3), - /* @GPIO(58,59,60,61) uart1_1 */ - PINCTRL_PIN_GROUP("uart1_1", mt7988_uart1_1), - /* @GPIO(58,59,60,61) gbe_led1 */ - PINCTRL_PIN_GROUP("gbe0_led1", mt7988_gbe0_led1), - PINCTRL_PIN_GROUP("gbe1_led1", mt7988_gbe1_led1), - PINCTRL_PIN_GROUP("gbe2_led1", mt7988_gbe2_led1), - PINCTRL_PIN_GROUP("gbe3_led1", mt7988_gbe3_led1), - /* @GPIO(62) 2p5gbe_led1 */ - PINCTRL_PIN_GROUP("2p5gbe_led1", mt7988_2p5gbe_led1), - /* @GPIO(64,65,66,67) gbe_led0 */ - PINCTRL_PIN_GROUP("gbe0_led0", mt7988_gbe0_led0), - PINCTRL_PIN_GROUP("gbe1_led0", mt7988_gbe1_led0), - PINCTRL_PIN_GROUP("gbe2_led0", mt7988_gbe2_led0), - PINCTRL_PIN_GROUP("gbe3_led0", mt7988_gbe3_led0), - /* @GPIO(68) 2p5gbe_led0 */ - PINCTRL_PIN_GROUP("2p5gbe_led0", mt7988_2p5gbe_led0), - /* @GPIO(63) drv_vbus_p1 */ - PINCTRL_PIN_GROUP("drv_vbus_p1", mt7988_drv_vbus_p1), - /* @GPIO(63) pcie_clk_req_n2_1 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n2_1", mt7988_pcie_clk_req_n2_1), - /* @GPIO(69, 70) mdc_mdio1 */ - PINCTRL_PIN_GROUP("mdc_mdio1", mt7988_mdc_mdio1), - /* @GPIO(69, 70) i2c1_2 */ - PINCTRL_PIN_GROUP("i2c1_2", mt7988_i2c1_2), - /* @GPIO(69) pwm6 */ - PINCTRL_PIN_GROUP("pwm6", mt7988_pwm6), - /* @GPIO(70) pwm7 */ - PINCTRL_PIN_GROUP("pwm7", mt7988_pwm7), - /* @GPIO(69,70) i2c2_0 */ - PINCTRL_PIN_GROUP("i2c2_0", mt7988_i2c2_0), - /* @GPIO(71,72) i2c2_1 */ - PINCTRL_PIN_GROUP("i2c2_1", mt7988_i2c2_1), - /* @GPIO(73) pcie_2l_1_pereset */ - PINCTRL_PIN_GROUP("pcie_2l_1_pereset", mt7988_pcie_2l_1_pereset), - /* @GPIO(74) pcie_1l_0_pereset */ - PINCTRL_PIN_GROUP("pcie_1l_0_pereset", mt7988_pcie_1l_0_pereset), - /* @GPIO(75) pcie_wake_n1_0 */ - PINCTRL_PIN_GROUP("pcie_wake_n1_0", mt7988_pcie_wake_n1_0), - /* @GPIO(76) pcie_clk_req_n1 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n1", mt7988_pcie_clk_req_n1), - /* @GPIO(77) pcie_wake_n2_0 */ - PINCTRL_PIN_GROUP("pcie_wake_n2_0", mt7988_pcie_wake_n2_0), - /* @GPIO(78) pcie_clk_req_n2_0 */ - PINCTRL_PIN_GROUP("pcie_clk_req_n2_0", mt7988_pcie_clk_req_n2_0), - /* @GPIO(79) drv_vbus */ - PINCTRL_PIN_GROUP("drv_vbus", mt7988_drv_vbus), - /* @GPIO(79) pcie_wake_n2_1 */ - PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1), - /* @GPIO(80,81,82,83) uart1_2 */ - PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2), - /* @GPIO(80) pwm2 */ - PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2), - /* @GPIO(81) pwm3 */ - PINCTRL_PIN_GROUP("pwm3", mt7988_pwm3), - /* @GPIO(82) pwm4 */ - PINCTRL_PIN_GROUP("pwm4", mt7988_pwm4), - /* @GPIO(83) pwm5 */ - PINCTRL_PIN_GROUP("pwm5", mt7988_pwm5), - /* @GPIO(80) net_wo0_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), - /* @GPIO(81) net_wo1_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), - /* @GPIO(82) net_wo2_uart_txd_0 */ - PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), - /* @GPIO(80,81) tops_uart1_2 */ - PINCTRL_PIN_GROUP("tops_uart1_2", mt7988_tops_uart1_2), - /* @GPIO(80) net_wo0_uart_txd_1 */ - PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7988_net_wo0_uart_txd_1), - /* @GPIO(81) net_wo1_uart_txd_1 */ - PINCTRL_PIN_GROUP("net_wo1_uart_txd_1", mt7988_net_wo1_uart_txd_1), - /* @GPIO(82) net_wo2_uart_txd_1 */ - PINCTRL_PIN_GROUP("net_wo2_uart_txd_1", mt7988_net_wo2_uart_txd_1), -}; - -/* Joint those groups owning the same capability in user point of view which - * allows that people tend to use through the device tree. - */ -static const char * const mt7988_jtag_groups[] = { - "tops_jtag0_0", "wo0_jtag", "wo1_jtag", - "wo2_jtag", "jtag", "tops_jtag0_1", -}; -static const char * const mt7988_int_usxgmii_groups[] = { - "int_usxgmii", -}; -static const char * const mt7988_pwm_groups[] = { - "pwm0", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7" -}; -static const char * const mt7988_dfd_groups[] = { - "dfd", -}; -static const char * const mt7988_i2c_groups[] = { - "xfi_phy0_i2c0", - "xfi_phy1_i2c0", - "xfi_phy_pll_i2c0", - "xfi_phy_pll_i2c1", - "i2c0_0", - "i2c1_sfp", - "xfi_pextp_phy0_i2c", - "xfi_pextp_phy1_i2c", - "i2c0_1", - "u30_phy_i2c0", - "u32_phy_i2c0", - "xfi_phy0_i2c1", - "xfi_phy1_i2c1", - "xfi_phy_pll_i2c2", - "i2c1_0", - "u30_phy_i2c1", - "u32_phy_i2c1", - "xfi_phy_pll_i2c3", - "sgmii0_i2c", - "sgmii1_i2c", - "i2c1_2", - "i2c2_0", - "i2c2_1", -}; -static const char * const mt7988_ethernet_groups[] = { - "mdc_mdio0", - "2p5g_ext_mdio", - "gbe_ext_mdio", - "mdc_mdio1", -}; -static const char * const mt7988_pcie_groups[] = { - "pcie_wake_n0_0", "pcie_clk_req_n0_0", "pcie_wake_n3_0", - "pcie_clk_req_n3", "pcie_p0_phy_i2c", "pcie_p1_phy_i2c", - "pcie_p3_phy_i2c", "pcie_p2_phy_i2c", "ckm_phy_i2c", - "pcie_wake_n0_1", "pcie_wake_n3_1", "pcie_2l_0_pereset", - "pcie_1l_1_pereset", "pcie_clk_req_n2_1", "pcie_2l_1_pereset", - "pcie_1l_0_pereset", "pcie_wake_n1_0", "pcie_clk_req_n1", - "pcie_wake_n2_0", "pcie_clk_req_n2_0", "pcie_wake_n2_1", - "pcie_clk_req_n0_1" -}; -static const char * const mt7988_pmic_groups[] = { - "pmic", -}; -static const char * const mt7988_wdt_groups[] = { - "watchdog", -}; -static const char * const mt7988_spi_groups[] = { - "spi0", "spi0_wp_hold", "spi1", "spi2", "spi2_wp_hold", -}; -static const char * const mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi", - "emmc_51" }; -static const char * const mt7988_uart_groups[] = { - "uart2", - "tops_uart0_0", - "uart2_0", - "uart1_0", - "uart2_1", - "net_wo0_uart_txd_0", - "net_wo1_uart_txd_0", - "net_wo2_uart_txd_0", - "tops_uart1_0", - "ops_uart0_1", - "ops_uart1_1", - "uart0", - "tops_uart0_2", - "uart1_1", - "uart2_3", - "uart1_2", - "tops_uart1_2", - "net_wo0_uart_txd_1", - "net_wo1_uart_txd_1", - "net_wo2_uart_txd_1", -}; -static const char * const mt7988_udi_groups[] = { - "udi", -}; -static const char * const mt7988_audio_groups[] = { - "i2s", "pcm", -}; -static const char * const mt7988_led_groups[] = { - "gbe0_led1", "gbe1_led1", "gbe2_led1", "gbe3_led1", "2p5gbe_led1", - "gbe0_led0", "gbe1_led0", "gbe2_led0", "gbe3_led0", "2p5gbe_led0", - "wf5g_led0", "wf5g_led1", -}; -static const char * const mt7988_usb_groups[] = { - "drv_vbus", - "drv_vbus_p1", -}; - -static const struct function_desc mt7988_functions[] = { - { "audio", mt7988_audio_groups, ARRAY_SIZE(mt7988_audio_groups) }, - { "jtag", mt7988_jtag_groups, ARRAY_SIZE(mt7988_jtag_groups) }, - { "int_usxgmii", mt7988_int_usxgmii_groups, - ARRAY_SIZE(mt7988_int_usxgmii_groups) }, - { "pwm", mt7988_pwm_groups, ARRAY_SIZE(mt7988_pwm_groups) }, - { "dfd", mt7988_dfd_groups, ARRAY_SIZE(mt7988_dfd_groups) }, - { "i2c", mt7988_i2c_groups, ARRAY_SIZE(mt7988_i2c_groups) }, - { "eth", mt7988_ethernet_groups, ARRAY_SIZE(mt7988_ethernet_groups) }, - { "pcie", mt7988_pcie_groups, ARRAY_SIZE(mt7988_pcie_groups) }, - { "pmic", mt7988_pmic_groups, ARRAY_SIZE(mt7988_pmic_groups) }, - { "watchdog", mt7988_wdt_groups, ARRAY_SIZE(mt7988_wdt_groups) }, - { "spi", mt7988_spi_groups, ARRAY_SIZE(mt7988_spi_groups) }, - { "flash", mt7988_flash_groups, ARRAY_SIZE(mt7988_flash_groups) }, - { "uart", mt7988_uart_groups, ARRAY_SIZE(mt7988_uart_groups) }, - { "udi", mt7988_udi_groups, ARRAY_SIZE(mt7988_udi_groups) }, - { "usb", mt7988_usb_groups, ARRAY_SIZE(mt7988_usb_groups) }, - { "led", mt7988_led_groups, ARRAY_SIZE(mt7988_led_groups) }, -}; - -static const struct mtk_eint_hw mt7988_eint_hw = { - .port_mask = 7, - .ports = 7, - .ap_num = ARRAY_SIZE(mt7988_pins), - .db_cnt = 16, -}; - -static const char * const mt7988_pinctrl_register_base_names[] = { - "gpio_base", "iocfg_tr_base", "iocfg_br_base", - "iocfg_rb_base", "iocfg_lb_base", "iocfg_tl_base", -}; - -static struct mtk_pin_soc mt7988_data = { - .reg_cal = mt7988_reg_cals, - .pins = mt7988_pins, - .npins = ARRAY_SIZE(mt7988_pins), - .grps = mt7988_groups, - .ngrps = ARRAY_SIZE(mt7988_groups), - .funcs = mt7988_functions, - .nfuncs = ARRAY_SIZE(mt7988_functions), - .eint_hw = &mt7988_eint_hw, - .gpio_m = 0, - .ies_present = false, - .base_names = mt7988_pinctrl_register_base_names, - .nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names), - .bias_disable_set = mtk_pinconf_bias_disable_set, - .bias_disable_get = mtk_pinconf_bias_disable_get, - .bias_set = mtk_pinconf_bias_set, - .bias_get = mtk_pinconf_bias_get, - .drive_set = mtk_pinconf_drive_set_rev1, - .drive_get = mtk_pinconf_drive_get_rev1, - .adv_pull_get = mtk_pinconf_adv_pull_get, - .adv_pull_set = mtk_pinconf_adv_pull_set, -}; - -static const struct of_device_id mt7988_pinctrl_of_match[] = { - { - .compatible = "mediatek,mt7988-pinctrl", - }, - {} -}; - -static int mt7988_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_moore_pinctrl_probe(pdev, &mt7988_data); -} - -static struct platform_driver mt7988_pinctrl_driver = { - .driver = { - .name = "mt7988-pinctrl", - .of_match_table = mt7988_pinctrl_of_match, - }, - .probe = mt7988_pinctrl_probe, -}; - -static int __init mt7988_pinctrl_init(void) -{ - return platform_driver_register(&mt7988_pinctrl_driver); -} -arch_initcall(mt7988_pinctrl_init); - diff --git a/6.1/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mediatek,mt7988-clk.h b/6.1/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mediatek,mt7988-clk.h deleted file mode 100644 index 77cfea4a..00000000 --- a/6.1/target/linux/mediatek/files-6.1/include/dt-bindings/clock/mediatek,mt7988-clk.h +++ /dev/null @@ -1,276 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -/* - * Copyright (c) 2023 MediaTek Inc. - * Author: Sam Shih - * Author: Xiufeng Li - */ - -#ifndef _DT_BINDINGS_CLK_MT7988_H -#define _DT_BINDINGS_CLK_MT7988_H - -/* APMIXEDSYS */ - -#define CLK_APMIXED_NETSYSPLL 0 -#define CLK_APMIXED_MPLL 1 -#define CLK_APMIXED_MMPLL 2 -#define CLK_APMIXED_APLL2 3 -#define CLK_APMIXED_NET1PLL 4 -#define CLK_APMIXED_NET2PLL 5 -#define CLK_APMIXED_WEDMCUPLL 6 -#define CLK_APMIXED_SGMPLL 7 -#define CLK_APMIXED_ARM_B 8 -#define CLK_APMIXED_CCIPLL2_B 9 -#define CLK_APMIXED_USXGMIIPLL 10 -#define CLK_APMIXED_MSDCPLL 11 - -/* TOPCKGEN */ - -#define CLK_TOP_XTAL 0 -#define CLK_TOP_XTAL_D2 1 -#define CLK_TOP_RTC_32K 2 -#define CLK_TOP_RTC_32P7K 3 -#define CLK_TOP_MPLL_D2 4 -#define CLK_TOP_MPLL_D3_D2 5 -#define CLK_TOP_MPLL_D4 6 -#define CLK_TOP_MPLL_D8 7 -#define CLK_TOP_MPLL_D8_D2 8 -#define CLK_TOP_MMPLL_D2 9 -#define CLK_TOP_MMPLL_D3_D5 10 -#define CLK_TOP_MMPLL_D4 11 -#define CLK_TOP_MMPLL_D6_D2 12 -#define CLK_TOP_MMPLL_D8 13 -#define CLK_TOP_APLL2_D4 14 -#define CLK_TOP_NET1PLL_D4 15 -#define CLK_TOP_NET1PLL_D5 16 -#define CLK_TOP_NET1PLL_D5_D2 17 -#define CLK_TOP_NET1PLL_D5_D4 18 -#define CLK_TOP_NET1PLL_D8 19 -#define CLK_TOP_NET1PLL_D8_D2 20 -#define CLK_TOP_NET1PLL_D8_D4 21 -#define CLK_TOP_NET1PLL_D8_D8 22 -#define CLK_TOP_NET1PLL_D8_D16 23 -#define CLK_TOP_NET2PLL_D2 24 -#define CLK_TOP_NET2PLL_D4 25 -#define CLK_TOP_NET2PLL_D4_D4 26 -#define CLK_TOP_NET2PLL_D4_D8 27 -#define CLK_TOP_NET2PLL_D6 28 -#define CLK_TOP_NET2PLL_D8 29 -#define CLK_TOP_NETSYS_SEL 30 -#define CLK_TOP_NETSYS_500M_SEL 31 -#define CLK_TOP_NETSYS_2X_SEL 32 -#define CLK_TOP_NETSYS_GSW_SEL 33 -#define CLK_TOP_ETH_GMII_SEL 34 -#define CLK_TOP_NETSYS_MCU_SEL 35 -#define CLK_TOP_NETSYS_PAO_2X_SEL 36 -#define CLK_TOP_EIP197_SEL 37 -#define CLK_TOP_AXI_INFRA_SEL 38 -#define CLK_TOP_UART_SEL 39 -#define CLK_TOP_EMMC_250M_SEL 40 -#define CLK_TOP_EMMC_400M_SEL 41 -#define CLK_TOP_SPI_SEL 42 -#define CLK_TOP_SPIM_MST_SEL 43 -#define CLK_TOP_NFI1X_SEL 44 -#define CLK_TOP_SPINFI_SEL 45 -#define CLK_TOP_PWM_SEL 46 -#define CLK_TOP_I2C_SEL 47 -#define CLK_TOP_PCIE_MBIST_250M_SEL 48 -#define CLK_TOP_PEXTP_TL_SEL 49 -#define CLK_TOP_PEXTP_TL_P1_SEL 50 -#define CLK_TOP_PEXTP_TL_P2_SEL 51 -#define CLK_TOP_PEXTP_TL_P3_SEL 52 -#define CLK_TOP_USB_SYS_SEL 53 -#define CLK_TOP_USB_SYS_P1_SEL 54 -#define CLK_TOP_USB_XHCI_SEL 55 -#define CLK_TOP_USB_XHCI_P1_SEL 56 -#define CLK_TOP_USB_FRMCNT_SEL 57 -#define CLK_TOP_USB_FRMCNT_P1_SEL 58 -#define CLK_TOP_AUD_SEL 59 -#define CLK_TOP_A1SYS_SEL 60 -#define CLK_TOP_AUD_L_SEL 61 -#define CLK_TOP_A_TUNER_SEL 62 -#define CLK_TOP_SSPXTP_SEL 63 -#define CLK_TOP_USB_PHY_SEL 64 -#define CLK_TOP_USXGMII_SBUS_0_SEL 65 -#define CLK_TOP_USXGMII_SBUS_1_SEL 66 -#define CLK_TOP_SGM_0_SEL 67 -#define CLK_TOP_SGM_SBUS_0_SEL 68 -#define CLK_TOP_SGM_1_SEL 69 -#define CLK_TOP_SGM_SBUS_1_SEL 70 -#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71 -#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72 -#define CLK_TOP_SYSAXI_SEL 73 -#define CLK_TOP_SYSAPB_SEL 74 -#define CLK_TOP_ETH_REFCK_50M_SEL 75 -#define CLK_TOP_ETH_SYS_200M_SEL 76 -#define CLK_TOP_ETH_SYS_SEL 77 -#define CLK_TOP_ETH_XGMII_SEL 78 -#define CLK_TOP_BUS_TOPS_SEL 79 -#define CLK_TOP_NPU_TOPS_SEL 80 -#define CLK_TOP_DRAMC_SEL 81 -#define CLK_TOP_DRAMC_MD32_SEL 82 -#define CLK_TOP_INFRA_F26M_SEL 83 -#define CLK_TOP_PEXTP_P0_SEL 84 -#define CLK_TOP_PEXTP_P1_SEL 85 -#define CLK_TOP_PEXTP_P2_SEL 86 -#define CLK_TOP_PEXTP_P3_SEL 87 -#define CLK_TOP_DA_XTP_GLB_P0_SEL 88 -#define CLK_TOP_DA_XTP_GLB_P1_SEL 89 -#define CLK_TOP_DA_XTP_GLB_P2_SEL 90 -#define CLK_TOP_DA_XTP_GLB_P3_SEL 91 -#define CLK_TOP_CKM_SEL 92 -#define CLK_TOP_DA_SEL 93 -#define CLK_TOP_PEXTP_SEL 94 -#define CLK_TOP_TOPS_P2_26M_SEL 95 -#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96 -#define CLK_TOP_NETSYS_SYNC_250M_SEL 97 -#define CLK_TOP_MACSEC_SEL 98 -#define CLK_TOP_NETSYS_TOPS_400M_SEL 99 -#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100 -#define CLK_TOP_NETSYS_WARP_SEL 101 -#define CLK_TOP_ETH_MII_SEL 102 -#define CLK_TOP_NPU_SEL 103 -#define CLK_TOP_AUD_I2S_M 104 - -/* MCUSYS */ - -#define CLK_MCU_BUS_DIV_SEL 0 -#define CLK_MCU_ARM_DIV_SEL 1 - -/* INFRACFG_AO */ - -#define CLK_INFRA_MUX_UART0_SEL 0 -#define CLK_INFRA_MUX_UART1_SEL 1 -#define CLK_INFRA_MUX_UART2_SEL 2 -#define CLK_INFRA_MUX_SPI0_SEL 3 -#define CLK_INFRA_MUX_SPI1_SEL 4 -#define CLK_INFRA_MUX_SPI2_SEL 5 -#define CLK_INFRA_PWM_SEL 6 -#define CLK_INFRA_PWM_CK1_SEL 7 -#define CLK_INFRA_PWM_CK2_SEL 8 -#define CLK_INFRA_PWM_CK3_SEL 9 -#define CLK_INFRA_PWM_CK4_SEL 10 -#define CLK_INFRA_PWM_CK5_SEL 11 -#define CLK_INFRA_PWM_CK6_SEL 12 -#define CLK_INFRA_PWM_CK7_SEL 13 -#define CLK_INFRA_PWM_CK8_SEL 14 -#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15 -#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16 -#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17 -#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18 - -/* INFRACFG */ - -#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19 -#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20 -#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21 -#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22 -#define CLK_INFRA_66M_GPT_BCK 23 -#define CLK_INFRA_66M_PWM_HCK 24 -#define CLK_INFRA_66M_PWM_BCK 25 -#define CLK_INFRA_66M_PWM_CK1 26 -#define CLK_INFRA_66M_PWM_CK2 27 -#define CLK_INFRA_66M_PWM_CK3 28 -#define CLK_INFRA_66M_PWM_CK4 29 -#define CLK_INFRA_66M_PWM_CK5 30 -#define CLK_INFRA_66M_PWM_CK6 31 -#define CLK_INFRA_66M_PWM_CK7 32 -#define CLK_INFRA_66M_PWM_CK8 33 -#define CLK_INFRA_133M_CQDMA_BCK 34 -#define CLK_INFRA_66M_AUD_SLV_BCK 35 -#define CLK_INFRA_AUD_26M 36 -#define CLK_INFRA_AUD_L 37 -#define CLK_INFRA_AUD_AUD 38 -#define CLK_INFRA_AUD_EG2 39 -#define CLK_INFRA_DRAMC_F26M 40 -#define CLK_INFRA_133M_DBG_ACKM 41 -#define CLK_INFRA_66M_AP_DMA_BCK 42 -#define CLK_INFRA_66M_SEJ_BCK 43 -#define CLK_INFRA_PRE_CK_SEJ_F13M 44 -#define CLK_INFRA_26M_THERM_SYSTEM 45 -#define CLK_INFRA_I2C_BCK 46 -#define CLK_INFRA_52M_UART0_CK 47 -#define CLK_INFRA_52M_UART1_CK 48 -#define CLK_INFRA_52M_UART2_CK 49 -#define CLK_INFRA_NFI 50 -#define CLK_INFRA_SPINFI 51 -#define CLK_INFRA_66M_NFI_HCK 52 -#define CLK_INFRA_104M_SPI0 53 -#define CLK_INFRA_104M_SPI1 54 -#define CLK_INFRA_104M_SPI2_BCK 55 -#define CLK_INFRA_66M_SPI0_HCK 56 -#define CLK_INFRA_66M_SPI1_HCK 57 -#define CLK_INFRA_66M_SPI2_HCK 58 -#define CLK_INFRA_66M_FLASHIF_AXI 59 -#define CLK_INFRA_RTC 60 -#define CLK_INFRA_26M_ADC_BCK 61 -#define CLK_INFRA_RC_ADC 62 -#define CLK_INFRA_MSDC400 63 -#define CLK_INFRA_MSDC2_HCK 64 -#define CLK_INFRA_133M_MSDC_0_HCK 65 -#define CLK_INFRA_66M_MSDC_0_HCK 66 -#define CLK_INFRA_133M_CPUM_BCK 67 -#define CLK_INFRA_BIST2FPC 68 -#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69 -#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70 -#define CLK_INFRA_133M_USB_HCK 71 -#define CLK_INFRA_133M_USB_HCK_CK_P1 72 -#define CLK_INFRA_66M_USB_HCK 73 -#define CLK_INFRA_66M_USB_HCK_CK_P1 74 -#define CLK_INFRA_USB_SYS 75 -#define CLK_INFRA_USB_SYS_CK_P1 76 -#define CLK_INFRA_USB_REF 77 -#define CLK_INFRA_USB_CK_P1 78 -#define CLK_INFRA_USB_FRMCNT 79 -#define CLK_INFRA_USB_FRMCNT_CK_P1 80 -#define CLK_INFRA_USB_PIPE 81 -#define CLK_INFRA_USB_PIPE_CK_P1 82 -#define CLK_INFRA_USB_UTMI 83 -#define CLK_INFRA_USB_UTMI_CK_P1 84 -#define CLK_INFRA_USB_XHCI 85 -#define CLK_INFRA_USB_XHCI_CK_P1 86 -#define CLK_INFRA_PCIE_GFMUX_TL_P0 87 -#define CLK_INFRA_PCIE_GFMUX_TL_P1 88 -#define CLK_INFRA_PCIE_GFMUX_TL_P2 89 -#define CLK_INFRA_PCIE_GFMUX_TL_P3 90 -#define CLK_INFRA_PCIE_PIPE_P0 91 -#define CLK_INFRA_PCIE_PIPE_P1 92 -#define CLK_INFRA_PCIE_PIPE_P2 93 -#define CLK_INFRA_PCIE_PIPE_P3 94 -#define CLK_INFRA_133M_PCIE_CK_P0 95 -#define CLK_INFRA_133M_PCIE_CK_P1 96 -#define CLK_INFRA_133M_PCIE_CK_P2 97 -#define CLK_INFRA_133M_PCIE_CK_P3 98 - -/* ETHDMA */ - -#define CLK_ETHDMA_XGP1_EN 0 -#define CLK_ETHDMA_XGP2_EN 1 -#define CLK_ETHDMA_XGP3_EN 2 -#define CLK_ETHDMA_FE_EN 3 -#define CLK_ETHDMA_GP2_EN 4 -#define CLK_ETHDMA_GP1_EN 5 -#define CLK_ETHDMA_GP3_EN 6 -#define CLK_ETHDMA_ESW_EN 7 -#define CLK_ETHDMA_CRYPT0_EN 8 -#define CLK_ETHDMA_NR_CLK 9 - -/* SGMIISYS_0 */ - -#define CLK_SGM0_TX_EN 0 -#define CLK_SGM0_RX_EN 1 -#define CLK_SGMII0_NR_CLK 2 - -/* SGMIISYS_1 */ - -#define CLK_SGM1_TX_EN 0 -#define CLK_SGM1_RX_EN 1 -#define CLK_SGMII1_NR_CLK 2 - -/* ETHWARP */ - -#define CLK_ETHWARP_WOCPU2_EN 0 -#define CLK_ETHWARP_WOCPU1_EN 1 -#define CLK_ETHWARP_WOCPU0_EN 2 -#define CLK_ETHWARP_NR_CLK 3 - -#endif /* _DT_BINDINGS_CLK_MT7988_H */ diff --git a/6.1/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_mdio.c b/6.1/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_mdio.c deleted file mode 100644 index 08d2b57d..00000000 --- a/6.1/target/linux/mediatek/files/drivers/net/phy/rtk/rtl8367s_mdio.c +++ /dev/null @@ -1,309 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include - - -#include "./rtl8367c/include/rtk_switch.h" -#include "./rtl8367c/include/port.h" -#include "./rtl8367c/include/vlan.h" -#include "./rtl8367c/include/rtl8367c_asicdrv_port.h" - -struct rtk_gsw { - struct device *dev; - struct mii_bus *bus; - int reset_pin; -}; - -static struct rtk_gsw *_gsw; - -extern int gsw_debug_proc_init(void); -extern void gsw_debug_proc_exit(void); - -#ifdef CONFIG_SWCONFIG -extern int rtl8367s_swconfig_init( void (*reset_func)(void) ); -#endif - -/*mii_mgr_read/mii_mgr_write is the callback API for rtl8367 driver*/ -unsigned int mii_mgr_read(unsigned int phy_addr,unsigned int phy_register,unsigned int *read_data) -{ - struct mii_bus *bus = _gsw->bus; - - mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); - - *read_data = bus->read(bus, phy_addr, phy_register); - - mutex_unlock(&bus->mdio_lock); - - return 0; -} - -unsigned int mii_mgr_write(unsigned int phy_addr,unsigned int phy_register,unsigned int write_data) -{ - struct mii_bus *bus = _gsw->bus; - - mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); - - bus->write(bus, phy_addr, phy_register, write_data); - - mutex_unlock(&bus->mdio_lock); - - return 0; -} - -static int rtl8367s_hw_reset(void) -{ - struct rtk_gsw *gsw = _gsw; - - if (gsw->reset_pin < 0) - return 0; - - gpio_direction_output(gsw->reset_pin, 0); - - usleep_range(1000, 1100); - - gpio_set_value(gsw->reset_pin, 1); - - mdelay(500); - - return 0; -} - -static int rtl8367s_vlan_config(int want_at_p0) -{ - rtk_vlan_cfg_t vlan1, vlan2; - - /* Set LAN/WAN VLAN partition */ - memset(&vlan1, 0x00, sizeof(rtk_vlan_cfg_t)); - - RTK_PORTMASK_PORT_SET(vlan1.mbr, EXT_PORT0); - RTK_PORTMASK_PORT_SET(vlan1.mbr, UTP_PORT1); - RTK_PORTMASK_PORT_SET(vlan1.mbr, UTP_PORT2); - RTK_PORTMASK_PORT_SET(vlan1.mbr, UTP_PORT3); - RTK_PORTMASK_PORT_SET(vlan1.untag, EXT_PORT0); - RTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT1); - RTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT2); - RTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT3); - - if (want_at_p0) { - RTK_PORTMASK_PORT_SET(vlan1.mbr, UTP_PORT4); - RTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT4); - } else { - RTK_PORTMASK_PORT_SET(vlan1.mbr, UTP_PORT0); - RTK_PORTMASK_PORT_SET(vlan1.untag, UTP_PORT0); - } - - vlan1.ivl_en = 1; - - rtk_vlan_set(1, &vlan1); - - memset(&vlan2, 0x00, sizeof(rtk_vlan_cfg_t)); - - RTK_PORTMASK_PORT_SET(vlan2.mbr, EXT_PORT1); - RTK_PORTMASK_PORT_SET(vlan2.untag, EXT_PORT1); - - if (want_at_p0) { - RTK_PORTMASK_PORT_SET(vlan2.mbr, UTP_PORT0); - RTK_PORTMASK_PORT_SET(vlan2.untag, UTP_PORT0); - } else { - RTK_PORTMASK_PORT_SET(vlan2.mbr, UTP_PORT4); - RTK_PORTMASK_PORT_SET(vlan2.untag, UTP_PORT4); - } - - vlan2.ivl_en = 1; - rtk_vlan_set(2, &vlan2); - - rtk_vlan_portPvid_set(EXT_PORT0, 1, 0); - rtk_vlan_portPvid_set(UTP_PORT1, 1, 0); - rtk_vlan_portPvid_set(UTP_PORT2, 1, 0); - rtk_vlan_portPvid_set(UTP_PORT3, 1, 0); - rtk_vlan_portPvid_set(EXT_PORT1, 2, 0); - - if (want_at_p0) { - rtk_vlan_portPvid_set(UTP_PORT0, 2, 0); - rtk_vlan_portPvid_set(UTP_PORT4, 1, 0); - } else { - rtk_vlan_portPvid_set(UTP_PORT0, 1, 0); - rtk_vlan_portPvid_set(UTP_PORT4, 2, 0); - } - - return 0; -} - -static int rtl8367s_hw_init(void) -{ - - rtl8367s_hw_reset(); - - if(rtk_switch_init()) - return -1; - - mdelay(500); - - if (rtk_vlan_reset()) - return -1; - - if (rtk_vlan_init()) - return -1; - - return 0; -} - -static void set_rtl8367s_sgmii(void) -{ - rtk_port_mac_ability_t mac_cfg; - rtk_mode_ext_t mode; - - mode = MODE_EXT_HSGMII; - mac_cfg.forcemode = MAC_FORCE; - mac_cfg.speed = PORT_SPEED_2500M; - mac_cfg.duplex = PORT_FULL_DUPLEX; - mac_cfg.link = PORT_LINKUP; - mac_cfg.nway = DISABLED; - mac_cfg.txpause = ENABLED; - mac_cfg.rxpause = ENABLED; - rtk_port_macForceLinkExt_set(EXT_PORT0, mode, &mac_cfg); - rtk_port_sgmiiNway_set(EXT_PORT0, DISABLED); - rtk_port_phyEnableAll_set(ENABLED); - -} - -static void set_rtl8367s_rgmii(void) -{ - rtk_port_mac_ability_t mac_cfg; - rtk_mode_ext_t mode; - - mode = MODE_EXT_RGMII; - mac_cfg.forcemode = MAC_FORCE; - mac_cfg.speed = PORT_SPEED_1000M; - mac_cfg.duplex = PORT_FULL_DUPLEX; - mac_cfg.link = PORT_LINKUP; - mac_cfg.nway = DISABLED; - mac_cfg.txpause = ENABLED; - mac_cfg.rxpause = ENABLED; - rtk_port_macForceLinkExt_set(EXT_PORT1, mode, &mac_cfg); - rtk_port_rgmiiDelayExt_set(EXT_PORT1, 1, 3); - rtk_port_phyEnableAll_set(ENABLED); - -} - -void init_gsw(void) -{ - rtl8367s_hw_init(); - set_rtl8367s_sgmii(); - set_rtl8367s_rgmii(); -} - -// bleow are platform driver -static const struct of_device_id rtk_gsw_match[] = { - { .compatible = "mediatek,rtk-gsw" }, - {}, -}; - -MODULE_DEVICE_TABLE(of, rtk_gsw_match); - -static int rtk_gsw_probe(struct platform_device *pdev) -{ - struct device_node *np = pdev->dev.of_node; - struct device_node *mdio; - struct mii_bus *mdio_bus; - struct rtk_gsw *gsw; - const char *pm; - int ret; - - mdio = of_parse_phandle(np, "mediatek,mdio", 0); - - if (!mdio) - return -EINVAL; - - mdio_bus = of_mdio_find_bus(mdio); - - if (!mdio_bus) - return -EPROBE_DEFER; - - gsw = devm_kzalloc(&pdev->dev, sizeof(struct rtk_gsw), GFP_KERNEL); - - if (!gsw) - return -ENOMEM; - - gsw->dev = &pdev->dev; - - gsw->bus = mdio_bus; - - gsw->reset_pin = of_get_named_gpio(np, "mediatek,reset-pin", 0); - if (gsw->reset_pin >= 0) { - ret = devm_gpio_request(gsw->dev, gsw->reset_pin, "mediatek,reset-pin"); - if (ret) - printk("fail to devm_gpio_request\n"); - } - - _gsw = gsw; - - init_gsw(); - - //init default vlan or init swocnfig - if(!of_property_read_string(pdev->dev.of_node, - "mediatek,port_map", &pm)) { - - if (!strcasecmp(pm, "wllll")) - rtl8367s_vlan_config(1); - else - rtl8367s_vlan_config(0); - - } else { -#ifdef CONFIG_SWCONFIG - rtl8367s_swconfig_init(&init_gsw); -#else - rtl8367s_vlan_config(0); -#endif - } - - gsw_debug_proc_init(); - - platform_set_drvdata(pdev, gsw); - - return 0; - -} - -static int rtk_gsw_remove(struct platform_device *pdev) -{ - platform_set_drvdata(pdev, NULL); - gsw_debug_proc_exit(); - - return 0; -} - -static struct platform_driver gsw_driver = { - .probe = rtk_gsw_probe, - .remove = rtk_gsw_remove, - .driver = { - .name = "rtk-gsw", - .owner = THIS_MODULE, - .of_match_table = rtk_gsw_match, - }, -}; - -module_platform_driver(gsw_driver); - -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Mark Lee "); -MODULE_DESCRIPTION("rtl8367c switch driver for MT7622"); - diff --git a/6.1/target/linux/mediatek/mt7622/config-6.1 b/6.1/target/linux/mediatek/mt7622/config-6.1 deleted file mode 100644 index bf422052..00000000 --- a/6.1/target/linux/mediatek/mt7622/config-6.1 +++ /dev/null @@ -1,515 +0,0 @@ -CONFIG_64BIT=y -# CONFIG_AHCI_MTK is not set -CONFIG_AQUANTIA_PHY=y -CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y -CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_ARCH_FORCE_MAX_ORDER=11 -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_NR_GPIO=0 -# CONFIG_ARCH_NXP is not set -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_STACKWALK=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_WANTS_NO_INSTR=y -CONFIG_ARCH_WANTS_THP_SWAP=y -CONFIG_ARM64=y -CONFIG_ARM64_4K_PAGES=y -# CONFIG_ARM64_CNP is not set -# CONFIG_ARM64_ERRATUM_1742098 is not set -# CONFIG_ARM64_ERRATUM_2051678 is not set -# CONFIG_ARM64_ERRATUM_2054223 is not set -# CONFIG_ARM64_ERRATUM_2067961 is not set -# CONFIG_ARM64_ERRATUM_2077057 is not set -# CONFIG_ARM64_ERRATUM_2441007 is not set -# CONFIG_ARM64_ERRATUM_2441009 is not set -# CONFIG_ARM64_ERRATUM_2658417 is not set -CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_ERRATUM_845719=y -CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y -CONFIG_ARM64_MODULE_PLTS=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_PA_BITS=48 -CONFIG_ARM64_PA_BITS_48=y -# CONFIG_ARM64_SW_TTBR0_PAN is not set -CONFIG_ARM64_TAGGED_ADDR_ABI=y -CONFIG_ARM64_VA_BITS=39 -CONFIG_ARM64_VA_BITS_39=y -# CONFIG_ARMV8_DEPRECATED is not set -CONFIG_ARM_AMBA=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y -CONFIG_ARM_GIC_V3_ITS_PCI=y -CONFIG_ARM_MEDIATEK_CPUFREQ=y -CONFIG_ARM_PMU=y -CONFIG_ARM_PSCI_FW=y -CONFIG_ATA=y -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BLOCK_COMPAT=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y -CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_MEDIATEK=y -CONFIG_COMMON_CLK_MT2712=y -# CONFIG_COMMON_CLK_MT2712_BDPSYS is not set -# CONFIG_COMMON_CLK_MT2712_IMGSYS is not set -# CONFIG_COMMON_CLK_MT2712_JPGDECSYS is not set -# CONFIG_COMMON_CLK_MT2712_MFGCFG is not set -# CONFIG_COMMON_CLK_MT2712_MMSYS is not set -# CONFIG_COMMON_CLK_MT2712_VDECSYS is not set -# CONFIG_COMMON_CLK_MT2712_VENCSYS is not set -# CONFIG_COMMON_CLK_MT6779 is not set -# CONFIG_COMMON_CLK_MT6795 is not set -# CONFIG_COMMON_CLK_MT6797 is not set -CONFIG_COMMON_CLK_MT7622=y -CONFIG_COMMON_CLK_MT7622_AUDSYS=y -CONFIG_COMMON_CLK_MT7622_ETHSYS=y -CONFIG_COMMON_CLK_MT7622_HIFSYS=y -CONFIG_COMMON_CLK_MT7981=y -CONFIG_COMMON_CLK_MT7981_ETHSYS=y -# CONFIG_COMMON_CLK_MT7986 is not set -# CONFIG_COMMON_CLK_MT7988 is not set -# CONFIG_COMMON_CLK_MT8173 is not set -# CONFIG_COMMON_CLK_MT8183 is not set -# CONFIG_COMMON_CLK_MT8186 is not set -# CONFIG_COMMON_CLK_MT8195 is not set -# CONFIG_COMMON_CLK_MT8365 is not set -# CONFIG_COMMON_CLK_MT8516 is not set -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -CONFIG_COMPAT=y -CONFIG_COMPAT_32BIT_TIME=y -# CONFIG_COMPAT_ALIGNMENT_FIXUPS is not set -CONFIG_COMPAT_BINFMT_ELF=y -CONFIG_COMPAT_NETLINK_MESSAGES=y -CONFIG_COMPAT_OLD_SIGACTION=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y -# CONFIG_CPUFREQ_DT is not set -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_THERMAL=y -CONFIG_CRC16=y -CONFIG_CRYPTO_AES_ARM64=y -CONFIG_CRYPTO_AES_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE_BLK=y -CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -CONFIG_CRYPTO_CMAC=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRYPTD=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_ECC=y -CONFIG_CRYPTO_ECDH=y -CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_SHA1=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_LZO=y -# CONFIG_CRYPTO_POLYVAL_ARM64_CE is not set -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA256_ARM64=y -CONFIG_CRYPTO_SHA2_ARM64_CE=y -CONFIG_CRYPTO_SHA512=y -# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set -# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set -CONFIG_CRYPTO_ZSTD=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_MISC=y -CONFIG_DIMLIB=y -CONFIG_DMADEVICES=y -CONFIG_DMA_DIRECT_REMAP=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DTC=y -CONFIG_DYNAMIC_DEBUG=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EINT_MTK=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_EXT4_FS=y -CONFIG_F2FS_FS=y -CONFIG_FIT_PARTITION=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FRAME_POINTER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GCC12_NO_ARRAY_BOUNDS=y -CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IOREMAP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GLOB=y -CONFIG_GPIO_CDEV=y -CONFIG_GRO_CELLS=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -# CONFIG_HISI_PCIE_PMU is not set -# CONFIG_HISI_PTT is not set -# CONFIG_HNS3_PMU is not set -# CONFIG_HP_WATCHDOG is not set -CONFIG_HW_RANDOM=y -# CONFIG_HW_RANDOM_CN10K is not set -CONFIG_HW_RANDOM_MTK=y -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MT65XX=y -CONFIG_ICPLUS_PHY=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_INITRAMFS_SOURCE="" -# CONFIG_IR_MTK is not set -CONFIG_IRQCHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_JUMP_LABEL=y -# CONFIG_KEYBOARD_MT6779 is not set -# CONFIG_LEDS_PWM_MULTICOLOR is not set -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEDIATEK_2P5G_PHY=y -CONFIG_MEDIATEK_GE_PHY=y -CONFIG_MEDIATEK_GE_SOC_PHY=y -CONFIG_MEDIATEK_WATCHDOG=y -CONFIG_MEMFD_CREATE=y -CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 -CONFIG_MFD_SYSCON=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_CQHCI=y -CONFIG_MMC_MTK=y -CONFIG_MODULES_TREE_LOOKUP=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_MEDIATEK=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_MTK=y -CONFIG_MTD_NAND_MTK_BMT=y -CONFIG_MTD_PARSER_TRX=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -# CONFIG_MTK_CMDQ is not set -# CONFIG_MTK_CQDMA is not set -CONFIG_MTK_HSDMA=y -CONFIG_MTK_INFRACFG=y -CONFIG_MTK_PMIC_WRAP=y -CONFIG_MTK_SCPSYS=y -CONFIG_MTK_SCPSYS_PM_DOMAINS=y -CONFIG_MTK_SVS=y -CONFIG_MTK_THERMAL=y -CONFIG_MTK_TIMER=y -# CONFIG_MTK_UART_APDMA is not set -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_MT7530_MDIO=y -CONFIG_NET_DSA_MT7530_MMIO=y -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_MEDIATEK_SOC=y -CONFIG_NET_MEDIATEK_SOC_USXGMII=y -CONFIG_NET_MEDIATEK_SOC_WED=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NET_VENDOR_MEDIATEK=y -CONFIG_NLS=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=2 -CONFIG_NVMEM=y -# CONFIG_NVMEM_MTK_EFUSE is not set -CONFIG_NVMEM_SYSFS=y -# CONFIG_OCTEON_EP is not set -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_DYNAMIC=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_OVERLAY=y -CONFIG_OF_RESOLVE=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_PADATA=y -CONFIG_PAGE_POOL=y -CONFIG_PAGE_POOL_STATS=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -# CONFIG_PAGE_TABLE_CHECK is not set -CONFIG_PAHOLE_HAS_SPLIT_BTF=y -CONFIG_PAHOLE_VERSION=124 -CONFIG_PARTITION_PERCPU=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEASPM=y -# CONFIG_PCIEASPM_DEFAULT is not set -CONFIG_PCIEASPM_PERFORMANCE=y -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_MEDIATEK=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DEBUG=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PERF_EVENTS=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -CONFIG_PHYS_ADDR_T_64BIT=y -# CONFIG_PHY_MTK_DP is not set -# CONFIG_PHY_MTK_PCIE is not set -CONFIG_PHY_MTK_TPHY=y -# CONFIG_PHY_MTK_UFS is not set -# CONFIG_PHY_MTK_XSPHY is not set -CONFIG_PINCTRL=y -# CONFIG_PINCTRL_MT2712 is not set -# CONFIG_PINCTRL_MT6765 is not set -# CONFIG_PINCTRL_MT6795 is not set -# CONFIG_PINCTRL_MT6797 is not set -CONFIG_PINCTRL_MT7622=y -CONFIG_PINCTRL_MT7981=y -CONFIG_PINCTRL_MT7988=y -# CONFIG_PINCTRL_MT7986 is not set -# CONFIG_PINCTRL_MT8173 is not set -# CONFIG_PINCTRL_MT8183 is not set -# CONFIG_PINCTRL_MT8186 is not set -# CONFIG_PINCTRL_MT8188 is not set -CONFIG_PINCTRL_MT8516=y -CONFIG_PINCTRL_MTK=y -CONFIG_PINCTRL_MTK_MOORE=y -CONFIG_PINCTRL_MTK_V2=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PM_OPP=y -CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y -CONFIG_POWER_RESET=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_POWER_SUPPLY=y -# CONFIG_PREEMPT_DYNAMIC is not set -CONFIG_PREEMPT_NONE_BUILD=y -CONFIG_PRINTK_TIME=y -CONFIG_PSTORE=y -CONFIG_PSTORE_COMPRESS=y -CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" -CONFIG_PSTORE_CONSOLE=y -CONFIG_PSTORE_DEFLATE_COMPRESS=y -CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y -CONFIG_PSTORE_PMSG=y -CONFIG_PSTORE_RAM=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -# CONFIG_PWM_CLK is not set -CONFIG_PWM_MEDIATEK=y -# CONFIG_PWM_MTK_DISP is not set -CONFIG_PWM_SYSFS=y -# CONFIG_PWM_XILINX is not set -CONFIG_QUEUED_RWLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -# CONFIG_RANDOMIZE_KSTACK_OFFSET is not set -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -# CONFIG_RAVE_SP_CORE is not set -CONFIG_REALTEK_PHY=y -CONFIG_REED_SOLOMON=y -CONFIG_REED_SOLOMON_DEC8=y -CONFIG_REED_SOLOMON_ENC8=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_MT6380=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RODATA_FULL_DEFAULT_ENABLED=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_MT7622=y -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTL8367S_GSW=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -# CONFIG_SCHED_CLUSTER is not set -CONFIG_SCHED_MC=y -CONFIG_SCSI=y -CONFIG_SCSI_COMMON=y -# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_8250_RUNTIME_UARTS=3 -CONFIG_SERIAL_DEV_BUS=y -CONFIG_SERIAL_DEV_CTRL_TTYPORT=y -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOFTIRQ_ON_OWN_STACK=y -CONFIG_SPARSEMEM=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_DYNAMIC=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT65XX=y -CONFIG_SPI_MTK_NOR=y -CONFIG_SPI_MTK_SNFI=y -CONFIG_SRCU=y -# CONFIG_SURFACE_PLATFORMS is not set -CONFIG_SWCONFIG=y -CONFIG_SWIOTLB=y -CONFIG_SWPHY=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_SYSVIPC_COMPAT=y -# CONFIG_TEST_DYNAMIC_DEBUG is not set -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_EMULATION=y -CONFIG_THERMAL_GOV_BANG_BANG=y -CONFIG_THERMAL_GOV_FAIR_SHARE=y -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_GOV_USER_SPACE=y -CONFIG_THERMAL_OF=y -CONFIG_THERMAL_WRITABLE_TRIPS=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -# CONFIG_UCLAMP_TASK is not set -# CONFIG_UNMAP_KERNEL_AT_EL0 is not set -CONFIG_USB_SUPPORT=y -CONFIG_VMAP_STACK=y -# CONFIG_VMWARE_VMCI is not set -CONFIG_WATCHDOG_CORE=y -CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y -CONFIG_WATCHDOG_PRETIMEOUT_GOV=y -# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set -CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y -CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m -CONFIG_WATCHDOG_SYSFS=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZONE_DMA32=y -CONFIG_ZSTD_COMMON=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/6.1/target/linux/mediatek/mt7623/config-6.1 b/6.1/target/linux/mediatek/mt7623/config-6.1 deleted file mode 100644 index b6a75ab8..00000000 --- a/6.1/target/linux/mediatek/mt7623/config-6.1 +++ /dev/null @@ -1,609 +0,0 @@ -# CONFIG_AIO is not set -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_FORCE_MAX_ORDER=11 -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -# CONFIG_ARM_ATAG_DTB_COMPAT is not set -CONFIG_ARM_CPU_SUSPEND=y -# CONFIG_ARM_CPU_TOPOLOGY is not set -CONFIG_ARM_DMA_IOMMU_ALIGNMENT=8 -CONFIG_ARM_DMA_USE_IOMMU=y -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_GROUP_RELOCS=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -# CONFIG_ARM_MEDIATEK_CCI_DEVFREQ is not set -CONFIG_ARM_MEDIATEK_CPUFREQ=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -# CONFIG_ARM_SMMU is not set -CONFIG_ARM_THUMB=y -CONFIG_ARM_THUMBEE=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y -CONFIG_ATAGS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GPIO=y -CONFIG_BACKLIGHT_LED=y -CONFIG_BACKLIGHT_PWM=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BOUNCE=y -# CONFIG_CACHE_L2X0 is not set -CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y -CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" -CONFIG_CC_NO_ARRAY_BOUNDS=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="earlyprintk console=ttyS0,115200 rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_FROM_BOOTLOADER=y -# CONFIG_CMDLINE_OVERRIDE is not set -CONFIG_CMDLINE_PARTITION=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_MEDIATEK=y -CONFIG_COMMON_CLK_MT2701=y -CONFIG_COMMON_CLK_MT2701_AUDSYS=y -CONFIG_COMMON_CLK_MT2701_BDPSYS=y -CONFIG_COMMON_CLK_MT2701_ETHSYS=y -CONFIG_COMMON_CLK_MT2701_G3DSYS=y -CONFIG_COMMON_CLK_MT2701_HIFSYS=y -CONFIG_COMMON_CLK_MT2701_IMGSYS=y -CONFIG_COMMON_CLK_MT2701_MMSYS=y -CONFIG_COMMON_CLK_MT2701_VDECSYS=y -# CONFIG_COMMON_CLK_MT6795 is not set -# CONFIG_COMMON_CLK_MT7622 is not set -# CONFIG_COMMON_CLK_MT7629 is not set -# CONFIG_COMMON_CLK_MT7981 is not set -# CONFIG_COMMON_CLK_MT7986 is not set -# CONFIG_COMMON_CLK_MT7988 is not set -# CONFIG_COMMON_CLK_MT8135 is not set -# CONFIG_COMMON_CLK_MT8173 is not set -# CONFIG_COMMON_CLK_MT8365 is not set -# CONFIG_COMMON_CLK_MT8516 is not set -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONFIGFS_FS=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y -CONFIG_COREDUMP=y -# CONFIG_CPUFREQ_DT is not set -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_STAT=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -# CONFIG_CRC32_SARWATE is not set -CONFIG_CRC32_SLICEBY8=y -CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_HW=y -CONFIG_CRYPTO_JITTERENTROPY=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_SHA1=y -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_CURRENT_POINTER_IN_TPIDRURO=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_ALIGN_RODATA=y -CONFIG_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_GPIO=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_LL=y -CONFIG_DEBUG_LL_INCLUDE="debug/8250.S" -CONFIG_DEBUG_MISC=y -CONFIG_DEBUG_MT6589_UART0=y -# CONFIG_DEBUG_MT8127_UART0 is not set -# CONFIG_DEBUG_MT8135_UART3 is not set -CONFIG_DEBUG_PREEMPT=y -CONFIG_DEBUG_UART_8250=y -CONFIG_DEBUG_UART_8250_SHIFT=2 -CONFIG_DEBUG_UART_PHYS=0x11004000 -CONFIG_DEBUG_UART_VIRT=0xf1004000 -# CONFIG_DEVFREQ_GOV_PASSIVE is not set -# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set -# CONFIG_DEVFREQ_GOV_POWERSAVE is not set -CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y -# CONFIG_DEVFREQ_GOV_USERSPACE is not set -# CONFIG_DEVFREQ_THERMAL is not set -CONFIG_DIMLIB=y -CONFIG_DMADEVICES=y -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -CONFIG_DMA_OPS=y -CONFIG_DMA_SHARED_BUFFER=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DRM=y -CONFIG_DRM_BRIDGE=y -CONFIG_DRM_DISPLAY_CONNECTOR=y -CONFIG_DRM_FBDEV_EMULATION=y -CONFIG_DRM_FBDEV_OVERALLOC=100 -CONFIG_DRM_GEM_DMA_HELPER=y -CONFIG_DRM_GEM_SHMEM_HELPER=y -CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_LIMA=y -CONFIG_DRM_LVDS_CODEC=y -CONFIG_DRM_MEDIATEK=y -# CONFIG_DRM_MEDIATEK_DP is not set -CONFIG_DRM_MEDIATEK_HDMI=y -CONFIG_DRM_MIPI_DSI=y -CONFIG_DRM_NOMODESET=y -CONFIG_DRM_PANEL=y -CONFIG_DRM_PANEL_BRIDGE=y -CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y -CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=y -CONFIG_DRM_SCHED=y -CONFIG_DRM_SIMPLE_BRIDGE=y -CONFIG_DTC=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_EARLY_PRINTK=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EINT_MTK=y -CONFIG_ELF_CORE=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_EXT4_FS=y -CONFIG_EXTCON=y -CONFIG_F2FS_FS=y -CONFIG_FB=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_CMDLINE=y -CONFIG_FB_DEFERRED_IO=y -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_FOPS=y -CONFIG_FB_SYS_IMAGEBLIT=y -CONFIG_FIT_PARTITION=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FONT_8x16=y -CONFIG_FONT_8x8=y -CONFIG_FONT_SUPPORT=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_FRAME_WARN=1024 -CONFIG_FREEZER=y -CONFIG_FS_IOMAP=y -CONFIG_FS_MBCACHE=y -CONFIG_FWNODE_MDIO=y -CONFIG_FW_CACHE=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GCC11_NO_ARRAY_BOUNDS=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GPIO_CDEV=y -CONFIG_GRO_CELLS=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_SMP=y -CONFIG_HDMI=y -CONFIG_HID=y -CONFIG_HIGHMEM=y -CONFIG_HIGHPTE=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HWMON=y -CONFIG_HW_CONSOLE=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MTK=y -CONFIG_HZ_FIXED=0 -CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MT65XX=y -CONFIG_ICPLUS_PHY=y -CONFIG_IIO=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_INPUT=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_KEYBOARD=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_IOMMU_API=y -# CONFIG_IOMMU_DEBUGFS is not set -# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set -CONFIG_IOMMU_DEFAULT_DMA_STRICT=y -# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set -CONFIG_IOMMU_IO_PGTABLE=y -CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S_SELFTEST is not set -# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set -CONFIG_IOMMU_SUPPORT=y -CONFIG_IRQCHIP=y -CONFIG_IRQSTACKS=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_WORK=y -CONFIG_JBD2=y -CONFIG_KALLSYMS=y -CONFIG_KCMP=y -# CONFIG_KEYBOARD_MT6779 is not set -CONFIG_KEYBOARD_MTK_PMIC=y -CONFIG_KMAP_LOCAL=y -CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_LCD_PLATFORM=y -CONFIG_LEDS_MT6323=y -# CONFIG_LEDS_QCOM_LPG is not set -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LOGO=y -CONFIG_LOGO_LINUX_CLUT224=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -# CONFIG_MACH_MT2701 is not set -# CONFIG_MACH_MT6589 is not set -# CONFIG_MACH_MT6592 is not set -CONFIG_MACH_MT7623=y -# CONFIG_MACH_MT7629 is not set -# CONFIG_MACH_MT8127 is not set -# CONFIG_MACH_MT8135 is not set -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAILBOX=y -# CONFIG_MAILBOX_TEST is not set -CONFIG_MDIO_BITBANG=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MDIO_GPIO=y -CONFIG_MEDIATEK_GE_PHY=y -CONFIG_MEDIATEK_MT6577_AUXADC=y -CONFIG_MEDIATEK_WATCHDOG=y -CONFIG_MEMFD_CREATE=y -CONFIG_MEMORY=y -CONFIG_MFD_CORE=y -# CONFIG_MFD_HI6421_SPMI is not set -CONFIG_MFD_MT6397=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MMC=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_CQHCI=y -CONFIG_MMC_MTK=y -CONFIG_MMC_SDHCI=y -# CONFIG_MMC_SDHCI_PCI is not set -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_CMDLINE_PARTS=y -# CONFIG_MTD_NAND_ECC_MEDIATEK is not set -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_UIMAGE_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -# CONFIG_MTK_ADSP_MBOX is not set -CONFIG_MTK_CMDQ=y -CONFIG_MTK_CMDQ_MBOX=y -CONFIG_MTK_CQDMA=y -# CONFIG_MTK_HSDMA is not set -CONFIG_MTK_INFRACFG=y -CONFIG_MTK_IOMMU=y -CONFIG_MTK_IOMMU_V1=y -CONFIG_MTK_MMSYS=y -CONFIG_MTK_PMIC_WRAP=y -CONFIG_MTK_SCPSYS=y -CONFIG_MTK_SCPSYS_PM_DOMAINS=y -CONFIG_MTK_SMI=y -# CONFIG_MTK_SVS is not set -CONFIG_MTK_THERMAL=y -CONFIG_MTK_TIMER=y -# CONFIG_MTK_UART_APDMA is not set -# CONFIG_MUSB_PIO_ONLY is not set -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NEON=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_MT7530_MDIO=y -# CONFIG_NET_DSA_MT7530_MMIO is not set -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_MEDIATEK_SOC=y -CONFIG_NET_MEDIATEK_SOC_WED=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NET_VENDOR_MEDIATEK=y -# CONFIG_NET_VENDOR_WIZNET is not set -CONFIG_NLS=y -CONFIG_NOP_USB_XCEIV=y -CONFIG_NO_HZ=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=4 -CONFIG_NVMEM=y -CONFIG_NVMEM_MTK_EFUSE=y -# CONFIG_NVMEM_SPMI_SDAM is not set -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_DYNAMIC=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IOMMU=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OF_OVERLAY=y -CONFIG_OF_RESOLVE=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PAGE_POOL=y -CONFIG_PAGE_POOL_STATS=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_MEDIATEK=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCS_MTK_LYNXI=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -# CONFIG_PHY_MTK_DP is not set -CONFIG_PHY_MTK_HDMI=y -CONFIG_PHY_MTK_MIPI_DSI=y -# CONFIG_PHY_MTK_PCIE is not set -CONFIG_PHY_MTK_TPHY=y -# CONFIG_PHY_MTK_UFS is not set -# CONFIG_PHY_MTK_XSPHY is not set -CONFIG_PINCTRL=y -CONFIG_PINCTRL_MT2701=y -# CONFIG_PINCTRL_MT6397 is not set -CONFIG_PINCTRL_MT7623=y -CONFIG_PINCTRL_MTK=y -CONFIG_PINCTRL_MTK_MOORE=y -CONFIG_PINCTRL_MTK_V2=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_DEVFREQ=y -# CONFIG_PM_DEVFREQ_EVENT is not set -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PM_GENERIC_DOMAINS_SLEEP=y -CONFIG_PM_OPP=y -CONFIG_PM_SLEEP=y -CONFIG_PM_SLEEP_SMP=y -CONFIG_POWER_RESET=y -# CONFIG_POWER_RESET_MT6323 is not set -CONFIG_POWER_SUPPLY=y -CONFIG_POWER_SUPPLY_HWMON=y -CONFIG_PREEMPT=y -CONFIG_PREEMPTION=y -CONFIG_PREEMPT_BUILD=y -CONFIG_PREEMPT_COUNT=y -# CONFIG_PREEMPT_NONE is not set -CONFIG_PREEMPT_RCU=y -CONFIG_PRINTK_TIME=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -CONFIG_PWM_MEDIATEK=y -# CONFIG_PWM_MTK_DISP is not set -CONFIG_PWM_SYSFS=y -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_GPIO=y -CONFIG_REGULATOR_MT6323=y -# CONFIG_REGULATOR_MT6331 is not set -# CONFIG_REGULATOR_MT6332 is not set -# CONFIG_REGULATOR_MT6358 is not set -# CONFIG_REGULATOR_MT6380 is not set -# CONFIG_REGULATOR_MT6397 is not set -# CONFIG_REGULATOR_QCOM_LABIBB is not set -# CONFIG_REGULATOR_QCOM_SPMI is not set -# CONFIG_REGULATOR_QCOM_USB_VBUS is not set -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -CONFIG_RTC_CLASS=y -# CONFIG_RTC_DRV_MT6397 is not set -# CONFIG_RTC_DRV_MT7622 is not set -CONFIG_RTC_I2C_AND_SPI=y -CONFIG_RTC_MC146818_LIB=y -# CONFIG_RTL8367S_GSW is not set -CONFIG_RWSEM_SPIN_ON_OWNER=y -# CONFIG_SERIAL_8250_DMA is not set -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SGL_ALLOC=y -CONFIG_SMP=y -# CONFIG_SMP_ON_UP is not set -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOFTIRQ_ON_OWN_STACK=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_BITBANG=y -CONFIG_SPI_DYNAMIC=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT65XX=y -# CONFIG_SPI_MTK_NOR is not set -CONFIG_SPMI=y -# CONFIG_SPMI_HISI3670 is not set -# CONFIG_SPMI_MTK_PMIF is not set -CONFIG_SRCU=y -# CONFIG_STRIP_ASM_SYMS is not set -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYNC_FILE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_THERMAL=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_GOV_STEP_WISE=y -CONFIG_THERMAL_OF=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TOUCHSCREEN_EDT_FT5X06=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -# CONFIG_UACCE is not set -CONFIG_UBIFS_FS=y -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNINLINE_SPIN_UNLOCK=y -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_F_ACM=y -CONFIG_USB_F_ECM=y -CONFIG_USB_F_MASS_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_USB_GPIO_VBUS=y -CONFIG_USB_G_MULTI=y -CONFIG_USB_G_MULTI_CDC=y -# CONFIG_USB_G_MULTI_RNDIS is not set -CONFIG_USB_HID=y -CONFIG_USB_HIDDEV=y -CONFIG_USB_INVENTRA_DMA=y -CONFIG_USB_LIBCOMPOSITE=y -CONFIG_USB_MUSB_DUAL_ROLE=y -CONFIG_USB_MUSB_HDRC=y -CONFIG_USB_MUSB_MEDIATEK=y -CONFIG_USB_OTG=y -CONFIG_USB_PHY=y -CONFIG_USB_ROLE_SWITCH=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_U_ETHER=y -CONFIG_USB_U_SERIAL=y -CONFIG_USE_OF=y -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_VIDEOMODE_HELPERS=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_VT=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_CONSOLE_SLEEP=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_WATCHDOG_CORE=y -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMMON=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/6.1/target/linux/mediatek/mt7629/config-6.1 b/6.1/target/linux/mediatek/mt7629/config-6.1 deleted file mode 100644 index c0c501e5..00000000 --- a/6.1/target/linux/mediatek/mt7629/config-6.1 +++ /dev/null @@ -1,349 +0,0 @@ -CONFIG_ALIGNMENT_TRAP=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_ARCH_FORCE_MAX_ORDER=11 -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_ARCH_MEDIATEK=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -CONFIG_ARCH_MULTIPLATFORM=y -CONFIG_ARCH_MULTI_V6_V7=y -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_GIC=y -CONFIG_ARM_HAS_GROUP_RELOCS=y -CONFIG_ARM_HEAVY_MB=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_PATCH_IDIV=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_ARM_THUMB=y -CONFIG_ARM_UNWIND=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_ATAGS=y -CONFIG_AUTO_ZRELADDR=y -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_CACHE_L2X0=y -CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y -CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" -CONFIG_CC_NO_ARRAY_BOUNDS=y -# CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE is not set -CONFIG_CC_OPTIMIZE_FOR_SIZE=y -CONFIG_CHR_DEV_SCH=y -CONFIG_CLKSRC_MMIO=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_CMDLINE="rootfstype=squashfs,jffs2" -CONFIG_CMDLINE_FROM_BOOTLOADER=y -CONFIG_CMDLINE_OVERRIDE=y -CONFIG_COMMON_CLK=y -CONFIG_COMMON_CLK_MEDIATEK=y -# CONFIG_COMMON_CLK_MT2701 is not set -# CONFIG_COMMON_CLK_MT6795 is not set -# CONFIG_COMMON_CLK_MT7622 is not set -CONFIG_COMMON_CLK_MT7629=y -CONFIG_COMMON_CLK_MT7629_ETHSYS=y -CONFIG_COMMON_CLK_MT7629_HIFSYS=y -# CONFIG_COMMON_CLK_MT7981 is not set -# CONFIG_COMMON_CLK_MT7986 is not set -# CONFIG_COMMON_CLK_MT7988 is not set -# CONFIG_COMMON_CLK_MT8135 is not set -# CONFIG_COMMON_CLK_MT8173 is not set -# CONFIG_COMMON_CLK_MT8365 is not set -# CONFIG_COMMON_CLK_MT8516 is not set -CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_CONTEXT_TRACKING=y -CONFIG_CONTEXT_TRACKING_IDLE=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_PM=y -CONFIG_CPU_RMAP=y -CONFIG_CPU_SPECTRE=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_V7=y -CONFIG_CRC16=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_HASH_INFO=y -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_LIB_SHA1=y -CONFIG_CRYPTO_LIB_UTILS=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_ZSTD=y -CONFIG_CURRENT_POINTER_IN_TPIDRURO=y -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_DEBUG_INFO=y -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -CONFIG_DEBUG_MISC=y -CONFIG_DEFAULT_HOSTNAME="(mt7629)" -CONFIG_DIMLIB=y -CONFIG_DMA_OPS=y -CONFIG_DTC=y -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EINT_MTK=y -CONFIG_EXCLUSIVE_SYSTEM_RAM=y -CONFIG_FIXED_PHY=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_FRAME_WARN=1024 -CONFIG_FWNODE_MDIO=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_FW_LOADER_SYSFS=y -CONFIG_GCC11_NO_ARRAY_BOUNDS=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_GENERIC_ARCH_TOPOLOGY=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_GENERIC_EARLY_IOREMAP=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_PHY=y -CONFIG_GENERIC_PINCONF=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_GPIO_CDEV=y -CONFIG_GRO_CELLS=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAVE_SMP=y -CONFIG_HOTPLUG_CPU=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_MTK=y -CONFIG_HZ_FIXED=0 -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQCHIP=y -CONFIG_IRQSTACKS=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_IRQ_WORK=y -# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set -CONFIG_LIBFDT=y -CONFIG_LOCK_DEBUGGING_SUPPORT=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -# CONFIG_MACH_MT2701 is not set -# CONFIG_MACH_MT6589 is not set -# CONFIG_MACH_MT6592 is not set -# CONFIG_MACH_MT7623 is not set -CONFIG_MACH_MT7629=y -# CONFIG_MACH_MT8127 is not set -# CONFIG_MACH_MT8135 is not set -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_DEVRES=y -CONFIG_MEDIATEK_GE_PHY=y -CONFIG_MEDIATEK_WATCHDOG=y -CONFIG_MEMFD_CREATE=y -CONFIG_MFD_SYSCON=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_MIGRATION=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_MTD_NAND_CORE=y -CONFIG_MTD_NAND_ECC=y -CONFIG_MTD_NAND_ECC_MEDIATEK=y -CONFIG_MTD_NAND_ECC_SW_HAMMING=y -CONFIG_MTD_NAND_MTK_BMT=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_SPI_NAND=y -CONFIG_MTD_SPI_NOR=y -CONFIG_MTD_SPLIT_FIRMWARE=y -CONFIG_MTD_SPLIT_FIT_FW=y -CONFIG_MTD_UBI=y -CONFIG_MTD_UBI_BEB_LIMIT=20 -CONFIG_MTD_UBI_BLOCK=y -CONFIG_MTD_UBI_WL_THRESHOLD=4096 -# CONFIG_MTK_CMDQ is not set -CONFIG_MTK_INFRACFG=y -# CONFIG_MTK_PMIC_WRAP is not set -CONFIG_MTK_SCPSYS=y -CONFIG_MTK_SCPSYS_PM_DOMAINS=y -CONFIG_MTK_TIMER=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NETFILTER=y -CONFIG_NET_DEVLINK=y -CONFIG_NET_DSA=y -CONFIG_NET_DSA_MT7530=y -CONFIG_NET_DSA_MT7530_MDIO=y -# CONFIG_NET_DSA_MT7530_MMIO is not set -CONFIG_NET_DSA_TAG_MTK=y -CONFIG_NET_FLOW_LIMIT=y -CONFIG_NET_MEDIATEK_SOC=y -CONFIG_NET_MEDIATEK_SOC_WED=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_SWITCHDEV=y -CONFIG_NET_VENDOR_MEDIATEK=y -CONFIG_NLS=y -CONFIG_NO_HZ_COMMON=y -CONFIG_NO_HZ_IDLE=y -CONFIG_NR_CPUS=2 -CONFIG_NVMEM=y -# CONFIG_NVMEM_MTK_EFUSE is not set -CONFIG_NVMEM_SYSFS=y -CONFIG_OF=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_FLATTREE=y -CONFIG_OF_GPIO=y -CONFIG_OF_IRQ=y -CONFIG_OF_KOBJ=y -CONFIG_OF_MDIO=y -CONFIG_OLD_SIGACTION=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_PADATA=y -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_PAGE_POOL=y -CONFIG_PAGE_POOL_STATS=y -CONFIG_PAGE_SIZE_LESS_THAN_256KB=y -CONFIG_PAGE_SIZE_LESS_THAN_64KB=y -CONFIG_PCI=y -CONFIG_PCIEAER=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCIE_MEDIATEK=y -CONFIG_PCIE_PME=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCS_MTK_LYNXI=y -CONFIG_PERF_USE_VMALLOC=y -CONFIG_PGTABLE_LEVELS=2 -CONFIG_PHYLIB=y -CONFIG_PHYLINK=y -# CONFIG_PHY_MTK_DP is not set -# CONFIG_PHY_MTK_PCIE is not set -CONFIG_PHY_MTK_TPHY=y -# CONFIG_PHY_MTK_UFS is not set -# CONFIG_PHY_MTK_XSPHY is not set -CONFIG_PINCTRL=y -CONFIG_PINCTRL_MT7629=y -CONFIG_PINCTRL_MTK_MOORE=y -CONFIG_PINCTRL_MTK_V2=y -CONFIG_PM=y -CONFIG_PM_CLK=y -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_PREEMPT_NONE_BUILD=y -CONFIG_PTP_1588_CLOCK_OPTIONAL=y -CONFIG_PWM=y -CONFIG_PWM_MEDIATEK=y -# CONFIG_PWM_MTK_DISP is not set -CONFIG_PWM_SYSFS=y -CONFIG_RANDSTRUCT_NONE=y -CONFIG_RAS=y -CONFIG_RATIONAL=y -CONFIG_REGMAP=y -CONFIG_REGMAP_MMIO=y -CONFIG_RESET_CONTROLLER=y -CONFIG_RFS_ACCEL=y -CONFIG_RPS=y -# CONFIG_RTL8367S_GSW is not set -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_SCSI=y -CONFIG_SCSI_COMMON=y -CONFIG_SERIAL_8250_FSL=y -CONFIG_SERIAL_8250_MT6577=y -CONFIG_SERIAL_8250_NR_UARTS=3 -CONFIG_SERIAL_8250_RUNTIME_UARTS=3 -CONFIG_SERIAL_MCTRL_GPIO=y -CONFIG_SERIAL_OF_PLATFORM=y -CONFIG_SGL_ALLOC=y -CONFIG_SG_POOL=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_SOFTIRQ_ON_OWN_STACK=y -CONFIG_SPARSE_IRQ=y -CONFIG_SPI=y -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y -CONFIG_SPI_MT65XX=y -CONFIG_SPI_MTK_NOR=y -CONFIG_SPI_MTK_SNFI=y -CONFIG_SRCU=y -CONFIG_STACKTRACE=y -# CONFIG_SWAP is not set -CONFIG_SWCONFIG=y -CONFIG_SWPHY=y -CONFIG_SWP_EMULATE=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_THREAD_INFO_IN_TASK=y -CONFIG_TICK_CPU_ACCOUNTING=y -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_TREE_RCU=y -CONFIG_TREE_SRCU=y -CONFIG_UBIFS_FS=y -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -CONFIG_UNWINDER_ARM=y -CONFIG_USB=y -CONFIG_USB_COMMON=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_MTK=y -# CONFIG_USB_XHCI_PLATFORM is not set -CONFIG_USE_OF=y -# CONFIG_VFP is not set -CONFIG_WATCHDOG_CORE=y -# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set -CONFIG_XPS=y -CONFIG_XXHASH=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_BCJ=y -CONFIG_ZBOOT_ROM_BSS=0 -CONFIG_ZBOOT_ROM_TEXT=0 -CONFIG_ZLIB_DEFLATE=y -CONFIG_ZLIB_INFLATE=y -CONFIG_ZSTD_COMMON=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y diff --git a/6.1/target/linux/mediatek/patches-6.1/000-v6.2-kbuild-Allow-DTB-overlays-to-built-from-.dtso-named-.patch b/6.1/target/linux/mediatek/patches-6.1/000-v6.2-kbuild-Allow-DTB-overlays-to-built-from-.dtso-named-.patch deleted file mode 100644 index 17c5c609..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/000-v6.2-kbuild-Allow-DTB-overlays-to-built-from-.dtso-named-.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 363547d2191cbc32ca954ba75d72908712398ff2 Mon Sep 17 00:00:00 2001 -From: Andrew Davis -Date: Mon, 24 Oct 2022 12:34:28 -0500 -Subject: [PATCH] kbuild: Allow DTB overlays to built from .dtso named source - files - -Currently DTB Overlays (.dtbo) are build from source files with the same -extension (.dts) as the base DTs (.dtb). This may become confusing and -even lead to wrong results. For example, a composite DTB (created from a -base DTB and a set of overlays) might have the same name as one of the -overlays that create it. - -Different files should be generated from differently named sources. - .dtb <-> .dts - .dtbo <-> .dtso - -We do not remove the ability to compile DTBO files from .dts files here, -only add a new rule allowing the .dtso file name. The current .dts named -overlays can be renamed with time. After all have been renamed we can -remove the other rule. - -Signed-off-by: Andrew Davis -Reviewed-by: Geert Uytterhoeven -Tested-by: Geert Uytterhoeven -Reviewed-by: Frank Rowand -Tested-by: Frank Rowand -Link: https://lore.kernel.org/r/20221024173434.32518-2-afd@ti.com -Signed-off-by: Rob Herring ---- - scripts/Makefile.lib | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/scripts/Makefile.lib -+++ b/scripts/Makefile.lib -@@ -408,6 +408,9 @@ $(obj)/%.dtb: $(src)/%.dts $(DTC) $(DT_T - $(obj)/%.dtbo: $(src)/%.dts $(DTC) FORCE - $(call if_changed_dep,dtc) - -+$(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE -+ $(call if_changed_dep,dtc) -+ - dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) - - # Bzip2 diff --git a/6.1/target/linux/mediatek/patches-6.1/001-v6.2-arm64-dts-mediatek-mt7986-add-support-for-RX-Wireles.patch b/6.1/target/linux/mediatek/patches-6.1/001-v6.2-arm64-dts-mediatek-mt7986-add-support-for-RX-Wireles.patch deleted file mode 100644 index 970e0f92..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/001-v6.2-arm64-dts-mediatek-mt7986-add-support-for-RX-Wireles.patch +++ /dev/null @@ -1,106 +0,0 @@ -From 2c4daed9580164522859fa100128be408cc69be2 Mon Sep 17 00:00:00 2001 -From: Lorenzo Bianconi -Date: Sat, 5 Nov 2022 23:36:16 +0100 -Subject: [PATCH 01/19] arm64: dts: mediatek: mt7986: add support for RX - Wireless Ethernet Dispatch - -Similar to TX Wireless Ethernet Dispatch, introduce RX Wireless Ethernet -Dispatch to offload traffic received by the wlan interface to lan/wan -one. - -Co-developed-by: Sujuan Chen -Signed-off-by: Sujuan Chen -Signed-off-by: Lorenzo Bianconi -Signed-off-by: David S. Miller ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 65 +++++++++++++++++++++++ - 1 file changed, 65 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -76,6 +76,47 @@ - no-map; - reg = <0 0x4fc00000 0 0x00100000>; - }; -+ -+ wo_emi0: wo-emi@4fd00000 { -+ reg = <0 0x4fd00000 0 0x40000>; -+ no-map; -+ }; -+ -+ wo_emi1: wo-emi@4fd40000 { -+ reg = <0 0x4fd40000 0 0x40000>; -+ no-map; -+ }; -+ -+ wo_ilm0: wo-ilm@151e0000 { -+ reg = <0 0x151e0000 0 0x8000>; -+ no-map; -+ }; -+ -+ wo_ilm1: wo-ilm@151f0000 { -+ reg = <0 0x151f0000 0 0x8000>; -+ no-map; -+ }; -+ -+ wo_data: wo-data@4fd80000 { -+ reg = <0 0x4fd80000 0 0x240000>; -+ no-map; -+ }; -+ -+ wo_dlm0: wo-dlm@151e8000 { -+ reg = <0 0x151e8000 0 0x2000>; -+ no-map; -+ }; -+ -+ wo_dlm1: wo-dlm@151f8000 { -+ reg = <0 0x151f8000 0 0x2000>; -+ no-map; -+ }; -+ -+ wo_boot: wo-boot@15194000 { -+ reg = <0 0x15194000 0 0x1000>; -+ no-map; -+ }; -+ - }; - - timer { -@@ -239,6 +280,11 @@ - reg = <0 0x15010000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; -+ memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, -+ <&wo_data>, <&wo_boot>; -+ memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", -+ "wo-data", "wo-boot"; -+ mediatek,wo-ccif = <&wo_ccif0>; - }; - - wed1: wed@15011000 { -@@ -247,6 +293,25 @@ - reg = <0 0x15011000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; -+ memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>, -+ <&wo_data>, <&wo_boot>; -+ memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", -+ "wo-data", "wo-boot"; -+ mediatek,wo-ccif = <&wo_ccif1>; -+ }; -+ -+ wo_ccif0: syscon@151a5000 { -+ compatible = "mediatek,mt7986-wo-ccif", "syscon"; -+ reg = <0 0x151a5000 0 0x1000>; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ -+ wo_ccif1: syscon@151ad000 { -+ compatible = "mediatek,mt7986-wo-ccif", "syscon"; -+ reg = <0 0x151ad000 0 0x1000>; -+ interrupt-parent = <&gic>; -+ interrupts = ; - }; - - eth: ethernet@15100000 { diff --git a/6.1/target/linux/mediatek/patches-6.1/002-v6.2-arm64-dts-mt7986-harmonize-device-node-order.patch b/6.1/target/linux/mediatek/patches-6.1/002-v6.2-arm64-dts-mt7986-harmonize-device-node-order.patch deleted file mode 100644 index b5091687..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/002-v6.2-arm64-dts-mt7986-harmonize-device-node-order.patch +++ /dev/null @@ -1,166 +0,0 @@ -From 438e53828c08cf0e8a65b61cf6ce1e4b6620551a Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Sun, 6 Nov 2022 09:50:24 +0100 -Subject: [PATCH 02/19] arm64: dts: mt7986: harmonize device node order - -This arrange device tree nodes in alphabetical order. - -Signed-off-by: Sam Shih -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20221106085034.12582-2-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 94 ++++++++++---------- - arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 22 ++--- - 2 files changed, 58 insertions(+), 58 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -@@ -54,6 +54,53 @@ - }; - }; - -+&pio { -+ uart1_pins: uart1-pins { -+ mux { -+ function = "uart"; -+ groups = "uart1"; -+ }; -+ }; -+ -+ uart2_pins: uart2-pins { -+ mux { -+ function = "uart"; -+ groups = "uart2"; -+ }; -+ }; -+ -+ wf_2g_5g_pins: wf-2g-5g-pins { -+ mux { -+ function = "wifi"; -+ groups = "wf_2g", "wf_5g"; -+ }; -+ conf { -+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", -+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", -+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", -+ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", -+ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", -+ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", -+ "WF1_TOP_CLK", "WF1_TOP_DATA"; -+ drive-strength = <4>; -+ }; -+ }; -+ -+ wf_dbdc_pins: wf-dbdc-pins { -+ mux { -+ function = "wifi"; -+ groups = "wf_dbdc"; -+ }; -+ conf { -+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", -+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", -+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", -+ "WF0_TOP_CLK", "WF0_TOP_DATA"; -+ drive-strength = <4>; -+ }; -+ }; -+}; -+ - &switch { - ports { - #address-cells = <1>; -@@ -121,50 +168,3 @@ - pinctrl-0 = <&wf_2g_5g_pins>; - pinctrl-1 = <&wf_dbdc_pins>; - }; -- --&pio { -- uart1_pins: uart1-pins { -- mux { -- function = "uart"; -- groups = "uart1"; -- }; -- }; -- -- uart2_pins: uart2-pins { -- mux { -- function = "uart"; -- groups = "uart2"; -- }; -- }; -- -- wf_2g_5g_pins: wf-2g-5g-pins { -- mux { -- function = "wifi"; -- groups = "wf_2g", "wf_5g"; -- }; -- conf { -- pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", -- "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", -- "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", -- "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", -- "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", -- "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", -- "WF1_TOP_CLK", "WF1_TOP_DATA"; -- drive-strength = <4>; -- }; -- }; -- -- wf_dbdc_pins: wf-dbdc-pins { -- mux { -- function = "wifi"; -- groups = "wf_dbdc"; -- }; -- conf { -- pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", -- "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", -- "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", -- "WF0_TOP_CLK", "WF0_TOP_DATA"; -- drive-strength = <4>; -- }; -- }; --}; ---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -@@ -25,10 +25,6 @@ - }; - }; - --&uart0 { -- status = "okay"; --}; -- - ð { - status = "okay"; - -@@ -99,13 +95,6 @@ - }; - }; - --&wifi { -- status = "okay"; -- pinctrl-names = "default", "dbdc"; -- pinctrl-0 = <&wf_2g_5g_pins>; -- pinctrl-1 = <&wf_dbdc_pins>; --}; -- - &pio { - wf_2g_5g_pins: wf-2g-5g-pins { - mux { -@@ -138,3 +127,14 @@ - }; - }; - }; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&wifi { -+ status = "okay"; -+ pinctrl-names = "default", "dbdc"; -+ pinctrl-0 = <&wf_2g_5g_pins>; -+ pinctrl-1 = <&wf_dbdc_pins>; -+}; diff --git a/6.1/target/linux/mediatek/patches-6.1/003-v6.2-arm64-dts-mt7986-add-crypto-related-device-nodes.patch b/6.1/target/linux/mediatek/patches-6.1/003-v6.2-arm64-dts-mt7986-add-crypto-related-device-nodes.patch deleted file mode 100644 index 5706531a..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/003-v6.2-arm64-dts-mt7986-add-crypto-related-device-nodes.patch +++ /dev/null @@ -1,68 +0,0 @@ -From ffb05357b47f06b2b4d1e14ba89169e28feb727b Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Sun, 6 Nov 2022 09:50:27 +0100 -Subject: [PATCH 03/19] arm64: dts: mt7986: add crypto related device nodes - -This patch adds crypto engine support for MT7986. - -Signed-off-by: Vic Wu -Signed-off-by: Sam Shih -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20221106085034.12582-5-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 4 ++++ - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 15 +++++++++++++++ - arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 4 ++++ - 3 files changed, 23 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -@@ -25,6 +25,10 @@ - }; - }; - -+&crypto { -+ status = "okay"; -+}; -+ - ð { - status = "okay"; - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -223,6 +223,21 @@ - status = "disabled"; - }; - -+ crypto: crypto@10320000 { -+ compatible = "inside-secure,safexcel-eip97"; -+ reg = <0 0x10320000 0 0x40000>; -+ interrupts = , -+ , -+ , -+ ; -+ interrupt-names = "ring0", "ring1", "ring2", "ring3"; -+ clocks = <&infracfg CLK_INFRA_EIP97_CK>; -+ clock-names = "infra_eip97_ck"; -+ assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>; -+ assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>; -+ status = "disabled"; -+ }; -+ - uart0: serial@11002000 { - compatible = "mediatek,mt7986-uart", - "mediatek,mt6577-uart"; ---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -@@ -25,6 +25,10 @@ - }; - }; - -+&crypto { -+ status = "okay"; -+}; -+ - ð { - status = "okay"; - diff --git a/6.1/target/linux/mediatek/patches-6.1/004-v6.2-arm64-dts-mt7986-add-i2c-node.patch b/6.1/target/linux/mediatek/patches-6.1/004-v6.2-arm64-dts-mt7986-add-i2c-node.patch deleted file mode 100644 index 0e5b77a1..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/004-v6.2-arm64-dts-mt7986-add-i2c-node.patch +++ /dev/null @@ -1,37 +0,0 @@ -From b49b7dc404ded1d89cbc568d875009a5c1ed4ef6 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Sun, 6 Nov 2022 09:50:29 +0100 -Subject: [PATCH 04/19] arm64: dts: mt7986: add i2c node - -Add i2c Node to mt7986 devicetree. - -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20221106085034.12582-7-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -279,6 +279,20 @@ - status = "disabled"; - }; - -+ i2c0: i2c@11008000 { -+ compatible = "mediatek,mt7986-i2c"; -+ reg = <0 0x11008000 0 0x90>, -+ <0 0x10217080 0 0x80>; -+ interrupts = ; -+ clock-div = <5>; -+ clocks = <&infracfg CLK_INFRA_I2C0_CK>, -+ <&infracfg CLK_INFRA_AP_DMA_CK>; -+ clock-names = "main", "dma"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ - ethsys: syscon@15000000 { - #address-cells = <1>; - #size-cells = <1>; diff --git a/6.1/target/linux/mediatek/patches-6.1/005-v6.2-arm64-dts-mediatek-mt7986-Add-SoC-compatible.patch b/6.1/target/linux/mediatek/patches-6.1/005-v6.2-arm64-dts-mediatek-mt7986-Add-SoC-compatible.patch deleted file mode 100644 index 8201b47d..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/005-v6.2-arm64-dts-mediatek-mt7986-Add-SoC-compatible.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 2cd6022800d6da7822e169f3e6f7f790c1431445 Mon Sep 17 00:00:00 2001 -From: Matthias Brugger -Date: Mon, 14 Nov 2022 13:16:53 +0100 -Subject: [PATCH 05/19] arm64: dts: mediatek: mt7986: Add SoC compatible - -Missing SoC compatible in the board file causes dt bindings check. - -Signed-off-by: Matthias Brugger -Link: https://lore.kernel.org/r/20221114121653.14739-1-matthias.bgg@kernel.org -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 2 +- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 1 + - arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 2 +- - arch/arm64/boot/dts/mediatek/mt7986b.dtsi | 3 +++ - 4 files changed, 6 insertions(+), 2 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -@@ -9,7 +9,7 @@ - - / { - model = "MediaTek MT7986a RFB"; -- compatible = "mediatek,mt7986a-rfb"; -+ compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a"; - - aliases { - serial0 = &uart0; ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -10,6 +10,7 @@ - #include - - / { -+ compatible = "mediatek,mt7986a"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; ---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -@@ -9,7 +9,7 @@ - - / { - model = "MediaTek MT7986b RFB"; -- compatible = "mediatek,mt7986b-rfb"; -+ compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b"; - - aliases { - serial0 = &uart0; ---- a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi -@@ -5,6 +5,9 @@ - */ - - #include "mt7986a.dtsi" -+/ { -+ compatible = "mediatek,mt7986b"; -+}; - - &pio { - compatible = "mediatek,mt7986b-pinctrl"; diff --git a/6.1/target/linux/mediatek/patches-6.1/006-v6.2-arm64-dts-mt7986-add-spi-related-device-nodes.patch b/6.1/target/linux/mediatek/patches-6.1/006-v6.2-arm64-dts-mt7986-add-spi-related-device-nodes.patch deleted file mode 100644 index b319b166..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/006-v6.2-arm64-dts-mt7986-add-spi-related-device-nodes.patch +++ /dev/null @@ -1,157 +0,0 @@ -From f4029538f063a845dc9aae46cce4cf386e6253a5 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Fri, 18 Nov 2022 20:01:21 +0100 -Subject: [PATCH 06/19] arm64: dts: mt7986: add spi related device nodes - -This patch adds spi support for MT7986. - -Signed-off-by: Sam Shih -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20221118190126.100895-7-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 35 ++++++++++++++++++++ - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 28 ++++++++++++++++ - arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 35 ++++++++++++++++++++ - 3 files changed, 98 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -@@ -59,6 +59,20 @@ - }; - - &pio { -+ spi_flash_pins: spi-flash-pins { -+ mux { -+ function = "spi"; -+ groups = "spi0", "spi0_wp_hold"; -+ }; -+ }; -+ -+ spic_pins: spic-pins { -+ mux { -+ function = "spi"; -+ groups = "spi1_2"; -+ }; -+ }; -+ - uart1_pins: uart1-pins { - mux { - function = "uart"; -@@ -105,6 +119,27 @@ - }; - }; - -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi_flash_pins>; -+ cs-gpios = <0>, <0>; -+ status = "okay"; -+ spi_nand: spi_nand@0 { -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-max-frequency = <10000000>; -+ spi-tx-buswidth = <4>; -+ spi-rx-buswidth = <4>; -+ }; -+}; -+ -+&spi1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spic_pins>; -+ cs-gpios = <0>, <0>; -+ status = "okay"; -+}; -+ - &switch { - ports { - #address-cells = <1>; ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -294,6 +294,34 @@ - status = "disabled"; - }; - -+ spi0: spi@1100a000 { -+ compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0 0x1100a000 0 0x100>; -+ interrupts = ; -+ clocks = <&topckgen CLK_TOP_MPLL_D2>, -+ <&topckgen CLK_TOP_SPI_SEL>, -+ <&infracfg CLK_INFRA_SPI0_CK>, -+ <&infracfg CLK_INFRA_SPI0_HCK_CK>; -+ clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; -+ status = "disabled"; -+ }; -+ -+ spi1: spi@1100b000 { -+ compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0 0x1100b000 0 0x100>; -+ interrupts = ; -+ clocks = <&topckgen CLK_TOP_MPLL_D2>, -+ <&topckgen CLK_TOP_SPIM_MST_SEL>, -+ <&infracfg CLK_INFRA_SPI1_CK>, -+ <&infracfg CLK_INFRA_SPI1_HCK_CK>; -+ clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; -+ status = "disabled"; -+ }; -+ - ethsys: syscon@15000000 { - #address-cells = <1>; - #size-cells = <1>; ---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -@@ -100,6 +100,20 @@ - }; - - &pio { -+ spi_flash_pins: spi-flash-pins { -+ mux { -+ function = "spi"; -+ groups = "spi0", "spi0_wp_hold"; -+ }; -+ }; -+ -+ spic_pins: spic-pins { -+ mux { -+ function = "spi"; -+ groups = "spi1_2"; -+ }; -+ }; -+ - wf_2g_5g_pins: wf-2g-5g-pins { - mux { - function = "wifi"; -@@ -132,6 +146,27 @@ - }; - }; - -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi_flash_pins>; -+ cs-gpios = <0>, <0>; -+ status = "okay"; -+ spi_nand: spi_nand@0 { -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-max-frequency = <10000000>; -+ spi-tx-buswidth = <4>; -+ spi-rx-buswidth = <4>; -+ }; -+}; -+ -+&spi1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spic_pins>; -+ cs-gpios = <0>, <0>; -+ status = "okay"; -+}; -+ - &uart0 { - status = "okay"; - }; diff --git a/6.1/target/linux/mediatek/patches-6.1/007-v6.3-arm64-dts-mt7986-add-usb-related-device-nodes.patch b/6.1/target/linux/mediatek/patches-6.1/007-v6.3-arm64-dts-mt7986-add-usb-related-device-nodes.patch deleted file mode 100644 index 53567c66..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/007-v6.3-arm64-dts-mt7986-add-usb-related-device-nodes.patch +++ /dev/null @@ -1,127 +0,0 @@ -From 9e8e24ab716098e617195ce29b88e84608bf2108 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Fri, 6 Jan 2023 16:28:42 +0100 -Subject: [PATCH 07/19] arm64: dts: mt7986: add usb related device nodes - -This patch adds USB support for MT7986. - -Signed-off-by: Sam Shih -Signed-off-by: Frank Wunderlich -Reviewed-by: Chunfeng Yun -Link: https://lore.kernel.org/r/20230106152845.88717-3-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 8 +++ - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 55 ++++++++++++++++++++ - arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 8 +++ - 3 files changed, 71 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -@@ -140,6 +140,10 @@ - status = "okay"; - }; - -+&ssusb { -+ status = "okay"; -+}; -+ - &switch { - ports { - #address-cells = <1>; -@@ -201,6 +205,10 @@ - status = "okay"; - }; - -+&usb_phy { -+ status = "okay"; -+}; -+ - &wifi { - status = "okay"; - pinctrl-names = "default", "dbdc"; ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -322,6 +322,61 @@ - status = "disabled"; - }; - -+ ssusb: usb@11200000 { -+ compatible = "mediatek,mt7986-xhci", -+ "mediatek,mtk-xhci"; -+ reg = <0 0x11200000 0 0x2e00>, -+ <0 0x11203e00 0 0x0100>; -+ reg-names = "mac", "ippc"; -+ interrupts = ; -+ clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, -+ <&infracfg CLK_INFRA_IUSB_CK>, -+ <&infracfg CLK_INFRA_IUSB_133_CK>, -+ <&infracfg CLK_INFRA_IUSB_66M_CK>, -+ <&topckgen CLK_TOP_U2U3_XHCI_SEL>; -+ clock-names = "sys_ck", -+ "ref_ck", -+ "mcu_ck", -+ "dma_ck", -+ "xhci_ck"; -+ phys = <&u2port0 PHY_TYPE_USB2>, -+ <&u3port0 PHY_TYPE_USB3>, -+ <&u2port1 PHY_TYPE_USB2>; -+ status = "disabled"; -+ }; -+ -+ usb_phy: t-phy@11e10000 { -+ compatible = "mediatek,mt7986-tphy", -+ "mediatek,generic-tphy-v2"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 0 0x11e10000 0x1700>; -+ status = "disabled"; -+ -+ u2port0: usb-phy@0 { -+ reg = <0x0 0x700>; -+ clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>, -+ <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>; -+ clock-names = "ref", "da_ref"; -+ #phy-cells = <1>; -+ }; -+ -+ u3port0: usb-phy@700 { -+ reg = <0x700 0x900>; -+ clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; -+ clock-names = "ref"; -+ #phy-cells = <1>; -+ }; -+ -+ u2port1: usb-phy@1000 { -+ reg = <0x1000 0x700>; -+ clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>, -+ <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>; -+ clock-names = "ref", "da_ref"; -+ #phy-cells = <1>; -+ }; -+ }; -+ - ethsys: syscon@15000000 { - #address-cells = <1>; - #size-cells = <1>; ---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -@@ -167,10 +167,18 @@ - status = "okay"; - }; - -+&ssusb { -+ status = "okay"; -+}; -+ - &uart0 { - status = "okay"; - }; - -+&usb_phy { -+ status = "okay"; -+}; -+ - &wifi { - status = "okay"; - pinctrl-names = "default", "dbdc"; diff --git a/6.1/target/linux/mediatek/patches-6.1/008-v6.3-arm64-dts-mt7986-add-mmc-related-device-nodes.patch b/6.1/target/linux/mediatek/patches-6.1/008-v6.3-arm64-dts-mt7986-add-mmc-related-device-nodes.patch deleted file mode 100644 index 9c0a4814..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/008-v6.3-arm64-dts-mt7986-add-mmc-related-device-nodes.patch +++ /dev/null @@ -1,160 +0,0 @@ -From c1744e9e75a6a8abc7c893f349bcbf725b9c0d74 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Fri, 6 Jan 2023 16:28:43 +0100 -Subject: [PATCH 08/19] arm64: dts: mt7986: add mmc related device nodes - -This patch adds mmc support for MT7986. - -Signed-off-by: Sam Shih -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20230106152845.88717-4-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 96 ++++++++++++++++++++ - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 15 +++ - 2 files changed, 111 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -@@ -5,6 +5,8 @@ - */ - - /dts-v1/; -+#include -+ - #include "mt7986a.dtsi" - - / { -@@ -23,6 +25,24 @@ - device_type = "memory"; - reg = <0 0x40000000 0 0x40000000>; - }; -+ -+ reg_1p8v: regulator-1p8v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-1.8V"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ reg_3p3v: regulator-3p3v { -+ compatible = "regulator-fixed"; -+ regulator-name = "fixed-3.3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; - }; - - &crypto { -@@ -58,7 +78,83 @@ - }; - }; - -+&mmc0 { -+ pinctrl-names = "default", "state_uhs"; -+ pinctrl-0 = <&mmc0_pins_default>; -+ pinctrl-1 = <&mmc0_pins_uhs>; -+ bus-width = <8>; -+ max-frequency = <200000000>; -+ cap-mmc-highspeed; -+ mmc-hs200-1_8v; -+ mmc-hs400-1_8v; -+ hs400-ds-delay = <0x14014>; -+ vmmc-supply = <®_3p3v>; -+ vqmmc-supply = <®_1p8v>; -+ non-removable; -+ no-sd; -+ no-sdio; -+ status = "okay"; -+}; -+ - &pio { -+ mmc0_pins_default: mmc0-pins { -+ mux { -+ function = "emmc"; -+ groups = "emmc_51"; -+ }; -+ conf-cmd-dat { -+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", -+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", -+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; -+ input-enable; -+ drive-strength = <4>; -+ bias-pull-up = ; /* pull-up 10K */ -+ }; -+ conf-clk { -+ pins = "EMMC_CK"; -+ drive-strength = <6>; -+ bias-pull-down = ; /* pull-down 50K */ -+ }; -+ conf-ds { -+ pins = "EMMC_DSL"; -+ bias-pull-down = ; /* pull-down 50K */ -+ }; -+ conf-rst { -+ pins = "EMMC_RSTB"; -+ drive-strength = <4>; -+ bias-pull-up = ; /* pull-up 10K */ -+ }; -+ }; -+ -+ mmc0_pins_uhs: mmc0-uhs-pins { -+ mux { -+ function = "emmc"; -+ groups = "emmc_51"; -+ }; -+ conf-cmd-dat { -+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", -+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", -+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; -+ input-enable; -+ drive-strength = <4>; -+ bias-pull-up = ; /* pull-up 10K */ -+ }; -+ conf-clk { -+ pins = "EMMC_CK"; -+ drive-strength = <6>; -+ bias-pull-down = ; /* pull-down 50K */ -+ }; -+ conf-ds { -+ pins = "EMMC_DSL"; -+ bias-pull-down = ; /* pull-down 50K */ -+ }; -+ conf-rst { -+ pins = "EMMC_RSTB"; -+ drive-strength = <4>; -+ bias-pull-up = ; /* pull-up 10K */ -+ }; -+ }; -+ - spi_flash_pins: spi-flash-pins { - mux { - function = "spi"; ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -345,6 +345,21 @@ - status = "disabled"; - }; - -+ mmc0: mmc@11230000 { -+ compatible = "mediatek,mt7986-mmc"; -+ reg = <0 0x11230000 0 0x1000>, -+ <0 0x11c20000 0 0x1000>; -+ interrupts = ; -+ clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>, -+ <&infracfg CLK_INFRA_MSDC_HCK_CK>, -+ <&infracfg CLK_INFRA_MSDC_CK>, -+ <&infracfg CLK_INFRA_MSDC_133M_CK>, -+ <&infracfg CLK_INFRA_MSDC_66M_CK>; -+ clock-names = "source", "hclk", "source_cg", "bus_clk", -+ "sys_cg"; -+ status = "disabled"; -+ }; -+ - usb_phy: t-phy@11e10000 { - compatible = "mediatek,mt7986-tphy", - "mediatek,generic-tphy-v2"; diff --git a/6.1/target/linux/mediatek/patches-6.1/009-v6.3-arm64-dts-mt7986-add-pcie-related-device-nodes.patch b/6.1/target/linux/mediatek/patches-6.1/009-v6.3-arm64-dts-mt7986-add-pcie-related-device-nodes.patch deleted file mode 100644 index adc63948..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/009-v6.3-arm64-dts-mt7986-add-pcie-related-device-nodes.patch +++ /dev/null @@ -1,118 +0,0 @@ -From 87a42ef1d6cf602e4aa40555b4404cad6149a90f Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Fri, 6 Jan 2023 16:28:44 +0100 -Subject: [PATCH 09/19] arm64: dts: mt7986: add pcie related device nodes - -This patch adds PCIe support for MT7986. - -Signed-off-by: Jieyy Yang -Signed-off-by: Sam Shih -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20230106152845.88717-5-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 16 ++++++ - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 52 ++++++++++++++++++++ - 2 files changed, 68 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -@@ -93,6 +93,15 @@ - non-removable; - no-sd; - no-sdio; -+}; -+ -+&pcie { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_pins>; -+ status = "okay"; -+}; -+ -+&pcie_phy { - status = "okay"; - }; - -@@ -155,6 +164,13 @@ - }; - }; - -+ pcie_pins: pcie-pins { -+ mux { -+ function = "pcie"; -+ groups = "pcie_clk", "pcie_wake", "pcie_pereset"; -+ }; -+ }; -+ - spi_flash_pins: spi-flash-pins { - mux { - function = "spi"; ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -8,6 +8,7 @@ - #include - #include - #include -+#include - - / { - compatible = "mediatek,mt7986a"; -@@ -360,6 +361,57 @@ - status = "disabled"; - }; - -+ pcie: pcie@11280000 { -+ compatible = "mediatek,mt7986-pcie", -+ "mediatek,mt8192-pcie"; -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ reg = <0x00 0x11280000 0x00 0x4000>; -+ reg-names = "pcie-mac"; -+ interrupts = ; -+ bus-range = <0x00 0xff>; -+ ranges = <0x82000000 0x00 0x20000000 0x00 -+ 0x20000000 0x00 0x10000000>; -+ clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, -+ <&infracfg CLK_INFRA_IPCIE_CK>, -+ <&infracfg CLK_INFRA_IPCIER_CK>, -+ <&infracfg CLK_INFRA_IPCIEB_CK>; -+ clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; -+ status = "disabled"; -+ -+ phys = <&pcie_port PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy"; -+ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &pcie_intc 0>, -+ <0 0 0 2 &pcie_intc 1>, -+ <0 0 0 3 &pcie_intc 2>, -+ <0 0 0 4 &pcie_intc 3>; -+ pcie_intc: interrupt-controller { -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ }; -+ }; -+ -+ pcie_phy: t-phy@11c00000 { -+ compatible = "mediatek,mt7986-tphy", -+ "mediatek,generic-tphy-v2"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ status = "disabled"; -+ -+ pcie_port: pcie-phy@11c00000 { -+ reg = <0 0x11c00000 0 0x20000>; -+ clocks = <&clk40m>; -+ clock-names = "ref"; -+ #phy-cells = <1>; -+ }; -+ }; -+ - usb_phy: t-phy@11e10000 { - compatible = "mediatek,mt7986-tphy", - "mediatek,generic-tphy-v2"; diff --git a/6.1/target/linux/mediatek/patches-6.1/010-v6.3-arm64-dts-mt7986-add-Bananapi-R3.patch b/6.1/target/linux/mediatek/patches-6.1/010-v6.3-arm64-dts-mt7986-add-Bananapi-R3.patch deleted file mode 100644 index abe0b6e9..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/010-v6.3-arm64-dts-mt7986-add-Bananapi-R3.patch +++ /dev/null @@ -1,689 +0,0 @@ -From a751f7412e0098801673b80bc7a4738ae7d710ce Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 6 Jan 2023 16:28:45 +0100 -Subject: [PATCH 10/19] arm64: dts: mt7986: add Bananapi R3 - -Add support for Bananapi R3 SBC. - -- SD/eMMC support (switching first 4 bits of data-bus with sw6/D) -- SPI-NAND/NOR support (switched CS by sw5/C) -- all rj45 ports and both SFP working (eth1/lan4) -- all USB-Ports + SIM-Slot tested -- i2c and all uarts tested -- wifi tested (with eeprom calibration data) - -The device can boot from all 4 storage options. Both, SPI and MMC, can -be switched using hardware switches on the board, see -https://wiki.banana-pi.org/Banana_Pi_BPI-R3#Jumper_setting - -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20230106152845.88717-6-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/Makefile | 5 + - .../mt7986a-bananapi-bpi-r3-emmc.dtso | 29 ++ - .../mt7986a-bananapi-bpi-r3-nand.dtso | 55 +++ - .../mediatek/mt7986a-bananapi-bpi-r3-nor.dtso | 68 +++ - .../mediatek/mt7986a-bananapi-bpi-r3-sd.dtso | 23 + - .../dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 450 ++++++++++++++++++ - 6 files changed, 630 insertions(+) - create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso - create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso - create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso - create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso - create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts - ---- a/arch/arm64/boot/dts/mediatek/Makefile -+++ b/arch/arm64/boot/dts/mediatek/Makefile -@@ -7,6 +7,11 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-ev - dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo -+dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb - dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb - dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso -@@ -0,0 +1,29 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2021 MediaTek Inc. -+ * Author: Sam.Shih -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; -+ -+ fragment@0 { -+ target-path = "/soc/mmc@11230000"; -+ __overlay__ { -+ bus-width = <8>; -+ max-frequency = <200000000>; -+ cap-mmc-highspeed; -+ mmc-hs200-1_8v; -+ mmc-hs400-1_8v; -+ hs400-ds-delay = <0x14014>; -+ non-removable; -+ no-sd; -+ no-sdio; -+ status = "okay"; -+ }; -+ }; -+}; -+ ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso -@@ -0,0 +1,55 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -+/* -+ * Authors: Daniel Golle -+ * Frank Wunderlich -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; -+ -+ fragment@0 { -+ target-path = "/soc/spi@1100a000"; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ spi_nand: spi_nand@0 { -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-max-frequency = <10000000>; -+ spi-tx-buswidth = <4>; -+ spi-rx-buswidth = <4>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "bl2"; -+ reg = <0x0 0x80000>; -+ read-only; -+ }; -+ -+ partition@80000 { -+ label = "reserved"; -+ reg = <0x80000 0x300000>; -+ }; -+ -+ partition@380000 { -+ label = "fip"; -+ reg = <0x380000 0x200000>; -+ read-only; -+ }; -+ -+ partition@580000 { -+ label = "ubi"; -+ reg = <0x580000 0x7a80000>; -+ }; -+ }; -+ }; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso -@@ -0,0 +1,68 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -+/* -+ * Authors: Daniel Golle -+ * Frank Wunderlich -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; -+ -+ fragment@0 { -+ target-path = "/soc/spi@1100a000"; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <10000000>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "bl2"; -+ reg = <0x0 0x20000>; -+ read-only; -+ }; -+ -+ partition@20000 { -+ label = "reserved"; -+ reg = <0x20000 0x20000>; -+ }; -+ -+ partition@40000 { -+ label = "u-boot-env"; -+ reg = <0x40000 0x40000>; -+ }; -+ -+ partition@80000 { -+ label = "reserved2"; -+ reg = <0x80000 0x80000>; -+ }; -+ -+ partition@100000 { -+ label = "fip"; -+ reg = <0x100000 0x80000>; -+ read-only; -+ }; -+ -+ partition@180000 { -+ label = "recovery"; -+ reg = <0x180000 0xa80000>; -+ }; -+ -+ partition@c00000 { -+ label = "fit"; -+ reg = <0xc00000 0x1400000>; -+ }; -+ }; -+ }; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso -@@ -0,0 +1,23 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2021 MediaTek Inc. -+ * Author: Sam.Shih -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; -+ -+ fragment@0 { -+ target-path = "/soc/mmc@11230000"; -+ __overlay__ { -+ bus-width = <4>; -+ max-frequency = <52000000>; -+ cap-sd-highspeed; -+ status = "okay"; -+ }; -+ }; -+}; -+ ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -@@ -0,0 +1,450 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2021 MediaTek Inc. -+ * Authors: Sam.Shih -+ * Frank Wunderlich -+ * Daniel Golle -+ */ -+ -+/dts-v1/; -+#include -+#include -+#include -+#include -+ -+#include "mt7986a.dtsi" -+ -+/ { -+ model = "Bananapi BPI-R3"; -+ compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; -+ -+ aliases { -+ serial0 = &uart0; -+ ethernet0 = &gmac0; -+ ethernet1 = &gmac1; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ dcin: regulator-12vd { -+ compatible = "regulator-fixed"; -+ regulator-name = "12vd"; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ -+ reset-key { -+ label = "reset"; -+ linux,code = ; -+ gpios = <&pio 9 GPIO_ACTIVE_LOW>; -+ }; -+ -+ wps-key { -+ label = "wps"; -+ linux,code = ; -+ gpios = <&pio 10 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ /* i2c of the left SFP cage (wan) */ -+ i2c_sfp1: i2c-gpio-0 { -+ compatible = "i2c-gpio"; -+ sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -+ scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -+ i2c-gpio,delay-us = <2>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ /* i2c of the right SFP cage (lan) */ -+ i2c_sfp2: i2c-gpio-1 { -+ compatible = "i2c-gpio"; -+ sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -+ scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; -+ i2c-gpio,delay-us = <2>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ green_led: led-0 { -+ color = ; -+ function = LED_FUNCTION_POWER; -+ gpios = <&pio 69 GPIO_ACTIVE_HIGH>; -+ default-state = "on"; -+ }; -+ -+ blue_led: led-1 { -+ color = ; -+ function = LED_FUNCTION_STATUS; -+ gpios = <&pio 86 GPIO_ACTIVE_HIGH>; -+ default-state = "off"; -+ }; -+ }; -+ -+ reg_1p8v: regulator-1p8v { -+ compatible = "regulator-fixed"; -+ regulator-name = "1.8vd"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ vin-supply = <&dcin>; -+ }; -+ -+ reg_3p3v: regulator-3p3v { -+ compatible = "regulator-fixed"; -+ regulator-name = "3.3vd"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ vin-supply = <&dcin>; -+ }; -+ -+ /* left SFP cage (wan) */ -+ sfp1: sfp-1 { -+ compatible = "sff,sfp"; -+ i2c-bus = <&i2c_sfp1>; -+ los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>; -+ mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>; -+ tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>; -+ tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ /* right SFP cage (lan) */ -+ sfp2: sfp-2 { -+ compatible = "sff,sfp"; -+ i2c-bus = <&i2c_sfp2>; -+ los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>; -+ mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>; -+ tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>; -+ tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>; -+ }; -+}; -+ -+&crypto { -+ status = "okay"; -+}; -+ -+ð { -+ status = "okay"; -+ -+ gmac0: mac@0 { -+ compatible = "mediatek,eth-mac"; -+ reg = <0>; -+ phy-mode = "2500base-x"; -+ -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ pause; -+ }; -+ }; -+ -+ gmac1: mac@1 { -+ compatible = "mediatek,eth-mac"; -+ reg = <1>; -+ phy-mode = "2500base-x"; -+ sfp = <&sfp1>; -+ managed = "in-band-status"; -+ }; -+ -+ mdio: mdio-bus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+}; -+ -+&mdio { -+ switch: switch@31 { -+ compatible = "mediatek,mt7531"; -+ reg = <31>; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&pio>; -+ interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; -+ reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; -+ }; -+}; -+ -+&mmc0 { -+ pinctrl-names = "default", "state_uhs"; -+ pinctrl-0 = <&mmc0_pins_default>; -+ pinctrl-1 = <&mmc0_pins_uhs>; -+ vmmc-supply = <®_3p3v>; -+ vqmmc-supply = <®_1p8v>; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c_pins>; -+ status = "okay"; -+}; -+ -+&pcie { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_pins>; -+ status = "okay"; -+}; -+ -+&pcie_phy { -+ status = "okay"; -+}; -+ -+&pio { -+ i2c_pins: i2c-pins { -+ mux { -+ function = "i2c"; -+ groups = "i2c"; -+ }; -+ }; -+ -+ mmc0_pins_default: mmc0-pins { -+ mux { -+ function = "emmc"; -+ groups = "emmc_51"; -+ }; -+ conf-cmd-dat { -+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", -+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", -+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; -+ input-enable; -+ drive-strength = <4>; -+ bias-pull-up = ; /* pull-up 10K */ -+ }; -+ conf-clk { -+ pins = "EMMC_CK"; -+ drive-strength = <6>; -+ bias-pull-down = ; /* pull-down 50K */ -+ }; -+ conf-ds { -+ pins = "EMMC_DSL"; -+ bias-pull-down = ; /* pull-down 50K */ -+ }; -+ conf-rst { -+ pins = "EMMC_RSTB"; -+ drive-strength = <4>; -+ bias-pull-up = ; /* pull-up 10K */ -+ }; -+ }; -+ -+ mmc0_pins_uhs: mmc0-uhs-pins { -+ mux { -+ function = "emmc"; -+ groups = "emmc_51"; -+ }; -+ conf-cmd-dat { -+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", -+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", -+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; -+ input-enable; -+ drive-strength = <4>; -+ bias-pull-up = ; /* pull-up 10K */ -+ }; -+ conf-clk { -+ pins = "EMMC_CK"; -+ drive-strength = <6>; -+ bias-pull-down = ; /* pull-down 50K */ -+ }; -+ conf-ds { -+ pins = "EMMC_DSL"; -+ bias-pull-down = ; /* pull-down 50K */ -+ }; -+ conf-rst { -+ pins = "EMMC_RSTB"; -+ drive-strength = <4>; -+ bias-pull-up = ; /* pull-up 10K */ -+ }; -+ }; -+ -+ pcie_pins: pcie-pins { -+ mux { -+ function = "pcie"; -+ groups = "pcie_clk", "pcie_pereset"; -+ }; -+ }; -+ -+ spi_flash_pins: spi-flash-pins { -+ mux { -+ function = "spi"; -+ groups = "spi0", "spi0_wp_hold"; -+ }; -+ }; -+ -+ spic_pins: spic-pins { -+ mux { -+ function = "spi"; -+ groups = "spi1_0"; -+ }; -+ }; -+ -+ uart1_pins: uart1-pins { -+ mux { -+ function = "uart"; -+ groups = "uart1_rx_tx"; -+ }; -+ }; -+ -+ uart2_pins: uart2-pins { -+ mux { -+ function = "uart"; -+ groups = "uart2_0_rx_tx"; -+ }; -+ }; -+ -+ wf_2g_5g_pins: wf-2g-5g-pins { -+ mux { -+ function = "wifi"; -+ groups = "wf_2g", "wf_5g"; -+ }; -+ conf { -+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", -+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", -+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", -+ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", -+ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", -+ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", -+ "WF1_TOP_CLK", "WF1_TOP_DATA"; -+ drive-strength = <4>; -+ }; -+ }; -+ -+ wf_dbdc_pins: wf-dbdc-pins { -+ mux { -+ function = "wifi"; -+ groups = "wf_dbdc"; -+ }; -+ conf { -+ pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", -+ "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", -+ "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", -+ "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", -+ "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", -+ "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", -+ "WF1_TOP_CLK", "WF1_TOP_DATA"; -+ drive-strength = <4>; -+ }; -+ }; -+ -+ wf_led_pins: wf-led-pins { -+ mux { -+ function = "led"; -+ groups = "wifi_led"; -+ }; -+ }; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi_flash_pins>; -+ status = "okay"; -+}; -+ -+&spi1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spic_pins>; -+ status = "okay"; -+}; -+ -+&ssusb { -+ status = "okay"; -+}; -+ -+&switch { -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ label = "wan"; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ label = "lan0"; -+ }; -+ -+ port@2 { -+ reg = <2>; -+ label = "lan1"; -+ }; -+ -+ port@3 { -+ reg = <3>; -+ label = "lan2"; -+ }; -+ -+ port@4 { -+ reg = <4>; -+ label = "lan3"; -+ }; -+ -+ port5: port@5 { -+ reg = <5>; -+ label = "lan4"; -+ phy-mode = "2500base-x"; -+ sfp = <&sfp2>; -+ managed = "in-band-status"; -+ }; -+ -+ port@6 { -+ reg = <6>; -+ label = "cpu"; -+ ethernet = <&gmac0>; -+ phy-mode = "2500base-x"; -+ -+ fixed-link { -+ speed = <2500>; -+ full-duplex; -+ pause; -+ }; -+ }; -+ }; -+}; -+ -+&trng { -+ status = "okay"; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart2_pins>; -+ status = "okay"; -+}; -+ -+&usb_phy { -+ status = "okay"; -+}; -+ -+&watchdog { -+ status = "okay"; -+}; -+ -+&wifi { -+ status = "okay"; -+ pinctrl-names = "default", "dbdc"; -+ pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>; -+ pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>; -+}; -+ diff --git a/6.1/target/linux/mediatek/patches-6.1/011-v6.5-arm64-mediatek-Propagate-chassis-type-where-possible.patch b/6.1/target/linux/mediatek/patches-6.1/011-v6.5-arm64-mediatek-Propagate-chassis-type-where-possible.patch deleted file mode 100644 index 79038334..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/011-v6.5-arm64-mediatek-Propagate-chassis-type-where-possible.patch +++ /dev/null @@ -1,323 +0,0 @@ -From 4c2d5411f4b101f7aa0fd74f80109e3afd6dc967 Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Wed, 17 May 2023 12:11:08 +0200 -Subject: [PATCH 11/19] arm64: mediatek: Propagate chassis-type where possible - -The chassis-type string identifies the form-factor of the system: -add this property to all device trees of devices for which the form -factor is known. - -Signed-off-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20230517101108.205654-1-angelogioacchino.delregno@collabora.com -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 1 + - arch/arm64/boot/dts/mediatek/mt6755-evb.dts | 1 + - arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 1 + - arch/arm64/boot/dts/mediatek/mt6795-evb.dts | 1 + - arch/arm64/boot/dts/mediatek/mt6797-evb.dts | 1 + - arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts | 1 + - arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 1 + - arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 1 + - arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 1 + - arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 1 + - arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8173-elm.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts | 1 + - .../boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts | 1 + - arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 1 + - 28 files changed, 28 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts -@@ -11,6 +11,7 @@ - - / { - model = "MediaTek MT2712 evaluation board"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt2712-evb", "mediatek,mt2712"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt6755-evb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt6755-evb.dts -@@ -9,6 +9,7 @@ - - / { - model = "MediaTek MT6755 EVB"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt6755-evb", "mediatek,mt6755"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts -@@ -10,6 +10,7 @@ - - / { - model = "MediaTek MT6779 EVB"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt6779-evb", "mediatek,mt6779"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt6795-evb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt6795-evb.dts -@@ -9,6 +9,7 @@ - - / { - model = "MediaTek MT6795 Evaluation Board"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt6795-evb", "mediatek,mt6795"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt6797-evb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt6797-evb.dts -@@ -9,6 +9,7 @@ - - / { - model = "MediaTek MT6797 Evaluation Board"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt6797-evb", "mediatek,mt6797"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts -+++ b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts -@@ -12,6 +12,7 @@ - - / { - model = "Mediatek X20 Development Board"; -+ chassis-type = "embedded"; - compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -15,6 +15,7 @@ - - / { - model = "Bananapi BPI-R64"; -+ chassis-type = "embedded"; - compatible = "bananapi,bpi-r64", "mediatek,mt7622"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -15,6 +15,7 @@ - - / { - model = "MediaTek MT7622 RFB1 board"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -@@ -16,6 +16,7 @@ - - / { - model = "Bananapi BPI-R3"; -+ chassis-type = "embedded"; - compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts -@@ -11,6 +11,7 @@ - - / { - model = "MediaTek MT7986a RFB"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts -@@ -9,6 +9,7 @@ - - / { - model = "MediaTek MT7986b RFB"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8167-pumpkin.dts -@@ -11,6 +11,7 @@ - - / { - model = "Pumpkin MT8167"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt8167-pumpkin", "mediatek,mt8167"; - - memory@40000000 { ---- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana-rev7.dts -@@ -8,6 +8,7 @@ - - / { - model = "Google Hanawl"; -+ chassis-type = "laptop"; - compatible = "google,hana-rev7", "mediatek,mt8173"; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dts -@@ -8,6 +8,7 @@ - - / { - model = "Google Hana"; -+ chassis-type = "laptop"; - compatible = "google,hana-rev6", "google,hana-rev5", - "google,hana-rev4", "google,hana-rev3", - "google,hana", "mediatek,mt8173"; ---- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dts -@@ -8,6 +8,7 @@ - - / { - model = "Google Elm"; -+ chassis-type = "laptop"; - compatible = "google,elm-rev8", "google,elm-rev7", "google,elm-rev6", - "google,elm-rev5", "google,elm-rev4", "google,elm-rev3", - "google,elm", "mediatek,mt8173"; ---- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts -@@ -10,6 +10,7 @@ - - / { - model = "MediaTek MT8173 evaluation board"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt8173-evb", "mediatek,mt8173"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts -@@ -11,6 +11,7 @@ - - / { - model = "MediaTek MT8183 evaluation board"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt8183-evb", "mediatek,mt8183"; - - aliases { ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-burnet.dts -@@ -9,6 +9,7 @@ - - / { - model = "Google burnet board"; -+ chassis-type = "convertible"; - compatible = "google,burnet", "mediatek,mt8183"; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts -@@ -9,6 +9,7 @@ - - / { - model = "Google damu board"; -+ chassis-type = "convertible"; - compatible = "google,damu", "mediatek,mt8183"; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dts -@@ -9,6 +9,7 @@ - - / { - model = "Google juniper sku16 board"; -+ chassis-type = "convertible"; - compatible = "google,juniper-sku16", "google,juniper", "mediatek,mt8183"; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu-sku22.dts -@@ -9,6 +9,7 @@ - - / { - model = "MediaTek kakadu board sku22"; -+ chassis-type = "tablet"; - compatible = "google,kakadu-rev3-sku22", "google,kakadu-rev2-sku22", - "google,kakadu", "mediatek,mt8183"; - }; ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kakadu.dts -@@ -9,6 +9,7 @@ - - / { - model = "MediaTek kakadu board"; -+ chassis-type = "tablet"; - compatible = "google,kakadu-rev3", "google,kakadu-rev2", - "google,kakadu", "mediatek,mt8183"; - }; ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku16.dts -@@ -12,6 +12,7 @@ - - / { - model = "MediaTek kodama sku16 board"; -+ chassis-type = "tablet"; - compatible = "google,kodama-sku16", "google,kodama", "mediatek,mt8183"; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku272.dts -@@ -12,6 +12,7 @@ - - / { - model = "MediaTek kodama sku272 board"; -+ chassis-type = "tablet"; - compatible = "google,kodama-sku272", "google,kodama", "mediatek,mt8183"; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku288.dts -@@ -12,6 +12,7 @@ - - / { - model = "MediaTek kodama sku288 board"; -+ chassis-type = "tablet"; - compatible = "google,kodama-sku288", "google,kodama", "mediatek,mt8183"; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku0.dts -@@ -14,6 +14,7 @@ - - / { - model = "MediaTek krane sku0 board"; -+ chassis-type = "tablet"; - compatible = "google,krane-sku0", "google,krane", "mediatek,mt8183"; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts -@@ -14,6 +14,7 @@ - - / { - model = "MediaTek krane sku176 board"; -+ chassis-type = "tablet"; - compatible = "google,krane-sku176", "google,krane", "mediatek,mt8183"; - }; - ---- a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts -+++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts -@@ -7,6 +7,7 @@ - - / { - model = "MediaTek MT8186 evaluation board"; -+ chassis-type = "embedded"; - compatible = "mediatek,mt8186-evb", "mediatek,mt8186"; - - aliases { diff --git a/6.1/target/linux/mediatek/patches-6.1/012-v6.5-arm64-dts-mt7986-add-PWM.patch b/6.1/target/linux/mediatek/patches-6.1/012-v6.5-arm64-dts-mt7986-add-PWM.patch deleted file mode 100644 index e8c47945..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/012-v6.5-arm64-dts-mt7986-add-PWM.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 3b92c547e3d4a35c6214b3e7fa1103d0749d83b1 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Fri, 21 Apr 2023 15:20:44 +0200 -Subject: [PATCH 12/19] arm64: dts: mt7986: add PWM - -This adds pwm node to mt7986. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20230421132047.42166-5-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -240,6 +240,20 @@ - status = "disabled"; - }; - -+ pwm: pwm@10048000 { -+ compatible = "mediatek,mt7986-pwm"; -+ reg = <0 0x10048000 0 0x1000>; -+ #clock-cells = <1>; -+ #pwm-cells = <2>; -+ interrupts = ; -+ clocks = <&topckgen CLK_TOP_PWM_SEL>, -+ <&infracfg CLK_INFRA_PWM_STA>, -+ <&infracfg CLK_INFRA_PWM1_CK>, -+ <&infracfg CLK_INFRA_PWM2_CK>; -+ clock-names = "top", "main", "pwm1", "pwm2"; -+ status = "disabled"; -+ }; -+ - uart0: serial@11002000 { - compatible = "mediatek,mt7986-uart", - "mediatek,mt6577-uart"; diff --git a/6.1/target/linux/mediatek/patches-6.1/013-v6.5-arm64-dts-mt7986-add-PWM-to-BPI-R3.patch b/6.1/target/linux/mediatek/patches-6.1/013-v6.5-arm64-dts-mt7986-add-PWM-to-BPI-R3.patch deleted file mode 100644 index ce908e3d..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/013-v6.5-arm64-dts-mt7986-add-PWM-to-BPI-R3.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 35e482bb599df010b4869017ff576dbb7a4d4c2e Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Fri, 21 Apr 2023 15:20:45 +0200 -Subject: [PATCH 13/19] arm64: dts: mt7986: add PWM to BPI-R3 - -Add pwm node and pinctrl to BananaPi R3 devicetree. - -Signed-off-by: Frank Wunderlich -Link: https://lore.kernel.org/r/20230421132047.42166-6-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -@@ -275,6 +275,13 @@ - }; - }; - -+ pwm_pins: pwm-pins { -+ mux { -+ function = "pwm"; -+ groups = "pwm0", "pwm1_0"; -+ }; -+ }; -+ - spi_flash_pins: spi-flash-pins { - mux { - function = "spi"; -@@ -345,6 +352,12 @@ - }; - }; - -+&pwm { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwm_pins>; -+ status = "okay"; -+}; -+ - &spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spi_flash_pins>; diff --git a/6.1/target/linux/mediatek/patches-6.1/014-v6.5-arm64-dts-mt7986-set-Wifi-Leds-low-active-for-BPI-R3.patch b/6.1/target/linux/mediatek/patches-6.1/014-v6.5-arm64-dts-mt7986-set-Wifi-Leds-low-active-for-BPI-R3.patch deleted file mode 100644 index c7b38484..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/014-v6.5-arm64-dts-mt7986-set-Wifi-Leds-low-active-for-BPI-R3.patch +++ /dev/null @@ -1,27 +0,0 @@ -From ccdda5714446db8690505371442f7807f5d7c6fc Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Sun, 5 Feb 2023 18:48:33 +0100 -Subject: [PATCH 14/19] arm64: dts: mt7986: set Wifi Leds low-active for BPI-R3 - -Leds for Wifi are low-active, so add property to devicetree. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20230205174833.107050-1-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 4 ++++ - 1 file changed, 4 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -@@ -460,5 +460,9 @@ - pinctrl-names = "default", "dbdc"; - pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>; - pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>; -+ -+ led { -+ led-active-low; -+ }; - }; - diff --git a/6.1/target/linux/mediatek/patches-6.1/015-v6.5-arm64-dts-mt7986-use-size-of-reserved-partition-for-.patch b/6.1/target/linux/mediatek/patches-6.1/015-v6.5-arm64-dts-mt7986-use-size-of-reserved-partition-for-.patch deleted file mode 100644 index 0b84f146..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/015-v6.5-arm64-dts-mt7986-use-size-of-reserved-partition-for-.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 1423b4b780adcf3994e63a5988a62d5d1d509bb1 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Sun, 28 May 2023 13:33:42 +0200 -Subject: [PATCH 15/19] arm64: dts: mt7986: use size of reserved partition for - bl2 - -To store uncompressed bl2 more space is required than partition is -actually defined. - -There is currently no known usage of this reserved partition. -Openwrt uses same partition layout. - -We added same change to u-boot with commit d7bb1099 [1]. - -[1] https://source.denx.de/u-boot/u-boot/-/commit/d7bb109900c1ca754a0198b9afb50e3161ffc21e - -Cc: stable@vger.kernel.org -Fixes: 8e01fb15b815 ("arm64: dts: mt7986: add Bananapi R3") -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Reviewed-by: Daniel Golle -Link: https://lore.kernel.org/r/20230528113343.7649-1-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso | 7 +------ - 1 file changed, 1 insertion(+), 6 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso -@@ -27,15 +27,10 @@ - - partition@0 { - label = "bl2"; -- reg = <0x0 0x20000>; -+ reg = <0x0 0x40000>; - read-only; - }; - -- partition@20000 { -- label = "reserved"; -- reg = <0x20000 0x20000>; -- }; -- - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x40000>; diff --git a/6.1/target/linux/mediatek/patches-6.1/016-v6.5-arm64-dts-mt7986-add-thermal-and-efuse.patch b/6.1/target/linux/mediatek/patches-6.1/016-v6.5-arm64-dts-mt7986-add-thermal-and-efuse.patch deleted file mode 100644 index 0d12079d..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/016-v6.5-arm64-dts-mt7986-add-thermal-and-efuse.patch +++ /dev/null @@ -1,80 +0,0 @@ -From 40a5a767d698ef7a71f8be851ea18b0a7a8b47bd Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 30 May 2023 22:12:33 +0200 -Subject: [PATCH 16/19] arm64: dts: mt7986: add thermal and efuse - -Add thermal related nodes to mt7986 devicetree. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20230530201235.22330-3-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 36 ++++++++++++++++++++++- - 1 file changed, 35 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -337,6 +337,15 @@ - status = "disabled"; - }; - -+ auxadc: adc@1100d000 { -+ compatible = "mediatek,mt7986-auxadc"; -+ reg = <0 0x1100d000 0 0x1000>; -+ clocks = <&infracfg CLK_INFRA_ADC_26M_CK>; -+ clock-names = "main"; -+ #io-channel-cells = <1>; -+ status = "disabled"; -+ }; -+ - ssusb: usb@11200000 { - compatible = "mediatek,mt7986-xhci", - "mediatek,mtk-xhci"; -@@ -375,6 +384,21 @@ - status = "disabled"; - }; - -+ thermal: thermal@1100c800 { -+ #thermal-sensor-cells = <1>; -+ compatible = "mediatek,mt7986-thermal"; -+ reg = <0 0x1100c800 0 0x800>; -+ interrupts = ; -+ clocks = <&infracfg CLK_INFRA_THERM_CK>, -+ <&infracfg CLK_INFRA_ADC_26M_CK>, -+ <&infracfg CLK_INFRA_ADC_FRC_CK>; -+ clock-names = "therm", "auxadc", "adc_32k"; -+ mediatek,auxadc = <&auxadc>; -+ mediatek,apmixedsys = <&apmixedsys>; -+ nvmem-cells = <&thermal_calibration>; -+ nvmem-cell-names = "calibration-data"; -+ }; -+ - pcie: pcie@11280000 { - compatible = "mediatek,mt7986-pcie", - "mediatek,mt8192-pcie"; -@@ -426,6 +450,17 @@ - }; - }; - -+ efuse: efuse@11d00000 { -+ compatible = "mediatek,mt7986-efuse", "mediatek,efuse"; -+ reg = <0 0x11d00000 0 0x1000>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ thermal_calibration: calib@274 { -+ reg = <0x274 0xc>; -+ }; -+ }; -+ - usb_phy: t-phy@11e10000 { - compatible = "mediatek,mt7986-tphy", - "mediatek,generic-tphy-v2"; -@@ -567,5 +602,4 @@ - memory-region = <&wmcpu_emi>; - }; - }; -- - }; diff --git a/6.1/target/linux/mediatek/patches-6.1/017-v6.5-arm64-dts-mt7986-add-thermal-zones.patch b/6.1/target/linux/mediatek/patches-6.1/017-v6.5-arm64-dts-mt7986-add-thermal-zones.patch deleted file mode 100644 index 3fe3e885..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/017-v6.5-arm64-dts-mt7986-add-thermal-zones.patch +++ /dev/null @@ -1,51 +0,0 @@ -From bb78d0cf5117517f1ed296ae71048945d9107675 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 30 May 2023 22:12:34 +0200 -Subject: [PATCH 17/19] arm64: dts: mt7986: add thermal-zones - -Add thermal-zones to mt7986 devicetree. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20230530201235.22330-4-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 28 +++++++++++++++++++++++ - 1 file changed, 28 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -602,4 +602,32 @@ - memory-region = <&wmcpu_emi>; - }; - }; -+ -+ thermal-zones { -+ cpu_thermal: cpu-thermal { -+ polling-delay-passive = <1000>; -+ polling-delay = <1000>; -+ thermal-sensors = <&thermal 0>; -+ -+ trips { -+ cpu_trip_active_high: active-high { -+ temperature = <115000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ cpu_trip_active_low: active-low { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ -+ cpu_trip_passive: passive { -+ temperature = <40000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ }; -+ }; -+ }; - }; diff --git a/6.1/target/linux/mediatek/patches-6.1/018-v6.5-arm64-dts-mt7986-add-pwm-fan-and-cooling-maps-to-BPI.patch b/6.1/target/linux/mediatek/patches-6.1/018-v6.5-arm64-dts-mt7986-add-pwm-fan-and-cooling-maps-to-BPI.patch deleted file mode 100644 index ca7d872a..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/018-v6.5-arm64-dts-mt7986-add-pwm-fan-and-cooling-maps-to-BPI.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 5d90603b09e5814ffc38c47e79ccf9bc564f9296 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 30 May 2023 22:12:35 +0200 -Subject: [PATCH 18/19] arm64: dts: mt7986: add pwm-fan and cooling-maps to - BPI-R3 dts - -Add pwm-fan and cooling-maps to BananaPi-R3 devicetree. - -Signed-off-by: Daniel Golle -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20230530201235.22330-5-linux@fw-web.de -Signed-off-by: Matthias Brugger ---- - .../dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 31 +++++++++++++++++++ - 1 file changed, 31 insertions(+) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -@@ -38,6 +38,15 @@ - regulator-always-on; - }; - -+ fan: pwm-fan { -+ compatible = "pwm-fan"; -+ #cooling-cells = <2>; -+ /* cooling level (0, 1, 2) - pwm inverted */ -+ cooling-levels = <255 96 0>; -+ pwms = <&pwm 0 10000 0>; -+ status = "okay"; -+ }; -+ - gpio-keys { - compatible = "gpio-keys"; - -@@ -133,6 +142,28 @@ - }; - }; - -+&cpu_thermal { -+ cooling-maps { -+ cpu-active-high { -+ /* active: set fan to cooling level 2 */ -+ cooling-device = <&fan 2 2>; -+ trip = <&cpu_trip_active_high>; -+ }; -+ -+ cpu-active-low { -+ /* active: set fan to cooling level 1 */ -+ cooling-device = <&fan 1 1>; -+ trip = <&cpu_trip_active_low>; -+ }; -+ -+ cpu-passive { -+ /* passive: set fan to cooling level 0 */ -+ cooling-device = <&fan 0 0>; -+ trip = <&cpu_trip_passive>; -+ }; -+ }; -+}; -+ - &crypto { - status = "okay"; - }; diff --git a/6.1/target/linux/mediatek/patches-6.1/019-v6.5-arm64-dts-mt7986-increase-bl2-partition-on-NAND-of-B.patch b/6.1/target/linux/mediatek/patches-6.1/019-v6.5-arm64-dts-mt7986-increase-bl2-partition-on-NAND-of-B.patch deleted file mode 100644 index 9cc6cad0..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/019-v6.5-arm64-dts-mt7986-increase-bl2-partition-on-NAND-of-B.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 6dd3b939370094eb79529683be84500f3c757404 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 6 Jun 2023 16:43:20 +0100 -Subject: [PATCH 19/19] arm64: dts: mt7986: increase bl2 partition on NAND of - Bananapi R3 - -The bootrom burned into the MT7986 SoC will try multiple locations on -the SPI-NAND flash to load bl2 in case the bl2 image located at the the -previously attempted offset is corrupt. - -Use 0x100000 instead of 0x80000 as partition size for bl2 on SPI-NAND, -allowing for up to four redundant copies of bl2 (typically sized a -bit less than 0x40000). - -Fixes: 8e01fb15b8157 ("arm64: dts: mt7986: add Bananapi R3") -Signed-off-by: Daniel Golle -Link: https://lore.kernel.org/r/ZH9UGF99RgzrHZ88@makrotopia.org -Signed-off-by: Matthias Brugger ---- - .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso -@@ -29,13 +29,13 @@ - - partition@0 { - label = "bl2"; -- reg = <0x0 0x80000>; -+ reg = <0x0 0x100000>; - read-only; - }; - -- partition@80000 { -+ partition@100000 { - label = "reserved"; -- reg = <0x80000 0x300000>; -+ reg = <0x100000 0x280000>; - }; - - partition@380000 { diff --git a/6.1/target/linux/mediatek/patches-6.1/100-dts-update-mt7622-rfb1.patch b/6.1/target/linux/mediatek/patches-6.1/100-dts-update-mt7622-rfb1.patch deleted file mode 100644 index 1c249c03..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/100-dts-update-mt7622-rfb1.patch +++ /dev/null @@ -1,107 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -1,7 +1,6 @@ - /* -- * Copyright (c) 2017 MediaTek Inc. -- * Author: Ming Huang -- * Sean Wang -+ * Copyright (c) 2018 MediaTek Inc. -+ * Author: Ryder Lee - * - * SPDX-License-Identifier: (GPL-2.0 OR MIT) - */ -@@ -24,7 +23,7 @@ - - chosen { - stdout-path = "serial0:115200n8"; -- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512"; -+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512"; - }; - - cpus { -@@ -45,18 +44,18 @@ - key-factory { - label = "factory"; - linux,code = ; -- gpios = <&pio 0 0>; -+ gpios = <&pio 0 GPIO_ACTIVE_LOW>; - }; - - key-wps { - label = "wps"; - linux,code = ; -- gpios = <&pio 102 0>; -+ gpios = <&pio 102 GPIO_ACTIVE_LOW>; - }; - }; - - memory { -- reg = <0 0x40000000 0 0x20000000>; -+ reg = <0 0x40000000 0 0x40000000>; - }; - - reg_1p8v: regulator-1p8v { -@@ -132,22 +131,22 @@ - - port@0 { - reg = <0>; -- label = "lan0"; -+ label = "lan1"; - }; - - port@1 { - reg = <1>; -- label = "lan1"; -+ label = "lan2"; - }; - - port@2 { - reg = <2>; -- label = "lan2"; -+ label = "lan3"; - }; - - port@3 { - reg = <3>; -- label = "lan3"; -+ label = "lan4"; - }; - - port@4 { -@@ -240,7 +239,22 @@ - status = "okay"; - }; - -+&pcie1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie1_pins>; -+ status = "okay"; -+}; -+ - &pio { -+ /* Attention: GPIO 90 is used to switch between PCIe@1,0 and -+ * SATA functions. i.e. output-high: PCIe, output-low: SATA -+ */ -+ asm_sel { -+ gpio-hog; -+ gpios = <90 GPIO_ACTIVE_HIGH>; -+ output-high; -+ }; -+ - /* eMMC is shared pin with parallel NAND */ - emmc_pins_default: emmc-pins-default { - mux { -@@ -517,11 +531,11 @@ - }; - - &sata { -- status = "okay"; -+ status = "disabled"; - }; - - &sata_phy { -- status = "okay"; -+ status = "disabled"; - }; - - &spi0 { diff --git a/6.1/target/linux/mediatek/patches-6.1/101-dts-update-mt7629-rfb.patch b/6.1/target/linux/mediatek/patches-6.1/101-dts-update-mt7629-rfb.patch deleted file mode 100644 index b1770371..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/101-dts-update-mt7629-rfb.patch +++ /dev/null @@ -1,60 +0,0 @@ ---- a/arch/arm/boot/dts/mt7629-rfb.dts -+++ b/arch/arm/boot/dts/mt7629-rfb.dts -@@ -18,6 +18,7 @@ - - chosen { - stdout-path = "serial0:115200n8"; -+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8"; - }; - - gpio-keys { -@@ -70,6 +71,10 @@ - compatible = "mediatek,eth-mac"; - reg = <0>; - phy-mode = "2500base-x"; -+ -+ nvmem-cells = <&macaddr_factory_2a>; -+ nvmem-cell-names = "mac-address"; -+ - fixed-link { - speed = <2500>; - full-duplex; -@@ -82,6 +87,9 @@ - reg = <1>; - phy-mode = "gmii"; - phy-handle = <&phy0>; -+ -+ nvmem-cells = <&macaddr_factory_24>; -+ nvmem-cell-names = "mac-address"; - }; - - mdio: mdio-bus { -@@ -133,8 +141,9 @@ - }; - - partition@b0000 { -- label = "kernel"; -+ label = "firmware"; - reg = <0xb0000 0xb50000>; -+ compatible = "denx,fit"; - }; - }; - }; -@@ -273,3 +282,17 @@ - pinctrl-0 = <&watchdog_pins>; - status = "okay"; - }; -+ -+&factory { -+ compatible = "nvmem-cells"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ macaddr_factory_24: macaddr@24 { -+ reg = <0x24 0x6>; -+ }; -+ -+ macaddr_factory_2a: macaddr@2a { -+ reg = <0x2a 0x6>; -+ }; -+}; diff --git a/6.1/target/linux/mediatek/patches-6.1/103-mt7623-enable-arch-timer.patch b/6.1/target/linux/mediatek/patches-6.1/103-mt7623-enable-arch-timer.patch deleted file mode 100644 index 04df7b92..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/103-mt7623-enable-arch-timer.patch +++ /dev/null @@ -1,20 +0,0 @@ -From d6a596012150960f0f3a214d31bbac4b607dbd1e Mon Sep 17 00:00:00 2001 -From: Chuanhong Guo -Date: Fri, 29 Apr 2022 10:40:56 +0800 -Subject: [PATCH] arm: mediatek: select arch timer for mt7623 - -Signed-off-by: Chuanhong Guo ---- - arch/arm/mach-mediatek/Kconfig | 1 + - 1 file changed, 1 insertion(+) - ---- a/arch/arm/mach-mediatek/Kconfig -+++ b/arch/arm/mach-mediatek/Kconfig -@@ -26,6 +26,7 @@ config MACH_MT6592 - config MACH_MT7623 - bool "MediaTek MT7623 SoCs support" - default ARCH_MEDIATEK -+ select HAVE_ARM_ARCH_TIMER - - config MACH_MT7629 - bool "MediaTek MT7629 SoCs support" diff --git a/6.1/target/linux/mediatek/patches-6.1/104-mt7622-add-snor-irq.patch b/6.1/target/linux/mediatek/patches-6.1/104-mt7622-add-snor-irq.patch deleted file mode 100644 index 0d9c91f4..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/104-mt7622-add-snor-irq.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -578,6 +578,7 @@ - compatible = "mediatek,mt7622-nor", - "mediatek,mt8173-nor"; - reg = <0 0x11014000 0 0xe0>; -+ interrupts = ; - clocks = <&pericfg CLK_PERI_FLASH_PD>, - <&topckgen CLK_TOP_FLASH_SEL>; - clock-names = "spi", "sf"; diff --git a/6.1/target/linux/mediatek/patches-6.1/105-dts-mt7622-enable-pstore.patch b/6.1/target/linux/mediatek/patches-6.1/105-dts-mt7622-enable-pstore.patch deleted file mode 100644 index 93da722e..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/105-dts-mt7622-enable-pstore.patch +++ /dev/null @@ -1,16 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -134,6 +134,13 @@ - #size-cells = <2>; - ranges; - -+ /* 64 KiB reserved for ramoops/pstore */ -+ ramoops@42ff0000 { -+ compatible = "ramoops"; -+ reg = <0 0x42ff0000 0 0x10000>; -+ record-size = <0x1000>; -+ }; -+ - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x30000>; diff --git a/6.1/target/linux/mediatek/patches-6.1/110-dts-fix-bpi2-console.patch b/6.1/target/linux/mediatek/patches-6.1/110-dts-fix-bpi2-console.patch deleted file mode 100644 index 8dc53d29..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/110-dts-fix-bpi2-console.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -19,6 +19,7 @@ - - chosen { - stdout-path = "serial2:115200n8"; -+ bootargs = "console=ttyS2,115200n8 console=tty1"; - }; - - connector { diff --git a/6.1/target/linux/mediatek/patches-6.1/111-dts-fix-bpi64-console.patch b/6.1/target/linux/mediatek/patches-6.1/111-dts-fix-bpi64-console.patch deleted file mode 100644 index f77f10cb..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/111-dts-fix-bpi64-console.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -24,7 +24,7 @@ - - chosen { - stdout-path = "serial0:115200n8"; -- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512"; -+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512"; - }; - - cpus { diff --git a/6.1/target/linux/mediatek/patches-6.1/112-dts-fix-bpi64-lan-names.patch b/6.1/target/linux/mediatek/patches-6.1/112-dts-fix-bpi64-lan-names.patch deleted file mode 100644 index 816683e6..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/112-dts-fix-bpi64-lan-names.patch +++ /dev/null @@ -1,37 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -20,6 +20,7 @@ - - aliases { - serial0 = &uart0; -+ ethernet0 = &gmac0; - }; - - chosen { -@@ -164,22 +165,22 @@ - - port@1 { - reg = <1>; -- label = "lan0"; -+ label = "lan1"; - }; - - port@2 { - reg = <2>; -- label = "lan1"; -+ label = "lan2"; - }; - - port@3 { - reg = <3>; -- label = "lan2"; -+ label = "lan3"; - }; - - port@4 { - reg = <4>; -- label = "lan3"; -+ label = "lan4"; - }; - - port@6 { diff --git a/6.1/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch b/6.1/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch deleted file mode 100644 index bf1912a9..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/113-dts-fix-bpi64-leds-and-buttons.patch +++ /dev/null @@ -1,47 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -21,6 +21,10 @@ - aliases { - serial0 = &uart0; - ethernet0 = &gmac0; -+ led-boot = &led_system_green; -+ led-failsafe = &led_system_blue; -+ led-running = &led_system_green; -+ led-upgrade = &led_system_blue; - }; - - chosen { -@@ -44,8 +48,8 @@ - compatible = "gpio-keys"; - - factory-key { -- label = "factory"; -- linux,code = ; -+ label = "reset"; -+ linux,code = ; - gpios = <&pio 0 GPIO_ACTIVE_HIGH>; - }; - -@@ -59,17 +63,17 @@ - leds { - compatible = "gpio-leds"; - -- led-0 { -+ led_system_green: led-0 { - label = "bpi-r64:pio:green"; - color = ; - gpios = <&pio 89 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - -- led-1 { -- label = "bpi-r64:pio:red"; -- color = ; -- gpios = <&pio 88 GPIO_ACTIVE_HIGH>; -+ led_system_blue: led-1 { -+ label = "bpi-r64:pio:blue"; -+ color = ; -+ gpios = <&pio 85 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - }; diff --git a/6.1/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch b/6.1/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch deleted file mode 100644 index 3d1b9021..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/114-dts-bpi64-disable-rtc.patch +++ /dev/null @@ -1,21 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -558,12 +558,16 @@ - status = "okay"; - }; - -+&rtc { -+ status = "disabled"; -+}; -+ - &sata { -- status = "disable"; -+ status = "disabled"; - }; - - &sata_phy { -- status = "disable"; -+ status = "disabled"; - }; - - &spi0 { diff --git a/6.1/target/linux/mediatek/patches-6.1/115-dts-bpi64-add-snand-support.patch b/6.1/target/linux/mediatek/patches-6.1/115-dts-bpi64-add-snand-support.patch deleted file mode 100644 index b159a17c..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/115-dts-bpi64-add-snand-support.patch +++ /dev/null @@ -1,50 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -255,14 +255,42 @@ - status = "disabled"; - }; - --&nor_flash { -- pinctrl-names = "default"; -- pinctrl-0 = <&spi_nor_pins>; -- status = "disabled"; -+&bch { -+ status = "okay"; -+}; - -+&snfi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&serial_nand_pins>; -+ status = "okay"; - flash@0 { -- compatible = "jedec,spi-nor"; -+ compatible = "spi-nand"; - reg = <0>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ nand-ecc-engine = <&snfi>; -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "bl2"; -+ reg = <0x0 0x80000>; -+ read-only; -+ }; -+ -+ partition@80000 { -+ label = "fip"; -+ reg = <0x80000 0x200000>; -+ read-only; -+ }; -+ -+ partition@280000 { -+ label = "ubi"; -+ reg = <0x280000 0x7d80000>; -+ }; -+ }; - }; - }; - diff --git a/6.1/target/linux/mediatek/patches-6.1/121-hack-spi-nand-1b-bbm.patch b/6.1/target/linux/mediatek/patches-6.1/121-hack-spi-nand-1b-bbm.patch deleted file mode 100644 index ff5521c4..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/121-hack-spi-nand-1b-bbm.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -724,7 +724,7 @@ static int spinand_mtd_write(struct mtd_ - static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos) - { - struct spinand_device *spinand = nand_to_spinand(nand); -- u8 marker[2] = { }; -+ u8 marker[1] = { }; - struct nand_page_io_req req = { - .pos = *pos, - .ooblen = sizeof(marker), -@@ -735,7 +735,7 @@ static bool spinand_isbad(struct nand_de - - spinand_select_target(spinand, pos->target); - spinand_read_page(spinand, &req); -- if (marker[0] != 0xff || marker[1] != 0xff) -+ if (marker[0] != 0xff) - return true; - - return false; diff --git a/6.1/target/linux/mediatek/patches-6.1/130-dts-mt7629-add-snand-support.patch b/6.1/target/linux/mediatek/patches-6.1/130-dts-mt7629-add-snand-support.patch deleted file mode 100644 index 82654e68..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/130-dts-mt7629-add-snand-support.patch +++ /dev/null @@ -1,94 +0,0 @@ -From c813fbe806257c574240770ef716fbee19f7dbfa Mon Sep 17 00:00:00 2001 -From: Xiangsheng Hou -Date: Thu, 6 Jun 2019 16:29:04 +0800 -Subject: [PATCH] spi: spi-mem: Mediatek: Add SPI Nand support for MT7629 - -Signed-off-by: Xiangsheng Hou ---- - arch/arm/boot/dts/mt7629-rfb.dts | 45 ++++++++++++++++++++++++++++++++ - arch/arm/boot/dts/mt7629.dtsi | 22 ++++++++++++++++ - 3 files changed, 79 insertions(+) - ---- a/arch/arm/boot/dts/mt7629.dtsi -+++ b/arch/arm/boot/dts/mt7629.dtsi -@@ -272,6 +272,27 @@ - status = "disabled"; - }; - -+ snfi: spi@1100d000 { -+ compatible = "mediatek,mt7629-snand"; -+ reg = <0x1100d000 0x1000>; -+ interrupts = ; -+ clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>; -+ clock-names = "nfi_clk", "pad_clk"; -+ nand-ecc-engine = <&bch>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ bch: ecc@1100e000 { -+ compatible = "mediatek,mt7622-ecc"; -+ reg = <0x1100e000 0x1000>; -+ interrupts = ; -+ clocks = <&pericfg CLK_PERI_NFIECC_PD>; -+ clock-names = "nfiecc_clk"; -+ status = "disabled"; -+ }; -+ - spi: spi@1100a000 { - compatible = "mediatek,mt7629-spi", - "mediatek,mt7622-spi"; ---- a/arch/arm/boot/dts/mt7629-rfb.dts -+++ b/arch/arm/boot/dts/mt7629-rfb.dts -@@ -255,6 +255,50 @@ - }; - }; - -+&bch { -+ status = "okay"; -+}; -+ -+&snfi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&serial_nand_pins>; -+ status = "okay"; -+ flash@0 { -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ nand-ecc-engine = <&snfi>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "Bootloader"; -+ reg = <0x00000 0x0100000>; -+ read-only; -+ }; -+ -+ partition@100000 { -+ label = "Config"; -+ reg = <0x100000 0x0040000>; -+ }; -+ -+ partition@140000 { -+ label = "factory"; -+ reg = <0x140000 0x0080000>; -+ }; -+ -+ partition@1c0000 { -+ label = "firmware"; -+ reg = <0x1c0000 0x1000000>; -+ }; -+ }; -+ }; -+}; -+ - &spi { - pinctrl-names = "default"; - pinctrl-0 = <&spi_pins>; diff --git a/6.1/target/linux/mediatek/patches-6.1/131-dts-mt7622-add-snand-support.patch b/6.1/target/linux/mediatek/patches-6.1/131-dts-mt7622-add-snand-support.patch deleted file mode 100644 index 9cfe69eb..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/131-dts-mt7622-add-snand-support.patch +++ /dev/null @@ -1,68 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -538,6 +538,65 @@ - status = "disabled"; - }; - -+&bch { -+ status = "okay"; -+}; -+ -+&snfi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&serial_nand_pins>; -+ status = "okay"; -+ flash@0 { -+ compatible = "spi-nand"; -+ reg = <0>; -+ spi-tx-bus-width = <4>; -+ spi-rx-bus-width = <4>; -+ nand-ecc-engine = <&snfi>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "Preloader"; -+ reg = <0x00000 0x0080000>; -+ read-only; -+ }; -+ -+ partition@80000 { -+ label = "ATF"; -+ reg = <0x80000 0x0040000>; -+ }; -+ -+ partition@c0000 { -+ label = "Bootloader"; -+ reg = <0xc0000 0x0080000>; -+ }; -+ -+ partition@140000 { -+ label = "Config"; -+ reg = <0x140000 0x0080000>; -+ }; -+ -+ partition@1c0000 { -+ label = "Factory"; -+ reg = <0x1c0000 0x0100000>; -+ }; -+ -+ partition@200000 { -+ label = "firmware"; -+ reg = <0x2c0000 0x2000000>; -+ }; -+ -+ partition@2200000 { -+ label = "User_data"; -+ reg = <0x22c0000 0x4000000>; -+ }; -+ }; -+ }; -+}; -+ - &spi0 { - pinctrl-names = "default"; - pinctrl-0 = <&spic0_pins>; diff --git a/6.1/target/linux/mediatek/patches-6.1/140-dts-fix-wmac-support-for-mt7622-rfb1.patch b/6.1/target/linux/mediatek/patches-6.1/140-dts-fix-wmac-support-for-mt7622-rfb1.patch deleted file mode 100644 index b01ce97c..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/140-dts-fix-wmac-support-for-mt7622-rfb1.patch +++ /dev/null @@ -1,18 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -579,7 +579,7 @@ - reg = <0x140000 0x0080000>; - }; - -- partition@1c0000 { -+ factory: partition@1c0000 { - label = "Factory"; - reg = <0x1c0000 0x0100000>; - }; -@@ -640,5 +640,6 @@ - &wmac { - pinctrl-names = "default"; - pinctrl-0 = <&wmac_pins>; -+ mediatek,mtd-eeprom = <&factory 0x0000>; - status = "okay"; - }; diff --git a/6.1/target/linux/mediatek/patches-6.1/150-dts-mt7623-eip97-inside-secure-support.patch b/6.1/target/linux/mediatek/patches-6.1/150-dts-mt7623-eip97-inside-secure-support.patch deleted file mode 100644 index 0860a22c..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/150-dts-mt7623-eip97-inside-secure-support.patch +++ /dev/null @@ -1,24 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623.dtsi -+++ b/arch/arm/boot/dts/mt7623.dtsi -@@ -984,17 +984,15 @@ - }; - - crypto: crypto@1b240000 { -- compatible = "mediatek,eip97-crypto"; -+ compatible = "inside-secure,safexcel-eip97"; - reg = <0 0x1b240000 0 0x20000>; - interrupts = , - , - , -- , -- ; -+ ; -+ interrupt-names = "ring0", "ring1", "ring2", "ring3"; - clocks = <ðsys CLK_ETHSYS_CRYPTO>; -- clock-names = "cryp"; -- power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; -- status = "disabled"; -+ status = "okay"; - }; - - bdpsys: syscon@1c000000 { diff --git a/6.1/target/linux/mediatek/patches-6.1/160-dts-mt7623-bpi-r2-earlycon.patch b/6.1/target/linux/mediatek/patches-6.1/160-dts-mt7623-bpi-r2-earlycon.patch deleted file mode 100644 index 091cffc3..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/160-dts-mt7623-bpi-r2-earlycon.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -19,7 +19,7 @@ - - chosen { - stdout-path = "serial2:115200n8"; -- bootargs = "console=ttyS2,115200n8 console=tty1"; -+ bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1"; - }; - - connector { diff --git a/6.1/target/linux/mediatek/patches-6.1/161-dts-mt7623-bpi-r2-mmc-device-order.patch b/6.1/target/linux/mediatek/patches-6.1/161-dts-mt7623-bpi-r2-mmc-device-order.patch deleted file mode 100644 index d1bafc15..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/161-dts-mt7623-bpi-r2-mmc-device-order.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -15,6 +15,8 @@ - - aliases { - serial2 = &uart2; -+ mmc0 = &mmc0; -+ mmc1 = &mmc1; - }; - - chosen { diff --git a/6.1/target/linux/mediatek/patches-6.1/162-dts-mt7623-bpi-r2-led-aliases.patch b/6.1/target/linux/mediatek/patches-6.1/162-dts-mt7623-bpi-r2-led-aliases.patch deleted file mode 100644 index f6745add..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/162-dts-mt7623-bpi-r2-led-aliases.patch +++ /dev/null @@ -1,29 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -17,6 +17,10 @@ - serial2 = &uart2; - mmc0 = &mmc0; - mmc1 = &mmc1; -+ led-boot = &led_system_green; -+ led-failsafe = &led_system_blue; -+ led-running = &led_system_green; -+ led-upgrade = &led_system_blue; - }; - - chosen { -@@ -112,13 +116,13 @@ - pinctrl-names = "default"; - pinctrl-0 = <&led_pins_a>; - -- blue { -+ led_system_blue: blue { - label = "bpi-r2:pio:blue"; - gpios = <&pio 240 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - -- green { -+ led_system_green: green { - label = "bpi-r2:pio:green"; - gpios = <&pio 241 GPIO_ACTIVE_LOW>; - default-state = "off"; diff --git a/6.1/target/linux/mediatek/patches-6.1/163-dts-mt7623-bpi-r2-ethernet-alias.patch b/6.1/target/linux/mediatek/patches-6.1/163-dts-mt7623-bpi-r2-ethernet-alias.patch deleted file mode 100644 index b1dd75a4..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/163-dts-mt7623-bpi-r2-ethernet-alias.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts -@@ -15,6 +15,7 @@ - - aliases { - serial2 = &uart2; -+ ethernet0 = &gmac0; - mmc0 = &mmc0; - mmc1 = &mmc1; - led-boot = &led_system_green; diff --git a/6.1/target/linux/mediatek/patches-6.1/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch b/6.1/target/linux/mediatek/patches-6.1/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch deleted file mode 100644 index 5a834ac3..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/180-dts-mt7622-bpi-r64-add-mt7531-irq.patch +++ /dev/null @@ -1,13 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -156,6 +156,10 @@ - switch@0 { - compatible = "mediatek,mt7531"; - reg = <0>; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ interrupt-parent = <&pio>; -+ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; - reset-gpios = <&pio 54 0>; - - ports { diff --git a/6.1/target/linux/mediatek/patches-6.1/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch b/6.1/target/linux/mediatek/patches-6.1/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch deleted file mode 100644 index 1e04d23a..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/190-arm64-dts-mediatek-mt7622-fix-GICv2-range.patch +++ /dev/null @@ -1,106 +0,0 @@ -From patchwork Tue Apr 26 19:51:36 2022 -Content-Type: text/plain; charset="utf-8" -MIME-Version: 1.0 -Content-Transfer-Encoding: 7bit -X-Patchwork-Submitter: Daniel Golle -X-Patchwork-Id: 12827872 -Return-Path: - -X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on - aws-us-west-2-korg-lkml-1.web.codeaurora.org -Received: from bombadil.infradead.org (bombadil.infradead.org - [198.137.202.133]) - (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) - (No client certificate requested) - by smtp.lore.kernel.org (Postfix) with ESMTPS id BACF3C433EF - for ; - Tue, 26 Apr 2022 19:53:05 +0000 (UTC) -DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; - d=lists.infradead.org; s=bombadil.20210309; h=Sender: - Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: - List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Subject:Cc:To: - From:Date:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: - Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: - List-Owner; bh=OWGSxvlKoyPWz6b629RNINucULo6oOdFssAIiJETWRg=; b=T0HEjee0FX3hlb - x5jl7xLK5sKM0pkE2oRgwzthbFlNg8ST1j/2GkgcgT0S2Bi0vRfFxHeu/RKzS9RmiVnKJnPGL8ctg - WoBLyO5i+NcmosGoy6MmoOjGTNhj/+3q3Z1jRLBSJ4ySSP22X77YeuJTmVzySPUllQhWvDhjMVCR9 - QBRmQdc6gCAg3IYGEbWwS2TG+UHveDCeZRWxMzrwI8UPadNCRFROwugmiQ3mdU41lHCTDpnlfuRJh - o1igLKfMBLz+D8rFYvDh7FfkcKkY6lNoswA2HKUun1MEzgoyQKmITPnG2maX/BvJJuj/B3ZJShh4k - AZHmXoQxq1mrsm2FxfnQ==; -Received: from localhost ([::1] helo=bombadil.infradead.org) - by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) - id 1njRE5-00G05D-9z; Tue, 26 Apr 2022 19:51:57 +0000 -Received: from fudo.makrotopia.org ([2a07:2ec0:3002::71]) - by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) - id 1njRE1-00G03h-9H; Tue, 26 Apr 2022 19:51:55 +0000 -Received: from local - by fudo.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) - (Exim 4.94.2) (envelope-from ) - id 1njRDu-0006aF-4F; Tue, 26 Apr 2022 21:51:46 +0200 -Date: Tue, 26 Apr 2022 20:51:36 +0100 -From: Daniel Golle -To: devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, - linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org -Cc: Rob Herring , - Krzysztof Kozlowski , - Matthias Brugger -Subject: [PATCH] arm64: dts: mediatek: mt7622: fix GICv2 range -Message-ID: -MIME-Version: 1.0 -Content-Disposition: inline -X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 -X-CRM114-CacheID: sfid-20220426_125153_359242_EA3D452C -X-CRM114-Status: GOOD ( 12.45 ) -X-BeenThere: linux-arm-kernel@lists.infradead.org -X-Mailman-Version: 2.1.34 -Precedence: list -List-Id: -List-Unsubscribe: - , - -List-Archive: -List-Post: -List-Help: -List-Subscribe: - , - -Sender: "linux-arm-kernel" -Errors-To: - linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org - -With the current range specified for the CPU interface there is an -error message at boot: - -GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set - -Setting irqchip.gicv2_force_probe=1 in bootargs results in: - -GIC: Aliased GICv2 at 0x0000000010320000, trying to find the canonical range over 128kB -GIC: Adjusting CPU interface base to 0x000000001032f000 -GIC: Using split EOI/Deactivate mode - -Using the adjusted CPU interface base and 8K size results in only the -final line remaining and fully working system as well as /proc/interrupts -showing additional IPI3,4,5,6: - -IPI3: 0 0 CPU stop (for crash dump) interrupts -IPI4: 0 0 Timer broadcast interrupts -IPI5: 0 0 IRQ work interrupts -IPI6: 0 0 CPU wake-up interrupts - -Signed-off-by: Daniel Golle ---- - arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -346,7 +346,7 @@ - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10310000 0 0x1000>, -- <0 0x10320000 0 0x1000>, -+ <0 0x1032f000 0 0x2000>, - <0 0x10340000 0 0x2000>, - <0 0x10360000 0 0x2000>; - }; diff --git a/6.1/target/linux/mediatek/patches-6.1/193-dts-mt7623-thermal_zone_fix.patch b/6.1/target/linux/mediatek/patches-6.1/193-dts-mt7623-thermal_zone_fix.patch deleted file mode 100644 index 1cfb53d6..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/193-dts-mt7623-thermal_zone_fix.patch +++ /dev/null @@ -1,48 +0,0 @@ -From 824d56e753a588fcfd650db1822e34a02a48bb77 Mon Sep 17 00:00:00 2001 -From: Bruno Umuarama -Date: Thu, 13 Oct 2022 21:18:21 +0000 -Subject: [PATCH] mediatek: mt7623: fix thermal zone -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Raising the temperatures for passive and active trips. @VA1DER -proposed at issue 9396 to remove passive trip. This commit relates to -his suggestion. - -Without this patch. the CPU will be throttled all the way down to 98MHz -if the temperature rises even a degree above the trip point, and it was -further discovered that if the internal temperature of the device is -above the first trip point temperature when it boots then it will start -in a throttled state and even -$ echo disabled > /sys/class/thermal/thermal_zone0/mode -will have no effect. - -The patch increases the passive trip point and active cooling map. The -throttling temperature will then be at 77°C and 82°C, which is still a -low enough temperature for ARM devices to not be in the real danger -zone, and gives some operational headroom. - -Signed-off-by: Bruno Umuarama ---- - arch/arm/boot/dts/mt7623.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm/boot/dts/mt7623.dtsi -+++ b/arch/arm/boot/dts/mt7623.dtsi -@@ -160,13 +160,13 @@ - - trips { - cpu_passive: cpu-passive { -- temperature = <57000>; -+ temperature = <77000>; - hysteresis = <2000>; - type = "passive"; - }; - - cpu_active: cpu-active { -- temperature = <67000>; -+ temperature = <82000>; - hysteresis = <2000>; - type = "active"; - }; diff --git a/6.1/target/linux/mediatek/patches-6.1/194-dts-mt7968a-add-ramoops.patch b/6.1/target/linux/mediatek/patches-6.1/194-dts-mt7968a-add-ramoops.patch deleted file mode 100644 index 161c1e75..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/194-dts-mt7968a-add-ramoops.patch +++ /dev/null @@ -1,17 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -68,6 +68,14 @@ - #address-cells = <2>; - #size-cells = <2>; - ranges; -+ -+ /* 64 KiB reserved for ramoops/pstore */ -+ ramoops@42ff0000 { -+ compatible = "ramoops"; -+ reg = <0 0x42ff0000 0 0x10000>; -+ record-size = <0x1000>; -+ }; -+ - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ - secmon_reserved: secmon@43000000 { - reg = <0 0x43000000 0 0x30000>; diff --git a/6.1/target/linux/mediatek/patches-6.1/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch b/6.1/target/linux/mediatek/patches-6.1/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch deleted file mode 100644 index 7126da78..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/195-dts-mt7986a-bpi-r3-leds-port-names-and-wifi-eeprom.patch +++ /dev/null @@ -1,196 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts -@@ -23,6 +23,10 @@ - serial0 = &uart0; - ethernet0 = &gmac0; - ethernet1 = &gmac1; -+ led-boot = &green_led; -+ led-failsafe = &green_led; -+ led-running = &green_led; -+ led-upgrade = &blue_led; - }; - - chosen { -@@ -417,27 +421,27 @@ - - port@1 { - reg = <1>; -- label = "lan0"; -+ label = "lan1"; - }; - - port@2 { - reg = <2>; -- label = "lan1"; -+ label = "lan2"; - }; - - port@3 { - reg = <3>; -- label = "lan2"; -+ label = "lan3"; - }; - - port@4 { - reg = <4>; -- label = "lan3"; -+ label = "lan4"; - }; - - port5: port@5 { - reg = <5>; -- label = "lan4"; -+ label = "sfp2"; - phy-mode = "2500base-x"; - sfp = <&sfp2>; - managed = "in-band-status"; -@@ -488,9 +492,137 @@ - - &wifi { - status = "okay"; -- pinctrl-names = "default", "dbdc"; -+ pinctrl-names = "default"; - pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>; -- pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>; -+ -+ mediatek,eeprom-data = <0x86790900 0x000c4326 0x60000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 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0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>; - - led { - led-active-low; ---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso -+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso -@@ -55,6 +55,7 @@ - partition@c00000 { - label = "fit"; - reg = <0xc00000 0x1400000>; -+ compatible = "denx,fit"; - }; - }; - }; diff --git a/6.1/target/linux/mediatek/patches-6.1/200-phy-phy-mtk-tphy-Add-hifsys-support.patch b/6.1/target/linux/mediatek/patches-6.1/200-phy-phy-mtk-tphy-Add-hifsys-support.patch deleted file mode 100644 index 6347533a..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/200-phy-phy-mtk-tphy-Add-hifsys-support.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 28f9a5e2a3f5441ab5594669ed82da11e32277a9 Mon Sep 17 00:00:00 2001 -From: Kristian Evensen -Date: Mon, 30 Apr 2018 14:38:01 +0200 -Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support - ---- - drivers/phy/mediatek/phy-mtk-tphy.c | 20 ++++++++++++++++++++ - 1 file changed, 20 insertions(+) - ---- a/drivers/phy/mediatek/phy-mtk-tphy.c -+++ b/drivers/phy/mediatek/phy-mtk-tphy.c -@@ -17,6 +17,8 @@ - #include - #include - #include -+#include -+#include - - #include "phy-mtk-io.h" - -@@ -264,6 +266,9 @@ - - #define TPHY_CLKS_CNT 2 - -+#define HIF_SYSCFG1 0x14 -+#define HIF_SYSCFG1_PHY2_MASK (0x3 << 20) -+ - enum mtk_phy_version { - MTK_PHY_V1 = 1, - MTK_PHY_V2, -@@ -331,6 +336,7 @@ struct mtk_tphy { - void __iomem *sif_base; /* only shared sif */ - const struct mtk_phy_pdata *pdata; - struct mtk_phy_instance **phys; -+ struct regmap *hif; - int nphys; - int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */ - int src_coef; /* coefficient for slew rate calibrate */ -@@ -596,6 +602,10 @@ static void pcie_phy_instance_init(struc - if (tphy->pdata->version != MTK_PHY_V1) - return; - -+ if (tphy->hif) -+ regmap_update_bits(tphy->hif, HIF_SYSCFG1, -+ HIF_SYSCFG1_PHY2_MASK, 0); -+ - mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG0, - P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H, - FIELD_PREP(P3A_RG_XTAL_EXT_PE1H, 0x2) | -@@ -1241,6 +1251,16 @@ static int mtk_tphy_probe(struct platfor - &tphy->src_coef); - } - -+ if (of_find_property(np, "mediatek,phy-switch", NULL)) { -+ tphy->hif = syscon_regmap_lookup_by_phandle(np, -+ "mediatek,phy-switch"); -+ if (IS_ERR(tphy->hif)) { -+ dev_err(&pdev->dev, -+ "missing \"mediatek,phy-switch\" phandle\n"); -+ return PTR_ERR(tphy->hif); -+ } -+ } -+ - port = 0; - for_each_child_of_node(np, child_np) { - struct mtk_phy_instance *instance; diff --git a/6.1/target/linux/mediatek/patches-6.1/210-v6.2-pinctrl-mt7986-allow-configuring-uart-rx-tx-and-rts-.patch b/6.1/target/linux/mediatek/patches-6.1/210-v6.2-pinctrl-mt7986-allow-configuring-uart-rx-tx-and-rts-.patch deleted file mode 100644 index 3e16a533..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/210-v6.2-pinctrl-mt7986-allow-configuring-uart-rx-tx-and-rts-.patch +++ /dev/null @@ -1,88 +0,0 @@ -From f76e8bc416bebb0f7b9f57b1247eae945421c0b9 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Sat, 8 Oct 2022 18:48:06 +0200 -Subject: [PATCH 1/2] pinctrl: mt7986: allow configuring uart rx/tx and rts/cts - separately - -Some mt7986 boards use uart rts/cts pins as gpio, -This patch allows to change rts/cts to gpio mode, but keep -rx/tx as UART function. - -Signed-off-by: Frank Wunderlich -Signed-off-by: Sam Shih -Link: https://lore.kernel.org/r/20221008164807.113590-1-linux@fw-web.de -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/pinctrl-mt7986.c | 32 ++++++++++++++++++----- - 1 file changed, 25 insertions(+), 7 deletions(-) - ---- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c -@@ -675,11 +675,17 @@ static int mt7986_uart1_1_funcs[] = { 4, - static int mt7986_spi1_2_pins[] = { 29, 30, 31, 32, }; - static int mt7986_spi1_2_funcs[] = { 1, 1, 1, 1, }; - --static int mt7986_uart1_2_pins[] = { 29, 30, 31, 32, }; --static int mt7986_uart1_2_funcs[] = { 3, 3, 3, 3, }; -+static int mt7986_uart1_2_rx_tx_pins[] = { 29, 30, }; -+static int mt7986_uart1_2_rx_tx_funcs[] = { 3, 3, }; - --static int mt7986_uart2_0_pins[] = { 29, 30, 31, 32, }; --static int mt7986_uart2_0_funcs[] = { 4, 4, 4, 4, }; -+static int mt7986_uart1_2_cts_rts_pins[] = { 31, 32, }; -+static int mt7986_uart1_2_cts_rts_funcs[] = { 3, 3, }; -+ -+static int mt7986_uart2_0_rx_tx_pins[] = { 29, 30, }; -+static int mt7986_uart2_0_rx_tx_funcs[] = { 4, 4, }; -+ -+static int mt7986_uart2_0_cts_rts_pins[] = { 31, 32, }; -+static int mt7986_uart2_0_cts_rts_funcs[] = { 4, 4, }; - - static int mt7986_spi0_pins[] = { 33, 34, 35, 36, }; - static int mt7986_spi0_funcs[] = { 1, 1, 1, 1, }; -@@ -708,6 +714,12 @@ static int mt7986_pcie_reset_funcs[] = { - static int mt7986_uart1_pins[] = { 42, 43, 44, 45, }; - static int mt7986_uart1_funcs[] = { 1, 1, 1, 1, }; - -+static int mt7986_uart1_rx_tx_pins[] = { 42, 43, }; -+static int mt7986_uart1_rx_tx_funcs[] = { 1, 1, }; -+ -+static int mt7986_uart1_cts_rts_pins[] = { 44, 45, }; -+static int mt7986_uart1_cts_rts_funcs[] = { 1, 1, }; -+ - static int mt7986_uart2_pins[] = { 46, 47, 48, 49, }; - static int mt7986_uart2_funcs[] = { 1, 1, 1, 1, }; - -@@ -749,6 +761,8 @@ static const struct group_desc mt7986_gr - PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led), - PINCTRL_PIN_GROUP("i2c", mt7986_i2c), - PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0), -+ PINCTRL_PIN_GROUP("uart1_rx_tx", mt7986_uart1_rx_tx), -+ PINCTRL_PIN_GROUP("uart1_cts_rts", mt7986_uart1_cts_rts), - PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk), - PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake), - PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0), -@@ -760,8 +774,10 @@ static const struct group_desc mt7986_gr - PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1), - PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1), - PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2), -- PINCTRL_PIN_GROUP("uart1_2", mt7986_uart1_2), -- PINCTRL_PIN_GROUP("uart2_0", mt7986_uart2_0), -+ PINCTRL_PIN_GROUP("uart1_2_rx_tx", mt7986_uart1_2_rx_tx), -+ PINCTRL_PIN_GROUP("uart1_2_cts_rts", mt7986_uart1_2_cts_rts), -+ PINCTRL_PIN_GROUP("uart2_0_rx_tx", mt7986_uart2_0_rx_tx), -+ PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7986_uart2_0_cts_rts), - PINCTRL_PIN_GROUP("spi0", mt7986_spi0), - PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold), - PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1), -@@ -800,7 +816,9 @@ static const char *mt7986_pwm_groups[] = - static const char *mt7986_spi_groups[] = { - "spi0", "spi0_wp_hold", "spi1_0", "spi1_1", "spi1_2", "spi1_3", }; - static const char *mt7986_uart_groups[] = { -- "uart1_0", "uart1_1", "uart1_2", "uart1_3_rx_tx", "uart1_3_cts_rts", -+ "uart1_0", "uart1_1", "uart1_rx_tx", "uart1_cts_rts", -+ "uart1_2_rx_tx", "uart1_2_cts_rts", -+ "uart1_3_rx_tx", "uart1_3_cts_rts", "uart2_0_rx_tx", "uart2_0_cts_rts", - "uart2_0", "uart2_1", "uart0", "uart1", "uart2", - }; - static const char *mt7986_wdt_groups[] = { "watchdog", }; diff --git a/6.1/target/linux/mediatek/patches-6.1/211-v6.2-pinctrl-mediatek-add-pull_type-attribute-for-mediate.patch b/6.1/target/linux/mediatek/patches-6.1/211-v6.2-pinctrl-mediatek-add-pull_type-attribute-for-mediate.patch deleted file mode 100644 index 47ded1ae..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/211-v6.2-pinctrl-mediatek-add-pull_type-attribute-for-mediate.patch +++ /dev/null @@ -1,100 +0,0 @@ -From 822d774abbcc66b811e28c68b59b40b964ba5b46 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Sun, 6 Nov 2022 09:01:13 +0100 -Subject: [PATCH 2/2] pinctrl: mediatek: add pull_type attribute for mediatek - MT7986 SoC - -Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature") -add SoC specify 'pull_type' attribute for bias configuration. - -This patch add pull_type attribute to pinctrl-mt7986.c, and make -bias_set_combo and bias_get_combo available to mediatek MT7986 SoC. - -Signed-off-by: Sam Shih -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20221106080114.7426-7-linux@fw-web.de -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/pinctrl-mt7986.c | 56 +++++++++++++++++++++++ - 1 file changed, 56 insertions(+) - ---- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c -@@ -407,6 +407,60 @@ static const struct mtk_pin_field_calc m - PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1), - }; - -+static const unsigned int mt7986_pull_type[] = { -+ MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/ -+ MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/ -+ MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/ -+ MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/ -+ MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/ -+ MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/ -+ MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/ -+ MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ -+ MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/ -+ MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/ -+ MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/ -+ MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ -+ MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ -+ MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ -+ MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ -+ MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/ -+ MTK_PULL_PU_PD_TYPE,/*100*/ -+}; -+ - static const struct mtk_pin_reg_calc mt7986_reg_cals[] = { - [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range), - [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range), -@@ -868,6 +922,7 @@ static struct mtk_pin_soc mt7986a_data = - .ies_present = false, - .base_names = mt7986_pinctrl_register_base_names, - .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), -+ .pull_type = mt7986_pull_type, - .bias_set_combo = mtk_pinconf_bias_set_combo, - .bias_get_combo = mtk_pinconf_bias_get_combo, - .drive_set = mtk_pinconf_drive_set_rev1, -@@ -889,6 +944,7 @@ static struct mtk_pin_soc mt7986b_data = - .ies_present = false, - .base_names = mt7986_pinctrl_register_base_names, - .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), -+ .pull_type = mt7986_pull_type, - .bias_set_combo = mtk_pinconf_bias_set_combo, - .bias_get_combo = mtk_pinconf_bias_get_combo, - .drive_set = mtk_pinconf_drive_set_rev1, diff --git a/6.1/target/linux/mediatek/patches-6.1/215-v6.3-pinctrl-add-mt7981-pinctrl-driver.patch b/6.1/target/linux/mediatek/patches-6.1/215-v6.3-pinctrl-add-mt7981-pinctrl-driver.patch deleted file mode 100644 index 46dfa24b..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/215-v6.3-pinctrl-add-mt7981-pinctrl-driver.patch +++ /dev/null @@ -1,1094 +0,0 @@ -From 6c83b2d94fcca735cf7d8aa7a55a4957eb404a9d Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Thu, 26 Jan 2023 00:34:56 +0000 -Subject: [PATCH] pinctrl: add mt7981 pinctrl driver - -Add pinctrl driver for the MediaTek MT7981 SoC, based on the driver -which can also be found the SDK. - -Signed-off-by: Daniel Golle -Reviewed-by: Rob Herring -Link: https://lore.kernel.org/r/ef5112946d16cacc67e65e439ba7b52a9950c1bb.1674693008.git.daniel@makrotopia.org -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/Kconfig | 5 + - drivers/pinctrl/mediatek/Makefile | 1 + - drivers/pinctrl/mediatek/pinctrl-mt7981.c | 1048 +++++++++++++++++++++ - 3 files changed, 1054 insertions(+) - create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7981.c - ---- a/drivers/pinctrl/mediatek/Kconfig -+++ b/drivers/pinctrl/mediatek/Kconfig -@@ -127,6 +127,11 @@ config PINCTRL_MT7622 - default ARM64 && ARCH_MEDIATEK - select PINCTRL_MTK_MOORE - -+config PINCTRL_MT7981 -+ bool "Mediatek MT7981 pin control" -+ depends on OF -+ select PINCTRL_MTK_MOORE -+ - config PINCTRL_MT7986 - bool "Mediatek MT7986 pin control" - depends on OF ---- a/drivers/pinctrl/mediatek/Makefile -+++ b/drivers/pinctrl/mediatek/Makefile -@@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_MT6797) += pinctrl- - obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o - obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o - obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o -+obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o - obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o - obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o - obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o ---- /dev/null -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c -@@ -0,0 +1,1048 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * The MT7981 driver based on Linux generic pinctrl binding. -+ * -+ * Copyright (C) 2020 MediaTek Inc. -+ * Author: Sam Shih -+ */ -+ -+#include "pinctrl-moore.h" -+ -+#define MT7981_PIN(_number, _name) \ -+ MTK_PIN(_number, _name, 0, _number, DRV_GRP4) -+ -+#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \ -+ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ -+ _x_bits, 32, 0) -+ -+#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \ -+ PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ -+ _x_bits, 32, 1) -+ -+static const struct mtk_pin_field_calc mt7981_pin_mode_range[] = { -+ PIN_FIELD(0, 56, 0x300, 0x10, 0, 4), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_dir_range[] = { -+ PIN_FIELD(0, 56, 0x0, 0x10, 0, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_di_range[] = { -+ PIN_FIELD(0, 56, 0x200, 0x10, 0, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_do_range[] = { -+ PIN_FIELD(0, 56, 0x100, 0x10, 0, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_ies_range[] = { -+ PIN_FIELD_BASE(0, 0, 1, 0x10, 0x10, 1, 1), -+ PIN_FIELD_BASE(1, 1, 1, 0x10, 0x10, 0, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1), -+ PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, 4, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(5, 5, 4, 0x20, 0x10, 1, 1), -+ PIN_FIELD_BASE(6, 6, 4, 0x20, 0x10, 3, 1), -+ PIN_FIELD_BASE(7, 7, 4, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(8, 8, 4, 0x20, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(9, 9, 5, 0x20, 0x10, 9, 1), -+ PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1), -+ PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1), -+ PIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1), -+ PIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1), -+ -+ PIN_FIELD_BASE(14, 14, 4, 0x20, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(15, 15, 2, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(16, 16, 2, 0x20, 0x10, 1, 1), -+ PIN_FIELD_BASE(17, 17, 2, 0x20, 0x10, 5, 1), -+ PIN_FIELD_BASE(18, 18, 2, 0x20, 0x10, 4, 1), -+ PIN_FIELD_BASE(19, 19, 2, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, 2, 0x20, 0x10, 3, 1), -+ PIN_FIELD_BASE(21, 21, 2, 0x20, 0x10, 6, 1), -+ PIN_FIELD_BASE(22, 22, 2, 0x20, 0x10, 7, 1), -+ PIN_FIELD_BASE(23, 23, 2, 0x20, 0x10, 10, 1), -+ PIN_FIELD_BASE(24, 24, 2, 0x20, 0x10, 9, 1), -+ PIN_FIELD_BASE(25, 25, 2, 0x20, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(26, 26, 5, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(27, 27, 5, 0x20, 0x10, 4, 1), -+ PIN_FIELD_BASE(28, 28, 5, 0x20, 0x10, 3, 1), -+ PIN_FIELD_BASE(29, 29, 5, 0x20, 0x10, 1, 1), -+ PIN_FIELD_BASE(30, 30, 5, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(31, 31, 5, 0x20, 0x10, 5, 1), -+ -+ PIN_FIELD_BASE(32, 32, 1, 0x10, 0x10, 2, 1), -+ PIN_FIELD_BASE(33, 33, 1, 0x10, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(34, 34, 4, 0x20, 0x10, 5, 1), -+ PIN_FIELD_BASE(35, 35, 4, 0x20, 0x10, 7, 1), -+ -+ PIN_FIELD_BASE(36, 36, 3, 0x10, 0x10, 2, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0x10, 0x10, 3, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 0, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 1, 1), -+ -+ PIN_FIELD_BASE(40, 40, 7, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(41, 41, 7, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(42, 42, 7, 0x30, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, 7, 0x30, 0x10, 7, 1), -+ PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1), -+ PIN_FIELD_BASE(45, 45, 7, 0x30, 0x10, 3, 1), -+ PIN_FIELD_BASE(46, 46, 7, 0x30, 0x10, 4, 1), -+ PIN_FIELD_BASE(47, 47, 7, 0x30, 0x10, 5, 1), -+ PIN_FIELD_BASE(48, 48, 7, 0x30, 0x10, 6, 1), -+ PIN_FIELD_BASE(49, 49, 7, 0x30, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(50, 50, 6, 0x10, 0x10, 0, 1), -+ PIN_FIELD_BASE(51, 51, 6, 0x10, 0x10, 2, 1), -+ PIN_FIELD_BASE(52, 52, 6, 0x10, 0x10, 3, 1), -+ PIN_FIELD_BASE(53, 53, 6, 0x10, 0x10, 4, 1), -+ PIN_FIELD_BASE(54, 54, 6, 0x10, 0x10, 5, 1), -+ PIN_FIELD_BASE(55, 55, 6, 0x10, 0x10, 6, 1), -+ PIN_FIELD_BASE(56, 56, 6, 0x10, 0x10, 1, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_smt_range[] = { -+ PIN_FIELD_BASE(0, 0, 1, 0x60, 0x10, 1, 1), -+ PIN_FIELD_BASE(1, 1, 1, 0x60, 0x10, 0, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0x90, 0x10, 6, 1), -+ PIN_FIELD_BASE(3, 3, 4, 0x80, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, 4, 0x80, 0x10, 2, 1), -+ PIN_FIELD_BASE(5, 5, 4, 0x80, 0x10, 1, 1), -+ PIN_FIELD_BASE(6, 6, 4, 0x80, 0x10, 3, 1), -+ PIN_FIELD_BASE(7, 7, 4, 0x80, 0x10, 0, 1), -+ PIN_FIELD_BASE(8, 8, 4, 0x80, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(9, 9, 5, 0x90, 0x10, 9, 1), -+ PIN_FIELD_BASE(10, 10, 5, 0x90, 0x10, 8, 1), -+ PIN_FIELD_BASE(11, 11, 5, 0x90, 0x10, 10, 1), -+ PIN_FIELD_BASE(12, 12, 5, 0x90, 0x10, 7, 1), -+ PIN_FIELD_BASE(13, 13, 5, 0x90, 0x10, 11, 1), -+ -+ PIN_FIELD_BASE(14, 14, 4, 0x80, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(15, 15, 2, 0x90, 0x10, 0, 1), -+ PIN_FIELD_BASE(16, 16, 2, 0x90, 0x10, 1, 1), -+ PIN_FIELD_BASE(17, 17, 2, 0x90, 0x10, 5, 1), -+ PIN_FIELD_BASE(18, 18, 2, 0x90, 0x10, 4, 1), -+ PIN_FIELD_BASE(19, 19, 2, 0x90, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1), -+ PIN_FIELD_BASE(21, 21, 2, 0x90, 0x10, 6, 1), -+ PIN_FIELD_BASE(22, 22, 2, 0x90, 0x10, 7, 1), -+ PIN_FIELD_BASE(23, 23, 2, 0x90, 0x10, 10, 1), -+ PIN_FIELD_BASE(24, 24, 2, 0x90, 0x10, 9, 1), -+ PIN_FIELD_BASE(25, 25, 2, 0x90, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(26, 26, 5, 0x90, 0x10, 0, 1), -+ PIN_FIELD_BASE(27, 27, 5, 0x90, 0x10, 4, 1), -+ PIN_FIELD_BASE(28, 28, 5, 0x90, 0x10, 3, 1), -+ PIN_FIELD_BASE(29, 29, 5, 0x90, 0x10, 1, 1), -+ PIN_FIELD_BASE(30, 30, 5, 0x90, 0x10, 2, 1), -+ PIN_FIELD_BASE(31, 31, 5, 0x90, 0x10, 5, 1), -+ -+ PIN_FIELD_BASE(32, 32, 1, 0x60, 0x10, 2, 1), -+ PIN_FIELD_BASE(33, 33, 1, 0x60, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(34, 34, 4, 0x80, 0x10, 5, 1), -+ PIN_FIELD_BASE(35, 35, 4, 0x80, 0x10, 7, 1), -+ -+ PIN_FIELD_BASE(36, 36, 3, 0x60, 0x10, 2, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 3, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0x60, 0x10, 0, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0x60, 0x10, 1, 1), -+ -+ PIN_FIELD_BASE(40, 40, 7, 0x70, 0x10, 1, 1), -+ PIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1), -+ PIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1), -+ PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1), -+ PIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1), -+ PIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1), -+ PIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1), -+ PIN_FIELD_BASE(48, 48, 7, 0x70, 0x10, 6, 1), -+ PIN_FIELD_BASE(49, 49, 7, 0x70, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(50, 50, 6, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(51, 51, 6, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(52, 52, 6, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(53, 53, 6, 0x50, 0x10, 4, 1), -+ PIN_FIELD_BASE(54, 54, 6, 0x50, 0x10, 5, 1), -+ PIN_FIELD_BASE(55, 55, 6, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(56, 56, 6, 0x50, 0x10, 1, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_pu_range[] = { -+ PIN_FIELD_BASE(40, 40, 7, 0x50, 0x10, 1, 1), -+ PIN_FIELD_BASE(41, 41, 7, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(42, 42, 7, 0x50, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, 7, 0x50, 0x10, 7, 1), -+ PIN_FIELD_BASE(44, 44, 7, 0x50, 0x10, 8, 1), -+ PIN_FIELD_BASE(45, 45, 7, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(46, 46, 7, 0x50, 0x10, 4, 1), -+ PIN_FIELD_BASE(47, 47, 7, 0x50, 0x10, 5, 1), -+ PIN_FIELD_BASE(48, 48, 7, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(49, 49, 7, 0x50, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(50, 50, 6, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(51, 51, 6, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(52, 52, 6, 0x30, 0x10, 3, 1), -+ PIN_FIELD_BASE(53, 53, 6, 0x30, 0x10, 4, 1), -+ PIN_FIELD_BASE(54, 54, 6, 0x30, 0x10, 5, 1), -+ PIN_FIELD_BASE(55, 55, 6, 0x30, 0x10, 6, 1), -+ PIN_FIELD_BASE(56, 56, 6, 0x30, 0x10, 1, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_pd_range[] = { -+ PIN_FIELD_BASE(40, 40, 7, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(41, 41, 7, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(42, 42, 7, 0x40, 0x10, 9, 1), -+ PIN_FIELD_BASE(43, 43, 7, 0x40, 0x10, 7, 1), -+ PIN_FIELD_BASE(44, 44, 7, 0x40, 0x10, 8, 1), -+ PIN_FIELD_BASE(45, 45, 7, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(46, 46, 7, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(47, 47, 7, 0x40, 0x10, 5, 1), -+ PIN_FIELD_BASE(48, 48, 7, 0x40, 0x10, 6, 1), -+ PIN_FIELD_BASE(49, 49, 7, 0x40, 0x10, 2, 1), -+ -+ PIN_FIELD_BASE(50, 50, 6, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(51, 51, 6, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(52, 52, 6, 0x20, 0x10, 3, 1), -+ PIN_FIELD_BASE(53, 53, 6, 0x20, 0x10, 4, 1), -+ PIN_FIELD_BASE(54, 54, 6, 0x20, 0x10, 5, 1), -+ PIN_FIELD_BASE(55, 55, 6, 0x20, 0x10, 6, 1), -+ PIN_FIELD_BASE(56, 56, 6, 0x20, 0x10, 1, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = { -+ PIN_FIELD_BASE(0, 0, 1, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(1, 1, 1, 0x00, 0x10, 0, 3), -+ -+ PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3), -+ -+ PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1), -+ PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1), -+ PIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 12, 3), -+ -+ PIN_FIELD_BASE(9, 9, 5, 0x00, 0x10, 27, 3), -+ PIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3), -+ PIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3), -+ PIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3), -+ -+ PIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3), -+ -+ PIN_FIELD_BASE(15, 15, 2, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(16, 16, 2, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(17, 17, 2, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(18, 18, 2, 0x00, 0x10, 12, 3), -+ PIN_FIELD_BASE(19, 19, 2, 0x00, 0x10, 6, 3), -+ PIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3), -+ PIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3), -+ PIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3), -+ PIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3), -+ -+ PIN_FIELD_BASE(26, 26, 5, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(27, 27, 5, 0x00, 0x10, 12, 3), -+ PIN_FIELD_BASE(28, 28, 5, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(29, 29, 5, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(30, 30, 5, 0x00, 0x10, 6, 3), -+ PIN_FIELD_BASE(31, 31, 5, 0x00, 0x10, 15, 3), -+ -+ PIN_FIELD_BASE(32, 32, 1, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(33, 33, 1, 0x00, 0x10, 12, 3), -+ -+ PIN_FIELD_BASE(34, 34, 4, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(35, 35, 4, 0x00, 0x10, 21, 3), -+ -+ PIN_FIELD_BASE(36, 36, 3, 0x00, 0x10, 6, 3), -+ PIN_FIELD_BASE(37, 37, 3, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(38, 38, 3, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(39, 39, 3, 0x00, 0x10, 3, 3), -+ -+ PIN_FIELD_BASE(40, 40, 7, 0x00, 0x10, 3, 3), -+ PIN_FIELD_BASE(41, 41, 7, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(42, 42, 7, 0x00, 0x10, 27, 3), -+ PIN_FIELD_BASE(43, 43, 7, 0x00, 0x10, 21, 3), -+ PIN_FIELD_BASE(44, 44, 7, 0x00, 0x10, 24, 3), -+ PIN_FIELD_BASE(45, 45, 7, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(46, 46, 7, 0x00, 0x10, 12, 3), -+ PIN_FIELD_BASE(47, 47, 7, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(48, 48, 7, 0x00, 0x10, 18, 3), -+ PIN_FIELD_BASE(49, 49, 7, 0x00, 0x10, 6, 3), -+ -+ PIN_FIELD_BASE(50, 50, 6, 0x00, 0x10, 0, 3), -+ PIN_FIELD_BASE(51, 51, 6, 0x00, 0x10, 6, 3), -+ PIN_FIELD_BASE(52, 52, 6, 0x00, 0x10, 9, 3), -+ PIN_FIELD_BASE(53, 53, 6, 0x00, 0x10, 12, 3), -+ PIN_FIELD_BASE(54, 54, 6, 0x00, 0x10, 15, 3), -+ PIN_FIELD_BASE(55, 55, 6, 0x00, 0x10, 18, 3), -+ PIN_FIELD_BASE(56, 56, 6, 0x00, 0x10, 3, 3), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_pupd_range[] = { -+ PIN_FIELD_BASE(0, 0, 1, 0x20, 0x10, 1, 1), -+ PIN_FIELD_BASE(1, 1, 1, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 6, 1), -+ PIN_FIELD_BASE(3, 3, 4, 0x30, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, 4, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(5, 5, 4, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(6, 6, 4, 0x30, 0x10, 3, 1), -+ PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(9, 9, 5, 0x30, 0x10, 9, 1), -+ PIN_FIELD_BASE(10, 10, 5, 0x30, 0x10, 8, 1), -+ PIN_FIELD_BASE(11, 11, 5, 0x30, 0x10, 10, 1), -+ PIN_FIELD_BASE(12, 12, 5, 0x30, 0x10, 7, 1), -+ PIN_FIELD_BASE(13, 13, 5, 0x30, 0x10, 11, 1), -+ -+ PIN_FIELD_BASE(14, 14, 4, 0x30, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(15, 15, 2, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(16, 16, 2, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1), -+ PIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1), -+ PIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1), -+ PIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1), -+ PIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1), -+ PIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1), -+ PIN_FIELD_BASE(24, 24, 2, 0x30, 0x10, 9, 1), -+ PIN_FIELD_BASE(25, 25, 2, 0x30, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(26, 26, 5, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(27, 27, 5, 0x30, 0x10, 4, 1), -+ PIN_FIELD_BASE(28, 28, 5, 0x30, 0x10, 3, 1), -+ PIN_FIELD_BASE(29, 29, 5, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(30, 30, 5, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(31, 31, 5, 0x30, 0x10, 5, 1), -+ -+ PIN_FIELD_BASE(32, 32, 1, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(33, 33, 1, 0x20, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(34, 34, 4, 0x30, 0x10, 5, 1), -+ PIN_FIELD_BASE(35, 35, 4, 0x30, 0x10, 7, 1), -+ -+ PIN_FIELD_BASE(36, 36, 3, 0x20, 0x10, 2, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0x20, 0x10, 3, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0x20, 0x10, 0, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0x20, 0x10, 1, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_r0_range[] = { -+ PIN_FIELD_BASE(0, 0, 1, 0x30, 0x10, 1, 1), -+ PIN_FIELD_BASE(1, 1, 1, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0x40, 0x10, 6, 1), -+ PIN_FIELD_BASE(3, 3, 4, 0x40, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, 4, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(5, 5, 4, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(6, 6, 4, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(9, 9, 5, 0x40, 0x10, 9, 1), -+ PIN_FIELD_BASE(10, 10, 5, 0x40, 0x10, 8, 1), -+ PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1), -+ PIN_FIELD_BASE(12, 12, 5, 0x40, 0x10, 7, 1), -+ PIN_FIELD_BASE(13, 13, 5, 0x40, 0x10, 11, 1), -+ -+ PIN_FIELD_BASE(14, 14, 4, 0x40, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(15, 15, 2, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(16, 16, 2, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(17, 17, 2, 0x40, 0x10, 5, 1), -+ PIN_FIELD_BASE(18, 18, 2, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(19, 19, 2, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, 2, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(21, 21, 2, 0x40, 0x10, 6, 1), -+ PIN_FIELD_BASE(22, 22, 2, 0x40, 0x10, 7, 1), -+ PIN_FIELD_BASE(23, 23, 2, 0x40, 0x10, 10, 1), -+ PIN_FIELD_BASE(24, 24, 2, 0x40, 0x10, 9, 1), -+ PIN_FIELD_BASE(25, 25, 2, 0x40, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(26, 26, 5, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(27, 27, 5, 0x40, 0x10, 4, 1), -+ PIN_FIELD_BASE(28, 28, 5, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(29, 29, 5, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(30, 30, 5, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(31, 31, 5, 0x40, 0x10, 5, 1), -+ -+ PIN_FIELD_BASE(32, 32, 1, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(33, 33, 1, 0x30, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(34, 34, 4, 0x40, 0x10, 5, 1), -+ PIN_FIELD_BASE(35, 35, 4, 0x40, 0x10, 7, 1), -+ -+ PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 2, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 3, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0x30, 0x10, 0, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0x30, 0x10, 1, 1), -+}; -+ -+static const struct mtk_pin_field_calc mt7981_pin_r1_range[] = { -+ PIN_FIELD_BASE(0, 0, 1, 0x40, 0x10, 1, 1), -+ PIN_FIELD_BASE(1, 1, 1, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(3, 3, 4, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(4, 4, 4, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(5, 5, 4, 0x50, 0x10, 1, 1), -+ PIN_FIELD_BASE(6, 6, 4, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(7, 7, 4, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(8, 8, 4, 0x50, 0x10, 4, 1), -+ -+ PIN_FIELD_BASE(9, 9, 5, 0x50, 0x10, 9, 1), -+ PIN_FIELD_BASE(10, 10, 5, 0x50, 0x10, 8, 1), -+ PIN_FIELD_BASE(11, 11, 5, 0x50, 0x10, 10, 1), -+ PIN_FIELD_BASE(12, 12, 5, 0x50, 0x10, 7, 1), -+ PIN_FIELD_BASE(13, 13, 5, 0x50, 0x10, 11, 1), -+ -+ PIN_FIELD_BASE(14, 14, 4, 0x50, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(15, 15, 2, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(16, 16, 2, 0x50, 0x10, 1, 1), -+ PIN_FIELD_BASE(17, 17, 2, 0x50, 0x10, 5, 1), -+ PIN_FIELD_BASE(18, 18, 2, 0x50, 0x10, 4, 1), -+ PIN_FIELD_BASE(19, 19, 2, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(20, 20, 2, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(21, 21, 2, 0x50, 0x10, 6, 1), -+ PIN_FIELD_BASE(22, 22, 2, 0x50, 0x10, 7, 1), -+ PIN_FIELD_BASE(23, 23, 2, 0x50, 0x10, 10, 1), -+ PIN_FIELD_BASE(24, 24, 2, 0x50, 0x10, 9, 1), -+ PIN_FIELD_BASE(25, 25, 2, 0x50, 0x10, 8, 1), -+ -+ PIN_FIELD_BASE(26, 26, 5, 0x50, 0x10, 0, 1), -+ PIN_FIELD_BASE(27, 27, 5, 0x50, 0x10, 4, 1), -+ PIN_FIELD_BASE(28, 28, 5, 0x50, 0x10, 3, 1), -+ PIN_FIELD_BASE(29, 29, 5, 0x50, 0x10, 1, 1), -+ PIN_FIELD_BASE(30, 30, 5, 0x50, 0x10, 2, 1), -+ PIN_FIELD_BASE(31, 31, 5, 0x50, 0x10, 5, 1), -+ -+ PIN_FIELD_BASE(32, 32, 1, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(33, 33, 1, 0x40, 0x10, 3, 1), -+ -+ PIN_FIELD_BASE(34, 34, 4, 0x50, 0x10, 5, 1), -+ PIN_FIELD_BASE(35, 35, 4, 0x50, 0x10, 7, 1), -+ -+ PIN_FIELD_BASE(36, 36, 3, 0x40, 0x10, 2, 1), -+ PIN_FIELD_BASE(37, 37, 3, 0x40, 0x10, 3, 1), -+ PIN_FIELD_BASE(38, 38, 3, 0x40, 0x10, 0, 1), -+ PIN_FIELD_BASE(39, 39, 3, 0x40, 0x10, 1, 1), -+}; -+ -+static const unsigned int mt7981_pull_type[] = { -+ MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ -+ MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/ -+ MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/ -+ MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/ -+ MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/ -+ MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/ -+ MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/ -+ MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/ -+ MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ -+ MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/ -+ MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/ -+ MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/ -+ MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ -+ MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ -+ MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ -+ MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ -+ MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/ -+ MTK_PULL_PU_PD_TYPE,/*100*/ -+}; -+ -+static const struct mtk_pin_reg_calc mt7981_reg_cals[] = { -+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7981_pin_mode_range), -+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7981_pin_dir_range), -+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7981_pin_di_range), -+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7981_pin_do_range), -+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7981_pin_smt_range), -+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7981_pin_ies_range), -+ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7981_pin_pu_range), -+ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7981_pin_pd_range), -+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7981_pin_drv_range), -+ [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7981_pin_pupd_range), -+ [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7981_pin_r0_range), -+ [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7981_pin_r1_range), -+}; -+ -+static const struct mtk_pin_desc mt7981_pins[] = { -+ MT7981_PIN(0, "GPIO_WPS"), -+ MT7981_PIN(1, "GPIO_RESET"), -+ MT7981_PIN(2, "SYS_WATCHDOG"), -+ MT7981_PIN(3, "PCIE_PERESET_N"), -+ MT7981_PIN(4, "JTAG_JTDO"), -+ MT7981_PIN(5, "JTAG_JTDI"), -+ MT7981_PIN(6, "JTAG_JTMS"), -+ MT7981_PIN(7, "JTAG_JTCLK"), -+ MT7981_PIN(8, "JTAG_JTRST_N"), -+ MT7981_PIN(9, "WO_JTAG_JTDO"), -+ MT7981_PIN(10, "WO_JTAG_JTDI"), -+ MT7981_PIN(11, "WO_JTAG_JTMS"), -+ MT7981_PIN(12, "WO_JTAG_JTCLK"), -+ MT7981_PIN(13, "WO_JTAG_JTRST_N"), -+ MT7981_PIN(14, "USB_VBUS"), -+ MT7981_PIN(15, "PWM0"), -+ MT7981_PIN(16, "SPI0_CLK"), -+ MT7981_PIN(17, "SPI0_MOSI"), -+ MT7981_PIN(18, "SPI0_MISO"), -+ MT7981_PIN(19, "SPI0_CS"), -+ MT7981_PIN(20, "SPI0_HOLD"), -+ MT7981_PIN(21, "SPI0_WP"), -+ MT7981_PIN(22, "SPI1_CLK"), -+ MT7981_PIN(23, "SPI1_MOSI"), -+ MT7981_PIN(24, "SPI1_MISO"), -+ MT7981_PIN(25, "SPI1_CS"), -+ MT7981_PIN(26, "SPI2_CLK"), -+ MT7981_PIN(27, "SPI2_MOSI"), -+ MT7981_PIN(28, "SPI2_MISO"), -+ MT7981_PIN(29, "SPI2_CS"), -+ MT7981_PIN(30, "SPI2_HOLD"), -+ MT7981_PIN(31, "SPI2_WP"), -+ MT7981_PIN(32, "UART0_RXD"), -+ MT7981_PIN(33, "UART0_TXD"), -+ MT7981_PIN(34, "PCIE_CLK_REQ"), -+ MT7981_PIN(35, "PCIE_WAKE_N"), -+ MT7981_PIN(36, "SMI_MDC"), -+ MT7981_PIN(37, "SMI_MDIO"), -+ MT7981_PIN(38, "GBE_INT"), -+ MT7981_PIN(39, "GBE_RESET"), -+ MT7981_PIN(40, "WF_DIG_RESETB"), -+ MT7981_PIN(41, "WF_CBA_RESETB"), -+ MT7981_PIN(42, "WF_XO_REQ"), -+ MT7981_PIN(43, "WF_TOP_CLK"), -+ MT7981_PIN(44, "WF_TOP_DATA"), -+ MT7981_PIN(45, "WF_HB1"), -+ MT7981_PIN(46, "WF_HB2"), -+ MT7981_PIN(47, "WF_HB3"), -+ MT7981_PIN(48, "WF_HB4"), -+ MT7981_PIN(49, "WF_HB0"), -+ MT7981_PIN(50, "WF_HB0_B"), -+ MT7981_PIN(51, "WF_HB5"), -+ MT7981_PIN(52, "WF_HB6"), -+ MT7981_PIN(53, "WF_HB7"), -+ MT7981_PIN(54, "WF_HB8"), -+ MT7981_PIN(55, "WF_HB9"), -+ MT7981_PIN(56, "WF_HB10"), -+}; -+ -+/* List all groups consisting of these pins dedicated to the enablement of -+ * certain hardware block and the corresponding mode for all of the pins. -+ * The hardware probably has multiple combinations of these pinouts. -+ */ -+ -+/* WA_AICE */ -+static int mt7981_wa_aice1_pins[] = { 0, 1, }; -+static int mt7981_wa_aice1_funcs[] = { 2, 2, }; -+ -+static int mt7981_wa_aice2_pins[] = { 0, 1, }; -+static int mt7981_wa_aice2_funcs[] = { 3, 3, }; -+ -+static int mt7981_wa_aice3_pins[] = { 28, 29, }; -+static int mt7981_wa_aice3_funcs[] = { 3, 3, }; -+ -+static int mt7981_wm_aice1_pins[] = { 9, 10, }; -+static int mt7981_wm_aice1_funcs[] = { 2, 2, }; -+ -+static int mt7981_wm_aice2_pins[] = { 30, 31, }; -+static int mt7981_wm_aice2_funcs[] = { 5, 5, }; -+ -+/* WM_UART */ -+static int mt7981_wm_uart_0_pins[] = { 0, 1, }; -+static int mt7981_wm_uart_0_funcs[] = { 5, 5, }; -+ -+static int mt7981_wm_uart_1_pins[] = { 20, 21, }; -+static int mt7981_wm_uart_1_funcs[] = { 4, 4, }; -+ -+static int mt7981_wm_uart_2_pins[] = { 30, 31, }; -+static int mt7981_wm_uart_2_funcs[] = { 3, 3, }; -+ -+/* DFD */ -+static int mt7981_dfd_pins[] = { 0, 1, 4, 5, }; -+static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, }; -+ -+/* SYS_WATCHDOG */ -+static int mt7981_watchdog_pins[] = { 2, }; -+static int mt7981_watchdog_funcs[] = { 1, }; -+ -+static int mt7981_watchdog1_pins[] = { 13, }; -+static int mt7981_watchdog1_funcs[] = { 5, }; -+ -+/* PCIE_PERESET_N */ -+static int mt7981_pcie_pereset_pins[] = { 3, }; -+static int mt7981_pcie_pereset_funcs[] = { 1, }; -+ -+/* JTAG */ -+static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, }; -+static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, }; -+ -+/* WM_JTAG */ -+static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, }; -+static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, }; -+ -+static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, }; -+static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; -+ -+/* WO0_JTAG */ -+static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, }; -+static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, }; -+ -+static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, }; -+static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; -+ -+/* UART2 */ -+static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, }; -+static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, }; -+ -+/* GBE_LED0 */ -+static int mt7981_gbe_led0_pins[] = { 8, }; -+static int mt7981_gbe_led0_funcs[] = { 3, }; -+ -+/* PTA_EXT */ -+static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, }; -+static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, }; -+ -+static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, }; -+static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, }; -+ -+/* PWM2 */ -+static int mt7981_pwm2_pins[] = { 7, }; -+static int mt7981_pwm2_funcs[] = { 4, }; -+ -+/* NET_WO0_UART_TXD */ -+static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, }; -+static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, }; -+ -+static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, }; -+static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, }; -+ -+static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, }; -+static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, }; -+ -+/* SPI1 */ -+static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, }; -+static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, }; -+ -+/* I2C */ -+static int mt7981_i2c0_0_pins[] = { 6, 7, }; -+static int mt7981_i2c0_0_funcs[] = { 6, 6, }; -+ -+static int mt7981_i2c0_1_pins[] = { 30, 31, }; -+static int mt7981_i2c0_1_funcs[] = { 4, 4, }; -+ -+static int mt7981_i2c0_2_pins[] = { 36, 37, }; -+static int mt7981_i2c0_2_funcs[] = { 2, 2, }; -+ -+static int mt7981_u2_phy_i2c_pins[] = { 30, 31, }; -+static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, }; -+ -+static int mt7981_u3_phy_i2c_pins[] = { 32, 33, }; -+static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, }; -+ -+static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, }; -+static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, }; -+ -+static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, }; -+static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, }; -+ -+/* DFD_NTRST */ -+static int mt7981_dfd_ntrst_pins[] = { 8, }; -+static int mt7981_dfd_ntrst_funcs[] = { 6, }; -+ -+/* PWM0 */ -+static int mt7981_pwm0_0_pins[] = { 13, }; -+static int mt7981_pwm0_0_funcs[] = { 2, }; -+ -+static int mt7981_pwm0_1_pins[] = { 15, }; -+static int mt7981_pwm0_1_funcs[] = { 1, }; -+ -+/* PWM1 */ -+static int mt7981_pwm1_0_pins[] = { 14, }; -+static int mt7981_pwm1_0_funcs[] = { 2, }; -+ -+static int mt7981_pwm1_1_pins[] = { 15, }; -+static int mt7981_pwm1_1_funcs[] = { 3, }; -+ -+/* GBE_LED1 */ -+static int mt7981_gbe_led1_pins[] = { 13, }; -+static int mt7981_gbe_led1_funcs[] = { 3, }; -+ -+/* PCM */ -+static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 }; -+static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, }; -+ -+/* UDI */ -+static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, }; -+static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, }; -+ -+/* DRV_VBUS */ -+static int mt7981_drv_vbus_pins[] = { 14, }; -+static int mt7981_drv_vbus_funcs[] = { 1, }; -+ -+/* EMMC */ -+static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; -+static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; -+ -+/* SNFI */ -+static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, }; -+static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, }; -+ -+/* SPI0 */ -+static int mt7981_spi0_pins[] = { 16, 17, 18, 19, }; -+static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, }; -+ -+/* SPI0 */ -+static int mt7981_spi0_wp_hold_pins[] = { 20, 21, }; -+static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, }; -+ -+/* SPI1 */ -+static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, }; -+static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, }; -+ -+/* SPI2 */ -+static int mt7981_spi2_pins[] = { 26, 27, 28, 29, }; -+static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, }; -+ -+/* SPI2 */ -+static int mt7981_spi2_wp_hold_pins[] = { 30, 31, }; -+static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, }; -+ -+/* UART1 */ -+static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, }; -+static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, }; -+ -+static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, }; -+static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, }; -+ -+/* UART2 */ -+static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; -+static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; -+ -+/* UART0 */ -+static int mt7981_uart0_pins[] = { 32, 33, }; -+static int mt7981_uart0_funcs[] = { 1, 1, }; -+ -+/* PCIE_CLK_REQ */ -+static int mt7981_pcie_clk_pins[] = { 34, }; -+static int mt7981_pcie_clk_funcs[] = { 2, }; -+ -+/* PCIE_WAKE_N */ -+static int mt7981_pcie_wake_pins[] = { 35, }; -+static int mt7981_pcie_wake_funcs[] = { 2, }; -+ -+/* MDC_MDIO */ -+static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, }; -+static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, }; -+ -+static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, }; -+static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, }; -+ -+/* WF0_MODE1 */ -+static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 }; -+static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; -+ -+/* WF0_MODE3 */ -+static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 }; -+static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 }; -+ -+/* WF2G_LED */ -+static int mt7981_wf2g_led0_pins[] = { 30, }; -+static int mt7981_wf2g_led0_funcs[] = { 2, }; -+ -+static int mt7981_wf2g_led1_pins[] = { 34, }; -+static int mt7981_wf2g_led1_funcs[] = { 1, }; -+ -+/* WF5G_LED */ -+static int mt7981_wf5g_led0_pins[] = { 31, }; -+static int mt7981_wf5g_led0_funcs[] = { 2, }; -+ -+static int mt7981_wf5g_led1_pins[] = { 35, }; -+static int mt7981_wf5g_led1_funcs[] = { 1, }; -+ -+/* MT7531_INT */ -+static int mt7981_mt7531_int_pins[] = { 38, }; -+static int mt7981_mt7531_int_funcs[] = { 1, }; -+ -+/* ANT_SEL */ -+static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 }; -+static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 }; -+ -+static const struct group_desc mt7981_groups[] = { -+ /* @GPIO(0,1): WA_AICE(2) */ -+ PINCTRL_PIN_GROUP("wa_aice1", mt7981_wa_aice1), -+ /* @GPIO(0,1): WA_AICE(3) */ -+ PINCTRL_PIN_GROUP("wa_aice2", mt7981_wa_aice2), -+ /* @GPIO(0,1): WM_UART(5) */ -+ PINCTRL_PIN_GROUP("wm_uart_0", mt7981_wm_uart_0), -+ /* @GPIO(0,1,4,5): DFD(6) */ -+ PINCTRL_PIN_GROUP("dfd", mt7981_dfd), -+ /* @GPIO(2): SYS_WATCHDOG(1) */ -+ PINCTRL_PIN_GROUP("watchdog", mt7981_watchdog), -+ /* @GPIO(3): PCIE_PERESET_N(1) */ -+ PINCTRL_PIN_GROUP("pcie_pereset", mt7981_pcie_pereset), -+ /* @GPIO(4,8) JTAG(1) */ -+ PINCTRL_PIN_GROUP("jtag", mt7981_jtag), -+ /* @GPIO(4,8) WM_JTAG(2) */ -+ PINCTRL_PIN_GROUP("wm_jtag_0", mt7981_wm_jtag_0), -+ /* @GPIO(9,13) WO0_JTAG(1) */ -+ PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0), -+ /* @GPIO(4,7) WM_JTAG(3) */ -+ PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0), -+ /* @GPIO(8) GBE_LED0(3) */ -+ PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0), -+ /* @GPIO(4,6) PTA_EXT(4) */ -+ PINCTRL_PIN_GROUP("pta_ext_0", mt7981_pta_ext_0), -+ /* @GPIO(7) PWM2(4) */ -+ PINCTRL_PIN_GROUP("pwm2", mt7981_pwm2), -+ /* @GPIO(8) NET_WO0_UART_TXD(4) */ -+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7981_net_wo0_uart_txd_0), -+ /* @GPIO(4,7) SPI1(5) */ -+ PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0), -+ /* @GPIO(6,7) I2C(5) */ -+ PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0), -+ /* @GPIO(0,1,4,5): DFD_NTRST(6) */ -+ PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst), -+ /* @GPIO(9,10): WM_AICE(2) */ -+ PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1), -+ /* @GPIO(13): PWM0(2) */ -+ PINCTRL_PIN_GROUP("pwm0_0", mt7981_pwm0_0), -+ /* @GPIO(15): PWM0(1) */ -+ PINCTRL_PIN_GROUP("pwm0_1", mt7981_pwm0_1), -+ /* @GPIO(14): PWM1(2) */ -+ PINCTRL_PIN_GROUP("pwm1_0", mt7981_pwm1_0), -+ /* @GPIO(15): PWM1(3) */ -+ PINCTRL_PIN_GROUP("pwm1_1", mt7981_pwm1_1), -+ /* @GPIO(14) NET_WO0_UART_TXD(3) */ -+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7981_net_wo0_uart_txd_1), -+ /* @GPIO(15) NET_WO0_UART_TXD(4) */ -+ PINCTRL_PIN_GROUP("net_wo0_uart_txd_2", mt7981_net_wo0_uart_txd_2), -+ /* @GPIO(13) GBE_LED0(3) */ -+ PINCTRL_PIN_GROUP("gbe_led1", mt7981_gbe_led1), -+ /* @GPIO(9,13) PCM(4) */ -+ PINCTRL_PIN_GROUP("pcm", mt7981_pcm), -+ /* @GPIO(13): SYS_WATCHDOG1(5) */ -+ PINCTRL_PIN_GROUP("watchdog1", mt7981_watchdog1), -+ /* @GPIO(9,13) UDI(4) */ -+ PINCTRL_PIN_GROUP("udi", mt7981_udi), -+ /* @GPIO(14) DRV_VBUS(1) */ -+ PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus), -+ /* @GPIO(15,25): EMMC(2) */ -+ PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45), -+ /* @GPIO(16,21): SNFI(3) */ -+ PINCTRL_PIN_GROUP("snfi", mt7981_snfi), -+ /* @GPIO(16,19): SPI0(1) */ -+ PINCTRL_PIN_GROUP("spi0", mt7981_spi0), -+ /* @GPIO(20,21): SPI0(1) */ -+ PINCTRL_PIN_GROUP("spi0_wp_hold", mt7981_spi0_wp_hold), -+ /* @GPIO(22,25) SPI1(1) */ -+ PINCTRL_PIN_GROUP("spi1_1", mt7981_spi1_1), -+ /* @GPIO(26,29): SPI2(1) */ -+ PINCTRL_PIN_GROUP("spi2", mt7981_spi2), -+ /* @GPIO(30,31): SPI0(1) */ -+ PINCTRL_PIN_GROUP("spi2_wp_hold", mt7981_spi2_wp_hold), -+ /* @GPIO(16,19): UART1(4) */ -+ PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0), -+ /* @GPIO(26,29): UART1(2) */ -+ PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1), -+ /* @GPIO(22,25): UART1(3) */ -+ PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1), -+ /* @GPIO(22,24) PTA_EXT(4) */ -+ PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1), -+ /* @GPIO(20,21): WM_UART(4) */ -+ PINCTRL_PIN_GROUP("wm_aurt_1", mt7981_wm_uart_1), -+ /* @GPIO(30,31): WM_UART(3) */ -+ PINCTRL_PIN_GROUP("wm_aurt_2", mt7981_wm_uart_2), -+ /* @GPIO(20,24) WM_JTAG(5) */ -+ PINCTRL_PIN_GROUP("wm_jtag_1", mt7981_wm_jtag_1), -+ /* @GPIO(25,29) WO0_JTAG(5) */ -+ PINCTRL_PIN_GROUP("wo0_jtag_1", mt7981_wo0_jtag_1), -+ /* @GPIO(28,29): WA_AICE(3) */ -+ PINCTRL_PIN_GROUP("wa_aice3", mt7981_wa_aice3), -+ /* @GPIO(30,31): WM_AICE(5) */ -+ PINCTRL_PIN_GROUP("wm_aice2", mt7981_wm_aice2), -+ /* @GPIO(30,31): I2C(4) */ -+ PINCTRL_PIN_GROUP("i2c0_1", mt7981_i2c0_1), -+ /* @GPIO(30,31): I2C(6) */ -+ PINCTRL_PIN_GROUP("u2_phy_i2c", mt7981_u2_phy_i2c), -+ /* @GPIO(32,33): I2C(1) */ -+ PINCTRL_PIN_GROUP("uart0", mt7981_uart0), -+ /* @GPIO(32,33): I2C(2) */ -+ PINCTRL_PIN_GROUP("sgmii1_phy_i2c", mt7981_sgmii1_phy_i2c), -+ /* @GPIO(32,33): I2C(3) */ -+ PINCTRL_PIN_GROUP("u3_phy_i2c", mt7981_u3_phy_i2c), -+ /* @GPIO(32,33): I2C(5) */ -+ PINCTRL_PIN_GROUP("sgmii0_phy_i2c", mt7981_sgmii0_phy_i2c), -+ /* @GPIO(34): PCIE_CLK_REQ(2) */ -+ PINCTRL_PIN_GROUP("pcie_clk", mt7981_pcie_clk), -+ /* @GPIO(35): PCIE_WAKE_N(2) */ -+ PINCTRL_PIN_GROUP("pcie_wake", mt7981_pcie_wake), -+ /* @GPIO(36,37): I2C(2) */ -+ PINCTRL_PIN_GROUP("i2c0_2", mt7981_i2c0_2), -+ /* @GPIO(36,37): MDC_MDIO(1) */ -+ PINCTRL_PIN_GROUP("smi_mdc_mdio", mt7981_smi_mdc_mdio), -+ /* @GPIO(36,37): MDC_MDIO(3) */ -+ PINCTRL_PIN_GROUP("gbe_ext_mdc_mdio", mt7981_gbe_ext_mdc_mdio), -+ /* @GPIO(69,85): WF0_MODE1(1) */ -+ PINCTRL_PIN_GROUP("wf0_mode1", mt7981_wf0_mode1), -+ /* @GPIO(74,80): WF0_MODE3(3) */ -+ PINCTRL_PIN_GROUP("wf0_mode3", mt7981_wf0_mode3), -+ /* @GPIO(30): WF2G_LED(2) */ -+ PINCTRL_PIN_GROUP("wf2g_led0", mt7981_wf2g_led0), -+ /* @GPIO(34): WF2G_LED(1) */ -+ PINCTRL_PIN_GROUP("wf2g_led1", mt7981_wf2g_led1), -+ /* @GPIO(31): WF5G_LED(2) */ -+ PINCTRL_PIN_GROUP("wf5g_led0", mt7981_wf5g_led0), -+ /* @GPIO(35): WF5G_LED(1) */ -+ PINCTRL_PIN_GROUP("wf5g_led1", mt7981_wf5g_led1), -+ /* @GPIO(38): MT7531_INT(1) */ -+ PINCTRL_PIN_GROUP("mt7531_int", mt7981_mt7531_int), -+ /* @GPIO(14,15,26,17,18,19,20,21,22,23,24,25,34,35): ANT_SEL(1) */ -+ PINCTRL_PIN_GROUP("ant_sel", mt7981_ant_sel), -+}; -+ -+/* Joint those groups owning the same capability in user point of view which -+ * allows that people tend to use through the device tree. -+ */ -+static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1", -+ "wa_aice3", "wm_aice1_2", }; -+static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0", -+ "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2", -+ "uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", }; -+static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", }; -+static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", }; -+static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", }; -+static const char *mt7981_jtag_groups[] = { "jtag", "wm_jtag_0", "wo0_jtag_0", -+ "wo0_jtag_1", "wm_jtag_1", }; -+static const char *mt7981_led_groups[] = { "gbe_led0", "gbe_led1", "wf2g_led0", -+ "wf2g_led1", "wf5g_led0", "wf5g_led1", }; -+static const char *mt7981_pta_groups[] = { "pta_ext_0", "pta_ext_1", }; -+static const char *mt7981_pwm_groups[] = { "pwm2", "pwm0_0", "pwm0_1", -+ "pwm1_0", "pwm1_1", }; -+static const char *mt7981_spi_groups[] = { "spi1_0", "spi0", "spi0_wp_hold", "spi1_1", "spi2", -+ "spi2_wp_hold", }; -+static const char *mt7981_i2c_groups[] = { "i2c0_0", "i2c0_1", "u2_phy_i2c", -+ "sgmii1_phy_i2c", "u3_phy_i2c", "sgmii0_phy_i2c", "i2c0_2", }; -+static const char *mt7981_pcm_groups[] = { "pcm", }; -+static const char *mt7981_udi_groups[] = { "udi", }; -+static const char *mt7981_usb_groups[] = { "drv_vbus", }; -+static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", }; -+static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio", -+ "wf0_mode1", "wf0_mode3", "mt7531_int", }; -+static const char *mt7981_ant_groups[] = { "ant_sel", }; -+ -+static const struct function_desc mt7981_functions[] = { -+ {"wa_aice", mt7981_wa_aice_groups, ARRAY_SIZE(mt7981_wa_aice_groups)}, -+ {"dfd", mt7981_dfd_groups, ARRAY_SIZE(mt7981_dfd_groups)}, -+ {"jtag", mt7981_jtag_groups, ARRAY_SIZE(mt7981_jtag_groups)}, -+ {"pta", mt7981_pta_groups, ARRAY_SIZE(mt7981_pta_groups)}, -+ {"pcm", mt7981_pcm_groups, ARRAY_SIZE(mt7981_pcm_groups)}, -+ {"udi", mt7981_udi_groups, ARRAY_SIZE(mt7981_udi_groups)}, -+ {"usb", mt7981_usb_groups, ARRAY_SIZE(mt7981_usb_groups)}, -+ {"ant", mt7981_ant_groups, ARRAY_SIZE(mt7981_ant_groups)}, -+ {"eth", mt7981_ethernet_groups, ARRAY_SIZE(mt7981_ethernet_groups)}, -+ {"i2c", mt7981_i2c_groups, ARRAY_SIZE(mt7981_i2c_groups)}, -+ {"led", mt7981_led_groups, ARRAY_SIZE(mt7981_led_groups)}, -+ {"pwm", mt7981_pwm_groups, ARRAY_SIZE(mt7981_pwm_groups)}, -+ {"spi", mt7981_spi_groups, ARRAY_SIZE(mt7981_spi_groups)}, -+ {"uart", mt7981_uart_groups, ARRAY_SIZE(mt7981_uart_groups)}, -+ {"watchdog", mt7981_wdt_groups, ARRAY_SIZE(mt7981_wdt_groups)}, -+ {"flash", mt7981_flash_groups, ARRAY_SIZE(mt7981_flash_groups)}, -+ {"pcie", mt7981_pcie_groups, ARRAY_SIZE(mt7981_pcie_groups)}, -+}; -+ -+static const struct mtk_eint_hw mt7981_eint_hw = { -+ .port_mask = 7, -+ .ports = 7, -+ .ap_num = ARRAY_SIZE(mt7981_pins), -+ .db_cnt = 16, -+}; -+ -+static const char * const mt7981_pinctrl_register_base_names[] = { -+ "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", -+ "iocfg_lb", "iocfg_bl", "iocfg_tm", "iocfg_tl", -+}; -+ -+static struct mtk_pin_soc mt7981_data = { -+ .reg_cal = mt7981_reg_cals, -+ .pins = mt7981_pins, -+ .npins = ARRAY_SIZE(mt7981_pins), -+ .grps = mt7981_groups, -+ .ngrps = ARRAY_SIZE(mt7981_groups), -+ .funcs = mt7981_functions, -+ .nfuncs = ARRAY_SIZE(mt7981_functions), -+ .eint_hw = &mt7981_eint_hw, -+ .gpio_m = 0, -+ .ies_present = false, -+ .base_names = mt7981_pinctrl_register_base_names, -+ .nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names), -+ .pull_type = mt7981_pull_type, -+ .bias_set_combo = mtk_pinconf_bias_set_combo, -+ .bias_get_combo = mtk_pinconf_bias_get_combo, -+ .drive_set = mtk_pinconf_drive_set_rev1, -+ .drive_get = mtk_pinconf_drive_get_rev1, -+ .adv_pull_get = mtk_pinconf_adv_pull_get, -+ .adv_pull_set = mtk_pinconf_adv_pull_set, -+}; -+ -+static const struct of_device_id mt7981_pinctrl_of_match[] = { -+ { .compatible = "mediatek,mt7981-pinctrl", }, -+ {} -+}; -+ -+static int mt7981_pinctrl_probe(struct platform_device *pdev) -+{ -+ return mtk_moore_pinctrl_probe(pdev, &mt7981_data); -+} -+ -+static struct platform_driver mt7981_pinctrl_driver = { -+ .driver = { -+ .name = "mt7981-pinctrl", -+ .of_match_table = mt7981_pinctrl_of_match, -+ }, -+ .probe = mt7981_pinctrl_probe, -+}; -+ -+static int __init mt7981_pinctrl_init(void) -+{ -+ return platform_driver_register(&mt7981_pinctrl_driver); -+} -+arch_initcall(mt7981_pinctrl_init); diff --git a/6.1/target/linux/mediatek/patches-6.1/216-v6.3-pinctrl-mediatek-add-missing-options-to-PINCTRL_MT79.patch b/6.1/target/linux/mediatek/patches-6.1/216-v6.3-pinctrl-mediatek-add-missing-options-to-PINCTRL_MT79.patch deleted file mode 100644 index 995e0dc7..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/216-v6.3-pinctrl-mediatek-add-missing-options-to-PINCTRL_MT79.patch +++ /dev/null @@ -1,30 +0,0 @@ -From c0ad453e94e5c404efbcf668648d07eaa1a71ed7 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= -Date: Sat, 18 Feb 2023 09:51:06 +0300 -Subject: [PATCH] pinctrl: mediatek: add missing options to PINCTRL_MT7981 -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -There are options missing from PINCTRL_MT7981 whilst being on every other -pin controller. Add them. - -Signed-off-by: Arınç ÜNAL -Acked-by: Daniel Golle -Link: https://lore.kernel.org/r/20230218065108.8958-1-arinc.unal@arinc9.com -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/Kconfig | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/pinctrl/mediatek/Kconfig -+++ b/drivers/pinctrl/mediatek/Kconfig -@@ -130,6 +130,8 @@ config PINCTRL_MT7622 - config PINCTRL_MT7981 - bool "Mediatek MT7981 pin control" - depends on OF -+ depends on ARM64 || COMPILE_TEST -+ default ARM64 && ARCH_MEDIATEK - select PINCTRL_MTK_MOORE - - config PINCTRL_MT7986 diff --git a/6.1/target/linux/mediatek/patches-6.1/220-v6.3-clk-mediatek-clk-gate-Propagate-struct-device-with-m.patch b/6.1/target/linux/mediatek/patches-6.1/220-v6.3-clk-mediatek-clk-gate-Propagate-struct-device-with-m.patch deleted file mode 100644 index e3292a06..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/220-v6.3-clk-mediatek-clk-gate-Propagate-struct-device-with-m.patch +++ /dev/null @@ -1,536 +0,0 @@ -From fe5c8d03f3de89ae058e365b783f8c1314f47490 Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Fri, 20 Jan 2023 10:20:33 +0100 -Subject: [PATCH 01/15] clk: mediatek: clk-gate: Propagate struct device with - mtk_clk_register_gates() - -Commit e4c23e19aa2a ("clk: mediatek: Register clock gate with device") -introduces a helper function for the sole purpose of propagating a -struct device pointer to the clk API when registering the mtk-gate -clocks to take advantage of Runtime PM when/where needed and where -a power domain is defined in devicetree. - -Function mtk_clk_register_gates() then becomes a wrapper around the -new mtk_clk_register_gates_with_dev() function that will simply pass -NULL as struct device: this is essential when registering drivers -with CLK_OF_DECLARE instead of as a platform device, as there will -be no struct device to pass... but we can as well simply have only -one function that always takes such pointer as a param and pass NULL -when unavoidable. - -This commit removes the mtk_clk_register_gates() wrapper and renames -mtk_clk_register_gates_with_dev() to the former and all of the calls -to either of the two functions were fixed in all drivers in order to -reflect this change; also, to improve consistency with other kernel -functions, the pointer to struct device was moved as the first param. - -Since a lot of MediaTek clock drivers are actually registering as a -platform device, but were still registering the mtk-gate clocks -without passing any struct device to the clock framework, they've -been changed to pass a valid one now, as to make all those platforms -able to use runtime power management where available. - -While at it, some much needed indentation changes were also done. - -Signed-off-by: AngeloGioacchino Del Regno -Reviewed-by: Chen-Yu Tsai -Reviewed-by: Markus Schneider-Pargmann -Tested-by: Miles Chen -Link: https://lore.kernel.org/r/20230120092053.182923-4-angelogioacchino.delregno@collabora.com -Tested-by: Mingming Su -Signed-off-by: Stephen Boyd - -[daniel@makrotopia.org: dropped parts not relevant for OpenWrt] ---- - drivers/clk/mediatek/clk-gate.c | 23 +++++++--------------- - drivers/clk/mediatek/clk-gate.h | 7 +------ - drivers/clk/mediatek/clk-mt2701-aud.c | 4 ++-- - drivers/clk/mediatek/clk-mt2701-eth.c | 4 ++-- - drivers/clk/mediatek/clk-mt2701-g3d.c | 2 +- - drivers/clk/mediatek/clk-mt2701-hif.c | 4 ++-- - drivers/clk/mediatek/clk-mt2701-mm.c | 4 ++-- - drivers/clk/mediatek/clk-mt2701.c | 12 +++++------ - drivers/clk/mediatek/clk-mt2712-mm.c | 4 ++-- - drivers/clk/mediatek/clk-mt2712.c | 12 +++++------ - drivers/clk/mediatek/clk-mt7622-aud.c | 4 ++-- - drivers/clk/mediatek/clk-mt7622-eth.c | 8 ++++---- - drivers/clk/mediatek/clk-mt7622-hif.c | 8 ++++---- - drivers/clk/mediatek/clk-mt7622.c | 14 ++++++------- - drivers/clk/mediatek/clk-mt7629-eth.c | 7 ++++--- - drivers/clk/mediatek/clk-mt7629-hif.c | 8 ++++---- - drivers/clk/mediatek/clk-mt7629.c | 10 +++++----- - drivers/clk/mediatek/clk-mt7986-eth.c | 10 +++++----- - drivers/clk/mediatek/clk-mt7986-infracfg.c | 4 ++-- - 19 files changed, 68 insertions(+), 81 deletions(-) - ---- a/drivers/clk/mediatek/clk-gate.c -+++ b/drivers/clk/mediatek/clk-gate.c -@@ -152,12 +152,12 @@ const struct clk_ops mtk_clk_gate_ops_no - }; - EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr_inv); - --static struct clk_hw *mtk_clk_register_gate(const char *name, -+static struct clk_hw *mtk_clk_register_gate(struct device *dev, const char *name, - const char *parent_name, - struct regmap *regmap, int set_ofs, - int clr_ofs, int sta_ofs, u8 bit, - const struct clk_ops *ops, -- unsigned long flags, struct device *dev) -+ unsigned long flags) - { - struct mtk_clk_gate *cg; - int ret; -@@ -202,10 +202,9 @@ static void mtk_clk_unregister_gate(stru - kfree(cg); - } - --int mtk_clk_register_gates_with_dev(struct device_node *node, -- const struct mtk_gate *clks, int num, -- struct clk_hw_onecell_data *clk_data, -- struct device *dev) -+int mtk_clk_register_gates(struct device *dev, struct device_node *node, -+ const struct mtk_gate *clks, int num, -+ struct clk_hw_onecell_data *clk_data) - { - int i; - struct clk_hw *hw; -@@ -229,13 +228,13 @@ int mtk_clk_register_gates_with_dev(stru - continue; - } - -- hw = mtk_clk_register_gate(gate->name, gate->parent_name, -+ hw = mtk_clk_register_gate(dev, gate->name, gate->parent_name, - regmap, - gate->regs->set_ofs, - gate->regs->clr_ofs, - gate->regs->sta_ofs, - gate->shift, gate->ops, -- gate->flags, dev); -+ gate->flags); - - if (IS_ERR(hw)) { - pr_err("Failed to register clk %s: %pe\n", gate->name, -@@ -261,14 +260,6 @@ err: - - return PTR_ERR(hw); - } --EXPORT_SYMBOL_GPL(mtk_clk_register_gates_with_dev); -- --int mtk_clk_register_gates(struct device_node *node, -- const struct mtk_gate *clks, int num, -- struct clk_hw_onecell_data *clk_data) --{ -- return mtk_clk_register_gates_with_dev(node, clks, num, clk_data, NULL); --} - EXPORT_SYMBOL_GPL(mtk_clk_register_gates); - - void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num, ---- a/drivers/clk/mediatek/clk-gate.h -+++ b/drivers/clk/mediatek/clk-gate.h -@@ -50,15 +50,10 @@ struct mtk_gate { - #define GATE_MTK(_id, _name, _parent, _regs, _shift, _ops) \ - GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, _ops, 0) - --int mtk_clk_register_gates(struct device_node *node, -+int mtk_clk_register_gates(struct device *dev, struct device_node *node, - const struct mtk_gate *clks, int num, - struct clk_hw_onecell_data *clk_data); - --int mtk_clk_register_gates_with_dev(struct device_node *node, -- const struct mtk_gate *clks, int num, -- struct clk_hw_onecell_data *clk_data, -- struct device *dev); -- - void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num, - struct clk_hw_onecell_data *clk_data); - ---- a/drivers/clk/mediatek/clk-mt2701-aud.c -+++ b/drivers/clk/mediatek/clk-mt2701-aud.c -@@ -127,8 +127,8 @@ static int clk_mt2701_aud_probe(struct p - - clk_data = mtk_alloc_clk_data(CLK_AUD_NR); - -- mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, audio_clks, -+ ARRAY_SIZE(audio_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) { ---- a/drivers/clk/mediatek/clk-mt2701-eth.c -+++ b/drivers/clk/mediatek/clk-mt2701-eth.c -@@ -51,8 +51,8 @@ static int clk_mt2701_eth_probe(struct p - - clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR); - -- mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, eth_clks, -+ ARRAY_SIZE(eth_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) ---- a/drivers/clk/mediatek/clk-mt2701-g3d.c -+++ b/drivers/clk/mediatek/clk-mt2701-g3d.c -@@ -45,7 +45,7 @@ static int clk_mt2701_g3dsys_init(struct - - clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR); - -- mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks), -+ mtk_clk_register_gates(&pdev->dev, node, g3d_clks, ARRAY_SIZE(g3d_clks), - clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); ---- a/drivers/clk/mediatek/clk-mt2701-hif.c -+++ b/drivers/clk/mediatek/clk-mt2701-hif.c -@@ -48,8 +48,8 @@ static int clk_mt2701_hif_probe(struct p - - clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR); - -- mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, hif_clks, -+ ARRAY_SIZE(hif_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) { ---- a/drivers/clk/mediatek/clk-mt2701-mm.c -+++ b/drivers/clk/mediatek/clk-mt2701-mm.c -@@ -76,8 +76,8 @@ static int clk_mt2701_mm_probe(struct pl - - clk_data = mtk_alloc_clk_data(CLK_MM_NR); - -- mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, mm_clks, -+ ARRAY_SIZE(mm_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) ---- a/drivers/clk/mediatek/clk-mt2701.c -+++ b/drivers/clk/mediatek/clk-mt2701.c -@@ -683,8 +683,8 @@ static int mtk_topckgen_init(struct plat - mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), - base, &mt2701_clk_lock, clk_data); - -- mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, top_clks, -+ ARRAY_SIZE(top_clks), clk_data); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - } -@@ -783,8 +783,8 @@ static int mtk_infrasys_init(struct plat - } - } - -- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), -- infra_clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, infra_clks, -+ ARRAY_SIZE(infra_clks), infra_clk_data); - mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), - infra_clk_data); - -@@ -894,8 +894,8 @@ static int mtk_pericfg_init(struct platf - - clk_data = mtk_alloc_clk_data(CLK_PERI_NR); - -- mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, peri_clks, -+ ARRAY_SIZE(peri_clks), clk_data); - - mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base, - &mt2701_clk_lock, clk_data); ---- a/drivers/clk/mediatek/clk-mt2712-mm.c -+++ b/drivers/clk/mediatek/clk-mt2712-mm.c -@@ -117,8 +117,8 @@ static int clk_mt2712_mm_probe(struct pl - - clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); - -- mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, mm_clks, -+ ARRAY_SIZE(mm_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - ---- a/drivers/clk/mediatek/clk-mt2712.c -+++ b/drivers/clk/mediatek/clk-mt2712.c -@@ -1324,8 +1324,8 @@ static int clk_mt2712_top_probe(struct p - &mt2712_clk_lock, top_clk_data); - mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, - &mt2712_clk_lock, top_clk_data); -- mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), -- top_clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, top_clks, -+ ARRAY_SIZE(top_clks), top_clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); - -@@ -1344,8 +1344,8 @@ static int clk_mt2712_infra_probe(struct - - clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - -- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, infra_clks, -+ ARRAY_SIZE(infra_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - -@@ -1366,8 +1366,8 @@ static int clk_mt2712_peri_probe(struct - - clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); - -- mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, peri_clks, -+ ARRAY_SIZE(peri_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - ---- a/drivers/clk/mediatek/clk-mt7622-aud.c -+++ b/drivers/clk/mediatek/clk-mt7622-aud.c -@@ -114,8 +114,8 @@ static int clk_mt7622_audiosys_init(stru - - clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK); - -- mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, audio_clks, -+ ARRAY_SIZE(audio_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) { ---- a/drivers/clk/mediatek/clk-mt7622-eth.c -+++ b/drivers/clk/mediatek/clk-mt7622-eth.c -@@ -69,8 +69,8 @@ static int clk_mt7622_ethsys_init(struct - - clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK); - -- mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, eth_clks, -+ ARRAY_SIZE(eth_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) -@@ -91,8 +91,8 @@ static int clk_mt7622_sgmiisys_init(stru - - clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK); - -- mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, sgmii_clks, -+ ARRAY_SIZE(sgmii_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) ---- a/drivers/clk/mediatek/clk-mt7622-hif.c -+++ b/drivers/clk/mediatek/clk-mt7622-hif.c -@@ -80,8 +80,8 @@ static int clk_mt7622_ssusbsys_init(stru - - clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); - -- mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, ssusb_clks, -+ ARRAY_SIZE(ssusb_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) -@@ -102,8 +102,8 @@ static int clk_mt7622_pciesys_init(struc - - clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK); - -- mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, pcie_clks, -+ ARRAY_SIZE(pcie_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) ---- a/drivers/clk/mediatek/clk-mt7622.c -+++ b/drivers/clk/mediatek/clk-mt7622.c -@@ -621,8 +621,8 @@ static int mtk_topckgen_init(struct plat - mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), - base, &mt7622_clk_lock, clk_data); - -- mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, top_clks, -+ ARRAY_SIZE(top_clks), clk_data); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - } -@@ -635,8 +635,8 @@ static int mtk_infrasys_init(struct plat - - clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - -- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, infra_clks, -+ ARRAY_SIZE(infra_clks), clk_data); - - mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes), - clk_data); -@@ -663,7 +663,7 @@ static int mtk_apmixedsys_init(struct pl - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), - clk_data); - -- mtk_clk_register_gates(node, apmixed_clks, -+ mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, - ARRAY_SIZE(apmixed_clks), clk_data); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -@@ -682,8 +682,8 @@ static int mtk_pericfg_init(struct platf - - clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); - -- mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, peri_clks, -+ ARRAY_SIZE(peri_clks), clk_data); - - mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base, - &mt7622_clk_lock, clk_data); ---- a/drivers/clk/mediatek/clk-mt7629-eth.c -+++ b/drivers/clk/mediatek/clk-mt7629-eth.c -@@ -80,7 +80,8 @@ static int clk_mt7629_ethsys_init(struct - - clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK); - -- mtk_clk_register_gates(node, eth_clks, CLK_ETH_NR_CLK, clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, eth_clks, -+ CLK_ETH_NR_CLK, clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) -@@ -102,8 +103,8 @@ static int clk_mt7629_sgmiisys_init(stru - - clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK); - -- mtk_clk_register_gates(node, sgmii_clks[id++], CLK_SGMII_NR_CLK, -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, sgmii_clks[id++], -+ CLK_SGMII_NR_CLK, clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) ---- a/drivers/clk/mediatek/clk-mt7629-hif.c -+++ b/drivers/clk/mediatek/clk-mt7629-hif.c -@@ -75,8 +75,8 @@ static int clk_mt7629_ssusbsys_init(stru - - clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); - -- mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, ssusb_clks, -+ ARRAY_SIZE(ssusb_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) -@@ -97,8 +97,8 @@ static int clk_mt7629_pciesys_init(struc - - clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK); - -- mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, pcie_clks, -+ ARRAY_SIZE(pcie_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) ---- a/drivers/clk/mediatek/clk-mt7629.c -+++ b/drivers/clk/mediatek/clk-mt7629.c -@@ -581,8 +581,8 @@ static int mtk_infrasys_init(struct plat - - clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - -- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, infra_clks, -+ ARRAY_SIZE(infra_clks), clk_data); - - mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes), - clk_data); -@@ -604,8 +604,8 @@ static int mtk_pericfg_init(struct platf - - clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); - -- mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, peri_clks, -+ ARRAY_SIZE(peri_clks), clk_data); - - mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base, - &mt7629_clk_lock, clk_data); -@@ -631,7 +631,7 @@ static int mtk_apmixedsys_init(struct pl - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), - clk_data); - -- mtk_clk_register_gates(node, apmixed_clks, -+ mtk_clk_register_gates(&pdev->dev, node, apmixed_clks, - ARRAY_SIZE(apmixed_clks), clk_data); - - clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk); ---- a/drivers/clk/mediatek/clk-mt7986-eth.c -+++ b/drivers/clk/mediatek/clk-mt7986-eth.c -@@ -72,8 +72,8 @@ static void __init mtk_sgmiisys_0_init(s - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks)); - -- mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks), -- clk_data); -+ mtk_clk_register_gates(NULL, node, sgmii0_clks, -+ ARRAY_SIZE(sgmii0_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) -@@ -90,8 +90,8 @@ static void __init mtk_sgmiisys_1_init(s - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks)); - -- mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks), -- clk_data); -+ mtk_clk_register_gates(NULL, node, sgmii1_clks, -+ ARRAY_SIZE(sgmii1_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - -@@ -109,7 +109,7 @@ static void __init mtk_ethsys_init(struc - - clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks)); - -- mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data); -+ mtk_clk_register_gates(NULL, node, eth_clks, ARRAY_SIZE(eth_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - ---- a/drivers/clk/mediatek/clk-mt7986-infracfg.c -+++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c -@@ -180,8 +180,8 @@ static int clk_mt7986_infracfg_probe(str - mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); - mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node, - &mt7986_clk_lock, clk_data); -- mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), -- clk_data); -+ mtk_clk_register_gates(&pdev->dev, node, infra_clks, -+ ARRAY_SIZE(infra_clks), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) { ---- a/drivers/clk/mediatek/clk-mtk.c -+++ b/drivers/clk/mediatek/clk-mtk.c -@@ -459,8 +459,8 @@ int mtk_clk_simple_probe(struct platform - if (!clk_data) - return -ENOMEM; - -- r = mtk_clk_register_gates_with_dev(node, mcd->clks, mcd->num_clks, -- clk_data, &pdev->dev); -+ r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks, mcd->num_clks, -+ clk_data); - if (r) - goto free_data; - diff --git a/6.1/target/linux/mediatek/patches-6.1/221-v6.3-clk-mediatek-cpumux-Propagate-struct-device-where-po.patch b/6.1/target/linux/mediatek/patches-6.1/221-v6.3-clk-mediatek-cpumux-Propagate-struct-device-where-po.patch deleted file mode 100644 index 2333e722..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/221-v6.3-clk-mediatek-cpumux-Propagate-struct-device-where-po.patch +++ /dev/null @@ -1,140 +0,0 @@ -From b888303c7d23d7bd0c8667cfc657669e5d153fea Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Fri, 20 Jan 2023 10:20:34 +0100 -Subject: [PATCH 02/15] clk: mediatek: cpumux: Propagate struct device where - possible - -Take a pointer to a struct device in mtk_clk_register_cpumuxes() and -propagate the same to mtk_clk_register_cpumux() => clk_hw_register(). -Even though runtime pm is unlikely to be used with CPU muxes, this -helps with code consistency and possibly opens to commonization of -some mtk_clk_register_(x) functions. - -Signed-off-by: AngeloGioacchino Del Regno -Reviewed-by: Chen-Yu Tsai -Reviewed-by: Markus Schneider-Pargmann -Tested-by: Miles Chen -Link: https://lore.kernel.org/r/20230120092053.182923-5-angelogioacchino.delregno@collabora.com -Tested-by: Mingming Su -Signed-off-by: Stephen Boyd ---- - drivers/clk/mediatek/clk-cpumux.c | 8 ++++---- - drivers/clk/mediatek/clk-cpumux.h | 2 +- - drivers/clk/mediatek/clk-mt2701.c | 2 +- - drivers/clk/mediatek/clk-mt6795-infracfg.c | 3 ++- - drivers/clk/mediatek/clk-mt7622.c | 4 ++-- - drivers/clk/mediatek/clk-mt7629.c | 4 ++-- - drivers/clk/mediatek/clk-mt8173.c | 4 ++-- - 7 files changed, 14 insertions(+), 13 deletions(-) - ---- a/drivers/clk/mediatek/clk-cpumux.c -+++ b/drivers/clk/mediatek/clk-cpumux.c -@@ -58,7 +58,7 @@ static const struct clk_ops clk_cpumux_o - }; - - static struct clk_hw * --mtk_clk_register_cpumux(const struct mtk_composite *mux, -+mtk_clk_register_cpumux(struct device *dev, const struct mtk_composite *mux, - struct regmap *regmap) - { - struct mtk_clk_cpumux *cpumux; -@@ -81,7 +81,7 @@ mtk_clk_register_cpumux(const struct mtk - cpumux->regmap = regmap; - cpumux->hw.init = &init; - -- ret = clk_hw_register(NULL, &cpumux->hw); -+ ret = clk_hw_register(dev, &cpumux->hw); - if (ret) { - kfree(cpumux); - return ERR_PTR(ret); -@@ -102,7 +102,7 @@ static void mtk_clk_unregister_cpumux(st - kfree(cpumux); - } - --int mtk_clk_register_cpumuxes(struct device_node *node, -+int mtk_clk_register_cpumuxes(struct device *dev, struct device_node *node, - const struct mtk_composite *clks, int num, - struct clk_hw_onecell_data *clk_data) - { -@@ -125,7 +125,7 @@ int mtk_clk_register_cpumuxes(struct dev - continue; - } - -- hw = mtk_clk_register_cpumux(mux, regmap); -+ hw = mtk_clk_register_cpumux(dev, mux, regmap); - if (IS_ERR(hw)) { - pr_err("Failed to register clk %s: %pe\n", mux->name, - hw); ---- a/drivers/clk/mediatek/clk-cpumux.h -+++ b/drivers/clk/mediatek/clk-cpumux.h -@@ -11,7 +11,7 @@ struct clk_hw_onecell_data; - struct device_node; - struct mtk_composite; - --int mtk_clk_register_cpumuxes(struct device_node *node, -+int mtk_clk_register_cpumuxes(struct device *dev, struct device_node *node, - const struct mtk_composite *clks, int num, - struct clk_hw_onecell_data *clk_data); - ---- a/drivers/clk/mediatek/clk-mt2701.c -+++ b/drivers/clk/mediatek/clk-mt2701.c -@@ -757,7 +757,7 @@ static void __init mtk_infrasys_init_ear - mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), - infra_clk_data); - -- mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), -+ mtk_clk_register_cpumuxes(NULL, node, cpu_muxes, ARRAY_SIZE(cpu_muxes), - infra_clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, ---- a/drivers/clk/mediatek/clk-mt6795-infracfg.c -+++ b/drivers/clk/mediatek/clk-mt6795-infracfg.c -@@ -105,7 +105,8 @@ static int clk_mt6795_infracfg_probe(str - if (ret) - goto free_clk_data; - -- ret = mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data); -+ ret = mtk_clk_register_cpumuxes(&pdev->dev, node, cpu_muxes, -+ ARRAY_SIZE(cpu_muxes), clk_data); - if (ret) - goto unregister_gates; - ---- a/drivers/clk/mediatek/clk-mt7622.c -+++ b/drivers/clk/mediatek/clk-mt7622.c -@@ -638,8 +638,8 @@ static int mtk_infrasys_init(struct plat - mtk_clk_register_gates(&pdev->dev, node, infra_clks, - ARRAY_SIZE(infra_clks), clk_data); - -- mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes), -- clk_data); -+ mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes, -+ ARRAY_SIZE(infra_muxes), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, - clk_data); ---- a/drivers/clk/mediatek/clk-mt7629.c -+++ b/drivers/clk/mediatek/clk-mt7629.c -@@ -584,8 +584,8 @@ static int mtk_infrasys_init(struct plat - mtk_clk_register_gates(&pdev->dev, node, infra_clks, - ARRAY_SIZE(infra_clks), clk_data); - -- mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes), -- clk_data); -+ mtk_clk_register_cpumuxes(&pdev->dev, node, infra_muxes, -+ ARRAY_SIZE(infra_muxes), clk_data); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, - clk_data); ---- a/drivers/clk/mediatek/clk-mt8173.c -+++ b/drivers/clk/mediatek/clk-mt8173.c -@@ -892,8 +892,8 @@ static void __init mtk_infrasys_init(str - clk_data); - mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); - -- mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), -- clk_data); -+ mtk_clk_register_cpumuxes(NULL, node, cpu_muxes, -+ ARRAY_SIZE(cpu_muxes), clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) diff --git a/6.1/target/linux/mediatek/patches-6.1/222-v6.3-clk-mediatek-clk-mtk-Propagate-struct-device-for-com.patch b/6.1/target/linux/mediatek/patches-6.1/222-v6.3-clk-mediatek-clk-mtk-Propagate-struct-device-for-com.patch deleted file mode 100644 index 01eed6cc..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/222-v6.3-clk-mediatek-clk-mtk-Propagate-struct-device-for-com.patch +++ /dev/null @@ -1,181 +0,0 @@ -From f23375db001ec0fe9f565be75eff43adde15407e Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Fri, 20 Jan 2023 10:20:35 +0100 -Subject: [PATCH 03/15] clk: mediatek: clk-mtk: Propagate struct device for - composites - -Like done for cpumux clocks, propagate struct device for composite -clocks registered through clk-mtk helpers to be able to get runtime -pm support for MTK clocks. - -Signed-off-by: AngeloGioacchino Del Regno -Tested-by: Miles Chen -Link: https://lore.kernel.org/r/20230120092053.182923-6-angelogioacchino.delregno@collabora.com -Tested-by: Mingming Su -Signed-off-by: Stephen Boyd - -[daniel@makrotopia.org: remove parts not relevant for OpenWrt] ---- - drivers/clk/mediatek/clk-mt2701.c | 10 ++++++---- - drivers/clk/mediatek/clk-mt2712.c | 12 ++++++++---- - drivers/clk/mediatek/clk-mt7622.c | 8 +++++--- - drivers/clk/mediatek/clk-mt7629.c | 8 +++++--- - drivers/clk/mediatek/clk-mtk.c | 11 ++++++----- - drivers/clk/mediatek/clk-mtk.h | 3 ++- - 6 files changed, 32 insertions(+), 20 deletions(-) - ---- a/drivers/clk/mediatek/clk-mt2701.c -+++ b/drivers/clk/mediatek/clk-mt2701.c -@@ -677,8 +677,9 @@ static int mtk_topckgen_init(struct plat - mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs), - clk_data); - -- mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), -- base, &mt2701_clk_lock, clk_data); -+ mtk_clk_register_composites(&pdev->dev, top_muxes, -+ ARRAY_SIZE(top_muxes), base, -+ &mt2701_clk_lock, clk_data); - - mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), - base, &mt2701_clk_lock, clk_data); -@@ -897,8 +898,9 @@ static int mtk_pericfg_init(struct platf - mtk_clk_register_gates(&pdev->dev, node, peri_clks, - ARRAY_SIZE(peri_clks), clk_data); - -- mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base, -- &mt2701_clk_lock, clk_data); -+ mtk_clk_register_composites(&pdev->dev, peri_muxs, -+ ARRAY_SIZE(peri_muxs), base, -+ &mt2701_clk_lock, clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) ---- a/drivers/clk/mediatek/clk-mt2712.c -+++ b/drivers/clk/mediatek/clk-mt2712.c -@@ -1320,8 +1320,9 @@ static int clk_mt2712_top_probe(struct p - mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), - top_clk_data); - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); -- mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, -- &mt2712_clk_lock, top_clk_data); -+ mtk_clk_register_composites(&pdev->dev, top_muxes, -+ ARRAY_SIZE(top_muxes), base, -+ &mt2712_clk_lock, top_clk_data); - mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, - &mt2712_clk_lock, top_clk_data); - mtk_clk_register_gates(&pdev->dev, node, top_clks, -@@ -1395,8 +1396,11 @@ static int clk_mt2712_mcu_probe(struct p - - clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK); - -- mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base, -- &mt2712_clk_lock, clk_data); -+ r = mtk_clk_register_composites(&pdev->dev, mcu_muxes, -+ ARRAY_SIZE(mcu_muxes), base, -+ &mt2712_clk_lock, clk_data); -+ if (r) -+ dev_err(&pdev->dev, "Could not register composites: %d\n", r); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - ---- a/drivers/clk/mediatek/clk-mt7622.c -+++ b/drivers/clk/mediatek/clk-mt7622.c -@@ -615,8 +615,9 @@ static int mtk_topckgen_init(struct plat - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), - clk_data); - -- mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), -- base, &mt7622_clk_lock, clk_data); -+ mtk_clk_register_composites(&pdev->dev, top_muxes, -+ ARRAY_SIZE(top_muxes), base, -+ &mt7622_clk_lock, clk_data); - - mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), - base, &mt7622_clk_lock, clk_data); -@@ -685,7 +686,8 @@ static int mtk_pericfg_init(struct platf - mtk_clk_register_gates(&pdev->dev, node, peri_clks, - ARRAY_SIZE(peri_clks), clk_data); - -- mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base, -+ mtk_clk_register_composites(&pdev->dev, peri_muxes, -+ ARRAY_SIZE(peri_muxes), base, - &mt7622_clk_lock, clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); ---- a/drivers/clk/mediatek/clk-mt7629.c -+++ b/drivers/clk/mediatek/clk-mt7629.c -@@ -564,8 +564,9 @@ static int mtk_topckgen_init(struct plat - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), - clk_data); - -- mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), -- base, &mt7629_clk_lock, clk_data); -+ mtk_clk_register_composites(&pdev->dev, top_muxes, -+ ARRAY_SIZE(top_muxes), base, -+ &mt7629_clk_lock, clk_data); - - clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk); - clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk); -@@ -607,7 +608,8 @@ static int mtk_pericfg_init(struct platf - mtk_clk_register_gates(&pdev->dev, node, peri_clks, - ARRAY_SIZE(peri_clks), clk_data); - -- mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base, -+ mtk_clk_register_composites(&pdev->dev, peri_muxes, -+ ARRAY_SIZE(peri_muxes), base, - &mt7629_clk_lock, clk_data); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); ---- a/drivers/clk/mediatek/clk-mtk.c -+++ b/drivers/clk/mediatek/clk-mtk.c -@@ -197,8 +197,8 @@ void mtk_clk_unregister_factors(const st - } - EXPORT_SYMBOL_GPL(mtk_clk_unregister_factors); - --static struct clk_hw *mtk_clk_register_composite(const struct mtk_composite *mc, -- void __iomem *base, spinlock_t *lock) -+static struct clk_hw *mtk_clk_register_composite(struct device *dev, -+ const struct mtk_composite *mc, void __iomem *base, spinlock_t *lock) - { - struct clk_hw *hw; - struct clk_mux *mux = NULL; -@@ -264,7 +264,7 @@ static struct clk_hw *mtk_clk_register_c - div_ops = &clk_divider_ops; - } - -- hw = clk_hw_register_composite(NULL, mc->name, parent_names, num_parents, -+ hw = clk_hw_register_composite(dev, mc->name, parent_names, num_parents, - mux_hw, mux_ops, - div_hw, div_ops, - gate_hw, gate_ops, -@@ -308,7 +308,8 @@ static void mtk_clk_unregister_composite - kfree(mux); - } - --int mtk_clk_register_composites(const struct mtk_composite *mcs, int num, -+int mtk_clk_register_composites(struct device *dev, -+ const struct mtk_composite *mcs, int num, - void __iomem *base, spinlock_t *lock, - struct clk_hw_onecell_data *clk_data) - { -@@ -327,7 +328,7 @@ int mtk_clk_register_composites(const st - continue; - } - -- hw = mtk_clk_register_composite(mc, base, lock); -+ hw = mtk_clk_register_composite(dev, mc, base, lock); - - if (IS_ERR(hw)) { - pr_err("Failed to register clk %s: %pe\n", mc->name, ---- a/drivers/clk/mediatek/clk-mtk.h -+++ b/drivers/clk/mediatek/clk-mtk.h -@@ -149,7 +149,8 @@ struct mtk_composite { - .flags = 0, \ - } - --int mtk_clk_register_composites(const struct mtk_composite *mcs, int num, -+int mtk_clk_register_composites(struct device *dev, -+ const struct mtk_composite *mcs, int num, - void __iomem *base, spinlock_t *lock, - struct clk_hw_onecell_data *clk_data); - void mtk_clk_unregister_composites(const struct mtk_composite *mcs, int num, diff --git a/6.1/target/linux/mediatek/patches-6.1/223-v6.3-clk-mediatek-clk-mux-Propagate-struct-device-for-mtk.patch b/6.1/target/linux/mediatek/patches-6.1/223-v6.3-clk-mediatek-clk-mux-Propagate-struct-device-for-mtk.patch deleted file mode 100644 index a50422da..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/223-v6.3-clk-mediatek-clk-mux-Propagate-struct-device-for-mtk.patch +++ /dev/null @@ -1,103 +0,0 @@ -From 5d911479e4c732729bfa798e4a9e3e5aec3e30a7 Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Fri, 20 Jan 2023 10:20:36 +0100 -Subject: [PATCH 04/15] clk: mediatek: clk-mux: Propagate struct device for - mtk-mux - -Like done for other clocks, propagate struct device for mtk mux clocks -registered through clk-mux helpers to enable runtime pm support. - -Signed-off-by: AngeloGioacchino Del Regno -Tested-by: Miles Chen -Link: https://lore.kernel.org/r/20230120092053.182923-7-angelogioacchino.delregno@collabora.com -Tested-by: Mingming Su -Signed-off-by: Stephen Boyd - -[daniel@makrotopia.org: removed parts not relevant for OpenWrt] ---- - drivers/clk/mediatek/clk-mt7986-infracfg.c | 3 ++- - drivers/clk/mediatek/clk-mt7986-topckgen.c | 3 ++- - drivers/clk/mediatek/clk-mux.c | 14 ++++++++------ - drivers/clk/mediatek/clk-mux.h | 3 ++- - 4 files changed, 14 insertions(+), 9 deletions(-) - ---- a/drivers/clk/mediatek/clk-mt7986-infracfg.c -+++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c -@@ -178,7 +178,8 @@ static int clk_mt7986_infracfg_probe(str - return -ENOMEM; - - mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); -- mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node, -+ mtk_clk_register_muxes(&pdev->dev, infra_muxes, -+ ARRAY_SIZE(infra_muxes), node, - &mt7986_clk_lock, clk_data); - mtk_clk_register_gates(&pdev->dev, node, infra_clks, - ARRAY_SIZE(infra_clks), clk_data); ---- a/drivers/clk/mediatek/clk-mt7986-topckgen.c -+++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c -@@ -303,7 +303,8 @@ static int clk_mt7986_topckgen_probe(str - mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), - clk_data); - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); -- mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, -+ mtk_clk_register_muxes(&pdev->dev, top_muxes, -+ ARRAY_SIZE(top_muxes), node, - &mt7986_clk_lock, clk_data); - - clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk); ---- a/drivers/clk/mediatek/clk-mux.c -+++ b/drivers/clk/mediatek/clk-mux.c -@@ -154,9 +154,10 @@ const struct clk_ops mtk_mux_gate_clr_se - }; - EXPORT_SYMBOL_GPL(mtk_mux_gate_clr_set_upd_ops); - --static struct clk_hw *mtk_clk_register_mux(const struct mtk_mux *mux, -- struct regmap *regmap, -- spinlock_t *lock) -+static struct clk_hw *mtk_clk_register_mux(struct device *dev, -+ const struct mtk_mux *mux, -+ struct regmap *regmap, -+ spinlock_t *lock) - { - struct mtk_clk_mux *clk_mux; - struct clk_init_data init = {}; -@@ -177,7 +178,7 @@ static struct clk_hw *mtk_clk_register_m - clk_mux->lock = lock; - clk_mux->hw.init = &init; - -- ret = clk_hw_register(NULL, &clk_mux->hw); -+ ret = clk_hw_register(dev, &clk_mux->hw); - if (ret) { - kfree(clk_mux); - return ERR_PTR(ret); -@@ -198,7 +199,8 @@ static void mtk_clk_unregister_mux(struc - kfree(mux); - } - --int mtk_clk_register_muxes(const struct mtk_mux *muxes, -+int mtk_clk_register_muxes(struct device *dev, -+ const struct mtk_mux *muxes, - int num, struct device_node *node, - spinlock_t *lock, - struct clk_hw_onecell_data *clk_data) -@@ -222,7 +224,7 @@ int mtk_clk_register_muxes(const struct - continue; - } - -- hw = mtk_clk_register_mux(mux, regmap, lock); -+ hw = mtk_clk_register_mux(dev, mux, regmap, lock); - - if (IS_ERR(hw)) { - pr_err("Failed to register clk %s: %pe\n", mux->name, ---- a/drivers/clk/mediatek/clk-mux.h -+++ b/drivers/clk/mediatek/clk-mux.h -@@ -83,7 +83,8 @@ extern const struct clk_ops mtk_mux_gate - 0, _upd_ofs, _upd, CLK_SET_RATE_PARENT, \ - mtk_mux_clr_set_upd_ops) - --int mtk_clk_register_muxes(const struct mtk_mux *muxes, -+int mtk_clk_register_muxes(struct device *dev, -+ const struct mtk_mux *muxes, - int num, struct device_node *node, - spinlock_t *lock, - struct clk_hw_onecell_data *clk_data); diff --git a/6.1/target/linux/mediatek/patches-6.1/224-v6.3-clk-mediatek-clk-mtk-Add-dummy-clock-ops.patch b/6.1/target/linux/mediatek/patches-6.1/224-v6.3-clk-mediatek-clk-mtk-Add-dummy-clock-ops.patch deleted file mode 100644 index de2e6976..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/224-v6.3-clk-mediatek-clk-mtk-Add-dummy-clock-ops.patch +++ /dev/null @@ -1,74 +0,0 @@ -From b8eb1081d267708ba976525a1fe2162901b34f3a Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Fri, 20 Jan 2023 10:20:37 +0100 -Subject: [PATCH] clk: mediatek: clk-mtk: Add dummy clock ops - -In order to migrate some (few) old clock drivers to the common -mtk_clk_simple_probe() function, add dummy clock ops to be able -to insert a dummy clock with ID 0 at the beginning of the list. - -Signed-off-by: AngeloGioacchino Del Regno -Reviewed-by: Miles Chen -Reviewed-by: Chen-Yu Tsai -Tested-by: Miles Chen -Link: https://lore.kernel.org/r/20230120092053.182923-8-angelogioacchino.delregno@collabora.com -Tested-by: Mingming Su -Signed-off-by: Stephen Boyd ---- - drivers/clk/mediatek/clk-mtk.c | 16 ++++++++++++++++ - drivers/clk/mediatek/clk-mtk.h | 19 +++++++++++++++++++ - 2 files changed, 35 insertions(+) - ---- a/drivers/clk/mediatek/clk-mtk.c -+++ b/drivers/clk/mediatek/clk-mtk.c -@@ -18,6 +18,22 @@ - #include "clk-mtk.h" - #include "clk-gate.h" - -+const struct mtk_gate_regs cg_regs_dummy = { 0, 0, 0 }; -+EXPORT_SYMBOL_GPL(cg_regs_dummy); -+ -+static int mtk_clk_dummy_enable(struct clk_hw *hw) -+{ -+ return 0; -+} -+ -+static void mtk_clk_dummy_disable(struct clk_hw *hw) { } -+ -+const struct clk_ops mtk_clk_dummy_ops = { -+ .enable = mtk_clk_dummy_enable, -+ .disable = mtk_clk_dummy_disable, -+}; -+EXPORT_SYMBOL_GPL(mtk_clk_dummy_ops); -+ - static void mtk_init_clk_data(struct clk_hw_onecell_data *clk_data, - unsigned int clk_num) - { ---- a/drivers/clk/mediatek/clk-mtk.h -+++ b/drivers/clk/mediatek/clk-mtk.h -@@ -22,6 +22,25 @@ - - struct platform_device; - -+/* -+ * We need the clock IDs to start from zero but to maintain devicetree -+ * backwards compatibility we can't change bindings to start from zero. -+ * Only a few platforms are affected, so we solve issues given by the -+ * commonized MTK clocks probe function(s) by adding a dummy clock at -+ * the beginning where needed. -+ */ -+#define CLK_DUMMY 0 -+ -+extern const struct clk_ops mtk_clk_dummy_ops; -+extern const struct mtk_gate_regs cg_regs_dummy; -+ -+#define GATE_DUMMY(_id, _name) { \ -+ .id = _id, \ -+ .name = _name, \ -+ .regs = &cg_regs_dummy, \ -+ .ops = &mtk_clk_dummy_ops, \ -+ } -+ - struct mtk_fixed_clk { - int id; - const char *name; diff --git a/6.1/target/linux/mediatek/patches-6.1/225-v6.3-clk-mediatek-Switch-to-mtk_clk_simple_probe-where-po.patch b/6.1/target/linux/mediatek/patches-6.1/225-v6.3-clk-mediatek-Switch-to-mtk_clk_simple_probe-where-po.patch deleted file mode 100644 index becfcd0e..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/225-v6.3-clk-mediatek-Switch-to-mtk_clk_simple_probe-where-po.patch +++ /dev/null @@ -1,790 +0,0 @@ -From c26e28015b74af73e0b299f6ad3ff22931e600b4 Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Fri, 20 Jan 2023 10:20:41 +0100 -Subject: [PATCH 05/15] clk: mediatek: Switch to mtk_clk_simple_probe() where - possible - -mtk_clk_simple_probe() is a function that registers mtk gate clocks -and, if reset data is present, a reset controller and across all of -the MTK clock drivers, such a function is duplicated many times: -switch to the common mtk_clk_simple_probe() function for all of the -clock drivers that are registering as platform drivers. - -Signed-off-by: AngeloGioacchino Del Regno -Reviewed-by: Miles Chen -Tested-by: Miles Chen -Link: https://lore.kernel.org/r/20230120092053.182923-12-angelogioacchino.delregno@collabora.com -Tested-by: Mingming Su -Signed-off-by: Stephen Boyd - -[daniel@makrotopia.org: removed parts not relevant for OpenWrt] ---- - drivers/clk/mediatek/clk-mt2701-aud.c | 31 ++++++---- - drivers/clk/mediatek/clk-mt2701-eth.c | 36 ++++-------- - drivers/clk/mediatek/clk-mt2701-g3d.c | 56 ++++-------------- - drivers/clk/mediatek/clk-mt2701-hif.c | 38 ++++-------- - drivers/clk/mediatek/clk-mt2712.c | 83 ++++++++++---------------- - drivers/clk/mediatek/clk-mt7622-aud.c | 54 ++++++----------- - drivers/clk/mediatek/clk-mt7622-eth.c | 82 +++++--------------------- - drivers/clk/mediatek/clk-mt7622-hif.c | 85 +++++---------------------- - drivers/clk/mediatek/clk-mt7629-hif.c | 85 +++++---------------------- - 9 files changed, 144 insertions(+), 406 deletions(-) - ---- a/drivers/clk/mediatek/clk-mt2701-aud.c -+++ b/drivers/clk/mediatek/clk-mt2701-aud.c -@@ -52,6 +52,7 @@ static const struct mtk_gate_regs audio3 - }; - - static const struct mtk_gate audio_clks[] = { -+ GATE_DUMMY(CLK_DUMMY, "aud_dummy"), - /* AUDIO0 */ - GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2), - GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20), -@@ -114,29 +115,27 @@ static const struct mtk_gate audio_clks[ - GATE_AUDIO3(CLK_AUD_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14), - }; - -+static const struct mtk_clk_desc audio_desc = { -+ .clks = audio_clks, -+ .num_clks = ARRAY_SIZE(audio_clks), -+}; -+ - static const struct of_device_id of_match_clk_mt2701_aud[] = { -- { .compatible = "mediatek,mt2701-audsys", }, -- {} -+ { .compatible = "mediatek,mt2701-audsys", .data = &audio_desc }, -+ { /* sentinel */ } - }; - - static int clk_mt2701_aud_probe(struct platform_device *pdev) - { -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; - int r; - -- clk_data = mtk_alloc_clk_data(CLK_AUD_NR); -- -- mtk_clk_register_gates(&pdev->dev, node, audio_clks, -- ARRAY_SIZE(audio_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -+ r = mtk_clk_simple_probe(pdev); - if (r) { - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - -- goto err_clk_provider; -+ return r; - } - - r = devm_of_platform_populate(&pdev->dev); -@@ -146,13 +145,19 @@ static int clk_mt2701_aud_probe(struct p - return 0; - - err_plat_populate: -- of_clk_del_provider(node); --err_clk_provider: -+ mtk_clk_simple_remove(pdev); - return r; - } - -+static int clk_mt2701_aud_remove(struct platform_device *pdev) -+{ -+ of_platform_depopulate(&pdev->dev); -+ return mtk_clk_simple_remove(pdev); -+} -+ - static struct platform_driver clk_mt2701_aud_drv = { - .probe = clk_mt2701_aud_probe, -+ .remove = clk_mt2701_aud_remove, - .driver = { - .name = "clk-mt2701-aud", - .of_match_table = of_match_clk_mt2701_aud, ---- a/drivers/clk/mediatek/clk-mt2701-eth.c -+++ b/drivers/clk/mediatek/clk-mt2701-eth.c -@@ -20,6 +20,7 @@ static const struct mtk_gate_regs eth_cg - GATE_MTK(_id, _name, _parent, ð_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) - - static const struct mtk_gate eth_clks[] = { -+ GATE_DUMMY(CLK_DUMMY, "eth_dummy"), - GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5), - GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6), - GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7), -@@ -38,35 +39,20 @@ static const struct mtk_clk_rst_desc clk - .rst_bank_nr = ARRAY_SIZE(rst_ofs), - }; - --static const struct of_device_id of_match_clk_mt2701_eth[] = { -- { .compatible = "mediatek,mt2701-ethsys", }, -- {} -+static const struct mtk_clk_desc eth_desc = { -+ .clks = eth_clks, -+ .num_clks = ARRAY_SIZE(eth_clks), -+ .rst_desc = &clk_rst_desc, - }; - --static int clk_mt2701_eth_probe(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- int r; -- struct device_node *node = pdev->dev.of_node; -- -- clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR); -- -- mtk_clk_register_gates(&pdev->dev, node, eth_clks, -- ARRAY_SIZE(eth_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); -- -- return r; --} -+static const struct of_device_id of_match_clk_mt2701_eth[] = { -+ { .compatible = "mediatek,mt2701-ethsys", .data = ð_desc }, -+ { /* sentinel */ } -+}; - - static struct platform_driver clk_mt2701_eth_drv = { -- .probe = clk_mt2701_eth_probe, -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, - .driver = { - .name = "clk-mt2701-eth", - .of_match_table = of_match_clk_mt2701_eth, ---- a/drivers/clk/mediatek/clk-mt2701-g3d.c -+++ b/drivers/clk/mediatek/clk-mt2701-g3d.c -@@ -26,6 +26,7 @@ static const struct mtk_gate_regs g3d_cg - }; - - static const struct mtk_gate g3d_clks[] = { -+ GATE_DUMMY(CLK_DUMMY, "g3d_dummy"), - GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0), - }; - -@@ -37,57 +38,20 @@ static const struct mtk_clk_rst_desc clk - .rst_bank_nr = ARRAY_SIZE(rst_ofs), - }; - --static int clk_mt2701_g3dsys_init(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; -- int r; -- -- clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR); -- -- mtk_clk_register_gates(&pdev->dev, node, g3d_clks, ARRAY_SIZE(g3d_clks), -- clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); -- -- return r; --} -+static const struct mtk_clk_desc g3d_desc = { -+ .clks = g3d_clks, -+ .num_clks = ARRAY_SIZE(g3d_clks), -+ .rst_desc = &clk_rst_desc, -+}; - - static const struct of_device_id of_match_clk_mt2701_g3d[] = { -- { -- .compatible = "mediatek,mt2701-g3dsys", -- .data = clk_mt2701_g3dsys_init, -- }, { -- /* sentinel */ -- } -+ { .compatible = "mediatek,mt2701-g3dsys", .data = &g3d_desc }, -+ { /* sentinel */ } - }; - --static int clk_mt2701_g3d_probe(struct platform_device *pdev) --{ -- int (*clk_init)(struct platform_device *); -- int r; -- -- clk_init = of_device_get_match_data(&pdev->dev); -- if (!clk_init) -- return -EINVAL; -- -- r = clk_init(pdev); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- return r; --} -- - static struct platform_driver clk_mt2701_g3d_drv = { -- .probe = clk_mt2701_g3d_probe, -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, - .driver = { - .name = "clk-mt2701-g3d", - .of_match_table = of_match_clk_mt2701_g3d, ---- a/drivers/clk/mediatek/clk-mt2701-hif.c -+++ b/drivers/clk/mediatek/clk-mt2701-hif.c -@@ -20,6 +20,7 @@ static const struct mtk_gate_regs hif_cg - GATE_MTK(_id, _name, _parent, &hif_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) - - static const struct mtk_gate hif_clks[] = { -+ GATE_DUMMY(CLK_DUMMY, "hif_dummy"), - GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21), - GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22), - GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24), -@@ -35,37 +36,20 @@ static const struct mtk_clk_rst_desc clk - .rst_bank_nr = ARRAY_SIZE(rst_ofs), - }; - --static const struct of_device_id of_match_clk_mt2701_hif[] = { -- { .compatible = "mediatek,mt2701-hifsys", }, -- {} -+static const struct mtk_clk_desc hif_desc = { -+ .clks = hif_clks, -+ .num_clks = ARRAY_SIZE(hif_clks), -+ .rst_desc = &clk_rst_desc, - }; - --static int clk_mt2701_hif_probe(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- int r; -- struct device_node *node = pdev->dev.of_node; -- -- clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR); -- -- mtk_clk_register_gates(&pdev->dev, node, hif_clks, -- ARRAY_SIZE(hif_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- if (r) { -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- return r; -- } -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); -- -- return 0; --} -+static const struct of_device_id of_match_clk_mt2701_hif[] = { -+ { .compatible = "mediatek,mt2701-hifsys", .data = &hif_desc }, -+ { /* sentinel */ } -+}; - - static struct platform_driver clk_mt2701_hif_drv = { -- .probe = clk_mt2701_hif_probe, -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, - .driver = { - .name = "clk-mt2701-hif", - .of_match_table = of_match_clk_mt2701_hif, ---- a/drivers/clk/mediatek/clk-mt2712.c -+++ b/drivers/clk/mediatek/clk-mt2712.c -@@ -1337,50 +1337,6 @@ static int clk_mt2712_top_probe(struct p - return r; - } - --static int clk_mt2712_infra_probe(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- int r; -- struct device_node *node = pdev->dev.of_node; -- -- clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); -- -- mtk_clk_register_gates(&pdev->dev, node, infra_clks, -- ARRAY_SIZE(infra_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- -- if (r != 0) -- pr_err("%s(): could not register clock provider: %d\n", -- __func__, r); -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]); -- -- return r; --} -- --static int clk_mt2712_peri_probe(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- int r; -- struct device_node *node = pdev->dev.of_node; -- -- clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); -- -- mtk_clk_register_gates(&pdev->dev, node, peri_clks, -- ARRAY_SIZE(peri_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- -- if (r != 0) -- pr_err("%s(): could not register clock provider: %d\n", -- __func__, r); -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]); -- -- return r; --} -- - static int clk_mt2712_mcu_probe(struct platform_device *pdev) - { - struct clk_hw_onecell_data *clk_data; -@@ -1419,12 +1375,6 @@ static const struct of_device_id of_matc - .compatible = "mediatek,mt2712-topckgen", - .data = clk_mt2712_top_probe, - }, { -- .compatible = "mediatek,mt2712-infracfg", -- .data = clk_mt2712_infra_probe, -- }, { -- .compatible = "mediatek,mt2712-pericfg", -- .data = clk_mt2712_peri_probe, -- }, { - .compatible = "mediatek,mt2712-mcucfg", - .data = clk_mt2712_mcu_probe, - }, { -@@ -1450,6 +1400,33 @@ static int clk_mt2712_probe(struct platf - return r; - } - -+static const struct mtk_clk_desc infra_desc = { -+ .clks = infra_clks, -+ .num_clks = ARRAY_SIZE(infra_clks), -+ .rst_desc = &clk_rst_desc[0], -+}; -+ -+static const struct mtk_clk_desc peri_desc = { -+ .clks = peri_clks, -+ .num_clks = ARRAY_SIZE(peri_clks), -+ .rst_desc = &clk_rst_desc[1], -+}; -+ -+static const struct of_device_id of_match_clk_mt2712_simple[] = { -+ { .compatible = "mediatek,mt2712-infracfg", .data = &infra_desc }, -+ { .compatible = "mediatek,mt2712-pericfg", .data = &peri_desc, }, -+ { /* sentinel */ } -+}; -+ -+static struct platform_driver clk_mt2712_simple_drv = { -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, -+ .driver = { -+ .name = "clk-mt2712-simple", -+ .of_match_table = of_match_clk_mt2712_simple, -+ }, -+}; -+ - static struct platform_driver clk_mt2712_drv = { - .probe = clk_mt2712_probe, - .driver = { -@@ -1460,7 +1437,11 @@ static struct platform_driver clk_mt2712 - - static int __init clk_mt2712_init(void) - { -- return platform_driver_register(&clk_mt2712_drv); -+ int ret = platform_driver_register(&clk_mt2712_drv); -+ -+ if (ret) -+ return ret; -+ return platform_driver_register(&clk_mt2712_simple_drv); - } - - arch_initcall(clk_mt2712_init); ---- a/drivers/clk/mediatek/clk-mt7622-aud.c -+++ b/drivers/clk/mediatek/clk-mt7622-aud.c -@@ -106,24 +106,22 @@ static const struct mtk_gate audio_clks[ - GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14), - }; - --static int clk_mt7622_audiosys_init(struct platform_device *pdev) -+static const struct mtk_clk_desc audio_desc = { -+ .clks = audio_clks, -+ .num_clks = ARRAY_SIZE(audio_clks), -+}; -+ -+static int clk_mt7622_aud_probe(struct platform_device *pdev) - { -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; - int r; - -- clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK); -- -- mtk_clk_register_gates(&pdev->dev, node, audio_clks, -- ARRAY_SIZE(audio_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -+ r = mtk_clk_simple_probe(pdev); - if (r) { - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - -- goto err_clk_provider; -+ return r; - } - - r = devm_of_platform_populate(&pdev->dev); -@@ -133,40 +131,24 @@ static int clk_mt7622_audiosys_init(stru - return 0; - - err_plat_populate: -- of_clk_del_provider(node); --err_clk_provider: -+ mtk_clk_simple_remove(pdev); - return r; - } - --static const struct of_device_id of_match_clk_mt7622_aud[] = { -- { -- .compatible = "mediatek,mt7622-audsys", -- .data = clk_mt7622_audiosys_init, -- }, { -- /* sentinel */ -- } --}; -- --static int clk_mt7622_aud_probe(struct platform_device *pdev) -+static int clk_mt7622_aud_remove(struct platform_device *pdev) - { -- int (*clk_init)(struct platform_device *); -- int r; -- -- clk_init = of_device_get_match_data(&pdev->dev); -- if (!clk_init) -- return -EINVAL; -- -- r = clk_init(pdev); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- return r; -+ of_platform_depopulate(&pdev->dev); -+ return mtk_clk_simple_remove(pdev); - } - -+static const struct of_device_id of_match_clk_mt7622_aud[] = { -+ { .compatible = "mediatek,mt7622-audsys", .data = &audio_desc }, -+ { /* sentinel */ } -+}; -+ - static struct platform_driver clk_mt7622_aud_drv = { - .probe = clk_mt7622_aud_probe, -+ .remove = clk_mt7622_aud_remove, - .driver = { - .name = "clk-mt7622-aud", - .of_match_table = of_match_clk_mt7622_aud, ---- a/drivers/clk/mediatek/clk-mt7622-eth.c -+++ b/drivers/clk/mediatek/clk-mt7622-eth.c -@@ -61,80 +61,26 @@ static const struct mtk_clk_rst_desc clk - .rst_bank_nr = ARRAY_SIZE(rst_ofs), - }; - --static int clk_mt7622_ethsys_init(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; -- int r; -- -- clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK); -- -- mtk_clk_register_gates(&pdev->dev, node, eth_clks, -- ARRAY_SIZE(eth_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); -- -- return r; --} -- --static int clk_mt7622_sgmiisys_init(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; -- int r; -- -- clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK); -- -- mtk_clk_register_gates(&pdev->dev, node, sgmii_clks, -- ARRAY_SIZE(sgmii_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -+static const struct mtk_clk_desc eth_desc = { -+ .clks = eth_clks, -+ .num_clks = ARRAY_SIZE(eth_clks), -+ .rst_desc = &clk_rst_desc, -+}; - -- return r; --} -+static const struct mtk_clk_desc sgmii_desc = { -+ .clks = sgmii_clks, -+ .num_clks = ARRAY_SIZE(sgmii_clks), -+}; - - static const struct of_device_id of_match_clk_mt7622_eth[] = { -- { -- .compatible = "mediatek,mt7622-ethsys", -- .data = clk_mt7622_ethsys_init, -- }, { -- .compatible = "mediatek,mt7622-sgmiisys", -- .data = clk_mt7622_sgmiisys_init, -- }, { -- /* sentinel */ -- } -+ { .compatible = "mediatek,mt7622-ethsys", .data = ð_desc }, -+ { .compatible = "mediatek,mt7622-sgmiisys", .data = &sgmii_desc }, -+ { /* sentinel */ } - }; - --static int clk_mt7622_eth_probe(struct platform_device *pdev) --{ -- int (*clk_init)(struct platform_device *); -- int r; -- -- clk_init = of_device_get_match_data(&pdev->dev); -- if (!clk_init) -- return -EINVAL; -- -- r = clk_init(pdev); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- return r; --} -- - static struct platform_driver clk_mt7622_eth_drv = { -- .probe = clk_mt7622_eth_probe, -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, - .driver = { - .name = "clk-mt7622-eth", - .of_match_table = of_match_clk_mt7622_eth, ---- a/drivers/clk/mediatek/clk-mt7622-hif.c -+++ b/drivers/clk/mediatek/clk-mt7622-hif.c -@@ -72,82 +72,27 @@ static const struct mtk_clk_rst_desc clk - .rst_bank_nr = ARRAY_SIZE(rst_ofs), - }; - --static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; -- int r; -- -- clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); -- -- mtk_clk_register_gates(&pdev->dev, node, ssusb_clks, -- ARRAY_SIZE(ssusb_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); -- -- return r; --} -- --static int clk_mt7622_pciesys_init(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; -- int r; -- -- clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK); -- -- mtk_clk_register_gates(&pdev->dev, node, pcie_clks, -- ARRAY_SIZE(pcie_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); -+static const struct mtk_clk_desc ssusb_desc = { -+ .clks = ssusb_clks, -+ .num_clks = ARRAY_SIZE(ssusb_clks), -+ .rst_desc = &clk_rst_desc, -+}; - -- return r; --} -+static const struct mtk_clk_desc pcie_desc = { -+ .clks = pcie_clks, -+ .num_clks = ARRAY_SIZE(pcie_clks), -+ .rst_desc = &clk_rst_desc, -+}; - - static const struct of_device_id of_match_clk_mt7622_hif[] = { -- { -- .compatible = "mediatek,mt7622-pciesys", -- .data = clk_mt7622_pciesys_init, -- }, { -- .compatible = "mediatek,mt7622-ssusbsys", -- .data = clk_mt7622_ssusbsys_init, -- }, { -- /* sentinel */ -- } -+ { .compatible = "mediatek,mt7622-pciesys", .data = &pcie_desc }, -+ { .compatible = "mediatek,mt7622-ssusbsys", .data = &ssusb_desc }, -+ { /* sentinel */ } - }; - --static int clk_mt7622_hif_probe(struct platform_device *pdev) --{ -- int (*clk_init)(struct platform_device *); -- int r; -- -- clk_init = of_device_get_match_data(&pdev->dev); -- if (!clk_init) -- return -EINVAL; -- -- r = clk_init(pdev); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- return r; --} -- - static struct platform_driver clk_mt7622_hif_drv = { -- .probe = clk_mt7622_hif_probe, -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, - .driver = { - .name = "clk-mt7622-hif", - .of_match_table = of_match_clk_mt7622_hif, ---- a/drivers/clk/mediatek/clk-mt7629-hif.c -+++ b/drivers/clk/mediatek/clk-mt7629-hif.c -@@ -67,82 +67,27 @@ static const struct mtk_clk_rst_desc clk - .rst_bank_nr = ARRAY_SIZE(rst_ofs), - }; - --static int clk_mt7629_ssusbsys_init(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; -- int r; -- -- clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); -- -- mtk_clk_register_gates(&pdev->dev, node, ssusb_clks, -- ARRAY_SIZE(ssusb_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); -- -- return r; --} -- --static int clk_mt7629_pciesys_init(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; -- int r; -- -- clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK); -- -- mtk_clk_register_gates(&pdev->dev, node, pcie_clks, -- ARRAY_SIZE(pcie_clks), clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); -+static const struct mtk_clk_desc ssusb_desc = { -+ .clks = ssusb_clks, -+ .num_clks = ARRAY_SIZE(ssusb_clks), -+ .rst_desc = &clk_rst_desc, -+}; - -- return r; --} -+static const struct mtk_clk_desc pcie_desc = { -+ .clks = pcie_clks, -+ .num_clks = ARRAY_SIZE(pcie_clks), -+ .rst_desc = &clk_rst_desc, -+}; - - static const struct of_device_id of_match_clk_mt7629_hif[] = { -- { -- .compatible = "mediatek,mt7629-pciesys", -- .data = clk_mt7629_pciesys_init, -- }, { -- .compatible = "mediatek,mt7629-ssusbsys", -- .data = clk_mt7629_ssusbsys_init, -- }, { -- /* sentinel */ -- } -+ { .compatible = "mediatek,mt7629-pciesys", .data = &pcie_desc }, -+ { .compatible = "mediatek,mt7629-ssusbsys", .data = &ssusb_desc }, -+ { /* sentinel */ } - }; - --static int clk_mt7629_hif_probe(struct platform_device *pdev) --{ -- int (*clk_init)(struct platform_device *); -- int r; -- -- clk_init = of_device_get_match_data(&pdev->dev); -- if (!clk_init) -- return -EINVAL; -- -- r = clk_init(pdev); -- if (r) -- dev_err(&pdev->dev, -- "could not register clock provider: %s: %d\n", -- pdev->name, r); -- -- return r; --} -- - static struct platform_driver clk_mt7629_hif_drv = { -- .probe = clk_mt7629_hif_probe, -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, - .driver = { - .name = "clk-mt7629-hif", - .of_match_table = of_match_clk_mt7629_hif, diff --git a/6.1/target/linux/mediatek/patches-6.1/226-v6.3-clk-mediatek-clk-mtk-Extend-mtk_clk_simple_probe.patch b/6.1/target/linux/mediatek/patches-6.1/226-v6.3-clk-mediatek-clk-mtk-Extend-mtk_clk_simple_probe.patch deleted file mode 100644 index ad02df10..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/226-v6.3-clk-mediatek-clk-mtk-Extend-mtk_clk_simple_probe.patch +++ /dev/null @@ -1,189 +0,0 @@ -From 7b6183108c8ccf0dc295f39cdf78bd8078455636 Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Fri, 20 Jan 2023 10:20:42 +0100 -Subject: [PATCH] clk: mediatek: clk-mtk: Extend mtk_clk_simple_probe() - -As a preparation to increase probe functions commonization across -various MediaTek SoC clock controller drivers, extend function -mtk_clk_simple_probe() to be able to register not only gates, but -also fixed clocks, factors, muxes and composites. - -Signed-off-by: AngeloGioacchino Del Regno -Reviewed-by: Miles Chen -Reviewed-by: Chen-Yu Tsai -Tested-by: Miles Chen -Link: https://lore.kernel.org/r/20230120092053.182923-13-angelogioacchino.delregno@collabora.com -Tested-by: Mingming Su -Signed-off-by: Stephen Boyd ---- - drivers/clk/mediatek/clk-mtk.c | 101 ++++++++++++++++++++++++++++++--- - drivers/clk/mediatek/clk-mtk.h | 10 ++++ - 2 files changed, 103 insertions(+), 8 deletions(-) - ---- a/drivers/clk/mediatek/clk-mtk.c -+++ b/drivers/clk/mediatek/clk-mtk.c -@@ -11,12 +11,14 @@ - #include - #include - #include -+#include - #include - #include - #include - - #include "clk-mtk.h" - #include "clk-gate.h" -+#include "clk-mux.h" - - const struct mtk_gate_regs cg_regs_dummy = { 0, 0, 0 }; - EXPORT_SYMBOL_GPL(cg_regs_dummy); -@@ -466,20 +468,71 @@ int mtk_clk_simple_probe(struct platform - const struct mtk_clk_desc *mcd; - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; -- int r; -+ void __iomem *base; -+ int num_clks, r; - - mcd = of_device_get_match_data(&pdev->dev); - if (!mcd) - return -EINVAL; - -- clk_data = mtk_alloc_clk_data(mcd->num_clks); -+ /* Composite clocks needs us to pass iomem pointer */ -+ if (mcd->composite_clks) { -+ if (!mcd->shared_io) -+ base = devm_platform_ioremap_resource(pdev, 0); -+ else -+ base = of_iomap(node, 0); -+ -+ if (IS_ERR_OR_NULL(base)) -+ return IS_ERR(base) ? PTR_ERR(base) : -ENOMEM; -+ } -+ -+ /* Calculate how many clk_hw_onecell_data entries to allocate */ -+ num_clks = mcd->num_clks + mcd->num_composite_clks; -+ num_clks += mcd->num_fixed_clks + mcd->num_factor_clks; -+ num_clks += mcd->num_mux_clks; -+ -+ clk_data = mtk_alloc_clk_data(num_clks); - if (!clk_data) - return -ENOMEM; - -- r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks, mcd->num_clks, -- clk_data); -- if (r) -- goto free_data; -+ if (mcd->fixed_clks) { -+ r = mtk_clk_register_fixed_clks(mcd->fixed_clks, -+ mcd->num_fixed_clks, clk_data); -+ if (r) -+ goto free_data; -+ } -+ -+ if (mcd->factor_clks) { -+ r = mtk_clk_register_factors(mcd->factor_clks, -+ mcd->num_factor_clks, clk_data); -+ if (r) -+ goto unregister_fixed_clks; -+ } -+ -+ if (mcd->mux_clks) { -+ r = mtk_clk_register_muxes(&pdev->dev, mcd->mux_clks, -+ mcd->num_mux_clks, node, -+ mcd->clk_lock, clk_data); -+ if (r) -+ goto unregister_factors; -+ }; -+ -+ if (mcd->composite_clks) { -+ /* We don't check composite_lock because it's optional */ -+ r = mtk_clk_register_composites(&pdev->dev, -+ mcd->composite_clks, -+ mcd->num_composite_clks, -+ base, mcd->clk_lock, clk_data); -+ if (r) -+ goto unregister_muxes; -+ } -+ -+ if (mcd->clks) { -+ r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks, -+ mcd->num_clks, clk_data); -+ if (r) -+ goto unregister_composites; -+ } - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) -@@ -497,9 +550,28 @@ int mtk_clk_simple_probe(struct platform - return r; - - unregister_clks: -- mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data); -+ if (mcd->clks) -+ mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data); -+unregister_composites: -+ if (mcd->composite_clks) -+ mtk_clk_unregister_composites(mcd->composite_clks, -+ mcd->num_composite_clks, clk_data); -+unregister_muxes: -+ if (mcd->mux_clks) -+ mtk_clk_unregister_muxes(mcd->mux_clks, -+ mcd->num_mux_clks, clk_data); -+unregister_factors: -+ if (mcd->factor_clks) -+ mtk_clk_unregister_factors(mcd->factor_clks, -+ mcd->num_factor_clks, clk_data); -+unregister_fixed_clks: -+ if (mcd->fixed_clks) -+ mtk_clk_unregister_fixed_clks(mcd->fixed_clks, -+ mcd->num_fixed_clks, clk_data); - free_data: - mtk_free_clk_data(clk_data); -+ if (mcd->shared_io && base) -+ iounmap(base); - return r; - } - EXPORT_SYMBOL_GPL(mtk_clk_simple_probe); -@@ -511,7 +583,20 @@ int mtk_clk_simple_remove(struct platfor - struct device_node *node = pdev->dev.of_node; - - of_clk_del_provider(node); -- mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data); -+ if (mcd->clks) -+ mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data); -+ if (mcd->composite_clks) -+ mtk_clk_unregister_composites(mcd->composite_clks, -+ mcd->num_composite_clks, clk_data); -+ if (mcd->mux_clks) -+ mtk_clk_unregister_muxes(mcd->mux_clks, -+ mcd->num_mux_clks, clk_data); -+ if (mcd->factor_clks) -+ mtk_clk_unregister_factors(mcd->factor_clks, -+ mcd->num_factor_clks, clk_data); -+ if (mcd->fixed_clks) -+ mtk_clk_unregister_fixed_clks(mcd->fixed_clks, -+ mcd->num_fixed_clks, clk_data); - mtk_free_clk_data(clk_data); - - return 0; ---- a/drivers/clk/mediatek/clk-mtk.h -+++ b/drivers/clk/mediatek/clk-mtk.h -@@ -215,7 +215,17 @@ void mtk_clk_unregister_ref2usb_tx(struc - struct mtk_clk_desc { - const struct mtk_gate *clks; - size_t num_clks; -+ const struct mtk_composite *composite_clks; -+ size_t num_composite_clks; -+ const struct mtk_fixed_clk *fixed_clks; -+ size_t num_fixed_clks; -+ const struct mtk_fixed_factor *factor_clks; -+ size_t num_factor_clks; -+ const struct mtk_mux *mux_clks; -+ size_t num_mux_clks; - const struct mtk_clk_rst_desc *rst_desc; -+ spinlock_t *clk_lock; -+ bool shared_io; - }; - - int mtk_clk_simple_probe(struct platform_device *pdev); diff --git a/6.1/target/linux/mediatek/patches-6.1/227-v6.3-clk-mediatek-clk-mt7986-topckgen-Properly-keep-some-.patch b/6.1/target/linux/mediatek/patches-6.1/227-v6.3-clk-mediatek-clk-mt7986-topckgen-Properly-keep-some-.patch deleted file mode 100644 index bf9a1729..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/227-v6.3-clk-mediatek-clk-mt7986-topckgen-Properly-keep-some-.patch +++ /dev/null @@ -1,97 +0,0 @@ -From 3511004225ce917a4aa6e6ac61481ac60f08f401 Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Fri, 20 Jan 2023 10:20:52 +0100 -Subject: [PATCH 06/15] clk: mediatek: clk-mt7986-topckgen: Properly keep some - clocks enabled - -Instead of calling clk_prepare_enable() on a bunch of clocks at probe -time, set the CLK_IS_CRITICAL flag to the same as these are required -to be always on, and this is the right way of achieving that. - -Signed-off-by: AngeloGioacchino Del Regno -Reviewed-by: Chen-Yu Tsai -Reviewed-by: Miles Chen -Link: https://lore.kernel.org/r/20230120092053.182923-23-angelogioacchino.delregno@collabora.com -Tested-by: Mingming Su -Signed-off-by: Stephen Boyd ---- - drivers/clk/mediatek/clk-mt7986-topckgen.c | 46 +++++++++++----------- - 1 file changed, 24 insertions(+), 22 deletions(-) - ---- a/drivers/clk/mediatek/clk-mt7986-topckgen.c -+++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c -@@ -202,16 +202,23 @@ static const struct mtk_mux top_muxes[] - MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel", - f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23, - 0x1C0, 10), -- MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents, -- 0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", -+ f_26m_adc_parents, 0x020, 0x024, 0x028, -+ 24, 1, 31, 0x1C0, 11, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), - /* CLK_CFG_3 */ -- MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", -- dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7, -- 0x1C0, 12), -- MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, -- 0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13), -- MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, -- 0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", -+ dramc_md32_parents, 0x030, 0x034, 0x038, -+ 0, 1, 7, 0x1C0, 12, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", -+ sysaxi_parents, 0x030, 0x034, 0x038, -+ 8, 2, 15, 0x1C0, 13, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", -+ sysapb_parents, 0x030, 0x034, 0x038, -+ 16, 2, 23, 0x1C0, 14, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), - MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", - arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, - 31, 0x1C0, 15), -@@ -234,9 +241,10 @@ static const struct mtk_mux top_muxes[] - MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", - sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, - 0x1C0, 21), -- MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", -- sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23, -- 0x1C0, 22), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", -+ sgm_reg_parents, 0x050, 0x054, 0x058, -+ 16, 1, 23, 0x1C0, 22, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), - MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, - 0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23), - /* CLK_CFG_6 */ -@@ -252,9 +260,10 @@ static const struct mtk_mux top_muxes[] - f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31, - 0x1C0, 27), - /* CLK_CFG_7 */ -- MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel", -- f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7, -- 0x1C0, 28), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel", -+ f_26m_adc_parents, 0x070, 0x074, 0x078, -+ 0, 1, 7, 0x1C0, 28, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), - MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, - 0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29), - MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", -@@ -307,13 +316,6 @@ static int clk_mt7986_topckgen_probe(str - ARRAY_SIZE(top_muxes), node, - &mt7986_clk_lock, clk_data); - -- clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk); -- clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAPB_SEL]->clk); -- clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_SEL]->clk); -- clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_MD32_SEL]->clk); -- clk_prepare_enable(clk_data->hws[CLK_TOP_F26M_SEL]->clk); -- clk_prepare_enable(clk_data->hws[CLK_TOP_SGM_REG_SEL]->clk); -- - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - - if (r) { diff --git a/6.1/target/linux/mediatek/patches-6.1/228-v6.3-clk-mediatek-clk-mt7986-topckgen-Migrate-to-mtk_clk_.patch b/6.1/target/linux/mediatek/patches-6.1/228-v6.3-clk-mediatek-clk-mt7986-topckgen-Migrate-to-mtk_clk_.patch deleted file mode 100644 index d77b859f..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/228-v6.3-clk-mediatek-clk-mt7986-topckgen-Migrate-to-mtk_clk_.patch +++ /dev/null @@ -1,88 +0,0 @@ -From 9ce3b4e4719d4eec38b2c8da939c073835573d1d Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Fri, 20 Jan 2023 10:20:53 +0100 -Subject: [PATCH 07/15] clk: mediatek: clk-mt7986-topckgen: Migrate to - mtk_clk_simple_probe() - -There are no more non-common calls in clk_mt7986_topckgen_probe(): -migrate this driver to mtk_clk_simple_probe(). - -Signed-off-by: AngeloGioacchino Del Regno -Reviewed-by: Miles Chen -Reviewed-by: Chen-Yu Tsai -Link: https://lore.kernel.org/r/20230120092053.182923-24-angelogioacchino.delregno@collabora.com -Tested-by: Mingming Su -Signed-off-by: Stephen Boyd ---- - drivers/clk/mediatek/clk-mt7986-topckgen.c | 55 +++++----------------- - 1 file changed, 13 insertions(+), 42 deletions(-) - ---- a/drivers/clk/mediatek/clk-mt7986-topckgen.c -+++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c -@@ -290,53 +290,24 @@ static const struct mtk_mux top_muxes[] - 0x1C4, 5), - }; - --static int clk_mt7986_topckgen_probe(struct platform_device *pdev) --{ -- struct clk_hw_onecell_data *clk_data; -- struct device_node *node = pdev->dev.of_node; -- int r; -- void __iomem *base; -- int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) + -- ARRAY_SIZE(top_muxes); -- -- base = of_iomap(node, 0); -- if (!base) { -- pr_err("%s(): ioremap failed\n", __func__); -- return -ENOMEM; -- } -- -- clk_data = mtk_alloc_clk_data(nr); -- if (!clk_data) -- return -ENOMEM; -- -- mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), -- clk_data); -- mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); -- mtk_clk_register_muxes(&pdev->dev, top_muxes, -- ARRAY_SIZE(top_muxes), node, -- &mt7986_clk_lock, clk_data); -- -- r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -- -- if (r) { -- pr_err("%s(): could not register clock provider: %d\n", -- __func__, r); -- goto free_topckgen_data; -- } -- return r; -- --free_topckgen_data: -- mtk_free_clk_data(clk_data); -- return r; --} -+static const struct mtk_clk_desc topck_desc = { -+ .fixed_clks = top_fixed_clks, -+ .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), -+ .factor_clks = top_divs, -+ .num_factor_clks = ARRAY_SIZE(top_divs), -+ .mux_clks = top_muxes, -+ .num_mux_clks = ARRAY_SIZE(top_muxes), -+ .clk_lock = &mt7986_clk_lock, -+}; - - static const struct of_device_id of_match_clk_mt7986_topckgen[] = { -- { .compatible = "mediatek,mt7986-topckgen", }, -- {} -+ { .compatible = "mediatek,mt7986-topckgen", .data = &topck_desc }, -+ { /* sentinel */ } - }; - - static struct platform_driver clk_mt7986_topckgen_drv = { -- .probe = clk_mt7986_topckgen_probe, -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, - .driver = { - .name = "clk-mt7986-topckgen", - .of_match_table = of_match_clk_mt7986_topckgen, diff --git a/6.1/target/linux/mediatek/patches-6.1/229-v6.4-clk-mediatek-mt7986-apmixed-Use-PLL_AO-flag-to-set-c.patch b/6.1/target/linux/mediatek/patches-6.1/229-v6.4-clk-mediatek-mt7986-apmixed-Use-PLL_AO-flag-to-set-c.patch deleted file mode 100644 index a47dd4b0..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/229-v6.4-clk-mediatek-mt7986-apmixed-Use-PLL_AO-flag-to-set-c.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 06abdc84080729dc2c54946e1712c5ee1589ca1c Mon Sep 17 00:00:00 2001 -From: AngeloGioacchino Del Regno -Date: Mon, 6 Mar 2023 15:05:21 +0100 -Subject: [PATCH 13/15] clk: mediatek: mt7986-apmixed: Use PLL_AO flag to set - critical clock - -Instead of calling clk_prepare_enable() at probe time, add the PLL_AO -flag to CLK_APMIXED_ARMPLL clock: this will set CLK_IS_CRITICAL. - -Signed-off-by: AngeloGioacchino Del Regno -Reviewed-by: Chen-Yu Tsai -Tested-by: Daniel Golle -Link: https://lore.kernel.org/r/20230306140543.1813621-33-angelogioacchino.delregno@collabora.com -Signed-off-by: Stephen Boyd ---- - drivers/clk/mediatek/clk-mt7986-apmixed.c | 4 +--- - 1 file changed, 1 insertion(+), 3 deletions(-) - ---- a/drivers/clk/mediatek/clk-mt7986-apmixed.c -+++ b/drivers/clk/mediatek/clk-mt7986-apmixed.c -@@ -42,7 +42,7 @@ - "clkxtal") - - static const struct mtk_pll_data plls[] = { -- PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, 0, 32, -+ PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, PLL_AO, 32, - 0x0200, 4, 0, 0x0204, 0), - PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x0, 0, 32, - 0x0210, 4, 0, 0x0214, 0), -@@ -77,8 +77,6 @@ static int clk_mt7986_apmixed_probe(stru - - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - -- clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk); -- - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) { - pr_err("%s(): could not register clock provider: %d\n", diff --git a/6.1/target/linux/mediatek/patches-6.1/230-v6.4-dt-bindings-clock-mediatek-add-mt7981-clock-IDs.patch b/6.1/target/linux/mediatek/patches-6.1/230-v6.4-dt-bindings-clock-mediatek-add-mt7981-clock-IDs.patch deleted file mode 100644 index ae76940e..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/230-v6.4-dt-bindings-clock-mediatek-add-mt7981-clock-IDs.patch +++ /dev/null @@ -1,237 +0,0 @@ -From a6473d0f9f07b1196f3a67099826f50a2a4e84e8 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Thu, 26 Jan 2023 03:34:05 +0000 -Subject: [PATCH] dt-bindings: clock: mediatek: add mt7981 clock IDs - -Add MT7981 clock dt-bindings, include topckgen, apmixedsys, -infracfg, and ethernet subsystem clocks. - -Acked-by: Krzysztof Kozlowski -Signed-off-by: Jianhui Zhao -Signed-off-by: Daniel Golle -Link: https://lore.kernel.org/r/e353d32b5a4481766519a037afe1ed44e31ece1a.1674703830.git.daniel@makrotopia.org -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Stephen Boyd ---- - .../dt-bindings/clock/mediatek,mt7981-clk.h | 215 ++++++++++++++++++ - 1 file changed, 215 insertions(+) - create mode 100644 include/dt-bindings/clock/mediatek,mt7981-clk.h - ---- /dev/null -+++ b/include/dt-bindings/clock/mediatek,mt7981-clk.h -@@ -0,0 +1,215 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ -+/* -+ * Copyright (c) 2021 MediaTek Inc. -+ * Author: Wenzhen.Yu -+ * Author: Jianhui Zhao -+ * Author: Daniel Golle -+ */ -+ -+#ifndef _DT_BINDINGS_CLK_MT7981_H -+#define _DT_BINDINGS_CLK_MT7981_H -+ -+/* TOPCKGEN */ -+#define CLK_TOP_CB_CKSQ_40M 0 -+#define CLK_TOP_CB_M_416M 1 -+#define CLK_TOP_CB_M_D2 2 -+#define CLK_TOP_CB_M_D3 3 -+#define CLK_TOP_M_D3_D2 4 -+#define CLK_TOP_CB_M_D4 5 -+#define CLK_TOP_CB_M_D8 6 -+#define CLK_TOP_M_D8_D2 7 -+#define CLK_TOP_CB_MM_720M 8 -+#define CLK_TOP_CB_MM_D2 9 -+#define CLK_TOP_CB_MM_D3 10 -+#define CLK_TOP_CB_MM_D3_D5 11 -+#define CLK_TOP_CB_MM_D4 12 -+#define CLK_TOP_CB_MM_D6 13 -+#define CLK_TOP_MM_D6_D2 14 -+#define CLK_TOP_CB_MM_D8 15 -+#define CLK_TOP_CB_APLL2_196M 16 -+#define CLK_TOP_APLL2_D2 17 -+#define CLK_TOP_APLL2_D4 18 -+#define CLK_TOP_NET1_2500M 19 -+#define CLK_TOP_CB_NET1_D4 20 -+#define CLK_TOP_CB_NET1_D5 21 -+#define CLK_TOP_NET1_D5_D2 22 -+#define CLK_TOP_NET1_D5_D4 23 -+#define CLK_TOP_CB_NET1_D8 24 -+#define CLK_TOP_NET1_D8_D2 25 -+#define CLK_TOP_NET1_D8_D4 26 -+#define CLK_TOP_CB_NET2_800M 27 -+#define CLK_TOP_CB_NET2_D2 28 -+#define CLK_TOP_CB_NET2_D4 29 -+#define CLK_TOP_NET2_D4_D2 30 -+#define CLK_TOP_NET2_D4_D4 31 -+#define CLK_TOP_CB_NET2_D6 32 -+#define CLK_TOP_CB_WEDMCU_208M 33 -+#define CLK_TOP_CB_SGM_325M 34 -+#define CLK_TOP_CKSQ_40M_D2 35 -+#define CLK_TOP_CB_RTC_32K 36 -+#define CLK_TOP_CB_RTC_32P7K 37 -+#define CLK_TOP_USB_TX250M 38 -+#define CLK_TOP_FAUD 39 -+#define CLK_TOP_NFI1X 40 -+#define CLK_TOP_USB_EQ_RX250M 41 -+#define CLK_TOP_USB_CDR_CK 42 -+#define CLK_TOP_USB_LN0_CK 43 -+#define CLK_TOP_SPINFI_BCK 44 -+#define CLK_TOP_SPI 45 -+#define CLK_TOP_SPIM_MST 46 -+#define CLK_TOP_UART_BCK 47 -+#define CLK_TOP_PWM_BCK 48 -+#define CLK_TOP_I2C_BCK 49 -+#define CLK_TOP_PEXTP_TL 50 -+#define CLK_TOP_EMMC_208M 51 -+#define CLK_TOP_EMMC_400M 52 -+#define CLK_TOP_DRAMC_REF 53 -+#define CLK_TOP_DRAMC_MD32 54 -+#define CLK_TOP_SYSAXI 55 -+#define CLK_TOP_SYSAPB 56 -+#define CLK_TOP_ARM_DB_MAIN 57 -+#define CLK_TOP_AP2CNN_HOST 58 -+#define CLK_TOP_NETSYS 59 -+#define CLK_TOP_NETSYS_500M 60 -+#define CLK_TOP_NETSYS_WED_MCU 61 -+#define CLK_TOP_NETSYS_2X 62 -+#define CLK_TOP_SGM_325M 63 -+#define CLK_TOP_SGM_REG 64 -+#define CLK_TOP_F26M 65 -+#define CLK_TOP_EIP97B 66 -+#define CLK_TOP_USB3_PHY 67 -+#define CLK_TOP_AUD 68 -+#define CLK_TOP_A1SYS 69 -+#define CLK_TOP_AUD_L 70 -+#define CLK_TOP_A_TUNER 71 -+#define CLK_TOP_U2U3_REF 72 -+#define CLK_TOP_U2U3_SYS 73 -+#define CLK_TOP_U2U3_XHCI 74 -+#define CLK_TOP_USB_FRMCNT 75 -+#define CLK_TOP_NFI1X_SEL 76 -+#define CLK_TOP_SPINFI_SEL 77 -+#define CLK_TOP_SPI_SEL 78 -+#define CLK_TOP_SPIM_MST_SEL 79 -+#define CLK_TOP_UART_SEL 80 -+#define CLK_TOP_PWM_SEL 81 -+#define CLK_TOP_I2C_SEL 82 -+#define CLK_TOP_PEXTP_TL_SEL 83 -+#define CLK_TOP_EMMC_208M_SEL 84 -+#define CLK_TOP_EMMC_400M_SEL 85 -+#define CLK_TOP_F26M_SEL 86 -+#define CLK_TOP_DRAMC_SEL 87 -+#define CLK_TOP_DRAMC_MD32_SEL 88 -+#define CLK_TOP_SYSAXI_SEL 89 -+#define CLK_TOP_SYSAPB_SEL 90 -+#define CLK_TOP_ARM_DB_MAIN_SEL 91 -+#define CLK_TOP_AP2CNN_HOST_SEL 92 -+#define CLK_TOP_NETSYS_SEL 93 -+#define CLK_TOP_NETSYS_500M_SEL 94 -+#define CLK_TOP_NETSYS_MCU_SEL 95 -+#define CLK_TOP_NETSYS_2X_SEL 96 -+#define CLK_TOP_SGM_325M_SEL 97 -+#define CLK_TOP_SGM_REG_SEL 98 -+#define CLK_TOP_EIP97B_SEL 99 -+#define CLK_TOP_USB3_PHY_SEL 100 -+#define CLK_TOP_AUD_SEL 101 -+#define CLK_TOP_A1SYS_SEL 102 -+#define CLK_TOP_AUD_L_SEL 103 -+#define CLK_TOP_A_TUNER_SEL 104 -+#define CLK_TOP_U2U3_SEL 105 -+#define CLK_TOP_U2U3_SYS_SEL 106 -+#define CLK_TOP_U2U3_XHCI_SEL 107 -+#define CLK_TOP_USB_FRMCNT_SEL 108 -+#define CLK_TOP_AUD_I2S_M 109 -+ -+/* INFRACFG */ -+#define CLK_INFRA_66M_MCK 0 -+#define CLK_INFRA_UART0_SEL 1 -+#define CLK_INFRA_UART1_SEL 2 -+#define CLK_INFRA_UART2_SEL 3 -+#define CLK_INFRA_SPI0_SEL 4 -+#define CLK_INFRA_SPI1_SEL 5 -+#define CLK_INFRA_SPI2_SEL 6 -+#define CLK_INFRA_PWM1_SEL 7 -+#define CLK_INFRA_PWM2_SEL 8 -+#define CLK_INFRA_PWM3_SEL 9 -+#define CLK_INFRA_PWM_BSEL 10 -+#define CLK_INFRA_PCIE_SEL 11 -+#define CLK_INFRA_GPT_STA 12 -+#define CLK_INFRA_PWM_HCK 13 -+#define CLK_INFRA_PWM_STA 14 -+#define CLK_INFRA_PWM1_CK 15 -+#define CLK_INFRA_PWM2_CK 16 -+#define CLK_INFRA_PWM3_CK 17 -+#define CLK_INFRA_CQ_DMA_CK 18 -+#define CLK_INFRA_AUD_BUS_CK 19 -+#define CLK_INFRA_AUD_26M_CK 20 -+#define CLK_INFRA_AUD_L_CK 21 -+#define CLK_INFRA_AUD_AUD_CK 22 -+#define CLK_INFRA_AUD_EG2_CK 23 -+#define CLK_INFRA_DRAMC_26M_CK 24 -+#define CLK_INFRA_DBG_CK 25 -+#define CLK_INFRA_AP_DMA_CK 26 -+#define CLK_INFRA_SEJ_CK 27 -+#define CLK_INFRA_SEJ_13M_CK 28 -+#define CLK_INFRA_THERM_CK 29 -+#define CLK_INFRA_I2C0_CK 30 -+#define CLK_INFRA_UART0_CK 31 -+#define CLK_INFRA_UART1_CK 32 -+#define CLK_INFRA_UART2_CK 33 -+#define CLK_INFRA_SPI2_CK 34 -+#define CLK_INFRA_SPI2_HCK_CK 35 -+#define CLK_INFRA_NFI1_CK 36 -+#define CLK_INFRA_SPINFI1_CK 37 -+#define CLK_INFRA_NFI_HCK_CK 38 -+#define CLK_INFRA_SPI0_CK 39 -+#define CLK_INFRA_SPI1_CK 40 -+#define CLK_INFRA_SPI0_HCK_CK 41 -+#define CLK_INFRA_SPI1_HCK_CK 42 -+#define CLK_INFRA_FRTC_CK 43 -+#define CLK_INFRA_MSDC_CK 44 -+#define CLK_INFRA_MSDC_HCK_CK 45 -+#define CLK_INFRA_MSDC_133M_CK 46 -+#define CLK_INFRA_MSDC_66M_CK 47 -+#define CLK_INFRA_ADC_26M_CK 48 -+#define CLK_INFRA_ADC_FRC_CK 49 -+#define CLK_INFRA_FBIST2FPC_CK 50 -+#define CLK_INFRA_I2C_MCK_CK 51 -+#define CLK_INFRA_I2C_PCK_CK 52 -+#define CLK_INFRA_IUSB_133_CK 53 -+#define CLK_INFRA_IUSB_66M_CK 54 -+#define CLK_INFRA_IUSB_SYS_CK 55 -+#define CLK_INFRA_IUSB_CK 56 -+#define CLK_INFRA_IPCIE_CK 57 -+#define CLK_INFRA_IPCIE_PIPE_CK 58 -+#define CLK_INFRA_IPCIER_CK 59 -+#define CLK_INFRA_IPCIEB_CK 60 -+ -+/* APMIXEDSYS */ -+#define CLK_APMIXED_ARMPLL 0 -+#define CLK_APMIXED_NET2PLL 1 -+#define CLK_APMIXED_MMPLL 2 -+#define CLK_APMIXED_SGMPLL 3 -+#define CLK_APMIXED_WEDMCUPLL 4 -+#define CLK_APMIXED_NET1PLL 5 -+#define CLK_APMIXED_MPLL 6 -+#define CLK_APMIXED_APLL2 7 -+ -+/* SGMIISYS_0 */ -+#define CLK_SGM0_TX_EN 0 -+#define CLK_SGM0_RX_EN 1 -+#define CLK_SGM0_CK0_EN 2 -+#define CLK_SGM0_CDR_CK0_EN 3 -+ -+/* SGMIISYS_1 */ -+#define CLK_SGM1_TX_EN 0 -+#define CLK_SGM1_RX_EN 1 -+#define CLK_SGM1_CK1_EN 2 -+#define CLK_SGM1_CDR_CK1_EN 3 -+ -+/* ETHSYS */ -+#define CLK_ETH_FE_EN 0 -+#define CLK_ETH_GP2_EN 1 -+#define CLK_ETH_GP1_EN 2 -+#define CLK_ETH_WOCPU0_EN 3 -+ -+#endif /* _DT_BINDINGS_CLK_MT7981_H */ diff --git a/6.1/target/linux/mediatek/patches-6.1/231-v6.4-clk-mediatek-add-MT7981-clock-support.patch b/6.1/target/linux/mediatek/patches-6.1/231-v6.4-clk-mediatek-add-MT7981-clock-support.patch deleted file mode 100644 index f9dd94a7..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/231-v6.4-clk-mediatek-add-MT7981-clock-support.patch +++ /dev/null @@ -1,932 +0,0 @@ -From 8efeeb9c8b4ecf4fb4a74be9403aba951403bbaa Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Thu, 26 Jan 2023 03:34:24 +0000 -Subject: [PATCH] clk: mediatek: add MT7981 clock support - -Add MT7981 clock support, include topckgen, apmixedsys, infracfg and -ethernet subsystem clocks. - -The drivers are based on clk-mt7981.c which can be found in MediaTek's -SDK sources. To be fit for upstream inclusion the driver has been split -into clock domains and the infracfg part has been significantly -de-bloated by removing all the 1:1 factors (aliases). - -Signed-off-by: Jianhui Zhao -Signed-off-by: Daniel Golle -Link: https://lore.kernel.org/r/8136eb5b2049177bc2f6d3e0f2aefecc342d626f.1674703830.git.daniel@makrotopia.org -Reviewed-by: AngeloGioacchino Del Regno -[sboyd@kernel.org: Add module license] -Signed-off-by: Stephen Boyd ---- - drivers/clk/mediatek/Kconfig | 17 + - drivers/clk/mediatek/Makefile | 4 + - drivers/clk/mediatek/clk-mt7981-apmixed.c | 102 +++++ - drivers/clk/mediatek/clk-mt7981-eth.c | 118 ++++++ - drivers/clk/mediatek/clk-mt7981-infracfg.c | 207 ++++++++++ - drivers/clk/mediatek/clk-mt7981-topckgen.c | 422 +++++++++++++++++++++ - 6 files changed, 870 insertions(+) - create mode 100644 drivers/clk/mediatek/clk-mt7981-apmixed.c - create mode 100644 drivers/clk/mediatek/clk-mt7981-eth.c - create mode 100644 drivers/clk/mediatek/clk-mt7981-infracfg.c - create mode 100644 drivers/clk/mediatek/clk-mt7981-topckgen.c - ---- a/drivers/clk/mediatek/Kconfig -+++ b/drivers/clk/mediatek/Kconfig -@@ -381,6 +381,23 @@ config COMMON_CLK_MT7629_HIFSYS - This driver supports MediaTek MT7629 HIFSYS clocks providing - to PCI-E and USB. - -+config COMMON_CLK_MT7981 -+ bool "Clock driver for MediaTek MT7981" -+ depends on ARCH_MEDIATEK || COMPILE_TEST -+ select COMMON_CLK_MEDIATEK -+ default ARCH_MEDIATEK -+ help -+ This driver supports MediaTek MT7981 basic clocks and clocks -+ required for various peripherals found on this SoC. -+ -+config COMMON_CLK_MT7981_ETHSYS -+ tristate "Clock driver for MediaTek MT7981 ETHSYS" -+ depends on COMMON_CLK_MT7981 -+ default COMMON_CLK_MT7981 -+ help -+ This driver adds support for clocks for Ethernet and SGMII -+ required on MediaTek MT7981 SoC. -+ - config COMMON_CLK_MT7986 - bool "Clock driver for MediaTek MT7986" - depends on ARCH_MEDIATEK || COMPILE_TEST ---- a/drivers/clk/mediatek/Makefile -+++ b/drivers/clk/mediatek/Makefile -@@ -52,6 +52,10 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) + - obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o - obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o - obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o -+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-apmixed.o -+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-topckgen.o -+obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-infracfg.o -+obj-$(CONFIG_COMMON_CLK_MT7981_ETHSYS) += clk-mt7981-eth.o - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7981-apmixed.c -@@ -0,0 +1,102 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2021 MediaTek Inc. -+ * Author: Sam Shih -+ * Author: Wenzhen Yu -+ * Author: Jianhui Zhao -+ * Author: Daniel Golle -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "clk-gate.h" -+#include "clk-mtk.h" -+#include "clk-mux.h" -+#include "clk-pll.h" -+ -+#include -+#include -+ -+#define MT7981_PLL_FMAX (2500UL * MHZ) -+#define CON0_MT7981_RST_BAR BIT(27) -+ -+#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ -+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \ -+ _div_table, _parent_name) \ -+ { \ -+ .id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \ -+ .en_mask = _en_mask, .flags = _flags, \ -+ .rst_bar_mask = CON0_MT7981_RST_BAR, .fmax = MT7981_PLL_FMAX, \ -+ .pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \ -+ .tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg, \ -+ .pcw_shift = _pcw_shift, .div_table = _div_table, \ -+ .parent_name = _parent_name, \ -+ } -+ -+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ -+ _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) \ -+ PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ -+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \ -+ "clkxtal") -+ -+static const struct mtk_pll_data plls[] = { -+ PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO, -+ 32, 0x0200, 4, 0, 0x0204, 0), -+ PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32, -+ 0x0210, 4, 0, 0x0214, 0), -+ PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32, -+ 0x0220, 4, 0, 0x0224, 0), -+ PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32, -+ 0x0230, 4, 0, 0x0234, 0), -+ PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32, -+ 0x0240, 4, 0, 0x0244, 0), -+ PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025C, 0x00000001, 0, 32, -+ 0x0250, 4, 0, 0x0254, 0), -+ PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32, -+ 0x0260, 4, 0, 0x0264, 0), -+ PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32, -+ 0x0278, 4, 0, 0x027C, 0), -+}; -+ -+static const struct of_device_id of_match_clk_mt7981_apmixed[] = { -+ { .compatible = "mediatek,mt7981-apmixedsys", }, -+ { /* sentinel */ } -+}; -+ -+static int clk_mt7981_apmixed_probe(struct platform_device *pdev) -+{ -+ struct clk_hw_onecell_data *clk_data; -+ struct device_node *node = pdev->dev.of_node; -+ int r; -+ -+ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls)); -+ if (!clk_data) -+ return -ENOMEM; -+ -+ mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); -+ -+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -+ if (r) { -+ pr_err("%s(): could not register clock provider: %d\n", -+ __func__, r); -+ goto free_apmixed_data; -+ } -+ return r; -+ -+free_apmixed_data: -+ mtk_free_clk_data(clk_data); -+ return r; -+} -+ -+static struct platform_driver clk_mt7981_apmixed_drv = { -+ .probe = clk_mt7981_apmixed_probe, -+ .driver = { -+ .name = "clk-mt7981-apmixed", -+ .of_match_table = of_match_clk_mt7981_apmixed, -+ }, -+}; -+builtin_platform_driver(clk_mt7981_apmixed_drv); ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7981-eth.c -@@ -0,0 +1,118 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2021 MediaTek Inc. -+ * Author: Sam Shih -+ * Author: Wenzhen Yu -+ * Author: Jianhui Zhao -+ * Author: Daniel Golle -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "clk-mtk.h" -+#include "clk-gate.h" -+ -+#include -+ -+static const struct mtk_gate_regs sgmii0_cg_regs = { -+ .set_ofs = 0xE4, -+ .clr_ofs = 0xE4, -+ .sta_ofs = 0xE4, -+}; -+ -+#define GATE_SGMII0(_id, _name, _parent, _shift) { \ -+ .id = _id, \ -+ .name = _name, \ -+ .parent_name = _parent, \ -+ .regs = &sgmii0_cg_regs, \ -+ .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ -+ } -+ -+static const struct mtk_gate sgmii0_clks[] __initconst = { -+ GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "usb_tx250m", 2), -+ GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "usb_eq_rx250m", 3), -+ GATE_SGMII0(CLK_SGM0_CK0_EN, "sgm0_ck0_en", "usb_ln0", 4), -+ GATE_SGMII0(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", "usb_cdr", 5), -+}; -+ -+static const struct mtk_gate_regs sgmii1_cg_regs = { -+ .set_ofs = 0xE4, -+ .clr_ofs = 0xE4, -+ .sta_ofs = 0xE4, -+}; -+ -+#define GATE_SGMII1(_id, _name, _parent, _shift) { \ -+ .id = _id, \ -+ .name = _name, \ -+ .parent_name = _parent, \ -+ .regs = &sgmii1_cg_regs, \ -+ .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ -+ } -+ -+static const struct mtk_gate sgmii1_clks[] __initconst = { -+ GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "usb_tx250m", 2), -+ GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "usb_eq_rx250m", 3), -+ GATE_SGMII1(CLK_SGM1_CK1_EN, "sgm1_ck1_en", "usb_ln0", 4), -+ GATE_SGMII1(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", "usb_cdr", 5), -+}; -+ -+static const struct mtk_gate_regs eth_cg_regs = { -+ .set_ofs = 0x30, -+ .clr_ofs = 0x30, -+ .sta_ofs = 0x30, -+}; -+ -+#define GATE_ETH(_id, _name, _parent, _shift) { \ -+ .id = _id, \ -+ .name = _name, \ -+ .parent_name = _parent, \ -+ .regs = ð_cg_regs, \ -+ .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \ -+ } -+ -+static const struct mtk_gate eth_clks[] __initconst = { -+ GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x", 6), -+ GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m", 7), -+ GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m", 8), -+ GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_wed_mcu", 15), -+}; -+ -+static const struct mtk_clk_desc eth_desc = { -+ .clks = eth_clks, -+ .num_clks = ARRAY_SIZE(eth_clks), -+}; -+ -+static const struct mtk_clk_desc sgmii0_desc = { -+ .clks = sgmii0_clks, -+ .num_clks = ARRAY_SIZE(sgmii0_clks), -+}; -+ -+static const struct mtk_clk_desc sgmii1_desc = { -+ .clks = sgmii1_clks, -+ .num_clks = ARRAY_SIZE(sgmii1_clks), -+}; -+ -+static const struct of_device_id of_match_clk_mt7981_eth[] = { -+ { .compatible = "mediatek,mt7981-ethsys", .data = ð_desc }, -+ { .compatible = "mediatek,mt7981-sgmiisys_0", .data = &sgmii0_desc }, -+ { .compatible = "mediatek,mt7981-sgmiisys_1", .data = &sgmii1_desc }, -+ { /* sentinel */ } -+}; -+ -+static struct platform_driver clk_mt7981_eth_drv = { -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, -+ .driver = { -+ .name = "clk-mt7981-eth", -+ .of_match_table = of_match_clk_mt7981_eth, -+ }, -+}; -+module_platform_driver(clk_mt7981_eth_drv); -+MODULE_LICENSE("GPL v2"); ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7981-infracfg.c -@@ -0,0 +1,207 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2021 MediaTek Inc. -+ * Author: Sam Shih -+ * Author: Wenzhen Yu -+ * Author: Jianhui Zhao -+ * Author: Daniel Golle -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "clk-mtk.h" -+#include "clk-gate.h" -+#include "clk-mux.h" -+ -+#include -+#include -+ -+static DEFINE_SPINLOCK(mt7981_clk_lock); -+ -+static const struct mtk_fixed_factor infra_divs[] = { -+ FACTOR(CLK_INFRA_66M_MCK, "infra_66m_mck", "sysaxi_sel", 1, 2), -+}; -+ -+static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel", -+ "uart_sel" }; -+ -+static const char *const infra_spi0_parents[] __initconst = { "i2c_sel", -+ "spi_sel" }; -+ -+static const char *const infra_spi1_parents[] __initconst = { "i2c_sel", -+ "spim_mst_sel" }; -+ -+static const char *const infra_pwm1_parents[] __initconst = { "pwm_sel" }; -+ -+static const char *const infra_pwm_bsel_parents[] __initconst = { -+ "cb_rtc_32p7k", "csw_f26m_sel", "infra_66m_mck", "pwm_sel" -+}; -+ -+static const char *const infra_pcie_parents[] __initconst = { -+ "cb_rtc_32p7k", "csw_f26m_sel", "cb_cksq_40m", "pextp_tl_ck_sel" -+}; -+ -+static const struct mtk_mux infra_muxes[] = { -+ /* MODULE_CLK_SEL_0 */ -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel", -+ infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1, -+ -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel", -+ infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1, -+ -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel", -+ infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1, -+ -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel", -+ infra_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1, -+ -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel", -+ infra_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1, -+ -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI2_SEL, "infra_spi2_sel", -+ infra_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1, -+ -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel", -+ infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 9, 1, -+ -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel", -+ infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 11, 1, -+ -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM3_SEL, "infra_pwm3_sel", -+ infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 15, 1, -+ -1, -1, -1), -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel", -+ infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13, -+ 2, -1, -1, -1), -+ /* MODULE_CLK_SEL_1 */ -+ MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel", -+ infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2, -+ -1, -1, -1), -+}; -+ -+static const struct mtk_gate_regs infra0_cg_regs = { -+ .set_ofs = 0x40, -+ .clr_ofs = 0x44, -+ .sta_ofs = 0x48, -+}; -+ -+static const struct mtk_gate_regs infra1_cg_regs = { -+ .set_ofs = 0x50, -+ .clr_ofs = 0x54, -+ .sta_ofs = 0x58, -+}; -+ -+static const struct mtk_gate_regs infra2_cg_regs = { -+ .set_ofs = 0x60, -+ .clr_ofs = 0x64, -+ .sta_ofs = 0x68, -+}; -+ -+#define GATE_INFRA0(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .name = _name, .parent_name = _parent, \ -+ .regs = &infra0_cg_regs, .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_setclr, \ -+ } -+ -+#define GATE_INFRA1(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .name = _name, .parent_name = _parent, \ -+ .regs = &infra1_cg_regs, .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_setclr, \ -+ } -+ -+#define GATE_INFRA2(_id, _name, _parent, _shift) \ -+ { \ -+ .id = _id, .name = _name, .parent_name = _parent, \ -+ .regs = &infra2_cg_regs, .shift = _shift, \ -+ .ops = &mtk_clk_gate_ops_setclr, \ -+ } -+ -+static const struct mtk_gate infra_clks[] = { -+ /* INFRA0 */ -+ GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_66m_mck", 0), -+ GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_66m_mck", 1), -+ GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2), -+ GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3), -+ GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4), -+ GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi", 6), -+ -+ GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi", 8), -+ GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9), -+ GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l", 10), -+ GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys", 11), -+ GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner", 13), -+ GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel", -+ 14), -+ GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_66m_mck", 15), -+ GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_66m_mck", 16), -+ GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_66m_mck", 24), -+ GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25), -+ GATE_INFRA0(CLK_INFRA_PWM3_CK, "infra_pwm3", "infra_pwm3_sel", 27), -+ /* INFRA1 */ -+ GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0), -+ GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_bck", 1), -+ GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2), -+ GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3), -+ GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4), -+ GATE_INFRA1(CLK_INFRA_SPI2_CK, "infra_spi2", "infra_spi2_sel", 6), -+ GATE_INFRA1(CLK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", "infra_66m_mck", 7), -+ GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x", 8), -+ GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_bck", 9), -+ GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_66m_mck", 10), -+ GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11), -+ GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12), -+ GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_66m_mck", -+ 13), -+ GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_66m_mck", -+ 14), -+ GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "cb_rtc_32k", 15), -+ GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_400m", 16), -+ GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_208m", 17), -+ GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi", 18), -+ GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "sysaxi", 19), -+ GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20), -+ GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m", 21), -+ GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x", 23), -+ GATE_INFRA1(CLK_INFRA_I2C_MCK_CK, "infra_i2c_mck", "sysaxi", 25), -+ GATE_INFRA1(CLK_INFRA_I2C_PCK_CK, "infra_i2c_pck", "infra_66m_mck", 26), -+ /* INFRA2 */ -+ GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi", 0), -+ GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "sysaxi", 1), -+ GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys", 2), -+ GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_ref", 3), -+ GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl", 12), -+ GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "cb_cksq_40m", -+ 13), -+ GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m", 14), -+ GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi", 15), -+}; -+ -+static const struct mtk_clk_desc infracfg_desc = { -+ .factor_clks = infra_divs, -+ .num_factor_clks = ARRAY_SIZE(infra_divs), -+ .mux_clks = infra_muxes, -+ .num_mux_clks = ARRAY_SIZE(infra_muxes), -+ .clks = infra_clks, -+ .num_clks = ARRAY_SIZE(infra_clks), -+ .clk_lock = &mt7981_clk_lock, -+}; -+ -+static const struct of_device_id of_match_clk_mt7981_infracfg[] = { -+ { .compatible = "mediatek,mt7981-infracfg", .data = &infracfg_desc }, -+ { /* sentinel */ } -+}; -+ -+static struct platform_driver clk_mt7981_infracfg_drv = { -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, -+ .driver = { -+ .name = "clk-mt7981-infracfg", -+ .of_match_table = of_match_clk_mt7981_infracfg, -+ }, -+}; -+builtin_platform_driver(clk_mt7981_infracfg_drv); ---- /dev/null -+++ b/drivers/clk/mediatek/clk-mt7981-topckgen.c -@@ -0,0 +1,422 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2021 MediaTek Inc. -+ * Author: Sam Shih -+ * Author: Wenzhen Yu -+ * Author: Jianhui Zhao -+ */ -+ -+ -+#include -+#include -+#include -+#include -+#include -+#include "clk-mtk.h" -+#include "clk-gate.h" -+#include "clk-mux.h" -+ -+#include -+#include -+ -+static DEFINE_SPINLOCK(mt7981_clk_lock); -+ -+static const struct mtk_fixed_factor top_divs[] = { -+ FACTOR(CLK_TOP_CB_CKSQ_40M, "cb_cksq_40m", "clkxtal", 1, 1), -+ FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1), -+ FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2), -+ FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", "mpll", 1, 3), -+ FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2), -+ FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4), -+ FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8), -+ FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16), -+ FACTOR(CLK_TOP_CB_MM_720M, "cb_mm_720m", "mmpll", 1, 1), -+ FACTOR(CLK_TOP_CB_MM_D2, "cb_mm_d2", "mmpll", 1, 2), -+ FACTOR(CLK_TOP_CB_MM_D3, "cb_mm_d3", "mmpll", 1, 3), -+ FACTOR(CLK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", "mmpll", 1, 15), -+ FACTOR(CLK_TOP_CB_MM_D4, "cb_mm_d4", "mmpll", 1, 4), -+ FACTOR(CLK_TOP_CB_MM_D6, "cb_mm_d6", "mmpll", 1, 6), -+ FACTOR(CLK_TOP_MM_D6_D2, "mm_d6_d2", "mmpll", 1, 12), -+ FACTOR(CLK_TOP_CB_MM_D8, "cb_mm_d8", "mmpll", 1, 8), -+ FACTOR(CLK_TOP_CB_APLL2_196M, "cb_apll2_196m", "apll2", 1, 1), -+ FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2), -+ FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4), -+ FACTOR(CLK_TOP_NET1_2500M, "net1_2500m", "net1pll", 1, 1), -+ FACTOR(CLK_TOP_CB_NET1_D4, "cb_net1_d4", "net1pll", 1, 4), -+ FACTOR(CLK_TOP_CB_NET1_D5, "cb_net1_d5", "net1pll", 1, 5), -+ FACTOR(CLK_TOP_NET1_D5_D2, "net1_d5_d2", "net1pll", 1, 10), -+ FACTOR(CLK_TOP_NET1_D5_D4, "net1_d5_d4", "net1pll", 1, 20), -+ FACTOR(CLK_TOP_CB_NET1_D8, "cb_net1_d8", "net1pll", 1, 8), -+ FACTOR(CLK_TOP_NET1_D8_D2, "net1_d8_d2", "net1pll", 1, 16), -+ FACTOR(CLK_TOP_NET1_D8_D4, "net1_d8_d4", "net1pll", 1, 32), -+ FACTOR(CLK_TOP_CB_NET2_800M, "cb_net2_800m", "net2pll", 1, 1), -+ FACTOR(CLK_TOP_CB_NET2_D2, "cb_net2_d2", "net2pll", 1, 2), -+ FACTOR(CLK_TOP_CB_NET2_D4, "cb_net2_d4", "net2pll", 1, 4), -+ FACTOR(CLK_TOP_NET2_D4_D2, "net2_d4_d2", "net2pll", 1, 8), -+ FACTOR(CLK_TOP_NET2_D4_D4, "net2_d4_d4", "net2pll", 1, 16), -+ FACTOR(CLK_TOP_CB_NET2_D6, "cb_net2_d6", "net2pll", 1, 6), -+ FACTOR(CLK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m", "wedmcupll", 1, 1), -+ FACTOR(CLK_TOP_CB_SGM_325M, "cb_sgm_325m", "sgmpll", 1, 1), -+ FACTOR(CLK_TOP_CKSQ_40M_D2, "cksq_40m_d2", "cb_cksq_40m", 1, 2), -+ FACTOR(CLK_TOP_CB_RTC_32K, "cb_rtc_32k", "cb_cksq_40m", 1, 1250), -+ FACTOR(CLK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", "cb_cksq_40m", 1, 1220), -+ FACTOR(CLK_TOP_USB_TX250M, "usb_tx250m", "cb_cksq_40m", 1, 1), -+ FACTOR(CLK_TOP_FAUD, "faud", "aud_sel", 1, 1), -+ FACTOR(CLK_TOP_NFI1X, "nfi1x", "nfi1x_sel", 1, 1), -+ FACTOR(CLK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", "cb_cksq_40m", 1, 1), -+ FACTOR(CLK_TOP_USB_CDR_CK, "usb_cdr", "cb_cksq_40m", 1, 1), -+ FACTOR(CLK_TOP_USB_LN0_CK, "usb_ln0", "cb_cksq_40m", 1, 1), -+ FACTOR(CLK_TOP_SPINFI_BCK, "spinfi_bck", "spinfi_sel", 1, 1), -+ FACTOR(CLK_TOP_SPI, "spi", "spi_sel", 1, 1), -+ FACTOR(CLK_TOP_SPIM_MST, "spim_mst", "spim_mst_sel", 1, 1), -+ FACTOR(CLK_TOP_UART_BCK, "uart_bck", "uart_sel", 1, 1), -+ FACTOR(CLK_TOP_PWM_BCK, "pwm_bck", "pwm_sel", 1, 1), -+ FACTOR(CLK_TOP_I2C_BCK, "i2c_bck", "i2c_sel", 1, 1), -+ FACTOR(CLK_TOP_PEXTP_TL, "pextp_tl", "pextp_tl_ck_sel", 1, 1), -+ FACTOR(CLK_TOP_EMMC_208M, "emmc_208m", "emmc_208m_sel", 1, 1), -+ FACTOR(CLK_TOP_EMMC_400M, "emmc_400m", "emmc_400m_sel", 1, 1), -+ FACTOR(CLK_TOP_DRAMC_REF, "dramc_ref", "dramc_sel", 1, 1), -+ FACTOR(CLK_TOP_DRAMC_MD32, "dramc_md32", "dramc_md32_sel", 1, 1), -+ FACTOR(CLK_TOP_SYSAXI, "sysaxi", "sysaxi_sel", 1, 1), -+ FACTOR(CLK_TOP_SYSAPB, "sysapb", "sysapb_sel", 1, 1), -+ FACTOR(CLK_TOP_ARM_DB_MAIN, "arm_db_main", "arm_db_main_sel", 1, 1), -+ FACTOR(CLK_TOP_AP2CNN_HOST, "ap2cnn_host", "ap2cnn_host_sel", 1, 1), -+ FACTOR(CLK_TOP_NETSYS, "netsys", "netsys_sel", 1, 1), -+ FACTOR(CLK_TOP_NETSYS_500M, "netsys_500m", "netsys_500m_sel", 1, 1), -+ FACTOR(CLK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu", "netsys_mcu_sel", 1, 1), -+ FACTOR(CLK_TOP_NETSYS_2X, "netsys_2x", "netsys_2x_sel", 1, 1), -+ FACTOR(CLK_TOP_SGM_325M, "sgm_325m", "sgm_325m_sel", 1, 1), -+ FACTOR(CLK_TOP_SGM_REG, "sgm_reg", "sgm_reg_sel", 1, 1), -+ FACTOR(CLK_TOP_F26M, "csw_f26m", "csw_f26m_sel", 1, 1), -+ FACTOR(CLK_TOP_EIP97B, "eip97b", "eip97b_sel", 1, 1), -+ FACTOR(CLK_TOP_USB3_PHY, "usb3_phy", "usb3_phy_sel", 1, 1), -+ FACTOR(CLK_TOP_AUD, "aud", "faud", 1, 1), -+ FACTOR(CLK_TOP_A1SYS, "a1sys", "a1sys_sel", 1, 1), -+ FACTOR(CLK_TOP_AUD_L, "aud_l", "aud_l_sel", 1, 1), -+ FACTOR(CLK_TOP_A_TUNER, "a_tuner", "a_tuner_sel", 1, 1), -+ FACTOR(CLK_TOP_U2U3_REF, "u2u3_ref", "u2u3_sel", 1, 1), -+ FACTOR(CLK_TOP_U2U3_SYS, "u2u3_sys", "u2u3_sys_sel", 1, 1), -+ FACTOR(CLK_TOP_U2U3_XHCI, "u2u3_xhci", "u2u3_xhci_sel", 1, 1), -+ FACTOR(CLK_TOP_USB_FRMCNT, "usb_frmcnt", "usb_frmcnt_sel", 1, 1), -+}; -+ -+static const char * const nfi1x_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_mm_d4", -+ "net1_d8_d2", -+ "cb_net2_d6", -+ "cb_m_d4", -+ "cb_mm_d8", -+ "net1_d8_d4", -+ "cb_m_d8" -+}; -+ -+static const char * const spinfi_parents[] __initconst = { -+ "cksq_40m_d2", -+ "cb_cksq_40m", -+ "net1_d5_d4", -+ "cb_m_d4", -+ "cb_mm_d8", -+ "net1_d8_d4", -+ "mm_d6_d2", -+ "cb_m_d8" -+}; -+ -+static const char * const spi_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_m_d2", -+ "cb_mm_d4", -+ "net1_d8_d2", -+ "cb_net2_d6", -+ "net1_d5_d4", -+ "cb_m_d4", -+ "net1_d8_d4" -+}; -+ -+static const char * const uart_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_m_d8", -+ "m_d8_d2" -+}; -+ -+static const char * const pwm_parents[] __initconst = { -+ "cb_cksq_40m", -+ "net1_d8_d2", -+ "net1_d5_d4", -+ "cb_m_d4", -+ "m_d8_d2", -+ "cb_rtc_32k" -+}; -+ -+static const char * const i2c_parents[] __initconst = { -+ "cb_cksq_40m", -+ "net1_d5_d4", -+ "cb_m_d4", -+ "net1_d8_d4" -+}; -+ -+static const char * const pextp_tl_ck_parents[] __initconst = { -+ "cb_cksq_40m", -+ "net1_d5_d4", -+ "cb_m_d4", -+ "cb_rtc_32k" -+}; -+ -+static const char * const emmc_208m_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_m_d2", -+ "cb_net2_d4", -+ "cb_apll2_196m", -+ "cb_mm_d4", -+ "net1_d8_d2", -+ "cb_mm_d6" -+}; -+ -+static const char * const emmc_400m_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_net2_d2", -+ "cb_mm_d2", -+ "cb_net2_d2" -+}; -+ -+static const char * const csw_f26m_parents[] __initconst = { -+ "cksq_40m_d2", -+ "m_d8_d2" -+}; -+ -+static const char * const dramc_md32_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_m_d2", -+ "cb_wedmcu_208m" -+}; -+ -+static const char * const sysaxi_parents[] __initconst = { -+ "cb_cksq_40m", -+ "net1_d8_d2" -+}; -+ -+static const char * const sysapb_parents[] __initconst = { -+ "cb_cksq_40m", -+ "m_d3_d2" -+}; -+ -+static const char * const arm_db_main_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_net2_d6" -+}; -+ -+static const char * const ap2cnn_host_parents[] __initconst = { -+ "cb_cksq_40m", -+ "net1_d8_d4" -+}; -+ -+static const char * const netsys_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_mm_d2" -+}; -+ -+static const char * const netsys_500m_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_net1_d5" -+}; -+ -+static const char * const netsys_mcu_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_mm_720m", -+ "cb_net1_d4", -+ "cb_net1_d5", -+ "cb_m_416m" -+}; -+ -+static const char * const netsys_2x_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_net2_800m", -+ "cb_mm_720m" -+}; -+ -+static const char * const sgm_325m_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_sgm_325m" -+}; -+ -+static const char * const sgm_reg_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_net2_d4" -+}; -+ -+static const char * const eip97b_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_net1_d5", -+ "cb_m_416m", -+ "cb_mm_d2", -+ "net1_d5_d2" -+}; -+ -+static const char * const aud_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_apll2_196m" -+}; -+ -+static const char * const a1sys_parents[] __initconst = { -+ "cb_cksq_40m", -+ "apll2_d4" -+}; -+ -+static const char * const aud_l_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_apll2_196m", -+ "m_d8_d2" -+}; -+ -+static const char * const a_tuner_parents[] __initconst = { -+ "cb_cksq_40m", -+ "apll2_d4", -+ "m_d8_d2" -+}; -+ -+static const char * const u2u3_parents[] __initconst = { -+ "cb_cksq_40m", -+ "m_d8_d2" -+}; -+ -+static const char * const u2u3_sys_parents[] __initconst = { -+ "cb_cksq_40m", -+ "net1_d5_d4" -+}; -+ -+static const char * const usb_frmcnt_parents[] __initconst = { -+ "cb_cksq_40m", -+ "cb_mm_d3_d5" -+}; -+ -+static const struct mtk_mux top_muxes[] = { -+ /* CLK_CFG_0 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, -+ 0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, -+ 0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, -+ 0x000, 0x004, 0x008, 16, 3, 23, 0x1C0, 2), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, -+ 0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3), -+ /* CLK_CFG_1 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, -+ 0x010, 0x014, 0x018, 0, 2, 7, 0x1C0, 4), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, -+ 0x010, 0x014, 0x018, 8, 3, 15, 0x1C0, 5), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, -+ 0x010, 0x014, 0x018, 16, 2, 23, 0x1C0, 6), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", -+ pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2, 31, -+ 0x1C0, 7), -+ /* CLK_CFG_2 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_208M_SEL, "emmc_208m_sel", -+ emmc_208m_parents, 0x020, 0x024, 0x028, 0, 3, 7, -+ 0x1C0, 8), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel", -+ emmc_400m_parents, 0x020, 0x024, 0x028, 8, 2, 15, -+ 0x1C0, 9), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel", -+ csw_f26m_parents, 0x020, 0x024, 0x028, 16, 1, 23, -+ 0x1C0, 10, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel", -+ csw_f26m_parents, 0x020, 0x024, 0x028, 24, 1, -+ 31, 0x1C0, 11, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), -+ /* CLK_CFG_3 */ -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", -+ dramc_md32_parents, 0x030, 0x034, 0x038, 0, 2, -+ 7, 0x1C0, 12, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", -+ sysaxi_parents, 0x030, 0x034, 0x038, 8, 1, 15, -+ 0x1C0, 13, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), -+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel", -+ sysapb_parents, 0x030, 0x034, 0x038, 16, 1, -+ 23, 0x1C0, 14, -+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", -+ arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1, 31, -+ 0x1C0, 15), -+ /* CLK_CFG_4 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", -+ ap2cnn_host_parents, 0x040, 0x044, 0x048, 0, 1, 7, -+ 0x1C0, 16), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, -+ 0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", -+ netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1, 23, -+ 0x1C0, 18), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", -+ netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31, -+ 0x1C0, 19), -+ /* CLK_CFG_5 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", -+ netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7, -+ 0x1C0, 20), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel", -+ sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15, -+ 0x1C0, 21), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, -+ 0x050, 0x054, 0x058, 16, 1, 23, 0x1C0, 22), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents, -+ 0x050, 0x054, 0x058, 24, 3, 31, 0x1C0, 23), -+ /* CLK_CFG_6 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel", -+ csw_f26m_parents, 0x060, 0x064, 0x068, 0, 1, -+ 7, 0x1C0, 24), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x060, -+ 0x064, 0x068, 8, 1, 15, 0x1C0, 25), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, -+ 0x060, 0x064, 0x068, 16, 1, 23, 0x1C0, 26), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, -+ 0x060, 0x064, 0x068, 24, 2, 31, 0x1C0, 27), -+ /* CLK_CFG_7 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", -+ a_tuner_parents, 0x070, 0x074, 0x078, 0, 2, 7, -+ 0x1C0, 28), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x070, -+ 0x074, 0x078, 8, 1, 15, 0x1C0, 29), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", -+ u2u3_sys_parents, 0x070, 0x074, 0x078, 16, 1, 23, -+ 0x1C0, 30), -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", -+ u2u3_sys_parents, 0x070, 0x074, 0x078, 24, 1, 31, -+ 0x1C4, 0), -+ /* CLK_CFG_8 */ -+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", -+ usb_frmcnt_parents, 0x080, 0x084, 0x088, 0, 1, 7, -+ 0x1C4, 1), -+}; -+ -+static struct mtk_composite top_aud_divs[] = { -+ DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud", -+ 0x0420, 0, 0x0420, 8, 8), -+}; -+ -+static const struct mtk_clk_desc topck_desc = { -+ .factor_clks = top_divs, -+ .num_factor_clks = ARRAY_SIZE(top_divs), -+ .mux_clks = top_muxes, -+ .num_mux_clks = ARRAY_SIZE(top_muxes), -+ .composite_clks = top_aud_divs, -+ .num_composite_clks = ARRAY_SIZE(top_aud_divs), -+ .clk_lock = &mt7981_clk_lock, -+}; -+ -+static const struct of_device_id of_match_clk_mt7981_topckgen[] = { -+ { .compatible = "mediatek,mt7981-topckgen", .data = &topck_desc }, -+ { /* sentinel */ } -+}; -+ -+static struct platform_driver clk_mt7981_topckgen_drv = { -+ .probe = mtk_clk_simple_probe, -+ .remove = mtk_clk_simple_remove, -+ .driver = { -+ .name = "clk-mt7981-topckgen", -+ .of_match_table = of_match_clk_mt7981_topckgen, -+ }, -+}; -+builtin_platform_driver(clk_mt7981_topckgen_drv); diff --git a/6.1/target/linux/mediatek/patches-6.1/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch b/6.1/target/linux/mediatek/patches-6.1/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch deleted file mode 100644 index a365f086..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/240-pinctrl-mediatek-add-support-for-MT7988-SoC.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/pinctrl/mediatek/Kconfig -+++ b/drivers/pinctrl/mediatek/Kconfig -@@ -141,6 +141,13 @@ config PINCTRL_MT7986 - default ARM64 && ARCH_MEDIATEK - select PINCTRL_MTK_MOORE - -+config PINCTRL_MT7988 -+ bool "Mediatek MT7988 pin control" -+ depends on OF -+ depends on ARM64 || COMPILE_TEST -+ default ARCH_MEDIATEK -+ select PINCTRL_MTK_MOORE -+ - config PINCTRL_MT8167 - bool "Mediatek MT8167 pin control" - depends on OF ---- a/drivers/pinctrl/mediatek/Makefile -+++ b/drivers/pinctrl/mediatek/Makefile -@@ -20,6 +20,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl- - obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o - obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o - obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o -+obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o - obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o - obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o - obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o diff --git a/6.1/target/linux/mediatek/patches-6.1/241-clk-mediatek-Add-pcw-chg-shift-control.patch b/6.1/target/linux/mediatek/patches-6.1/241-clk-mediatek-Add-pcw-chg-shift-control.patch deleted file mode 100644 index 75ca114a..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/241-clk-mediatek-Add-pcw-chg-shift-control.patch +++ /dev/null @@ -1,24 +0,0 @@ ---- a/drivers/clk/mediatek/clk-pll.c -+++ b/drivers/clk/mediatek/clk-pll.c -@@ -141,7 +141,10 @@ static void mtk_pll_set_rate_regs(struct - pll->data->pcw_shift); - val |= pcw << pll->data->pcw_shift; - writel(val, pll->pcw_addr); -- chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; -+ if (pll->data->pcw_chg_shift) -+ chg = readl(pll->pcw_chg_addr) | BIT(pll->data->pcw_chg_shift); -+ else -+ chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK; - writel(chg, pll->pcw_chg_addr); - if (pll->tuner_addr) - writel(val + 1, pll->tuner_addr); ---- a/drivers/clk/mediatek/clk-pll.h -+++ b/drivers/clk/mediatek/clk-pll.h -@@ -42,6 +42,7 @@ struct mtk_pll_data { - u32 pcw_reg; - int pcw_shift; - u32 pcw_chg_reg; -+ int pcw_chg_shift; - const struct mtk_pll_div_table *div_table; - const char *parent_name; - u32 en_reg; diff --git a/6.1/target/linux/mediatek/patches-6.1/242-clk-mediatek-add-mt7988-clock-support.patch b/6.1/target/linux/mediatek/patches-6.1/242-clk-mediatek-add-mt7988-clock-support.patch deleted file mode 100644 index 3ced0124..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/242-clk-mediatek-add-mt7988-clock-support.patch +++ /dev/null @@ -1,31 +0,0 @@ ---- a/drivers/clk/mediatek/Kconfig -+++ b/drivers/clk/mediatek/Kconfig -@@ -415,6 +415,15 @@ config COMMON_CLK_MT7986_ETHSYS - This driver adds support for clocks for Ethernet and SGMII - required on MediaTek MT7986 SoC. - -+config COMMON_CLK_MT7988 -+ bool "Clock driver for MediaTek MT7988" -+ depends on ARCH_MEDIATEK || COMPILE_TEST -+ select COMMON_CLK_MEDIATEK -+ default ARCH_MEDIATEK -+ help -+ This driver supports MediaTek MT7988 basic clocks and clocks -+ required for various periperals found on MediaTek. -+ - config COMMON_CLK_MT8135 - bool "Clock driver for MediaTek MT8135" - depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST ---- a/drivers/clk/mediatek/Makefile -+++ b/drivers/clk/mediatek/Makefile -@@ -60,6 +60,10 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-m - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o - obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o - obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o -+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-apmixed.o -+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o -+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o -+obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-eth.o - obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o - obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o - obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o diff --git a/6.1/target/linux/mediatek/patches-6.1/320-v6.2-mmc-mediatek-add-support-for-MT7986-SoC.patch b/6.1/target/linux/mediatek/patches-6.1/320-v6.2-mmc-mediatek-add-support-for-MT7986-SoC.patch deleted file mode 100644 index 5e3afd85..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/320-v6.2-mmc-mediatek-add-support-for-MT7986-SoC.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 24e961b93d292d0dd6380213d22a071a99ea787d Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Tue, 25 Oct 2022 15:29:53 +0200 -Subject: [PATCH 1/6] mmc: mediatek: add support for MT7986 SoC - -Adding mt7986 own characteristics and of_device_id to have support -of MT7986 SoC. - -Signed-off-by: Sam Shih -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20221025132953.81286-7-linux@fw-web.de -Signed-off-by: Ulf Hansson ---- - drivers/mmc/host/mtk-sd.c | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/drivers/mmc/host/mtk-sd.c -+++ b/drivers/mmc/host/mtk-sd.c -@@ -552,6 +552,19 @@ static const struct mtk_mmc_compatible m - .support_64g = false, - }; - -+static const struct mtk_mmc_compatible mt7986_compat = { -+ .clk_div_bits = 12, -+ .recheck_sdio_irq = true, -+ .hs400_tune = false, -+ .pad_tune_reg = MSDC_PAD_TUNE0, -+ .async_fifo = true, -+ .data_tune = true, -+ .busy_check = true, -+ .stop_clk_fix = true, -+ .enhance_rx = true, -+ .support_64g = true, -+}; -+ - static const struct mtk_mmc_compatible mt8135_compat = { - .clk_div_bits = 8, - .recheck_sdio_irq = true, -@@ -609,6 +622,7 @@ static const struct of_device_id msdc_of - { .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat}, - { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, - { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, -+ { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat}, - { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, - { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, - { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, diff --git a/6.1/target/linux/mediatek/patches-6.1/321-v6.2-mmc-mtk-sd-add-Inline-Crypto-Engine-clock-control.patch b/6.1/target/linux/mediatek/patches-6.1/321-v6.2-mmc-mtk-sd-add-Inline-Crypto-Engine-clock-control.patch deleted file mode 100644 index aaea33c3..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/321-v6.2-mmc-mtk-sd-add-Inline-Crypto-Engine-clock-control.patch +++ /dev/null @@ -1,57 +0,0 @@ -From 7b438d0377fbd520b475a68bdd9de1692393f22d Mon Sep 17 00:00:00 2001 -From: Mengqi Zhang -Date: Sun, 6 Nov 2022 11:39:24 +0800 -Subject: [PATCH 2/6] mmc: mtk-sd: add Inline Crypto Engine clock control - -Add crypto clock control and ungate it before CQHCI init. - -Signed-off-by: Mengqi Zhang -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20221106033924.9854-2-mengqi.zhang@mediatek.com -Signed-off-by: Ulf Hansson ---- - drivers/mmc/host/mtk-sd.c | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - ---- a/drivers/mmc/host/mtk-sd.c -+++ b/drivers/mmc/host/mtk-sd.c -@@ -452,6 +452,7 @@ struct msdc_host { - struct clk *bus_clk; /* bus clock which used to access register */ - struct clk *src_clk_cg; /* msdc source clock control gate */ - struct clk *sys_clk_cg; /* msdc subsys clock control gate */ -+ struct clk *crypto_clk; /* msdc crypto clock control gate */ - struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS]; - u32 mclk; /* mmc subsystem clock frequency */ - u32 src_clk_freq; /* source clock frequency */ -@@ -840,6 +841,7 @@ static void msdc_set_busy_timeout(struct - static void msdc_gate_clock(struct msdc_host *host) - { - clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); -+ clk_disable_unprepare(host->crypto_clk); - clk_disable_unprepare(host->src_clk_cg); - clk_disable_unprepare(host->src_clk); - clk_disable_unprepare(host->bus_clk); -@@ -855,6 +857,7 @@ static int msdc_ungate_clock(struct msdc - clk_prepare_enable(host->bus_clk); - clk_prepare_enable(host->src_clk); - clk_prepare_enable(host->src_clk_cg); -+ clk_prepare_enable(host->crypto_clk); - ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); - if (ret) { - dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); -@@ -2670,6 +2673,15 @@ static int msdc_drv_probe(struct platfor - goto host_free; - } - -+ /* only eMMC has crypto property */ -+ if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) { -+ host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto"); -+ if (IS_ERR(host->crypto_clk)) -+ host->crypto_clk = NULL; -+ else -+ mmc->caps2 |= MMC_CAP2_CRYPTO; -+ } -+ - host->irq = platform_get_irq(pdev, 0); - if (host->irq < 0) { - ret = -EINVAL; diff --git a/6.1/target/linux/mediatek/patches-6.1/322-v6.2-mmc-mtk-sd-fix-two-spelling-mistakes-in-comment.patch b/6.1/target/linux/mediatek/patches-6.1/322-v6.2-mmc-mtk-sd-fix-two-spelling-mistakes-in-comment.patch deleted file mode 100644 index 921d249f..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/322-v6.2-mmc-mtk-sd-fix-two-spelling-mistakes-in-comment.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 4b323f02b6e8df1b04292635ef829e7f723bf50e Mon Sep 17 00:00:00 2001 -From: Yu Zhe -Date: Thu, 10 Nov 2022 15:28:19 +0800 -Subject: [PATCH 3/6] mmc: mtk-sd: fix two spelling mistakes in comment - -spelling mistake fix : "alreay" -> "already" - "checksume" -> "checksum" - -Signed-off-by: Yu Zhe -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20221110072819.11530-1-yuzhe@nfschina.com -Signed-off-by: Ulf Hansson ---- - drivers/mmc/host/mtk-sd.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - ---- a/drivers/mmc/host/mtk-sd.c -+++ b/drivers/mmc/host/mtk-sd.c -@@ -750,7 +750,7 @@ static inline void msdc_dma_setup(struct - else - bd[j].bd_info &= ~BDMA_DESC_EOL; - -- /* checksume need to clear first */ -+ /* checksum need to clear first */ - bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; - bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; - } -@@ -1229,7 +1229,7 @@ static bool msdc_cmd_done(struct msdc_ho - !host->hs400_tuning)) - /* - * should not clear fifo/interrupt as the tune data -- * may have alreay come when cmd19/cmd21 gets response -+ * may have already come when cmd19/cmd21 gets response - * CRC error. - */ - msdc_reset_hw(host); diff --git a/6.1/target/linux/mediatek/patches-6.1/323-v6.2-mmc-Avoid-open-coding-by-using-mmc_op_tuning.patch b/6.1/target/linux/mediatek/patches-6.1/323-v6.2-mmc-Avoid-open-coding-by-using-mmc_op_tuning.patch deleted file mode 100644 index 8e2151e1..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/323-v6.2-mmc-Avoid-open-coding-by-using-mmc_op_tuning.patch +++ /dev/null @@ -1,39 +0,0 @@ -From b98e7e8daf0ebab9dcc36812378a71e1be0b5089 Mon Sep 17 00:00:00 2001 -From: ChanWoo Lee -Date: Thu, 24 Nov 2022 17:00:31 +0900 -Subject: [PATCH 4/6] mmc: Avoid open coding by using mmc_op_tuning() - -Replace code with the already defined function. No functional changes. - -Signed-off-by: ChanWoo Lee -Reviewed-by: Adrian Hunter -Link: https://lore.kernel.org/r/20221124080031.14690-1-cw9316.lee@samsung.com -Signed-off-by: Ulf Hansson ---- - drivers/mmc/host/mtk-sd.c | 8 ++------ - 1 file changed, 2 insertions(+), 6 deletions(-) - ---- a/drivers/mmc/host/mtk-sd.c -+++ b/drivers/mmc/host/mtk-sd.c -@@ -1224,9 +1224,7 @@ static bool msdc_cmd_done(struct msdc_ho - - if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { - if (events & MSDC_INT_CMDTMO || -- (cmd->opcode != MMC_SEND_TUNING_BLOCK && -- cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200 && -- !host->hs400_tuning)) -+ (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning)) - /* - * should not clear fifo/interrupt as the tune data - * may have already come when cmd19/cmd21 gets response -@@ -1320,9 +1318,7 @@ static void msdc_cmd_next(struct msdc_ho - { - if ((cmd->error && - !(cmd->error == -EILSEQ && -- (cmd->opcode == MMC_SEND_TUNING_BLOCK || -- cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200 || -- host->hs400_tuning))) || -+ (mmc_op_tuning(cmd->opcode) || host->hs400_tuning))) || - (mrq->sbc && mrq->sbc->error)) - msdc_request_done(host, mrq); - else if (cmd == mrq->sbc) diff --git a/6.1/target/linux/mediatek/patches-6.1/330-snand-mtk-bmt-support.patch b/6.1/target/linux/mediatek/patches-6.1/330-snand-mtk-bmt-support.patch deleted file mode 100644 index 55a308e4..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/330-snand-mtk-bmt-support.patch +++ /dev/null @@ -1,34 +0,0 @@ ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -19,6 +19,7 @@ - #include - #include - #include -+#include - - static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val) - { -@@ -1344,6 +1345,7 @@ static int spinand_probe(struct spi_mem - if (ret) - return ret; - -+ mtk_bmt_attach(mtd); - ret = mtd_device_register(mtd, NULL, 0); - if (ret) - goto err_spinand_cleanup; -@@ -1351,6 +1353,7 @@ static int spinand_probe(struct spi_mem - return 0; - - err_spinand_cleanup: -+ mtk_bmt_detach(mtd); - spinand_cleanup(spinand); - - return ret; -@@ -1369,6 +1372,7 @@ static int spinand_remove(struct spi_mem - if (ret) - return ret; - -+ mtk_bmt_detach(mtd); - spinand_cleanup(spinand); - - return 0; diff --git a/6.1/target/linux/mediatek/patches-6.1/331-mt7622-rfb1-enable-bmt.patch b/6.1/target/linux/mediatek/patches-6.1/331-mt7622-rfb1-enable-bmt.patch deleted file mode 100644 index 662515f2..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/331-mt7622-rfb1-enable-bmt.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts -@@ -552,6 +552,7 @@ - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - nand-ecc-engine = <&snfi>; -+ mediatek,bmt-v2; - - partitions { - compatible = "fixed-partitions"; diff --git a/6.1/target/linux/mediatek/patches-6.1/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch b/6.1/target/linux/mediatek/patches-6.1/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch deleted file mode 100644 index ec66363d..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/340-mtd-spinand-Add-support-for-the-Fidelix-FM35X1GA.patch +++ /dev/null @@ -1,122 +0,0 @@ -From 5f49a5c9b16330e0df8f639310e4715dcad71947 Mon Sep 17 00:00:00 2001 -From: Davide Fioravanti -Date: Fri, 8 Jan 2021 15:35:24 +0100 -Subject: [PATCH] mtd: spinand: Add support for the Fidelix FM35X1GA - -Datasheet: http://www.hobos.com.cn/upload/datasheet/DS35X1GAXXX_100_rev00.pdf - -Signed-off-by: Davide Fioravanti ---- - drivers/mtd/nand/spi/Makefile | 2 +- - drivers/mtd/nand/spi/core.c | 1 + - drivers/mtd/nand/spi/fidelix.c | 76 ++++++++++++++++++++++++++++++++++ - include/linux/mtd/spinand.h | 1 + - 4 files changed, 79 insertions(+), 1 deletion(-) - create mode 100644 drivers/mtd/nand/spi/fidelix.c - ---- a/drivers/mtd/nand/spi/Makefile -+++ b/drivers/mtd/nand/spi/Makefile -@@ -1,3 +1,3 @@ - # SPDX-License-Identifier: GPL-2.0 --spinand-objs := core.o ato.o esmt.o etron.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o -+spinand-objs := core.o ato.o esmt.o etron.o fidelix.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o - obj-$(CONFIG_MTD_SPI_NAND) += spinand.o ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -940,6 +940,7 @@ static const struct nand_ops spinand_ops - static const struct spinand_manufacturer *spinand_manufacturers[] = { - &ato_spinand_manufacturer, - &esmt_c8_spinand_manufacturer, -+ &fidelix_spinand_manufacturer, - &etron_spinand_manufacturer, - &gigadevice_spinand_manufacturer, - ¯onix_spinand_manufacturer, ---- /dev/null -+++ b/drivers/mtd/nand/spi/fidelix.c -@@ -0,0 +1,76 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Copyright (c) 2020 Davide Fioravanti -+ */ -+ -+#include -+#include -+#include -+ -+#define SPINAND_MFR_FIDELIX 0xE5 -+#define FIDELIX_ECCSR_MASK 0x0F -+ -+static SPINAND_OP_VARIANTS(read_cache_variants, -+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), -+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); -+ -+static SPINAND_OP_VARIANTS(write_cache_variants, -+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), -+ SPINAND_PROG_LOAD(true, 0, NULL, 0)); -+ -+static SPINAND_OP_VARIANTS(update_cache_variants, -+ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), -+ SPINAND_PROG_LOAD(false, 0, NULL, 0)); -+ -+static int fm35x1ga_ooblayout_ecc(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *region) -+{ -+ if (section > 3) -+ return -ERANGE; -+ -+ region->offset = (16 * section) + 8; -+ region->length = 8; -+ -+ return 0; -+} -+ -+static int fm35x1ga_ooblayout_free(struct mtd_info *mtd, int section, -+ struct mtd_oob_region *region) -+{ -+ if (section > 3) -+ return -ERANGE; -+ -+ region->offset = (16 * section) + 2; -+ region->length = 6; -+ -+ return 0; -+} -+ -+static const struct mtd_ooblayout_ops fm35x1ga_ooblayout = { -+ .ecc = fm35x1ga_ooblayout_ecc, -+ .free = fm35x1ga_ooblayout_free, -+}; -+ -+static const struct spinand_info fidelix_spinand_table[] = { -+ SPINAND_INFO("FM35X1GA", -+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71), -+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), -+ NAND_ECCREQ(4, 512), -+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, -+ &write_cache_variants, -+ &update_cache_variants), -+ SPINAND_HAS_QE_BIT, -+ SPINAND_ECCINFO(&fm35x1ga_ooblayout, NULL)), -+}; -+ -+static const struct spinand_manufacturer_ops fidelix_spinand_manuf_ops = { -+}; -+ -+const struct spinand_manufacturer fidelix_spinand_manufacturer = { -+ .id = SPINAND_MFR_FIDELIX, -+ .name = "Fidelix", -+ .chips = fidelix_spinand_table, -+ .nchips = ARRAY_SIZE(fidelix_spinand_table), -+ .ops = &fidelix_spinand_manuf_ops, -+}; ---- a/include/linux/mtd/spinand.h -+++ b/include/linux/mtd/spinand.h -@@ -263,6 +263,7 @@ struct spinand_manufacturer { - extern const struct spinand_manufacturer ato_spinand_manufacturer; - extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer; - extern const struct spinand_manufacturer etron_spinand_manufacturer; -+extern const struct spinand_manufacturer fidelix_spinand_manufacturer; - extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; - extern const struct spinand_manufacturer macronix_spinand_manufacturer; - extern const struct spinand_manufacturer micron_spinand_manufacturer; diff --git a/6.1/target/linux/mediatek/patches-6.1/400-crypto-add-eip97-inside-secure-support.patch b/6.1/target/linux/mediatek/patches-6.1/400-crypto-add-eip97-inside-secure-support.patch deleted file mode 100644 index 25ca9485..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/400-crypto-add-eip97-inside-secure-support.patch +++ /dev/null @@ -1,27 +0,0 @@ ---- a/drivers/crypto/inside-secure/safexcel.c -+++ b/drivers/crypto/inside-secure/safexcel.c -@@ -600,6 +600,14 @@ static int safexcel_hw_init(struct safex - val |= EIP197_MST_CTRL_TX_MAX_CMD(5); - writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL); - } -+ /* -+ * Set maximum number of TX commands to 2^4 = 16 for EIP97 HW2.1/HW2.3 -+ */ -+ else { -+ val = 0; -+ val |= EIP97_MST_CTRL_TX_MAX_CMD(4); -+ writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL); -+ } - - /* Configure wr/rd cache values */ - writel(EIP197_MST_CTRL_RD_CACHE(RD_CACHE_4BITS) | ---- a/drivers/crypto/inside-secure/safexcel.h -+++ b/drivers/crypto/inside-secure/safexcel.h -@@ -315,6 +315,7 @@ - #define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0) - #define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4) - #define EIP197_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 20) -+#define EIP97_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 4) - #define EIP197_MST_CTRL_BYTE_SWAP BIT(24) - #define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25) - #define EIP197_MST_CTRL_BYTE_SWAP_BITS GENMASK(25, 24) diff --git a/6.1/target/linux/mediatek/patches-6.1/401-crypto-fix-eip97-cache-incoherent.patch b/6.1/target/linux/mediatek/patches-6.1/401-crypto-fix-eip97-cache-incoherent.patch deleted file mode 100644 index 186c66f6..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/401-crypto-fix-eip97-cache-incoherent.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/drivers/crypto/inside-secure/safexcel.h -+++ b/drivers/crypto/inside-secure/safexcel.h -@@ -737,6 +737,9 @@ enum safexcel_eip_version { - /* Priority we use for advertising our algorithms */ - #define SAFEXCEL_CRA_PRIORITY 300 - -+/* System cache line size */ -+#define SYSTEM_CACHELINE_SIZE 64 -+ - /* SM3 digest result for zero length message */ - #define EIP197_SM3_ZEROM_HASH "\x1A\xB2\x1D\x83\x55\xCF\xA1\x7F" \ - "\x8E\x61\x19\x48\x31\xE8\x1A\x8F" \ ---- a/drivers/crypto/inside-secure/safexcel_hash.c -+++ b/drivers/crypto/inside-secure/safexcel_hash.c -@@ -55,9 +55,9 @@ struct safexcel_ahash_req { - u8 block_sz; /* block size, only set once */ - u8 digest_sz; /* output digest size, only set once */ - __le32 state[SHA3_512_BLOCK_SIZE / -- sizeof(__le32)] __aligned(sizeof(__le32)); -+ sizeof(__le32)] __aligned(SYSTEM_CACHELINE_SIZE); - -- u64 len; -+ u64 len __aligned(SYSTEM_CACHELINE_SIZE); - u64 processed; - - u8 cache[HASH_CACHE_SIZE] __aligned(sizeof(u32)); diff --git a/6.1/target/linux/mediatek/patches-6.1/405-v6.2-mt7986-trng-add-rng-support.patch b/6.1/target/linux/mediatek/patches-6.1/405-v6.2-mt7986-trng-add-rng-support.patch deleted file mode 100644 index 615a1a1d..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/405-v6.2-mt7986-trng-add-rng-support.patch +++ /dev/null @@ -1,43 +0,0 @@ -From f1da27b7c4191f78ed81d3dabf64c769f896296c Mon Sep 17 00:00:00 2001 -From: "Mingming.Su" -Date: Sat, 8 Oct 2022 18:45:53 +0200 -Subject: [PATCH] hwrng: mtk - add mt7986 support - -1. Add trng compatible name for MT7986 -2. Fix mtk_rng_wait_ready() function - -Signed-off-by: Mingming.Su -Signed-off-by: Frank Wunderlich -Signed-off-by: Herbert Xu ---- - drivers/char/hw_random/mtk-rng.c | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - ---- a/drivers/char/hw_random/mtk-rng.c -+++ b/drivers/char/hw_random/mtk-rng.c -@@ -22,7 +22,7 @@ - #define RNG_AUTOSUSPEND_TIMEOUT 100 - - #define USEC_POLL 2 --#define TIMEOUT_POLL 20 -+#define TIMEOUT_POLL 60 - - #define RNG_CTRL 0x00 - #define RNG_EN BIT(0) -@@ -77,7 +77,7 @@ static bool mtk_rng_wait_ready(struct hw - readl_poll_timeout_atomic(priv->base + RNG_CTRL, ready, - ready & RNG_READY, USEC_POLL, - TIMEOUT_POLL); -- return !!ready; -+ return !!(ready & RNG_READY); - } - - static int mtk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait) -@@ -179,6 +179,7 @@ static const struct dev_pm_ops mtk_rng_p - #endif /* CONFIG_PM */ - - static const struct of_device_id mtk_rng_match[] = { -+ { .compatible = "mediatek,mt7986-rng" }, - { .compatible = "mediatek,mt7623-rng" }, - {}, - }; diff --git a/6.1/target/linux/mediatek/patches-6.1/410-bt-mtk-serial-fix.patch b/6.1/target/linux/mediatek/patches-6.1/410-bt-mtk-serial-fix.patch deleted file mode 100644 index 5b94c921..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/410-bt-mtk-serial-fix.patch +++ /dev/null @@ -1,33 +0,0 @@ ---- a/drivers/tty/serial/8250/8250.h -+++ b/drivers/tty/serial/8250/8250.h -@@ -86,6 +86,7 @@ struct serial8250_config { - * STOP PARITY EPAR SPAR WLEN5 WLEN6 - */ - #define UART_CAP_NOTEMT BIT(18) /* UART without interrupt on TEMT available */ -+#define UART_CAP_NMOD BIT(19) /* UART doesn't do termios */ - - #define UART_BUG_QUOT BIT(0) /* UART has buggy quot LSB */ - #define UART_BUG_TXEN BIT(1) /* UART has buggy TX IIR status */ ---- a/drivers/tty/serial/8250/8250_port.c -+++ b/drivers/tty/serial/8250/8250_port.c -@@ -287,7 +287,7 @@ static const struct serial8250_config ua - .tx_loadsz = 16, - .fcr = UART_FCR_ENABLE_FIFO | - UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, -- .flags = UART_CAP_FIFO, -+ .flags = UART_CAP_FIFO | UART_CAP_NMOD, - }, - [PORT_NPCM] = { - .name = "Nuvoton 16550", -@@ -2773,6 +2773,11 @@ serial8250_do_set_termios(struct uart_po - unsigned long flags; - unsigned int baud, quot, frac = 0; - -+ if (up->capabilities & UART_CAP_NMOD) { -+ termios->c_cflag = 0; -+ return; -+ } -+ - if (up->capabilities & UART_CAP_MINI) { - termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR); - if ((termios->c_cflag & CSIZE) == CS5 || diff --git a/6.1/target/linux/mediatek/patches-6.1/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch b/6.1/target/linux/mediatek/patches-6.1/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch deleted file mode 100644 index 8c2c80d6..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/431-drivers-spi-mt65xx-Move-chip_config-to-driver-s-priv.patch +++ /dev/null @@ -1,130 +0,0 @@ -From bfd3acc428085742d754a6d328d1a93ebf9451df Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:29:51 +0800 -Subject: [PATCH 1/6] drivers: spi-mt65xx: Move chip_config to driver's private - data - -Signed-off-by: SkyLake.Huang ---- - drivers/spi/spi-mt65xx.c | 29 +++++++++--------------- - include/linux/platform_data/spi-mt65xx.h | 17 -------------- - 2 files changed, 11 insertions(+), 35 deletions(-) - delete mode 100644 include/linux/platform_data/spi-mt65xx.h - ---- a/drivers/spi/spi-mt65xx.c -+++ b/drivers/spi/spi-mt65xx.c -@@ -14,7 +14,6 @@ - #include - #include - #include --#include - #include - #include - #include -@@ -171,6 +170,8 @@ struct mtk_spi { - struct device *dev; - dma_addr_t tx_dma; - dma_addr_t rx_dma; -+ u32 sample_sel; -+ u32 get_tick_dly; - }; - - static const struct mtk_spi_compatible mtk_common_compat; -@@ -216,15 +217,6 @@ static const struct mtk_spi_compatible m - .no_need_unprepare = true, - }; - --/* -- * A piece of default chip info unless the platform -- * supplies it. -- */ --static const struct mtk_chip_config mtk_default_chip_info = { -- .sample_sel = 0, -- .tick_delay = 0, --}; -- - static const struct of_device_id mtk_spi_of_match[] = { - { .compatible = "mediatek,spi-ipm", - .data = (void *)&mtk_ipm_compat, -@@ -352,7 +344,6 @@ static int mtk_spi_hw_init(struct spi_ma - { - u16 cpha, cpol; - u32 reg_val; -- struct mtk_chip_config *chip_config = spi->controller_data; - struct mtk_spi *mdata = spi_master_get_devdata(master); - - cpha = spi->mode & SPI_CPHA ? 1 : 0; -@@ -402,7 +393,7 @@ static int mtk_spi_hw_init(struct spi_ma - else - reg_val &= ~SPI_CMD_CS_POL; - -- if (chip_config->sample_sel) -+ if (mdata->sample_sel) - reg_val |= SPI_CMD_SAMPLE_SEL; - else - reg_val &= ~SPI_CMD_SAMPLE_SEL; -@@ -429,20 +420,20 @@ static int mtk_spi_hw_init(struct spi_ma - if (mdata->dev_comp->ipm_design) { - reg_val = readl(mdata->base + SPI_CMD_REG); - reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK; -- reg_val |= ((chip_config->tick_delay & 0x7) -+ reg_val |= ((mdata->get_tick_dly & 0x7) - << SPI_CMD_IPM_GET_TICKDLY_OFFSET); - writel(reg_val, mdata->base + SPI_CMD_REG); - } else { - reg_val = readl(mdata->base + SPI_CFG1_REG); - reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK; -- reg_val |= ((chip_config->tick_delay & 0x7) -+ reg_val |= ((mdata->get_tick_dly & 0x7) - << SPI_CFG1_GET_TICK_DLY_OFFSET); - writel(reg_val, mdata->base + SPI_CFG1_REG); - } - } else { - reg_val = readl(mdata->base + SPI_CFG1_REG); - reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1; -- reg_val |= ((chip_config->tick_delay & 0x3) -+ reg_val |= ((mdata->get_tick_dly & 0x3) - << SPI_CFG1_GET_TICK_DLY_OFFSET_V1); - writel(reg_val, mdata->base + SPI_CFG1_REG); - } -@@ -732,9 +723,6 @@ static int mtk_spi_setup(struct spi_devi - { - struct mtk_spi *mdata = spi_master_get_devdata(spi->master); - -- if (!spi->controller_data) -- spi->controller_data = (void *)&mtk_default_chip_info; -- - if (mdata->dev_comp->need_pad_sel && spi->cs_gpiod) - /* CS de-asserted, gpiolib will handle inversion */ - gpiod_direction_output(spi->cs_gpiod, 0); -@@ -1138,6 +1126,10 @@ static int mtk_spi_probe(struct platform - mdata = spi_master_get_devdata(master); - mdata->dev_comp = device_get_match_data(dev); - -+ /* Set device configs to default first. Calibrate it later. */ -+ mdata->sample_sel = 0; -+ mdata->get_tick_dly = 2; -+ - if (mdata->dev_comp->enhance_timing) - master->mode_bits |= SPI_CS_HIGH; - ---- a/include/linux/platform_data/spi-mt65xx.h -+++ /dev/null -@@ -1,17 +0,0 @@ --/* SPDX-License-Identifier: GPL-2.0-only */ --/* -- * MTK SPI bus driver definitions -- * -- * Copyright (c) 2015 MediaTek Inc. -- * Author: Leilk Liu -- */ -- --#ifndef ____LINUX_PLATFORM_DATA_SPI_MTK_H --#define ____LINUX_PLATFORM_DATA_SPI_MTK_H -- --/* Board specific platform_data */ --struct mtk_chip_config { -- u32 sample_sel; -- u32 tick_delay; --}; --#endif diff --git a/6.1/target/linux/mediatek/patches-6.1/432-drivers-spi-Add-support-for-dynamic-calibration.patch b/6.1/target/linux/mediatek/patches-6.1/432-drivers-spi-Add-support-for-dynamic-calibration.patch deleted file mode 100644 index 280993e5..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/432-drivers-spi-Add-support-for-dynamic-calibration.patch +++ /dev/null @@ -1,236 +0,0 @@ -From 2ade0172154e50c8a2bfd8634c6eff943cffea29 Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:35:52 +0800 -Subject: [PATCH 2/6] drivers: spi: Add support for dynamic calibration - -Signed-off-by: SkyLake.Huang ---- - drivers/spi/spi.c | 137 ++++++++++++++++++++++++++++++++++++++++ - include/linux/spi/spi.h | 42 ++++++++++++ - 2 files changed, 179 insertions(+) - ---- a/drivers/spi/spi.c -+++ b/drivers/spi/spi.c -@@ -1374,6 +1374,70 @@ static int spi_transfer_wait(struct spi_ - return 0; - } - -+int spi_do_calibration(struct spi_controller *ctlr, struct spi_device *spi, -+ int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen), void *drv_priv) -+{ -+ int datalen = ctlr->cal_rule->datalen; -+ int addrlen = ctlr->cal_rule->addrlen; -+ u8 *buf; -+ int ret; -+ int i; -+ struct list_head *cal_head, *listptr; -+ struct spi_cal_target *target; -+ -+ /* Calculate calibration result */ -+ int hit_val, total_hit, origin; -+ bool hit; -+ -+ /* Make sure we can start calibration */ -+ if(!ctlr->cal_target || !ctlr->cal_rule || !ctlr->append_caldata) -+ return 0; -+ -+ buf = kzalloc(datalen * sizeof(u8), GFP_KERNEL); -+ if(!buf) -+ return -ENOMEM; -+ -+ ret = ctlr->append_caldata(ctlr); -+ if (ret) -+ goto cal_end; -+ -+ cal_head = ctlr->cal_target; -+ list_for_each(listptr, cal_head) { -+ target = list_entry(listptr, struct spi_cal_target, list); -+ -+ hit = false; -+ hit_val = 0; -+ total_hit = 0; -+ origin = *target->cal_item; -+ -+ for(i=target->cal_min; i<=target->cal_max; i+=target->step) { -+ *target->cal_item = i; -+ ret = (*cal_read)(drv_priv, ctlr->cal_rule->addr, addrlen, buf, datalen); -+ if(ret) -+ break; -+ dev_dbg(&spi->dev, "controller cal item value: 0x%x\n", i); -+ if(memcmp(ctlr->cal_rule->match_data, buf, datalen * sizeof(u8)) == 0) { -+ hit = true; -+ hit_val += i; -+ total_hit++; -+ dev_dbg(&spi->dev, "golden data matches data read!\n"); -+ } -+ } -+ if(hit) { -+ *target->cal_item = DIV_ROUND_CLOSEST(hit_val, total_hit); -+ dev_info(&spi->dev, "calibration result: 0x%x", *target->cal_item); -+ } else { -+ *target->cal_item = origin; -+ dev_warn(&spi->dev, "calibration failed, fallback to default: 0x%x", origin); -+ } -+ } -+ -+cal_end: -+ kfree(buf); -+ return ret? ret: 0; -+} -+EXPORT_SYMBOL_GPL(spi_do_calibration); -+ - static void _spi_transfer_delay_ns(u32 ns) - { - if (!ns) -@@ -2208,6 +2272,75 @@ void spi_flush_queue(struct spi_controll - /*-------------------------------------------------------------------------*/ - - #if defined(CONFIG_OF) -+static inline void alloc_cal_data(struct list_head **cal_target, -+ struct spi_cal_rule **cal_rule, bool enable) -+{ -+ if(enable) { -+ *cal_target = kmalloc(sizeof(struct list_head), GFP_KERNEL); -+ INIT_LIST_HEAD(*cal_target); -+ *cal_rule = kmalloc(sizeof(struct spi_cal_rule), GFP_KERNEL); -+ } else { -+ kfree(*cal_target); -+ kfree(*cal_rule); -+ } -+} -+ -+static int of_spi_parse_cal_dt(struct spi_controller *ctlr, struct spi_device *spi, -+ struct device_node *nc) -+{ -+ u32 value; -+ int rc; -+ const char *cal_mode; -+ -+ rc = of_property_read_bool(nc, "spi-cal-enable"); -+ if (rc) -+ alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, true); -+ else -+ return 0; -+ -+ rc = of_property_read_string(nc, "spi-cal-mode", &cal_mode); -+ if(!rc) { -+ if(strcmp("read-data", cal_mode) == 0){ -+ ctlr->cal_rule->mode = SPI_CAL_READ_DATA; -+ } else if(strcmp("read-pp", cal_mode) == 0) { -+ ctlr->cal_rule->mode = SPI_CAL_READ_PP; -+ return 0; -+ } else if(strcmp("read-sfdp", cal_mode) == 0){ -+ ctlr->cal_rule->mode = SPI_CAL_READ_SFDP; -+ return 0; -+ } -+ } else -+ goto err; -+ -+ ctlr->cal_rule->datalen = 0; -+ rc = of_property_read_u32(nc, "spi-cal-datalen", &value); -+ if(!rc && value > 0) { -+ ctlr->cal_rule->datalen = value; -+ -+ ctlr->cal_rule->match_data = kzalloc(value * sizeof(u8), GFP_KERNEL); -+ rc = of_property_read_u8_array(nc, "spi-cal-data", -+ ctlr->cal_rule->match_data, value); -+ if(rc) -+ kfree(ctlr->cal_rule->match_data); -+ } -+ -+ rc = of_property_read_u32(nc, "spi-cal-addrlen", &value); -+ if(!rc && value > 0) { -+ ctlr->cal_rule->addrlen = value; -+ -+ ctlr->cal_rule->addr = kzalloc(value * sizeof(u32), GFP_KERNEL); -+ rc = of_property_read_u32_array(nc, "spi-cal-addr", -+ ctlr->cal_rule->addr, value); -+ if(rc) -+ kfree(ctlr->cal_rule->addr); -+ } -+ return 0; -+ -+err: -+ alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, false); -+ return 0; -+} -+ - static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, - struct device_node *nc) - { -@@ -2326,6 +2459,10 @@ of_register_spi_device(struct spi_contro - if (rc) - goto err_out; - -+ rc = of_spi_parse_cal_dt(ctlr, spi, nc); -+ if (rc) -+ goto err_out; -+ - /* Store a pointer to the node in the device structure */ - of_node_get(nc); - spi->dev.of_node = nc; ---- a/include/linux/spi/spi.h -+++ b/include/linux/spi/spi.h -@@ -298,6 +298,40 @@ struct spi_driver { - struct device_driver driver; - }; - -+enum { -+ SPI_CAL_READ_DATA = 0, -+ SPI_CAL_READ_PP = 1, /* only for SPI-NAND */ -+ SPI_CAL_READ_SFDP = 2, /* only for SPI-NOR */ -+}; -+ -+struct nand_addr { -+ unsigned int lun; -+ unsigned int plane; -+ unsigned int eraseblock; -+ unsigned int page; -+ unsigned int dataoffs; -+}; -+ -+/** -+ * Read calibration rule from device dts node. -+ * Once calibration result matches the rule, we regard is as success. -+ */ -+struct spi_cal_rule { -+ int datalen; -+ u8 *match_data; -+ int addrlen; -+ u32 *addr; -+ int mode; -+}; -+ -+struct spi_cal_target { -+ u32 *cal_item; -+ int cal_min; /* min of cal_item */ -+ int cal_max; /* max of cal_item */ -+ int step; /* Increase/decrease cal_item */ -+ struct list_head list; -+}; -+ - static inline struct spi_driver *to_spi_driver(struct device_driver *drv) - { - return drv ? container_of(drv, struct spi_driver, driver) : NULL; -@@ -682,6 +716,11 @@ struct spi_controller { - void *dummy_rx; - void *dummy_tx; - -+ /* For calibration */ -+ int (*append_caldata)(struct spi_controller *ctlr); -+ struct list_head *cal_target; -+ struct spi_cal_rule *cal_rule; -+ - int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs); - - /* -@@ -1489,6 +1528,9 @@ spi_register_board_info(struct spi_board - { return 0; } - #endif - -+extern int spi_do_calibration(struct spi_controller *ctlr, -+ struct spi_device *spi, int (*cal_read)(void *, u32 *, int, u8 *, int), void *drv_priv); -+ - /* If you're hotplugging an adapter with devices (parport, usb, etc) - * use spi_new_device() to describe each device. You can also call - * spi_unregister_device() to start making that device vanish, but diff --git a/6.1/target/linux/mediatek/patches-6.1/433-drivers-spi-mem-Add-spi-calibration-hook.patch b/6.1/target/linux/mediatek/patches-6.1/433-drivers-spi-mem-Add-spi-calibration-hook.patch deleted file mode 100644 index e87d63db..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/433-drivers-spi-mem-Add-spi-calibration-hook.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 06640a5da2973318c06e516da16a5b579622e7c5 Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:37:55 +0800 -Subject: [PATCH 3/6] drivers: spi-mem: Add spi calibration hook - -Signed-off-by: SkyLake.Huang ---- - drivers/spi/spi-mem.c | 8 ++++++++ - include/linux/spi/spi-mem.h | 4 ++++ - 2 files changed, 12 insertions(+) - ---- a/drivers/spi/spi-mem.c -+++ b/drivers/spi/spi-mem.c -@@ -419,6 +419,14 @@ int spi_mem_exec_op(struct spi_mem *mem, - } - EXPORT_SYMBOL_GPL(spi_mem_exec_op); - -+int spi_mem_do_calibration(struct spi_mem *mem, -+ int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen), -+ void *priv) -+{ -+ return spi_do_calibration(mem->spi->controller, mem->spi, cal_read, priv); -+} -+EXPORT_SYMBOL_GPL(spi_mem_do_calibration); -+ - /** - * spi_mem_get_name() - Return the SPI mem device name to be used by the - * upper layer if necessary ---- a/include/linux/spi/spi-mem.h -+++ b/include/linux/spi/spi-mem.h -@@ -366,6 +366,10 @@ bool spi_mem_supports_op(struct spi_mem - int spi_mem_exec_op(struct spi_mem *mem, - const struct spi_mem_op *op); - -+int spi_mem_do_calibration(struct spi_mem *mem, -+ int (*cal_read)(void *, u32 *, int, u8 *, int), -+ void *priv); -+ - const char *spi_mem_get_name(struct spi_mem *mem); - - struct spi_mem_dirmap_desc * diff --git a/6.1/target/linux/mediatek/patches-6.1/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch b/6.1/target/linux/mediatek/patches-6.1/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch deleted file mode 100644 index ee3dc278..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/434-drivers-spi-mt65xx-Add-controller-s-calibration-para.patch +++ /dev/null @@ -1,43 +0,0 @@ -From d278c7a0bf730318a7ccf8d0a8b434c813e23fd0 Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:39:03 +0800 -Subject: [PATCH 4/6] drivers: spi-mt65xx: Add controller's calibration - paramter - -Signed-off-by: SkyLake.Huang ---- - drivers/spi/spi-mt65xx.c | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - ---- a/drivers/spi/spi-mt65xx.c -+++ b/drivers/spi/spi-mt65xx.c -@@ -832,6 +832,21 @@ static irqreturn_t mtk_spi_interrupt(int - return IRQ_HANDLED; - } - -+static int mtk_spi_append_caldata(struct spi_controller *ctlr) -+{ -+ struct spi_cal_target *cal_target = kmalloc(sizeof(*cal_target), GFP_KERNEL); -+ struct mtk_spi *mdata = spi_master_get_devdata(ctlr); -+ -+ cal_target->cal_item = &mdata->get_tick_dly; -+ cal_target->cal_min = 0; -+ cal_target->cal_max = 7; -+ cal_target->step = 1; -+ -+ list_add(&cal_target->list, ctlr->cal_target); -+ -+ return 0; -+} -+ - static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem, - struct spi_mem_op *op) - { -@@ -1122,6 +1137,7 @@ static int mtk_spi_probe(struct platform - master->setup = mtk_spi_setup; - master->set_cs_timing = mtk_spi_set_hw_cs_timing; - master->use_gpio_descriptors = true; -+ master->append_caldata = mtk_spi_append_caldata; - - mdata = spi_master_get_devdata(master); - mdata->dev_comp = device_get_match_data(dev); diff --git a/6.1/target/linux/mediatek/patches-6.1/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch b/6.1/target/linux/mediatek/patches-6.1/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch deleted file mode 100644 index 3991d892..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/435-drivers-mtd-spinand-Add-calibration-support-for-spin.patch +++ /dev/null @@ -1,81 +0,0 @@ -From 7670ec4a14891a1a182b98a9c403ffbf6b49e4b1 Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:39:56 +0800 -Subject: [PATCH 5/6] drivers: mtd: spinand: Add calibration support for - spinand - -Signed-off-by: SkyLake.Huang ---- - drivers/mtd/nand/spi/core.c | 54 +++++++++++++++++++++++++++++++++++++ - 1 file changed, 54 insertions(+) - ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -978,6 +978,56 @@ static int spinand_manufacturer_match(st - return -ENOTSUPP; - } - -+int spinand_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen) { -+ struct spinand_device *spinand = (struct spinand_device *)priv; -+ struct device *dev = &spinand->spimem->spi->dev; -+ struct spi_mem_op op = SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, buf, readlen); -+ struct nand_pos pos; -+ struct nand_page_io_req req; -+ u8 status; -+ int ret; -+ -+ if(addrlen != sizeof(struct nand_addr)/sizeof(unsigned int)) { -+ dev_err(dev, "Must provide correct addr(length) for spinand calibration\n"); -+ return -EINVAL; -+ } -+ -+ ret = spinand_reset_op(spinand); -+ if (ret) -+ return ret; -+ -+ /* We should store our golden data in first target because -+ * we can't switch target at this moment. -+ */ -+ pos = (struct nand_pos){ -+ .target = 0, -+ .lun = *addr, -+ .plane = *(addr+1), -+ .eraseblock = *(addr+2), -+ .page = *(addr+3), -+ }; -+ -+ req = (struct nand_page_io_req){ -+ .pos = pos, -+ .dataoffs = *(addr+4), -+ .datalen = readlen, -+ .databuf.in = buf, -+ .mode = MTD_OPS_AUTO_OOB, -+ }; -+ -+ ret = spinand_load_page_op(spinand, &req); -+ if (ret) -+ return ret; -+ -+ ret = spinand_wait(spinand, &status); -+ if (ret < 0) -+ return ret; -+ -+ ret = spi_mem_exec_op(spinand->spimem, &op); -+ -+ return 0; -+} -+ - static int spinand_id_detect(struct spinand_device *spinand) - { - u8 *id = spinand->id.data; -@@ -1228,6 +1278,10 @@ static int spinand_init(struct spinand_d - if (!spinand->scratchbuf) - return -ENOMEM; - -+ ret = spi_mem_do_calibration(spinand->spimem, spinand_cal_read, spinand); -+ if (ret) -+ dev_err(dev, "Failed to calibrate SPI-NAND (err = %d)\n", ret); -+ - ret = spinand_detect(spinand); - if (ret) - goto err_free_bufs; diff --git a/6.1/target/linux/mediatek/patches-6.1/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch b/6.1/target/linux/mediatek/patches-6.1/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch deleted file mode 100644 index 704b8165..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/436-drivers-mtd-spi-nor-Add-calibration-support-for-spi-.patch +++ /dev/null @@ -1,57 +0,0 @@ -From f3fe3b15eca7908eaac57f9b8387a5dbc45ec5b2 Mon Sep 17 00:00:00 2001 -From: "SkyLake.Huang" -Date: Thu, 23 Jun 2022 18:40:59 +0800 -Subject: [PATCH 6/6] drivers: mtd: spi-nor: Add calibration support for - spi-nor - -Signed-off-by: SkyLake.Huang ---- - drivers/mtd/nand/spi/core.c | 5 ++++- - drivers/mtd/spi-nor/core.c | 15 +++++++++++++++ - 2 files changed, 19 insertions(+), 1 deletion(-) - ---- a/drivers/mtd/nand/spi/core.c -+++ b/drivers/mtd/nand/spi/core.c -@@ -1019,7 +1019,10 @@ int spinand_cal_read(void *priv, u32 *ad - if (ret) - return ret; - -- ret = spinand_wait(spinand, &status); -+ ret = spinand_wait(spinand, -+ SPINAND_READ_INITIAL_DELAY_US, -+ SPINAND_READ_POLL_DELAY_US, -+ &status); - if (ret < 0) - return ret; - ---- a/drivers/mtd/spi-nor/core.c -+++ b/drivers/mtd/spi-nor/core.c -@@ -2899,6 +2899,18 @@ static const struct flash_info *spi_nor_ - return NULL; - } - -+static int spi_nor_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen) -+{ -+ struct spi_nor *nor = (struct spi_nor *)priv; -+ -+ nor->reg_proto = SNOR_PROTO_1_1_1; -+ nor->read_proto = SNOR_PROTO_1_1_1; -+ nor->read_opcode = SPINOR_OP_READ; -+ nor->read_dummy = 0; -+ -+ return nor->controller_ops->read(nor, *addr, readlen, buf); -+} -+ - static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor, - const char *name) - { -@@ -3002,6 +3014,9 @@ int spi_nor_scan(struct spi_nor *nor, co - if (!nor->bouncebuf) - return -ENOMEM; - -+ if(nor->spimem) -+ spi_mem_do_calibration(nor->spimem, spi_nor_cal_read, nor); -+ - info = spi_nor_get_flash_info(nor, name); - if (IS_ERR(info)) - return PTR_ERR(info); diff --git a/6.1/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch b/6.1/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch deleted file mode 100644 index cdfe79eb..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/500-gsw-rtl8367s-mt7622-support.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -382,6 +382,12 @@ config ROCKCHIP_PHY - help - Currently supports the integrated Ethernet PHY. - -+config RTL8367S_GSW -+ tristate "rtl8367 Gigabit Switch support for mt7622" -+ depends on NET_VENDOR_MEDIATEK -+ help -+ This driver supports rtl8367s in mt7622 -+ - config SMSC_PHY - tristate "SMSC PHYs" - help ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -98,6 +98,7 @@ obj-$(CONFIG_QSEMI_PHY) += qsemi.o - obj-$(CONFIG_REALTEK_PHY) += realtek.o - obj-$(CONFIG_RENESAS_PHY) += uPD60620.o - obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o -+obj-$(CONFIG_RTL8367S_GSW) += rtk/ - obj-$(CONFIG_SMSC_PHY) += smsc.o - obj-$(CONFIG_STE10XP) += ste10Xp.o - obj-$(CONFIG_TERANETICS_PHY) += teranetics.o diff --git a/6.1/target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch b/6.1/target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch deleted file mode 100644 index 05a6ff0f..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/601-PCI-mediatek-Assert-PERST-for-100ms-for-power-and-cl.patch +++ /dev/null @@ -1,34 +0,0 @@ -From: qizhong cheng -Date: Mon, 27 Dec 2021 21:31:10 +0800 -Subject: [PATCH] PCI: mediatek: Assert PERST# for 100ms for power and clock to - stabilize -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Described in PCIe CEM specification sections 2.2 (PERST# Signal) and -2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should -be delayed 100ms (TPVPERL) for the power and clock to become stable. - -Link: https://lore.kernel.org/r/20211227133110.14500-1-qizhong.cheng@mediatek.com -Signed-off-by: qizhong cheng -Signed-off-by: Lorenzo Pieralisi -Acked-by: Pali Rohár ---- - ---- a/drivers/pci/controller/pcie-mediatek.c -+++ b/drivers/pci/controller/pcie-mediatek.c -@@ -702,6 +702,13 @@ static int mtk_pcie_startup_port_v2(stru - */ - msleep(100); - -+ /* -+ * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and -+ * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should -+ * be delayed 100ms (TPVPERL) for the power and clock to become stable. -+ */ -+ msleep(100); -+ - /* De-assert PHY, PE, PIPE, MAC and configuration reset */ - val = readl(port->base + PCIE_RST_CTRL); - val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | diff --git a/6.1/target/linux/mediatek/patches-6.1/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch b/6.1/target/linux/mediatek/patches-6.1/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch deleted file mode 100644 index bf479ab5..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/602-arm64-dts-mediatek-add-mt7622-pcie-slot-node.patch +++ /dev/null @@ -1,28 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -849,6 +849,12 @@ - #address-cells = <0>; - #interrupt-cells = <1>; - }; -+ -+ slot0: pcie@0,0 { -+ reg = <0x0000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ }; - }; - - pcie1: pcie@1a145000 { -@@ -887,6 +893,12 @@ - #address-cells = <0>; - #interrupt-cells = <1>; - }; -+ -+ slot1: pcie@1,0 { -+ reg = <0x0800 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ }; - }; - - sata: sata@1a200000 { diff --git a/6.1/target/linux/mediatek/patches-6.1/610-pcie-mediatek-fix-clearing-interrupt-status.patch b/6.1/target/linux/mediatek/patches-6.1/610-pcie-mediatek-fix-clearing-interrupt-status.patch deleted file mode 100644 index 2a49b227..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/610-pcie-mediatek-fix-clearing-interrupt-status.patch +++ /dev/null @@ -1,23 +0,0 @@ -From: Felix Fietkau -Date: Fri, 4 Sep 2020 18:33:27 +0200 -Subject: [PATCH] pcie-mediatek: fix clearing interrupt status - -Clearing the status needs to happen after running the handler, otherwise -we will get an extra spurious interrupt after the cause has been cleared - -Signed-off-by: Felix Fietkau ---- - ---- a/drivers/pci/controller/pcie-mediatek.c -+++ b/drivers/pci/controller/pcie-mediatek.c -@@ -607,9 +607,9 @@ static void mtk_pcie_intr_handler(struct - if (status & INTX_MASK) { - for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) { - /* Clear the INTx */ -- writel(1 << bit, port->base + PCIE_INT_STATUS); - generic_handle_domain_irq(port->irq_domain, - bit - INTX_SHIFT); -+ writel(1 << bit, port->base + PCIE_INT_STATUS); - } - } - diff --git a/6.1/target/linux/mediatek/patches-6.1/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch b/6.1/target/linux/mediatek/patches-6.1/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch deleted file mode 100644 index de64eda8..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/710-pci-pcie-mediatek-add-support-for-coherent-DMA.patch +++ /dev/null @@ -1,82 +0,0 @@ -From: Felix Fietkau -Date: Fri, 4 Sep 2020 18:42:42 +0200 -Subject: [PATCH] pci: pcie-mediatek: add support for coherent DMA - -It improves performance by eliminating the need for a cache flush for DMA on -attached devices - -Signed-off-by: Felix Fietkau ---- - ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -837,6 +837,9 @@ - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; - status = "disabled"; -+ dma-coherent; -+ mediatek,hifsys = <&hifsys>; -+ mediatek,cci-control = <&cci_control2>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; -@@ -881,6 +884,9 @@ - bus-range = <0x00 0xff>; - ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; - status = "disabled"; -+ dma-coherent; -+ mediatek,hifsys = <&hifsys>; -+ mediatek,cci-control = <&cci_control2>; - - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; ---- a/drivers/pci/controller/pcie-mediatek.c -+++ b/drivers/pci/controller/pcie-mediatek.c -@@ -20,6 +20,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -139,6 +140,11 @@ - #define PCIE_LINK_STATUS_V2 0x804 - #define PCIE_PORT_LINKUP_V2 BIT(10) - -+/* DMA channel mapping */ -+#define HIFSYS_DMA_AG_MAP 0x008 -+#define HIFSYS_DMA_AG_MAP_PCIE0 BIT(0) -+#define HIFSYS_DMA_AG_MAP_PCIE1 BIT(1) -+ - struct mtk_pcie_port; - - /** -@@ -1054,6 +1060,27 @@ static int mtk_pcie_setup(struct mtk_pci - struct mtk_pcie_port *port, *tmp; - int err, slot; - -+ if (of_dma_is_coherent(node)) { -+ struct regmap *con; -+ u32 mask; -+ -+ con = syscon_regmap_lookup_by_phandle(node, -+ "mediatek,cci-control"); -+ /* enable CPU/bus coherency */ -+ if (!IS_ERR(con)) -+ regmap_write(con, 0, 3); -+ -+ con = syscon_regmap_lookup_by_phandle(node, -+ "mediatek,hifsys"); -+ if (IS_ERR(con)) { -+ dev_err(dev, "missing hifsys node\n"); -+ return PTR_ERR(con); -+ } -+ -+ mask = HIFSYS_DMA_AG_MAP_PCIE0 | HIFSYS_DMA_AG_MAP_PCIE1; -+ regmap_update_bits(con, HIFSYS_DMA_AG_MAP, mask, mask); -+ } -+ - slot = of_get_pci_domain_nr(dev->of_node); - if (slot < 0) { - for_each_available_child_of_node(node, child) { diff --git a/6.1/target/linux/mediatek/patches-6.1/721-dts-mt7622-mediatek-fix-300mhz.patch b/6.1/target/linux/mediatek/patches-6.1/721-dts-mt7622-mediatek-fix-300mhz.patch deleted file mode 100644 index f9a5fdbd..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/721-dts-mt7622-mediatek-fix-300mhz.patch +++ /dev/null @@ -1,27 +0,0 @@ -From: Jip de Beer -Date: Sun, 9 Jan 2022 13:14:04 +0100 -Subject: [PATCH] mediatek mt7622: fix 300mhz typo in dts - -The lowest frequency should be 300MHz, since that is the label -assigned to the OPP in the mt7622.dtsi device tree, while there is one -missing zero in the actual value. - -To be clear, the lowest frequency should be 300MHz instead of 30MHz. - -As mentioned @dangowrt on the OpenWrt forum there is no benefit in -leaving 30MHz as the lowest frequency. - -Signed-off-by: Jip de Beer -Signed-off-by: Fritz D. Ansel ---- ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -24,7 +24,7 @@ - compatible = "operating-points-v2"; - opp-shared; - opp-300000000 { -- opp-hz = /bits/ 64 <30000000>; -+ opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <950000>; - }; - diff --git a/6.1/target/linux/mediatek/patches-6.1/722-remove-300Hz-to-prevent-freeze.patch b/6.1/target/linux/mediatek/patches-6.1/722-remove-300Hz-to-prevent-freeze.patch deleted file mode 100644 index 52069496..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/722-remove-300Hz-to-prevent-freeze.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi -@@ -23,11 +23,17 @@ - cpu_opp_table: opp-table { - compatible = "operating-points-v2"; - opp-shared; -- opp-300000000 { -- opp-hz = /bits/ 64 <300000000>; -- opp-microvolt = <950000>; -- }; -- -+ /* Due to the bug described at the link below, remove the 300 MHz clock to avoid a low -+ * voltage condition that can cause a hang when rebooting the RT3200/E8450. -+ * -+ * https://forum.openwrt.org/t/belkin-rt3200-linksys-e8450-wifi-ax-discussion/94302/1490 -+ * -+ * opp-300000000 { -+ * opp-hz = /bits/ 64 <300000000>; -+ * opp-microvolt = <950000>; -+ * }; -+ * -+ */ - opp-437500000 { - opp-hz = /bits/ 64 <437500000>; - opp-microvolt = <1000000>; diff --git a/6.1/target/linux/mediatek/patches-6.1/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch b/6.1/target/linux/mediatek/patches-6.1/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch deleted file mode 100644 index cba76ad7..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/730-v6.5-net-phy-add-driver-for-MediaTek-SoC-built-in-GE-PHYs.patch +++ /dev/null @@ -1,1204 +0,0 @@ -From 98c485eaf509bc0e2a85f9b58d17cd501f274c4e Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Sun, 11 Jun 2023 00:48:10 +0100 -Subject: [PATCH] net: phy: add driver for MediaTek SoC built-in GE PHYs - -Some of MediaTek's Filogic SoCs come with built-in gigabit Ethernet -PHYs which require calibration data from the SoC's efuse. -Despite the similar design the driver doesn't share any code with the -existing mediatek-ge.c. -Add support for such PHYs by introducing a new driver with basic -support for MediaTek SoCs MT7981 and MT7988 built-in 1GE PHYs. - -Signed-off-by: Daniel Golle -Reviewed-by: Andrew Lunn -Signed-off-by: David S. Miller ---- - MAINTAINERS | 9 + - drivers/net/phy/Kconfig | 12 + - drivers/net/phy/Makefile | 1 + - drivers/net/phy/mediatek-ge-soc.c | 1116 +++++++++++++++++++++++++++++ - drivers/net/phy/mediatek-ge.c | 3 +- - 5 files changed, 1140 insertions(+), 1 deletion(-) - create mode 100644 drivers/net/phy/mediatek-ge-soc.c - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -12934,6 +12934,15 @@ S: Maintained - F: drivers/net/pcs/pcs-mtk-lynxi.c - F: include/linux/pcs/pcs-mtk-lynxi.h - -+MEDIATEK ETHERNET PHY DRIVERS -+M: Daniel Golle -+M: Qingfang Deng -+M: SkyLake Huang -+L: netdev@vger.kernel.org -+S: Maintained -+F: drivers/net/phy/mediatek-ge-soc.c -+F: drivers/net/phy/mediatek-ge.c -+ - MEDIATEK I2C CONTROLLER DRIVER - M: Qii Wang - L: linux-i2c@vger.kernel.org ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -307,6 +307,18 @@ config MEDIATEK_GE_PHY - help - Supports the MediaTek Gigabit Ethernet PHYs. - -+config MEDIATEK_GE_SOC_PHY -+ tristate "MediaTek SoC Ethernet PHYs" -+ depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST -+ select NVMEM_MTK_EFUSE -+ help -+ Supports MediaTek SoC built-in Gigabit Ethernet PHYs. -+ -+ Include support for built-in Ethernet PHYs which are present in -+ the MT7981 and MT7988 SoCs. These PHYs need calibration data -+ present in the SoCs efuse and will dynamically calibrate VCM -+ (common-mode voltage) during startup. -+ - config MICREL_PHY - tristate "Micrel PHYs" - depends on PTP_1588_CLOCK_OPTIONAL ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -84,6 +84,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o - obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o - obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o - obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o -+obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o - obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o - obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o - obj-$(CONFIG_MICREL_PHY) += micrel.o ---- /dev/null -+++ b/drivers/net/phy/mediatek-ge-soc.c -@@ -0,0 +1,1116 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define MTK_GPHY_ID_MT7981 0x03a29461 -+#define MTK_GPHY_ID_MT7988 0x03a29481 -+ -+#define MTK_EXT_PAGE_ACCESS 0x1f -+#define MTK_PHY_PAGE_STANDARD 0x0000 -+#define MTK_PHY_PAGE_EXTENDED_3 0x0003 -+ -+#define MTK_PHY_LPI_REG_14 0x14 -+#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0) -+ -+#define MTK_PHY_LPI_REG_1c 0x1c -+#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8) -+ -+#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 -+#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 -+ -+#define ANALOG_INTERNAL_OPERATION_MAX_US 20 -+#define TXRESERVE_MIN 0 -+#define TXRESERVE_MAX 7 -+ -+#define MTK_PHY_ANARG_RG 0x10 -+#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8) -+ -+/* Registers on MDIO_MMD_VEND1 */ -+#define MTK_PHY_TXVLD_DA_RG 0x12 -+#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10) -+#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16 -+#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10) -+#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17 -+#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8) -+#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18 -+#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8) -+#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19 -+#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8) -+#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20 -+#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8) -+#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21 -+#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8) -+#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22 -+#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8) -+#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0) -+ -+#define MTK_PHY_RXADC_CTRL_RG7 0xc6 -+#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8) -+ -+#define MTK_PHY_RXADC_CTRL_RG9 0xc8 -+#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12) -+#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8) -+#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4) -+#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0) -+ -+#define MTK_PHY_LDO_OUTPUT_V 0xd7 -+ -+#define MTK_PHY_RG_ANA_CAL_RG0 0xdb -+#define MTK_PHY_RG_CAL_CKINV BIT(12) -+#define MTK_PHY_RG_ANA_CALEN BIT(8) -+#define MTK_PHY_RG_ZCALEN_A BIT(0) -+ -+#define MTK_PHY_RG_ANA_CAL_RG1 0xdc -+#define MTK_PHY_RG_ZCALEN_B BIT(12) -+#define MTK_PHY_RG_ZCALEN_C BIT(8) -+#define MTK_PHY_RG_ZCALEN_D BIT(4) -+#define MTK_PHY_RG_TXVOS_CALEN BIT(0) -+ -+#define MTK_PHY_RG_ANA_CAL_RG5 0xe0 -+#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8) -+ -+#define MTK_PHY_RG_TX_FILTER 0xfe -+ -+#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120 -+#define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8) -+#define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0) -+ -+#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122 -+#define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0) -+ -+#define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144 -+#define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5) -+ -+#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172 -+#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8) -+#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0) -+ -+#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173 -+#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8) -+#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0) -+ -+#define MTK_PHY_RG_AD_CAL_COMP 0x17a -+#define MTK_PHY_AD_CAL_COMP_OUT_SHIFT (8) -+ -+#define MTK_PHY_RG_AD_CAL_CLK 0x17b -+#define MTK_PHY_DA_CAL_CLK BIT(0) -+ -+#define MTK_PHY_RG_AD_CALIN 0x17c -+#define MTK_PHY_DA_CALIN_FLAG BIT(0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d -+#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e -+#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f -+#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN0_D 0x180 -+#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN1_A 0x181 -+#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN1_B 0x182 -+#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN1_C 0x183 -+#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DASN_DAC_IN1_D 0x184 -+#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0) -+ -+#define MTK_PHY_RG_DEV1E_REG19b 0x19b -+#define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8) -+ -+#define MTK_PHY_RG_LP_IIR2_K1_L 0x22a -+#define MTK_PHY_RG_LP_IIR2_K1_U 0x22b -+#define MTK_PHY_RG_LP_IIR2_K2_L 0x22c -+#define MTK_PHY_RG_LP_IIR2_K2_U 0x22d -+#define MTK_PHY_RG_LP_IIR2_K3_L 0x22e -+#define MTK_PHY_RG_LP_IIR2_K3_U 0x22f -+#define MTK_PHY_RG_LP_IIR2_K4_L 0x230 -+#define MTK_PHY_RG_LP_IIR2_K4_U 0x231 -+#define MTK_PHY_RG_LP_IIR2_K5_L 0x232 -+#define MTK_PHY_RG_LP_IIR2_K5_U 0x233 -+ -+#define MTK_PHY_RG_DEV1E_REG234 0x234 -+#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0) -+#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4) -+#define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12) -+ -+#define MTK_PHY_RG_LPF_CNT_VAL 0x235 -+ -+#define MTK_PHY_RG_DEV1E_REG238 0x238 -+#define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0) -+#define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12) -+ -+#define MTK_PHY_RG_DEV1E_REG239 0x239 -+#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0) -+#define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12) -+ -+#define MTK_PHY_RG_DEV1E_REG27C 0x27c -+#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8) -+#define MTK_PHY_RG_DEV1E_REG27D 0x27d -+#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0) -+ -+#define MTK_PHY_RG_DEV1E_REG2C7 0x2c7 -+#define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0) -+#define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8) -+ -+#define MTK_PHY_RG_DEV1E_REG2D1 0x2d1 -+#define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0) -+#define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8) -+#define MTK_PHY_LPI_TR_READY BIT(9) -+#define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10) -+ -+#define MTK_PHY_RG_DEV1E_REG323 0x323 -+#define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0) -+#define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4) -+ -+#define MTK_PHY_RG_DEV1E_REG324 0x324 -+#define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0) -+#define MTK_PHY_SMI_DET_MAX_EN BIT(8) -+ -+#define MTK_PHY_RG_DEV1E_REG326 0x326 -+#define MTK_PHY_LPI_MODE_SD_ON BIT(0) -+#define MTK_PHY_RESET_RANDUPD_CNT BIT(1) -+#define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2) -+#define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4) -+#define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5) -+ -+#define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502 -+#define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503 -+ -+#define MTK_PHY_DA_TX_R50_PAIR_A 0x53d -+#define MTK_PHY_DA_TX_R50_PAIR_B 0x53e -+#define MTK_PHY_DA_TX_R50_PAIR_C 0x53f -+#define MTK_PHY_DA_TX_R50_PAIR_D 0x540 -+ -+#define MTK_PHY_RG_BG_RASEL 0x115 -+#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) -+ -+/* These macro privides efuse parsing for internal phy. */ -+#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) -+#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) -+#define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0)) -+#define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0)) -+#define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0)) -+ -+#define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0)) -+#define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0)) -+#define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0)) -+#define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0)) -+#define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0)) -+ -+#define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0)) -+#define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0)) -+ -+#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0)) -+#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0)) -+ -+enum { -+ NO_PAIR, -+ PAIR_A, -+ PAIR_B, -+ PAIR_C, -+ PAIR_D, -+}; -+ -+enum { -+ GPHY_PORT0, -+ GPHY_PORT1, -+ GPHY_PORT2, -+ GPHY_PORT3, -+}; -+ -+enum calibration_mode { -+ EFUSE_K, -+ SW_K -+}; -+ -+enum CAL_ITEM { -+ REXT, -+ TX_OFFSET, -+ TX_AMP, -+ TX_R50, -+ TX_VCM -+}; -+ -+enum CAL_MODE { -+ EFUSE_M, -+ SW_M -+}; -+ -+static int mtk_socphy_read_page(struct phy_device *phydev) -+{ -+ return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); -+} -+ -+static int mtk_socphy_write_page(struct phy_device *phydev, int page) -+{ -+ return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); -+} -+ -+/* One calibration cycle consists of: -+ * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high -+ * until AD_CAL_COMP is ready to output calibration result. -+ * 2.Wait until DA_CAL_CLK is available. -+ * 3.Fetch AD_CAL_COMP_OUT. -+ */ -+static int cal_cycle(struct phy_device *phydev, int devad, -+ u32 regnum, u16 mask, u16 cal_val) -+{ -+ int reg_val; -+ int ret; -+ -+ phy_modify_mmd(phydev, devad, regnum, -+ mask, cal_val); -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, -+ MTK_PHY_DA_CALIN_FLAG); -+ -+ ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_AD_CAL_CLK, reg_val, -+ reg_val & MTK_PHY_DA_CAL_CLK, 500, -+ ANALOG_INTERNAL_OPERATION_MAX_US, false); -+ if (ret) { -+ phydev_err(phydev, "Calibration cycle timeout\n"); -+ return ret; -+ } -+ -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, -+ MTK_PHY_DA_CALIN_FLAG); -+ ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP) >> -+ MTK_PHY_AD_CAL_COMP_OUT_SHIFT; -+ phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); -+ -+ return ret; -+} -+ -+static int rext_fill_result(struct phy_device *phydev, u16 *buf) -+{ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, -+ MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, -+ MTK_PHY_RG_BG_RASEL_MASK, buf[1]); -+ -+ return 0; -+} -+ -+static int rext_cal_efuse(struct phy_device *phydev, u32 *buf) -+{ -+ u16 rext_cal_val[2]; -+ -+ rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); -+ rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]); -+ rext_fill_result(phydev, rext_cal_val); -+ -+ return 0; -+} -+ -+static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf) -+{ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, -+ MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, -+ MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, -+ MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, -+ MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]); -+ -+ return 0; -+} -+ -+static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf) -+{ -+ u16 tx_offset_cal_val[4]; -+ -+ tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]); -+ tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]); -+ tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]); -+ tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]); -+ -+ tx_offset_fill_result(phydev, tx_offset_cal_val); -+ -+ return 0; -+} -+ -+static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) -+{ -+ int i; -+ int bias[16] = {}; -+ const int vals_9461[16] = { 7, 1, 4, 7, -+ 7, 1, 4, 7, -+ 7, 1, 4, 7, -+ 7, 1, 4, 7 }; -+ const int vals_9481[16] = { 10, 6, 6, 10, -+ 10, 6, 6, 10, -+ 10, 6, 6, 10, -+ 10, 6, 6, 10 }; -+ switch (phydev->drv->phy_id) { -+ case MTK_GPHY_ID_MT7981: -+ /* We add some calibration to efuse values -+ * due to board level influence. -+ * GBE: +7, TBT: +1, HBT: +4, TST: +7 -+ */ -+ memcpy(bias, (const void *)vals_9461, sizeof(bias)); -+ break; -+ case MTK_GPHY_ID_MT7988: -+ memcpy(bias, (const void *)vals_9481, sizeof(bias)); -+ break; -+ } -+ -+ /* Prevent overflow */ -+ for (i = 0; i < 12; i++) { -+ if (buf[i >> 2] + bias[i] > 63) { -+ buf[i >> 2] = 63; -+ bias[i] = 0; -+ } -+ } -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, -+ MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, (buf[0] + bias[0]) << 10); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, -+ MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, buf[0] + bias[1]); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, -+ MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, (buf[0] + bias[2]) << 10); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, -+ MTK_PHY_DA_TX_I2MPB_A_TST_MASK, buf[0] + bias[3]); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, -+ MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, (buf[1] + bias[4]) << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, -+ MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, buf[1] + bias[5]); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, -+ MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, (buf[1] + bias[6]) << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, -+ MTK_PHY_DA_TX_I2MPB_B_TST_MASK, buf[1] + bias[7]); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, -+ MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, (buf[2] + bias[8]) << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, -+ MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, buf[2] + bias[9]); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, -+ MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, (buf[2] + bias[10]) << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, -+ MTK_PHY_DA_TX_I2MPB_C_TST_MASK, buf[2] + bias[11]); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, -+ MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, (buf[3] + bias[12]) << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, -+ MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, buf[3] + bias[13]); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, -+ MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, (buf[3] + bias[14]) << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, -+ MTK_PHY_DA_TX_I2MPB_D_TST_MASK, buf[3] + bias[15]); -+ -+ return 0; -+} -+ -+static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf) -+{ -+ u16 tx_amp_cal_val[4]; -+ -+ tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]); -+ tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]); -+ tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]); -+ tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]); -+ tx_amp_fill_result(phydev, tx_amp_cal_val); -+ -+ return 0; -+} -+ -+static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val, -+ u8 txg_calen_x) -+{ -+ int bias = 0; -+ u16 reg, val; -+ -+ if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988) -+ bias = -2; -+ -+ val = clamp_val(bias + tx_r50_cal_val, 0, 63); -+ -+ switch (txg_calen_x) { -+ case PAIR_A: -+ reg = MTK_PHY_DA_TX_R50_PAIR_A; -+ break; -+ case PAIR_B: -+ reg = MTK_PHY_DA_TX_R50_PAIR_B; -+ break; -+ case PAIR_C: -+ reg = MTK_PHY_DA_TX_R50_PAIR_C; -+ break; -+ case PAIR_D: -+ reg = MTK_PHY_DA_TX_R50_PAIR_D; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); -+ -+ return 0; -+} -+ -+static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf, -+ u8 txg_calen_x) -+{ -+ u16 tx_r50_cal_val; -+ -+ switch (txg_calen_x) { -+ case PAIR_A: -+ tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]); -+ break; -+ case PAIR_B: -+ tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]); -+ break; -+ case PAIR_C: -+ tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]); -+ break; -+ case PAIR_D: -+ tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]); -+ break; -+ default: -+ return -EINVAL; -+ } -+ tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); -+ -+ return 0; -+} -+ -+static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x) -+{ -+ u8 lower_idx, upper_idx, txreserve_val; -+ u8 lower_ret, upper_ret; -+ int ret; -+ -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, -+ MTK_PHY_RG_ANA_CALEN); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, -+ MTK_PHY_RG_CAL_CKINV); -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, -+ MTK_PHY_RG_TXVOS_CALEN); -+ -+ switch (rg_txreserve_x) { -+ case PAIR_A: -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN0_A, -+ MTK_PHY_DASN_DAC_IN0_A_MASK); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN1_A, -+ MTK_PHY_DASN_DAC_IN1_A_MASK); -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_ANA_CAL_RG0, -+ MTK_PHY_RG_ZCALEN_A); -+ break; -+ case PAIR_B: -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN0_B, -+ MTK_PHY_DASN_DAC_IN0_B_MASK); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN1_B, -+ MTK_PHY_DASN_DAC_IN1_B_MASK); -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_ANA_CAL_RG1, -+ MTK_PHY_RG_ZCALEN_B); -+ break; -+ case PAIR_C: -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN0_C, -+ MTK_PHY_DASN_DAC_IN0_C_MASK); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN1_C, -+ MTK_PHY_DASN_DAC_IN1_C_MASK); -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_ANA_CAL_RG1, -+ MTK_PHY_RG_ZCALEN_C); -+ break; -+ case PAIR_D: -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN0_D, -+ MTK_PHY_DASN_DAC_IN0_D_MASK); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DASN_DAC_IN1_D, -+ MTK_PHY_DASN_DAC_IN1_D_MASK); -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_ANA_CAL_RG1, -+ MTK_PHY_RG_ZCALEN_D); -+ break; -+ default: -+ ret = -EINVAL; -+ goto restore; -+ } -+ -+ lower_idx = TXRESERVE_MIN; -+ upper_idx = TXRESERVE_MAX; -+ -+ phydev_dbg(phydev, "Start TX-VCM SW cal.\n"); -+ while ((upper_idx - lower_idx) > 1) { -+ txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2); -+ ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, -+ MTK_PHY_DA_RX_PSBN_TBT_MASK | -+ MTK_PHY_DA_RX_PSBN_HBT_MASK | -+ MTK_PHY_DA_RX_PSBN_GBE_MASK | -+ MTK_PHY_DA_RX_PSBN_LP_MASK, -+ txreserve_val << 12 | txreserve_val << 8 | -+ txreserve_val << 4 | txreserve_val); -+ if (ret == 1) { -+ upper_idx = txreserve_val; -+ upper_ret = ret; -+ } else if (ret == 0) { -+ lower_idx = txreserve_val; -+ lower_ret = ret; -+ } else { -+ goto restore; -+ } -+ } -+ -+ if (lower_idx == TXRESERVE_MIN) { -+ lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RXADC_CTRL_RG9, -+ MTK_PHY_DA_RX_PSBN_TBT_MASK | -+ MTK_PHY_DA_RX_PSBN_HBT_MASK | -+ MTK_PHY_DA_RX_PSBN_GBE_MASK | -+ MTK_PHY_DA_RX_PSBN_LP_MASK, -+ lower_idx << 12 | lower_idx << 8 | -+ lower_idx << 4 | lower_idx); -+ ret = lower_ret; -+ } else if (upper_idx == TXRESERVE_MAX) { -+ upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RXADC_CTRL_RG9, -+ MTK_PHY_DA_RX_PSBN_TBT_MASK | -+ MTK_PHY_DA_RX_PSBN_HBT_MASK | -+ MTK_PHY_DA_RX_PSBN_GBE_MASK | -+ MTK_PHY_DA_RX_PSBN_LP_MASK, -+ upper_idx << 12 | upper_idx << 8 | -+ upper_idx << 4 | upper_idx); -+ ret = upper_ret; -+ } -+ if (ret < 0) -+ goto restore; -+ -+ /* We calibrate TX-VCM in different logic. Check upper index and then -+ * lower index. If this calibration is valid, apply lower index's result. -+ */ -+ ret = upper_ret - lower_ret; -+ if (ret == 1) { -+ ret = 0; -+ /* Make sure we use upper_idx in our calibration system */ -+ cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, -+ MTK_PHY_DA_RX_PSBN_TBT_MASK | -+ MTK_PHY_DA_RX_PSBN_HBT_MASK | -+ MTK_PHY_DA_RX_PSBN_GBE_MASK | -+ MTK_PHY_DA_RX_PSBN_LP_MASK, -+ upper_idx << 12 | upper_idx << 8 | -+ upper_idx << 4 | upper_idx); -+ phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx); -+ } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 && -+ lower_ret == 1) { -+ ret = 0; -+ cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, -+ MTK_PHY_DA_RX_PSBN_TBT_MASK | -+ MTK_PHY_DA_RX_PSBN_HBT_MASK | -+ MTK_PHY_DA_RX_PSBN_GBE_MASK | -+ MTK_PHY_DA_RX_PSBN_LP_MASK, -+ lower_idx << 12 | lower_idx << 8 | -+ lower_idx << 4 | lower_idx); -+ phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n", -+ lower_idx); -+ } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && -+ lower_ret == 0) { -+ ret = 0; -+ phydev_warn(phydev, "TX-VCM SW cal result at high margin 0x%x\n", -+ upper_idx); -+ } else { -+ ret = -EINVAL; -+ } -+ -+restore: -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, -+ MTK_PHY_RG_ANA_CALEN); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, -+ MTK_PHY_RG_TXVOS_CALEN); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, -+ MTK_PHY_RG_ZCALEN_A); -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, -+ MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C | -+ MTK_PHY_RG_ZCALEN_D); -+ -+ return ret; -+} -+ -+static void mt798x_phy_common_finetune(struct phy_device *phydev) -+{ -+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); -+ /* EnabRandUpdTrig = 1 */ -+ __phy_write(phydev, 0x11, 0x2f00); -+ __phy_write(phydev, 0x12, 0xe); -+ __phy_write(phydev, 0x10, 0x8fb0); -+ -+ /* NormMseLoThresh = 85 */ -+ __phy_write(phydev, 0x11, 0x55a0); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x83aa); -+ -+ /* TrFreeze = 0 */ -+ __phy_write(phydev, 0x11, 0x0); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x9686); -+ -+ /* SSTrKp1000Slv = 5 */ -+ __phy_write(phydev, 0x11, 0xbaef); -+ __phy_write(phydev, 0x12, 0x2e); -+ __phy_write(phydev, 0x10, 0x968c); -+ -+ /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, -+ * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 -+ */ -+ __phy_write(phydev, 0x11, 0xd10a); -+ __phy_write(phydev, 0x12, 0x34); -+ __phy_write(phydev, 0x10, 0x8f82); -+ -+ /* VcoSlicerThreshBitsHigh */ -+ __phy_write(phydev, 0x11, 0x5555); -+ __phy_write(phydev, 0x12, 0x55); -+ __phy_write(phydev, 0x10, 0x8ec0); -+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -+ -+ /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, -+ MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK, -+ BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); -+ -+ /* rg_tr_lpf_cnt_val = 512 */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); -+ -+ /* IIR2 related */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); -+ -+ /* FFE peaking */ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, -+ MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, -+ MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); -+ -+ /* Disable LDO pump */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); -+ /* Adjust LDO output voltage */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); -+} -+ -+static void mt7981_phy_finetune(struct phy_device *phydev) -+{ -+ u16 val[8] = { 0x01ce, 0x01c1, -+ 0x020f, 0x0202, -+ 0x03d0, 0x03c0, -+ 0x0013, 0x0005 }; -+ int i, k; -+ -+ /* 100M eye finetune: -+ * Keep middle level of TX MLT3 shapper as default. -+ * Only change TX MLT3 overshoot level here. -+ */ -+ for (k = 0, i = 1; i < 12; i++) { -+ if (i % 3 == 0) -+ continue; -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); -+ } -+ -+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); -+ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */ -+ __phy_write(phydev, 0x11, 0xc71); -+ __phy_write(phydev, 0x12, 0xc); -+ __phy_write(phydev, 0x10, 0x8fae); -+ -+ /* ResetSyncOffset = 6 */ -+ __phy_write(phydev, 0x11, 0x600); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x8fc0); -+ -+ /* VgaDecRate = 1 */ -+ __phy_write(phydev, 0x11, 0x4c2a); -+ __phy_write(phydev, 0x12, 0x3e); -+ __phy_write(phydev, 0x10, 0x8fa4); -+ -+ /* FfeUpdGainForce = 4 */ -+ __phy_write(phydev, 0x11, 0x240); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x9680); -+ -+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -+} -+ -+static void mt7988_phy_finetune(struct phy_device *phydev) -+{ -+ u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, -+ 0x020d, 0x0206, 0x0384, 0x03d0, -+ 0x03c6, 0x030a, 0x0011, 0x0005 }; -+ int i; -+ -+ /* Set default MLT3 shaper first */ -+ for (i = 0; i < 12; i++) -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]); -+ -+ /* TCT finetune */ -+ phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); -+ -+ /* Disable TX power saving */ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, -+ MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); -+ -+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); -+ -+ /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */ -+ __phy_write(phydev, 0x11, 0x671); -+ __phy_write(phydev, 0x12, 0xc); -+ __phy_write(phydev, 0x10, 0x8fae); -+ -+ /* ResetSyncOffset = 5 */ -+ __phy_write(phydev, 0x11, 0x500); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x8fc0); -+ -+ /* VgaDecRate is 1 at default on mt7988 */ -+ -+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -+ -+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30); -+ /* TxClkOffset = 2 */ -+ __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK, -+ FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2)); -+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -+} -+ -+static void mt798x_phy_eee(struct phy_device *phydev) -+{ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120, -+ MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK | -+ MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, -+ FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) | -+ FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14)); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, -+ MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, -+ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, -+ 0xff)); -+ -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_TESTMUX_ADC_CTRL, -+ MTK_PHY_RG_TXEN_DIG_MASK); -+ -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY); -+ -+ phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238, -+ MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK | -+ MTK_PHY_LPI_SLV_SEND_TX_EN, -+ FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, -+ MTK_PHY_LPI_SEND_LOC_TIMER_MASK | -+ MTK_PHY_LPI_TXPCS_LOC_RCV, -+ FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117)); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, -+ MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK, -+ FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | -+ FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13)); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1, -+ MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, -+ FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, -+ 0x33) | -+ MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY | -+ MTK_PHY_LPI_VCO_EEE_STG0_EN); -+ -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, -+ MTK_PHY_EEE_WAKE_MAS_INT_DC | -+ MTK_PHY_EEE_WAKE_SLV_INT_DC); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324, -+ MTK_PHY_SMI_DETCNT_MAX_MASK, -+ FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) | -+ MTK_PHY_SMI_DET_MAX_EN); -+ -+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326, -+ MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT | -+ MTK_PHY_TREC_UPDATE_ENAB_CLR | -+ MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF | -+ MTK_PHY_TR_READY_SKIP_AFE_WAKEUP); -+ -+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); -+ /* Regsigdet_sel_1000 = 0 */ -+ __phy_write(phydev, 0x11, 0xb); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x9690); -+ -+ /* REG_EEE_st2TrKf1000 = 3 */ -+ __phy_write(phydev, 0x11, 0x114f); -+ __phy_write(phydev, 0x12, 0x2); -+ __phy_write(phydev, 0x10, 0x969a); -+ -+ /* RegEEE_slv_wake_tr_timer_tar = 6, RegEEE_slv_remtx_timer_tar = 20 */ -+ __phy_write(phydev, 0x11, 0x3028); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x969e); -+ -+ /* RegEEE_slv_wake_int_timer_tar = 8 */ -+ __phy_write(phydev, 0x11, 0x5010); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x96a0); -+ -+ /* RegEEE_trfreeze_timer2 = 586 */ -+ __phy_write(phydev, 0x11, 0x24a); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x96a8); -+ -+ /* RegEEE100Stg1_tar = 16 */ -+ __phy_write(phydev, 0x11, 0x3210); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x96b8); -+ -+ /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */ -+ __phy_write(phydev, 0x11, 0x1463); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x96ca); -+ -+ /* DfeTailEnableVgaThresh1000 = 27 */ -+ __phy_write(phydev, 0x11, 0x36); -+ __phy_write(phydev, 0x12, 0x0); -+ __phy_write(phydev, 0x10, 0x8f80); -+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -+ -+ phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); -+ __phy_modify(phydev, MTK_PHY_LPI_REG_14, MTK_PHY_LPI_WAKE_TIMER_1000_MASK, -+ FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c)); -+ -+ __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK, -+ FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc)); -+ phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); -+ -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, -+ MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, -+ MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, -+ FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 0xff)); -+} -+ -+static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item, -+ u8 start_pair, u8 end_pair) -+{ -+ u8 pair_n; -+ int ret; -+ -+ for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { -+ /* TX_OFFSET & TX_AMP have no SW calibration. */ -+ switch (cal_item) { -+ case TX_VCM: -+ ret = tx_vcm_cal_sw(phydev, pair_n); -+ break; -+ default: -+ return -EINVAL; -+ } -+ if (ret) -+ return ret; -+ } -+ return 0; -+} -+ -+static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item, -+ u8 start_pair, u8 end_pair, u32 *buf) -+{ -+ u8 pair_n; -+ int ret; -+ -+ for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { -+ /* TX_VCM has no efuse calibration. */ -+ switch (cal_item) { -+ case REXT: -+ ret = rext_cal_efuse(phydev, buf); -+ break; -+ case TX_OFFSET: -+ ret = tx_offset_cal_efuse(phydev, buf); -+ break; -+ case TX_AMP: -+ ret = tx_amp_cal_efuse(phydev, buf); -+ break; -+ case TX_R50: -+ ret = tx_r50_cal_efuse(phydev, buf, pair_n); -+ break; -+ default: -+ return -EINVAL; -+ } -+ if (ret) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item, -+ enum CAL_MODE cal_mode, u8 start_pair, -+ u8 end_pair, u32 *buf) -+{ -+ int ret; -+ -+ switch (cal_mode) { -+ case EFUSE_M: -+ ret = cal_efuse(phydev, cal_item, start_pair, -+ end_pair, buf); -+ break; -+ case SW_M: -+ ret = cal_sw(phydev, cal_item, start_pair, end_pair); -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ if (ret) { -+ phydev_err(phydev, "cal %d failed\n", cal_item); -+ return -EIO; -+ } -+ -+ return 0; -+} -+ -+static int mt798x_phy_calibration(struct phy_device *phydev) -+{ -+ int ret = 0; -+ u32 *buf; -+ size_t len; -+ struct nvmem_cell *cell; -+ -+ cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data"); -+ if (IS_ERR(cell)) { -+ if (PTR_ERR(cell) == -EPROBE_DEFER) -+ return PTR_ERR(cell); -+ return 0; -+ } -+ -+ buf = (u32 *)nvmem_cell_read(cell, &len); -+ if (IS_ERR(buf)) -+ return PTR_ERR(buf); -+ nvmem_cell_put(cell); -+ -+ if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) { -+ phydev_err(phydev, "invalid efuse data\n"); -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf); -+ if (ret) -+ goto out; -+ ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf); -+ if (ret) -+ goto out; -+ ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf); -+ if (ret) -+ goto out; -+ ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf); -+ if (ret) -+ goto out; -+ ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf); -+ if (ret) -+ goto out; -+ -+out: -+ kfree(buf); -+ return ret; -+} -+ -+static int mt798x_phy_config_init(struct phy_device *phydev) -+{ -+ switch (phydev->drv->phy_id) { -+ case MTK_GPHY_ID_MT7981: -+ mt7981_phy_finetune(phydev); -+ break; -+ case MTK_GPHY_ID_MT7988: -+ mt7988_phy_finetune(phydev); -+ break; -+ } -+ -+ mt798x_phy_common_finetune(phydev); -+ mt798x_phy_eee(phydev); -+ -+ return mt798x_phy_calibration(phydev); -+} -+ -+static struct phy_driver mtk_socphy_driver[] = { -+ { -+ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), -+ .name = "MediaTek MT7981 PHY", -+ .config_init = mt798x_phy_config_init, -+ .config_intr = genphy_no_config_intr, -+ .handle_interrupt = genphy_handle_interrupt_no_ack, -+ .probe = mt798x_phy_calibration, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ .read_page = mtk_socphy_read_page, -+ .write_page = mtk_socphy_write_page, -+ }, -+ { -+ PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), -+ .name = "MediaTek MT7988 PHY", -+ .config_init = mt798x_phy_config_init, -+ .config_intr = genphy_no_config_intr, -+ .handle_interrupt = genphy_handle_interrupt_no_ack, -+ .probe = mt798x_phy_calibration, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ .read_page = mtk_socphy_read_page, -+ .write_page = mtk_socphy_write_page, -+ }, -+}; -+ -+module_phy_driver(mtk_socphy_driver); -+ -+static struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = { -+ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) }, -+ { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) }, -+ { } -+}; -+ -+MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver"); -+MODULE_AUTHOR("Daniel Golle "); -+MODULE_AUTHOR("SkyLake Huang "); -+MODULE_LICENSE("GPL"); -+ -+MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl); ---- a/drivers/net/phy/mediatek-ge.c -+++ b/drivers/net/phy/mediatek-ge.c -@@ -136,7 +136,8 @@ static struct phy_driver mtk_gephy_drive - module_phy_driver(mtk_gephy_driver); - - static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = { -- { PHY_ID_MATCH_VENDOR(0x03a29400) }, -+ { PHY_ID_MATCH_EXACT(0x03a29441) }, -+ { PHY_ID_MATCH_EXACT(0x03a29412) }, - { } - }; - diff --git a/6.1/target/linux/mediatek/patches-6.1/731-net-phy-mediatek-ge-soc-initialize-MT7988-PHY-LEDs-d.patch b/6.1/target/linux/mediatek/patches-6.1/731-net-phy-mediatek-ge-soc-initialize-MT7988-PHY-LEDs-d.patch deleted file mode 100644 index 83d0f26b..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/731-net-phy-mediatek-ge-soc-initialize-MT7988-PHY-LEDs-d.patch +++ /dev/null @@ -1,213 +0,0 @@ -From 5d2d78860f98eb5c03bc404eb024606878901ac8 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 13 Jun 2023 03:27:14 +0100 -Subject: [PATCH] net: phy: mediatek-ge-soc: initialize MT7988 PHY LEDs default - state - -Initialize LEDs and set sane default values. -Read boottrap register and apply LED polarities accordingly to get -uniform behavior from all LEDs on MT7988. -Requires syscon phandle 'mediatek,pio' present in parenting MDIO bus -which should point to the syscon holding the boottrap register. - -Signed-off-by: Daniel Golle ---- - drivers/net/phy/mediatek-ge-soc.c | 144 ++++++++++++++++++++++++++++-- - 1 file changed, 136 insertions(+), 8 deletions(-) - ---- a/drivers/net/phy/mediatek-ge-soc.c -+++ b/drivers/net/phy/mediatek-ge-soc.c -@@ -1,11 +1,13 @@ - // SPDX-License-Identifier: GPL-2.0+ - #include -+#include - #include - #include - #include - #include - #include - #include -+#include - - #define MTK_GPHY_ID_MT7981 0x03a29461 - #define MTK_GPHY_ID_MT7988 0x03a29481 -@@ -208,9 +210,40 @@ - #define MTK_PHY_DA_TX_R50_PAIR_C 0x53f - #define MTK_PHY_DA_TX_R50_PAIR_D 0x540 - -+/* Registers on MDIO_MMD_VEND2 */ -+#define MTK_PHY_LED0_ON_CTRL 0x24 -+#define MTK_PHY_LED1_ON_CTRL 0x26 -+#define MTK_PHY_LED_ON_MASK GENMASK(6, 0) -+#define MTK_PHY_LED_ON_LINK1000 BIT(0) -+#define MTK_PHY_LED_ON_LINK100 BIT(1) -+#define MTK_PHY_LED_ON_LINK10 BIT(2) -+#define MTK_PHY_LED_ON_LINKDOWN BIT(3) -+#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */ -+#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */ -+#define MTK_PHY_LED_FORCE_ON BIT(6) -+#define MTK_PHY_LED_POLARITY BIT(14) -+#define MTK_PHY_LED_ENABLE BIT(15) -+ -+#define MTK_PHY_LED0_BLINK_CTRL 0x25 -+#define MTK_PHY_LED1_BLINK_CTRL 0x27 -+#define MTK_PHY_LED_1000TX BIT(0) -+#define MTK_PHY_LED_1000RX BIT(1) -+#define MTK_PHY_LED_100TX BIT(2) -+#define MTK_PHY_LED_100RX BIT(3) -+#define MTK_PHY_LED_10TX BIT(4) -+#define MTK_PHY_LED_10RX BIT(5) -+#define MTK_PHY_LED_COLLISION BIT(6) -+#define MTK_PHY_LED_RX_CRC_ERR BIT(7) -+#define MTK_PHY_LED_RX_IDLE_ERR BIT(8) -+#define MTK_PHY_LED_FORCE_BLINK BIT(9) -+ - #define MTK_PHY_RG_BG_RASEL 0x115 - #define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) - -+/* Register in boottrap syscon defining the initial state of the 4 PHY LEDs */ -+#define RG_GPIO_MISC_TPBANK0 0x6f0 -+#define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8) -+ - /* These macro privides efuse parsing for internal phy. */ - #define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) - #define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) -@@ -238,13 +271,6 @@ enum { - PAIR_D, - }; - --enum { -- GPHY_PORT0, -- GPHY_PORT1, -- GPHY_PORT2, -- GPHY_PORT3, --}; -- - enum calibration_mode { - EFUSE_K, - SW_K -@@ -263,6 +289,10 @@ enum CAL_MODE { - SW_M - }; - -+struct mtk_socphy_shared { -+ u32 boottrap; -+}; -+ - static int mtk_socphy_read_page(struct phy_device *phydev) - { - return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); -@@ -1073,6 +1103,104 @@ static int mt798x_phy_config_init(struct - return mt798x_phy_calibration(phydev); - } - -+static int mt798x_phy_setup_led(struct phy_device *phydev, bool inverted) -+{ -+ struct pinctrl *pinctrl; -+ const u16 led_on_ctrl_defaults = MTK_PHY_LED_ENABLE | -+ MTK_PHY_LED_ON_LINK1000 | -+ MTK_PHY_LED_ON_LINK100 | -+ MTK_PHY_LED_ON_LINK10; -+ const u16 led_blink_defaults = MTK_PHY_LED_1000TX | -+ MTK_PHY_LED_1000RX | -+ MTK_PHY_LED_100TX | -+ MTK_PHY_LED_100RX | -+ MTK_PHY_LED_10TX | -+ MTK_PHY_LED_10RX; -+ -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, -+ led_on_ctrl_defaults ^ -+ (inverted ? MTK_PHY_LED_POLARITY : 0)); -+ -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, -+ led_on_ctrl_defaults); -+ -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL, -+ led_blink_defaults); -+ -+ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_BLINK_CTRL, -+ led_blink_defaults); -+ -+ pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); -+ if (IS_ERR(pinctrl)) -+ dev_err(&phydev->mdio.bus->dev, "Failed to setup PHY LED\n"); -+ -+ return 0; -+} -+ -+static int mt7988_phy_probe_shared(struct phy_device *phydev) -+{ -+ struct device_node *np = dev_of_node(&phydev->mdio.bus->dev); -+ struct mtk_socphy_shared *priv = phydev->shared->priv; -+ struct regmap *regmap; -+ u32 reg; -+ int ret; -+ -+ /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B, -+ * LED_C and LED_D respectively. At the same time those pins are used to -+ * bootstrap configuration of the reference clock source (LED_A), -+ * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D). -+ * In practise this is done using a LED and a resistor pulling the pin -+ * either to GND or to VIO. -+ * The detected value at boot time is accessible at run-time using the -+ * TPBANK0 register located in the gpio base of the pinctrl, in order -+ * to read it here it needs to be referenced by a phandle called -+ * 'mediatek,pio' in the MDIO bus hosting the PHY. -+ * The 4 bits in TPBANK0 are kept as package shared data and are used to -+ * set LED polarity for each of the LED0. -+ */ -+ regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio"); -+ if (IS_ERR(regmap)) -+ return PTR_ERR(regmap); -+ -+ ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, ®); -+ if (ret) -+ return ret; -+ -+ priv->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg); -+ -+ return 0; -+} -+ -+static bool mt7988_phy_get_boottrap_polarity(struct phy_device *phydev) -+{ -+ struct mtk_socphy_shared *priv = phydev->shared->priv; -+ -+ if (priv->boottrap & BIT(phydev->mdio.addr)) -+ return false; -+ -+ return true; -+} -+ -+static int mt7988_phy_probe(struct phy_device *phydev) -+{ -+ int err; -+ -+ err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0, -+ sizeof(struct mtk_socphy_shared)); -+ if (err) -+ return err; -+ -+ if (phy_package_probe_once(phydev)) { -+ err = mt7988_phy_probe_shared(phydev); -+ if (err) -+ return err; -+ } -+ -+ mt798x_phy_setup_led(phydev, mt7988_phy_get_boottrap_polarity(phydev)); -+ -+ return mt798x_phy_calibration(phydev); -+} -+ - static struct phy_driver mtk_socphy_driver[] = { - { - PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), -@@ -1092,7 +1220,7 @@ static struct phy_driver mtk_socphy_driv - .config_init = mt798x_phy_config_init, - .config_intr = genphy_no_config_intr, - .handle_interrupt = genphy_handle_interrupt_no_ack, -- .probe = mt798x_phy_calibration, -+ .probe = mt7988_phy_probe, - .suspend = genphy_suspend, - .resume = genphy_resume, - .read_page = mtk_socphy_read_page, diff --git a/6.1/target/linux/mediatek/patches-6.1/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch b/6.1/target/linux/mediatek/patches-6.1/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch deleted file mode 100644 index d7457273..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/732-net-phy-mxl-gpy-don-t-use-SGMII-AN-if-using-phylink.patch +++ /dev/null @@ -1,63 +0,0 @@ -From a969b663c866129ed9eb217785a6574fbe826f1d Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Thu, 6 Apr 2023 23:36:50 +0100 -Subject: [PATCH] net: phy: mxl-gpy: don't use SGMII AN if using phylink - -MAC drivers using phylink expect SGMII in-band-status to be switched off -when attached to a PHY. Make sure this is the case also for mxl-gpy which -keeps SGMII in-band-status in case of SGMII interface mode is used. - -Signed-off-by: Daniel Golle ---- - drivers/net/phy/mxl-gpy.c | 19 ++++++++++++++++--- - 1 file changed, 16 insertions(+), 3 deletions(-) - ---- a/drivers/net/phy/mxl-gpy.c -+++ b/drivers/net/phy/mxl-gpy.c -@@ -367,8 +367,11 @@ static bool gpy_2500basex_chk(struct phy - - phydev->speed = SPEED_2500; - phydev->interface = PHY_INTERFACE_MODE_2500BASEX; -- phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, -- VSPEC1_SGMII_CTRL_ANEN, 0); -+ -+ if (!phydev->phylink) -+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, -+ VSPEC1_SGMII_CTRL_ANEN, 0); -+ - return true; - } - -@@ -392,6 +395,14 @@ static int gpy_config_aneg(struct phy_de - u32 adv; - int ret; - -+ /* Disable SGMII auto-negotiation if using phylink */ -+ if (phydev->phylink) { -+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, -+ VSPEC1_SGMII_CTRL_ANEN, 0); -+ if (ret < 0) -+ return ret; -+ } -+ - if (phydev->autoneg == AUTONEG_DISABLE) { - /* Configure half duplex with genphy_setup_forced, - * because genphy_c45_pma_setup_forced does not support. -@@ -482,6 +493,8 @@ static void gpy_update_interface(struct - switch (phydev->speed) { - case SPEED_2500: - phydev->interface = PHY_INTERFACE_MODE_2500BASEX; -+ if (phydev->phylink) -+ break; - ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL, - VSPEC1_SGMII_CTRL_ANEN, 0); - if (ret < 0) -@@ -493,7 +506,7 @@ static void gpy_update_interface(struct - case SPEED_100: - case SPEED_10: - phydev->interface = PHY_INTERFACE_MODE_SGMII; -- if (gpy_sgmii_aneg_en(phydev)) -+ if (phydev->phylink || gpy_sgmii_aneg_en(phydev)) - break; - /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed - * if ANEG is disabled (in 2500-BaseX mode). diff --git a/6.1/target/linux/mediatek/patches-6.1/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch b/6.1/target/linux/mediatek/patches-6.1/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch deleted file mode 100644 index c3baafa2..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/733-net-phy-add-driver-for-MediaTek-2.5G-PHY.patch +++ /dev/null @@ -1,39 +0,0 @@ -From 128dc09b0af36772062142ce9e85b19c84ac789a Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Tue, 28 Feb 2023 17:53:37 +0000 -Subject: [PATCH] net: phy: add driver for MediaTek 2.5G PHY - -Signed-off-by: Daniel Golle ---- - drivers/net/phy/Kconfig | 7 ++ - drivers/net/phy/Makefile | 1 + - drivers/net/phy/mediatek-2p5ge.c | 220 +++++++++++++++++++++++++++++++ - 3 files changed, 226 insertions(+) - create mode 100644 drivers/net/phy/mediatek-2p5ge.c - ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -319,6 +319,13 @@ config MEDIATEK_GE_SOC_PHY - present in the SoCs efuse and will dynamically calibrate VCM - (common-mode voltage) during startup. - -+config MEDIATEK_2P5G_PHY -+ tristate "MediaTek 2.5G Ethernet PHY" -+ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST -+ default NET_MEDIATEK_SOC -+ help -+ Supports the MediaTek 2.5G Ethernet PHY. -+ - config MICREL_PHY - tristate "Micrel PHYs" - depends on PTP_1588_CLOCK_OPTIONAL ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -83,6 +83,7 @@ obj-$(CONFIG_MARVELL_10G_PHY) += marvell - obj-$(CONFIG_MARVELL_PHY) += marvell.o - obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o - obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o -+obj-$(CONFIG_MEDIATEK_2P5G_PHY) += mediatek-2p5ge.o - obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o - obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o - obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o diff --git a/6.1/target/linux/mediatek/patches-6.1/804-pwm-add-mt7986-support.patch b/6.1/target/linux/mediatek/patches-6.1/804-pwm-add-mt7986-support.patch deleted file mode 100644 index 0c73d520..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/804-pwm-add-mt7986-support.patch +++ /dev/null @@ -1,23 +0,0 @@ ---- a/drivers/pwm/pwm-mediatek.c -+++ b/drivers/pwm/pwm-mediatek.c -@@ -329,6 +329,12 @@ static const struct pwm_mediatek_of_data - .has_ck_26m_sel = true, - }; - -+static const struct pwm_mediatek_of_data mt7986_pwm_data = { -+ .num_pwms = 2, -+ .pwm45_fixup = false, -+ .has_ck_26m_sel = true, -+}; -+ - static const struct pwm_mediatek_of_data mt8516_pwm_data = { - .num_pwms = 5, - .pwm45_fixup = false, -@@ -342,6 +348,7 @@ static const struct of_device_id pwm_med - { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, - { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data }, - { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data }, -+ { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data }, - { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data }, - { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data }, - { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data }, diff --git a/6.1/target/linux/mediatek/patches-6.1/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch b/6.1/target/linux/mediatek/patches-6.1/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch deleted file mode 100644 index b142b22e..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/805-v6.2-thermal-drivers-mtk-use-function-pointer-for-raw_to_.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 69c17529e8418da3eec703dde31e1b01e5b0f7e8 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Wed, 18 Jan 2023 02:48:41 +0000 -Subject: [PATCH 1/2] thermal/drivers/mtk: use function pointer for - raw_to_mcelsius - -Instead of having if-else logic selecting either raw_to_mcelsius_v1 or -raw_to_mcelsius_v2 in mtk_thermal_bank_temperature introduce a function -pointer raw_to_mcelsius to struct mtk_thermal which is initialized in the -probe function. - -Signed-off-by: Daniel Golle ---- - drivers/thermal/mtk_thermal.c | 17 ++++++++++------- - 1 file changed, 10 insertions(+), 7 deletions(-) - ---- a/drivers/thermal/mtk_thermal.c -+++ b/drivers/thermal/mtk_thermal.c -@@ -292,6 +292,8 @@ struct mtk_thermal { - - const struct mtk_thermal_data *conf; - struct mtk_thermal_bank banks[MAX_NUM_ZONES]; -+ -+ int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw); - }; - - /* MT8183 thermal sensor data */ -@@ -656,13 +658,9 @@ static int mtk_thermal_bank_temperature( - for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) { - raw = readl(mt->thermal_base + conf->msr[i]); - -- if (mt->conf->version == MTK_THERMAL_V1) { -- temp = raw_to_mcelsius_v1( -- mt, conf->bank_data[bank->id].sensors[i], raw); -- } else { -- temp = raw_to_mcelsius_v2( -- mt, conf->bank_data[bank->id].sensors[i], raw); -- } -+ temp = mt->raw_to_mcelsius( -+ mt, conf->bank_data[bank->id].sensors[i], raw); -+ - - /* - * The first read of a sensor often contains very high bogus -@@ -1085,6 +1083,11 @@ static int mtk_thermal_probe(struct plat - mtk_thermal_release_periodic_ts(mt, auxadc_base); - } - -+ if (mt->conf->version == MTK_THERMAL_V1) -+ mt->raw_to_mcelsius = raw_to_mcelsius_v1; -+ else -+ mt->raw_to_mcelsius = raw_to_mcelsius_v2; -+ - for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++) - for (i = 0; i < mt->conf->num_banks; i++) - mtk_thermal_init_bank(mt, i, apmixed_phys_base, diff --git a/6.1/target/linux/mediatek/patches-6.1/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch b/6.1/target/linux/mediatek/patches-6.1/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch deleted file mode 100644 index 3ac2e7fc..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/806-v6.2-thermal-mediatek-add-support-for-MT7986-and-MT7981.patch +++ /dev/null @@ -1,240 +0,0 @@ -From aa957c759b1182aee00cc35178667f849f941b42 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Wed, 30 Nov 2022 13:19:39 +0000 -Subject: [PATCH 2/2] thermal: mediatek: add support for MT7986 and MT7981 - -Add support for V3 generation thermal found in MT7986 and MT7981 SoCs. -Brings code to assign values from efuse as well as new function to -convert raw temperature to millidegree celsius, as found in MediaTek's -SDK sources (but cleaned up and de-duplicated) - -[1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/baf36c7eef477aae1f8f2653b6c29e2caf48475b -Signed-off-by: Daniel Golle ---- - drivers/thermal/mtk_thermal.c | 137 ++++++++++++++++++++++++++++++++-- - 1 file changed, 132 insertions(+), 5 deletions(-) - ---- a/drivers/thermal/mtk_thermal.c -+++ b/drivers/thermal/mtk_thermal.c -@@ -150,6 +150,20 @@ - #define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1) - #define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1) - -+/* -+ * Layout of the fuses providing the calibration data -+ * These macros can be used for MT7981 and MT7986. -+ */ -+#define CALIB_BUF0_ADC_GE_V3(x) (((x) >> 0) & 0x3ff) -+#define CALIB_BUF0_DEGC_CALI_V3(x) (((x) >> 20) & 0x3f) -+#define CALIB_BUF0_O_SLOPE_V3(x) (((x) >> 26) & 0x3f) -+#define CALIB_BUF1_VTS_TS1_V3(x) (((x) >> 0) & 0x1ff) -+#define CALIB_BUF1_VTS_TS2_V3(x) (((x) >> 21) & 0x1ff) -+#define CALIB_BUF1_VTS_TSABB_V3(x) (((x) >> 9) & 0x1ff) -+#define CALIB_BUF1_VALID_V3(x) (((x) >> 18) & 0x1) -+#define CALIB_BUF1_O_SLOPE_SIGN_V3(x) (((x) >> 19) & 0x1) -+#define CALIB_BUF1_ID_V3(x) (((x) >> 20) & 0x1) -+ - enum { - VTS1, - VTS2, -@@ -163,6 +177,7 @@ enum { - enum mtk_thermal_version { - MTK_THERMAL_V1 = 1, - MTK_THERMAL_V2, -+ MTK_THERMAL_V3, - }; - - /* MT2701 thermal sensors */ -@@ -245,6 +260,27 @@ enum mtk_thermal_version { - /* The calibration coefficient of sensor */ - #define MT8183_CALIBRATION 153 - -+/* AUXADC channel 11 is used for the temperature sensors */ -+#define MT7986_TEMP_AUXADC_CHANNEL 11 -+ -+/* The total number of temperature sensors in the MT7986 */ -+#define MT7986_NUM_SENSORS 1 -+ -+/* The number of banks in the MT7986 */ -+#define MT7986_NUM_ZONES 1 -+ -+/* The number of sensing points per bank */ -+#define MT7986_NUM_SENSORS_PER_ZONE 1 -+ -+/* MT7986 thermal sensors */ -+#define MT7986_TS1 0 -+ -+/* The number of controller in the MT7986 */ -+#define MT7986_NUM_CONTROLLER 1 -+ -+/* The calibration coefficient of sensor */ -+#define MT7986_CALIBRATION 165 -+ - struct mtk_thermal; - - struct thermal_bank_cfg { -@@ -388,6 +424,14 @@ static const int mt7622_mux_values[MT762 - static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 }; - static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, }; - -+/* MT7986 thermal sensor data */ -+static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, }; -+static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, }; -+static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, }; -+static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, }; -+static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 }; -+static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, }; -+ - /* - * The MT8173 thermal controller has four banks. Each bank can read up to - * four temperature sensors simultaneously. The MT8173 has a total of 5 -@@ -551,6 +595,30 @@ static const struct mtk_thermal_data mt8 - .version = MTK_THERMAL_V1, - }; - -+/* -+ * MT7986 uses AUXADC Channel 11 for raw data access. -+ */ -+static const struct mtk_thermal_data mt7986_thermal_data = { -+ .auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL, -+ .num_banks = MT7986_NUM_ZONES, -+ .num_sensors = MT7986_NUM_SENSORS, -+ .vts_index = mt7986_vts_index, -+ .cali_val = MT7986_CALIBRATION, -+ .num_controller = MT7986_NUM_CONTROLLER, -+ .controller_offset = mt7986_tc_offset, -+ .need_switch_bank = true, -+ .bank_data = { -+ { -+ .num_sensors = 1, -+ .sensors = mt7986_bank_data, -+ }, -+ }, -+ .msr = mt7986_msr, -+ .adcpnp = mt7986_adcpnp, -+ .sensor_mux_values = mt7986_mux_values, -+ .version = MTK_THERMAL_V3, -+}; -+ - /** - * raw_to_mcelsius - convert a raw ADC value to mcelsius - * @mt: The thermal controller -@@ -605,6 +673,22 @@ static int raw_to_mcelsius_v2(struct mtk - return (format_2 - tmp) * 100; - } - -+static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw) -+{ -+ s32 tmp; -+ -+ if (raw == 0) -+ return 0; -+ -+ raw &= 0xfff; -+ tmp = 100000 * 15 / 16 * 10000; -+ tmp /= 4096 - 512 + mt->adc_ge; -+ tmp /= 1490; -+ tmp *= raw - mt->vts[sensno] - 2900; -+ -+ return mt->degc_cali * 500 - tmp; -+} -+ - /** - * mtk_thermal_get_bank - get bank - * @bank: The bank -@@ -885,6 +969,25 @@ static int mtk_thermal_extract_efuse_v2( - return 0; - } - -+static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf) -+{ -+ if (!CALIB_BUF1_VALID_V3(buf[1])) -+ return -EINVAL; -+ -+ mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]); -+ mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]); -+ mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]); -+ mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]); -+ mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]); -+ mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]); -+ mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]); -+ -+ if (CALIB_BUF1_ID_V3(buf[1]) == 0) -+ mt->o_slope = 0; -+ -+ return 0; -+} -+ - static int mtk_thermal_get_calibration_data(struct device *dev, - struct mtk_thermal *mt) - { -@@ -895,6 +998,7 @@ static int mtk_thermal_get_calibration_d - - /* Start with default values */ - mt->adc_ge = 512; -+ mt->adc_oe = 512; - for (i = 0; i < mt->conf->num_sensors; i++) - mt->vts[i] = 260; - mt->degc_cali = 40; -@@ -920,10 +1024,20 @@ static int mtk_thermal_get_calibration_d - goto out; - } - -- if (mt->conf->version == MTK_THERMAL_V1) -+ switch (mt->conf->version) { -+ case MTK_THERMAL_V1: - ret = mtk_thermal_extract_efuse_v1(mt, buf); -- else -+ break; -+ case MTK_THERMAL_V2: - ret = mtk_thermal_extract_efuse_v2(mt, buf); -+ break; -+ case MTK_THERMAL_V3: -+ ret = mtk_thermal_extract_efuse_v3(mt, buf); -+ break; -+ default: -+ ret = -EINVAL; -+ break; -+ } - - if (ret) { - dev_info(dev, "Device not calibrated, using default calibration values\n"); -@@ -954,6 +1068,10 @@ static const struct of_device_id mtk_the - .data = (void *)&mt7622_thermal_data, - }, - { -+ .compatible = "mediatek,mt7986-thermal", -+ .data = (void *)&mt7986_thermal_data, -+ }, -+ { - .compatible = "mediatek,mt8183-thermal", - .data = (void *)&mt8183_thermal_data, - }, { -@@ -1078,15 +1196,24 @@ static int mtk_thermal_probe(struct plat - goto err_disable_clk_auxadc; - } - -- if (mt->conf->version == MTK_THERMAL_V2) { -+ if (mt->conf->version != MTK_THERMAL_V1) { - mtk_thermal_turn_on_buffer(apmixed_base); - mtk_thermal_release_periodic_ts(mt, auxadc_base); - } - -- if (mt->conf->version == MTK_THERMAL_V1) -+ switch (mt->conf->version) { -+ case MTK_THERMAL_V1: - mt->raw_to_mcelsius = raw_to_mcelsius_v1; -- else -+ break; -+ case MTK_THERMAL_V2: - mt->raw_to_mcelsius = raw_to_mcelsius_v2; -+ break; -+ case MTK_THERMAL_V3: -+ mt->raw_to_mcelsius = raw_to_mcelsius_v3; -+ break; -+ default: -+ break; -+ } - - for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++) - for (i = 0; i < mt->conf->num_banks; i++) diff --git a/6.1/target/linux/mediatek/patches-6.1/826-v6.2-pinctrl-mediatek-extend-pinctrl-moore-to-support-new.patch b/6.1/target/linux/mediatek/patches-6.1/826-v6.2-pinctrl-mediatek-extend-pinctrl-moore-to-support-new.patch deleted file mode 100644 index f130fdbc..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/826-v6.2-pinctrl-mediatek-extend-pinctrl-moore-to-support-new.patch +++ /dev/null @@ -1,129 +0,0 @@ -From fae82621ac33e2a4a96220c56e90d1ec6237d394 Mon Sep 17 00:00:00 2001 -From: Sam Shih -Date: Sun, 6 Nov 2022 09:01:12 +0100 -Subject: [PATCH] pinctrl: mediatek: extend pinctrl-moore to support new bias - functions - -Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature") -introduced SoC specify 'pull_type' attribute to mtk_pinconf_bias_set_combo -and mtk_pinconf_bias_get_combo, and make the functions able to support -almost all Mediatek SoCs that use pinctrl-mtk-common-v2.c. - -This patch enables pinctrl_moore to support these functions. - -Signed-off-by: Sam Shih -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Link: https://lore.kernel.org/r/20221106080114.7426-6-linux@fw-web.de -Signed-off-by: Linus Walleij ---- - drivers/pinctrl/mediatek/pinctrl-moore.c | 49 ++++++++++++++++++++---- - 1 file changed, 42 insertions(+), 7 deletions(-) - ---- a/drivers/pinctrl/mediatek/pinctrl-moore.c -+++ b/drivers/pinctrl/mediatek/pinctrl-moore.c -@@ -8,6 +8,7 @@ - * - */ - -+#include - #include - #include "pinctrl-moore.h" - -@@ -105,7 +106,7 @@ static int mtk_pinconf_get(struct pinctr - { - struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); - u32 param = pinconf_to_config_param(*config); -- int val, val2, err, reg, ret = 1; -+ int val, val2, err, pullup, reg, ret = 1; - const struct mtk_pin_desc *desc; - - desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; -@@ -114,7 +115,13 @@ static int mtk_pinconf_get(struct pinctr - - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: -- if (hw->soc->bias_disable_get) { -+ if (hw->soc->bias_get_combo) { -+ err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); -+ if (err) -+ return err; -+ if (ret != MTK_PUPD_SET_R1R0_00 && ret != MTK_DISABLE) -+ return -EINVAL; -+ } else if (hw->soc->bias_disable_get) { - err = hw->soc->bias_disable_get(hw, desc, &ret); - if (err) - return err; -@@ -123,7 +130,15 @@ static int mtk_pinconf_get(struct pinctr - } - break; - case PIN_CONFIG_BIAS_PULL_UP: -- if (hw->soc->bias_get) { -+ if (hw->soc->bias_get_combo) { -+ err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); -+ if (err) -+ return err; -+ if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE) -+ return -EINVAL; -+ if (!pullup) -+ return -EINVAL; -+ } else if (hw->soc->bias_get) { - err = hw->soc->bias_get(hw, desc, 1, &ret); - if (err) - return err; -@@ -132,7 +147,15 @@ static int mtk_pinconf_get(struct pinctr - } - break; - case PIN_CONFIG_BIAS_PULL_DOWN: -- if (hw->soc->bias_get) { -+ if (hw->soc->bias_get_combo) { -+ err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); -+ if (err) -+ return err; -+ if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE) -+ return -EINVAL; -+ if (pullup) -+ return -EINVAL; -+ } else if (hw->soc->bias_get) { - err = hw->soc->bias_get(hw, desc, 0, &ret); - if (err) - return err; -@@ -235,7 +258,11 @@ static int mtk_pinconf_set(struct pinctr - - switch (param) { - case PIN_CONFIG_BIAS_DISABLE: -- if (hw->soc->bias_disable_set) { -+ if (hw->soc->bias_set_combo) { -+ err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE); -+ if (err) -+ return err; -+ } else if (hw->soc->bias_disable_set) { - err = hw->soc->bias_disable_set(hw, desc); - if (err) - return err; -@@ -244,7 +271,11 @@ static int mtk_pinconf_set(struct pinctr - } - break; - case PIN_CONFIG_BIAS_PULL_UP: -- if (hw->soc->bias_set) { -+ if (hw->soc->bias_set_combo) { -+ err = hw->soc->bias_set_combo(hw, desc, 1, arg); -+ if (err) -+ return err; -+ } else if (hw->soc->bias_set) { - err = hw->soc->bias_set(hw, desc, 1); - if (err) - return err; -@@ -253,7 +284,11 @@ static int mtk_pinconf_set(struct pinctr - } - break; - case PIN_CONFIG_BIAS_PULL_DOWN: -- if (hw->soc->bias_set) { -+ if (hw->soc->bias_set_combo) { -+ err = hw->soc->bias_set_combo(hw, desc, 0, arg); -+ if (err) -+ return err; -+ } else if (hw->soc->bias_set) { - err = hw->soc->bias_set(hw, desc, 0); - if (err) - return err; diff --git a/6.1/target/linux/mediatek/patches-6.1/851-v6.2-i2c-mediatek-add-mt7986-support.patch b/6.1/target/linux/mediatek/patches-6.1/851-v6.2-i2c-mediatek-add-mt7986-support.patch deleted file mode 100644 index 4c398c59..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/851-v6.2-i2c-mediatek-add-mt7986-support.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 11f9a0f4e51887ad7b4a2898a368fcd0c2984e89 Mon Sep 17 00:00:00 2001 -From: Frank Wunderlich -Date: Sun, 9 Oct 2022 12:16:31 +0200 -Subject: [PATCH 12/16] i2c: mediatek: add mt7986 support - -Add i2c support for MT7986 SoC. - -Signed-off-by: Frank Wunderlich -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -431,6 +431,19 @@ static const struct mtk_i2c_compatible m - .max_dma_support = 33, - }; - -+static const struct mtk_i2c_compatible mt7986_compat = { -+ .quirks = &mt7622_i2c_quirks, -+ .regs = mt_i2c_regs_v1, -+ .pmic_i2c = 0, -+ .dcm = 1, -+ .auto_restart = 1, -+ .aux_len_reg = 1, -+ .timing_adjust = 0, -+ .dma_sync = 1, -+ .ltiming_adjust = 0, -+ .max_dma_support = 32, -+}; -+ - static const struct mtk_i2c_compatible mt8173_compat = { - .regs = mt_i2c_regs_v1, - .pmic_i2c = 0, -@@ -503,6 +516,7 @@ static const struct of_device_id mtk_i2c - { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, - { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, - { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, -+ { .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat }, - { .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat }, - { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, - { .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat }, diff --git a/6.1/target/linux/mediatek/patches-6.1/852-v6.3-i2c-mt65xx-Use-devm_platform_get_and_ioremap_resourc.patch b/6.1/target/linux/mediatek/patches-6.1/852-v6.3-i2c-mt65xx-Use-devm_platform_get_and_ioremap_resourc.patch deleted file mode 100644 index 18c66cda..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/852-v6.3-i2c-mt65xx-Use-devm_platform_get_and_ioremap_resourc.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 98204ccafd45a8a6109ff2d60e2c179b95d92578 Mon Sep 17 00:00:00 2001 -From: ye xingchen -Date: Thu, 19 Jan 2023 17:19:58 +0800 -Subject: [PATCH 13/16] i2c: mt65xx: Use - devm_platform_get_and_ioremap_resource() - -Convert platform_get_resource(), devm_ioremap_resource() to a single -call to devm_platform_get_and_ioremap_resource(), as this is exactly -what this function does. - -Signed-off-by: ye xingchen -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 7 ++----- - 1 file changed, 2 insertions(+), 5 deletions(-) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -1366,20 +1366,17 @@ static int mtk_i2c_probe(struct platform - { - int ret = 0; - struct mtk_i2c *i2c; -- struct resource *res; - int i, irq, speed_clk; - - i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); - if (!i2c) - return -ENOMEM; - -- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -- i2c->base = devm_ioremap_resource(&pdev->dev, res); -+ i2c->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); - if (IS_ERR(i2c->base)) - return PTR_ERR(i2c->base); - -- res = platform_get_resource(pdev, IORESOURCE_MEM, 1); -- i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res); -+ i2c->pdmabase = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); - if (IS_ERR(i2c->pdmabase)) - return PTR_ERR(i2c->pdmabase); - diff --git a/6.1/target/linux/mediatek/patches-6.1/853-v6.3-i2c-mt65xx-drop-of_match_ptr-for-ID-table.patch b/6.1/target/linux/mediatek/patches-6.1/853-v6.3-i2c-mt65xx-drop-of_match_ptr-for-ID-table.patch deleted file mode 100644 index d000d535..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/853-v6.3-i2c-mt65xx-drop-of_match_ptr-for-ID-table.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 8106fa2e0ae6082833fe1df97829c46c0183eaea Mon Sep 17 00:00:00 2001 -From: Krzysztof Kozlowski -Date: Sat, 11 Mar 2023 12:16:54 +0100 -Subject: [PATCH 14/16] i2c: mt65xx: drop of_match_ptr for ID table -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The driver can match only via the DT table so the table should be always -used and the of_match_ptr does not have any sense (this also allows ACPI -matching via PRP0001, even though it might not be relevant here). - - drivers/i2c/busses/i2c-mt65xx.c:514:34: error: ‘mtk_i2c_of_match’ defined but not used [-Werror=unused-const-variable=] - -Signed-off-by: Krzysztof Kozlowski -Reviewed-by: Guenter Roeck -Reviewed-by: AngeloGioacchino Del Regno -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -1546,7 +1546,7 @@ static struct platform_driver mtk_i2c_dr - .driver = { - .name = I2C_DRV_NAME, - .pm = &mtk_i2c_pm, -- .of_match_table = of_match_ptr(mtk_i2c_of_match), -+ .of_match_table = mtk_i2c_of_match, - }, - }; - diff --git a/6.1/target/linux/mediatek/patches-6.1/854-v6.4-i2c-mediatek-add-support-for-MT7981-SoC.patch b/6.1/target/linux/mediatek/patches-6.1/854-v6.4-i2c-mediatek-add-support-for-MT7981-SoC.patch deleted file mode 100644 index e0973741..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/854-v6.4-i2c-mediatek-add-support-for-MT7981-SoC.patch +++ /dev/null @@ -1,47 +0,0 @@ -From f69f3d662ba3bf999c36d9ac1e684540c4487bc3 Mon Sep 17 00:00:00 2001 -From: Daniel Golle -Date: Mon, 10 Apr 2023 17:19:38 +0100 -Subject: [PATCH 15/16] i2c: mediatek: add support for MT7981 SoC - -Add support for the I2C units found in the MediaTek MT7981 and MT7988 -SoCs. Just like other recent MediaTek I2C units that also uses v3 -register offsets (which differ from v2 only by OFFSET_SLAVE_ADDR being -0x94 instead of 0x4). - -Signed-off-by: Daniel Golle -Reviewed-by: AngeloGioacchino Del Regno -Reviewed-by: Alexandre Mergnat -Signed-off-by: Wolfram Sang ---- - drivers/i2c/busses/i2c-mt65xx.c | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - ---- a/drivers/i2c/busses/i2c-mt65xx.c -+++ b/drivers/i2c/busses/i2c-mt65xx.c -@@ -431,6 +431,18 @@ static const struct mtk_i2c_compatible m - .max_dma_support = 33, - }; - -+static const struct mtk_i2c_compatible mt7981_compat = { -+ .regs = mt_i2c_regs_v3, -+ .pmic_i2c = 0, -+ .dcm = 0, -+ .auto_restart = 1, -+ .aux_len_reg = 1, -+ .timing_adjust = 1, -+ .dma_sync = 1, -+ .ltiming_adjust = 1, -+ .max_dma_support = 33 -+}; -+ - static const struct mtk_i2c_compatible mt7986_compat = { - .quirks = &mt7622_i2c_quirks, - .regs = mt_i2c_regs_v1, -@@ -516,6 +528,7 @@ static const struct of_device_id mtk_i2c - { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat }, - { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat }, - { .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat }, -+ { .compatible = "mediatek,mt7981-i2c", .data = &mt7981_compat }, - { .compatible = "mediatek,mt7986-i2c", .data = &mt7986_compat }, - { .compatible = "mediatek,mt8168-i2c", .data = &mt8168_compat }, - { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat }, diff --git a/6.1/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch b/6.1/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch deleted file mode 100644 index 600b94d7..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/900-dts-mt7622-bpi-r64-aliases-for-dtoverlay.patch +++ /dev/null @@ -1,65 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -314,7 +314,7 @@ - /* Attention: GPIO 90 is used to switch between PCIe@1,0 and - * SATA functions. i.e. output-high: PCIe, output-low: SATA - */ -- asm_sel { -+ asmsel: asm_sel { - gpio-hog; - gpios = <90 GPIO_ACTIVE_HIGH>; - output-high; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-sata.dtso -@@ -0,0 +1,31 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -+ -+#include -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r64", "mediatek,mt7622"; -+ -+ fragment@0 { -+ target = <&asmsel>; -+ __overlay__ { -+ gpios = <90 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&sata>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&sata_phy>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-pcie1.dtso -@@ -0,0 +1,17 @@ -+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ -+ -+#include -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "bananapi,bpi-r64", "mediatek,mt7622"; -+ -+ fragment@0 { -+ target = <&asmsel>; -+ __overlay__ { -+ gpios = <90 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+}; diff --git a/6.1/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch b/6.1/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch deleted file mode 100644 index b19992b4..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/901-arm-add-cmdline-override.patch +++ /dev/null @@ -1,54 +0,0 @@ ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -1587,6 +1587,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN - - endchoice - -+config CMDLINE_OVERRIDE -+ bool "Use alternative cmdline from device tree" -+ help -+ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can -+ be used, this is not a good option for kernels that are shared across -+ devices. This setting enables using "chosen/cmdline-override" as the -+ cmdline if it exists in the device tree. -+ - config CMDLINE - string "Default kernel command string" - default "" ---- a/drivers/of/fdt.c -+++ b/drivers/of/fdt.c -@@ -1187,6 +1187,17 @@ int __init early_init_dt_scan_chosen(cha - if (p != NULL && l > 0) - strlcat(cmdline, p, min_t(int, strlen(cmdline) + (int)l, COMMAND_LINE_SIZE)); - -+ /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different -+ * device tree option of chosen/bootargs-override. This is -+ * helpful on boards where u-boot sets bootargs, and is unable -+ * to be modified. -+ */ -+#ifdef CONFIG_CMDLINE_OVERRIDE -+ p = of_get_flat_dt_prop(node, "bootargs-override", &l); -+ if (p != NULL && l > 0) -+ strlcpy(cmdline, p, min((int)l, COMMAND_LINE_SIZE)); -+#endif -+ - handle_cmdline: - /* - * CONFIG_CMDLINE is meant to be a default in case nothing else ---- a/arch/arm64/Kconfig -+++ b/arch/arm64/Kconfig -@@ -1942,6 +1942,14 @@ config CMDLINE_FORCE - - endchoice - -+config CMDLINE_OVERRIDE -+ bool "Use alternative cmdline from device tree" -+ help -+ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can -+ be used, this is not a good option for kernels that are shared across -+ devices. This setting enables using "chosen/cmdline-override" as the -+ cmdline if it exists in the device tree. -+ - config EFI_STUB - bool - diff --git a/6.1/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch b/6.1/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch deleted file mode 100644 index a45d51dd..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/910-dts-mt7622-bpi-r64-wifi-eeprom.patch +++ /dev/null @@ -1,31 +0,0 @@ ---- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts -@@ -641,5 +641,28 @@ - }; - - &wmac { -+ mediatek,eeprom-data = <0x22760500 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x44000020 0x0 0x10002000 -+ 0x4400 0x4000000 0x0 0x0 -+ 0x200000b3 0x40b6c3c3 0x26000000 0x41c42600 -+ 0x41c4 0x26000000 0xc0c52600 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0xc6c6 -+ 0xc3c3c2c1 0xc300c3 0x818181 0x83c1c182 -+ 0x83838382 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x84002e00 0x90000087 0x8a000000 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0xb000009 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x0 -+ 0x0 0x0 0x0 0x7707>; -+ - status = "okay"; - }; diff --git a/6.1/target/linux/mediatek/patches-6.1/930-spi-mt65xx-enable-sel-clk.patch b/6.1/target/linux/mediatek/patches-6.1/930-spi-mt65xx-enable-sel-clk.patch deleted file mode 100644 index 6e6810b4..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/930-spi-mt65xx-enable-sel-clk.patch +++ /dev/null @@ -1,18 +0,0 @@ ---- a/drivers/spi/spi-mt65xx.c -+++ b/drivers/spi/spi-mt65xx.c -@@ -1225,8 +1225,15 @@ static int mtk_spi_probe(struct platform - if (ret < 0) - return dev_err_probe(dev, ret, "failed to enable hclk\n"); - -+ ret = clk_prepare_enable(mdata->sel_clk); -+ if (ret < 0) { -+ clk_disable_unprepare(mdata->spi_hclk); -+ return dev_err_probe(dev, ret, "failed to enable sel_clk\n"); -+ } -+ - ret = clk_prepare_enable(mdata->spi_clk); - if (ret < 0) { -+ clk_disable_unprepare(mdata->sel_clk); - clk_disable_unprepare(mdata->spi_hclk); - return dev_err_probe(dev, ret, "failed to enable spi_clk\n"); - } diff --git a/6.1/target/linux/mediatek/patches-6.1/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch b/6.1/target/linux/mediatek/patches-6.1/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch deleted file mode 100644 index 2fe565f3..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/940-net-ethernet-mtk_wed-rename-mtk_wed_get_memory_regio.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 3cf212c4ce6cd72c09bc47f35f539ba0afd4d106 Mon Sep 17 00:00:00 2001 -Message-Id: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org> -From: Lorenzo Bianconi -Date: Sun, 12 Mar 2023 16:40:31 +0100 -Subject: [PATCH net-next 1/2] net: ethernet: mtk_wed: rename - mtk_wed_get_memory_region in mtk_wed_get_reserved_memory_region - -This is a preliminary patch to move wed ilm/dlm and cpuboot properties in -dedicated dts nodes. - -Signed-off-by: Lorenzo Bianconi ---- - drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -@@ -215,8 +215,8 @@ int mtk_wed_mcu_msg_update(struct mtk_we - } - - static int --mtk_wed_get_memory_region(struct mtk_wed_wo *wo, -- struct mtk_wed_wo_memory_region *region) -+mtk_wed_get_reserved_memory_region(struct mtk_wed_wo *wo, -+ struct mtk_wed_wo_memory_region *region) - { - struct reserved_mem *rmem; - struct device_node *np; -@@ -311,13 +311,13 @@ mtk_wed_mcu_load_firmware(struct mtk_wed - - /* load firmware region metadata */ - for (i = 0; i < ARRAY_SIZE(mem_region); i++) { -- ret = mtk_wed_get_memory_region(wo, &mem_region[i]); -+ ret = mtk_wed_get_reserved_memory_region(wo, &mem_region[i]); - if (ret) - return ret; - } - - wo->boot.name = "wo-boot"; -- ret = mtk_wed_get_memory_region(wo, &wo->boot); -+ ret = mtk_wed_get_reserved_memory_region(wo, &wo->boot); - if (ret) - return ret; - diff --git a/6.1/target/linux/mediatek/patches-6.1/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch b/6.1/target/linux/mediatek/patches-6.1/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch deleted file mode 100644 index 0a58ae95..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/941-arm64-dts-mt7986-move-cpuboot-in-a-dedicated-node.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 247e566e3459481f1fa98733534bfed767e18b42 Mon Sep 17 00:00:00 2001 -Message-Id: <247e566e3459481f1fa98733534bfed767e18b42.1678620342.git.lorenzo@kernel.org> -From: Lorenzo Bianconi -Date: Sat, 11 Mar 2023 16:32:41 +0100 -Subject: [PATCH net-next] arm64: dts: mt7986: move cpuboot in a dedicated node - -Signed-off-by: Lorenzo Bianconi ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 21 +++++++++++---------- - 1 file changed, 11 insertions(+), 10 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -121,12 +121,6 @@ - reg = <0 0x151f8000 0 0x2000>; - no-map; - }; -- -- wo_boot: wo-boot@15194000 { -- reg = <0 0x15194000 0 0x1000>; -- no-map; -- }; -- - }; - - timer { -@@ -518,10 +512,11 @@ - interrupt-parent = <&gic>; - interrupts = ; - memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, -- <&wo_data>, <&wo_boot>; -+ <&wo_data>; - memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", -- "wo-data", "wo-boot"; -+ "wo-data"; - mediatek,wo-ccif = <&wo_ccif0>; -+ mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - - wed1: wed@15011000 { -@@ -531,10 +526,11 @@ - interrupt-parent = <&gic>; - interrupts = ; - memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>, -- <&wo_data>, <&wo_boot>; -+ <&wo_data>; - memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", -- "wo-data", "wo-boot"; -+ "wo-data"; - mediatek,wo-ccif = <&wo_ccif1>; -+ mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - - wo_ccif0: syscon@151a5000 { -@@ -551,6 +547,11 @@ - interrupts = ; - }; - -+ wo_cpuboot: syscon@15194000 { -+ compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; -+ reg = <0 0x15194000 0 0x1000>; -+ }; -+ - eth: ethernet@15100000 { - compatible = "mediatek,mt7986-eth"; - reg = <0 0x15100000 0 0x80000>; diff --git a/6.1/target/linux/mediatek/patches-6.1/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch b/6.1/target/linux/mediatek/patches-6.1/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch deleted file mode 100644 index 9de4ffa4..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/942-net-ethernet-mtk_wed-move-cpuboot-in-a-dedicated-dts.patch +++ /dev/null @@ -1,89 +0,0 @@ -From f292d1bf83ec160bef2532b58aa08f5b71041923 Mon Sep 17 00:00:00 2001 -Message-Id: -In-Reply-To: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org> -References: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org> -From: Lorenzo Bianconi -Date: Sat, 11 Mar 2023 18:13:04 +0100 -Subject: [PATCH net-next 2/2] net: ethernet: mtk_wed: move cpuboot in a - dedicated dts node - -Since the cpuboot memory region is not part of the RAM SoC, move cpuboot -in a deidicated syscon node. -This patch helps to keep backward-compatibility with older version of -uboot codebase where we have a limit of 8 reserved-memory dts child -nodes. -Keep backward-compatibility with older dts version where cpuboot was -defined as reserved-memory child node. - -Signed-off-by: Lorenzo Bianconi ---- - drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 34 +++++++++++++++++---- - drivers/net/ethernet/mediatek/mtk_wed_wo.h | 3 +- - 2 files changed, 30 insertions(+), 7 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -@@ -18,12 +18,23 @@ - - static u32 wo_r32(struct mtk_wed_wo *wo, u32 reg) - { -- return readl(wo->boot.addr + reg); -+ u32 val; -+ -+ if (!wo->boot_regmap) -+ return readl(wo->boot.addr + reg); -+ -+ if (regmap_read(wo->boot_regmap, reg, &val)) -+ val = ~0; -+ -+ return val; - } - - static void wo_w32(struct mtk_wed_wo *wo, u32 reg, u32 val) - { -- writel(val, wo->boot.addr + reg); -+ if (wo->boot_regmap) -+ regmap_write(wo->boot_regmap, reg, val); -+ else -+ writel(val, wo->boot.addr + reg); - } - - static struct sk_buff * -@@ -316,10 +327,21 @@ mtk_wed_mcu_load_firmware(struct mtk_wed - return ret; - } - -- wo->boot.name = "wo-boot"; -- ret = mtk_wed_get_reserved_memory_region(wo, &wo->boot); -- if (ret) -- return ret; -+ wo->boot_regmap = syscon_regmap_lookup_by_phandle(wo->hw->node, -+ "mediatek,wo-cpuboot"); -+ if (IS_ERR(wo->boot_regmap)) { -+ if (wo->boot_regmap != ERR_PTR(-ENODEV)) -+ return PTR_ERR(wo->boot_regmap); -+ -+ /* For backward compatibility, we need to check if cpu_boot -+ * is defined through reserved memory property. -+ */ -+ wo->boot_regmap = NULL; -+ wo->boot.name = "wo-boot"; -+ ret = mtk_wed_get_reserved_memory_region(wo, &wo->boot); -+ if (ret) -+ return ret; -+ } - - /* set dummy cr */ - wed_w32(wo->hw->wed_dev, MTK_WED_SCR0 + 4 * MTK_WED_DUMMY_CR_FWDL, ---- a/drivers/net/ethernet/mediatek/mtk_wed_wo.h -+++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.h -@@ -228,7 +228,8 @@ struct mtk_wed_wo_queue { - - struct mtk_wed_wo { - struct mtk_wed_hw *hw; -- struct mtk_wed_wo_memory_region boot; -+ struct mtk_wed_wo_memory_region boot; /* backward compatibility */ -+ struct regmap *boot_regmap; - - struct mtk_wed_wo_queue q_tx; - struct mtk_wed_wo_queue q_rx; diff --git a/6.1/target/linux/mediatek/patches-6.1/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch b/6.1/target/linux/mediatek/patches-6.1/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch deleted file mode 100644 index 7b6c5d1e..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/943-net-ethernet-mtk_wed-move-ilm-a-dedicated-dts-node.patch +++ /dev/null @@ -1,91 +0,0 @@ -From f3565e6c2276411275e707a5442d3f69cc111273 Mon Sep 17 00:00:00 2001 -Message-Id: -From: Lorenzo Bianconi -Date: Sun, 12 Mar 2023 18:51:47 +0100 -Subject: [PATCH net-next 1/3] net: ethernet: mtk_wed: move ilm a dedicated dts - node - -Since the ilm memory region is not part of the RAM SoC, move ilm in a -deidicated syscon node. -This patch helps to keep backward-compatibility with older version of -uboot codebase where we have a limit of 8 reserved-memory dts child -nodes. -Keep backward-compatibility with older dts version where ilm was defined -as reserved-memory child node. - -Signed-off-by: Lorenzo Bianconi ---- - drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 55 ++++++++++++++++++--- - 1 file changed, 49 insertions(+), 6 deletions(-) - ---- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c -@@ -300,6 +300,52 @@ next: - } - - static int -+mtk_wed_mcu_load_memory_regions(struct mtk_wed_wo *wo, -+ struct mtk_wed_wo_memory_region *region) -+{ -+ struct device_node *np; -+ int ret; -+ -+ /* firmware EMI memory region */ -+ ret = mtk_wed_get_reserved_memory_region(wo, -+ ®ion[MTK_WED_WO_REGION_EMI]); -+ if (ret) -+ return ret; -+ -+ /* firmware DATA memory region */ -+ ret = mtk_wed_get_reserved_memory_region(wo, -+ ®ion[MTK_WED_WO_REGION_DATA]); -+ if (ret) -+ return ret; -+ -+ np = of_parse_phandle(wo->hw->node, "mediatek,wo-ilm", 0); -+ if (np) { -+ struct mtk_wed_wo_memory_region *ilm_region; -+ struct resource res; -+ -+ ret = of_address_to_resource(np, 0, &res); -+ of_node_put(np); -+ -+ if (ret < 0) -+ return ret; -+ -+ ilm_region = ®ion[MTK_WED_WO_REGION_ILM]; -+ ilm_region->phy_addr = res.start; -+ ilm_region->size = resource_size(&res); -+ ilm_region->addr = devm_ioremap(wo->hw->dev, res.start, -+ resource_size(&res)); -+ -+ return IS_ERR(ilm_region->addr) ? PTR_ERR(ilm_region->addr) : 0; -+ } -+ -+ /* For backward compatibility, we need to check if ILM -+ * node is defined through reserved memory property. -+ */ -+ return mtk_wed_get_reserved_memory_region(wo, -+ ®ion[MTK_WED_WO_REGION_ILM]); -+} -+ -+static int - mtk_wed_mcu_load_firmware(struct mtk_wed_wo *wo) - { - static struct mtk_wed_wo_memory_region mem_region[] = { -@@ -320,12 +366,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed - u32 val, boot_cr; - int ret, i; - -- /* load firmware region metadata */ -- for (i = 0; i < ARRAY_SIZE(mem_region); i++) { -- ret = mtk_wed_get_reserved_memory_region(wo, &mem_region[i]); -- if (ret) -- return ret; -- } -+ ret = mtk_wed_mcu_load_memory_regions(wo, mem_region); -+ if (ret) -+ return ret; - - wo->boot_regmap = syscon_regmap_lookup_by_phandle(wo->hw->node, - "mediatek,wo-cpuboot"); diff --git a/6.1/target/linux/mediatek/patches-6.1/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch b/6.1/target/linux/mediatek/patches-6.1/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch deleted file mode 100644 index fb3940f5..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/944-net-ethernet-mtk_wed-move-dlm-a-dedicated-dts-node.patch +++ /dev/null @@ -1,57 +0,0 @@ -From b74ba226be2c45091b93bd49192bdd6d2178729e Mon Sep 17 00:00:00 2001 -Message-Id: -In-Reply-To: -References: -From: Lorenzo Bianconi -Date: Mon, 13 Mar 2023 15:45:16 +0100 -Subject: [PATCH net-next 3/3] net: ethernet: mtk_wed: move dlm a dedicated dts - node - -Since the dlm memory region is not part of the RAM SoC, move dlm in a -deidicated syscon node. -This patch helps to keep backward-compatibility with older version of -uboot codebase where we have a limit of 8 reserved-memory dts child -nodes. -Keep backward-compatibility with older dts version where dlm was defined -as reserved-memory child node. - -Signed-off-by: Lorenzo Bianconi ---- - drivers/net/ethernet/mediatek/mtk_wed.c | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - ---- a/drivers/net/ethernet/mediatek/mtk_wed.c -+++ b/drivers/net/ethernet/mediatek/mtk_wed.c -@@ -806,6 +806,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device - struct device_node *np; - int index; - -+ np = of_parse_phandle(dev->hw->node, "mediatek,wo-dlm", 0); -+ if (np) { -+ struct resource res; -+ int ret; -+ -+ ret = of_address_to_resource(np, 0, &res); -+ of_node_put(np); -+ -+ if (ret < 0) -+ return ret; -+ -+ dev->rro.miod_phys = res.start; -+ goto out; -+ } -+ -+ /* For backward compatibility, we need to check if DLM -+ * node is defined through reserved memory property. -+ */ - index = of_property_match_string(dev->hw->node, "memory-region-names", - "wo-dlm"); - if (index < 0) -@@ -822,6 +840,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device - return -ENODEV; - - dev->rro.miod_phys = rmem->base; -+out: - dev->rro.fdbk_phys = MTK_WED_MIOD_COUNT + dev->rro.miod_phys; - - return mtk_wed_rro_ring_alloc(dev, &dev->rro.ring, diff --git a/6.1/target/linux/mediatek/patches-6.1/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch b/6.1/target/linux/mediatek/patches-6.1/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch deleted file mode 100644 index 36fe9278..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/945-arm64-dts-mt7986-move-ilm-in-a-dedicated-node.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 01561065af5bf1d2a4244896d897e3a1eafbcd46 Mon Sep 17 00:00:00 2001 -Message-Id: <01561065af5bf1d2a4244896d897e3a1eafbcd46.1678717704.git.lorenzo@kernel.org> -From: Lorenzo Bianconi -Date: Mon, 13 Mar 2023 15:10:56 +0100 -Subject: [PATCH net-next] arm64: dts: mt7986: move ilm in a dedicated node - -Since the ilm memory region is not part of the RAM SoC, move ilm in a -deidicated syscon node. -This patch helps to keep backward-compatibility with older version of -uboot codebase where we have a limit of 8 reserved-memory dts child -nodes. - -Signed-off-by: Lorenzo Bianconi ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 34 +++++++++++------------ - 1 file changed, 16 insertions(+), 18 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -97,16 +97,6 @@ - no-map; - }; - -- wo_ilm0: wo-ilm@151e0000 { -- reg = <0 0x151e0000 0 0x8000>; -- no-map; -- }; -- -- wo_ilm1: wo-ilm@151f0000 { -- reg = <0 0x151f0000 0 0x8000>; -- no-map; -- }; -- - wo_data: wo-data@4fd80000 { - reg = <0 0x4fd80000 0 0x240000>; - no-map; -@@ -511,11 +501,10 @@ - reg = <0 0x15010000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; -- memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, -- <&wo_data>; -- memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", -- "wo-data"; -+ memory-region = <&wo_emi0>, <&wo_dlm0>, <&wo_data>; -+ memory-region-names = "wo-emi", "wo-dlm", "wo-data"; - mediatek,wo-ccif = <&wo_ccif0>; -+ mediatek,wo-ilm = <&wo_ilm0>; - mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - -@@ -525,11 +514,10 @@ - reg = <0 0x15011000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; -- memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>, -- <&wo_data>; -- memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", -- "wo-data"; -+ memory-region = <&wo_emi1>, <&wo_dlm1>, <&wo_data>; -+ memory-region-names = "wo-emi", "wo-dlm", "wo-data"; - mediatek,wo-ccif = <&wo_ccif1>; -+ mediatek,wo-ilm = <&wo_ilm1>; - mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - -@@ -547,6 +535,16 @@ - interrupts = ; - }; - -+ wo_ilm0: syscon@151e0000 { -+ compatible = "mediatek,mt7986-wo-ilm", "syscon"; -+ reg = <0 0x151e0000 0 0x8000>; -+ }; -+ -+ wo_ilm1: syscon@151f0000 { -+ compatible = "mediatek,mt7986-wo-ilm", "syscon"; -+ reg = <0 0x151f0000 0 0x8000>; -+ }; -+ - wo_cpuboot: syscon@15194000 { - compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; - reg = <0 0x15194000 0 0x1000>; diff --git a/6.1/target/linux/mediatek/patches-6.1/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch b/6.1/target/linux/mediatek/patches-6.1/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch deleted file mode 100644 index 55f17286..00000000 --- a/6.1/target/linux/mediatek/patches-6.1/946-arm64-dts-mt7986-move-dlm-in-a-dedicated-node.patch +++ /dev/null @@ -1,81 +0,0 @@ -From 9f76be683a8ec498563c294bc1cc279468058302 Mon Sep 17 00:00:00 2001 -Message-Id: <9f76be683a8ec498563c294bc1cc279468058302.1678719283.git.lorenzo@kernel.org> -From: Lorenzo Bianconi -Date: Mon, 13 Mar 2023 15:53:30 +0100 -Subject: [PATCH net-next] arm64: dts: mt7986: move dlm in a dedicated node - -Since the dlm memory region is not part of the RAM SoC, move dlm in a -deidicated syscon node. -This patch helps to keep backward-compatibility with older version of -uboot codebase where we have a limit of 8 reserved-memory dts child -nodes. - -Signed-off-by: Lorenzo Bianconi ---- - arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 30 ++++++++++++----------- - 1 file changed, 16 insertions(+), 14 deletions(-) - ---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi -@@ -101,16 +101,6 @@ - reg = <0 0x4fd80000 0 0x240000>; - no-map; - }; -- -- wo_dlm0: wo-dlm@151e8000 { -- reg = <0 0x151e8000 0 0x2000>; -- no-map; -- }; -- -- wo_dlm1: wo-dlm@151f8000 { -- reg = <0 0x151f8000 0 0x2000>; -- no-map; -- }; - }; - - timer { -@@ -501,10 +491,11 @@ - reg = <0 0x15010000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; -- memory-region = <&wo_emi0>, <&wo_dlm0>, <&wo_data>; -- memory-region-names = "wo-emi", "wo-dlm", "wo-data"; -+ memory-region = <&wo_emi0>, <&wo_data>; -+ memory-region-names = "wo-emi", "wo-data"; - mediatek,wo-ccif = <&wo_ccif0>; - mediatek,wo-ilm = <&wo_ilm0>; -+ mediatek,wo-dlm = <&wo_dlm0>; - mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - -@@ -514,10 +505,11 @@ - reg = <0 0x15011000 0 0x1000>; - interrupt-parent = <&gic>; - interrupts = ; -- memory-region = <&wo_emi1>, <&wo_dlm1>, <&wo_data>; -- memory-region-names = "wo-emi", "wo-dlm", "wo-data"; -+ memory-region = <&wo_emi1>, <&wo_data>; -+ memory-region-names = "wo-emi", "wo-data"; - mediatek,wo-ccif = <&wo_ccif1>; - mediatek,wo-ilm = <&wo_ilm1>; -+ mediatek,wo-dlm = <&wo_dlm1>; - mediatek,wo-cpuboot = <&wo_cpuboot>; - }; - -@@ -545,6 +537,16 @@ - reg = <0 0x151f0000 0 0x8000>; - }; - -+ wo_dlm0: syscon@151e8000 { -+ compatible = "mediatek,mt7986-wo-dlm", "syscon"; -+ reg = <0 0x151e8000 0 0x2000>; -+ }; -+ -+ wo_dlm1: syscon@151f8000 { -+ compatible = "mediatek,mt7986-wo-dlm", "syscon"; -+ reg = <0 0x151f8000 0 0x2000>; -+ }; -+ - wo_cpuboot: syscon@15194000 { - compatible = "mediatek,mt7986-wo-cpuboot", "syscon"; - reg = <0 0x15194000 0 0x1000>;