mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Fix Rockchip 6.1 compilation
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
948aebf05a
commit
747950fd6c
67 changed files with 16078 additions and 2 deletions
|
|
@ -341,6 +341,7 @@ CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8
|
|||
# CONFIG_ARCNET is not set
|
||||
# CONFIG_ARC_EMAC is not set
|
||||
# CONFIG_ARC_IRQ_NO_AUTOSAVE is not set
|
||||
# CONFIG_ARM64_4K_PAGES is not set
|
||||
# CONFIG_ARM64_16K_PAGES is not set
|
||||
# CONFIG_ARM64_64K_PAGES is not set
|
||||
# CONFIG_ARM64_AMU_EXTN is not set
|
||||
|
|
@ -442,6 +443,7 @@ CONFIG_ARM_GIC_MAX_NR=1
|
|||
# CONFIG_ARM_LPAE is not set
|
||||
# CONFIG_ARM_MEDIATEK_CPUFREQ_HW is not set
|
||||
# CONFIG_ARM_MHU is not set
|
||||
# CONFIG_ARM_MHU_V2 is not set
|
||||
CONFIG_ARM_MODULE_PLTS=y
|
||||
# CONFIG_ARM_PATCH_PHYS_VIRT is not set
|
||||
# CONFIG_ARM_PSCI is not set
|
||||
|
|
@ -951,6 +953,7 @@ CONFIG_CFG80211_HEADERS=y
|
|||
# CONFIG_CHARGER_MAX77976 is not set
|
||||
# CONFIG_CHARGER_MAX8903 is not set
|
||||
# CONFIG_CHARGER_QCOM_SMBB is not set
|
||||
# CONFIG_CHARGER_RK817 is not set
|
||||
# CONFIG_CHARGER_RT9455 is not set
|
||||
# CONFIG_CHARGER_SBS is not set
|
||||
# CONFIG_CHARGER_SMB347 is not set
|
||||
|
|
@ -1001,6 +1004,7 @@ CONFIG_CLS_U32_MARK=y
|
|||
# CONFIG_CM3605 is not set
|
||||
# CONFIG_CM36651 is not set
|
||||
# CONFIG_CMA is not set
|
||||
# CONFIG_CMA_SYSFS is not set
|
||||
CONFIG_CMDLINE=""
|
||||
# CONFIG_CMDLINE_BOOL is not set
|
||||
# CONFIG_CMDLINE_EXTEND is not set
|
||||
|
|
@ -1046,6 +1050,7 @@ CONFIG_CMDLINE=""
|
|||
CONFIG_COMPACTION=y
|
||||
# CONFIG_COMPAL_LAPTOP is not set
|
||||
# CONFIG_COMPAT is not set
|
||||
# CONFIG_COMPAT_ALIGNMENT_FIXUPS is not set
|
||||
# CONFIG_COMPAT_BRK is not set
|
||||
# CONFIG_COMPILE_TEST is not set
|
||||
# CONFIG_CONFIGFS_FS is not set
|
||||
|
|
@ -2515,6 +2520,7 @@ CONFIG_HIGH_RES_TIMERS=y
|
|||
# CONFIG_HOSTAP_PLX is not set
|
||||
# CONFIG_HOTPLUG_CPU is not set
|
||||
# CONFIG_HOTPLUG_PCI is not set
|
||||
# CONFIG_HOTPLUG_PCI_SHPC is not set
|
||||
# CONFIG_HP03 is not set
|
||||
# CONFIG_HP100 is not set
|
||||
# CONFIG_HP206C is not set
|
||||
|
|
@ -2724,6 +2730,7 @@ CONFIG_IIO_CONSUMERS_PER_TRIGGER=2
|
|||
# CONFIG_IIO_MUX is not set
|
||||
# CONFIG_IIO_PERIODIC_RTC_TRIGGER is not set
|
||||
# CONFIG_IIO_RESCALE is not set
|
||||
# CONFIG_IIO_SCMI is not set
|
||||
# CONFIG_IIO_SIMPLE_DUMMY is not set
|
||||
# CONFIG_IIO_SSP_SENSORHUB is not set
|
||||
# CONFIG_IIO_ST_ACCEL_3AXIS is not set
|
||||
|
|
@ -2892,6 +2899,8 @@ CONFIG_INPUT_MISC=y
|
|||
# CONFIG_INV_MPU6050_I2C is not set
|
||||
# CONFIG_INV_MPU6050_IIO is not set
|
||||
# CONFIG_INV_MPU6050_SPI is not set
|
||||
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
|
||||
# CONFIG_IOMMU_IO_PGTABLE_DART is not set
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
# CONFIG_IONIC is not set
|
||||
# CONFIG_IOSCHED_BFQ is not set
|
||||
|
|
@ -6505,6 +6514,7 @@ CONFIG_SND_X86=y
|
|||
# CONFIG_SPI_PXA2XX_PCI is not set
|
||||
# CONFIG_SPI_QCOM_QSPI is not set
|
||||
# CONFIG_SPI_ROCKCHIP is not set
|
||||
# CONFIG_SPI_ROCKCHIP_SFC is not set
|
||||
# CONFIG_SPI_S3C64XX is not set
|
||||
# CONFIG_SPI_SC18IS602 is not set
|
||||
# CONFIG_SPI_SIFIVE is not set
|
||||
|
|
@ -6997,9 +7007,13 @@ CONFIG_TTY=y
|
|||
# CONFIG_TWL6040_CORE is not set
|
||||
# CONFIG_TXGBE is not set
|
||||
# CONFIG_TYPEC is not set
|
||||
# CONFIG_TYPEC_ANX7411 is not set
|
||||
# CONFIG_TYPEC_DP_ALTMODE is not set
|
||||
# CONFIG_TYPEC_MUX_FSA4480 is not set
|
||||
# CONFIG_TYPEC_RT1719 is not set
|
||||
# CONFIG_TYPEC_TCPM is not set
|
||||
# CONFIG_TYPEC_UCSI is not set
|
||||
# CONFIG_TYPEC_WUSB3801 is not set
|
||||
# CONFIG_TYPHOON is not set
|
||||
# CONFIG_UACCESS_WITH_MEMCPY is not set
|
||||
# CONFIG_UBIFS_ATIME_SUPPORT is not set
|
||||
|
|
|
|||
43
6.1/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds
Executable file
43
6.1/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds
Executable file
|
|
@ -0,0 +1,43 @@
|
|||
#!/bin/sh
|
||||
|
||||
. /lib/functions/leds.sh
|
||||
. /lib/functions/uci-defaults.sh
|
||||
|
||||
board=$(board_name)
|
||||
boardname="${board##*,}"
|
||||
|
||||
board_config_update
|
||||
|
||||
case $board in
|
||||
friendlyarm,nanopi-r2c|\
|
||||
friendlyarm,nanopi-r2s|\
|
||||
xunlong,orangepi-r1-plus|\
|
||||
xunlong,orangepi-r1-plus-lts)
|
||||
ucidef_set_led_netdev "wan" "WAN" "$boardname:green:wan" "eth0"
|
||||
ucidef_set_led_netdev "lan" "LAN" "$boardname:green:lan" "eth1"
|
||||
;;
|
||||
friendlyarm,nanopi-r4s|\
|
||||
friendlyarm,nanopi-r4se|\
|
||||
sharevdi,guangmiao-g4c)
|
||||
ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth0"
|
||||
ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth1"
|
||||
;;
|
||||
friendlyarm,nanopi-r5c)
|
||||
ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth1"
|
||||
ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth0"
|
||||
;;
|
||||
friendlyarm,nanopi-r5s)
|
||||
ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth0"
|
||||
ucidef_set_led_netdev "lan1" "LAN1" "green:lan1" "eth1"
|
||||
ucidef_set_led_netdev "lan2" "LAN2" "green:lan2" "eth2"
|
||||
;;
|
||||
hinlink,opc-h66k|\
|
||||
hinlink,opc-h68k|\
|
||||
hinlink,opc-h69k)
|
||||
ucidef_set_led_netdev "wan" "WAN" "blue:net" "eth0"
|
||||
;;
|
||||
esac
|
||||
|
||||
board_config_flush
|
||||
|
||||
exit 0
|
||||
128
6.1/target/linux/rockchip/armv8/base-files/etc/board.d/02_network
Executable file
128
6.1/target/linux/rockchip/armv8/base-files/etc/board.d/02_network
Executable file
|
|
@ -0,0 +1,128 @@
|
|||
#!/bin/sh
|
||||
|
||||
. /lib/functions/uci-defaults.sh
|
||||
. /lib/functions/system.sh
|
||||
|
||||
rockchip_setup_interfaces()
|
||||
{
|
||||
local board="$1"
|
||||
|
||||
case "$board" in
|
||||
ariaboard,photonicat|\
|
||||
dilusense,dlfr100|\
|
||||
ezpro,mrkaio-m68s|\
|
||||
ezpro,mrkaio-m68s-plus|\
|
||||
hinlink,opc-h66k|\
|
||||
friendlyarm,nanopi-r2c|\
|
||||
friendlyarm,nanopi-r2s|\
|
||||
friendlyarm,nanopi-r4s|\
|
||||
friendlyarm,nanopi-r4se|\
|
||||
rocktech,mpc1903|\
|
||||
sharevdi,h3399pc|\
|
||||
sharevdi,guangmiao-g4c|\
|
||||
xunlong,orangepi-r1-plus|\
|
||||
xunlong,orangepi-r1-plus-lts)
|
||||
ucidef_set_interfaces_lan_wan 'eth1' 'eth0'
|
||||
;;
|
||||
hinlink,opc-h68k|\
|
||||
hinlink,opc-h69k)
|
||||
ucidef_set_interfaces_lan_wan 'eth1 eth2 eth3' 'eth0'
|
||||
;;
|
||||
fastrhino,r66s|\
|
||||
firefly,rk3568-roc-pc|\
|
||||
friendlyarm,nanopi-r5c|\
|
||||
radxa,e25)
|
||||
ucidef_set_interfaces_lan_wan 'eth0' 'eth1'
|
||||
;;
|
||||
fastrhino,r68s)
|
||||
ucidef_set_interfaces_lan_wan 'eth0 eth2 eth3' 'eth1'
|
||||
;;
|
||||
friendlyarm,nanopi-r5s)
|
||||
ucidef_set_interfaces_lan_wan "eth1 eth2" "eth0"
|
||||
;;
|
||||
*)
|
||||
ucidef_set_interface_lan 'eth0'
|
||||
;;
|
||||
esac
|
||||
}
|
||||
|
||||
generate_mac_from_mmc_cid()
|
||||
{
|
||||
local sd_hash=$(sha256sum /sys/class/block/mmcblk*/device/cid | head -n 1)
|
||||
local mac_base=$(macaddr_canonicalize "$(echo "${sd_hash}" | dd bs=1 count=12 2>/dev/null)")
|
||||
echo "$(macaddr_unsetbit_mc "$(macaddr_setbit_la "${mac_base}")")"
|
||||
}
|
||||
|
||||
nanopi_r4s_get_mac()
|
||||
{
|
||||
local interface=$1
|
||||
local eeprom_path="/sys/bus/i2c/devices/2-0051/eeprom"
|
||||
local address
|
||||
|
||||
if [ -f "$eeprom_path" ]; then
|
||||
address=$(get_mac_binary "$eeprom_path" 0xfa)
|
||||
if [ "$interface" = "lan" ]; then
|
||||
address=$(macaddr_setbit_la "$address")
|
||||
fi
|
||||
else
|
||||
address=$(generate_mac_from_mmc_cid)
|
||||
if [ "$interface" = "lan" ]; then
|
||||
address=$(macaddr_add "$address" 1)
|
||||
fi
|
||||
fi
|
||||
|
||||
echo "$address"
|
||||
}
|
||||
|
||||
rockchip_setup_macs()
|
||||
{
|
||||
local board="$1"
|
||||
local lan_mac=""
|
||||
local wan_mac=""
|
||||
local label_mac=""
|
||||
|
||||
case "$board" in
|
||||
ariaboard,photonicat|\
|
||||
dilusense,dlfr100|\
|
||||
ezpro,mrkaio-m68s|\
|
||||
ezpro,mrkaio-m68s-plus|\
|
||||
hinlink,opc-h66k|\
|
||||
hinlink,opc-h68k|\
|
||||
hinlink,opc-h69k|\
|
||||
fastrhino,r66s|\
|
||||
fastrhino,r68s|\
|
||||
firefly,rk3568-roc-pc|\
|
||||
friendlyarm,nanopi-r2c|\
|
||||
friendlyarm,nanopi-r2s|\
|
||||
friendlyarm,nanopi-r5s|\
|
||||
friendlyarm,nanopi-r5c|\
|
||||
sharevdi,h3399pc|\
|
||||
sharevdi,guangmiao-g4c|\
|
||||
rocktech,mpc1903)
|
||||
wan_mac=$(generate_mac_from_mmc_cid)
|
||||
lan_mac=$(macaddr_add "$wan_mac" +1)
|
||||
;;
|
||||
friendlyarm,nanopi-r4s|\
|
||||
friendlyarm,nanopi-r4se)
|
||||
wan_mac=$(nanopi_r4s_get_mac wan)
|
||||
lan_mac=$(nanopi_r4s_get_mac lan)
|
||||
;;
|
||||
xunlong,orangepi-r1-plus|\
|
||||
xunlong,orangepi-r1-plus-lts)
|
||||
lan_mac=$(cat /sys/class/net/eth1/address)
|
||||
wan_mac=$(macaddr_add "$lan_mac" -1)
|
||||
;;
|
||||
esac
|
||||
|
||||
[ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac
|
||||
[ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" $wan_mac
|
||||
[ -n "$label_mac" ] && ucidef_set_label_macaddr $label_mac
|
||||
}
|
||||
|
||||
board_config_update
|
||||
board=$(board_name)
|
||||
rockchip_setup_interfaces $board
|
||||
rockchip_setup_macs $board
|
||||
board_config_flush
|
||||
|
||||
exit 0
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
#!/bin/sh
|
||||
|
||||
[ "$ACTION" = add ] || exit
|
||||
|
||||
get_device_irq() {
|
||||
local device="$1"
|
||||
local line
|
||||
local seconds
|
||||
|
||||
# wait up to 10 seconds for the irq/device to appear
|
||||
for seconds in $(seq 0 9); do
|
||||
line=$(grep -m 1 "${device}\$" /proc/interrupts) && break
|
||||
sleep 1
|
||||
done
|
||||
echo ${line} | sed 's/:.*//'
|
||||
}
|
||||
|
||||
set_interface_core() {
|
||||
local core_mask="$1"
|
||||
local interface="$2"
|
||||
local device="$3"
|
||||
|
||||
[ -z "${device}" ] && device="$interface"
|
||||
|
||||
local irq=$(get_device_irq "$device")
|
||||
|
||||
echo "${core_mask}" > /proc/irq/${irq}/smp_affinity
|
||||
}
|
||||
|
||||
case "$(board_name)" in
|
||||
fastrhino,r66s|\
|
||||
friendlyarm,nanopi-r5c|\
|
||||
firefly,rk3568-roc-pc)
|
||||
set_interface_core 2 "eth0"
|
||||
set_interface_core 4 "eth1"
|
||||
;;
|
||||
friendlyarm,nanopi-r2c|\
|
||||
friendlyarm,nanopi-r2s|\
|
||||
xunlong,orangepi-r1-plus|\
|
||||
xunlong,orangepi-r1-plus-lts)
|
||||
set_interface_core 2 "eth0"
|
||||
set_interface_core 4 "eth1" "xhci-hcd:usb3"
|
||||
;;
|
||||
friendlyarm,nanopi-r4s|\
|
||||
friendlyarm,nanopi-r4se|\
|
||||
sharevdi,guangmiao-g4c)
|
||||
set_interface_core 10 "eth0"
|
||||
set_interface_core 20 "eth1"
|
||||
;;
|
||||
friendlyarm,nanopi-r5s)
|
||||
set_interface_core 0 "eth0"
|
||||
set_interface_core 2 "eth1"
|
||||
set_interface_core 4 "eth2"
|
||||
;;
|
||||
esac
|
||||
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
#!/bin/sh
|
||||
|
||||
if [ "${ACTION}" = "add" ]; then
|
||||
usbmode -s && sleep 5
|
||||
[ -n "$(cat /proc/net/wireless | grep wlan)" ] && wifi config && wifi
|
||||
fi
|
||||
15
6.1/target/linux/rockchip/armv8/base-files/etc/init.d/fanctrl
Executable file
15
6.1/target/linux/rockchip/armv8/base-files/etc/init.d/fanctrl
Executable file
|
|
@ -0,0 +1,15 @@
|
|||
#!/bin/sh /etc/rc.common
|
||||
# Copyright (C) 2006-2011 OpenWrt.org
|
||||
|
||||
START=99
|
||||
|
||||
. /lib/functions/system.sh
|
||||
|
||||
boot() {
|
||||
case $(board_name) in
|
||||
rongpin,king3399)
|
||||
echo 50 > /sys/class/gpio/export && echo high > /sys/class/gpio/gpio50/direction
|
||||
echo 56 > /sys/class/gpio/export && echo high > /sys/class/gpio/gpio56/direction
|
||||
;;
|
||||
esac
|
||||
}
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
#!/bin/sh
|
||||
uci -q batch <<-EOF >/dev/null
|
||||
set network.globals.packet_steering=1
|
||||
commit network
|
||||
EOF
|
||||
|
||||
exit 0
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
move_config() {
|
||||
local partdev
|
||||
|
||||
. /lib/upgrade/common.sh
|
||||
|
||||
if export_bootdevice && export_partdevice partdev 1; then
|
||||
if mount -o rw,noatime "/dev/$partdev" /mnt; then
|
||||
if [ -f "/mnt/$BACKUP_FILE" ]; then
|
||||
mv -f "/mnt/$BACKUP_FILE" /
|
||||
fi
|
||||
umount /mnt
|
||||
fi
|
||||
fi
|
||||
}
|
||||
|
||||
boot_hook_add preinit_mount_root move_config
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
platform_check_image() {
|
||||
local diskdev partdev diff
|
||||
|
||||
export_bootdevice && export_partdevice diskdev 0 || {
|
||||
echo "Unable to determine upgrade device"
|
||||
return 1
|
||||
}
|
||||
|
||||
get_partitions "/dev/$diskdev" bootdisk
|
||||
|
||||
#extract the boot sector from the image
|
||||
get_image "$@" | dd of=/tmp/image.bs count=1 bs=512b 2>/dev/null
|
||||
|
||||
get_partitions /tmp/image.bs image
|
||||
|
||||
#compare tables
|
||||
diff="$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)"
|
||||
|
||||
rm -f /tmp/image.bs /tmp/partmap.bootdisk /tmp/partmap.image
|
||||
|
||||
if [ -n "$diff" ]; then
|
||||
echo "Partition layout has changed. Full image will be written."
|
||||
ask_bool 0 "Abort" && exit 1
|
||||
return 0
|
||||
fi
|
||||
}
|
||||
|
||||
platform_copy_config() {
|
||||
local partdev
|
||||
|
||||
if export_partdevice partdev 1; then
|
||||
mount -o rw,noatime "/dev/$partdev" /mnt
|
||||
cp -af "$UPGRADE_BACKUP" "/mnt/$BACKUP_FILE"
|
||||
umount /mnt
|
||||
fi
|
||||
}
|
||||
|
||||
platform_do_upgrade() {
|
||||
local diskdev partdev diff
|
||||
|
||||
export_bootdevice && export_partdevice diskdev 0 || {
|
||||
echo "Unable to determine upgrade device"
|
||||
return 1
|
||||
}
|
||||
|
||||
sync
|
||||
|
||||
if [ "$UPGRADE_OPT_SAVE_PARTITIONS" = "1" ]; then
|
||||
get_partitions "/dev/$diskdev" bootdisk
|
||||
|
||||
#extract the boot sector from the image
|
||||
get_image "$@" | dd of=/tmp/image.bs count=1 bs=512b
|
||||
|
||||
get_partitions /tmp/image.bs image
|
||||
|
||||
#compare tables
|
||||
diff="$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)"
|
||||
else
|
||||
diff=1
|
||||
fi
|
||||
|
||||
if [ -n "$diff" ]; then
|
||||
get_image "$@" | dd of="/dev/$diskdev" bs=4096 conv=fsync
|
||||
|
||||
# Separate removal and addtion is necessary; otherwise, partition 1
|
||||
# will be missing if it overlaps with the old partition 2
|
||||
partx -d - "/dev/$diskdev"
|
||||
partx -a - "/dev/$diskdev"
|
||||
|
||||
return 0
|
||||
fi
|
||||
|
||||
#iterate over each partition from the image and write it to the boot disk
|
||||
while read part start size; do
|
||||
if export_partdevice partdev $part; then
|
||||
echo "Writing image to /dev/$partdev..."
|
||||
get_image "$@" | dd of="/dev/$partdev" ibs="512" obs=1M skip="$start" count="$size" conv=fsync
|
||||
else
|
||||
echo "Unable to find partition $part device, skipped."
|
||||
fi
|
||||
done < /tmp/partmap.image
|
||||
|
||||
#copy partition uuid
|
||||
echo "Writing new UUID to /dev/$diskdev..."
|
||||
get_image "$@" | dd of="/dev/$diskdev" bs=1 skip=440 count=4 seek=440 conv=fsync
|
||||
}
|
||||
704
6.1/target/linux/rockchip/armv8/config-6.1
Normal file
704
6.1/target/linux/rockchip/armv8/config-6.1
Normal file
|
|
@ -0,0 +1,704 @@
|
|||
CONFIG_64BIT=y
|
||||
CONFIG_AF_UNIX_OOB=y
|
||||
CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
|
||||
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
|
||||
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
|
||||
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
|
||||
CONFIG_ARCH_KEEP_MEMBLOCK=y
|
||||
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
|
||||
CONFIG_ARCH_MMAP_RND_BITS_MAX=33
|
||||
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
|
||||
CONFIG_ARCH_MMAP_RND_BITS=18
|
||||
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
|
||||
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
|
||||
CONFIG_ARCH_PROC_KCORE_TEXT=y
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_ARCH_SPARSEMEM_ENABLE=y
|
||||
CONFIG_ARCH_STACKWALK=y
|
||||
CONFIG_ARCH_SUSPEND_POSSIBLE=y
|
||||
CONFIG_ARCH_WANTS_NO_INSTR=y
|
||||
CONFIG_ARCH_WANTS_THP_SWAP=y
|
||||
CONFIG_ARC_EMAC_CORE=y
|
||||
CONFIG_ARM64=y
|
||||
CONFIG_ARM64_CNP=y
|
||||
CONFIG_ARM64_CRYPTO=y
|
||||
CONFIG_ARM64_EPAN=y
|
||||
CONFIG_ARM64_ERRATUM_819472=y
|
||||
CONFIG_ARM64_ERRATUM_824069=y
|
||||
CONFIG_ARM64_ERRATUM_826319=y
|
||||
CONFIG_ARM64_ERRATUM_827319=y
|
||||
CONFIG_ARM64_ERRATUM_832075=y
|
||||
CONFIG_ARM64_ERRATUM_843419=y
|
||||
CONFIG_ARM64_ERRATUM_845719=y
|
||||
CONFIG_ARM64_ERRATUM_858921=y
|
||||
CONFIG_ARM64_ERRATUM_1742098=y
|
||||
CONFIG_ARM64_HW_AFDBM=y
|
||||
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
|
||||
CONFIG_ARM64_MODULE_PLTS=y
|
||||
CONFIG_ARM64_PAGE_SHIFT=12
|
||||
CONFIG_ARM64_PAN=y
|
||||
CONFIG_ARM64_PA_BITS=48
|
||||
CONFIG_ARM64_PA_BITS_48=y
|
||||
CONFIG_ARM64_PTR_AUTH=y
|
||||
CONFIG_ARM64_PTR_AUTH_KERNEL=y
|
||||
CONFIG_ARM64_RAS_EXTN=y
|
||||
CONFIG_ARM64_SVE=y
|
||||
# CONFIG_ARM64_SW_TTBR0_PAN is not set
|
||||
CONFIG_ARM64_TAGGED_ADDR_ABI=y
|
||||
CONFIG_ARM64_VA_BITS=48
|
||||
# CONFIG_ARM64_VA_BITS_39 is not set
|
||||
CONFIG_ARM64_VA_BITS_48=y
|
||||
CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
|
||||
# CONFIG_ARMV8_DEPRECATED is not set
|
||||
CONFIG_ARM_AMBA=y
|
||||
CONFIG_ARM_ARCH_TIMER=y
|
||||
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
|
||||
CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
|
||||
CONFIG_ARM_CPUIDLE=y
|
||||
CONFIG_ARM_GIC=y
|
||||
CONFIG_ARM_GIC_V2M=y
|
||||
CONFIG_ARM_GIC_V3=y
|
||||
CONFIG_ARM_GIC_V3_ITS=y
|
||||
CONFIG_ARM_GIC_V3_ITS_PCI=y
|
||||
CONFIG_ARM_MHU=y
|
||||
CONFIG_ARM_MHU_V2=y
|
||||
CONFIG_ARM_PSCI_CPUIDLE=y
|
||||
CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
|
||||
CONFIG_ARM_PSCI_FW=y
|
||||
CONFIG_ARM_RK3328_DMC_DEVFREQ=y
|
||||
# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
|
||||
# CONFIG_ARM_SCMI_CPUFREQ is not set
|
||||
CONFIG_ARM_SCMI_POWER_CONTROL=y
|
||||
CONFIG_ARM_SCMI_POWER_DOMAIN=y
|
||||
CONFIG_ARM_SCMI_PROTOCOL=y
|
||||
CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
|
||||
CONFIG_ARM_SCMI_TRANSPORT_SMC=y
|
||||
# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set
|
||||
CONFIG_ARM_SCPI_CPUFREQ=y
|
||||
CONFIG_ARM_SCPI_POWER_DOMAIN=y
|
||||
CONFIG_ARM_SCPI_PROTOCOL=y
|
||||
CONFIG_ARM_SMMU=y
|
||||
CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
|
||||
# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
|
||||
CONFIG_ARM_SMMU_V3=y
|
||||
# CONFIG_ARM_SMMU_V3_SVA is not set
|
||||
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
CONFIG_BACKLIGHT_GPIO=y
|
||||
CONFIG_BACKLIGHT_PWM=y
|
||||
CONFIG_BINARY_PRINTF=y
|
||||
CONFIG_BLK_DEV_BSG=y
|
||||
CONFIG_BLK_DEV_BSGLIB=y
|
||||
CONFIG_BLK_DEV_BSG_COMMON=y
|
||||
# CONFIG_BLK_DEV_INITRD is not set
|
||||
CONFIG_BLK_DEV_INTEGRITY=y
|
||||
CONFIG_BLK_DEV_INTEGRITY_T10=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_NVME=y
|
||||
CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_BLK_MQ_PCI=y
|
||||
CONFIG_BLK_PM=y
|
||||
CONFIG_BLOCK_COMPAT=y
|
||||
CONFIG_BRCMSTB_GISB_ARB=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_BSD_PROCESS_ACCT_V3=y
|
||||
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
|
||||
CONFIG_CHARGER_GPIO=y
|
||||
CONFIG_CLKSRC_MMIO=y
|
||||
CONFIG_CLK_PX30=y
|
||||
CONFIG_CLK_RK3308=y
|
||||
CONFIG_CLK_RK3328=y
|
||||
CONFIG_CLK_RK3368=y
|
||||
CONFIG_CLK_RK3399=y
|
||||
CONFIG_CLK_RK3568=y
|
||||
CONFIG_CLONE_BACKWARDS=y
|
||||
CONFIG_CMA=y
|
||||
CONFIG_CMA_ALIGNMENT=8
|
||||
CONFIG_CMA_AREAS=7
|
||||
# CONFIG_CMA_DEBUG is not set
|
||||
# CONFIG_CMA_DEBUGFS is not set
|
||||
CONFIG_CMA_SIZE_MBYTES=64
|
||||
# CONFIG_CMA_SIZE_SEL_MAX is not set
|
||||
CONFIG_CMA_SIZE_SEL_MBYTES=y
|
||||
# CONFIG_CMA_SIZE_SEL_MIN is not set
|
||||
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
|
||||
CONFIG_COMMON_CLK=y
|
||||
CONFIG_COMMON_CLK_RK808=y
|
||||
CONFIG_COMMON_CLK_ROCKCHIP=y
|
||||
CONFIG_COMMON_CLK_SCMI=y
|
||||
CONFIG_COMMON_CLK_SCPI=y
|
||||
CONFIG_COMPAT=y
|
||||
CONFIG_COMPAT_32BIT_TIME=y
|
||||
CONFIG_COMPAT_BINFMT_ELF=y
|
||||
CONFIG_COMPAT_NETLINK_MESSAGES=y
|
||||
CONFIG_COMPAT_OLD_SIGACTION=y
|
||||
CONFIG_CONFIGFS_FS=y
|
||||
CONFIG_CONSOLE_TRANSLATIONS=y
|
||||
CONFIG_CONTEXT_TRACKING=y
|
||||
CONFIG_CONTEXT_TRACKING_IDLE=y
|
||||
CONFIG_CONTIG_ALLOC=y
|
||||
CONFIG_CPUFREQ_DT=y
|
||||
CONFIG_CPUFREQ_DT_PLATDEV=y
|
||||
CONFIG_CPU_FREQ=y
|
||||
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
|
||||
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
|
||||
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
|
||||
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
|
||||
# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
|
||||
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
|
||||
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
|
||||
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
|
||||
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
|
||||
CONFIG_CPU_FREQ_STAT=y
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_CPU_IDLE_GOV_MENU=y
|
||||
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
|
||||
CONFIG_CPU_ISOLATION=y
|
||||
CONFIG_CPU_PM=y
|
||||
CONFIG_CPU_RMAP=y
|
||||
CONFIG_CPU_THERMAL=y
|
||||
CONFIG_CRASH_CORE=y
|
||||
CONFIG_CRASH_DUMP=y
|
||||
CONFIG_CRC16=y
|
||||
# CONFIG_CRC32_SARWATE is not set
|
||||
CONFIG_CRC32_SLICEBY8=y
|
||||
CONFIG_CRC64=y
|
||||
CONFIG_CRC64_ROCKSOFT=y
|
||||
CONFIG_CRC_T10DIF=y
|
||||
CONFIG_CROSS_MEMORY_ATTACH=y
|
||||
CONFIG_CRYPTO_AES_ARM64=y
|
||||
CONFIG_CRYPTO_AES_ARM64_CE=y
|
||||
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
|
||||
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
|
||||
CONFIG_CRYPTO_CRC32=y
|
||||
CONFIG_CRYPTO_CRC32C=y
|
||||
CONFIG_CRYPTO_CRC64_ROCKSOFT=y
|
||||
CONFIG_CRYPTO_CRCT10DIF=y
|
||||
CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
|
||||
CONFIG_CRYPTO_CRYPTD=y
|
||||
CONFIG_CRYPTO_GHASH_ARM64_CE=y
|
||||
CONFIG_CRYPTO_LIB_SHA1=y
|
||||
CONFIG_CRYPTO_LIB_SHA256=y
|
||||
CONFIG_CRYPTO_NULL2=y
|
||||
CONFIG_CRYPTO_RNG2=y
|
||||
CONFIG_CRYPTO_SIMD=y
|
||||
CONFIG_DCACHE_WORD_ACCESS=y
|
||||
CONFIG_DEBUG_BUGVERBOSE=y
|
||||
CONFIG_CRYPTO_DEV_ROCKCHIP=y
|
||||
# CONFIG_DEVFREQ_GOV_PASSIVE is not set
|
||||
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
|
||||
CONFIG_DEVFREQ_GOV_POWERSAVE=y
|
||||
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
|
||||
CONFIG_DEVFREQ_GOV_USERSPACE=y
|
||||
# CONFIG_DEVFREQ_THERMAL is not set
|
||||
CONFIG_DEVMEM=y
|
||||
# CONFIG_DEVPORT is not set
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_DMA_CMA=y
|
||||
CONFIG_DMA_DIRECT_REMAP=y
|
||||
CONFIG_DMA_ENGINE=y
|
||||
CONFIG_DMA_OF=y
|
||||
CONFIG_DMA_OPS=y
|
||||
CONFIG_DMA_SHARED_BUFFER=y
|
||||
CONFIG_DNOTIFY=y
|
||||
CONFIG_DTC=y
|
||||
CONFIG_DT_IDLE_GENPD=y
|
||||
CONFIG_DT_IDLE_STATES=y
|
||||
CONFIG_DUMMY_CONSOLE=y
|
||||
CONFIG_DWMAC_DWC_QOS_ETH=y
|
||||
CONFIG_DWMAC_GENERIC=y
|
||||
CONFIG_DWMAC_ROCKCHIP=y
|
||||
CONFIG_DW_WATCHDOG=y
|
||||
CONFIG_EDAC_SUPPORT=y
|
||||
CONFIG_EEPROM_AT24=y
|
||||
CONFIG_EMAC_ROCKCHIP=y
|
||||
CONFIG_ENERGY_MODEL=y
|
||||
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_EXT4_FS_POSIX_ACL=y
|
||||
CONFIG_EXTCON=y
|
||||
CONFIG_F2FS_FS=y
|
||||
CONFIG_FANOTIFY=y
|
||||
CONFIG_FHANDLE=y
|
||||
CONFIG_FIXED_PHY=y
|
||||
CONFIG_FIX_EARLYCON_MEM=y
|
||||
# CONFIG_FORTIFY_SOURCE is not set
|
||||
CONFIG_FRAME_POINTER=y
|
||||
CONFIG_FRAME_WARN=2048
|
||||
CONFIG_FS_IOMAP=y
|
||||
CONFIG_FS_MBCACHE=y
|
||||
CONFIG_FS_POSIX_ACL=y
|
||||
CONFIG_FWNODE_MDIO=y
|
||||
CONFIG_FW_LOADER_PAGED_BUF=y
|
||||
CONFIG_FW_LOADER_SYSFS=y
|
||||
CONFIG_GENERIC_ALLOCATOR=y
|
||||
CONFIG_GENERIC_ARCH_TOPOLOGY=y
|
||||
CONFIG_GENERIC_BUG=y
|
||||
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
|
||||
CONFIG_GENERIC_CPU_AUTOPROBE=y
|
||||
CONFIG_GENERIC_CPU_VULNERABILITIES=y
|
||||
CONFIG_GENERIC_CSUM=y
|
||||
CONFIG_GENERIC_EARLY_IOREMAP=y
|
||||
CONFIG_GENERIC_GETTIMEOFDAY=y
|
||||
CONFIG_GENERIC_IDLE_POLL_SETUP=y
|
||||
CONFIG_GENERIC_IOREMAP=y
|
||||
CONFIG_GENERIC_IRQ_CHIP=y
|
||||
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
|
||||
CONFIG_GENERIC_IRQ_MIGRATION=y
|
||||
CONFIG_GENERIC_IRQ_SHOW=y
|
||||
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
|
||||
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
|
||||
CONFIG_GENERIC_MSI_IRQ=y
|
||||
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_GENERIC_PCI_IOMAP=y
|
||||
CONFIG_GENERIC_PHY=y
|
||||
CONFIG_GENERIC_PINCONF=y
|
||||
CONFIG_GENERIC_SCHED_CLOCK=y
|
||||
CONFIG_GENERIC_SMP_IDLE_THREAD=y
|
||||
CONFIG_GENERIC_STRNCPY_FROM_USER=y
|
||||
CONFIG_GENERIC_STRNLEN_USER=y
|
||||
CONFIG_GENERIC_TIME_VSYSCALL=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIOLIB_IRQCHIP=y
|
||||
CONFIG_GPIO_CDEV=y
|
||||
CONFIG_GPIO_DWAPB=y
|
||||
CONFIG_GPIO_GENERIC=y
|
||||
CONFIG_GPIO_GENERIC_PLATFORM=y
|
||||
CONFIG_GPIO_ROCKCHIP=y
|
||||
# CONFIG_HARDENED_USERCOPY is not set
|
||||
CONFIG_HARDIRQS_SW_RESEND=y
|
||||
CONFIG_HAS_DMA=y
|
||||
CONFIG_HAS_IOMEM=y
|
||||
CONFIG_HAS_IOPORT_MAP=y
|
||||
CONFIG_HID=y
|
||||
CONFIG_HID_GENERIC=y
|
||||
CONFIG_HOTPLUG_CPU=y
|
||||
CONFIG_HOTPLUG_PCI=y
|
||||
# CONFIG_HOTPLUG_PCI_CPCI is not set
|
||||
# CONFIG_HOTPLUG_PCI_PCIE is not set
|
||||
CONFIG_HUGETLBFS=y
|
||||
CONFIG_HUGETLB_PAGE=y
|
||||
# CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP is not set
|
||||
CONFIG_HWMON=y
|
||||
CONFIG_HWSPINLOCK=y
|
||||
CONFIG_HW_CONSOLE=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_HW_RANDOM_ROCKCHIP=y
|
||||
CONFIG_HZ=250
|
||||
# CONFIG_HZ_100 is not set
|
||||
CONFIG_HZ_250=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_BOARDINFO=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_COMPAT=y
|
||||
CONFIG_I2C_HELPER_AUTO=y
|
||||
CONFIG_I2C_RK3X=y
|
||||
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
|
||||
CONFIG_INDIRECT_PIO=y
|
||||
CONFIG_INPUT=y
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_INPUT_FF_MEMLESS=y
|
||||
CONFIG_INPUT_KEYBOARD=y
|
||||
CONFIG_INPUT_LEDS=y
|
||||
CONFIG_INPUT_MATRIXKMAP=y
|
||||
# CONFIG_INPUT_MISC is not set
|
||||
# CONFIG_INPUT_RK805_PWRKEY is not set
|
||||
CONFIG_IOMMU_API=y
|
||||
# CONFIG_IOMMU_DEBUGFS is not set
|
||||
# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
|
||||
CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
|
||||
CONFIG_IOMMU_DMA=y
|
||||
CONFIG_IOMMU_IOVA=y
|
||||
CONFIG_IOMMU_IO_PGTABLE=y
|
||||
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
|
||||
CONFIG_IOMMU_IO_PGTABLE_LPAE=y
|
||||
# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
|
||||
CONFIG_IOMMU_SUPPORT=y
|
||||
# CONFIG_IO_STRICT_DEVMEM is not set
|
||||
CONFIG_IO_URING=y
|
||||
CONFIG_IRQCHIP=y
|
||||
CONFIG_IRQ_DOMAIN=y
|
||||
CONFIG_IRQ_DOMAIN_HIERARCHY=y
|
||||
CONFIG_IRQ_FORCED_THREADING=y
|
||||
CONFIG_IRQ_MSI_IOMMU=y
|
||||
CONFIG_IRQ_TIME_ACCOUNTING=y
|
||||
CONFIG_IRQ_WORK=y
|
||||
CONFIG_JBD2=y
|
||||
CONFIG_JFFS2_ZLIB=y
|
||||
CONFIG_JUMP_LABEL=y
|
||||
CONFIG_KALLSYMS=y
|
||||
CONFIG_KEXEC_CORE=y
|
||||
CONFIG_KEXEC_FILE=y
|
||||
# CONFIG_KEXEC_SIG is not set
|
||||
CONFIG_KSM=y
|
||||
# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
|
||||
CONFIG_LEDS_GPIO=y
|
||||
CONFIG_LEDS_PWM=y
|
||||
CONFIG_LEDS_SYSCON=y
|
||||
CONFIG_LEDS_TRIGGER_CPU=y
|
||||
CONFIG_LEDS_TRIGGER_PANIC=y
|
||||
CONFIG_LEGACY_PTYS=y
|
||||
CONFIG_LEGACY_PTY_COUNT=16
|
||||
CONFIG_LIBCRC32C=y
|
||||
CONFIG_LIBFDT=y
|
||||
CONFIG_LOCALVERSION_AUTO=y
|
||||
CONFIG_LOCK_DEBUGGING_SUPPORT=y
|
||||
CONFIG_LOCK_SPIN_ON_OWNER=y
|
||||
CONFIG_LOG_BUF_SHIFT=19
|
||||
CONFIG_LTO_NONE=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_MAGIC_SYSRQ_SERIAL=y
|
||||
CONFIG_MAILBOX=y
|
||||
# CONFIG_MAILBOX_TEST is not set
|
||||
CONFIG_MDIO_BUS=y
|
||||
CONFIG_MDIO_BUS_MUX=y
|
||||
CONFIG_MDIO_BUS_MUX_GPIO=y
|
||||
CONFIG_MDIO_BUS_MUX_MMIOREG=y
|
||||
CONFIG_MDIO_DEVICE=y
|
||||
CONFIG_MDIO_DEVRES=y
|
||||
CONFIG_MEMFD_CREATE=y
|
||||
CONFIG_MEMORY_ISOLATION=y
|
||||
CONFIG_MFD_CORE=y
|
||||
# CONFIG_MFD_KHADAS_MCU is not set
|
||||
CONFIG_MFD_RK808=y
|
||||
CONFIG_MFD_SYSCON=y
|
||||
CONFIG_MIGRATION=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_BLOCK=y
|
||||
CONFIG_MMC_BLOCK_MINORS=32
|
||||
CONFIG_MMC_CQHCI=y
|
||||
CONFIG_MMC_DW=y
|
||||
# CONFIG_MMC_DW_BLUEFIELD is not set
|
||||
# CONFIG_MMC_DW_EXYNOS is not set
|
||||
# CONFIG_MMC_DW_HI3798CV200 is not set
|
||||
# CONFIG_MMC_DW_K3 is not set
|
||||
# CONFIG_MMC_DW_PCI is not set
|
||||
CONFIG_MMC_DW_PLTFM=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_OF_ARASAN=y
|
||||
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
|
||||
# CONFIG_MMC_SDHCI_PCI is not set
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
CONFIG_MODULES_USE_ELF_RELA=y
|
||||
CONFIG_MOTORCOMM_PHY=y
|
||||
CONFIG_MQ_IOSCHED_DEADLINE=y
|
||||
# CONFIG_MTD_CFI is not set
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set
|
||||
CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y
|
||||
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
|
||||
CONFIG_MTD_SPLIT_FIRMWARE=y
|
||||
CONFIG_MUTEX_SPIN_ON_OWNER=y
|
||||
CONFIG_NEED_DMA_MAP_STATE=y
|
||||
CONFIG_NEED_SG_DMA_LENGTH=y
|
||||
CONFIG_NET_FLOW_LIMIT=y
|
||||
CONFIG_NET_SELFTESTS=y
|
||||
CONFIG_NET_SOCK_MSG=y
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NOP_USB_XCEIV=y
|
||||
CONFIG_NO_HZ_COMMON=y
|
||||
CONFIG_NO_HZ_IDLE=y
|
||||
CONFIG_NR_CPUS=256
|
||||
CONFIG_NVMEM=y
|
||||
# CONFIG_NVMEM_RMEM is not set
|
||||
CONFIG_NVMEM_SYSFS=y
|
||||
CONFIG_NVME_CORE=y
|
||||
# CONFIG_NVME_HWMON is not set
|
||||
# CONFIG_NVME_MULTIPATH is not set
|
||||
# CONFIG_NVMEM_ROCKCHIP_EFUSE is not set
|
||||
# CONFIG_NVMEM_ROCKCHIP_OTP is not set
|
||||
CONFIG_OF=y
|
||||
CONFIG_OF_ADDRESS=y
|
||||
CONFIG_OF_DYNAMIC=y
|
||||
CONFIG_OF_EARLY_FLATTREE=y
|
||||
CONFIG_OF_FLATTREE=y
|
||||
CONFIG_OF_GPIO=y
|
||||
CONFIG_OF_IOMMU=y
|
||||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_KOBJ=y
|
||||
CONFIG_OF_MDIO=y
|
||||
CONFIG_OF_NET=y
|
||||
CONFIG_OF_OVERLAY=y
|
||||
CONFIG_OF_RESOLVE=y
|
||||
CONFIG_OLD_SIGSUSPEND3=y
|
||||
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
|
||||
CONFIG_PADATA=y
|
||||
CONFIG_PAGE_POOL=y
|
||||
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
|
||||
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
|
||||
CONFIG_PAHOLE_VERSION=0
|
||||
# CONFIG_PANIC_ON_OOPS is not set
|
||||
CONFIG_PANIC_ON_OOPS_VALUE=0
|
||||
CONFIG_PANIC_TIMEOUT=0
|
||||
# CONFIG_PARTITION_ADVANCED is not set
|
||||
CONFIG_PARTITION_PERCPU=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCIEAER=y
|
||||
CONFIG_PCIEASPM=y
|
||||
CONFIG_PCIEASPM_DEFAULT=y
|
||||
# CONFIG_PCIEASPM_PERFORMANCE is not set
|
||||
# CONFIG_PCIEASPM_POWERSAVE is not set
|
||||
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
CONFIG_PCIE_DW=y
|
||||
CONFIG_PCIE_DW_HOST=y
|
||||
CONFIG_PCIE_PME=y
|
||||
CONFIG_PCIE_ROCKCHIP=y
|
||||
CONFIG_PCIE_ROCKCHIP_DW_HOST=y
|
||||
CONFIG_PCIE_ROCKCHIP_HOST=y
|
||||
CONFIG_PCI_DOMAINS=y
|
||||
CONFIG_PCI_DOMAINS_GENERIC=y
|
||||
CONFIG_PCI_MSI=y
|
||||
CONFIG_PCI_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_PCI_STUB=y
|
||||
CONFIG_PCS_XPCS=y
|
||||
CONFIG_PGTABLE_LEVELS=4
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHYLINK=y
|
||||
CONFIG_PHYS_ADDR_T_64BIT=y
|
||||
CONFIG_PHY_ROCKCHIP_DP=y
|
||||
# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
|
||||
CONFIG_PHY_ROCKCHIP_EMMC=y
|
||||
# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set
|
||||
# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
|
||||
# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
|
||||
CONFIG_PHY_ROCKCHIP_PCIE=y
|
||||
CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
|
||||
CONFIG_PHY_ROCKCHIP_TYPEC=y
|
||||
CONFIG_PHY_ROCKCHIP_USB=y
|
||||
CONFIG_PINCTRL=y
|
||||
# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
|
||||
# CONFIG_PINCTRL_RK805 is not set
|
||||
CONFIG_PINCTRL_ROCKCHIP=y
|
||||
# CONFIG_PINCTRL_SINGLE is not set
|
||||
CONFIG_PL330_DMA=y
|
||||
CONFIG_PLATFORM_MHU=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_PM_CLK=y
|
||||
CONFIG_PM_DEVFREQ=y
|
||||
# CONFIG_PM_DEVFREQ_EVENT is not set
|
||||
CONFIG_PM_GENERIC_DOMAINS=y
|
||||
CONFIG_PM_GENERIC_DOMAINS_OF=y
|
||||
CONFIG_PM_OPP=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_POWER_SUPPLY_HWMON=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_PREEMPTION=y
|
||||
CONFIG_PREEMPT_BUILD=y
|
||||
CONFIG_PREEMPT_COUNT=y
|
||||
# CONFIG_PREEMPT_NONE is not set
|
||||
CONFIG_PREEMPT_RCU=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
# CONFIG_PRINT_QUOTA_WARNING is not set
|
||||
CONFIG_PROC_PAGE_MONITOR=y
|
||||
CONFIG_PROC_VMCORE=y
|
||||
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
|
||||
CONFIG_PWM=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_PWM_SYSFS=y
|
||||
# CONFIG_QFMT_V1 is not set
|
||||
# CONFIG_QFMT_V2 is not set
|
||||
CONFIG_QUEUED_RWLOCKS=y
|
||||
CONFIG_QUEUED_SPINLOCKS=y
|
||||
CONFIG_QUOTA=y
|
||||
CONFIG_QUOTACTL=y
|
||||
# CONFIG_QUOTA_NETLINK_INTERFACE is not set
|
||||
CONFIG_RAID_ATTRS=y
|
||||
CONFIG_RANDOMIZE_BASE=y
|
||||
CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
|
||||
CONFIG_RANDSTRUCT_NONE=y
|
||||
CONFIG_RAS=y
|
||||
CONFIG_RATIONAL=y
|
||||
# CONFIG_RAVE_SP_CORE is not set
|
||||
CONFIG_RCU_TRACE=y
|
||||
CONFIG_REALTEK_PHY=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_REGMAP_I2C=y
|
||||
CONFIG_REGMAP_IRQ=y
|
||||
CONFIG_REGMAP_MMIO=y
|
||||
CONFIG_REGULATOR=y
|
||||
# CONFIG_REGULATOR_ARM_SCMI is not set
|
||||
CONFIG_REGULATOR_FAN53555=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_REGULATOR_GPIO=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_REGULATOR_RK808=y
|
||||
CONFIG_RELOCATABLE=y
|
||||
CONFIG_RESET_CONTROLLER=y
|
||||
CONFIG_RESET_SCMI=y
|
||||
CONFIG_RFS_ACCEL=y
|
||||
CONFIG_ROCKCHIP_EFUSE=y
|
||||
CONFIG_ROCKCHIP_ERRATUM_114514=y
|
||||
CONFIG_ROCKCHIP_GRF=y
|
||||
CONFIG_ROCKCHIP_IODOMAIN=y
|
||||
CONFIG_ROCKCHIP_IOMMU=y
|
||||
CONFIG_ROCKCHIP_MBOX=y
|
||||
# CONFIG_ROCKCHIP_OTP is not set
|
||||
CONFIG_ROCKCHIP_PHY=y
|
||||
CONFIG_ROCKCHIP_PM_DOMAINS=y
|
||||
CONFIG_ROCKCHIP_THERMAL=y
|
||||
CONFIG_ROCKCHIP_TIMER=y
|
||||
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
|
||||
CONFIG_RPS=y
|
||||
CONFIG_RSEQ=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_RK808=y
|
||||
CONFIG_RTC_I2C_AND_SPI=y
|
||||
CONFIG_RTC_NVMEM=y
|
||||
# CONFIG_RUNTIME_TESTING_MENU is not set
|
||||
CONFIG_RWSEM_SPIN_ON_OWNER=y
|
||||
CONFIG_SCHED_MC=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SCSI_COMMON=y
|
||||
# CONFIG_SCSI_LOWLEVEL is not set
|
||||
# CONFIG_SCSI_PROC_FS is not set
|
||||
CONFIG_SCSI_SAS_ATTRS=y
|
||||
CONFIG_SCSI_SAS_HOST_SMP=y
|
||||
CONFIG_SCSI_SAS_LIBSAS=y
|
||||
# CONFIG_SECURITY_DMESG_RESTRICT is not set
|
||||
# CONFIG_SENSORS_ARM_SCMI is not set
|
||||
CONFIG_SENSORS_ARM_SCPI=y
|
||||
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
CONFIG_SERIAL_8250_DWLIB=y
|
||||
CONFIG_SERIAL_8250_EXAR=y
|
||||
CONFIG_SERIAL_8250_EXTENDED=y
|
||||
CONFIG_SERIAL_8250_FSL=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=4
|
||||
CONFIG_SERIAL_8250_PCI=y
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
|
||||
CONFIG_SERIAL_8250_SHARE_IRQ=y
|
||||
CONFIG_SERIAL_AMBA_PL011=y
|
||||
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
|
||||
CONFIG_SERIAL_DEV_BUS=y
|
||||
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
|
||||
CONFIG_SERIAL_MCTRL_GPIO=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
CONFIG_SERIO=y
|
||||
CONFIG_SERIO_AMBAKMI=y
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
CONFIG_SG_POOL=y
|
||||
# CONFIG_SHORTCUT_FE is not set
|
||||
# CONFIG_SHADOW_CALL_STACK is not set
|
||||
CONFIG_SLUB_DEBUG=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SOCK_RX_QUEUE_MAPPING=y
|
||||
CONFIG_SPARSEMEM=y
|
||||
CONFIG_SPARSEMEM_EXTREME=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_BITBANG=y
|
||||
CONFIG_SPI_DYNAMIC=y
|
||||
CONFIG_SPI_MASTER=y
|
||||
CONFIG_SPI_MEM=y
|
||||
CONFIG_SPI_ROCKCHIP=y
|
||||
CONFIG_SPI_SPIDEV=y
|
||||
# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
|
||||
CONFIG_SQUASHFS_DECOMP_SINGLE=y
|
||||
# CONFIG_SQUASHFS_EMBEDDED is not set
|
||||
CONFIG_SQUASHFS_FILE_CACHE=y
|
||||
# CONFIG_SQUASHFS_FILE_DIRECT is not set
|
||||
CONFIG_SRAM=y
|
||||
CONFIG_SRCU=y
|
||||
CONFIG_STACKDEPOT=y
|
||||
CONFIG_STACKPROTECTOR=y
|
||||
CONFIG_STACKPROTECTOR_PER_TASK=y
|
||||
CONFIG_STACKPROTECTOR_STRONG=y
|
||||
CONFIG_STACKTRACE=y
|
||||
# CONFIG_STAGING is not set
|
||||
CONFIG_STMMAC_ETH=y
|
||||
CONFIG_STMMAC_PLATFORM=y
|
||||
# CONFIG_STMMAC_SELFTESTS is not set
|
||||
CONFIG_STRICT_DEVMEM=y
|
||||
# CONFIG_STRIP_ASM_SYMS is not set
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_SWIOTLB=y
|
||||
CONFIG_SWPHY=y
|
||||
CONFIG_SYNC_FILE=y
|
||||
CONFIG_SYSCTL_EXCEPTION_TRACE=y
|
||||
CONFIG_SYSFS_SYSCALL=y
|
||||
CONFIG_SYSVIPC_COMPAT=y
|
||||
# CONFIG_TEXTSEARCH is not set
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
|
||||
CONFIG_THERMAL_EMULATION=y
|
||||
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
|
||||
CONFIG_THERMAL_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_HWMON=y
|
||||
CONFIG_THERMAL_OF=y
|
||||
CONFIG_THREAD_INFO_IN_TASK=y
|
||||
CONFIG_TICK_CPU_ACCOUNTING=y
|
||||
CONFIG_TIMER_OF=y
|
||||
CONFIG_TIMER_PROBE=y
|
||||
CONFIG_TRACE_CLOCK=y
|
||||
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
|
||||
CONFIG_TRANSPARENT_HUGEPAGE=y
|
||||
CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
|
||||
# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
|
||||
CONFIG_TRANS_TABLE=y
|
||||
CONFIG_TREE_RCU=y
|
||||
CONFIG_TREE_SRCU=y
|
||||
CONFIG_TYPEC=y
|
||||
CONFIG_TYPEC_FUSB302=y
|
||||
# CONFIG_TYPEC_HD3SS3220 is not set
|
||||
# CONFIG_TYPEC_MUX_PI3USB30532 is not set
|
||||
# CONFIG_TYPEC_STUSB160X is not set
|
||||
# CONFIG_TYPEC_TCPCI is not set
|
||||
CONFIG_TYPEC_TCPM=y
|
||||
# CONFIG_TYPEC_TPS6598X is not set
|
||||
# CONFIG_UACCE is not set
|
||||
# CONFIG_UCLAMP_TASK is not set
|
||||
# CONFIG_UEVENT_HELPER is not set
|
||||
CONFIG_UNINLINE_SPIN_UNLOCK=y
|
||||
CONFIG_UNMAP_KERNEL_AT_EL0=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_COMMON=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_HOST=y
|
||||
CONFIG_USB_DWC3_OF_SIMPLE=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD_PLATFORM=y
|
||||
# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
|
||||
CONFIG_USB_HID=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_PHY=y
|
||||
CONFIG_USB_ROLE_SWITCH=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_ULPI_BUS=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_PLATFORM=y
|
||||
# CONFIG_VIRTIO_MENU is not set
|
||||
CONFIG_VMAP_STACK=y
|
||||
CONFIG_VM_EVENT_COUNTERS=y
|
||||
CONFIG_VT=y
|
||||
CONFIG_VT_CONSOLE=y
|
||||
CONFIG_VT_HW_CONSOLE_BINDING=y
|
||||
CONFIG_WATCHDOG_CORE=y
|
||||
CONFIG_XARRAY_MULTI=y
|
||||
CONFIG_XPS=y
|
||||
CONFIG_XXHASH=y
|
||||
CONFIG_XZ_DEC_ARM=y
|
||||
CONFIG_XZ_DEC_ARMTHUMB=y
|
||||
CONFIG_XZ_DEC_BCJ=y
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
CONFIG_ZONE_DMA32=y
|
||||
|
|
@ -0,0 +1,311 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#include <dt-bindings/clock/rockchip-ddr.h>
|
||||
#include <dt-bindings/memory/rk3328-dram.h>
|
||||
|
||||
/ {
|
||||
ddr_timing: ddr_timing {
|
||||
compatible = "rockchip,ddr-timing";
|
||||
ddr3_speed_bin = <DDR3_DEFAULT>;
|
||||
ddr4_speed_bin = <DDR4_DEFAULT>;
|
||||
pd_idle = <0>;
|
||||
sr_idle = <0>;
|
||||
sr_mc_gate_idle = <0>;
|
||||
srpd_lite_idle = <0>;
|
||||
standby_idle = <0>;
|
||||
|
||||
auto_pd_dis_freq = <1066>;
|
||||
auto_sr_dis_freq = <800>;
|
||||
ddr3_dll_dis_freq = <300>;
|
||||
ddr4_dll_dis_freq = <625>;
|
||||
phy_dll_dis_freq = <400>;
|
||||
|
||||
ddr3_odt_dis_freq = <100>;
|
||||
phy_ddr3_odt_dis_freq = <100>;
|
||||
ddr3_drv = <DDR3_DS_40ohm>;
|
||||
ddr3_odt = <DDR3_ODT_120ohm>;
|
||||
phy_ddr3_ca_drv = <PHY_DDR3_RON_RTT_34ohm>;
|
||||
phy_ddr3_ck_drv = <PHY_DDR3_RON_RTT_45ohm>;
|
||||
phy_ddr3_dq_drv = <PHY_DDR3_RON_RTT_34ohm>;
|
||||
phy_ddr3_odt = <PHY_DDR3_RON_RTT_225ohm>;
|
||||
|
||||
lpddr3_odt_dis_freq = <666>;
|
||||
phy_lpddr3_odt_dis_freq = <666>;
|
||||
lpddr3_drv = <LP3_DS_40ohm>;
|
||||
lpddr3_odt = <LP3_ODT_240ohm>;
|
||||
phy_lpddr3_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
|
||||
phy_lpddr3_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
|
||||
phy_lpddr3_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
|
||||
phy_lpddr3_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
|
||||
|
||||
lpddr4_odt_dis_freq = <800>;
|
||||
phy_lpddr4_odt_dis_freq = <800>;
|
||||
lpddr4_drv = <LP4_PDDS_60ohm>;
|
||||
lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
|
||||
lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
|
||||
phy_lpddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_40ohm>;
|
||||
phy_lpddr4_ck_cs_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
|
||||
phy_lpddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
|
||||
phy_lpddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_60ohm>;
|
||||
|
||||
ddr4_odt_dis_freq = <666>;
|
||||
phy_ddr4_odt_dis_freq = <666>;
|
||||
ddr4_drv = <DDR4_DS_34ohm>;
|
||||
ddr4_odt = <DDR4_RTT_NOM_240ohm>;
|
||||
phy_ddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
|
||||
phy_ddr4_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
|
||||
phy_ddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
|
||||
phy_ddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
|
||||
|
||||
/* CA de-skew, one step is 47.8ps, range 0-15 */
|
||||
ddr3a1_ddr4a9_de-skew = <7>;
|
||||
ddr3a0_ddr4a10_de-skew = <7>;
|
||||
ddr3a3_ddr4a6_de-skew = <8>;
|
||||
ddr3a2_ddr4a4_de-skew = <8>;
|
||||
ddr3a5_ddr4a8_de-skew = <7>;
|
||||
ddr3a4_ddr4a5_de-skew = <9>;
|
||||
ddr3a7_ddr4a11_de-skew = <7>;
|
||||
ddr3a6_ddr4a7_de-skew = <9>;
|
||||
ddr3a9_ddr4a0_de-skew = <8>;
|
||||
ddr3a8_ddr4a13_de-skew = <7>;
|
||||
ddr3a11_ddr4a3_de-skew = <9>;
|
||||
ddr3a10_ddr4cs0_de-skew = <7>;
|
||||
ddr3a13_ddr4a2_de-skew = <8>;
|
||||
ddr3a12_ddr4ba1_de-skew = <7>;
|
||||
ddr3a15_ddr4odt0_de-skew = <7>;
|
||||
ddr3a14_ddr4a1_de-skew = <8>;
|
||||
ddr3ba1_ddr4a15_de-skew = <7>;
|
||||
ddr3ba0_ddr4bg0_de-skew = <7>;
|
||||
ddr3ras_ddr4cke_de-skew = <7>;
|
||||
ddr3ba2_ddr4ba0_de-skew = <8>;
|
||||
ddr3we_ddr4bg1_de-skew = <8>;
|
||||
ddr3cas_ddr4a12_de-skew = <7>;
|
||||
ddr3ckn_ddr4ckn_de-skew = <8>;
|
||||
ddr3ckp_ddr4ckp_de-skew = <8>;
|
||||
ddr3cke_ddr4a16_de-skew = <8>;
|
||||
ddr3odt0_ddr4a14_de-skew = <7>;
|
||||
ddr3cs0_ddr4act_de-skew = <8>;
|
||||
ddr3reset_ddr4reset_de-skew = <7>;
|
||||
ddr3cs1_ddr4cs1_de-skew = <7>;
|
||||
ddr3odt1_ddr4odt1_de-skew = <7>;
|
||||
|
||||
/* DATA de-skew
|
||||
* RX one step is 25.1ps, range 0-15
|
||||
* TX one step is 47.8ps, range 0-15
|
||||
*/
|
||||
cs0_dm0_rx_de-skew = <7>;
|
||||
cs0_dm0_tx_de-skew = <8>;
|
||||
cs0_dq0_rx_de-skew = <7>;
|
||||
cs0_dq0_tx_de-skew = <8>;
|
||||
cs0_dq1_rx_de-skew = <7>;
|
||||
cs0_dq1_tx_de-skew = <8>;
|
||||
cs0_dq2_rx_de-skew = <7>;
|
||||
cs0_dq2_tx_de-skew = <8>;
|
||||
cs0_dq3_rx_de-skew = <7>;
|
||||
cs0_dq3_tx_de-skew = <8>;
|
||||
cs0_dq4_rx_de-skew = <7>;
|
||||
cs0_dq4_tx_de-skew = <8>;
|
||||
cs0_dq5_rx_de-skew = <7>;
|
||||
cs0_dq5_tx_de-skew = <8>;
|
||||
cs0_dq6_rx_de-skew = <7>;
|
||||
cs0_dq6_tx_de-skew = <8>;
|
||||
cs0_dq7_rx_de-skew = <7>;
|
||||
cs0_dq7_tx_de-skew = <8>;
|
||||
cs0_dqs0_rx_de-skew = <6>;
|
||||
cs0_dqs0p_tx_de-skew = <9>;
|
||||
cs0_dqs0n_tx_de-skew = <9>;
|
||||
|
||||
cs0_dm1_rx_de-skew = <7>;
|
||||
cs0_dm1_tx_de-skew = <7>;
|
||||
cs0_dq8_rx_de-skew = <7>;
|
||||
cs0_dq8_tx_de-skew = <8>;
|
||||
cs0_dq9_rx_de-skew = <7>;
|
||||
cs0_dq9_tx_de-skew = <7>;
|
||||
cs0_dq10_rx_de-skew = <7>;
|
||||
cs0_dq10_tx_de-skew = <8>;
|
||||
cs0_dq11_rx_de-skew = <7>;
|
||||
cs0_dq11_tx_de-skew = <7>;
|
||||
cs0_dq12_rx_de-skew = <7>;
|
||||
cs0_dq12_tx_de-skew = <8>;
|
||||
cs0_dq13_rx_de-skew = <7>;
|
||||
cs0_dq13_tx_de-skew = <7>;
|
||||
cs0_dq14_rx_de-skew = <7>;
|
||||
cs0_dq14_tx_de-skew = <8>;
|
||||
cs0_dq15_rx_de-skew = <7>;
|
||||
cs0_dq15_tx_de-skew = <7>;
|
||||
cs0_dqs1_rx_de-skew = <7>;
|
||||
cs0_dqs1p_tx_de-skew = <9>;
|
||||
cs0_dqs1n_tx_de-skew = <9>;
|
||||
|
||||
cs0_dm2_rx_de-skew = <7>;
|
||||
cs0_dm2_tx_de-skew = <8>;
|
||||
cs0_dq16_rx_de-skew = <7>;
|
||||
cs0_dq16_tx_de-skew = <8>;
|
||||
cs0_dq17_rx_de-skew = <7>;
|
||||
cs0_dq17_tx_de-skew = <8>;
|
||||
cs0_dq18_rx_de-skew = <7>;
|
||||
cs0_dq18_tx_de-skew = <8>;
|
||||
cs0_dq19_rx_de-skew = <7>;
|
||||
cs0_dq19_tx_de-skew = <8>;
|
||||
cs0_dq20_rx_de-skew = <7>;
|
||||
cs0_dq20_tx_de-skew = <8>;
|
||||
cs0_dq21_rx_de-skew = <7>;
|
||||
cs0_dq21_tx_de-skew = <8>;
|
||||
cs0_dq22_rx_de-skew = <7>;
|
||||
cs0_dq22_tx_de-skew = <8>;
|
||||
cs0_dq23_rx_de-skew = <7>;
|
||||
cs0_dq23_tx_de-skew = <8>;
|
||||
cs0_dqs2_rx_de-skew = <6>;
|
||||
cs0_dqs2p_tx_de-skew = <9>;
|
||||
cs0_dqs2n_tx_de-skew = <9>;
|
||||
|
||||
cs0_dm3_rx_de-skew = <7>;
|
||||
cs0_dm3_tx_de-skew = <7>;
|
||||
cs0_dq24_rx_de-skew = <7>;
|
||||
cs0_dq24_tx_de-skew = <8>;
|
||||
cs0_dq25_rx_de-skew = <7>;
|
||||
cs0_dq25_tx_de-skew = <7>;
|
||||
cs0_dq26_rx_de-skew = <7>;
|
||||
cs0_dq26_tx_de-skew = <7>;
|
||||
cs0_dq27_rx_de-skew = <7>;
|
||||
cs0_dq27_tx_de-skew = <7>;
|
||||
cs0_dq28_rx_de-skew = <7>;
|
||||
cs0_dq28_tx_de-skew = <7>;
|
||||
cs0_dq29_rx_de-skew = <7>;
|
||||
cs0_dq29_tx_de-skew = <7>;
|
||||
cs0_dq30_rx_de-skew = <7>;
|
||||
cs0_dq30_tx_de-skew = <7>;
|
||||
cs0_dq31_rx_de-skew = <7>;
|
||||
cs0_dq31_tx_de-skew = <7>;
|
||||
cs0_dqs3_rx_de-skew = <7>;
|
||||
cs0_dqs3p_tx_de-skew = <9>;
|
||||
cs0_dqs3n_tx_de-skew = <9>;
|
||||
|
||||
cs1_dm0_rx_de-skew = <7>;
|
||||
cs1_dm0_tx_de-skew = <8>;
|
||||
cs1_dq0_rx_de-skew = <7>;
|
||||
cs1_dq0_tx_de-skew = <8>;
|
||||
cs1_dq1_rx_de-skew = <7>;
|
||||
cs1_dq1_tx_de-skew = <8>;
|
||||
cs1_dq2_rx_de-skew = <7>;
|
||||
cs1_dq2_tx_de-skew = <8>;
|
||||
cs1_dq3_rx_de-skew = <7>;
|
||||
cs1_dq3_tx_de-skew = <8>;
|
||||
cs1_dq4_rx_de-skew = <7>;
|
||||
cs1_dq4_tx_de-skew = <8>;
|
||||
cs1_dq5_rx_de-skew = <7>;
|
||||
cs1_dq5_tx_de-skew = <8>;
|
||||
cs1_dq6_rx_de-skew = <7>;
|
||||
cs1_dq6_tx_de-skew = <8>;
|
||||
cs1_dq7_rx_de-skew = <7>;
|
||||
cs1_dq7_tx_de-skew = <8>;
|
||||
cs1_dqs0_rx_de-skew = <6>;
|
||||
cs1_dqs0p_tx_de-skew = <9>;
|
||||
cs1_dqs0n_tx_de-skew = <9>;
|
||||
|
||||
cs1_dm1_rx_de-skew = <7>;
|
||||
cs1_dm1_tx_de-skew = <7>;
|
||||
cs1_dq8_rx_de-skew = <7>;
|
||||
cs1_dq8_tx_de-skew = <8>;
|
||||
cs1_dq9_rx_de-skew = <7>;
|
||||
cs1_dq9_tx_de-skew = <7>;
|
||||
cs1_dq10_rx_de-skew = <7>;
|
||||
cs1_dq10_tx_de-skew = <8>;
|
||||
cs1_dq11_rx_de-skew = <7>;
|
||||
cs1_dq11_tx_de-skew = <7>;
|
||||
cs1_dq12_rx_de-skew = <7>;
|
||||
cs1_dq12_tx_de-skew = <8>;
|
||||
cs1_dq13_rx_de-skew = <7>;
|
||||
cs1_dq13_tx_de-skew = <7>;
|
||||
cs1_dq14_rx_de-skew = <7>;
|
||||
cs1_dq14_tx_de-skew = <8>;
|
||||
cs1_dq15_rx_de-skew = <7>;
|
||||
cs1_dq15_tx_de-skew = <7>;
|
||||
cs1_dqs1_rx_de-skew = <7>;
|
||||
cs1_dqs1p_tx_de-skew = <9>;
|
||||
cs1_dqs1n_tx_de-skew = <9>;
|
||||
|
||||
cs1_dm2_rx_de-skew = <7>;
|
||||
cs1_dm2_tx_de-skew = <8>;
|
||||
cs1_dq16_rx_de-skew = <7>;
|
||||
cs1_dq16_tx_de-skew = <8>;
|
||||
cs1_dq17_rx_de-skew = <7>;
|
||||
cs1_dq17_tx_de-skew = <8>;
|
||||
cs1_dq18_rx_de-skew = <7>;
|
||||
cs1_dq18_tx_de-skew = <8>;
|
||||
cs1_dq19_rx_de-skew = <7>;
|
||||
cs1_dq19_tx_de-skew = <8>;
|
||||
cs1_dq20_rx_de-skew = <7>;
|
||||
cs1_dq20_tx_de-skew = <8>;
|
||||
cs1_dq21_rx_de-skew = <7>;
|
||||
cs1_dq21_tx_de-skew = <8>;
|
||||
cs1_dq22_rx_de-skew = <7>;
|
||||
cs1_dq22_tx_de-skew = <8>;
|
||||
cs1_dq23_rx_de-skew = <7>;
|
||||
cs1_dq23_tx_de-skew = <8>;
|
||||
cs1_dqs2_rx_de-skew = <6>;
|
||||
cs1_dqs2p_tx_de-skew = <9>;
|
||||
cs1_dqs2n_tx_de-skew = <9>;
|
||||
|
||||
cs1_dm3_rx_de-skew = <7>;
|
||||
cs1_dm3_tx_de-skew = <7>;
|
||||
cs1_dq24_rx_de-skew = <7>;
|
||||
cs1_dq24_tx_de-skew = <8>;
|
||||
cs1_dq25_rx_de-skew = <7>;
|
||||
cs1_dq25_tx_de-skew = <7>;
|
||||
cs1_dq26_rx_de-skew = <7>;
|
||||
cs1_dq26_tx_de-skew = <7>;
|
||||
cs1_dq27_rx_de-skew = <7>;
|
||||
cs1_dq27_tx_de-skew = <7>;
|
||||
cs1_dq28_rx_de-skew = <7>;
|
||||
cs1_dq28_tx_de-skew = <7>;
|
||||
cs1_dq29_rx_de-skew = <7>;
|
||||
cs1_dq29_tx_de-skew = <7>;
|
||||
cs1_dq30_rx_de-skew = <7>;
|
||||
cs1_dq30_tx_de-skew = <7>;
|
||||
cs1_dq31_rx_de-skew = <7>;
|
||||
cs1_dq31_tx_de-skew = <7>;
|
||||
cs1_dqs3_rx_de-skew = <7>;
|
||||
cs1_dqs3p_tx_de-skew = <9>;
|
||||
cs1_dqs3n_tx_de-skew = <9>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,733 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/pwm/pwm.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "rk3399.dtsi"
|
||||
#include "rk3399-opp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Dilusense DLFR100";
|
||||
compatible = "dilusense,dlfr100", "rockchip,rk3399";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
clkin_gmac: external-gmac-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "clkin_gmac";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
clocks = <&rk808 1>;
|
||||
clock-names = "ext_clock";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_enable_h>;
|
||||
reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
vcc5v0_host: vcc5v0-host-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_host_en>;
|
||||
regulator-name = "vcc5v0_host";
|
||||
};
|
||||
|
||||
vcc_phy: vcc-phy-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_phy";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc_sd: vcc-sd {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc_sd_h>;
|
||||
regulator-name = "vcc_sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
adc-keys {
|
||||
compatible = "adc-keys";
|
||||
io-channels = <&saradc 1>;
|
||||
io-channel-names = "buttons";
|
||||
keyup-threshold-microvolt = <1800000>;
|
||||
poll-interval = <100>;
|
||||
|
||||
button-up {
|
||||
label = "Volume Up";
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
press-threshold-microvolt = <100000>;
|
||||
};
|
||||
|
||||
button-down {
|
||||
label = "Volume Down";
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
press-threshold-microvolt = <300000>;
|
||||
};
|
||||
|
||||
back {
|
||||
label = "Back";
|
||||
linux,code = <KEY_BACK>;
|
||||
press-threshold-microvolt = <985000>;
|
||||
};
|
||||
|
||||
menu {
|
||||
label = "Menu";
|
||||
linux,code = <KEY_MENU>;
|
||||
press-threshold-microvolt = <0x1314000>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
autorepeat;
|
||||
pinctrl-0 = <&pwr_btn>;
|
||||
|
||||
power {
|
||||
debounce-interval = <100>;
|
||||
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
|
||||
label = "GPIO Key Power";
|
||||
linux,code = <KEY_POWER>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
rt5640-sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "realtek,rt5640-codec";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,mclk-fs = <256>;
|
||||
simple-audio-card,widgets =
|
||||
"Microphone", "Mic Jack",
|
||||
"Headphone", "Headphones";
|
||||
simple-audio-card,routing =
|
||||
"Mic Jack", "micbias1",
|
||||
"Headphones", "HPOL",
|
||||
"Headphones", "HPOR";
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&i2s0>;
|
||||
};
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&rt5640>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu_l0 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l1 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l2 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l3 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_b0 {
|
||||
cpu-supply = <&vdd_cpu_b>;
|
||||
};
|
||||
|
||||
&cpu_b1 {
|
||||
cpu-supply = <&vdd_cpu_b>;
|
||||
};
|
||||
|
||||
&emmc_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac {
|
||||
assigned-clocks = <&cru SCLK_RMII_SRC>;
|
||||
assigned-clock-parents = <&clkin_gmac>;
|
||||
clock_in_out = "input";
|
||||
phy-supply = <&vcc_phy>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&rtl8211e>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>;
|
||||
tx_delay = <0x28>;
|
||||
rx_delay = <0x11>;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rtl8211e: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
rk808: pmic@1b {
|
||||
compatible = "rockchip,rk808";
|
||||
reg = <0x1b>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "rk808-clkout1", "rk808-clkout2";
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
vcc10-supply = <&vcc3v3_sys>;
|
||||
vcc11-supply = <&vcc3v3_sys>;
|
||||
vcc12-supply = <&vcc3v3_sys>;
|
||||
vddio-supply = <&vcc1v8_pmu>;
|
||||
|
||||
regulators {
|
||||
vdd_center: DCDC_REG1 {
|
||||
regulator-name = "vdd_center";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_l: DCDC_REG2 {
|
||||
regulator-name = "vdd_cpu_l";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG4 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc1v8_dvp: LDO_REG1 {
|
||||
regulator-name = "vcc1v8_dvp";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v0_tp: LDO_REG2 {
|
||||
regulator-name = "vcc3v0_tp";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc1v8_pmu: LDO_REG3 {
|
||||
regulator-name = "vcc1v8_pmu";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sdio: LDO_REG4 {
|
||||
regulator-name = "vcc_sdio";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca3v0_codec: LDO_REG5 {
|
||||
regulator-name = "vcca3v0_codec";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v5: LDO_REG6 {
|
||||
regulator-name = "vcc_1v5";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1500000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_codec: LDO_REG7 {
|
||||
regulator-name = "vcca1v8_codec";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v0: LDO_REG8 {
|
||||
regulator-name = "vcc_3v0";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_s3: SWITCH_REG1 {
|
||||
regulator-name = "vcc3v3_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_s0: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_b: regulator@40 {
|
||||
compatible = "silergy,syr827";
|
||||
reg = <0x40>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
pinctrl-0 = <&vsel1_pin>;
|
||||
pinctrl-names = "default";
|
||||
regulator-name = "vdd_cpu_b";
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-ramp-delay = <1000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-state = <3>;
|
||||
vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: regulator@41 {
|
||||
compatible = "silergy,syr828";
|
||||
reg = <0x41>;
|
||||
pinctrl-0 = <&vsel2_pin>;
|
||||
pinctrl-names = "default";
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-ramp-delay = <1000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-state = <3>;
|
||||
vsel-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
isl1208@6f {
|
||||
compatible = "isil,isl1208";
|
||||
reg = <0x6f>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
i2c-scl-rising-time-ns = <300>;
|
||||
i2c-scl-falling-time-ns = <15>;
|
||||
status = "okay";
|
||||
|
||||
rt5640: rt5640@1c {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "realtek,rt5640";
|
||||
reg = <0x1c>;
|
||||
realtek,in1-differential;
|
||||
pinctrl-0 = <&i2s_8ch_mclk>;
|
||||
clocks = <&cru SCLK_I2S_8CH_OUT>;
|
||||
clock-names = "mclk";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2s0 {
|
||||
rockchip,playback-channels = <8>;
|
||||
rockchip,capture-channels = <8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2s2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&io_domains {
|
||||
status = "okay";
|
||||
|
||||
bt656-supply = <&vcc_3v0>;
|
||||
audio-supply = <&vcca1v8_codec>;
|
||||
sdmmc-supply = <&vcc_sdio>;
|
||||
gpio1830-supply = <&vcc_3v0>;
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
ep-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
max-link-speed = <1>;
|
||||
num-lanes = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_clkreqn_cpm>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0 {
|
||||
reg = <0x00000000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie-eth@0,0 {
|
||||
compatible = "realtek,r8168";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
realtek,led-data = <0x87>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
buttons {
|
||||
pwr_btn: pwr-btn {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
i2s0 {
|
||||
i2s_8ch_mclk: i2s-8ch-mclk {
|
||||
rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int_l: pmic-int-l {
|
||||
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
vsel1_pin: vsel1-pin {
|
||||
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
|
||||
vsel2_pin: vsel2-pin {
|
||||
rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
|
||||
pmic_dvs2:pmic-dvs2 {
|
||||
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio-pwrseq {
|
||||
wifi_enable_h: wifi-enable-h {
|
||||
rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb2 {
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sd {
|
||||
vcc_sd_h: vcc-sd-h {
|
||||
rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac {
|
||||
phy_intb: phy-intb {
|
||||
rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
phy_rstb: phy-rstb {
|
||||
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdio0 {
|
||||
bus-width = <4>;
|
||||
disable-wp;
|
||||
cap-sd-highspeed;
|
||||
cap-sdio-irq;
|
||||
keep-power-in-suspend;
|
||||
clock-frequency = <50000000>;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
clock-frequency = <150000000>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc_sd>;
|
||||
vqmmc-supply = <&vcc_sdio>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tcphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tcphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
/* tshut mode 0:CRU 1:GPIO */
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
/* tshut polarity 0:LOW 1:HIGH */
|
||||
rockchip,hw-tshut-polarity = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_xfer &uart0_cts>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&usbdrd3_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&vopb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,664 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "rk3399.dtsi"
|
||||
#include "rk3399-opp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SHAREVDI GuangMiao G4C";
|
||||
compatible = "sharevdi,guangmiao-g4c", "rockchip,rk3399";
|
||||
|
||||
/delete-node/ display-subsystem;
|
||||
|
||||
aliases {
|
||||
led-boot = &status_led;
|
||||
led-failsafe = &status_led;
|
||||
led-running = &status_led;
|
||||
led-upgrade = &status_led;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
clkin_gmac: external-gmac-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "clkin_gmac";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
vcc_sys: vcc-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc_sys";
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_sys";
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
vcc_0v9: vcc-0v9 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vcc_0v9";
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
vcc5v0_host0: vcc5v0-host0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc5v0_host0";
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
vdd_log: vdd-log {
|
||||
compatible = "pwm-regulator";
|
||||
pwms = <&pwm2 0 25000 1>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-name = "vdd_log";
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&reset_button_pin>;
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
debounce-interval = <100>;
|
||||
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lan_led_pin>, <&status_led_pin>, <&wan_led_pin>;
|
||||
|
||||
lan_led: led-lan {
|
||||
gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:lan";
|
||||
};
|
||||
|
||||
status_led: led-status {
|
||||
gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:status";
|
||||
};
|
||||
|
||||
wan_led: led-wan {
|
||||
gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:wan";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu_b0 {
|
||||
cpu-supply = <&vdd_cpu_b>;
|
||||
};
|
||||
|
||||
&cpu_b1 {
|
||||
cpu-supply = <&vdd_cpu_b>;
|
||||
};
|
||||
|
||||
&cpu_l0 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l1 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l2 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l3 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&emmc_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac {
|
||||
assigned-clock-parents = <&clkin_gmac>;
|
||||
assigned-clocks = <&cru SCLK_RMII_SRC>;
|
||||
clock_in_out = "input";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_pmeb>, <&phy_rstb>;
|
||||
phy-handle = <&rtl8211e>;
|
||||
phy-mode = "rgmii";
|
||||
phy-supply = <&vcc3v3_s3>;
|
||||
tx_delay = <0x28>;
|
||||
rx_delay = <0x11>;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rtl8211e: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <400000>;
|
||||
i2c-scl-rising-time-ns = <160>;
|
||||
i2c-scl-falling-time-ns = <30>;
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu_b: regulator@40 {
|
||||
compatible = "silergy,syr827";
|
||||
reg = <0x40>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cpu_b_sleep>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-name = "vdd_cpu_b";
|
||||
regulator-ramp-delay = <1000>;
|
||||
vin-supply = <&vcc_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: regulator@41 {
|
||||
compatible = "silergy,syr828";
|
||||
reg = <0x41>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gpu_sleep>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-ramp-delay = <1000>;
|
||||
vin-supply = <&vcc_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk808: pmic@1b {
|
||||
compatible = "rockchip,rk808";
|
||||
reg = <0x1b>;
|
||||
clock-output-names = "rtc_clko_soc", "rtc_clko_wifi";
|
||||
#clock-cells = <1>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int_l>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc_sys>;
|
||||
vcc2-supply = <&vcc_sys>;
|
||||
vcc3-supply = <&vcc_sys>;
|
||||
vcc4-supply = <&vcc_sys>;
|
||||
vcc6-supply = <&vcc_sys>;
|
||||
vcc7-supply = <&vcc_sys>;
|
||||
vcc8-supply = <&vcc_3v0>;
|
||||
vcc9-supply = <&vcc_sys>;
|
||||
vcc10-supply = <&vcc_sys>;
|
||||
vcc11-supply = <&vcc_sys>;
|
||||
vcc12-supply = <&vcc_sys>;
|
||||
vddio-supply = <&vcc_3v0>;
|
||||
|
||||
regulators {
|
||||
vdd_center: DCDC_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_center";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_l: DCDC_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_cpu_l";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc_ddr";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_vldo1: LDO_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_vldo1";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_vldo2: LDO_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_vldo2";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sdio: LDO_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc_sdio";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v0_sd: LDO_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-name = "vcc3v0_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v5: LDO_REG6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-name = "vcc_1v5";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1500000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_codec: LDO_REG7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca1v8_codec";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v0: LDO_REG8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-name = "vcc_3v0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_s3: SWITCH_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc3v3_s3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_s0: SWITCH_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc3v3_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
i2c-scl-rising-time-ns = <450>;
|
||||
i2c-scl-falling-time-ns = <15>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&io_domains {
|
||||
bt656-supply = <&vcc_1v8>;
|
||||
audio-supply = <&vcca1v8_codec>;
|
||||
sdmmc-supply = <&vcc_sdio>;
|
||||
gpio1830-supply = <&vcc_3v0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
ep-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
max-link-speed = <1>;
|
||||
num-lanes = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_clkreqnb_cpm>;
|
||||
vpcie0v9-supply = <&vcc_0v9>;
|
||||
vpcie1v8-supply = <&vcca_1v8>;
|
||||
vpcie3v3-supply = <&vcc3v3_sys>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0 {
|
||||
reg = <0x00000000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie-eth@0,0 {
|
||||
compatible = "realtek,r8168";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
|
||||
realtek,led-data = <0x87>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
gpio-leds {
|
||||
lan_led_pin: lan-led-pin {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
status_led_pin: status-led-pin {
|
||||
rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
wan_led_pin: wan-led-pin {
|
||||
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac {
|
||||
phy_intb: phy-intb {
|
||||
rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
phy_pmeb: phy-pmeb {
|
||||
rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
phy_rstb: phy-rstb {
|
||||
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
cpu_b_sleep: cpu-b-sleep {
|
||||
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
|
||||
gpu_sleep: gpu-sleep {
|
||||
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
|
||||
pmic_int_l: pmic-int-l {
|
||||
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
rockchip-key {
|
||||
reset_button_pin: reset-button-pin {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio {
|
||||
bt_reg_on_h: bt-reg-on-h {
|
||||
/* external pullup to VCC1V8_PMUPLL */
|
||||
rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc {
|
||||
sdmmc0_det_l: sdmmc0-det-l {
|
||||
rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmu1830-supply = <&vcc_3v0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
pinctrl-names = "active";
|
||||
pinctrl-0 = <&pwm2_pin_pull_down>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcc_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
mmc-hs200-1_8v;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>;
|
||||
vqmmc-supply = <&vcc_sdio>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tcphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tcphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0_host {
|
||||
phy-supply = <&vcc5v0_host0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1_host {
|
||||
phy-supply = <&vcc5v0_host0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd3_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_0 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_1 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,837 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/input/linux-event-codes.h>
|
||||
#include "rk3399.dtsi"
|
||||
#include "rk3399-opp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SHAREVDI H3399PC";
|
||||
compatible = "sharevdi,h3399pc", "rockchip,rk3399";
|
||||
|
||||
aliases {
|
||||
mmc0 = &sdio0;
|
||||
mmc1 = &sdmmc;
|
||||
mmc2 = &sdhci;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
clkin_gmac: external-gmac-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "clkin_gmac";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
dc_12v: dc-12v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dc_12v";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
autorepeat;
|
||||
|
||||
power {
|
||||
debounce-interval = <100>;
|
||||
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
|
||||
label = "GPIO Key Power";
|
||||
linux,code = <KEY_POWER>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&work_led_pin>, <&diy_led_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
work_led: led-0 {
|
||||
label = "work";
|
||||
default-state = "on";
|
||||
gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
diy_led: led-1 {
|
||||
label = "diy";
|
||||
default-state = "off";
|
||||
gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
sound: sound {
|
||||
compatible = "audio-graph-card";
|
||||
label = "Analog";
|
||||
dais = <&i2s0_p0>;
|
||||
};
|
||||
|
||||
sound-dit {
|
||||
compatible = "audio-graph-card";
|
||||
label = "SPDIF";
|
||||
dais = <&spdif_p0>;
|
||||
};
|
||||
|
||||
spdif-dit {
|
||||
compatible = "linux,spdif-dit";
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
port {
|
||||
dit_p0_0: endpoint {
|
||||
remote-endpoint = <&spdif_p0_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
clocks = <&rk808 1>;
|
||||
clock-names = "ext_clock";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_enable_h>;
|
||||
|
||||
/*
|
||||
* On the module itself this is one of these (depending
|
||||
* on the actual card populated):
|
||||
* - SDIO_RESET_L_WL_REG_ON
|
||||
* - PDN (power down when low)
|
||||
*/
|
||||
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
sound-dit {
|
||||
compatible = "audio-graph-card";
|
||||
label = "SPDIF";
|
||||
dais = <&spdif_p0>;
|
||||
};
|
||||
|
||||
spdif-dit {
|
||||
compatible = "linux,spdif-dit";
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
port {
|
||||
dit_p0_0: endpoint {
|
||||
remote-endpoint = <&spdif_p0_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* switched by pmic_sleep */
|
||||
vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc1v8_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc_1v8>;
|
||||
};
|
||||
|
||||
vcc1v8_sys: vcc1v8-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc1v8_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie: vcc3v3-pcie-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_pwr_en>;
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc3v3_3g: vcc3v3-3g-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_3g_drv>;
|
||||
regulator-name = "vcc3v3_3g";
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
/* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
|
||||
vcc5v0_host: vcc5v0-host-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_host_en &vcc5v0_host3_en>;
|
||||
regulator-name = "vcc5v0_host";
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
vcc5v0_hub: vcc5v0-hub-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_hub_en>;
|
||||
regulator-name = "vcc5v0_host";
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
vcc_sys: vcc-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vdd_log: vdd-log {
|
||||
compatible = "pwm-regulator";
|
||||
pwms = <&pwm2 0 25000 1>;
|
||||
regulator-name = "vdd_log";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
vcc_phy: vcc-phy-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_phy";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu_l0 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l1 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l2 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l3 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_b0 {
|
||||
cpu-supply = <&vdd_cpu_b>;
|
||||
};
|
||||
|
||||
&cpu_b1 {
|
||||
cpu-supply = <&vdd_cpu_b>;
|
||||
};
|
||||
|
||||
&emmc_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac {
|
||||
assigned-clocks = <&cru SCLK_RMII_SRC>;
|
||||
assigned-clock-parents = <&clkin_gmac>;
|
||||
clock_in_out = "input";
|
||||
phy-supply = <&vcc_lan>;
|
||||
phy-mode = "rgmii";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins>;
|
||||
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 10000 50000>;
|
||||
tx_delay = <0x28>;
|
||||
rx_delay = <0x11>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&i2c3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_cec>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <400000>;
|
||||
i2c-scl-rising-time-ns = <168>;
|
||||
i2c-scl-falling-time-ns = <4>;
|
||||
status = "okay";
|
||||
|
||||
rk808: pmic@1b {
|
||||
compatible = "rockchip,rk808";
|
||||
reg = <0x1b>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "xin32k", "rk808-clkout2";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int_l>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
vcc10-supply = <&vcc3v3_sys>;
|
||||
vcc11-supply = <&vcc3v3_sys>;
|
||||
vcc12-supply = <&vcc3v3_sys>;
|
||||
vddio-supply = <&vcc1v8_pmu>;
|
||||
|
||||
regulators {
|
||||
vdd_center: DCDC_REG1 {
|
||||
regulator-name = "vdd_center";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_l: DCDC_REG2 {
|
||||
regulator-name = "vdd_cpu_l";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG4 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc2v8_dvp: LDO_REG1 {
|
||||
regulator-name = "vcc2v8_dvp";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
vcc1v8_dvp: LDO_REG2 {
|
||||
regulator-name = "vcc1v8_dvp";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc1v8_pmu: LDO_REG3 {
|
||||
regulator-name = "vcc1v8_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sdio: LDO_REG4 {
|
||||
regulator-name = "vcc_sdio";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca3v0_codec: LDO_REG5 {
|
||||
regulator-name = "vcca3v0_codec";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v5: LDO_REG6 {
|
||||
regulator-name = "vcc_1v5";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1500000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_codec: LDO_REG7 {
|
||||
regulator-name = "vcca1v8_codec";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v0: LDO_REG8 {
|
||||
regulator-name = "vcc_3v0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_s3: vcc_lan: SWITCH_REG1 {
|
||||
regulator-name = "vcc3v3_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_s0: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_b: regulator@40 {
|
||||
compatible = "silergy,syr827";
|
||||
reg = <0x40>;
|
||||
fcs,suspend-voltage-selector = <0>;
|
||||
regulator-name = "vdd_cpu_b";
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-ramp-delay = <1000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vcc_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: regulator@41 {
|
||||
compatible = "silergy,syr828";
|
||||
reg = <0x41>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-ramp-delay = <1000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vcc_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
i2c-scl-rising-time-ns = <300>;
|
||||
i2c-scl-falling-time-ns = <15>;
|
||||
status = "okay";
|
||||
|
||||
es8316: codec@11 {
|
||||
compatible = "everest,es8316";
|
||||
reg = <0x11>;
|
||||
clocks = <&cru SCLK_I2S_8CH_OUT>;
|
||||
clock-names = "mclk";
|
||||
#sound-dai-cells = <0>;
|
||||
pinctrl-0 = <&i2s_8ch_mclk>;
|
||||
spk-con-gpio = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
hp-det-gpio = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
port {
|
||||
es8316_p0_0: endpoint {
|
||||
remote-endpoint = <&i2s0_p0_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2s0 {
|
||||
rockchip,playback-channels = <8>;
|
||||
rockchip,capture-channels = <8>;
|
||||
status = "okay";
|
||||
|
||||
i2s0_p0: port {
|
||||
i2s0_p0_0: endpoint {
|
||||
dai-format = "i2s";
|
||||
mclk-fs = <256>;
|
||||
remote-endpoint = <&es8316_p0_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2s1 {
|
||||
rockchip,playback-channels = <2>;
|
||||
rockchip,capture-channels = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2s2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&io_domains {
|
||||
status = "okay";
|
||||
|
||||
bt656-supply = <&vcc1v8_dvp>;
|
||||
audio-supply = <&vcca1v8_codec>;
|
||||
sdmmc-supply = <&vcc_sdio>;
|
||||
gpio1830-supply = <&vcc_3v0>;
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
|
||||
max-link-speed = <1>;
|
||||
num-lanes = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_clkreqn_cpm>;
|
||||
status = "okay";
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0x00000000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie-eth@0,0 {
|
||||
compatible = "realtek,r8168";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
realtek,led-data = <0x87>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmu1830-supply = <&vcc_3v0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
i2s0 {
|
||||
i2s_8ch_mclk: i2s-8ch-mclk {
|
||||
rockchip,pins = <4 RK_PB4 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
work_led_pin: work-led-pin {
|
||||
rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
diy_led_pin: diy-led-pin {
|
||||
rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie {
|
||||
pcie_pwr_en: pcie-pwr-en {
|
||||
rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
pcie_3g_drv: pcie-3g-drv {
|
||||
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int_l: pmic-int-l {
|
||||
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
vsel1_pin: vsel1-pin {
|
||||
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
|
||||
vsel2_pin: vsel2-pin {
|
||||
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio-pwrseq {
|
||||
wifi_enable_h: wifi-enable-h {
|
||||
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb2 {
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
vcc5v0_host3_en: vcc5v0-host3-en {
|
||||
rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
vcc5v0_hub_en: vcc5v0-hub-en {
|
||||
rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca1v8_s3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdio0 {
|
||||
bus-width = <4>;
|
||||
cap-sdio-irq;
|
||||
cap-sd-highspeed;
|
||||
keep-power-in-suspend;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
|
||||
sd-uhs-sdr104;
|
||||
|
||||
/* Power supply */
|
||||
vqmmc-supply = <&vcc1v8_s3>; /* IO line */
|
||||
vmmc-supply = <&vcc_sdio>; /* card's power */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
disable-wp;
|
||||
cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
|
||||
max-frequency = <150000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spdif {
|
||||
pinctrl-0 = <&spdif_bus_1>;
|
||||
status = "okay";
|
||||
|
||||
spdif_p0: port {
|
||||
spdif_p0_0: endpoint {
|
||||
remote-endpoint = <&dit_p0_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tcphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tcphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
/* tshut mode 0:CRU 1:GPIO */
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
/* tshut polarity 0:LOW 1:HIGH */
|
||||
rockchip,hw-tshut-polarity = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_xfer &uart0_cts>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&usbdrd3_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&vopb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
1127
6.1/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3399-king3399.dts
Executable file
1127
6.1/target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3399-king3399.dts
Executable file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,687 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "rk3399.dtsi"
|
||||
#include "rk3399-opp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Rocktech MPC1903";
|
||||
compatible = "rocktech,mpc1903", "rockchip,rk3399";
|
||||
|
||||
aliases {
|
||||
mmc0 = &sdmmc;
|
||||
mmc1 = &sdhci;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
clkin_gmac: external-gmac-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "clkin_gmac";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
clocks = <&rk808 1>;
|
||||
clock-names = "ext_clock";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_enable_h>;
|
||||
reset-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
vcc12v_dcin: dc-12v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc12v_dcin";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc5v0_host: vcc5v0-host {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_host_en>;
|
||||
regulator-name = "vcc5v0_host";
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc5v0_hub: vcc5v0-hub {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_hub_en>;
|
||||
regulator-name = "vcc5v0_hub";
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc3v3_gsm: vcc3v3-gsm {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc3v3_gsm_en>;
|
||||
regulator-name = "vcc3v3_gsm";
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
vcc_lan: vcc-phy {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_lan";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vdd_log: vdd-log {
|
||||
compatible = "pwm-regulator";
|
||||
pwms = <&pwm2 0 25000 1>;
|
||||
regulator-name = "vdd_log";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&status_led_pin>;
|
||||
|
||||
status_led: status-led {
|
||||
label = "status_led";
|
||||
linux,default-trigger = "heartbeat";
|
||||
gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu_l0 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l1 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l2 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l3 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_b0 {
|
||||
cpu-supply = <&vdd_cpu_b>;
|
||||
};
|
||||
|
||||
&cpu_b1 {
|
||||
cpu-supply = <&vdd_cpu_b>;
|
||||
};
|
||||
|
||||
&emmc_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac {
|
||||
assigned-clocks = <&cru SCLK_RMII_SRC>;
|
||||
assigned-clock-parents = <&clkin_gmac>;
|
||||
clock_in_out = "input";
|
||||
phy-supply = <&vcc_lan>;
|
||||
phy-mode = "rgmii";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins>;
|
||||
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 10000 50000>;
|
||||
tx_delay = <0x28>;
|
||||
rx_delay = <0x11>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&i2c3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_i2c_xfer>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <400000>;
|
||||
i2c-scl-rising-time-ns = <168>;
|
||||
i2c-scl-falling-time-ns = <4>;
|
||||
status = "okay";
|
||||
|
||||
rk808: pmic@1b {
|
||||
compatible = "rockchip,rk808";
|
||||
reg = <0x1b>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "xin32k", "rk808-clkout2";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int_l>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc5v0_sys>;
|
||||
vcc2-supply = <&vcc5v0_sys>;
|
||||
vcc3-supply = <&vcc5v0_sys>;
|
||||
vcc4-supply = <&vcc5v0_sys>;
|
||||
vcc6-supply = <&vcc5v0_sys>;
|
||||
vcc7-supply = <&vcc5v0_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc5v0_sys>;
|
||||
vcc10-supply = <&vcc5v0_sys>;
|
||||
vcc11-supply = <&vcc5v0_sys>;
|
||||
vcc12-supply = <&vcc3v3_sys>;
|
||||
vddio-supply = <&vcc_3v0>;
|
||||
|
||||
regulators {
|
||||
vdd_center: DCDC_REG1 {
|
||||
regulator-name = "vdd_center";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_l: DCDC_REG2 {
|
||||
regulator-name = "vdd_cpu_l";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG4 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
gen_1v8: LDO_REG1 {
|
||||
regulator-name = "gen_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
gen_3v0: LDO_REG2 {
|
||||
regulator-name = "gen_3v0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc1v8_pmu: LDO_REG3 {
|
||||
regulator-name = "vcc1v8_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sdio: LDO_REG4 {
|
||||
regulator-name = "vcc_sdio";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca3v0_codec: LDO_REG5 {
|
||||
regulator-name = "vcca3v0_codec";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v5: LDO_REG6 {
|
||||
regulator-name = "vcc_1v5";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc1v8_codec: LDO_REG7 {
|
||||
regulator-name = "vcc1v8_codec";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v0: LDO_REG8 {
|
||||
regulator-name = "vcc_3v0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_s3: SWITCH_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc3v3_s3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_s0: SWITCH_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc3v3_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_b: regulator@40 {
|
||||
compatible = "silergy,syr827";
|
||||
reg = <0x40>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vsel1_pin>;
|
||||
regulator-name = "vdd_cpu_b";
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-ramp-delay = <1000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: regulator@41 {
|
||||
compatible = "silergy,syr828";
|
||||
reg = <0x41>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vsel2_pin>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-ramp-delay = <1000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rtc: pcf85263@51 {
|
||||
compatible = "nxp,pcf85263";
|
||||
reg = <0x51>;
|
||||
pinctrl-0 = <&rtc_int>;
|
||||
rtc_int_gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
i2c-scl-rising-time-ns = <300>;
|
||||
i2c-scl-falling-time-ns = <15>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
clock-frequency = <400000>;
|
||||
i2c-scl-rising-time-ns = <450>;
|
||||
i2c-scl-falling-time-ns = <15>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2s0 {
|
||||
rockchip,i2s-broken-burst-len;
|
||||
rockchip,playback-channels = <8>;
|
||||
rockchip,capture-channels = <8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2s2 {
|
||||
rockchip,bclk-fs = <128>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&io_domains {
|
||||
status = "okay";
|
||||
|
||||
bt656-supply = <&vcc_3v0>;
|
||||
audio-supply = <&vcc1v8_codec>;
|
||||
sdmmc-supply = <&vcc_sdio>;
|
||||
gpio1830-supply = <&vcc_3v0>;
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
status = "okay";
|
||||
|
||||
pmu1830-supply = <&vcc_3v0>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
bt {
|
||||
bt_enable_h: bt-enable-h {
|
||||
rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int_l: pmic-int-l {
|
||||
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
vsel1_pin: vsel1-pin {
|
||||
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
|
||||
vsel2_pin: vsel2-pin {
|
||||
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
|
||||
usb2 {
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_hub_en: vcc5v0-hub-en {
|
||||
rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
vcc3v3_gsm_en: vcc3v3-gsm-en {
|
||||
rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
wifi {
|
||||
wifi_enable_h: wifi-enable-h {
|
||||
rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
rtc {
|
||||
rtc_int: rtc-int {
|
||||
rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
led {
|
||||
status_led_pin: status-led-pin {
|
||||
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
rockchip-key {
|
||||
power_key: power-key {
|
||||
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
status = "okay";
|
||||
|
||||
vref-supply = <&vcc_1v8>;
|
||||
};
|
||||
|
||||
&sdio0 {
|
||||
bus-width = <4>;
|
||||
clock-frequency = <50000000>;
|
||||
cap-sdio-irq;
|
||||
cap-sd-highspeed;
|
||||
keep-power-in-suspend;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
|
||||
sd-uhs-sdr104;
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
max-frequency = <150000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tcphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tcphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
status = "okay";
|
||||
rockchip,hw-tshut-temp = <120000>;
|
||||
/* tshut mode 0:CRU 1:GPIO */
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
/* tshut polarity 0:LOW 1:HIGH */
|
||||
rockchip,hw-tshut-polarity = <1>;
|
||||
};
|
||||
|
||||
&u2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0_host {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1_host {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&usbdrd3_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&vopb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3399-nanopi-r4s.dts"
|
||||
|
||||
/ {
|
||||
model = "FriendlyElec NanoPi R4SE";
|
||||
compatible = "friendlyarm,nanopi-r4se", "rockchip,rk3399";
|
||||
};
|
||||
|
||||
|
||||
&emmc_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,526 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
led-boot = &led_work;
|
||||
led-failsafe = &led_work;
|
||||
led-running = &led_work;
|
||||
led-upgrade = &led_work;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
vcc12v_dcin: vcc12v-dcin {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-name = "vcc12v_dcin";
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_sys";
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_sys";
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_usb: vcc5v0-usb {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_usb";
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg: vcc5v0-usb-otg {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_otg_en>;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_usb_otg";
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie: vcc3v3-pcie {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&reset_button_pin>;
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
debounce-interval = <50>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_work_en>;
|
||||
|
||||
led_work: led-0 {
|
||||
label = "blue:work-led";
|
||||
gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&display_subsystem {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1390000>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-name = "vcc_ddr";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-name = "vdda0v9_image";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda_0v9";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_acodec";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-init-microvolt = <950000>;
|
||||
regulator-name = "vcca1v8_image";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <950000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc_3v3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc3v3_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
data-lanes = <1 2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x1 {
|
||||
num-lanes = <1>;
|
||||
reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0,0 {
|
||||
reg = <0x00100000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
rtl8125_1: pcie-eth@10,0 {
|
||||
compatible = "pci10ec,8125";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
|
||||
realtek,led-data = <0x238>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
num-lanes = <1>;
|
||||
reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0,0 {
|
||||
reg = <0x00200000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
rtl8125_2: pcie-eth@20,0 {
|
||||
compatible = "pci10ec,8125";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
|
||||
realtek,led-data = <0x238>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
led_work_en: led_work_en {
|
||||
rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
rockchip-key {
|
||||
reset_button_pin: reset-button-pin {
|
||||
rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc3v3_pmu>;
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
phy-supply = <&vcc5v0_usb_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
|
@ -0,0 +1,660 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
// Copyright (c) 2022 AmadeusGhost <amadeus@jmu.edu.cn>
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
mmc0 = &sdmmc0;
|
||||
mmc1 = &sdhci;
|
||||
|
||||
led-boot = &led_work;
|
||||
led-failsafe = &led_work;
|
||||
led-running = &led_work;
|
||||
led-upgrade = &led_work;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
hdmi-con {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&reset_button_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
debounce-interval = <50>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_net_en>, <&led_sata_en>, <&led_work_en>;
|
||||
|
||||
net {
|
||||
label = "blue:net";
|
||||
gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
sata {
|
||||
label = "amber:sata";
|
||||
gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led_work: work {
|
||||
label = "green:work";
|
||||
gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc12v_dcin: vcc12v-dcin {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-name = "vcc12v_dcin";
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_sys";
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_sys";
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_usb: vcc5v0-usb {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_usb";
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_host: vcc5v0-usb-host {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_host_en>;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_usb_host";
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie: vcc3v3-pcie {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
startup-delay-us = <5000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
rk809-sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,name = "Analog RK809";
|
||||
simple-audio-card,mclk-fs = <256>;
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&i2s1_8ch>;
|
||||
};
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&rk809>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
avdd-0v9-supply = <&vdda0v9_image>;
|
||||
avdd-1v8-supply = <&vcca1v8_image>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_in {
|
||||
hdmi_in_vp0: endpoint {
|
||||
remote-endpoint = <&vp0_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_out {
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1390000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
|
||||
#clock-cells = <1>;
|
||||
clock-names = "mclk";
|
||||
clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
|
||||
rockchip,system-power-controller;
|
||||
#sound-dai-cells = <0>;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-name = "vcc_ddr";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-name = "vdda0v9_image";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda_0v9";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_acodec";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca1v8_image";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
codec {
|
||||
mic-in-differential;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&i2s0_8ch {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2s1_8ch {
|
||||
rockchip,trcm-sync-tx-only;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie2x1 {
|
||||
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
data-lanes = <1 2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x1 {
|
||||
num-lanes = <1>;
|
||||
reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0,0 {
|
||||
reg = <0x00100000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
rtl8125_1: pcie-eth@10,0 {
|
||||
compatible = "pci10ec,8125";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
num-lanes = <1>;
|
||||
reset-gpios = <&gpio2 RK_PD0 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0,0 {
|
||||
reg = <0x00200000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
rtl8125_2: pcie-eth@20,0 {
|
||||
compatible = "pci10ec,8125";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
button {
|
||||
reset_button_pin: reset-button-pin {
|
||||
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
led_net_en: led_net_en {
|
||||
rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
led_sata_en: led_sata_en {
|
||||
rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
led_work_en: led_work_en {
|
||||
rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb_host_en: vcc5v0_usb_host_en {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc3v3_pmu>;
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio2-supply = <&vcc_1v8>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi_in_vp0>;
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
|
@ -0,0 +1,119 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
// Copyright (c) 2023 mleaf <mleaf90@gmail.com>
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3568-mrkaio-m68s.dtsi"
|
||||
|
||||
/ {
|
||||
model = "EZPRO Mrkaio M68S PLUS";
|
||||
compatible = "ezpro,mrkaio-m68s-plus", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
led-boot = &led_sys;
|
||||
led-failsafe = &led_sys;
|
||||
led-running = &led_sys;
|
||||
led-upgrade = &led_sys;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_sys_en>;
|
||||
|
||||
led_sys: sys {
|
||||
label = "red:sys";
|
||||
gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
switch_otg: switch-otg {
|
||||
compatible = "regulator-fixed";
|
||||
gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb_otg_switch_en>;
|
||||
regulator-name = "switch_otg";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc3v3_pcie: vcc3v3-pcie {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
startup-delay-us = <5000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie2x1 {
|
||||
num-viewport = <4>;
|
||||
reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0,0 {
|
||||
reg = <0x00000000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
r8125_1: pcie@01,0 {
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
data-lanes = <1 2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x1 {
|
||||
num-viewport = <4>;
|
||||
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0,0 {
|
||||
reg = <0x00100000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
r8125_2: pcie@10,0 {
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
num-lanes = <1>;
|
||||
max-link-speed = <2>;
|
||||
num-ib-windows = <8>;
|
||||
num-ob-windows = <8>;
|
||||
num-viewport = <4>;
|
||||
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
led_sys_en: led_sys_en {
|
||||
rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb_host_en: vcc5v0_usb_host_en {
|
||||
rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
|
||||
rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
usb_otg_switch_en: usb-otg-switch_en {
|
||||
rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,154 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
// Copyright (c) 2022 AmadeusGhost <amadeus@jmu.edu.cn>
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3568-mrkaio-m68s.dtsi"
|
||||
|
||||
/ {
|
||||
model = "EZPRO Mrkaio M68S";
|
||||
compatible = "ezpro,mrkaio-m68s", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
ethernet1 = &gmac1;
|
||||
|
||||
led-boot = &led_sys;
|
||||
led-failsafe = &led_sys;
|
||||
led-running = &led_sys;
|
||||
led-upgrade = &led_sys;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_sata_en>, <&led_sys_en>;
|
||||
|
||||
sata {
|
||||
label = "blue:sata";
|
||||
gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led_sys: sys {
|
||||
label = "red:sys";
|
||||
gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
switch_otg: switch-otg {
|
||||
compatible = "regulator-fixed";
|
||||
gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb_otg_switch_en>;
|
||||
regulator-name = "switch_otg";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc5v0_ahci: vcc5v0-ahci {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sata_pwr_en>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_ahci";
|
||||
};
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
&gmac0_rgmii_clk
|
||||
&gmac0_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x3c>;
|
||||
rx_delay = <0x2f>;
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
&gmac1m1_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x42>;
|
||||
rx_delay = <0x28>;
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
led_sata_en: led_sata_en {
|
||||
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
led_sys_en: led_sys_en {
|
||||
rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sata {
|
||||
sata_pwr_en: sata-pwr-en {
|
||||
rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb_host_en: vcc5v0_usb_host_en {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
usb_otg_switch_en: usb-otg-switch_en {
|
||||
rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sata2 {
|
||||
target-supply = <&vcc5v0_ahci>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,523 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
mmc0 = &sdmmc0;
|
||||
mmc1 = &sdhci;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
hdmi-con {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
dc_12v: dc-12v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-name = "dc_12v";
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_sys";
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_sys";
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_host: vcc5v0-usb-host {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_host_en>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc5v0_usb_host";
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg: vcc5v0-usb-otg {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_otg_en>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc5v0_usb_otg";
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
avdd-0v9-supply = <&vdda0v9_image>;
|
||||
avdd-1v8-supply = <&vcca1v8_image>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_in {
|
||||
hdmi_in_vp0: endpoint {
|
||||
remote-endpoint = <&vp0_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_out {
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1390000>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-name = "vcc_ddr";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda0v9_image";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda_0v9";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_acodec";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca1v8_image";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc_3v3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc3v3_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&i2s0_8ch {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&pinctrl {
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc3v3_pmu>;
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio2-supply = <&vcc_1v8>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
phy-supply = <&vcc5v0_usb_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi_in_vp0>;
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
|
@ -0,0 +1,681 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
|
||||
* (http://www.friendlyarm.com)
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
model = "FriendlyElec NanoPi R5C";
|
||||
compatible = "friendlyarm,nanopi-r5c","rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &rtl8125_1;
|
||||
ethernet1 = &rtl8125_2;
|
||||
mmc0 = &sdmmc0;
|
||||
mmc1 = &sdhci;
|
||||
|
||||
led-boot = &sys_led;
|
||||
led-failsafe = &sys_led;
|
||||
led-running = &sys_led;
|
||||
led-upgrade = &sys_led;
|
||||
};
|
||||
|
||||
chosen: chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
hdmi-con {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&sys_led_pin>, <&lan_led_pin>,
|
||||
<&wan_led_pin>, <&wlan_led_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
sys_led: led-0 {
|
||||
gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||
label = "red:power";
|
||||
};
|
||||
|
||||
wan_led: led-1 {
|
||||
gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:wan";
|
||||
};
|
||||
|
||||
lan_led: led-2 {
|
||||
gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:lan";
|
||||
};
|
||||
|
||||
wlan_led: led-3 {
|
||||
gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:wlan";
|
||||
};
|
||||
};
|
||||
|
||||
vdd_5v: vdd-5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_5v";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vdd_5v>;
|
||||
};
|
||||
|
||||
vcc3v3_sysp: vcc3v3-sysp {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sysp";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vdd_5v>;
|
||||
};
|
||||
|
||||
vcc5v0_sysp: vcc5v0-sysp {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sysp";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc3v3_sysp>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_host: vcc5v0-usb-host {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_host_en>;
|
||||
regulator-name = "vcc5v0_usb_host";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_sysp>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg: vcc5v0-usb-otg {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_otg_en>;
|
||||
regulator-name = "vcc5v0_usb_otg";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_sysp>;
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
avdd-0v9-supply = <&vdda0v9_image>;
|
||||
avdd-1v8-supply = <&vcca1v8_image>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_in {
|
||||
hdmi_in_vp0: endpoint {
|
||||
remote-endpoint = <&vp0_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_out {
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
i2c-scl-rising-time-ns = <160>;
|
||||
i2c-scl-falling-time-ns = <30>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1390000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-name = "vdda0v9_image";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-name = "vdda_0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-name = "vccio_acodec";
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-name = "vcca_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-name = "vcca1v8_image";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_sd";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
i2c-scl-rising-time-ns = <160>;
|
||||
i2c-scl-falling-time-ns = <30>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
hym8563: hym8563@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "xin32k";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hym8563_int>;
|
||||
};
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&i2s0_8ch {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&pcie2x1 {
|
||||
num-lanes = <1>;
|
||||
num-viewport = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&m2_w_disable_pin>;
|
||||
reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
data-lanes = <1 2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x1 {
|
||||
num-lanes = <1>;
|
||||
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
pcie@10 {
|
||||
reg = <0x00100000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
rtl8125_1: pcie-eth@10,0 {
|
||||
compatible = "pci10ec,8125";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
|
||||
realtek,led-data = <0x78>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
num-lanes = <1>;
|
||||
reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
pcie@20 {
|
||||
reg = <0x00200000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
rtl8125_2: pcie-eth@20,0 {
|
||||
compatible = "pci10ec,8125";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
|
||||
realtek,led-data = <0x78>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
sys_led_pin: sys-led-pin {
|
||||
rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
lan_led_pin: lan-led-pin {
|
||||
rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
wan_led_pin: wan-led-pin {
|
||||
rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
wlan_led_pin: wlan-led-pin {
|
||||
rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
hym8563 {
|
||||
hym8563_int: hym8563-int {
|
||||
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
m2-pins {
|
||||
m2_w_disable_pin: m2-w-disable-pin {
|
||||
rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb_host_en: vcc5v0_usb_host_en {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
phy-supply = <&vcc5v0_usb_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi_in_vp0>;
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
|
@ -0,0 +1,710 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
|
||||
* (http://www.friendlyarm.com)
|
||||
*
|
||||
* Copyright (c) 2022 Marty Jones <mj8263788@gmail.com>
|
||||
* Copyright (c) 2022 Tianling Shen <cnsztl@gmail.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
model = "FriendlyElec NanoPi R5S";
|
||||
compatible = "friendlyarm,nanopi-r5s","rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
mmc0 = &sdmmc0;
|
||||
mmc1 = &sdhci;
|
||||
|
||||
led-boot = &sys_led;
|
||||
led-failsafe = &sys_led;
|
||||
led-running = &sys_led;
|
||||
led-upgrade = &sys_led;
|
||||
};
|
||||
|
||||
chosen: chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
hdmi-con {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>,
|
||||
<&sys_led_pin>, <&wan_led_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
lan1_led: led-0 {
|
||||
gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:lan1";
|
||||
};
|
||||
|
||||
lan2_led: led-1 {
|
||||
gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:lan2";
|
||||
};
|
||||
|
||||
sys_led: led-2 {
|
||||
gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
label = "red:power";
|
||||
};
|
||||
|
||||
wan_led: led-3 {
|
||||
gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:wan";
|
||||
};
|
||||
};
|
||||
|
||||
vdd_5v: vdd-5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_5v";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vdd_5v>;
|
||||
};
|
||||
|
||||
vcc3v3_sysp: vcc3v3-sysp {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sysp";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vdd_5v>;
|
||||
};
|
||||
|
||||
vcc5v0_sysp: vcc5v0-sysp {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sysp";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc3v3_sysp>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_host: vcc5v0-usb-host {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_host_en>;
|
||||
regulator-name = "vcc5v0_usb_host";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_sysp>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie: vcc3v3-pcie {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
startup-delay-us = <5000>;
|
||||
vin-supply = <&vcc3v3_sysp>;
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
clock_in_out = "output";
|
||||
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
&gmac0_rgmii_clk
|
||||
&gmac0_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 15ms, 50ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 15000 50000>;
|
||||
tx_delay = <0x3c>;
|
||||
rx_delay = <0x2f>;
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
avdd-0v9-supply = <&vdda0v9_image>;
|
||||
avdd-1v8-supply = <&vcca1v8_image>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_in {
|
||||
hdmi_in_vp0: endpoint {
|
||||
remote-endpoint = <&vp0_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_out {
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
i2c-scl-rising-time-ns = <160>;
|
||||
i2c-scl-falling-time-ns = <30>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1390000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-name = "vdda0v9_image";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-name = "vdda_0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-name = "vccio_acodec";
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-name = "vcca_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-name = "vcca1v8_image";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_sd";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
i2c-scl-rising-time-ns = <160>;
|
||||
i2c-scl-falling-time-ns = <30>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
hym8563: hym8563@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "xin32k";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hym8563_int>;
|
||||
};
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&i2s0_8ch {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy0: phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x1>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac_int>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie2x1 {
|
||||
num-lanes = <1>;
|
||||
num-viewport = <4>;
|
||||
reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
pcie@00 {
|
||||
reg = <0x00000000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
r8125_1: pcie@01,0 {
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
data-lanes = <1 2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x1 {
|
||||
num-lanes = <1>;
|
||||
num-viewport = <4>;
|
||||
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
pcie@10 {
|
||||
reg = <0x00100000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
r8125_2: pcie@10,0 {
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
num-lanes = <1>;
|
||||
max-link-speed = <2>;
|
||||
num-ib-windows = <8>;
|
||||
num-ob-windows = <8>;
|
||||
num-viewport = <4>;
|
||||
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
lan1_led_pin: lan1-led-pin {
|
||||
rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
lan2_led_pin: lan2-led-pin {
|
||||
rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sys_led_pin: sys-led-pin {
|
||||
rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
wan_led_pin: wan-led-pin {
|
||||
rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
eth_phy {
|
||||
gmac_int: gmac-int {
|
||||
rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
hym8563 {
|
||||
hym8563_int: hym8563-int {
|
||||
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb_host_en: vcc5v0_usb_host_en {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_host {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi_in_vp0>;
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
// Copyright (c) 2022 AmadeusGhost <amadeus@jmu.edu.cn>
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3568-hinlink-opc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "HINLINK OPC-H66K Board";
|
||||
compatible = "hinlink,opc-h66k", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &rtl8125_1;
|
||||
ethernet1 = &rtl8125_2;
|
||||
};
|
||||
};
|
||||
|
||||
&vcc3v3_pcie {
|
||||
gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
// Copyright (c) 2022 AmadeusGhost <amadeus@jmu.edu.cn>
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3568-hinlink-opc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "HINLINK OPC-H68K Board";
|
||||
compatible = "hinlink,opc-h68k", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
ethernet1 = &gmac1;
|
||||
};
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
&gmac0_rgmii_clk
|
||||
&gmac0_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x3c>;
|
||||
rx_delay = <0x2f>;
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
&gmac1m1_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x4f>;
|
||||
rx_delay = <0x26>;
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&vcc3v3_pcie {
|
||||
gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
|
@ -0,0 +1,89 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
// Copyright (c) 2023 AmadeusGhost <amadeus@jmu.edu.cn>
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3568-hinlink-opc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "HINLINK OPC-H69K Board";
|
||||
compatible = "hinlink,opc-h69k", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
ethernet1 = &gmac1;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0_opp_table {
|
||||
/delete-node/ opp-1608000000;
|
||||
/delete-node/ opp-1800000000;
|
||||
/delete-node/ opp-1992000000;
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&gpu_opp_table {
|
||||
/delete-node/ opp-700000000;
|
||||
/delete-node/ opp-800000000;
|
||||
};
|
||||
#endif
|
||||
|
||||
&gmac0 {
|
||||
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
&gmac0_rgmii_clk
|
||||
&gmac0_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x3c>;
|
||||
rx_delay = <0x2f>;
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
&gmac1m1_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x4f>;
|
||||
rx_delay = <0x26>;
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&vcc3v3_pcie {
|
||||
gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
|
@ -0,0 +1,592 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ariaboard Photonicat";
|
||||
compatible = "ariaboard,photonicat", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
ethernet1 = &gmac1;
|
||||
mmc0 = &sdhci;
|
||||
mmc1 = &sdmmc0;
|
||||
mmc2 = &sdmmc1;
|
||||
};
|
||||
|
||||
chosen: chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
gmac0_xpcsclk: xpcs-gmac0-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "clk_gmac0_xpcs_mii";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
hdmi-con {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
modem-rfkill {
|
||||
compatible = "rfkill-gpio";
|
||||
name = "modem-rfkill";
|
||||
type = "wwan";
|
||||
reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
|
||||
shutdown-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
clocks = <&pmucru CLK_RTC_32K>;
|
||||
clock-names = "ext_clock";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_enable_h &clk32k_out1>;
|
||||
reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
vcc_1v8: vcc-1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
vcc_3v3: vcc-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
vcc_sysin: vcc-sysin {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_sysin";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
vcc_syson: vcc-syson {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_syson";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc_sysin>;
|
||||
};
|
||||
|
||||
vdda_0v9: vdda-0v9 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdda_0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
vcca_1v8: vcca-1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcca_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
/* pi6c pcie clock generator */
|
||||
vcc3v3_pi6c: vcc3v3-pi6c {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_enable_h>;
|
||||
regulator-name = "vcc3v3_pi6c";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc_syson>;
|
||||
};
|
||||
|
||||
/* actually fed by vcc_syson, dependent
|
||||
* on pi6c clock generator
|
||||
*/
|
||||
vcc3v3_pcie: vcc3v3-pcie {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc3v3_pi6c>;
|
||||
};
|
||||
|
||||
vcc3v3_ngff: vcc3v3-ngff {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ngffpcie_enable_h>;
|
||||
regulator-name = "vcc3v3_ngff";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
vcc3v3_sd: vcc3v3_sd {
|
||||
compatible = "regulator-fixed";
|
||||
gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc_sd_h>;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc3v3_sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc_3v3>;
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc_syson>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg: vcc5v0-usb-otg {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_otg_en>;
|
||||
regulator-name = "vcc5v0_usb_otg";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc_sysin>;
|
||||
};
|
||||
|
||||
vdd_gpu: vdd-gpu {
|
||||
compatible = "pwm-regulator";
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-settling-time-up-us = <250>;
|
||||
|
||||
pwms = <&pwm2 0 5000 1>;
|
||||
pwm-supply = <&vcc_syson>;
|
||||
};
|
||||
|
||||
vdd_logic: vdd-logic {
|
||||
compatible = "pwm-regulator";
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-settling-time-up-us = <250>;
|
||||
|
||||
pwms = <&pwm1 0 5000 1>;
|
||||
pwm-supply = <&vcc_syson>;
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>;
|
||||
assigned-clock-parents = <&gmac0_xpcsclk>;
|
||||
power-domains = <&power RK3568_PD_PIPE>;
|
||||
phys = <&combphy2 PHY_TYPE_SGMII>;
|
||||
phy-handle = <&sgmii_phy>;
|
||||
phy-mode = "sgmii";
|
||||
phy-supply = <&vcc_3v3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim>;
|
||||
rockchip,xpcs = <&xpcs>;
|
||||
snps,reset-gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0xff>;
|
||||
rx_delay = <0xff>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-handle = <&rgmii_phy>;
|
||||
phy-mode = "rgmii";
|
||||
phy-supply = <&vcc_3v3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
&gmac1m1_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x30>;
|
||||
rx_delay = <0x10>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
avdd-0v9-supply = <&vdda_0v9>;
|
||||
avdd-1v8-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_in {
|
||||
hdmi_in_vp0: endpoint {
|
||||
remote-endpoint = <&vp0_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_out {
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1390000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc_syson>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2m1_xfer>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&i2s0_8ch {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&mdio0 {
|
||||
sgmii_phy: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
phy-supply = <&vcc3v3_pi6c>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
bt {
|
||||
bt_enable_h: bt-enable-h {
|
||||
rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie {
|
||||
pcie_enable_h: pcie-enable-h {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio-pwrseq {
|
||||
wifi_enable_h: wifi-enable-h {
|
||||
rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
ngffpcie_enable_h: ngffpcie-enable-h {
|
||||
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sd {
|
||||
vcc_sd_h: vcc-sd-h {
|
||||
rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc_3v3>;
|
||||
pmuio2-supply = <&vcc_3v3>;
|
||||
vccio1-supply = <&vcc_3v3>;
|
||||
vccio3-supply = <&vcc_3v3>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_3v3>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
|
||||
vmmc-supply = <&vcc_3v3>;
|
||||
vqmmc-supply = <&vcc_1v8>;
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
no-1-8-v;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
keep-power-in-suspend;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sys>;
|
||||
vqmmc-supply = <&vcc_1v8>;
|
||||
status = "okay";
|
||||
|
||||
sdio_wifi@1 {
|
||||
reg = <1>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "host-wake";
|
||||
};
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
|
||||
status = "okay";
|
||||
uart-has-rtscts;
|
||||
|
||||
bluetooth {
|
||||
compatible = "qcom,qca9377-bt";
|
||||
enable-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
clocks = <&pmucru CLK_RTC_32K>;
|
||||
clock-names = "lpo";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&bt_enable_h>;
|
||||
vddio-supply = <&vcc_1v8>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
extcon = <&usb2phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
phy-supply = <&vcc3v3_ngff>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
phy-supply = <&vcc5v0_usb_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
phy-supply = <&vcc5v0_usb_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi_in_vp0>;
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
&xin32k {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&clk32k_out1>;
|
||||
};
|
||||
|
||||
&xpcs {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3568-fastrhino.dtsi"
|
||||
|
||||
/ {
|
||||
model = "FastRhino R66S";
|
||||
compatible = "fastrhino,r66s", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
mmc0 = &sdmmc0;
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3568-fastrhino.dtsi"
|
||||
|
||||
/ {
|
||||
model = "FastRhino R68S";
|
||||
compatible = "fastrhino,r68s", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
ethernet1 = &gmac1;
|
||||
mmc0 = &sdhci;
|
||||
};
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
&gmac0_rgmii_clk
|
||||
&gmac0_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x3c>;
|
||||
rx_delay = <0x2f>;
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
&gmac1m1_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x4f>;
|
||||
rx_delay = <0x26>;
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,418 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "radxa,cm3i", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
mmc0 = &sdhci;
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led_user: led-0 {
|
||||
gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
function = LED_FUNCTION_HEARTBEAT;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_user_en>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie30_avdd0v9: pcie30-avdd0v9-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie30_avdd0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
pcie30_avdd1v8: pcie30-avdd1v8-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie30_avdd1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v_input>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v_input>;
|
||||
};
|
||||
|
||||
/* labeled +5v_input in schematic */
|
||||
vcc5v_input: vcc5v-input-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v_input";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&display_subsystem {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v_input>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-name = "vdda0v9_image";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-name = "vdda_0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-name = "vccio_acodec";
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-name = "vcca_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-name = "vcca1v8_image";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
led_user_en: led_user_en {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc3v3_pmu>;
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio2-supply = <&vcc_1v8>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
vmmc-supply = <&vcc_3v3>;
|
||||
vqmmc-supply = <&vcc_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
extcon = <&usb2phy0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,251 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3568-radxa-cm3i.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Radxa E25 Carrier Board";
|
||||
compatible = "radxa,e25", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
mmc1 = &sdmmc0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
adc-keys {
|
||||
compatible = "adc-keys";
|
||||
io-channels = <&saradc 0>;
|
||||
io-channel-names = "buttons";
|
||||
keyup-threshold-microvolt = <1750000>;
|
||||
|
||||
button-power {
|
||||
label = "Power";
|
||||
linux,code = <KEY_POWER>;
|
||||
press-threshold-microvolt = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm-leds {
|
||||
compatible = "pwm-leds-multicolor";
|
||||
|
||||
multi-led {
|
||||
color = <LED_COLOR_ID_RGB>;
|
||||
max-brightness = <255>;
|
||||
|
||||
led-red {
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
pwms = <&pwm1 0 1000000 0>;
|
||||
};
|
||||
|
||||
led-green {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
pwms = <&pwm2 0 1000000 0>;
|
||||
};
|
||||
|
||||
led-blue {
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
pwms = <&pwm12 0 1000000 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vbus_typec: vbus-typec-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vbus_typec_en>;
|
||||
regulator-name = "vbus_typec";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc3v3_minipcie: vcc3v3-minipcie-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&minipcie_enable_h>;
|
||||
regulator-name = "vcc3v3_minipcie";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc3v3_ngff: vcc3v3-ngff-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ngffpcie_enable_h>;
|
||||
regulator-name = "vcc3v3_ngff";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
/* actually fed by vcc5v0_sys, dependent
|
||||
* on pi6c clock generator
|
||||
*/
|
||||
vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie30x1_enable_h>;
|
||||
regulator-name = "vcc3v3_pcie30x1";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc3v3_pi6c_05>;
|
||||
};
|
||||
|
||||
vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_enable_h>;
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie2x1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie20_reset_h>;
|
||||
reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pi6c_05>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
data-lanes = <1 2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x1 {
|
||||
num-lanes = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie30x1m0_pins>;
|
||||
reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie30x1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
num-lanes = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie30x2_reset_h>;
|
||||
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pi6c_05>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pcie {
|
||||
pcie20_reset_h: pcie20-reset-h {
|
||||
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pcie30x1_enable_h: pcie30x1-enable-h {
|
||||
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pcie30x2_reset_h: pcie30x2-reset-h {
|
||||
rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pcie_enable_h: pcie-enable-h {
|
||||
rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
minipcie_enable_h: minipcie-enable-h {
|
||||
rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
ngffpcie_enable_h: ngffpcie-enable-h {
|
||||
rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vbus_typec_en: vbus_typec_en {
|
||||
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm12 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm12m1_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata1 {
|
||||
ahci-supply = <&vcc3v3_pi6c_05>;
|
||||
target-supply = <&vcc3v3_pcie30x1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
/* Also used in pcie30x1_clkreqnm0 */
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
phy-supply = <&vbus_typec>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_host {
|
||||
phy-supply = <&vcc3v3_minipcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
phy-supply = <&vcc3v3_ngff>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,796 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Firefly Station P2";
|
||||
compatible = "firefly,rk3568-roc-pc", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
ethernet1 = &gmac1;
|
||||
mmc0 = &sdmmc0;
|
||||
mmc1 = &sdhci;
|
||||
};
|
||||
|
||||
chosen: chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
hdmi-con {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_work_en>, <&led_user_en>;
|
||||
|
||||
led-work {
|
||||
label = "blue:work";
|
||||
gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
led-user {
|
||||
label = "yellow:user";
|
||||
gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
rk809-sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,name = "Analog RK809";
|
||||
simple-audio-card,mclk-fs = <256>;
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&i2s1_8ch>;
|
||||
};
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&rk809>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
clocks = <&rk809 1>;
|
||||
clock-names = "ext_clock";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_enable_h>;
|
||||
reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
|
||||
post-power-on-delay-ms = <100>;
|
||||
};
|
||||
|
||||
dc_12v: dc-12v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dc_12v";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_usb: vcc5v0-usb {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_usb";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
pcie30_avdd0v9: pcie30-avdd0v9 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie30_avdd0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
pcie30_avdd1v8: pcie30-avdd1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie30_avdd1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
pcie_pi6c_oe: pcie-pi6c-oe {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie_pi6c_oe_en";
|
||||
regulator-always-on;
|
||||
gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_pi6c_oe_en>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie: vcc3v3_pi6c: vcc3v3-pcie {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_enable_h>;
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc5v0_host: vcc5v0-host {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_host";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_host_en>;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
vcc5v0_otg: vcc5v0-otg {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_otg";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_otg_en>;
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
vcc_hub_reset: vcc-hub-reset {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_hub_reset";
|
||||
regulator-always-on;
|
||||
enable-active-high;
|
||||
gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc_hub_reset_en>;
|
||||
};
|
||||
|
||||
vcc3v3_lcd0_n: vcc3v3-lcd0-n {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_lcd0_n";
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_lcd1_n: vcc3v3-lcd1-n {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_lcd1_n";
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
phy-mode = "rgmii";
|
||||
clock_in_out = "output";
|
||||
|
||||
snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
|
||||
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
&gmac0_rgmii_clk
|
||||
&gmac0_rgmii_bus
|
||||
&gmac0_clkinout>;
|
||||
|
||||
tx_delay = <0x3c>;
|
||||
rx_delay = <0x2f>;
|
||||
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
phy-mode = "rgmii";
|
||||
clock_in_out = "output";
|
||||
|
||||
snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
&gmac1m1_rgmii_bus
|
||||
&gmac1m1_clkinout>;
|
||||
|
||||
tx_delay = <0x4f>;
|
||||
rx_delay = <0x26>;
|
||||
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
avdd-0v9-supply = <&vdda0v9_image>;
|
||||
avdd-1v8-supply = <&vcca1v8_image>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_in {
|
||||
hdmi_in_vp0: endpoint {
|
||||
remote-endpoint = <&vp0_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_out {
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1390000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
|
||||
#clock-cells = <1>;
|
||||
clock-names = "mclk";
|
||||
clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
rockchip,system-power-controller;
|
||||
#sound-dai-cells = <0>;
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
wakeup-source;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-name = "vdda0v9_image";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-name = "vdda_0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-name = "vccio_acodec";
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-name = "vcca_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-name = "vcca1v8_image";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&i2s0_8ch {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2s1_8ch {
|
||||
rockchip,trcm-sync-tx-only;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy0: phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
led_work_en: led_work_en {
|
||||
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
led_user_en: led_user_en {
|
||||
rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio-pwrseq {
|
||||
wifi_enable_h: wifi-enable-h {
|
||||
rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_otg_en: vcc5v0-otg-en {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc_hub_reset_en: vcc-hub-reset-en {
|
||||
rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
fusb0_int {
|
||||
fusb0_int: fusb0-int {
|
||||
rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie {
|
||||
pcie_enable_h: pcie-enable-h {
|
||||
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pcie_reset_h: pcie-reset-h {
|
||||
rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pcie_pi6c_oe_en: pcie-pi6c-oe-en {
|
||||
rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
phy-supply = <&pcie_pi6c_oe>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_reset_h>;
|
||||
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc3v3_pmu>;
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio2-supply = <&vcc_1v8>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc2 {
|
||||
max-frequency = <150000000>;
|
||||
supports-sdio;
|
||||
bus-width = <4>;
|
||||
disable-wp;
|
||||
cap-sd-highspeed;
|
||||
cap-sdio-irq;
|
||||
keep-power-in-suspend;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
|
||||
sd-uhs-sdr104;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
extcon = <&usb2phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi_in_vp0>;
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
|
@ -0,0 +1,770 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Radxa ROCK3 Model A";
|
||||
compatible = "radxa,rock3a", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac1;
|
||||
mmc0 = &sdmmc0;
|
||||
mmc1 = &sdhci;
|
||||
};
|
||||
|
||||
chosen: chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
hdmi-con {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led_user: led-0 {
|
||||
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
function = LED_FUNCTION_HEARTBEAT;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_user_en>;
|
||||
};
|
||||
};
|
||||
|
||||
rk809-sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,name = "Analog RK809";
|
||||
simple-audio-card,mclk-fs = <256>;
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&i2s1_8ch>;
|
||||
};
|
||||
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&rk809>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc12v_dcin: vcc12v-dcin {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc12v_dcin";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_usb: vcc5v0-usb {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_usb";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_host: vcc5v0-usb-host {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_host_en>;
|
||||
regulator-name = "vcc5v0_usb_host";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_hub: vcc5v0-usb-hub {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_hub_en>;
|
||||
regulator-name = "vcc5v0_usb_hub";
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg: vcc5v0-usb-otg {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_otg_en>;
|
||||
regulator-name = "vcc5v0_usb_otg";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
pcie30_avdd0v9: pcie30-avdd0v9 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie30_avdd0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
pcie30_avdd1v8: pcie30-avdd1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie30_avdd1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
/* pi6c pcie clock generator */
|
||||
vcc3v3_pi6c_03: vcc3v3-pi6c-03 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_pi6c_03";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie: vcc3v3-pcie {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_enable_h>;
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc_cam: vcc-cam {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc_cam_en>;
|
||||
regulator-name = "vcc_cam";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_mipi: vcc-mipi {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc_mipi_en>;
|
||||
regulator-name = "vcc_mipi";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
&gmac1m1_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x42>;
|
||||
rx_delay = <0x28>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
avdd-0v9-supply = <&vdda0v9_image>;
|
||||
avdd-1v8-supply = <&vcca1v8_image>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_in {
|
||||
hdmi_in_vp0: endpoint {
|
||||
remote-endpoint = <&vp0_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_out {
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
|
||||
#clock-cells = <1>;
|
||||
clock-names = "mclk";
|
||||
clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
|
||||
rockchip,system-power-controller;
|
||||
#sound-dai-cells = <0>;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-name = "vdda0v9_image";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-name = "vdda_0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-name = "vccio_acodec";
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-name = "vcca_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-name = "vcca1v8_image";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
codec {
|
||||
mic-in-differential;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
status = "okay";
|
||||
|
||||
hym8563: rtc@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "rtcic_32kout";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hym8563_int>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&i2s0_8ch {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2s1_8ch {
|
||||
rockchip,trcm-sync-tx-only;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie2x1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_reset_h>;
|
||||
reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
phy-supply = <&vcc3v3_pi6c_03>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie30x2m1_pins>;
|
||||
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
cam {
|
||||
vcc_cam_en: vcc_cam_en {
|
||||
rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
display {
|
||||
vcc_mipi_en: vcc_mipi_en {
|
||||
rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
hym8563 {
|
||||
hym8563_int: hym8563-int {
|
||||
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
led_user_en: led_user_en {
|
||||
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie {
|
||||
pcie_enable_h: pcie-enable-h {
|
||||
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pcie_reset_h: pcie-reset-h {
|
||||
rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb_host_en: vcc5v0_usb_host_en {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_hub_en: vcc5v0_usb_hub_en {
|
||||
rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc3v3_pmu>;
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio2-supply = <&vcc_1v8>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
vmmc-supply = <&vcc_3v3>;
|
||||
vqmmc-supply = <&vcc_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
extcon = <&usb2phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
phy-supply = <&vcc5v0_usb_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi_in_vp0>;
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
|
@ -0,0 +1,310 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* rockchip-rng.c Random Number Generator driver for the Rockchip
|
||||
*
|
||||
* Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd.
|
||||
* Author: Lin Jinhan <troy.lin@rock-chips.com>
|
||||
*
|
||||
*/
|
||||
#include <linux/clk.h>
|
||||
#include <linux/hw_random.h>
|
||||
#include <linux/iopoll.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
|
||||
#define _SBF(s, v) ((v) << (s))
|
||||
#define HIWORD_UPDATE(val, mask, shift) \
|
||||
((val) << (shift) | (mask) << ((shift) + 16))
|
||||
|
||||
#define ROCKCHIP_AUTOSUSPEND_DELAY 100
|
||||
#define ROCKCHIP_POLL_PERIOD_US 100
|
||||
#define ROCKCHIP_POLL_TIMEOUT_US 10000
|
||||
#define RK_MAX_RNG_BYTE (32)
|
||||
|
||||
/* start of CRYPTO V1 register define */
|
||||
#define CRYPTO_V1_CTRL 0x0008
|
||||
#define CRYPTO_V1_RNG_START BIT(8)
|
||||
#define CRYPTO_V1_RNG_FLUSH BIT(9)
|
||||
|
||||
#define CRYPTO_V1_TRNG_CTRL 0x0200
|
||||
#define CRYPTO_V1_OSC_ENABLE BIT(16)
|
||||
#define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x) (x)
|
||||
|
||||
#define CRYPTO_V1_TRNG_DOUT_0 0x0204
|
||||
/* end of CRYPTO V1 register define */
|
||||
|
||||
/* start of CRYPTO V2 register define */
|
||||
#define CRYPTO_V2_RNG_CTL 0x0400
|
||||
#define CRYPTO_V2_RNG_64_BIT_LEN _SBF(4, 0x00)
|
||||
#define CRYPTO_V2_RNG_128_BIT_LEN _SBF(4, 0x01)
|
||||
#define CRYPTO_V2_RNG_192_BIT_LEN _SBF(4, 0x02)
|
||||
#define CRYPTO_V2_RNG_256_BIT_LEN _SBF(4, 0x03)
|
||||
#define CRYPTO_V2_RNG_FATESY_SOC_RING _SBF(2, 0x00)
|
||||
#define CRYPTO_V2_RNG_SLOWER_SOC_RING_0 _SBF(2, 0x01)
|
||||
#define CRYPTO_V2_RNG_SLOWER_SOC_RING_1 _SBF(2, 0x02)
|
||||
#define CRYPTO_V2_RNG_SLOWEST_SOC_RING _SBF(2, 0x03)
|
||||
#define CRYPTO_V2_RNG_ENABLE BIT(1)
|
||||
#define CRYPTO_V2_RNG_START BIT(0)
|
||||
#define CRYPTO_V2_RNG_SAMPLE_CNT 0x0404
|
||||
#define CRYPTO_V2_RNG_DOUT_0 0x0410
|
||||
/* end of CRYPTO V2 register define */
|
||||
|
||||
struct rk_rng_soc_data {
|
||||
int (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait);
|
||||
};
|
||||
|
||||
struct rk_rng {
|
||||
struct device *dev;
|
||||
struct hwrng rng;
|
||||
void __iomem *mem;
|
||||
struct rk_rng_soc_data *soc_data;
|
||||
int clk_num;
|
||||
struct clk_bulk_data *clk_bulks;
|
||||
};
|
||||
|
||||
static void rk_rng_writel(struct rk_rng *rng, u32 val, u32 offset)
|
||||
{
|
||||
__raw_writel(val, rng->mem + offset);
|
||||
}
|
||||
|
||||
static u32 rk_rng_readl(struct rk_rng *rng, u32 offset)
|
||||
{
|
||||
return __raw_readl(rng->mem + offset);
|
||||
}
|
||||
|
||||
static int rk_rng_init(struct hwrng *rng)
|
||||
{
|
||||
int ret;
|
||||
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
|
||||
|
||||
dev_dbg(rk_rng->dev, "clk_bulk_prepare_enable.\n");
|
||||
|
||||
ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);
|
||||
if (ret < 0) {
|
||||
dev_err(rk_rng->dev, "failed to enable clks %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rk_rng_cleanup(struct hwrng *rng)
|
||||
{
|
||||
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
|
||||
|
||||
dev_dbg(rk_rng->dev, "clk_bulk_disable_unprepare.\n");
|
||||
clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
|
||||
}
|
||||
|
||||
static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf,
|
||||
size_t size)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
for (i = 0; i < size; i += 4)
|
||||
*(u32 *)(buf + i) = be32_to_cpu(rk_rng_readl(rng, offset + i));
|
||||
}
|
||||
|
||||
static int rk_rng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
|
||||
{
|
||||
int ret = 0;
|
||||
u32 reg_ctrl = 0;
|
||||
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
|
||||
|
||||
ret = pm_runtime_get_sync(rk_rng->dev);
|
||||
if (ret < 0) {
|
||||
pm_runtime_put_noidle(rk_rng->dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* enable osc_ring to get entropy, sample period is set as 100 */
|
||||
reg_ctrl = CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100);
|
||||
rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_TRNG_CTRL);
|
||||
|
||||
reg_ctrl = HIWORD_UPDATE(CRYPTO_V1_RNG_START, CRYPTO_V1_RNG_START, 0);
|
||||
|
||||
rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_CTRL);
|
||||
|
||||
ret = readl_poll_timeout(rk_rng->mem + CRYPTO_V1_CTRL, reg_ctrl,
|
||||
!(reg_ctrl & CRYPTO_V1_RNG_START),
|
||||
ROCKCHIP_POLL_PERIOD_US,
|
||||
ROCKCHIP_POLL_TIMEOUT_US);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
|
||||
ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
|
||||
|
||||
rk_rng_read_regs(rk_rng, CRYPTO_V1_TRNG_DOUT_0, buf, ret);
|
||||
|
||||
out:
|
||||
/* close TRNG */
|
||||
rk_rng_writel(rk_rng, HIWORD_UPDATE(0, CRYPTO_V1_RNG_START, 0),
|
||||
CRYPTO_V1_CTRL);
|
||||
|
||||
pm_runtime_mark_last_busy(rk_rng->dev);
|
||||
pm_runtime_put_sync_autosuspend(rk_rng->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rk_rng_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
|
||||
{
|
||||
int ret = 0;
|
||||
u32 reg_ctrl = 0;
|
||||
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
|
||||
|
||||
ret = pm_runtime_get_sync(rk_rng->dev);
|
||||
if (ret < 0) {
|
||||
pm_runtime_put_noidle(rk_rng->dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* enable osc_ring to get entropy, sample period is set as 100 */
|
||||
rk_rng_writel(rk_rng, 100, CRYPTO_V2_RNG_SAMPLE_CNT);
|
||||
|
||||
reg_ctrl |= CRYPTO_V2_RNG_256_BIT_LEN;
|
||||
reg_ctrl |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0;
|
||||
reg_ctrl |= CRYPTO_V2_RNG_ENABLE;
|
||||
reg_ctrl |= CRYPTO_V2_RNG_START;
|
||||
|
||||
rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0),
|
||||
CRYPTO_V2_RNG_CTL);
|
||||
|
||||
ret = readl_poll_timeout(rk_rng->mem + CRYPTO_V2_RNG_CTL, reg_ctrl,
|
||||
!(reg_ctrl & CRYPTO_V2_RNG_START),
|
||||
ROCKCHIP_POLL_PERIOD_US,
|
||||
ROCKCHIP_POLL_TIMEOUT_US);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
|
||||
ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
|
||||
|
||||
rk_rng_read_regs(rk_rng, CRYPTO_V2_RNG_DOUT_0, buf, ret);
|
||||
|
||||
out:
|
||||
/* close TRNG */
|
||||
rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), CRYPTO_V2_RNG_CTL);
|
||||
|
||||
pm_runtime_mark_last_busy(rk_rng->dev);
|
||||
pm_runtime_put_sync_autosuspend(rk_rng->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct rk_rng_soc_data rk_rng_v1_soc_data = {
|
||||
.rk_rng_read = rk_rng_v1_read,
|
||||
};
|
||||
|
||||
static const struct rk_rng_soc_data rk_rng_v2_soc_data = {
|
||||
.rk_rng_read = rk_rng_v2_read,
|
||||
};
|
||||
|
||||
static const struct of_device_id rk_rng_dt_match[] = {
|
||||
{
|
||||
.compatible = "rockchip,cryptov1-rng",
|
||||
.data = (void *)&rk_rng_v1_soc_data,
|
||||
},
|
||||
{
|
||||
.compatible = "rockchip,cryptov2-rng",
|
||||
.data = (void *)&rk_rng_v2_soc_data,
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, rk_rng_dt_match);
|
||||
|
||||
static int rk_rng_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
struct rk_rng *rk_rng;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
const struct of_device_id *match;
|
||||
|
||||
dev_dbg(&pdev->dev, "probing...\n");
|
||||
rk_rng = devm_kzalloc(&pdev->dev, sizeof(struct rk_rng), GFP_KERNEL);
|
||||
if (!rk_rng)
|
||||
return -ENOMEM;
|
||||
|
||||
match = of_match_node(rk_rng_dt_match, np);
|
||||
rk_rng->soc_data = (struct rk_rng_soc_data *)match->data;
|
||||
|
||||
rk_rng->dev = &pdev->dev;
|
||||
rk_rng->rng.name = "rockchip";
|
||||
#ifndef CONFIG_PM
|
||||
rk_rng->rng.init = rk_rng_init;
|
||||
rk_rng->rng.cleanup = rk_rng_cleanup,
|
||||
#endif
|
||||
rk_rng->rng.read = rk_rng->soc_data->rk_rng_read;
|
||||
rk_rng->rng.quality = 999;
|
||||
|
||||
rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
|
||||
if (IS_ERR(rk_rng->mem))
|
||||
return PTR_ERR(rk_rng->mem);
|
||||
|
||||
rk_rng->clk_num = devm_clk_bulk_get_all(&pdev->dev, &rk_rng->clk_bulks);
|
||||
if (rk_rng->clk_num < 0) {
|
||||
dev_err(&pdev->dev, "failed to get clks property\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, rk_rng);
|
||||
|
||||
pm_runtime_set_autosuspend_delay(&pdev->dev,
|
||||
ROCKCHIP_AUTOSUSPEND_DELAY);
|
||||
pm_runtime_use_autosuspend(&pdev->dev);
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
|
||||
ret = devm_hwrng_register(&pdev->dev, &rk_rng->rng);
|
||||
if (ret) {
|
||||
pm_runtime_dont_use_autosuspend(&pdev->dev);
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int rk_rng_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct rk_rng *rk_rng = dev_get_drvdata(dev);
|
||||
|
||||
rk_rng_cleanup(&rk_rng->rng);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk_rng_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct rk_rng *rk_rng = dev_get_drvdata(dev);
|
||||
|
||||
return rk_rng_init(&rk_rng->rng);
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops rk_rng_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,
|
||||
rk_rng_runtime_resume, NULL)
|
||||
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
||||
pm_runtime_force_resume)
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
static struct platform_driver rk_rng_driver = {
|
||||
.driver = {
|
||||
.name = "rockchip-rng",
|
||||
#ifdef CONFIG_PM
|
||||
.pm = &rk_rng_pm_ops,
|
||||
#endif
|
||||
.of_match_table = rk_rng_dt_match,
|
||||
},
|
||||
.probe = rk_rng_probe,
|
||||
};
|
||||
|
||||
module_platform_driver(rk_rng_driver);
|
||||
|
||||
MODULE_DESCRIPTION("ROCKCHIP H/W Random Number Generator driver");
|
||||
MODULE_AUTHOR("Lin Jinhan <troy.lin@rock-chips.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
852
6.1/target/linux/rockchip/files/drivers/devfreq/rk3328_dmc.c
Normal file
852
6.1/target/linux/rockchip/files/drivers/devfreq/rk3328_dmc.c
Normal file
|
|
@ -0,0 +1,852 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
|
||||
* Author: Lin Huang <hl@rock-chips.com>
|
||||
*/
|
||||
|
||||
#include <linux/arm-smccc.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/devfreq.h>
|
||||
#include <linux/devfreq-event.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/iversion.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_opp.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/regulator/consumer.h>
|
||||
#include <linux/rwsem.h>
|
||||
#include <linux/suspend.h>
|
||||
#include <linux/version.h>
|
||||
|
||||
#include <soc/rockchip/rockchip_sip.h>
|
||||
|
||||
#define DTS_PAR_OFFSET (4096)
|
||||
|
||||
struct share_params {
|
||||
u32 hz;
|
||||
u32 lcdc_type;
|
||||
u32 vop;
|
||||
u32 vop_dclk_mode;
|
||||
u32 sr_idle_en;
|
||||
u32 addr_mcu_el3;
|
||||
/*
|
||||
* 1: need to wait flag1
|
||||
* 0: never wait flag1
|
||||
*/
|
||||
u32 wait_flag1;
|
||||
/*
|
||||
* 1: need to wait flag1
|
||||
* 0: never wait flag1
|
||||
*/
|
||||
u32 wait_flag0;
|
||||
u32 complt_hwirq;
|
||||
/* if need, add parameter after */
|
||||
};
|
||||
|
||||
static struct share_params *ddr_psci_param;
|
||||
|
||||
/* hope this define can adapt all future platform */
|
||||
static const char * const rk3328_dts_timing[] = {
|
||||
"ddr3_speed_bin",
|
||||
"ddr4_speed_bin",
|
||||
"pd_idle",
|
||||
"sr_idle",
|
||||
"sr_mc_gate_idle",
|
||||
"srpd_lite_idle",
|
||||
"standby_idle",
|
||||
|
||||
"auto_pd_dis_freq",
|
||||
"auto_sr_dis_freq",
|
||||
"ddr3_dll_dis_freq",
|
||||
"ddr4_dll_dis_freq",
|
||||
"phy_dll_dis_freq",
|
||||
|
||||
"ddr3_odt_dis_freq",
|
||||
"phy_ddr3_odt_dis_freq",
|
||||
"ddr3_drv",
|
||||
"ddr3_odt",
|
||||
"phy_ddr3_ca_drv",
|
||||
"phy_ddr3_ck_drv",
|
||||
"phy_ddr3_dq_drv",
|
||||
"phy_ddr3_odt",
|
||||
|
||||
"lpddr3_odt_dis_freq",
|
||||
"phy_lpddr3_odt_dis_freq",
|
||||
"lpddr3_drv",
|
||||
"lpddr3_odt",
|
||||
"phy_lpddr3_ca_drv",
|
||||
"phy_lpddr3_ck_drv",
|
||||
"phy_lpddr3_dq_drv",
|
||||
"phy_lpddr3_odt",
|
||||
|
||||
"lpddr4_odt_dis_freq",
|
||||
"phy_lpddr4_odt_dis_freq",
|
||||
"lpddr4_drv",
|
||||
"lpddr4_dq_odt",
|
||||
"lpddr4_ca_odt",
|
||||
"phy_lpddr4_ca_drv",
|
||||
"phy_lpddr4_ck_cs_drv",
|
||||
"phy_lpddr4_dq_drv",
|
||||
"phy_lpddr4_odt",
|
||||
|
||||
"ddr4_odt_dis_freq",
|
||||
"phy_ddr4_odt_dis_freq",
|
||||
"ddr4_drv",
|
||||
"ddr4_odt",
|
||||
"phy_ddr4_ca_drv",
|
||||
"phy_ddr4_ck_drv",
|
||||
"phy_ddr4_dq_drv",
|
||||
"phy_ddr4_odt",
|
||||
};
|
||||
|
||||
static const char * const rk3328_dts_ca_timing[] = {
|
||||
"ddr3a1_ddr4a9_de-skew",
|
||||
"ddr3a0_ddr4a10_de-skew",
|
||||
"ddr3a3_ddr4a6_de-skew",
|
||||
"ddr3a2_ddr4a4_de-skew",
|
||||
"ddr3a5_ddr4a8_de-skew",
|
||||
"ddr3a4_ddr4a5_de-skew",
|
||||
"ddr3a7_ddr4a11_de-skew",
|
||||
"ddr3a6_ddr4a7_de-skew",
|
||||
"ddr3a9_ddr4a0_de-skew",
|
||||
"ddr3a8_ddr4a13_de-skew",
|
||||
"ddr3a11_ddr4a3_de-skew",
|
||||
"ddr3a10_ddr4cs0_de-skew",
|
||||
"ddr3a13_ddr4a2_de-skew",
|
||||
"ddr3a12_ddr4ba1_de-skew",
|
||||
"ddr3a15_ddr4odt0_de-skew",
|
||||
"ddr3a14_ddr4a1_de-skew",
|
||||
"ddr3ba1_ddr4a15_de-skew",
|
||||
"ddr3ba0_ddr4bg0_de-skew",
|
||||
"ddr3ras_ddr4cke_de-skew",
|
||||
"ddr3ba2_ddr4ba0_de-skew",
|
||||
"ddr3we_ddr4bg1_de-skew",
|
||||
"ddr3cas_ddr4a12_de-skew",
|
||||
"ddr3ckn_ddr4ckn_de-skew",
|
||||
"ddr3ckp_ddr4ckp_de-skew",
|
||||
"ddr3cke_ddr4a16_de-skew",
|
||||
"ddr3odt0_ddr4a14_de-skew",
|
||||
"ddr3cs0_ddr4act_de-skew",
|
||||
"ddr3reset_ddr4reset_de-skew",
|
||||
"ddr3cs1_ddr4cs1_de-skew",
|
||||
"ddr3odt1_ddr4odt1_de-skew",
|
||||
};
|
||||
|
||||
static const char * const rk3328_dts_cs0_timing[] = {
|
||||
"cs0_dm0_rx_de-skew",
|
||||
"cs0_dm0_tx_de-skew",
|
||||
"cs0_dq0_rx_de-skew",
|
||||
"cs0_dq0_tx_de-skew",
|
||||
"cs0_dq1_rx_de-skew",
|
||||
"cs0_dq1_tx_de-skew",
|
||||
"cs0_dq2_rx_de-skew",
|
||||
"cs0_dq2_tx_de-skew",
|
||||
"cs0_dq3_rx_de-skew",
|
||||
"cs0_dq3_tx_de-skew",
|
||||
"cs0_dq4_rx_de-skew",
|
||||
"cs0_dq4_tx_de-skew",
|
||||
"cs0_dq5_rx_de-skew",
|
||||
"cs0_dq5_tx_de-skew",
|
||||
"cs0_dq6_rx_de-skew",
|
||||
"cs0_dq6_tx_de-skew",
|
||||
"cs0_dq7_rx_de-skew",
|
||||
"cs0_dq7_tx_de-skew",
|
||||
"cs0_dqs0_rx_de-skew",
|
||||
"cs0_dqs0p_tx_de-skew",
|
||||
"cs0_dqs0n_tx_de-skew",
|
||||
|
||||
"cs0_dm1_rx_de-skew",
|
||||
"cs0_dm1_tx_de-skew",
|
||||
"cs0_dq8_rx_de-skew",
|
||||
"cs0_dq8_tx_de-skew",
|
||||
"cs0_dq9_rx_de-skew",
|
||||
"cs0_dq9_tx_de-skew",
|
||||
"cs0_dq10_rx_de-skew",
|
||||
"cs0_dq10_tx_de-skew",
|
||||
"cs0_dq11_rx_de-skew",
|
||||
"cs0_dq11_tx_de-skew",
|
||||
"cs0_dq12_rx_de-skew",
|
||||
"cs0_dq12_tx_de-skew",
|
||||
"cs0_dq13_rx_de-skew",
|
||||
"cs0_dq13_tx_de-skew",
|
||||
"cs0_dq14_rx_de-skew",
|
||||
"cs0_dq14_tx_de-skew",
|
||||
"cs0_dq15_rx_de-skew",
|
||||
"cs0_dq15_tx_de-skew",
|
||||
"cs0_dqs1_rx_de-skew",
|
||||
"cs0_dqs1p_tx_de-skew",
|
||||
"cs0_dqs1n_tx_de-skew",
|
||||
|
||||
"cs0_dm2_rx_de-skew",
|
||||
"cs0_dm2_tx_de-skew",
|
||||
"cs0_dq16_rx_de-skew",
|
||||
"cs0_dq16_tx_de-skew",
|
||||
"cs0_dq17_rx_de-skew",
|
||||
"cs0_dq17_tx_de-skew",
|
||||
"cs0_dq18_rx_de-skew",
|
||||
"cs0_dq18_tx_de-skew",
|
||||
"cs0_dq19_rx_de-skew",
|
||||
"cs0_dq19_tx_de-skew",
|
||||
"cs0_dq20_rx_de-skew",
|
||||
"cs0_dq20_tx_de-skew",
|
||||
"cs0_dq21_rx_de-skew",
|
||||
"cs0_dq21_tx_de-skew",
|
||||
"cs0_dq22_rx_de-skew",
|
||||
"cs0_dq22_tx_de-skew",
|
||||
"cs0_dq23_rx_de-skew",
|
||||
"cs0_dq23_tx_de-skew",
|
||||
"cs0_dqs2_rx_de-skew",
|
||||
"cs0_dqs2p_tx_de-skew",
|
||||
"cs0_dqs2n_tx_de-skew",
|
||||
|
||||
"cs0_dm3_rx_de-skew",
|
||||
"cs0_dm3_tx_de-skew",
|
||||
"cs0_dq24_rx_de-skew",
|
||||
"cs0_dq24_tx_de-skew",
|
||||
"cs0_dq25_rx_de-skew",
|
||||
"cs0_dq25_tx_de-skew",
|
||||
"cs0_dq26_rx_de-skew",
|
||||
"cs0_dq26_tx_de-skew",
|
||||
"cs0_dq27_rx_de-skew",
|
||||
"cs0_dq27_tx_de-skew",
|
||||
"cs0_dq28_rx_de-skew",
|
||||
"cs0_dq28_tx_de-skew",
|
||||
"cs0_dq29_rx_de-skew",
|
||||
"cs0_dq29_tx_de-skew",
|
||||
"cs0_dq30_rx_de-skew",
|
||||
"cs0_dq30_tx_de-skew",
|
||||
"cs0_dq31_rx_de-skew",
|
||||
"cs0_dq31_tx_de-skew",
|
||||
"cs0_dqs3_rx_de-skew",
|
||||
"cs0_dqs3p_tx_de-skew",
|
||||
"cs0_dqs3n_tx_de-skew",
|
||||
};
|
||||
|
||||
static const char * const rk3328_dts_cs1_timing[] = {
|
||||
"cs1_dm0_rx_de-skew",
|
||||
"cs1_dm0_tx_de-skew",
|
||||
"cs1_dq0_rx_de-skew",
|
||||
"cs1_dq0_tx_de-skew",
|
||||
"cs1_dq1_rx_de-skew",
|
||||
"cs1_dq1_tx_de-skew",
|
||||
"cs1_dq2_rx_de-skew",
|
||||
"cs1_dq2_tx_de-skew",
|
||||
"cs1_dq3_rx_de-skew",
|
||||
"cs1_dq3_tx_de-skew",
|
||||
"cs1_dq4_rx_de-skew",
|
||||
"cs1_dq4_tx_de-skew",
|
||||
"cs1_dq5_rx_de-skew",
|
||||
"cs1_dq5_tx_de-skew",
|
||||
"cs1_dq6_rx_de-skew",
|
||||
"cs1_dq6_tx_de-skew",
|
||||
"cs1_dq7_rx_de-skew",
|
||||
"cs1_dq7_tx_de-skew",
|
||||
"cs1_dqs0_rx_de-skew",
|
||||
"cs1_dqs0p_tx_de-skew",
|
||||
"cs1_dqs0n_tx_de-skew",
|
||||
|
||||
"cs1_dm1_rx_de-skew",
|
||||
"cs1_dm1_tx_de-skew",
|
||||
"cs1_dq8_rx_de-skew",
|
||||
"cs1_dq8_tx_de-skew",
|
||||
"cs1_dq9_rx_de-skew",
|
||||
"cs1_dq9_tx_de-skew",
|
||||
"cs1_dq10_rx_de-skew",
|
||||
"cs1_dq10_tx_de-skew",
|
||||
"cs1_dq11_rx_de-skew",
|
||||
"cs1_dq11_tx_de-skew",
|
||||
"cs1_dq12_rx_de-skew",
|
||||
"cs1_dq12_tx_de-skew",
|
||||
"cs1_dq13_rx_de-skew",
|
||||
"cs1_dq13_tx_de-skew",
|
||||
"cs1_dq14_rx_de-skew",
|
||||
"cs1_dq14_tx_de-skew",
|
||||
"cs1_dq15_rx_de-skew",
|
||||
"cs1_dq15_tx_de-skew",
|
||||
"cs1_dqs1_rx_de-skew",
|
||||
"cs1_dqs1p_tx_de-skew",
|
||||
"cs1_dqs1n_tx_de-skew",
|
||||
|
||||
"cs1_dm2_rx_de-skew",
|
||||
"cs1_dm2_tx_de-skew",
|
||||
"cs1_dq16_rx_de-skew",
|
||||
"cs1_dq16_tx_de-skew",
|
||||
"cs1_dq17_rx_de-skew",
|
||||
"cs1_dq17_tx_de-skew",
|
||||
"cs1_dq18_rx_de-skew",
|
||||
"cs1_dq18_tx_de-skew",
|
||||
"cs1_dq19_rx_de-skew",
|
||||
"cs1_dq19_tx_de-skew",
|
||||
"cs1_dq20_rx_de-skew",
|
||||
"cs1_dq20_tx_de-skew",
|
||||
"cs1_dq21_rx_de-skew",
|
||||
"cs1_dq21_tx_de-skew",
|
||||
"cs1_dq22_rx_de-skew",
|
||||
"cs1_dq22_tx_de-skew",
|
||||
"cs1_dq23_rx_de-skew",
|
||||
"cs1_dq23_tx_de-skew",
|
||||
"cs1_dqs2_rx_de-skew",
|
||||
"cs1_dqs2p_tx_de-skew",
|
||||
"cs1_dqs2n_tx_de-skew",
|
||||
|
||||
"cs1_dm3_rx_de-skew",
|
||||
"cs1_dm3_tx_de-skew",
|
||||
"cs1_dq24_rx_de-skew",
|
||||
"cs1_dq24_tx_de-skew",
|
||||
"cs1_dq25_rx_de-skew",
|
||||
"cs1_dq25_tx_de-skew",
|
||||
"cs1_dq26_rx_de-skew",
|
||||
"cs1_dq26_tx_de-skew",
|
||||
"cs1_dq27_rx_de-skew",
|
||||
"cs1_dq27_tx_de-skew",
|
||||
"cs1_dq28_rx_de-skew",
|
||||
"cs1_dq28_tx_de-skew",
|
||||
"cs1_dq29_rx_de-skew",
|
||||
"cs1_dq29_tx_de-skew",
|
||||
"cs1_dq30_rx_de-skew",
|
||||
"cs1_dq30_tx_de-skew",
|
||||
"cs1_dq31_rx_de-skew",
|
||||
"cs1_dq31_tx_de-skew",
|
||||
"cs1_dqs3_rx_de-skew",
|
||||
"cs1_dqs3p_tx_de-skew",
|
||||
"cs1_dqs3n_tx_de-skew",
|
||||
};
|
||||
|
||||
struct rk3328_ddr_dts_config_timing {
|
||||
unsigned int ddr3_speed_bin;
|
||||
unsigned int ddr4_speed_bin;
|
||||
unsigned int pd_idle;
|
||||
unsigned int sr_idle;
|
||||
unsigned int sr_mc_gate_idle;
|
||||
unsigned int srpd_lite_idle;
|
||||
unsigned int standby_idle;
|
||||
|
||||
unsigned int auto_pd_dis_freq;
|
||||
unsigned int auto_sr_dis_freq;
|
||||
/* for ddr3 only */
|
||||
unsigned int ddr3_dll_dis_freq;
|
||||
/* for ddr4 only */
|
||||
unsigned int ddr4_dll_dis_freq;
|
||||
unsigned int phy_dll_dis_freq;
|
||||
|
||||
unsigned int ddr3_odt_dis_freq;
|
||||
unsigned int phy_ddr3_odt_dis_freq;
|
||||
unsigned int ddr3_drv;
|
||||
unsigned int ddr3_odt;
|
||||
unsigned int phy_ddr3_ca_drv;
|
||||
unsigned int phy_ddr3_ck_drv;
|
||||
unsigned int phy_ddr3_dq_drv;
|
||||
unsigned int phy_ddr3_odt;
|
||||
|
||||
unsigned int lpddr3_odt_dis_freq;
|
||||
unsigned int phy_lpddr3_odt_dis_freq;
|
||||
unsigned int lpddr3_drv;
|
||||
unsigned int lpddr3_odt;
|
||||
unsigned int phy_lpddr3_ca_drv;
|
||||
unsigned int phy_lpddr3_ck_drv;
|
||||
unsigned int phy_lpddr3_dq_drv;
|
||||
unsigned int phy_lpddr3_odt;
|
||||
|
||||
unsigned int lpddr4_odt_dis_freq;
|
||||
unsigned int phy_lpddr4_odt_dis_freq;
|
||||
unsigned int lpddr4_drv;
|
||||
unsigned int lpddr4_dq_odt;
|
||||
unsigned int lpddr4_ca_odt;
|
||||
unsigned int phy_lpddr4_ca_drv;
|
||||
unsigned int phy_lpddr4_ck_cs_drv;
|
||||
unsigned int phy_lpddr4_dq_drv;
|
||||
unsigned int phy_lpddr4_odt;
|
||||
|
||||
unsigned int ddr4_odt_dis_freq;
|
||||
unsigned int phy_ddr4_odt_dis_freq;
|
||||
unsigned int ddr4_drv;
|
||||
unsigned int ddr4_odt;
|
||||
unsigned int phy_ddr4_ca_drv;
|
||||
unsigned int phy_ddr4_ck_drv;
|
||||
unsigned int phy_ddr4_dq_drv;
|
||||
unsigned int phy_ddr4_odt;
|
||||
|
||||
unsigned int ca_skew[15];
|
||||
unsigned int cs0_skew[44];
|
||||
unsigned int cs1_skew[44];
|
||||
|
||||
unsigned int available;
|
||||
};
|
||||
|
||||
struct rk3328_ddr_de_skew_setting {
|
||||
unsigned int ca_de_skew[30];
|
||||
unsigned int cs0_de_skew[84];
|
||||
unsigned int cs1_de_skew[84];
|
||||
};
|
||||
|
||||
struct rk3328_dmcfreq {
|
||||
struct device *dev;
|
||||
struct devfreq *devfreq;
|
||||
struct devfreq_simple_ondemand_data ondemand_data;
|
||||
struct clk *dmc_clk;
|
||||
struct devfreq_event_dev *edev;
|
||||
struct mutex lock;
|
||||
struct regulator *vdd_center;
|
||||
unsigned long rate, target_rate;
|
||||
unsigned long volt, target_volt;
|
||||
|
||||
int (*set_auto_self_refresh)(u32 en);
|
||||
};
|
||||
|
||||
static void
|
||||
rk3328_de_skew_setting_2_register(struct rk3328_ddr_de_skew_setting *de_skew,
|
||||
struct rk3328_ddr_dts_config_timing *tim)
|
||||
{
|
||||
u32 n;
|
||||
u32 offset;
|
||||
u32 shift;
|
||||
|
||||
memset_io(tim->ca_skew, 0, sizeof(tim->ca_skew));
|
||||
memset_io(tim->cs0_skew, 0, sizeof(tim->cs0_skew));
|
||||
memset_io(tim->cs1_skew, 0, sizeof(tim->cs1_skew));
|
||||
|
||||
/* CA de-skew */
|
||||
for (n = 0; n < ARRAY_SIZE(de_skew->ca_de_skew); n++) {
|
||||
offset = n / 2;
|
||||
shift = n % 2;
|
||||
/* 0 => 4; 1 => 0 */
|
||||
shift = (shift == 0) ? 4 : 0;
|
||||
tim->ca_skew[offset] &= ~(0xf << shift);
|
||||
tim->ca_skew[offset] |= (de_skew->ca_de_skew[n] << shift);
|
||||
}
|
||||
|
||||
/* CS0 data de-skew */
|
||||
for (n = 0; n < ARRAY_SIZE(de_skew->cs0_de_skew); n++) {
|
||||
offset = ((n / 21) * 11) + ((n % 21) / 2);
|
||||
shift = ((n % 21) % 2);
|
||||
if ((n % 21) == 20)
|
||||
shift = 0;
|
||||
else
|
||||
/* 0 => 4; 1 => 0 */
|
||||
shift = (shift == 0) ? 4 : 0;
|
||||
tim->cs0_skew[offset] &= ~(0xf << shift);
|
||||
tim->cs0_skew[offset] |= (de_skew->cs0_de_skew[n] << shift);
|
||||
}
|
||||
|
||||
/* CS1 data de-skew */
|
||||
for (n = 0; n < ARRAY_SIZE(de_skew->cs1_de_skew); n++) {
|
||||
offset = ((n / 21) * 11) + ((n % 21) / 2);
|
||||
shift = ((n % 21) % 2);
|
||||
if ((n % 21) == 20)
|
||||
shift = 0;
|
||||
else
|
||||
/* 0 => 4; 1 => 0 */
|
||||
shift = (shift == 0) ? 4 : 0;
|
||||
tim->cs1_skew[offset] &= ~(0xf << shift);
|
||||
tim->cs1_skew[offset] |= (de_skew->cs1_de_skew[n] << shift);
|
||||
}
|
||||
}
|
||||
|
||||
static void of_get_rk3328_timings(struct device *dev,
|
||||
struct device_node *np, uint32_t *timing)
|
||||
{
|
||||
struct device_node *np_tim;
|
||||
u32 *p;
|
||||
struct rk3328_ddr_dts_config_timing *dts_timing;
|
||||
struct rk3328_ddr_de_skew_setting *de_skew;
|
||||
int ret = 0;
|
||||
u32 i;
|
||||
|
||||
dts_timing =
|
||||
(struct rk3328_ddr_dts_config_timing *)(timing +
|
||||
DTS_PAR_OFFSET / 4);
|
||||
|
||||
np_tim = of_parse_phandle(np, "ddr_timing", 0);
|
||||
if (!np_tim) {
|
||||
ret = -EINVAL;
|
||||
goto end;
|
||||
}
|
||||
de_skew = kmalloc(sizeof(*de_skew), GFP_KERNEL);
|
||||
if (!de_skew) {
|
||||
ret = -ENOMEM;
|
||||
goto end;
|
||||
}
|
||||
|
||||
p = (u32 *)dts_timing;
|
||||
for (i = 0; i < ARRAY_SIZE(rk3328_dts_timing); i++) {
|
||||
ret |= of_property_read_u32(np_tim, rk3328_dts_timing[i],
|
||||
p + i);
|
||||
}
|
||||
p = (u32 *)de_skew->ca_de_skew;
|
||||
for (i = 0; i < ARRAY_SIZE(rk3328_dts_ca_timing); i++) {
|
||||
ret |= of_property_read_u32(np_tim, rk3328_dts_ca_timing[i],
|
||||
p + i);
|
||||
}
|
||||
p = (u32 *)de_skew->cs0_de_skew;
|
||||
for (i = 0; i < ARRAY_SIZE(rk3328_dts_cs0_timing); i++) {
|
||||
ret |= of_property_read_u32(np_tim, rk3328_dts_cs0_timing[i],
|
||||
p + i);
|
||||
}
|
||||
p = (u32 *)de_skew->cs1_de_skew;
|
||||
for (i = 0; i < ARRAY_SIZE(rk3328_dts_cs1_timing); i++) {
|
||||
ret |= of_property_read_u32(np_tim, rk3328_dts_cs1_timing[i],
|
||||
p + i);
|
||||
}
|
||||
if (!ret)
|
||||
rk3328_de_skew_setting_2_register(de_skew, dts_timing);
|
||||
|
||||
kfree(de_skew);
|
||||
end:
|
||||
if (!ret) {
|
||||
dts_timing->available = 1;
|
||||
} else {
|
||||
dts_timing->available = 0;
|
||||
dev_err(dev, "of_get_ddr_timings: fail\n");
|
||||
}
|
||||
|
||||
of_node_put(np_tim);
|
||||
}
|
||||
|
||||
static int rockchip_ddr_set_auto_self_refresh(uint32_t en)
|
||||
{
|
||||
struct arm_smccc_res res;
|
||||
|
||||
ddr_psci_param->sr_idle_en = en;
|
||||
|
||||
arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
|
||||
SHARE_PAGE_TYPE_DDR, 0, ROCKCHIP_SIP_CONFIG_DRAM_SET_AT_SR,
|
||||
0, 0, 0, 0, &res);
|
||||
|
||||
return res.a0;
|
||||
}
|
||||
|
||||
static int rk3328_dmc_init(struct platform_device *pdev,
|
||||
struct rk3328_dmcfreq *dmcfreq)
|
||||
{
|
||||
struct arm_smccc_res res;
|
||||
u32 size, page_num;
|
||||
|
||||
arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
|
||||
0, 0, ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION,
|
||||
0, 0, 0, 0, &res);
|
||||
if (res.a0 || (res.a1 < 0x101)) {
|
||||
dev_err(&pdev->dev,
|
||||
"trusted firmware need to update or is invalid\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
dev_notice(&pdev->dev, "current ATF version 0x%lx\n", res.a1);
|
||||
|
||||
/*
|
||||
* first 4KB is used for interface parameters
|
||||
* after 4KB * N is dts parameters
|
||||
*/
|
||||
size = sizeof(struct rk3328_ddr_dts_config_timing);
|
||||
page_num = DIV_ROUND_UP(size, 4096) + 1;
|
||||
|
||||
arm_smccc_smc(ROCKCHIP_SIP_SHARE_MEM,
|
||||
page_num, SHARE_PAGE_TYPE_DDR, 0,
|
||||
0, 0, 0, 0, &res);
|
||||
if (res.a0 != 0) {
|
||||
dev_err(&pdev->dev, "no ATF memory for init\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ddr_psci_param = ioremap(res.a1, page_num << 12);
|
||||
of_get_rk3328_timings(&pdev->dev, pdev->dev.of_node,
|
||||
(uint32_t *)ddr_psci_param);
|
||||
|
||||
arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
|
||||
SHARE_PAGE_TYPE_DDR, 0, ROCKCHIP_SIP_CONFIG_DRAM_INIT,
|
||||
0, 0, 0, 0, &res);
|
||||
if (res.a0) {
|
||||
dev_err(&pdev->dev, "Rockchip dram init error %lx\n", res.a0);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
dmcfreq->set_auto_self_refresh = rockchip_ddr_set_auto_self_refresh;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk3328_dmcfreq_target(struct device *dev, unsigned long *freq,
|
||||
u32 flags)
|
||||
{
|
||||
struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);
|
||||
struct dev_pm_opp *opp;
|
||||
unsigned long old_clk_rate = dmcfreq->rate;
|
||||
unsigned long target_volt, target_rate;
|
||||
int err;
|
||||
|
||||
opp = devfreq_recommended_opp(dev, freq, flags);
|
||||
if (IS_ERR(opp))
|
||||
return PTR_ERR(opp);
|
||||
|
||||
target_rate = dev_pm_opp_get_freq(opp);
|
||||
target_volt = dev_pm_opp_get_voltage(opp);
|
||||
dev_pm_opp_put(opp);
|
||||
|
||||
if (dmcfreq->rate == target_rate)
|
||||
return 0;
|
||||
|
||||
mutex_lock(&dmcfreq->lock);
|
||||
|
||||
/*
|
||||
* If frequency scaling from low to high, adjust voltage first.
|
||||
* If frequency scaling from high to low, adjust frequency first.
|
||||
*/
|
||||
if (old_clk_rate < target_rate) {
|
||||
err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
|
||||
target_volt);
|
||||
if (err) {
|
||||
dev_err(dev, "Cannot set voltage %lu uV\n",
|
||||
target_volt);
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
|
||||
if (err) {
|
||||
dev_err(dev, "Cannot set frequency %lu (%d)\n", target_rate,
|
||||
err);
|
||||
regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
|
||||
dmcfreq->volt);
|
||||
goto out;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check the dpll rate,
|
||||
* There only two result we will get,
|
||||
* 1. Ddr frequency scaling fail, we still get the old rate.
|
||||
* 2. Ddr frequency scaling sucessful, we get the rate we set.
|
||||
*/
|
||||
dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
|
||||
|
||||
/* If get the incorrect rate, set voltage to old value. */
|
||||
if (dmcfreq->rate != target_rate) {
|
||||
dev_err(dev, "Got wrong frequency, Request %lu, Current %lu\n",
|
||||
target_rate, dmcfreq->rate);
|
||||
regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
|
||||
dmcfreq->volt);
|
||||
goto out;
|
||||
} else if (old_clk_rate > target_rate)
|
||||
err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
|
||||
target_volt);
|
||||
if (err)
|
||||
dev_err(dev, "Cannot set voltage %lu uV\n", target_volt);
|
||||
|
||||
dmcfreq->rate = target_rate;
|
||||
dmcfreq->volt = target_volt;
|
||||
|
||||
out:
|
||||
mutex_unlock(&dmcfreq->lock);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int rk3328_dmcfreq_get_dev_status(struct device *dev,
|
||||
struct devfreq_dev_status *stat)
|
||||
{
|
||||
struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);
|
||||
struct devfreq_event_data edata;
|
||||
int ret = 0;
|
||||
|
||||
ret = devfreq_event_get_event(dmcfreq->edev, &edata);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
stat->current_frequency = dmcfreq->rate;
|
||||
stat->busy_time = edata.load_count;
|
||||
stat->total_time = edata.total_count;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rk3328_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq)
|
||||
{
|
||||
struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);
|
||||
|
||||
*freq = dmcfreq->rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct devfreq_dev_profile rk3328_devfreq_dmc_profile = {
|
||||
.polling_ms = 200,
|
||||
.target = rk3328_dmcfreq_target,
|
||||
.get_dev_status = rk3328_dmcfreq_get_dev_status,
|
||||
.get_cur_freq = rk3328_dmcfreq_get_cur_freq,
|
||||
};
|
||||
|
||||
static __maybe_unused int rk3328_dmcfreq_suspend(struct device *dev)
|
||||
{
|
||||
struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);
|
||||
int ret = 0;
|
||||
|
||||
ret = devfreq_event_disable_edev(dmcfreq->edev);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to disable the devfreq-event devices\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devfreq_suspend_device(dmcfreq->devfreq);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to suspend the devfreq devices\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static __maybe_unused int rk3328_dmcfreq_resume(struct device *dev)
|
||||
{
|
||||
struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);
|
||||
int ret = 0;
|
||||
|
||||
ret = devfreq_event_enable_edev(dmcfreq->edev);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to enable the devfreq-event devices\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devfreq_resume_device(dmcfreq->devfreq);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to resume the devfreq devices\n");
|
||||
return ret;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(rk3328_dmcfreq_pm, rk3328_dmcfreq_suspend,
|
||||
rk3328_dmcfreq_resume);
|
||||
|
||||
static int rk3328_dmcfreq_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct rk3328_dmcfreq *data;
|
||||
struct dev_pm_opp *opp;
|
||||
int ret;
|
||||
|
||||
data = devm_kzalloc(dev, sizeof(struct rk3328_dmcfreq), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
mutex_init(&data->lock);
|
||||
|
||||
data->vdd_center = devm_regulator_get(dev, "center");
|
||||
if (IS_ERR(data->vdd_center)) {
|
||||
if (PTR_ERR(data->vdd_center) == -EPROBE_DEFER)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
dev_err(dev, "Cannot get the regulator \"center\"\n");
|
||||
return PTR_ERR(data->vdd_center);
|
||||
}
|
||||
|
||||
data->dmc_clk = devm_clk_get(dev, "dmc_clk");
|
||||
if (IS_ERR(data->dmc_clk)) {
|
||||
if (PTR_ERR(data->dmc_clk) == -EPROBE_DEFER)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
dev_err(dev, "Cannot get the clk dmc_clk\n");
|
||||
return PTR_ERR(data->dmc_clk);
|
||||
}
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 9, 0)
|
||||
data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
|
||||
#else
|
||||
data->edev = devfreq_event_get_edev_by_phandle(dev, "devfreq-events", 0);
|
||||
#endif
|
||||
if (IS_ERR(data->edev))
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
ret = devfreq_event_enable_edev(data->edev);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to enable devfreq-event devices\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = rk3328_dmc_init(pdev, data);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/*
|
||||
* We add a devfreq driver to our parent since it has a device tree node
|
||||
* with operating points.
|
||||
*/
|
||||
if (dev_pm_opp_of_add_table(dev)) {
|
||||
dev_err(dev, "Invalid operating-points in device tree.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
of_property_read_u32(np, "upthreshold",
|
||||
&data->ondemand_data.upthreshold);
|
||||
of_property_read_u32(np, "downdifferential",
|
||||
&data->ondemand_data.downdifferential);
|
||||
|
||||
data->rate = clk_get_rate(data->dmc_clk);
|
||||
|
||||
opp = devfreq_recommended_opp(dev, &data->rate, 0);
|
||||
if (IS_ERR(opp)) {
|
||||
ret = PTR_ERR(opp);
|
||||
goto err_free_opp;
|
||||
}
|
||||
|
||||
data->rate = dev_pm_opp_get_freq(opp);
|
||||
data->volt = dev_pm_opp_get_voltage(opp);
|
||||
dev_pm_opp_put(opp);
|
||||
|
||||
rk3328_devfreq_dmc_profile.initial_freq = data->rate;
|
||||
|
||||
data->devfreq = devm_devfreq_add_device(dev,
|
||||
&rk3328_devfreq_dmc_profile,
|
||||
DEVFREQ_GOV_SIMPLE_ONDEMAND,
|
||||
&data->ondemand_data);
|
||||
if (IS_ERR(data->devfreq)) {
|
||||
ret = PTR_ERR(data->devfreq);
|
||||
goto err_free_opp;
|
||||
}
|
||||
|
||||
devm_devfreq_register_opp_notifier(dev, data->devfreq);
|
||||
|
||||
data->dev = dev;
|
||||
platform_set_drvdata(pdev, data);
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_opp:
|
||||
dev_pm_opp_of_remove_table(&pdev->dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rk3328_dmcfreq_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(&pdev->dev);
|
||||
|
||||
/*
|
||||
* Before remove the opp table we need to unregister the opp notifier.
|
||||
*/
|
||||
devm_devfreq_unregister_opp_notifier(dmcfreq->dev, dmcfreq->devfreq);
|
||||
dev_pm_opp_of_remove_table(dmcfreq->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id rk3328dmc_devfreq_of_match[] = {
|
||||
{ .compatible = "rockchip,rk3328-dmc" },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rk3328dmc_devfreq_of_match);
|
||||
|
||||
static struct platform_driver rk3328_dmcfreq_driver = {
|
||||
.probe = rk3328_dmcfreq_probe,
|
||||
.remove = rk3328_dmcfreq_remove,
|
||||
.driver = {
|
||||
.name = "rk3328-dmc-freq",
|
||||
.pm = &rk3328_dmcfreq_pm,
|
||||
.of_match_table = rk3328dmc_devfreq_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(rk3328_dmcfreq_driver);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
|
||||
MODULE_DESCRIPTION("RK3328 dmcfreq driver with devfreq framework");
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
*
|
||||
* Copyright (C) 2017 ROCKCHIP, Inc.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H
|
||||
#define _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H
|
||||
|
||||
#define DDR2_DEFAULT (0)
|
||||
|
||||
#define DDR3_800D (0) /* 5-5-5 */
|
||||
#define DDR3_800E (1) /* 6-6-6 */
|
||||
#define DDR3_1066E (2) /* 6-6-6 */
|
||||
#define DDR3_1066F (3) /* 7-7-7 */
|
||||
#define DDR3_1066G (4) /* 8-8-8 */
|
||||
#define DDR3_1333F (5) /* 7-7-7 */
|
||||
#define DDR3_1333G (6) /* 8-8-8 */
|
||||
#define DDR3_1333H (7) /* 9-9-9 */
|
||||
#define DDR3_1333J (8) /* 10-10-10 */
|
||||
#define DDR3_1600G (9) /* 8-8-8 */
|
||||
#define DDR3_1600H (10) /* 9-9-9 */
|
||||
#define DDR3_1600J (11) /* 10-10-10 */
|
||||
#define DDR3_1600K (12) /* 11-11-11 */
|
||||
#define DDR3_1866J (13) /* 10-10-10 */
|
||||
#define DDR3_1866K (14) /* 11-11-11 */
|
||||
#define DDR3_1866L (15) /* 12-12-12 */
|
||||
#define DDR3_1866M (16) /* 13-13-13 */
|
||||
#define DDR3_2133K (17) /* 11-11-11 */
|
||||
#define DDR3_2133L (18) /* 12-12-12 */
|
||||
#define DDR3_2133M (19) /* 13-13-13 */
|
||||
#define DDR3_2133N (20) /* 14-14-14 */
|
||||
#define DDR3_DEFAULT (21)
|
||||
#define DDR_DDR2 (22)
|
||||
#define DDR_LPDDR (23)
|
||||
#define DDR_LPDDR2 (24)
|
||||
|
||||
#define DDR4_1600J (0) /* 10-10-10 */
|
||||
#define DDR4_1600K (1) /* 11-11-11 */
|
||||
#define DDR4_1600L (2) /* 12-12-12 */
|
||||
#define DDR4_1866L (3) /* 12-12-12 */
|
||||
#define DDR4_1866M (4) /* 13-13-13 */
|
||||
#define DDR4_1866N (5) /* 14-14-14 */
|
||||
#define DDR4_2133N (6) /* 14-14-14 */
|
||||
#define DDR4_2133P (7) /* 15-15-15 */
|
||||
#define DDR4_2133R (8) /* 16-16-16 */
|
||||
#define DDR4_2400P (9) /* 15-15-15 */
|
||||
#define DDR4_2400R (10) /* 16-16-16 */
|
||||
#define DDR4_2400U (11) /* 18-18-18 */
|
||||
#define DDR4_DEFAULT (12)
|
||||
|
||||
#define PAUSE_CPU_STACK_SIZE 16
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,159 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H
|
||||
#define _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H
|
||||
|
||||
#define DDR3_DS_34ohm (34)
|
||||
#define DDR3_DS_40ohm (40)
|
||||
|
||||
#define DDR3_ODT_DIS (0)
|
||||
#define DDR3_ODT_40ohm (40)
|
||||
#define DDR3_ODT_60ohm (60)
|
||||
#define DDR3_ODT_120ohm (120)
|
||||
|
||||
#define LP2_DS_34ohm (34)
|
||||
#define LP2_DS_40ohm (40)
|
||||
#define LP2_DS_48ohm (48)
|
||||
#define LP2_DS_60ohm (60)
|
||||
#define LP2_DS_68_6ohm (68) /* optional */
|
||||
#define LP2_DS_80ohm (80)
|
||||
#define LP2_DS_120ohm (120) /* optional */
|
||||
|
||||
#define LP3_DS_34ohm (34)
|
||||
#define LP3_DS_40ohm (40)
|
||||
#define LP3_DS_48ohm (48)
|
||||
#define LP3_DS_60ohm (60)
|
||||
#define LP3_DS_80ohm (80)
|
||||
#define LP3_DS_34D_40U (3440)
|
||||
#define LP3_DS_40D_48U (4048)
|
||||
#define LP3_DS_34D_48U (3448)
|
||||
|
||||
#define LP3_ODT_DIS (0)
|
||||
#define LP3_ODT_60ohm (60)
|
||||
#define LP3_ODT_120ohm (120)
|
||||
#define LP3_ODT_240ohm (240)
|
||||
|
||||
#define LP4_PDDS_40ohm (40)
|
||||
#define LP4_PDDS_48ohm (48)
|
||||
#define LP4_PDDS_60ohm (60)
|
||||
#define LP4_PDDS_80ohm (80)
|
||||
#define LP4_PDDS_120ohm (120)
|
||||
#define LP4_PDDS_240ohm (240)
|
||||
|
||||
#define LP4_DQ_ODT_40ohm (40)
|
||||
#define LP4_DQ_ODT_48ohm (48)
|
||||
#define LP4_DQ_ODT_60ohm (60)
|
||||
#define LP4_DQ_ODT_80ohm (80)
|
||||
#define LP4_DQ_ODT_120ohm (120)
|
||||
#define LP4_DQ_ODT_240ohm (240)
|
||||
#define LP4_DQ_ODT_DIS (0)
|
||||
|
||||
#define LP4_CA_ODT_40ohm (40)
|
||||
#define LP4_CA_ODT_48ohm (48)
|
||||
#define LP4_CA_ODT_60ohm (60)
|
||||
#define LP4_CA_ODT_80ohm (80)
|
||||
#define LP4_CA_ODT_120ohm (120)
|
||||
#define LP4_CA_ODT_240ohm (240)
|
||||
#define LP4_CA_ODT_DIS (0)
|
||||
|
||||
#define DDR4_DS_34ohm (34)
|
||||
#define DDR4_DS_48ohm (48)
|
||||
#define DDR4_RTT_NOM_DIS (0)
|
||||
#define DDR4_RTT_NOM_60ohm (60)
|
||||
#define DDR4_RTT_NOM_120ohm (120)
|
||||
#define DDR4_RTT_NOM_40ohm (40)
|
||||
#define DDR4_RTT_NOM_240ohm (240)
|
||||
#define DDR4_RTT_NOM_48ohm (48)
|
||||
#define DDR4_RTT_NOM_80ohm (80)
|
||||
#define DDR4_RTT_NOM_34ohm (34)
|
||||
|
||||
#define PHY_DDR3_RON_RTT_DISABLE (0)
|
||||
#define PHY_DDR3_RON_RTT_451ohm (1)
|
||||
#define PHY_DDR3_RON_RTT_225ohm (2)
|
||||
#define PHY_DDR3_RON_RTT_150ohm (3)
|
||||
#define PHY_DDR3_RON_RTT_112ohm (4)
|
||||
#define PHY_DDR3_RON_RTT_90ohm (5)
|
||||
#define PHY_DDR3_RON_RTT_75ohm (6)
|
||||
#define PHY_DDR3_RON_RTT_64ohm (7)
|
||||
#define PHY_DDR3_RON_RTT_56ohm (16)
|
||||
#define PHY_DDR3_RON_RTT_50ohm (17)
|
||||
#define PHY_DDR3_RON_RTT_45ohm (18)
|
||||
#define PHY_DDR3_RON_RTT_41ohm (19)
|
||||
#define PHY_DDR3_RON_RTT_37ohm (20)
|
||||
#define PHY_DDR3_RON_RTT_34ohm (21)
|
||||
#define PHY_DDR3_RON_RTT_33ohm (22)
|
||||
#define PHY_DDR3_RON_RTT_30ohm (23)
|
||||
#define PHY_DDR3_RON_RTT_28ohm (24)
|
||||
#define PHY_DDR3_RON_RTT_26ohm (25)
|
||||
#define PHY_DDR3_RON_RTT_25ohm (26)
|
||||
#define PHY_DDR3_RON_RTT_23ohm (27)
|
||||
#define PHY_DDR3_RON_RTT_22ohm (28)
|
||||
#define PHY_DDR3_RON_RTT_21ohm (29)
|
||||
#define PHY_DDR3_RON_RTT_20ohm (30)
|
||||
#define PHY_DDR3_RON_RTT_19ohm (31)
|
||||
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_480ohm (1)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_240ohm (2)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_160ohm (3)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_120ohm (4)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_96ohm (5)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_80ohm (6)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_68ohm (7)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_60ohm (16)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_53ohm (17)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_48ohm (18)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_43ohm (19)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_40ohm (20)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_37ohm (21)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_34ohm (22)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_32ohm (23)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_30ohm (24)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_28ohm (25)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_26ohm (26)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_25ohm (27)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_24ohm (28)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_22ohm (29)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_21ohm (30)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_20ohm (31)
|
||||
|
||||
#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H*/
|
||||
82
6.1/target/linux/rockchip/image/Makefile
Normal file
82
6.1/target/linux/rockchip/image/Makefile
Normal file
|
|
@ -0,0 +1,82 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
include $(TOPDIR)/rules.mk
|
||||
include $(INCLUDE_DIR)/image.mk
|
||||
|
||||
DEVICE_VARS += UBOOT_DEVICE_NAME
|
||||
|
||||
define Build/Compile
|
||||
$(CP) $(LINUX_DIR)/COPYING $(KDIR)/COPYING.linux
|
||||
endef
|
||||
|
||||
### Image scripts ###
|
||||
define Build/boot-common
|
||||
# This creates a new folder copies the dtb (as rockchip.dtb)
|
||||
# and the kernel image (as kernel.img)
|
||||
rm -fR $@.boot
|
||||
mkdir -p $@.boot
|
||||
|
||||
$(CP) $(DTS_DIR)/$(DEVICE_DTS).dtb $@.boot/rockchip.dtb
|
||||
$(CP) $(IMAGE_KERNEL) $@.boot/kernel.img
|
||||
endef
|
||||
|
||||
define Build/boot-script
|
||||
# Make an U-boot image and copy it to the boot partition
|
||||
mkimage -A arm -O linux -T script -C none -a 0 -e 0 -d $(if $(1),$(1),mmc).bootscript $@.boot/boot.scr
|
||||
endef
|
||||
|
||||
define Build/pine64-img
|
||||
# Creates the final SD/eMMC images,
|
||||
# combining boot partition, root partition as well as the u-boot bootloader
|
||||
|
||||
# Generate a new partition table in $@ with 32 MiB of
|
||||
# alignment padding for the idbloader and u-boot to fit:
|
||||
# http://opensource.rock-chips.com/wiki_Boot_option#Boot_flow
|
||||
#
|
||||
# U-Boot SPL expects the U-Boot ITB to be located at sector 0x4000 (8 MiB) on the MMC storage
|
||||
PADDING=1 $(SCRIPT_DIR)/gen_image_generic.sh \
|
||||
$@ \
|
||||
$(CONFIG_TARGET_KERNEL_PARTSIZE) $@.boot \
|
||||
$(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS) \
|
||||
32768
|
||||
|
||||
# Copy the idbloader and the u-boot image to the image at sector 0x40 and 0x4000
|
||||
dd if="$(STAGING_DIR_IMAGE)"/$(UBOOT_DEVICE_NAME)-idbloader.img of="$@" seek=64 conv=notrunc
|
||||
dd if="$(STAGING_DIR_IMAGE)"/$(UBOOT_DEVICE_NAME)-u-boot.itb of="$@" seek=16384 conv=notrunc
|
||||
endef
|
||||
|
||||
define Build/pine64-bin
|
||||
# Typical Rockchip boot flow with Rockchip miniloader
|
||||
# Rockchp idbLoader which is combinded by Rockchip ddr init bin
|
||||
# and miniloader bin from Rockchip rkbin project
|
||||
|
||||
# Generate a new partition table in $@ with 32 MiB of alignment
|
||||
# padding for the idbloader, uboot and trust image to fit:
|
||||
# http://opensource.rock-chips.com/wiki_Boot_option#Boot_flow
|
||||
PADDING=1 $(SCRIPT_DIR)/gen_image_generic.sh \
|
||||
$@ \
|
||||
$(CONFIG_TARGET_KERNEL_PARTSIZE) $@.boot \
|
||||
$(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS) \
|
||||
32768
|
||||
|
||||
# Copy the idbloader, uboot and trust image to the image at sector 0x40, 0x4000 and 0x6000
|
||||
dd if="$(STAGING_DIR_IMAGE)"/$(SOC)-idbloader.bin of="$@" seek=64 conv=notrunc
|
||||
dd if="$(STAGING_DIR_IMAGE)"/$(UBOOT_DEVICE_NAME)-uboot.img of="$@" seek=16384 conv=notrunc
|
||||
dd if="$(STAGING_DIR_IMAGE)"/$(SOC)-trust.bin of="$@" seek=24576 conv=notrunc
|
||||
endef
|
||||
|
||||
### Devices ###
|
||||
define Device/Default
|
||||
PROFILES := Default
|
||||
KERNEL := kernel-bin
|
||||
IMAGES := sysupgrade.img.gz
|
||||
DEVICE_DTS = rockchip/$$(SOC)-$(lastword $(subst _, ,$(1)))
|
||||
endef
|
||||
|
||||
ifdef CONFIG_LINUX_6_1
|
||||
DTS_CPPFLAGS += -DDTS_NO_LEGACY
|
||||
endif
|
||||
|
||||
include $(SUBTARGET).mk
|
||||
|
||||
$(eval $(call BuildImage))
|
||||
273
6.1/target/linux/rockchip/image/armv8.mk
Normal file
273
6.1/target/linux/rockchip/image/armv8.mk
Normal file
|
|
@ -0,0 +1,273 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
#
|
||||
# Copyright (C) 2020 Tobias Maedel
|
||||
|
||||
define Device/ariaboard_photonicat
|
||||
DEVICE_VENDOR := Ariaboard
|
||||
DEVICE_MODEL := Photonicat
|
||||
SOC := rk3568
|
||||
UBOOT_DEVICE_NAME := photonicat-rk3568
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := ath10k-firmware-qca9377-sdio kmod-ath10k kmod-ath10k-sdio pcat-manager
|
||||
endef
|
||||
TARGET_DEVICES += ariaboard_photonicat
|
||||
|
||||
define Device/dilusense_dlfr100
|
||||
DEVICE_VENDOR := Dilusense
|
||||
DEVICE_MODEL := DLFR100
|
||||
SOC := rk3399
|
||||
UBOOT_DEVICE_NAME := dilusense-dlfr100-rk3399
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-bin | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-r8168 -urngd
|
||||
endef
|
||||
TARGET_DEVICES += dilusense_dlfr100
|
||||
|
||||
define Device/ezpro_mrkaio-m68s
|
||||
DEVICE_VENDOR := EZPRO
|
||||
DEVICE_MODEL := Mrkaio M68S
|
||||
SOC := rk3568
|
||||
UBOOT_DEVICE_NAME := mrkaio-m68s-rk3568
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-ata-ahci kmod-ata-ahci-platform
|
||||
endef
|
||||
TARGET_DEVICES += ezpro_mrkaio-m68s
|
||||
|
||||
define Device/ezpro_mrkaio-m68s-plus
|
||||
DEVICE_VENDOR := EZPRO
|
||||
DEVICE_MODEL := Mrkaio M68S PLUS
|
||||
SOC := rk3568
|
||||
UBOOT_DEVICE_NAME := mrkaio-m68s-rk3568
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-r8125 kmod-ata-ahci kmod-ata-ahci-platform kmod-nvme kmod-scsi-core
|
||||
endef
|
||||
TARGET_DEVICES += ezpro_mrkaio-m68s-plus
|
||||
|
||||
define Device/hinlink_common
|
||||
DEVICE_VENDOR := HINLINK
|
||||
UBOOT_DEVICE_NAME := opc-h68k-rk3568
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-ata-ahci-platform kmod-mt7921e kmod-r8125 kmod-usb-serial-cp210x wpad-openssl
|
||||
endef
|
||||
|
||||
define Device/hinlink_opc-h66k
|
||||
$(call Device/hinlink_common)
|
||||
DEVICE_MODEL := OPC-H66K
|
||||
SOC := rk3568
|
||||
endef
|
||||
TARGET_DEVICES += hinlink_opc-h66k
|
||||
|
||||
define Device/hinlink_opc-h68k
|
||||
$(call Device/hinlink_common)
|
||||
DEVICE_MODEL := OPC-H68K
|
||||
SOC := rk3568
|
||||
endef
|
||||
TARGET_DEVICES += hinlink_opc-h68k
|
||||
|
||||
define Device/hinlink_opc-h69k
|
||||
$(call Device/hinlink_common)
|
||||
DEVICE_MODEL := OPC-H69K
|
||||
SOC := rk3568
|
||||
DEVICE_PACKAGES += kmod-usb-serial-option uqmi
|
||||
endef
|
||||
TARGET_DEVICES += hinlink_opc-h69k
|
||||
|
||||
define Device/fastrhino_common
|
||||
DEVICE_VENDOR := FastRhino
|
||||
SOC := rk3568
|
||||
UBOOT_DEVICE_NAME := r66s-rk3568
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-r8125
|
||||
endef
|
||||
|
||||
define Device/fastrhino_r66s
|
||||
$(call Device/fastrhino_common)
|
||||
DEVICE_MODEL := R66S
|
||||
endef
|
||||
TARGET_DEVICES += fastrhino_r66s
|
||||
|
||||
define Device/fastrhino_r68s
|
||||
$(call Device/fastrhino_common)
|
||||
DEVICE_MODEL := R68S
|
||||
endef
|
||||
TARGET_DEVICES += fastrhino_r68s
|
||||
|
||||
define Device/friendlyarm_nanopi-neo3
|
||||
DEVICE_VENDOR := FriendlyARM
|
||||
DEVICE_MODEL := NanoPi NEO3
|
||||
SOC := rk3328
|
||||
UBOOT_DEVICE_NAME := nanopi-r2s-rk3328
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-bin | gzip | append-metadata
|
||||
endef
|
||||
TARGET_DEVICES += friendlyarm_nanopi-neo3
|
||||
|
||||
define Device/friendlyarm_nanopi-r2c
|
||||
DEVICE_VENDOR := FriendlyARM
|
||||
DEVICE_MODEL := NanoPi R2C
|
||||
SOC := rk3328
|
||||
UBOOT_DEVICE_NAME := nanopi-r2c-rk3328
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-bin | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-usb-net-rtl8152
|
||||
endef
|
||||
TARGET_DEVICES += friendlyarm_nanopi-r2c
|
||||
|
||||
define Device/friendlyarm_nanopi-r2s
|
||||
DEVICE_VENDOR := FriendlyARM
|
||||
DEVICE_MODEL := NanoPi R2S
|
||||
SOC := rk3328
|
||||
UBOOT_DEVICE_NAME := nanopi-r2s-rk3328
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-bin | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-usb-net-rtl8152
|
||||
endef
|
||||
TARGET_DEVICES += friendlyarm_nanopi-r2s
|
||||
|
||||
define Device/friendlyarm_nanopi-r4s
|
||||
DEVICE_VENDOR := FriendlyARM
|
||||
DEVICE_MODEL := NanoPi R4S
|
||||
SOC := rk3399
|
||||
UBOOT_DEVICE_NAME := nanopi-r4s-rk3399
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r4s | pine64-bin | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-r8168 -urngd
|
||||
endef
|
||||
TARGET_DEVICES += friendlyarm_nanopi-r4s
|
||||
|
||||
define Device/friendlyarm_nanopi-r4se
|
||||
DEVICE_VENDOR := FriendlyARM
|
||||
DEVICE_MODEL := NanoPi R4SE
|
||||
SOC := rk3399
|
||||
UBOOT_DEVICE_NAME := nanopi-r4se-rk3399
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r4s | pine64-bin | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-r8168 -urngd
|
||||
endef
|
||||
TARGET_DEVICES += friendlyarm_nanopi-r4se
|
||||
|
||||
define Device/friendlyarm_nanopi-r5c
|
||||
DEVICE_VENDOR := FriendlyARM
|
||||
DEVICE_MODEL := NanoPi R5C
|
||||
SOC := rk3568
|
||||
UBOOT_DEVICE_NAME := nanopi-r5s-rk3568
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-r8125 kmod-nvme kmod-scsi-core
|
||||
endef
|
||||
TARGET_DEVICES += friendlyarm_nanopi-r5c
|
||||
|
||||
define Device/friendlyarm_nanopi-r5s
|
||||
DEVICE_VENDOR := FriendlyARM
|
||||
DEVICE_MODEL := NanoPi R5S
|
||||
SOC := rk3568
|
||||
UBOOT_DEVICE_NAME := nanopi-r5s-rk3568
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-r8125 kmod-nvme kmod-scsi-core
|
||||
endef
|
||||
TARGET_DEVICES += friendlyarm_nanopi-r5s
|
||||
|
||||
define Device/firefly_station-p2
|
||||
DEVICE_VENDOR := Firefly
|
||||
DEVICE_MODEL := Station P2
|
||||
DEVICE_DTS := rockchip/rk3568-roc-pc
|
||||
UBOOT_DEVICE_NAME := station-p2-rk3568
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-brcmfmac kmod-ikconfig kmod-ata-ahci-platform station-p2-firmware wpad-openssl
|
||||
endef
|
||||
TARGET_DEVICES += firefly_station-p2
|
||||
|
||||
define Device/pine64_rockpro64
|
||||
DEVICE_VENDOR := Pine64
|
||||
DEVICE_MODEL := RockPro64
|
||||
SOC := rk3399
|
||||
UBOOT_DEVICE_NAME := rockpro64-rk3399
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := -urngd
|
||||
endef
|
||||
TARGET_DEVICES += pine64_rockpro64
|
||||
|
||||
define Device/radxa_e25
|
||||
DEVICE_VENDOR := Radxa
|
||||
DEVICE_MODEL := E25
|
||||
DEVICE_DTS := rockchip/rk3568-radxa-e25
|
||||
UBOOT_DEVICE_NAME := radxa-e25-rk3568
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-ata-ahci-platform kmod-r8125
|
||||
endef
|
||||
TARGET_DEVICES += radxa_e25
|
||||
|
||||
define Device/radxa_rock-3a
|
||||
DEVICE_VENDOR := Radxa
|
||||
DEVICE_MODEL := ROCK3 A
|
||||
SOC := rk3568
|
||||
SUPPORTED_DEVICES := radxa,rock3a
|
||||
UBOOT_DEVICE_NAME := rock-3a-rk3568
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
|
||||
endef
|
||||
TARGET_DEVICES += radxa_rock-3a
|
||||
|
||||
define Device/radxa_rock-pi-4
|
||||
DEVICE_VENDOR := Radxa
|
||||
DEVICE_MODEL := ROCK Pi 4
|
||||
SOC := rk3399
|
||||
SUPPORTED_DEVICES := radxa,rockpi4
|
||||
UBOOT_DEVICE_NAME := rock-pi-4-rk3399
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := -urngd
|
||||
endef
|
||||
TARGET_DEVICES += radxa_rock-pi-4
|
||||
|
||||
define Device/rongpin_king3399
|
||||
DEVICE_VENDOR := Rongpin
|
||||
DEVICE_MODEL := King3399
|
||||
SOC := rk3399
|
||||
UBOOT_DEVICE_NAME := rongpin-king3399-rk3399
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r4s | pine64-bin | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-r8168 -urngd kmod-brcmfmac cypress-firmware-4356-sdio rongpin-king3399-firmware wpad-openssl
|
||||
endef
|
||||
TARGET_DEVICES += rongpin_king3399
|
||||
|
||||
define Device/rocktech_mpc1903
|
||||
DEVICE_VENDOR := Rocktech
|
||||
DEVICE_MODEL := MPC1903
|
||||
SOC := rk3399
|
||||
SUPPORTED_DEVICES := rocktech,mpc1903
|
||||
UBOOT_DEVICE_NAME := rocktech-mpc1903-rk3399
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-bin | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-usb-net-smsc75xx kmod-usb-serial-cp210x -urngd
|
||||
endef
|
||||
TARGET_DEVICES += rocktech_mpc1903
|
||||
|
||||
define Device/sharevdi_h3399pc
|
||||
DEVICE_VENDOR := SHAREVDI
|
||||
DEVICE_MODEL := H3399PC
|
||||
SOC := rk3399
|
||||
UBOOT_DEVICE_NAME := sharevdi-h3399pc-rk3399
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r4s | pine64-bin | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-r8168 -urngd
|
||||
endef
|
||||
TARGET_DEVICES += sharevdi_h3399pc
|
||||
|
||||
define Device/sharevdi_guangmiao-g4c
|
||||
DEVICE_VENDOR := SHAREVDI
|
||||
DEVICE_MODEL := GuangMiao G4C
|
||||
SOC := rk3399
|
||||
UBOOT_DEVICE_NAME := guangmiao-g4c-rk3399
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r4s | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-r8168 -urngd
|
||||
endef
|
||||
TARGET_DEVICES += sharevdi_guangmiao-g4c
|
||||
|
||||
define Device/xunlong_orangepi-r1-plus
|
||||
DEVICE_VENDOR := Xunlong
|
||||
DEVICE_MODEL := Orange Pi R1 Plus
|
||||
SOC := rk3328
|
||||
UBOOT_DEVICE_NAME := orangepi-r1-plus-rk3328
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-bin | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-usb-net-rtl8152
|
||||
endef
|
||||
TARGET_DEVICES += xunlong_orangepi-r1-plus
|
||||
|
||||
define Device/xunlong_orangepi-r1-plus-lts
|
||||
DEVICE_VENDOR := Xunlong
|
||||
DEVICE_MODEL := Orange Pi R1 Plus LTS
|
||||
SOC := rk3328
|
||||
UBOOT_DEVICE_NAME := orangepi-r1-plus-lts-rk3328
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-bin | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-usb-net-rtl8152
|
||||
endef
|
||||
TARGET_DEVICES += xunlong_orangepi-r1-plus-lts
|
||||
8
6.1/target/linux/rockchip/image/mmc.bootscript
Normal file
8
6.1/target/linux/rockchip/image/mmc.bootscript
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
part uuid mmc ${devnum}:2 uuid
|
||||
|
||||
setenv bootargs "console=ttyS2,1500000 console=tty1 earlycon=uart8250,mmio32,0xff1a0000 root=PARTUUID=${uuid} rw rootwait"
|
||||
|
||||
load mmc ${devnum}:1 ${fdt_addr_r} rockchip.dtb
|
||||
load mmc ${devnum}:1 ${kernel_addr_r} kernel.img
|
||||
|
||||
booti ${kernel_addr_r} - ${fdt_addr_r}
|
||||
8
6.1/target/linux/rockchip/image/nanopi-r2s.bootscript
Normal file
8
6.1/target/linux/rockchip/image/nanopi-r2s.bootscript
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
part uuid mmc ${devnum}:2 uuid
|
||||
|
||||
setenv bootargs "console=ttyS2,1500000 earlycon=uart8250,mmio32,0xff130000 root=PARTUUID=${uuid} rw rootwait"
|
||||
|
||||
load mmc ${devnum}:1 ${fdt_addr_r} rockchip.dtb
|
||||
load mmc ${devnum}:1 ${kernel_addr_r} kernel.img
|
||||
|
||||
booti ${kernel_addr_r} - ${fdt_addr_r}
|
||||
8
6.1/target/linux/rockchip/image/nanopi-r4s.bootscript
Normal file
8
6.1/target/linux/rockchip/image/nanopi-r4s.bootscript
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
part uuid mmc ${devnum}:2 uuid
|
||||
|
||||
setenv bootargs "console=ttyS2,1500000 earlycon=uart8250,mmio32,0xff1a0000 root=PARTUUID=${uuid} rw rootwait"
|
||||
|
||||
load mmc ${devnum}:1 ${fdt_addr_r} rockchip.dtb
|
||||
load mmc ${devnum}:1 ${kernel_addr_r} kernel.img
|
||||
|
||||
booti ${kernel_addr_r} - ${fdt_addr_r}
|
||||
8
6.1/target/linux/rockchip/image/nanopi-r5s.bootscript
Normal file
8
6.1/target/linux/rockchip/image/nanopi-r5s.bootscript
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
part uuid mmc ${devnum}:2 uuid
|
||||
|
||||
setenv bootargs "console=ttyS2,1500000 earlycon=uart8250,mmio32,0xfe660000 root=PARTUUID=${uuid} rw rootwait"
|
||||
|
||||
load mmc ${devnum}:1 ${fdt_addr_r} rockchip.dtb
|
||||
load mmc ${devnum}:1 ${kernel_addr_r} kernel.img
|
||||
|
||||
booti ${kernel_addr_r} - ${fdt_addr_r}
|
||||
70
6.1/target/linux/rockchip/modules.mk
Normal file
70
6.1/target/linux/rockchip/modules.mk
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
#
|
||||
# Copyright (C) 2020 OpenWrt.org
|
||||
|
||||
define KernelPackage/drm-rockchip
|
||||
SUBMENU:=$(VIDEO_MENU)
|
||||
TITLE:=Rockchip DRM support
|
||||
DEPENDS:=@TARGET_rockchip +kmod-backlight +kmod-drm-kms-helper \
|
||||
+kmod-multimedia-input +LINUX_6_1:kmod-drm-display-helper
|
||||
KCONFIG:= \
|
||||
CONFIG_DRM_ROCKCHIP \
|
||||
CONFIG_DRM_LOAD_EDID_FIRMWARE=y \
|
||||
CONFIG_DRM_FBDEV_EMULATION=y \
|
||||
CONFIG_DRM_FBDEV_OVERALLOC=100 \
|
||||
CONFIG_DRM_BRIDGE=y \
|
||||
CONFIG_HDMI=y \
|
||||
CONFIG_PHY_ROCKCHIP_INNO_HDMI \
|
||||
CONFIG_DRM_DW_HDMI \
|
||||
CONFIG_DRM_DW_HDMI_CEC \
|
||||
CONFIG_ROCKCHIP_ANALOGIX_DP=n \
|
||||
CONFIG_ROCKCHIP_CDN_DP=n \
|
||||
CONFIG_ROCKCHIP_DW_HDMI=y \
|
||||
CONFIG_ROCKCHIP_DW_MIPI_DSI=y \
|
||||
CONFIG_ROCKCHIP_INNO_HDMI=y \
|
||||
CONFIG_ROCKCHIP_LVDS=y \
|
||||
CONFIG_ROCKCHIP_RGB=n \
|
||||
CONFIG_ROCKCHIP_RK3066_HDMI=n \
|
||||
CONFIG_ROCKCHIP_VOP=y \
|
||||
CONFIG_ROCKCHIP_VOP2=y \
|
||||
CONFIG_DRM_GEM_CMA_HELPER@lt6.1 \
|
||||
CONFIG_DRM_GEM_DMA_HELPER@ge6.1 \
|
||||
CONFIG_DRM_PANEL=y \
|
||||
CONFIG_DRM_PANEL_BRIDGE=y \
|
||||
CONFIG_DRM_PANEL_SIMPLE
|
||||
FILES:= \
|
||||
$(LINUX_DIR)/drivers/gpu/drm/bridge/synopsys/dw-hdmi.ko \
|
||||
$(LINUX_DIR)/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.ko \
|
||||
$(LINUX_DIR)/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.ko \
|
||||
$(LINUX_DIR)/drivers/phy/rockchip/phy-rockchip-inno-hdmi.ko \
|
||||
$(LINUX_DIR)/drivers/gpu/drm/drm_dp_aux_bus.ko@lt5.19 \
|
||||
$(LINUX_DIR)/drivers/gpu/drm/drm_dma_helper.ko@ge6.1 \
|
||||
$(LINUX_DIR)/drivers/gpu/drm/panel/panel-simple.ko \
|
||||
$(LINUX_DIR)/drivers/gpu/drm/rockchip/rockchipdrm.ko \
|
||||
$(LINUX_DIR)/drivers/media/cec/core/cec.ko
|
||||
AUTOLOAD:=$(call AutoProbe,rockchipdrm phy-rockchip-inno-hdmi dw-hdmi-cec)
|
||||
endef
|
||||
|
||||
define KernelPackage/drm-rockchip/description
|
||||
Direct Rendering Manager (DRM) support for Rockchip
|
||||
endef
|
||||
|
||||
$(eval $(call KernelPackage,drm-rockchip))
|
||||
|
||||
define KernelPackage/saradc-rockchip
|
||||
SUBMENU:=$(IIO_MENU)
|
||||
TITLE:=Rockchip SARADC support
|
||||
DEPENDS:=@TARGET_rockchip +kmod-industrialio-triggered-buffer
|
||||
KCONFIG:= \
|
||||
CONFIG_RESET_CONTROLLER=y \
|
||||
CONFIG_ROCKCHIP_SARADC
|
||||
FILES:= \
|
||||
$(LINUX_DIR)/drivers/iio/adc/rockchip_saradc.ko
|
||||
AUTOLOAD:=$(call AutoProbe,rockchip_saradc)
|
||||
endef
|
||||
|
||||
define KernelPackage/saradc-rockchip/description
|
||||
Support for the SARADC found in SoCs from Rockchip
|
||||
endef
|
||||
|
||||
$(eval $(call KernelPackage,saradc-rockchip))
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
--- a/drivers/net/ethernet/realtek/r8169_main.c
|
||||
+++ b/drivers/net/ethernet/realtek/r8169_main.c
|
||||
@@ -17,6 +17,7 @@
|
||||
#include <linux/delay.h>
|
||||
#include <linux/ethtool.h>
|
||||
#include <linux/phy.h>
|
||||
+#include <linux/of.h>
|
||||
#include <linux/if_vlan.h>
|
||||
#include <linux/in.h>
|
||||
#include <linux/io.h>
|
||||
@@ -171,6 +172,7 @@ enum rtl_registers {
|
||||
MAR0 = 8, /* Multicast filter. */
|
||||
CounterAddrLow = 0x10,
|
||||
CounterAddrHigh = 0x14,
|
||||
+ CustomLED = 0x18,
|
||||
TxDescStartAddrLow = 0x20,
|
||||
TxDescStartAddrHigh = 0x24,
|
||||
TxHDescStartAddrLow = 0x28,
|
||||
@@ -5133,6 +5135,22 @@ static bool rtl_aspm_is_safe(struct rtl8
|
||||
return false;
|
||||
}
|
||||
|
||||
+static int rtl_led_configuration(struct rtl8169_private *tp)
|
||||
+{
|
||||
+ u32 led_data;
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = of_property_read_u32(tp->pci_dev->dev.of_node,
|
||||
+ "realtek,led-data", &led_data);
|
||||
+
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ RTL_W16(tp, CustomLED, led_data);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
{
|
||||
struct rtl8169_private *tp;
|
||||
@@ -5306,6 +5324,7 @@ static int rtl_init_one(struct pci_dev *
|
||||
if (!tp->counters)
|
||||
return -ENOMEM;
|
||||
|
||||
+ rtl_led_configuration(tp);
|
||||
pci_set_drvdata(pdev, tp);
|
||||
|
||||
rc = r8169_mdio_register(tp);
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -30,6 +30,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gr
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-dumo.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-inx.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-kd.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-guangmiao-g4c.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-r4se.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-hugsun-x99.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-captain.dtb
|
||||
@@ -50,6 +52,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ro
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-plus.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-4c-plus.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a-plus.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts
|
||||
@@ -0,0 +1,13 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright (c) 2019 Akash Gajjar <Akash_Gajjar@mentor.com>
|
||||
+ * Copyright (c) 2019 Pragnesh Patel <Pragnesh_Patel@mentor.com>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include "rk3399-rock-pi-4.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Radxa ROCK Pi 4";
|
||||
+ compatible = "radxa,rockpi4", "rockchip,rk3399";
|
||||
+};
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
From 0d329112c709d6cfedf0fffb19f0cc6b19043f6b Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Wed, 20 Feb 2019 07:38:34 +0000
|
||||
Subject: [PATCH] mmc: core: set initial signal voltage on power off
|
||||
|
||||
Some boards have SD card connectors where the power rail cannot be switched
|
||||
off by the driver. If the card has not been power cycled, it may still be
|
||||
using 1.8V signaling after a warm re-boot. Bootroms expecting 3.3V signaling
|
||||
will fail to boot from a UHS card that continue to use 1.8V signaling.
|
||||
|
||||
Set initial signal voltage in mmc_power_off() to allow re-boot to function.
|
||||
|
||||
This fixes re-boot with UHS cards on Asus Tinker Board (Rockchip RK3288),
|
||||
same issue have been seen on some Rockchip RK3399 boards.
|
||||
|
||||
I am sending this as a RFC because I have no insights into SD/MMC subsystem,
|
||||
this change fix a re-boot issue on my boards and does not break emmc/sdio.
|
||||
Is this an acceptable workaround? Any advice is appreciated.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
---
|
||||
drivers/mmc/core/core.c | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/drivers/mmc/core/core.c
|
||||
+++ b/drivers/mmc/core/core.c
|
||||
@@ -1366,6 +1366,8 @@ void mmc_power_off(struct mmc_host *host
|
||||
|
||||
mmc_pwrseq_power_off(host);
|
||||
|
||||
+ mmc_set_initial_signal_voltage(host);
|
||||
+
|
||||
host->ios.clock = 0;
|
||||
host->ios.vdd = 0;
|
||||
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
From 0cdf37b755feda3aaceb749750613b5e563e7284 Mon Sep 17 00:00:00 2001
|
||||
From: Andrew Powers-Holmes <aholmes@omnom.net>
|
||||
Date: Sat, 12 Nov 2022 22:41:26 +1100
|
||||
Subject: [PATCH] arm64: dts: rockchip: rk356x: Fix PCIe register and
|
||||
range mappings
|
||||
|
||||
The register and range mappings for the PCIe controller in Rockchip's
|
||||
RK356x SoCs are incorrect. Replace them with corrected values from the
|
||||
vendor BSP sources, updated to match current DT schema.
|
||||
|
||||
Tested-by: Ondrej Jirman <megi@xff.cz>
|
||||
Signed-off-by: Andrew Powers-Holmes <aholmes@omnom.net>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 14 ++++++++------
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 7 ++++---
|
||||
2 files changed, 12 insertions(+), 9 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -952,7 +952,7 @@
|
||||
compatible = "rockchip,rk3568-pcie";
|
||||
reg = <0x3 0xc0000000 0x0 0x00400000>,
|
||||
<0x0 0xfe260000 0x0 0x00010000>,
|
||||
- <0x3 0x3f000000 0x0 0x01000000>;
|
||||
+ <0x0 0xf4000000 0x0 0x00100000>;
|
||||
reg-names = "dbi", "apb", "config";
|
||||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
|
||||
@@ -982,8 +982,9 @@
|
||||
phys = <&combphy2 PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy";
|
||||
power-domains = <&power RK3568_PD_PIPE>;
|
||||
- ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000
|
||||
- 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>;
|
||||
+ ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
|
||||
+ <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
|
||||
+ <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
|
||||
resets = <&cru SRST_PCIE20_POWERUP>;
|
||||
reset-names = "pipe";
|
||||
#address-cells = <3>;
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
--- a/arch/arm64/Kconfig
|
||||
+++ b/arch/arm64/Kconfig
|
||||
@@ -1132,6 +1132,14 @@ config SOCIONEXT_SYNQUACER_PREITS
|
||||
|
||||
If unsure, say Y.
|
||||
|
||||
+config ROCKCHIP_ERRATUM_114514
|
||||
+ bool "Rockchip RK3568 force no_local_cache"
|
||||
+ default y
|
||||
+ help
|
||||
+ They consider this as a SoC implement design instead of a bug.
|
||||
+
|
||||
+ If unsure, say Y.
|
||||
+
|
||||
endmenu # "ARM errata workarounds via the alternatives framework"
|
||||
|
||||
choice
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
@@ -64,7 +64,7 @@
|
||||
compatible = "rockchip,rk3568-pcie";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
- bus-range = <0x0 0xf>;
|
||||
+ bus-range = <0x10 0x1f>;
|
||||
clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
|
||||
<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
|
||||
<&cru CLK_PCIE30X1_AUX_NDFT>;
|
||||
@@ -87,7 +87,7 @@
|
||||
num-ib-windows = <6>;
|
||||
num-ob-windows = <2>;
|
||||
max-link-speed = <3>;
|
||||
- msi-map = <0x0 &gic 0x1000 0x1000>;
|
||||
+ msi-map = <0x1000 &its 0x1000 0x1000>;
|
||||
num-lanes = <1>;
|
||||
phys = <&pcie30phy>;
|
||||
phy-names = "pcie-phy";
|
||||
@@ -116,7 +116,7 @@
|
||||
compatible = "rockchip,rk3568-pcie";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
- bus-range = <0x0 0xf>;
|
||||
+ bus-range = <0x20 0x2f>;
|
||||
clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
|
||||
<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
|
||||
<&cru CLK_PCIE30X2_AUX_NDFT>;
|
||||
@@ -139,7 +139,7 @@
|
||||
num-ib-windows = <6>;
|
||||
num-ob-windows = <2>;
|
||||
max-link-speed = <3>;
|
||||
- msi-map = <0x0 &gic 0x2000 0x1000>;
|
||||
+ msi-map = <0x2000 &its 0x2000 0x1000>;
|
||||
num-lanes = <2>;
|
||||
phys = <&pcie30phy>;
|
||||
phy-names = "pcie-phy";
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -315,14 +315,21 @@
|
||||
|
||||
gic: interrupt-controller@fd400000 {
|
||||
compatible = "arm,gic-v3";
|
||||
+ #interrupt-cells = <3>;
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <2>;
|
||||
+ ranges;
|
||||
+ interrupt-controller;
|
||||
+
|
||||
reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
|
||||
- <0x0 0xfd460000 0 0x80000>; /* GICR */
|
||||
+ <0x0 0xfd460000 0 0xc0000>; /* GICR */
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- interrupt-controller;
|
||||
- #interrupt-cells = <3>;
|
||||
- mbi-alias = <0x0 0xfd410000>;
|
||||
- mbi-ranges = <296 24>;
|
||||
- msi-controller;
|
||||
+ its: interrupt-controller@fd440000 {
|
||||
+ compatible = "arm,gic-v3-its";
|
||||
+ msi-controller;
|
||||
+ #msi-cells = <1>;
|
||||
+ reg = <0x0 0xfd440000 0x0 0x20000>;
|
||||
+ };
|
||||
};
|
||||
|
||||
usb_host0_ehci: usb@fd800000 {
|
||||
@@ -977,7 +984,7 @@
|
||||
num-ib-windows = <6>;
|
||||
num-ob-windows = <2>;
|
||||
max-link-speed = <2>;
|
||||
- msi-map = <0x0 &gic 0x0 0x1000>;
|
||||
+ msi-map = <0x0 &its 0x0 0x1000>;
|
||||
num-lanes = <1>;
|
||||
phys = <&combphy2 PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy";
|
||||
|
|
@ -0,0 +1,198 @@
|
|||
From 536378a084c6a4148141e132efee2fa9a464e007 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Thu, 3 Jun 2021 11:36:35 -0400
|
||||
Subject: [PATCH] irqchip: gic-v3: add hackaround for rk3568 its
|
||||
|
||||
---
|
||||
drivers/irqchip/irq-gic-v3-its.c | 70 +++++++++++++++++++++++++++++---
|
||||
1 file changed, 65 insertions(+), 5 deletions(-)
|
||||
|
||||
--- a/drivers/irqchip/irq-gic-v3-its.c
|
||||
+++ b/drivers/irqchip/irq-gic-v3-its.c
|
||||
@@ -45,6 +45,7 @@
|
||||
|
||||
#define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)
|
||||
#define RDIST_FLAGS_RD_TABLES_PREALLOCATED (1 << 1)
|
||||
+#define RDIST_FLAGS_FORCE_NO_LOCAL_CACHE (1 << 2)
|
||||
|
||||
#define RD_LOCAL_LPI_ENABLED BIT(0)
|
||||
#define RD_LOCAL_PENDTABLE_PREALLOCATED BIT(1)
|
||||
@@ -2178,6 +2179,11 @@ static struct page *its_allocate_prop_ta
|
||||
{
|
||||
struct page *prop_page;
|
||||
|
||||
+ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
|
||||
+ pr_err("ITS ALLOCATE PROP WORKAROUND\n");
|
||||
+ gfp_flags |= GFP_DMA;
|
||||
+ }
|
||||
+
|
||||
prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
|
||||
if (!prop_page)
|
||||
return NULL;
|
||||
@@ -2301,6 +2307,7 @@ static int its_setup_baser(struct its_no
|
||||
u32 alloc_pages, psz;
|
||||
struct page *page;
|
||||
void *base;
|
||||
+ gfp_t gfp_flags;
|
||||
|
||||
psz = baser->psz;
|
||||
alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
|
||||
@@ -2312,7 +2319,10 @@ static int its_setup_baser(struct its_no
|
||||
order = get_order(GITS_BASER_PAGES_MAX * psz);
|
||||
}
|
||||
|
||||
- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
|
||||
+ gfp_flags = GFP_KERNEL | __GFP_ZERO;
|
||||
+ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
|
||||
+ gfp_flags |= GFP_DMA;
|
||||
+ page = alloc_pages_node(its->numa_node, gfp_flags, order);
|
||||
if (!page)
|
||||
return -ENOMEM;
|
||||
|
||||
@@ -2359,6 +2369,13 @@ retry_baser:
|
||||
its_write_baser(its, baser, val);
|
||||
tmp = baser->val;
|
||||
|
||||
+ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
|
||||
+ if (tmp & GITS_BASER_SHAREABILITY_MASK)
|
||||
+ tmp &= ~GITS_BASER_SHAREABILITY_MASK;
|
||||
+ else
|
||||
+ gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
|
||||
+ }
|
||||
+
|
||||
if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
|
||||
/*
|
||||
* Shareability didn't stick. Just use
|
||||
@@ -2941,6 +2958,10 @@ static struct page *its_allocate_pending
|
||||
{
|
||||
struct page *pend_page;
|
||||
|
||||
+ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
|
||||
+ gfp_flags |= GFP_DMA;
|
||||
+ }
|
||||
+
|
||||
pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
|
||||
get_order(LPI_PENDBASE_SZ));
|
||||
if (!pend_page)
|
||||
@@ -3096,6 +3117,9 @@ static void its_cpu_init_lpis(void)
|
||||
gicr_write_propbaser(val, rbase + GICR_PROPBASER);
|
||||
tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
|
||||
|
||||
+ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
|
||||
+ tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
|
||||
+
|
||||
if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
|
||||
if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
|
||||
/*
|
||||
@@ -3120,6 +3144,9 @@ static void its_cpu_init_lpis(void)
|
||||
gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
|
||||
tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
|
||||
|
||||
+ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
|
||||
+ tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
|
||||
+
|
||||
if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
|
||||
/*
|
||||
* The HW reports non-shareable, we must remove the
|
||||
@@ -3283,7 +3310,12 @@ static bool its_alloc_table_entry(struct
|
||||
|
||||
/* Allocate memory for 2nd level table */
|
||||
if (!table[idx]) {
|
||||
- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
|
||||
+ gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO;
|
||||
+ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
|
||||
+ gfp_flags |= GFP_DMA;
|
||||
+ }
|
||||
+
|
||||
+ page = alloc_pages_node(its->numa_node, gfp_flags,
|
||||
get_order(baser->psz));
|
||||
if (!page)
|
||||
return false;
|
||||
@@ -3372,6 +3404,7 @@ static struct its_device *its_create_dev
|
||||
int nr_lpis;
|
||||
int nr_ites;
|
||||
int sz;
|
||||
+ gfp_t gfp_flags;
|
||||
|
||||
if (!its_alloc_device_table(its, dev_id))
|
||||
return NULL;
|
||||
@@ -3379,7 +3412,11 @@ static struct its_device *its_create_dev
|
||||
if (WARN_ON(!is_power_of_2(nvecs)))
|
||||
nvecs = roundup_pow_of_two(nvecs);
|
||||
|
||||
- dev = kzalloc(sizeof(*dev), GFP_KERNEL);
|
||||
+ gfp_flags = GFP_KERNEL;
|
||||
+ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
|
||||
+ gfp_flags |= GFP_DMA;
|
||||
+
|
||||
+ dev = kzalloc(sizeof(*dev), gfp_flags);
|
||||
/*
|
||||
* Even if the device wants a single LPI, the ITT must be
|
||||
* sized as a power of two (and you need at least one bit...).
|
||||
@@ -3387,7 +3424,7 @@ static struct its_device *its_create_dev
|
||||
nr_ites = max(2, nvecs);
|
||||
sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
|
||||
sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
|
||||
- itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
|
||||
+ itt = kzalloc_node(sz, gfp_flags, its->numa_node);
|
||||
if (alloc_lpis) {
|
||||
lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
|
||||
if (lpi_map)
|
||||
@@ -4710,6 +4747,13 @@ static bool __maybe_unused its_enable_qu
|
||||
return true;
|
||||
}
|
||||
|
||||
+static bool __maybe_unused its_enable_quirk_rk3568(void *data)
|
||||
+{
|
||||
+ gic_rdists->flags |= RDIST_FLAGS_FORCE_NO_LOCAL_CACHE;
|
||||
+
|
||||
+ return true;
|
||||
+}
|
||||
+
|
||||
static const struct gic_quirk its_quirks[] = {
|
||||
#ifdef CONFIG_CAVIUM_ERRATUM_22375
|
||||
{
|
||||
@@ -4756,6 +4800,14 @@ static const struct gic_quirk its_quirks
|
||||
.init = its_enable_quirk_hip07_161600802,
|
||||
},
|
||||
#endif
|
||||
+#ifdef CONFIG_ROCKCHIP_ERRATUM_114514
|
||||
+ {
|
||||
+ .desc = "ITS: Rockchip erratum 114514",
|
||||
+ .iidr = 0x0201743b,
|
||||
+ .mask = 0xffffffff,
|
||||
+ .init = its_enable_quirk_rk3568,
|
||||
+ },
|
||||
+#endif
|
||||
{
|
||||
}
|
||||
};
|
||||
@@ -5011,6 +5063,7 @@ static int __init its_probe_one(struct r
|
||||
struct page *page;
|
||||
u32 ctlr;
|
||||
int err;
|
||||
+ gfp_t gfp_flags;
|
||||
|
||||
its_base = its_map_one(res, &err);
|
||||
if (!its_base)
|
||||
@@ -5064,7 +5117,9 @@ static int __init its_probe_one(struct r
|
||||
|
||||
its->numa_node = numa_node;
|
||||
|
||||
- page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
|
||||
+ gfp_flags = GFP_KERNEL | __GFP_ZERO | GFP_DMA;
|
||||
+
|
||||
+ page = alloc_pages_node(its->numa_node, gfp_flags,
|
||||
get_order(ITS_CMD_QUEUE_SZ));
|
||||
if (!page) {
|
||||
err = -ENOMEM;
|
||||
@@ -5095,6 +5150,9 @@ static int __init its_probe_one(struct r
|
||||
gits_write_cbaser(baser, its->base + GITS_CBASER);
|
||||
tmp = gits_read_cbaser(its->base + GITS_CBASER);
|
||||
|
||||
+ if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
|
||||
+ tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
|
||||
+
|
||||
if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
|
||||
if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
|
||||
/*
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
@@ -173,11 +173,13 @@
|
||||
clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
|
||||
<&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
|
||||
<&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
|
||||
- <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
|
||||
+ <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
|
||||
+ <&cru PCLK_XPCS>;
|
||||
clock-names = "stmmaceth", "mac_clk_rx",
|
||||
"mac_clk_tx", "clk_mac_refout",
|
||||
"aclk_mac", "pclk_mac",
|
||||
- "clk_mac_speed", "ptp_ref";
|
||||
+ "clk_mac_speed", "ptp_ref",
|
||||
+ "pclk_xpcs";
|
||||
resets = <&cru SRST_A_GMAC0>;
|
||||
reset-names = "stmmaceth";
|
||||
rockchip,grf = <&grf>;
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -376,6 +376,12 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ xpcs: syscon@fda00000 {
|
||||
+ compatible = "rockchip,rk3568-xpcs", "syscon";
|
||||
+ reg = <0x0 0xfda00000 0x0 0x200000>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
pmugrf: syscon@fdc20000 {
|
||||
compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xfdc20000 0x0 0x10000>;
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
From b4aeb93e697e4dbe2d336d01290e92e98acfd83c Mon Sep 17 00:00:00 2001
|
||||
From: jensen <jensenhuang@friendlyarm.com>
|
||||
Date: Sat, 15 Oct 2022 18:47:24 +0800
|
||||
Subject: [PATCH] rfkill: gpio: add of_match_table support
|
||||
|
||||
Signed-off-by: jensen <jensenhuang@friendlyarm.com>
|
||||
---
|
||||
net/rfkill/rfkill-gpio.c | 8 ++++++++
|
||||
1 file changed, 8 insertions(+)
|
||||
|
||||
--- a/net/rfkill/rfkill-gpio.c
|
||||
+++ b/net/rfkill/rfkill-gpio.c
|
||||
@@ -156,6 +156,13 @@ static const struct acpi_device_id rfkil
|
||||
};
|
||||
MODULE_DEVICE_TABLE(acpi, rfkill_acpi_match);
|
||||
#endif
|
||||
+#ifdef CONFIG_OF
|
||||
+static struct of_device_id rfkill_gpio_of_match[] = {
|
||||
+ { .compatible = "rfkill-gpio" },
|
||||
+ { },
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, rfkill_gpio_of_match);
|
||||
+#endif
|
||||
|
||||
static struct platform_driver rfkill_gpio_driver = {
|
||||
.probe = rfkill_gpio_probe,
|
||||
@@ -163,6 +170,7 @@ static struct platform_driver rfkill_gpi
|
||||
.driver = {
|
||||
.name = "rfkill_gpio",
|
||||
.acpi_match_table = ACPI_PTR(rfkill_acpi_match),
|
||||
+ .of_match_table = of_match_ptr(rfkill_gpio_of_match),
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
From 3b7eb946b1d640d684a921e53e1e50985ab7eb89 Mon Sep 17 00:00:00 2001
|
||||
From: QiuSimons <45143996+QiuSimons@users.noreply.github.com>
|
||||
Date: Tue, 4 Aug 2020 20:17:53 +0800
|
||||
Subject: [PATCH] rockchip: rk3328: add i2c0 controller for nanopi r2s
|
||||
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 4 ++++
|
||||
1 files changed, 4 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
@@ -173,6 +173,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&i2c0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
|
||||
|
|
@ -0,0 +1,442 @@
|
|||
From 0f989817a4c1d2c3d196d550ff05cda98bc91324 Mon Sep 17 00:00:00 2001
|
||||
From: Julian Pidancet <julian@pidancet.net>
|
||||
Date: Sun, 23 Jan 2022 16:34:08 +0100
|
||||
Subject: [PATCH v2] rockchip: rk3328: add support for FriendlyARM NanoPi NEO3
|
||||
|
||||
This patch adds support for FriendlyARM NanoPi NEO3
|
||||
|
||||
Soc: RockChip RK3328
|
||||
RAM: 1GB/2GB DDR4
|
||||
LAN: 10/100/1000M Ethernet with unique MAC
|
||||
USB Host: 1x USB3.0 Type A and 2x USB2.0 on 2.54mm pin header
|
||||
MicroSD: x 1 for system boot and storage
|
||||
LED: Power LED x 1, System LED x 1
|
||||
Key: User Button x 1
|
||||
Fan: 2 Pin JST ZH 1.5mm Connector for 5V Fan
|
||||
GPIO: 26 pin-header, include I2C, UART, SPI, I2S, GPIO
|
||||
Power: 5V/1A, via Type-C or GPIO
|
||||
|
||||
Signed-off-by: Julian Pidancet <julian@pidancet.net>
|
||||
---
|
||||
|
||||
This is another shot at previous work submitted by Marty Jones
|
||||
<mj8263788@gmail.com> (https://lore.kernel.org/linux-arm-kernel/20201228152836.02795e09.mj8263788@gmail.com/),
|
||||
which is now a year old.
|
||||
|
||||
v2: Following up on Robin Murphy's comments, the NEO3 DTS is now
|
||||
standalone and no longer includes the nanopi R2S one. The lan_led and
|
||||
wan_len nodes have been removed, and the sys_led node has been renamed
|
||||
to status_led in accordance with the board schematics.
|
||||
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../boot/dts/rockchip/rk3328-nanopi-neo3.dts | 396 ++++++++++++++++++
|
||||
2 files changed, 397 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-neo3.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-neo3.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-neo3.dts
|
||||
@@ -0,0 +1,394 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
|
||||
+ * Copyright (c) 2022 Julian Pidancet <julian@pidancet.net>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include <dt-bindings/input/input.h>
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include "rk3328.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "FriendlyElec NanoPi NEO3";
|
||||
+ compatible = "friendlyarm,nanopi-neo3", "rockchip,rk3328";
|
||||
+
|
||||
+ aliases {
|
||||
+ led-boot = &status_led;
|
||||
+ led-failsafe = &status_led;
|
||||
+ led-running = &status_led;
|
||||
+ led-upgrade = &status_led;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ stdout-path = "serial2:1500000n8";
|
||||
+ };
|
||||
+
|
||||
+ gmac_clk: gmac-clock {
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <125000000>;
|
||||
+ clock-output-names = "gmac_clkin";
|
||||
+ #clock-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ keys {
|
||||
+ compatible = "gpio-keys";
|
||||
+ pinctrl-0 = <&reset_button_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+
|
||||
+ reset {
|
||||
+ label = "reset";
|
||||
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
|
||||
+ linux,code = <KEY_RESTART>;
|
||||
+ debounce-interval = <50>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+ pinctrl-0 = <&status_led_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+
|
||||
+ status_led: led-0 {
|
||||
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||
+ label = "nanopi-neo3:green:status";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_io_sdio: sdmmcio-regulator {
|
||||
+ compatible = "regulator-gpio";
|
||||
+ enable-active-high;
|
||||
+ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-0 = <&sdio_vcc_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ regulator-name = "vcc_io_sdio";
|
||||
+ regulator-always-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-settling-time-us = <5000>;
|
||||
+ regulator-type = "voltage";
|
||||
+ startup-delay-us = <2000>;
|
||||
+ states = <1800000 0x1>,
|
||||
+ <3300000 0x0>;
|
||||
+ vin-supply = <&vcc_io_33>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_sd: sdmmc-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
|
||||
+ pinctrl-0 = <&sdmmc0m1_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ regulator-name = "vcc_sd";
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vcc_io_33>;
|
||||
+ };
|
||||
+
|
||||
+ vdd_5v: vdd-5v {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vdd_5v";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_rtl8153: vcc-rtl8153-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&rtl8153_en_drv>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-name = "vcc_rtl8153";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ enable-active-high;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cpu0 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&cpu1 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&cpu2 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&cpu3 {
|
||||
+ cpu-supply = <&vdd_arm>;
|
||||
+};
|
||||
+
|
||||
+&display_subsystem {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&gmac2io {
|
||||
+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
|
||||
+ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
|
||||
+ clock_in_out = "input";
|
||||
+ phy-handle = <&rtl8211e>;
|
||||
+ phy-mode = "rgmii";
|
||||
+ phy-supply = <&vcc_io_33>;
|
||||
+ pinctrl-0 = <&rgmiim1_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+ rx_delay = <0x18>;
|
||||
+ snps,aal;
|
||||
+ tx_delay = <0x24>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ mdio {
|
||||
+ compatible = "snps,dwmac-mdio";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ rtl8211e: ethernet-phy@1 {
|
||||
+ reg = <1>;
|
||||
+ pinctrl-0 = <ð_phy_reset_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ reset-assert-us = <10000>;
|
||||
+ reset-deassert-us = <50000>;
|
||||
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2c1 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ rk805: pmic@18 {
|
||||
+ compatible = "rockchip,rk805";
|
||||
+ reg = <0x18>;
|
||||
+ interrupt-parent = <&gpio1>;
|
||||
+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ #clock-cells = <1>;
|
||||
+ clock-output-names = "xin32k", "rk805-clkout2";
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+ pinctrl-0 = <&pmic_int_l>;
|
||||
+ pinctrl-names = "default";
|
||||
+ rockchip,system-power-controller;
|
||||
+ wakeup-source;
|
||||
+
|
||||
+ vcc1-supply = <&vdd_5v>;
|
||||
+ vcc2-supply = <&vdd_5v>;
|
||||
+ vcc3-supply = <&vdd_5v>;
|
||||
+ vcc4-supply = <&vdd_5v>;
|
||||
+ vcc5-supply = <&vcc_io_33>;
|
||||
+ vcc6-supply = <&vdd_5v>;
|
||||
+
|
||||
+ regulators {
|
||||
+ vdd_log: DCDC_REG1 {
|
||||
+ regulator-name = "vdd_log";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1450000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1000000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_arm: DCDC_REG2 {
|
||||
+ regulator-name = "vdd_arm";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1450000>;
|
||||
+ regulator-ramp-delay = <12500>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <950000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_ddr: DCDC_REG3 {
|
||||
+ regulator-name = "vcc_ddr";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_io_33: DCDC_REG4 {
|
||||
+ regulator-name = "vcc_io_33";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_18: LDO_REG1 {
|
||||
+ regulator-name = "vcc_18";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc18_emmc: LDO_REG2 {
|
||||
+ regulator-name = "vcc18_emmc";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_10: LDO_REG3 {
|
||||
+ regulator-name = "vdd_10";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1000000>;
|
||||
+ regulator-max-microvolt = <1000000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1000000>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&io_domains {
|
||||
+ pmuio-supply = <&vcc_io_33>;
|
||||
+ vccio1-supply = <&vcc_io_33>;
|
||||
+ vccio2-supply = <&vcc18_emmc>;
|
||||
+ vccio3-supply = <&vcc_io_sdio>;
|
||||
+ vccio4-supply = <&vcc_18>;
|
||||
+ vccio5-supply = <&vcc_io_33>;
|
||||
+ vccio6-supply = <&vcc_io_33>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ button {
|
||||
+ reset_button_pin: reset-button-pin {
|
||||
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ ethernet-phy {
|
||||
+ eth_phy_reset_pin: eth-phy-reset-pin {
|
||||
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ status_led_pin: status-led-pin {
|
||||
+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmic {
|
||||
+ pmic_int_l: pmic-int-l {
|
||||
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ sd {
|
||||
+ sdio_vcc_pin: sdio-vcc-pin {
|
||||
+ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb {
|
||||
+ rtl8153_en_drv: rtl8153-en-drv {
|
||||
+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pwm2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc {
|
||||
+ bus-width = <4>;
|
||||
+ cap-sd-highspeed;
|
||||
+ disable-wp;
|
||||
+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
|
||||
+ pinctrl-names = "default";
|
||||
+ sd-uhs-sdr12;
|
||||
+ sd-uhs-sdr25;
|
||||
+ sd-uhs-sdr50;
|
||||
+ sd-uhs-sdr104;
|
||||
+ vmmc-supply = <&vcc_sd>;
|
||||
+ vqmmc-supply = <&vcc_io_sdio>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ rockchip,hw-tshut-mode = <0>;
|
||||
+ rockchip,hw-tshut-polarity = <0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy_host {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&u2phy_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb20_otg {
|
||||
+ status = "okay";
|
||||
+ dr_mode = "host";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usbdrd3 {
|
||||
+ dr_mode = "host";
|
||||
+ status = "okay";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ usb-eth@2 {
|
||||
+ compatible = "realtek,rtl8153";
|
||||
+ reg = <2>;
|
||||
+
|
||||
+ realtek,led-data = <0x87>;
|
||||
+ };
|
||||
+};
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -79,3 +79,15 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-so
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-photonicat.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-mrkaio-m68s.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-mrkaio-m68s-plus.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-opc-h66k.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-opc-h68k.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-opc-h69k.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-r66s.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-r68s.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -62,6 +62,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ro
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b-plus.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4c.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-king3399.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-mpc1903.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-h3399pc.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-dlfr100.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64-v2.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
From e5b5361651940ff5c0c1784dfd0130abec7ab535 Mon Sep 17 00:00:00 2001
|
||||
From: wevsty <ty@wevs.org>
|
||||
Date: Mon, 24 Aug 2020 02:27:11 +0800
|
||||
Subject: [PATCH] char: add support for rockchip hardware random number
|
||||
generator
|
||||
|
||||
This patch provides hardware random number generator support for all rockchip SOC.
|
||||
|
||||
rockchip-rng.c from https://github.com/rockchip-linux/kernel/blob/develop-4.4/drivers/char/hw_random/rockchip-rng.c
|
||||
|
||||
Signed-off-by: wevsty <ty@wevs.org>
|
||||
---
|
||||
|
||||
--- a/drivers/char/hw_random/Kconfig
|
||||
+++ b/drivers/char/hw_random/Kconfig
|
||||
@@ -372,6 +372,19 @@ config HW_RANDOM_STM32
|
||||
|
||||
If unsure, say N.
|
||||
|
||||
+config HW_RANDOM_ROCKCHIP
|
||||
+ tristate "Rockchip Random Number Generator support"
|
||||
+ depends on ARCH_ROCKCHIP
|
||||
+ default HW_RANDOM
|
||||
+ help
|
||||
+ This driver provides kernel-side support for the Random Number
|
||||
+ Generator hardware found on Rockchip cpus.
|
||||
+
|
||||
+ To compile this driver as a module, choose M here: the
|
||||
+ module will be called rockchip-rng.
|
||||
+
|
||||
+ If unsure, say Y.
|
||||
+
|
||||
config HW_RANDOM_PIC32
|
||||
tristate "Microchip PIC32 Random Number Generator support"
|
||||
depends on HW_RANDOM && MACH_PIC32
|
||||
--- a/drivers/char/hw_random/Makefile
|
||||
+++ b/drivers/char/hw_random/Makefile
|
||||
@@ -34,6 +34,7 @@ obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) +=
|
||||
obj-$(CONFIG_HW_RANDOM_ST) += st-rng.o
|
||||
obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o
|
||||
obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o
|
||||
+obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o
|
||||
obj-$(CONFIG_HW_RANDOM_PIC32) += pic32-rng.o
|
||||
obj-$(CONFIG_HW_RANDOM_MESON) += meson-rng.o
|
||||
obj-$(CONFIG_HW_RANDOM_CAVIUM) += cavium-rng.o cavium-rng-vf.o
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
From e5b5361651940ff5c0c1784dfd0130abec7ab535 Mon Sep 17 00:00:00 2001
|
||||
From: wevsty <ty@wevs.org>
|
||||
Date: Mon, 24 Aug 2020 02:27:11 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: add hardware random number generator
|
||||
for RK3328 and RK3399
|
||||
|
||||
Adding Hardware Random Number Generator Resources to the RK3328 and RK3399.
|
||||
|
||||
Signed-off-by: wevsty <ty@wevs.org>
|
||||
---
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
@@ -279,6 +279,17 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ rng: rng@ff060000 {
|
||||
+ compatible = "rockchip,cryptov1-rng";
|
||||
+ reg = <0x0 0xff060000 0x0 0x4000>;
|
||||
+
|
||||
+ clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>;
|
||||
+ clock-names = "clk_crypto", "hclk_crypto";
|
||||
+ assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>;
|
||||
+ assigned-clock-rates = <150000000>, <100000000>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
grf: syscon@ff100000 {
|
||||
compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xff100000 0x0 0x1000>;
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
|
||||
@@ -2043,6 +2043,16 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ rng: rng@ff8b8000 {
|
||||
+ compatible = "rockchip,cryptov1-rng";
|
||||
+ reg = <0x0 0xff8b8000 0x0 0x1000>;
|
||||
+ clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>;
|
||||
+ clock-names = "clk_crypto", "hclk_crypto";
|
||||
+ assigned-clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>;
|
||||
+ assigned-clock-rates = <150000000>, <100000000>;
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+
|
||||
gpu: gpu@ff9a0000 {
|
||||
compatible = "rockchip,rk3399-mali", "arm,mali-t860";
|
||||
reg = <0x0 0xff9a0000 0x0 0x10000>;
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
@@ -213,6 +213,16 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ rng: rng@fe388000 {
|
||||
+ compatible = "rockchip,cryptov2-rng";
|
||||
+ reg = <0x0 0xfe388000 0x0 0x2000>;
|
||||
+ clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
|
||||
+ clock-names = "clk_trng", "hclk_trng";
|
||||
+ resets = <&cru SRST_TRNG_NS>;
|
||||
+ reset-names = "reset";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
combphy0: phy@fe820000 {
|
||||
compatible = "rockchip,rk3568-naneng-combphy";
|
||||
reg = <0x0 0xfe820000 0x0 0x100>;
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
From fcd9629c05f373771e85920e1c1d0ab252617878 Mon Sep 17 00:00:00 2001
|
||||
From: hmz007 <hmz007@gmail.com>
|
||||
Date: Tue, 19 Nov 2019 13:53:25 +0800
|
||||
Subject: [PATCH] PM / devfreq: rockchip: add devfreq driver for rk3328 dmc
|
||||
|
||||
Signed-off-by: hmz007 <hmz007@gmail.com>
|
||||
---
|
||||
drivers/devfreq/Kconfig | 18 +-
|
||||
drivers/devfreq/Makefile | 1 +
|
||||
drivers/devfreq/rk3328_dmc.c | 846 +++++++++++++++++++++++++++++++++++
|
||||
3 files changed, 862 insertions(+), 3 deletions(-)
|
||||
create mode 100644 drivers/devfreq/rk3328_dmc.c
|
||||
|
||||
--- a/drivers/devfreq/Kconfig
|
||||
+++ b/drivers/devfreq/Kconfig
|
||||
@@ -130,6 +130,18 @@ config ARM_MEDIATEK_CCI_DEVFREQ
|
||||
buck voltages and update a proper CCI frequency. Use the notification
|
||||
to get the regulator status.
|
||||
|
||||
+config ARM_RK3328_DMC_DEVFREQ
|
||||
+ tristate "ARM RK3328 DMC DEVFREQ Driver"
|
||||
+ depends on ARCH_ROCKCHIP
|
||||
+ select DEVFREQ_EVENT_ROCKCHIP_DFI
|
||||
+ select DEVFREQ_GOV_SIMPLE_ONDEMAND
|
||||
+ select PM_DEVFREQ_EVENT
|
||||
+ select PM_OPP
|
||||
+ help
|
||||
+ This adds the DEVFREQ driver for the RK3328 DMC(Dynamic Memory Controller).
|
||||
+ It sets the frequency for the memory controller and reads the usage counts
|
||||
+ from hardware.
|
||||
+
|
||||
config ARM_RK3399_DMC_DEVFREQ
|
||||
tristate "ARM RK3399 DMC DEVFREQ Driver"
|
||||
depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
|
||||
--- a/drivers/devfreq/Makefile
|
||||
+++ b/drivers/devfreq/Makefile
|
||||
@@ -12,6 +12,7 @@ obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) +=
|
||||
obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o
|
||||
obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
|
||||
obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) += mtk-cci-devfreq.o
|
||||
+obj-$(CONFIG_ARM_RK3328_DMC_DEVFREQ) += rk3328_dmc.o
|
||||
obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
|
||||
obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o
|
||||
obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o
|
||||
|
|
@ -0,0 +1,210 @@
|
|||
From ce6d3614888e6358466f0e84e248177a6bca5258 Mon Sep 17 00:00:00 2001
|
||||
From: Tang Yun ping <typ@rock-chips.com>
|
||||
Date: Thu, 4 May 2017 20:49:58 +0800
|
||||
Subject: [PATCH] clk: rockchip: support setting ddr clock via SIP Version 2
|
||||
APIs
|
||||
|
||||
commit 764e893ee82321938fc6f4349e9e7caf06a04410 rockchip.
|
||||
|
||||
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
|
||||
Signed-off-by: hmz007 <hmz007@gmail.com>
|
||||
---
|
||||
drivers/clk/rockchip/clk-ddr.c | 130 ++++++++++++++++++++++++++++
|
||||
drivers/clk/rockchip/clk-rk3328.c | 7 +-
|
||||
drivers/clk/rockchip/clk.h | 3 +-
|
||||
include/soc/rockchip/rockchip_sip.h | 11 +++
|
||||
4 files changed, 147 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/drivers/clk/rockchip/clk-ddr.c
|
||||
+++ b/drivers/clk/rockchip/clk-ddr.c
|
||||
@@ -87,6 +87,133 @@ static const struct clk_ops rockchip_ddr
|
||||
.get_parent = rockchip_ddrclk_get_parent,
|
||||
};
|
||||
|
||||
+/* See v4.4/include/dt-bindings/display/rk_fb.h */
|
||||
+#define SCREEN_NULL 0
|
||||
+#define SCREEN_HDMI 6
|
||||
+
|
||||
+static inline int rk_drm_get_lcdc_type(void)
|
||||
+{
|
||||
+ return SCREEN_NULL;
|
||||
+}
|
||||
+
|
||||
+struct share_params {
|
||||
+ u32 hz;
|
||||
+ u32 lcdc_type;
|
||||
+ u32 vop;
|
||||
+ u32 vop_dclk_mode;
|
||||
+ u32 sr_idle_en;
|
||||
+ u32 addr_mcu_el3;
|
||||
+ /*
|
||||
+ * 1: need to wait flag1
|
||||
+ * 0: never wait flag1
|
||||
+ */
|
||||
+ u32 wait_flag1;
|
||||
+ /*
|
||||
+ * 1: need to wait flag1
|
||||
+ * 0: never wait flag1
|
||||
+ */
|
||||
+ u32 wait_flag0;
|
||||
+ u32 complt_hwirq;
|
||||
+ /* if need, add parameter after */
|
||||
+};
|
||||
+
|
||||
+struct rockchip_ddrclk_data {
|
||||
+ u32 inited_flag;
|
||||
+ void __iomem *share_memory;
|
||||
+};
|
||||
+
|
||||
+static struct rockchip_ddrclk_data ddr_data;
|
||||
+
|
||||
+static void rockchip_ddrclk_data_init(void)
|
||||
+{
|
||||
+ struct arm_smccc_res res;
|
||||
+
|
||||
+ arm_smccc_smc(ROCKCHIP_SIP_SHARE_MEM,
|
||||
+ 1, SHARE_PAGE_TYPE_DDR, 0,
|
||||
+ 0, 0, 0, 0, &res);
|
||||
+
|
||||
+ if (!res.a0) {
|
||||
+ ddr_data.share_memory = (void __iomem *)ioremap(res.a1, 1<<12);
|
||||
+ ddr_data.inited_flag = 1;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static int rockchip_ddrclk_sip_set_rate_v2(struct clk_hw *hw,
|
||||
+ unsigned long drate,
|
||||
+ unsigned long prate)
|
||||
+{
|
||||
+ struct share_params *p;
|
||||
+ struct arm_smccc_res res;
|
||||
+
|
||||
+ if (!ddr_data.inited_flag)
|
||||
+ rockchip_ddrclk_data_init();
|
||||
+
|
||||
+ p = (struct share_params *)ddr_data.share_memory;
|
||||
+
|
||||
+ p->hz = drate;
|
||||
+ p->lcdc_type = rk_drm_get_lcdc_type();
|
||||
+ p->wait_flag1 = 1;
|
||||
+ p->wait_flag0 = 1;
|
||||
+
|
||||
+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
|
||||
+ SHARE_PAGE_TYPE_DDR, 0,
|
||||
+ ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE,
|
||||
+ 0, 0, 0, 0, &res);
|
||||
+
|
||||
+ if ((int)res.a1 == -6) {
|
||||
+ pr_err("%s: timeout, drate = %lumhz\n", __func__, drate/1000000);
|
||||
+ /* TODO: rockchip_dmcfreq_wait_complete(); */
|
||||
+ }
|
||||
+
|
||||
+ return res.a0;
|
||||
+}
|
||||
+
|
||||
+static unsigned long rockchip_ddrclk_sip_recalc_rate_v2
|
||||
+ (struct clk_hw *hw, unsigned long parent_rate)
|
||||
+{
|
||||
+ struct arm_smccc_res res;
|
||||
+
|
||||
+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
|
||||
+ SHARE_PAGE_TYPE_DDR, 0,
|
||||
+ ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE,
|
||||
+ 0, 0, 0, 0, &res);
|
||||
+ if (!res.a0)
|
||||
+ return res.a1;
|
||||
+ else
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static long rockchip_ddrclk_sip_round_rate_v2(struct clk_hw *hw,
|
||||
+ unsigned long rate,
|
||||
+ unsigned long *prate)
|
||||
+{
|
||||
+ struct share_params *p;
|
||||
+ struct arm_smccc_res res;
|
||||
+
|
||||
+ if (!ddr_data.inited_flag)
|
||||
+ rockchip_ddrclk_data_init();
|
||||
+
|
||||
+ p = (struct share_params *)ddr_data.share_memory;
|
||||
+
|
||||
+ p->hz = rate;
|
||||
+
|
||||
+ arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
|
||||
+ SHARE_PAGE_TYPE_DDR, 0,
|
||||
+ ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE,
|
||||
+ 0, 0, 0, 0, &res);
|
||||
+ if (!res.a0)
|
||||
+ return res.a1;
|
||||
+ else
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct clk_ops rockchip_ddrclk_sip_ops_v2 = {
|
||||
+ .recalc_rate = rockchip_ddrclk_sip_recalc_rate_v2,
|
||||
+ .set_rate = rockchip_ddrclk_sip_set_rate_v2,
|
||||
+ .round_rate = rockchip_ddrclk_sip_round_rate_v2,
|
||||
+ .get_parent = rockchip_ddrclk_get_parent,
|
||||
+};
|
||||
+
|
||||
struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
|
||||
const char *const *parent_names,
|
||||
u8 num_parents, int mux_offset,
|
||||
@@ -114,6 +241,9 @@ struct clk *rockchip_clk_register_ddrclk
|
||||
case ROCKCHIP_DDRCLK_SIP:
|
||||
init.ops = &rockchip_ddrclk_sip_ops;
|
||||
break;
|
||||
+ case ROCKCHIP_DDRCLK_SIP_V2:
|
||||
+ init.ops = &rockchip_ddrclk_sip_ops_v2;
|
||||
+ break;
|
||||
default:
|
||||
pr_err("%s: unsupported ddrclk type %d\n", __func__, ddr_flag);
|
||||
kfree(ddrclk);
|
||||
--- a/drivers/clk/rockchip/clk-rk3328.c
|
||||
+++ b/drivers/clk/rockchip/clk-rk3328.c
|
||||
@@ -315,9 +315,10 @@ static struct rockchip_clk_branch rk3328
|
||||
RK3328_CLKGATE_CON(14), 1, GFLAGS),
|
||||
|
||||
/* PD_DDR */
|
||||
- COMPOSITE(0, "clk_ddr", mux_ddrphy_p, CLK_IGNORE_UNUSED,
|
||||
- RK3328_CLKSEL_CON(3), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
|
||||
- RK3328_CLKGATE_CON(0), 4, GFLAGS),
|
||||
+ COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
|
||||
+ RK3328_CLKSEL_CON(3), 8, 2, 0, 3,
|
||||
+ ROCKCHIP_DDRCLK_SIP_V2),
|
||||
+
|
||||
GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IGNORE_UNUSED,
|
||||
RK3328_CLKGATE_CON(18), 6, GFLAGS),
|
||||
GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
|
||||
--- a/drivers/clk/rockchip/clk.h
|
||||
+++ b/drivers/clk/rockchip/clk.h
|
||||
@@ -418,7 +418,8 @@ struct clk *rockchip_clk_register_mmc(co
|
||||
* DDRCLK flags, including method of setting the rate
|
||||
* ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
|
||||
*/
|
||||
-#define ROCKCHIP_DDRCLK_SIP BIT(0)
|
||||
+#define ROCKCHIP_DDRCLK_SIP 0x01
|
||||
+#define ROCKCHIP_DDRCLK_SIP_V2 0x03
|
||||
|
||||
struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
|
||||
const char *const *parent_names,
|
||||
--- a/include/soc/rockchip/rockchip_sip.h
|
||||
+++ b/include/soc/rockchip/rockchip_sip.h
|
||||
@@ -16,5 +16,16 @@
|
||||
#define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ 0x06
|
||||
#define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM 0x07
|
||||
#define ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD 0x08
|
||||
+#define ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION 0x08
|
||||
+
|
||||
+#define ROCKCHIP_SIP_SHARE_MEM 0x82000009
|
||||
+
|
||||
+/* Share mem page types */
|
||||
+typedef enum {
|
||||
+ SHARE_PAGE_TYPE_INVALID = 0,
|
||||
+ SHARE_PAGE_TYPE_UARTDBG,
|
||||
+ SHARE_PAGE_TYPE_DDR,
|
||||
+ SHARE_PAGE_TYPE_MAX,
|
||||
+} share_page_type_t;
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,662 @@
|
|||
From 4db93c6dad0c71750b86163df2fdb21c35f00d9a Mon Sep 17 00:00:00 2001
|
||||
From: hmz007 <hmz007@gmail.com>
|
||||
Date: Tue, 19 Nov 2019 12:49:48 +0800
|
||||
Subject: [PATCH] PM / devfreq: rockchip-dfi: add more soc support
|
||||
|
||||
Signed-off-by: hmz007 <hmz007@gmail.com>
|
||||
---
|
||||
drivers/devfreq/event/rockchip-dfi.c | 554 ++++++++++++++++++++++++---
|
||||
1 file changed, 505 insertions(+), 49 deletions(-)
|
||||
|
||||
--- a/drivers/devfreq/event/rockchip-dfi.c
|
||||
+++ b/drivers/devfreq/event/rockchip-dfi.c
|
||||
@@ -18,25 +18,66 @@
|
||||
#include <linux/list.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
-#include <soc/rockchip/rk3399_grf.h>
|
||||
-
|
||||
-#define RK3399_DMC_NUM_CH 2
|
||||
+#define PX30_PMUGRF_OS_REG2 0x208
|
||||
|
||||
+#define RK3128_GRF_SOC_CON0 0x140
|
||||
+#define RK3128_GRF_OS_REG1 0x1cc
|
||||
+#define RK3128_GRF_DFI_WRNUM 0x220
|
||||
+#define RK3128_GRF_DFI_RDNUM 0x224
|
||||
+#define RK3128_GRF_DFI_TIMERVAL 0x22c
|
||||
+#define RK3128_DDR_MONITOR_EN ((1 << (16 + 6)) + (1 << 6))
|
||||
+#define RK3128_DDR_MONITOR_DISB ((1 << (16 + 6)) + (0 << 6))
|
||||
+
|
||||
+#define RK3288_PMU_SYS_REG2 0x9c
|
||||
+#define RK3288_GRF_SOC_CON4 0x254
|
||||
+#define RK3288_GRF_SOC_STATUS(n) (0x280 + (n) * 4)
|
||||
+#define RK3288_DFI_EN (0x30003 << 14)
|
||||
+#define RK3288_DFI_DIS (0x30000 << 14)
|
||||
+#define RK3288_LPDDR_SEL (0x10001 << 13)
|
||||
+#define RK3288_DDR3_SEL (0x10000 << 13)
|
||||
+
|
||||
+#define RK3328_GRF_OS_REG2 0x5d0
|
||||
+
|
||||
+#define RK3368_GRF_DDRC0_CON0 0x600
|
||||
+#define RK3368_GRF_SOC_STATUS5 0x494
|
||||
+#define RK3368_GRF_SOC_STATUS6 0x498
|
||||
+#define RK3368_GRF_SOC_STATUS8 0x4a0
|
||||
+#define RK3368_GRF_SOC_STATUS9 0x4a4
|
||||
+#define RK3368_GRF_SOC_STATUS10 0x4a8
|
||||
+#define RK3368_DFI_EN (0x30003 << 5)
|
||||
+#define RK3368_DFI_DIS (0x30000 << 5)
|
||||
+
|
||||
+#define MAX_DMC_NUM_CH 2
|
||||
+#define READ_DRAMTYPE_INFO(n) (((n) >> 13) & 0x7)
|
||||
+#define READ_CH_INFO(n) (((n) >> 28) & 0x3)
|
||||
/* DDRMON_CTRL */
|
||||
-#define DDRMON_CTRL 0x04
|
||||
-#define CLR_DDRMON_CTRL (0x1f0000 << 0)
|
||||
-#define LPDDR4_EN (0x10001 << 4)
|
||||
-#define HARDWARE_EN (0x10001 << 3)
|
||||
-#define LPDDR3_EN (0x10001 << 2)
|
||||
-#define SOFTWARE_EN (0x10001 << 1)
|
||||
-#define SOFTWARE_DIS (0x10000 << 1)
|
||||
-#define TIME_CNT_EN (0x10001 << 0)
|
||||
+#define DDRMON_CTRL 0x04
|
||||
+#define CLR_DDRMON_CTRL (0x3f0000 << 0)
|
||||
+#define DDR4_EN (0x10001 << 5)
|
||||
+#define LPDDR4_EN (0x10001 << 4)
|
||||
+#define HARDWARE_EN (0x10001 << 3)
|
||||
+#define LPDDR2_3_EN (0x10001 << 2)
|
||||
+#define SOFTWARE_EN (0x10001 << 1)
|
||||
+#define SOFTWARE_DIS (0x10000 << 1)
|
||||
+#define TIME_CNT_EN (0x10001 << 0)
|
||||
|
||||
#define DDRMON_CH0_COUNT_NUM 0x28
|
||||
#define DDRMON_CH0_DFI_ACCESS_NUM 0x2c
|
||||
#define DDRMON_CH1_COUNT_NUM 0x3c
|
||||
#define DDRMON_CH1_DFI_ACCESS_NUM 0x40
|
||||
|
||||
+/* pmu grf */
|
||||
+#define PMUGRF_OS_REG2 0x308
|
||||
+
|
||||
+enum {
|
||||
+ DDR4 = 0,
|
||||
+ DDR3 = 3,
|
||||
+ LPDDR2 = 5,
|
||||
+ LPDDR3 = 6,
|
||||
+ LPDDR4 = 7,
|
||||
+ UNUSED = 0xFF
|
||||
+};
|
||||
+
|
||||
struct dmc_usage {
|
||||
u32 access;
|
||||
u32 total;
|
||||
@@ -50,33 +91,261 @@ struct dmc_usage {
|
||||
struct rockchip_dfi {
|
||||
struct devfreq_event_dev *edev;
|
||||
struct devfreq_event_desc *desc;
|
||||
- struct dmc_usage ch_usage[RK3399_DMC_NUM_CH];
|
||||
+ struct dmc_usage ch_usage[MAX_DMC_NUM_CH];
|
||||
struct device *dev;
|
||||
void __iomem *regs;
|
||||
struct regmap *regmap_pmu;
|
||||
+ struct regmap *regmap_grf;
|
||||
+ struct regmap *regmap_pmugrf;
|
||||
struct clk *clk;
|
||||
+ u32 dram_type;
|
||||
+ /*
|
||||
+ * available mask, 1: available, 0: not available
|
||||
+ * each bit represent a channel
|
||||
+ */
|
||||
+ u32 ch_msk;
|
||||
+};
|
||||
+
|
||||
+static void rk3128_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+
|
||||
+ regmap_write(info->regmap_grf,
|
||||
+ RK3128_GRF_SOC_CON0,
|
||||
+ RK3128_DDR_MONITOR_EN);
|
||||
+}
|
||||
+
|
||||
+static void rk3128_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+
|
||||
+ regmap_write(info->regmap_grf,
|
||||
+ RK3128_GRF_SOC_CON0,
|
||||
+ RK3128_DDR_MONITOR_DISB);
|
||||
+}
|
||||
+
|
||||
+static int rk3128_dfi_disable(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ rk3128_dfi_stop_hardware_counter(edev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3128_dfi_enable(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ rk3128_dfi_start_hardware_counter(edev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3128_dfi_set_event(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3128_dfi_get_event(struct devfreq_event_dev *edev,
|
||||
+ struct devfreq_event_data *edata)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+ unsigned long flags;
|
||||
+ u32 dfi_wr, dfi_rd, dfi_timer;
|
||||
+
|
||||
+ local_irq_save(flags);
|
||||
+
|
||||
+ rk3128_dfi_stop_hardware_counter(edev);
|
||||
+
|
||||
+ regmap_read(info->regmap_grf, RK3128_GRF_DFI_WRNUM, &dfi_wr);
|
||||
+ regmap_read(info->regmap_grf, RK3128_GRF_DFI_RDNUM, &dfi_rd);
|
||||
+ regmap_read(info->regmap_grf, RK3128_GRF_DFI_TIMERVAL, &dfi_timer);
|
||||
+
|
||||
+ edata->load_count = (dfi_wr + dfi_rd) * 4;
|
||||
+ edata->total_count = dfi_timer;
|
||||
+
|
||||
+ rk3128_dfi_start_hardware_counter(edev);
|
||||
+
|
||||
+ local_irq_restore(flags);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct devfreq_event_ops rk3128_dfi_ops = {
|
||||
+ .disable = rk3128_dfi_disable,
|
||||
+ .enable = rk3128_dfi_enable,
|
||||
+ .get_event = rk3128_dfi_get_event,
|
||||
+ .set_event = rk3128_dfi_set_event,
|
||||
+};
|
||||
+
|
||||
+static void rk3288_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+
|
||||
+ regmap_write(info->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_EN);
|
||||
+}
|
||||
+
|
||||
+static void rk3288_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+
|
||||
+ regmap_write(info->regmap_grf, RK3288_GRF_SOC_CON4, RK3288_DFI_DIS);
|
||||
+}
|
||||
+
|
||||
+static int rk3288_dfi_disable(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ rk3288_dfi_stop_hardware_counter(edev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3288_dfi_enable(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ rk3288_dfi_start_hardware_counter(edev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3288_dfi_set_event(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3288_dfi_get_busier_ch(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+ u32 tmp, max = 0;
|
||||
+ u32 i, busier_ch = 0;
|
||||
+ u32 rd_count, wr_count, total_count;
|
||||
+
|
||||
+ rk3288_dfi_stop_hardware_counter(edev);
|
||||
+
|
||||
+ /* Find out which channel is busier */
|
||||
+ for (i = 0; i < MAX_DMC_NUM_CH; i++) {
|
||||
+ if (!(info->ch_msk & BIT(i)))
|
||||
+ continue;
|
||||
+ regmap_read(info->regmap_grf,
|
||||
+ RK3288_GRF_SOC_STATUS(11 + i * 4), &wr_count);
|
||||
+ regmap_read(info->regmap_grf,
|
||||
+ RK3288_GRF_SOC_STATUS(12 + i * 4), &rd_count);
|
||||
+ regmap_read(info->regmap_grf,
|
||||
+ RK3288_GRF_SOC_STATUS(14 + i * 4), &total_count);
|
||||
+ info->ch_usage[i].access = (wr_count + rd_count) * 4;
|
||||
+ info->ch_usage[i].total = total_count;
|
||||
+ tmp = info->ch_usage[i].access;
|
||||
+ if (tmp > max) {
|
||||
+ busier_ch = i;
|
||||
+ max = tmp;
|
||||
+ }
|
||||
+ }
|
||||
+ rk3288_dfi_start_hardware_counter(edev);
|
||||
+
|
||||
+ return busier_ch;
|
||||
+}
|
||||
+
|
||||
+static int rk3288_dfi_get_event(struct devfreq_event_dev *edev,
|
||||
+ struct devfreq_event_data *edata)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+ int busier_ch;
|
||||
+ unsigned long flags;
|
||||
+
|
||||
+ local_irq_save(flags);
|
||||
+ busier_ch = rk3288_dfi_get_busier_ch(edev);
|
||||
+ local_irq_restore(flags);
|
||||
+
|
||||
+ edata->load_count = info->ch_usage[busier_ch].access;
|
||||
+ edata->total_count = info->ch_usage[busier_ch].total;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct devfreq_event_ops rk3288_dfi_ops = {
|
||||
+ .disable = rk3288_dfi_disable,
|
||||
+ .enable = rk3288_dfi_enable,
|
||||
+ .get_event = rk3288_dfi_get_event,
|
||||
+ .set_event = rk3288_dfi_set_event,
|
||||
+};
|
||||
+
|
||||
+static void rk3368_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+
|
||||
+ regmap_write(info->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_EN);
|
||||
+}
|
||||
+
|
||||
+static void rk3368_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+
|
||||
+ regmap_write(info->regmap_grf, RK3368_GRF_DDRC0_CON0, RK3368_DFI_DIS);
|
||||
+}
|
||||
+
|
||||
+static int rk3368_dfi_disable(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ rk3368_dfi_stop_hardware_counter(edev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3368_dfi_enable(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ rk3368_dfi_start_hardware_counter(edev);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3368_dfi_set_event(struct devfreq_event_dev *edev)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk3368_dfi_get_event(struct devfreq_event_dev *edev,
|
||||
+ struct devfreq_event_data *edata)
|
||||
+{
|
||||
+ struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
+ unsigned long flags;
|
||||
+ u32 dfi0_wr, dfi0_rd, dfi1_wr, dfi1_rd, dfi_timer;
|
||||
+
|
||||
+ local_irq_save(flags);
|
||||
+
|
||||
+ rk3368_dfi_stop_hardware_counter(edev);
|
||||
+
|
||||
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS5, &dfi0_wr);
|
||||
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS6, &dfi0_rd);
|
||||
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS9, &dfi1_wr);
|
||||
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS10, &dfi1_rd);
|
||||
+ regmap_read(info->regmap_grf, RK3368_GRF_SOC_STATUS8, &dfi_timer);
|
||||
+
|
||||
+ edata->load_count = (dfi0_wr + dfi0_rd + dfi1_wr + dfi1_rd) * 2;
|
||||
+ edata->total_count = dfi_timer;
|
||||
+
|
||||
+ rk3368_dfi_start_hardware_counter(edev);
|
||||
+
|
||||
+ local_irq_restore(flags);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct devfreq_event_ops rk3368_dfi_ops = {
|
||||
+ .disable = rk3368_dfi_disable,
|
||||
+ .enable = rk3368_dfi_enable,
|
||||
+ .get_event = rk3368_dfi_get_event,
|
||||
+ .set_event = rk3368_dfi_set_event,
|
||||
};
|
||||
|
||||
static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
|
||||
{
|
||||
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
void __iomem *dfi_regs = info->regs;
|
||||
- u32 val;
|
||||
- u32 ddr_type;
|
||||
-
|
||||
- /* get ddr type */
|
||||
- regmap_read(info->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
|
||||
- ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
|
||||
- RK3399_PMUGRF_DDRTYPE_MASK;
|
||||
|
||||
/* clear DDRMON_CTRL setting */
|
||||
writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
|
||||
|
||||
/* set ddr type to dfi */
|
||||
- if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3)
|
||||
- writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
|
||||
- else if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4)
|
||||
+ if (info->dram_type == LPDDR3 || info->dram_type == LPDDR2)
|
||||
+ writel_relaxed(LPDDR2_3_EN, dfi_regs + DDRMON_CTRL);
|
||||
+ else if (info->dram_type == LPDDR4)
|
||||
writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
|
||||
+ else if (info->dram_type == DDR4)
|
||||
+ writel_relaxed(DDR4_EN, dfi_regs + DDRMON_CTRL);
|
||||
|
||||
/* enable count, use software mode */
|
||||
writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);
|
||||
@@ -100,12 +369,22 @@ static int rockchip_dfi_get_busier_ch(st
|
||||
rockchip_dfi_stop_hardware_counter(edev);
|
||||
|
||||
/* Find out which channel is busier */
|
||||
- for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
|
||||
- info->ch_usage[i].access = readl_relaxed(dfi_regs +
|
||||
- DDRMON_CH0_DFI_ACCESS_NUM + i * 20) * 4;
|
||||
+ for (i = 0; i < MAX_DMC_NUM_CH; i++) {
|
||||
+ if (!(info->ch_msk & BIT(i)))
|
||||
+ continue;
|
||||
+
|
||||
info->ch_usage[i].total = readl_relaxed(dfi_regs +
|
||||
DDRMON_CH0_COUNT_NUM + i * 20);
|
||||
- tmp = info->ch_usage[i].access;
|
||||
+
|
||||
+ /* LPDDR4 BL = 16,other DDR type BL = 8 */
|
||||
+ tmp = readl_relaxed(dfi_regs +
|
||||
+ DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
|
||||
+ if (info->dram_type == LPDDR4)
|
||||
+ tmp *= 8;
|
||||
+ else
|
||||
+ tmp *= 4;
|
||||
+ info->ch_usage[i].access = tmp;
|
||||
+
|
||||
if (tmp > max) {
|
||||
busier_ch = i;
|
||||
max = tmp;
|
||||
@@ -121,7 +400,8 @@ static int rockchip_dfi_disable(struct d
|
||||
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
|
||||
rockchip_dfi_stop_hardware_counter(edev);
|
||||
- clk_disable_unprepare(info->clk);
|
||||
+ if (info->clk)
|
||||
+ clk_disable_unprepare(info->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -131,10 +411,13 @@ static int rockchip_dfi_enable(struct de
|
||||
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
int ret;
|
||||
|
||||
- ret = clk_prepare_enable(info->clk);
|
||||
- if (ret) {
|
||||
- dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ret);
|
||||
- return ret;
|
||||
+ if (info->clk) {
|
||||
+ ret = clk_prepare_enable(info->clk);
|
||||
+ if (ret) {
|
||||
+ dev_err(&edev->dev, "failed to enable dfi clk: %d\n",
|
||||
+ ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
}
|
||||
|
||||
rockchip_dfi_start_hardware_counter(edev);
|
||||
@@ -151,8 +434,11 @@ static int rockchip_dfi_get_event(struct
|
||||
{
|
||||
struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
|
||||
int busier_ch;
|
||||
+ unsigned long flags;
|
||||
|
||||
+ local_irq_save(flags);
|
||||
busier_ch = rockchip_dfi_get_busier_ch(edev);
|
||||
+ local_irq_restore(flags);
|
||||
|
||||
edata->load_count = info->ch_usage[busier_ch].access;
|
||||
edata->total_count = info->ch_usage[busier_ch].total;
|
||||
@@ -167,22 +453,116 @@ static const struct devfreq_event_ops ro
|
||||
.set_event = rockchip_dfi_set_event,
|
||||
};
|
||||
|
||||
-static const struct of_device_id rockchip_dfi_id_match[] = {
|
||||
- { .compatible = "rockchip,rk3399-dfi" },
|
||||
- { },
|
||||
-};
|
||||
-MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);
|
||||
+static __init int px30_dfi_init(struct platform_device *pdev,
|
||||
+ struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc)
|
||||
+{
|
||||
+ struct device_node *np = pdev->dev.of_node, *node;
|
||||
+ struct resource *res;
|
||||
+ u32 val;
|
||||
|
||||
-static int rockchip_dfi_probe(struct platform_device *pdev)
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ data->regs = devm_ioremap_resource(&pdev->dev, res);
|
||||
+ if (IS_ERR(data->regs))
|
||||
+ return PTR_ERR(data->regs);
|
||||
+
|
||||
+ node = of_parse_phandle(np, "rockchip,pmugrf", 0);
|
||||
+ if (node) {
|
||||
+ data->regmap_pmugrf = syscon_node_to_regmap(node);
|
||||
+ if (IS_ERR(data->regmap_pmugrf))
|
||||
+ return PTR_ERR(data->regmap_pmugrf);
|
||||
+ }
|
||||
+
|
||||
+ regmap_read(data->regmap_pmugrf, PX30_PMUGRF_OS_REG2, &val);
|
||||
+ data->dram_type = READ_DRAMTYPE_INFO(val);
|
||||
+ data->ch_msk = 1;
|
||||
+ data->clk = NULL;
|
||||
+
|
||||
+ desc->ops = &rockchip_dfi_ops;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static __init int rk3128_dfi_init(struct platform_device *pdev,
|
||||
+ struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc)
|
||||
{
|
||||
- struct device *dev = &pdev->dev;
|
||||
- struct rockchip_dfi *data;
|
||||
- struct devfreq_event_desc *desc;
|
||||
struct device_node *np = pdev->dev.of_node, *node;
|
||||
|
||||
- data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
|
||||
- if (!data)
|
||||
- return -ENOMEM;
|
||||
+ node = of_parse_phandle(np, "rockchip,grf", 0);
|
||||
+ if (node) {
|
||||
+ data->regmap_grf = syscon_node_to_regmap(node);
|
||||
+ if (IS_ERR(data->regmap_grf))
|
||||
+ return PTR_ERR(data->regmap_grf);
|
||||
+ }
|
||||
+
|
||||
+ desc->ops = &rk3128_dfi_ops;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static __init int rk3288_dfi_init(struct platform_device *pdev,
|
||||
+ struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc)
|
||||
+{
|
||||
+ struct device_node *np = pdev->dev.of_node, *node;
|
||||
+ u32 val;
|
||||
+
|
||||
+ node = of_parse_phandle(np, "rockchip,pmu", 0);
|
||||
+ if (node) {
|
||||
+ data->regmap_pmu = syscon_node_to_regmap(node);
|
||||
+ if (IS_ERR(data->regmap_pmu))
|
||||
+ return PTR_ERR(data->regmap_pmu);
|
||||
+ }
|
||||
+
|
||||
+ node = of_parse_phandle(np, "rockchip,grf", 0);
|
||||
+ if (node) {
|
||||
+ data->regmap_grf = syscon_node_to_regmap(node);
|
||||
+ if (IS_ERR(data->regmap_grf))
|
||||
+ return PTR_ERR(data->regmap_grf);
|
||||
+ }
|
||||
+
|
||||
+ regmap_read(data->regmap_pmu, RK3288_PMU_SYS_REG2, &val);
|
||||
+ data->dram_type = READ_DRAMTYPE_INFO(val);
|
||||
+ data->ch_msk = READ_CH_INFO(val);
|
||||
+
|
||||
+ if (data->dram_type == DDR3)
|
||||
+ regmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4,
|
||||
+ RK3288_DDR3_SEL);
|
||||
+ else
|
||||
+ regmap_write(data->regmap_grf, RK3288_GRF_SOC_CON4,
|
||||
+ RK3288_LPDDR_SEL);
|
||||
+
|
||||
+ desc->ops = &rk3288_dfi_ops;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static __init int rk3368_dfi_init(struct platform_device *pdev,
|
||||
+ struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc)
|
||||
+{
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+
|
||||
+ if (!dev->parent || !dev->parent->of_node)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ data->regmap_grf = syscon_node_to_regmap(dev->parent->of_node);
|
||||
+ if (IS_ERR(data->regmap_grf))
|
||||
+ return PTR_ERR(data->regmap_grf);
|
||||
+
|
||||
+ desc->ops = &rk3368_dfi_ops;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static __init int rockchip_dfi_init(struct platform_device *pdev,
|
||||
+ struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc)
|
||||
+{
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ struct device_node *np = pdev->dev.of_node, *node;
|
||||
+ u32 val;
|
||||
|
||||
data->regs = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(data->regs))
|
||||
@@ -201,21 +581,97 @@ static int rockchip_dfi_probe(struct pla
|
||||
if (IS_ERR(data->regmap_pmu))
|
||||
return PTR_ERR(data->regmap_pmu);
|
||||
}
|
||||
- data->dev = dev;
|
||||
+
|
||||
+ regmap_read(data->regmap_pmu, PMUGRF_OS_REG2, &val);
|
||||
+ data->dram_type = READ_DRAMTYPE_INFO(val);
|
||||
+ data->ch_msk = READ_CH_INFO(val);
|
||||
+
|
||||
+ desc->ops = &rockchip_dfi_ops;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static __init int rk3328_dfi_init(struct platform_device *pdev,
|
||||
+ struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc)
|
||||
+{
|
||||
+ struct device_node *np = pdev->dev.of_node, *node;
|
||||
+ struct resource *res;
|
||||
+ u32 val;
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ data->regs = devm_ioremap_resource(&pdev->dev, res);
|
||||
+ if (IS_ERR(data->regs))
|
||||
+ return PTR_ERR(data->regs);
|
||||
+
|
||||
+ node = of_parse_phandle(np, "rockchip,grf", 0);
|
||||
+ if (node) {
|
||||
+ data->regmap_grf = syscon_node_to_regmap(node);
|
||||
+ if (IS_ERR(data->regmap_grf))
|
||||
+ return PTR_ERR(data->regmap_grf);
|
||||
+ }
|
||||
+
|
||||
+ regmap_read(data->regmap_grf, RK3328_GRF_OS_REG2, &val);
|
||||
+ data->dram_type = READ_DRAMTYPE_INFO(val);
|
||||
+ data->ch_msk = 1;
|
||||
+ data->clk = NULL;
|
||||
+
|
||||
+ desc->ops = &rockchip_dfi_ops;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id rockchip_dfi_id_match[] = {
|
||||
+ { .compatible = "rockchip,px30-dfi", .data = px30_dfi_init },
|
||||
+ { .compatible = "rockchip,rk1808-dfi", .data = px30_dfi_init },
|
||||
+ { .compatible = "rockchip,rk3128-dfi", .data = rk3128_dfi_init },
|
||||
+ { .compatible = "rockchip,rk3288-dfi", .data = rk3288_dfi_init },
|
||||
+ { .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init },
|
||||
+ { .compatible = "rockchip,rk3368-dfi", .data = rk3368_dfi_init },
|
||||
+ { .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init },
|
||||
+ { },
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);
|
||||
+
|
||||
+static int rockchip_dfi_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ struct rockchip_dfi *data;
|
||||
+ struct devfreq_event_desc *desc;
|
||||
+ struct device_node *np = pdev->dev.of_node;
|
||||
+ const struct of_device_id *match;
|
||||
+ int (*init)(struct platform_device *pdev, struct rockchip_dfi *data,
|
||||
+ struct devfreq_event_desc *desc);
|
||||
+
|
||||
+ data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
|
||||
+ if (!data)
|
||||
+ return -ENOMEM;
|
||||
|
||||
desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
|
||||
if (!desc)
|
||||
return -ENOMEM;
|
||||
|
||||
- desc->ops = &rockchip_dfi_ops;
|
||||
+ match = of_match_node(rockchip_dfi_id_match, pdev->dev.of_node);
|
||||
+ if (match) {
|
||||
+ init = match->data;
|
||||
+ if (init) {
|
||||
+ if (init(pdev, data, desc))
|
||||
+ return -EINVAL;
|
||||
+ } else {
|
||||
+ return 0;
|
||||
+ }
|
||||
+ } else {
|
||||
+ return 0;
|
||||
+ }
|
||||
+
|
||||
desc->driver_data = data;
|
||||
desc->name = np->name;
|
||||
data->desc = desc;
|
||||
+ data->dev = dev;
|
||||
|
||||
- data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
|
||||
+ data->edev = devm_devfreq_event_add_edev(dev, desc);
|
||||
if (IS_ERR(data->edev)) {
|
||||
- dev_err(&pdev->dev,
|
||||
- "failed to add devfreq-event device\n");
|
||||
+ dev_err(dev, "failed to add devfreq-event device\n");
|
||||
return PTR_ERR(data->edev);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
From f9ae6e992d3d9e80357fee7d65ba0fe2dd37ae1f Mon Sep 17 00:00:00 2001
|
||||
From: hmz007 <hmz007@gmail.com>
|
||||
Date: Tue, 19 Nov 2019 14:21:51 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: rk3328: add dfi node
|
||||
|
||||
Signed-off-by: hmz007 <hmz007@gmail.com>
|
||||
[adjusted commit title]
|
||||
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 7 +++++++
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
@@ -1023,6 +1023,13 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ dfi: dfi@ff790000 {
|
||||
+ reg = <0x00 0xff790000 0x00 0x400>;
|
||||
+ compatible = "rockchip,rk3328-dfi";
|
||||
+ rockchip,grf = <&grf>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
gic: interrupt-controller@ff811000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
|
|
@ -0,0 +1,126 @@
|
|||
From f9ae6e992d3d9e80357fee7d65ba0fe2dd37ae1f Mon Sep 17 00:00:00 2001
|
||||
From: hmz007 <hmz007@gmail.com>
|
||||
Date: Tue, 19 Nov 2019 14:21:51 +0800
|
||||
Subject: [PATCH] arm64: dts: nanopi-r2: add rk3328-dmc relate node
|
||||
|
||||
Signed-off-by: hmz007 <hmz007@gmail.com>
|
||||
---
|
||||
.../rockchip/rk3328-dram-default-timing.dtsi | 311 ++++++++++++++++++
|
||||
.../dts/rockchip/rk3328-nanopi-r2-common.dtsi | 85 ++++-
|
||||
include/dt-bindings/clock/rockchip-ddr.h | 63 ++++
|
||||
include/dt-bindings/memory/rk3328-dram.h | 159 +++++++++
|
||||
4 files changed, 617 insertions(+), 1 deletion(-)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-dram-default-timing.dtsi
|
||||
create mode 100644 include/dt-bindings/clock/rockchip-ddr.h
|
||||
create mode 100644 include/dt-bindings/memory/rk3328-dram.h
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
@@ -7,6 +7,7 @@
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
+#include "rk3328-dram-default-timing.dtsi"
|
||||
#include "rk3328.dtsi"
|
||||
|
||||
/ {
|
||||
@@ -121,6 +122,72 @@
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vdd_5v>;
|
||||
};
|
||||
+
|
||||
+ dmc: dmc {
|
||||
+ compatible = "rockchip,rk3328-dmc";
|
||||
+ devfreq-events = <&dfi>;
|
||||
+ center-supply = <&vdd_log>;
|
||||
+ clocks = <&cru SCLK_DDRCLK>;
|
||||
+ clock-names = "dmc_clk";
|
||||
+ operating-points-v2 = <&dmc_opp_table>;
|
||||
+ ddr_timing = <&ddr_timing>;
|
||||
+ upthreshold = <40>;
|
||||
+ downdifferential = <20>;
|
||||
+ auto-min-freq = <786000>;
|
||||
+ auto-freq-en = <0>;
|
||||
+ #cooling-cells = <2>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ ddr_power_model: ddr_power_model {
|
||||
+ compatible = "ddr_power_model";
|
||||
+ dynamic-power-coefficient = <120>;
|
||||
+ static-power-coefficient = <200>;
|
||||
+ ts = <32000 4700 (-80) 2>;
|
||||
+ thermal-zone = "soc-thermal";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ dmc_opp_table: dmc-opp-table {
|
||||
+ compatible = "operating-points-v2";
|
||||
+
|
||||
+ rockchip,leakage-voltage-sel = <
|
||||
+ 1 10 0
|
||||
+ 11 254 1
|
||||
+ >;
|
||||
+ nvmem-cells = <&logic_leakage>;
|
||||
+ nvmem-cell-names = "ddr_leakage";
|
||||
+
|
||||
+ opp-786000000 {
|
||||
+ opp-hz = /bits/ 64 <786000000>;
|
||||
+ opp-microvolt = <1075000>;
|
||||
+ opp-microvolt-L0 = <1075000>;
|
||||
+ opp-microvolt-L1 = <1050000>;
|
||||
+ };
|
||||
+ opp-798000000 {
|
||||
+ opp-hz = /bits/ 64 <798000000>;
|
||||
+ opp-microvolt = <1075000>;
|
||||
+ opp-microvolt-L0 = <1075000>;
|
||||
+ opp-microvolt-L1 = <1050000>;
|
||||
+ };
|
||||
+ opp-840000000 {
|
||||
+ opp-hz = /bits/ 64 <840000000>;
|
||||
+ opp-microvolt = <1075000>;
|
||||
+ opp-microvolt-L0 = <1075000>;
|
||||
+ opp-microvolt-L1 = <1050000>;
|
||||
+ };
|
||||
+ opp-924000000 {
|
||||
+ opp-hz = /bits/ 64 <924000000>;
|
||||
+ opp-microvolt = <1100000>;
|
||||
+ opp-microvolt-L0 = <1100000>;
|
||||
+ opp-microvolt-L1 = <1075000>;
|
||||
+ };
|
||||
+ opp-1056000000 {
|
||||
+ opp-hz = /bits/ 64 <1056000000>;
|
||||
+ opp-microvolt = <1175000>;
|
||||
+ opp-microvolt-L0 = <1175000>;
|
||||
+ opp-microvolt-L1 = <1150000>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
@@ -139,6 +206,10 @@
|
||||
cpu-supply = <&vdd_arm>;
|
||||
};
|
||||
|
||||
+&dfi {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&display_subsystem {
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -206,6 +277,7 @@
|
||||
regulator-name = "vdd_log";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
+ regulator-init-microvolt = <1075000>;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1450000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
@@ -220,6 +292,7 @@
|
||||
regulator-name = "vdd_arm";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
+ regulator-init-microvolt = <1225000>;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1450000>;
|
||||
regulator-ramp-delay = <12500>;
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
|
||||
From: Leonidas P. Papadakos <papadakospan@gmail.com>
|
||||
Date: Fri, 1 Mar 2019 21:55:53 +0200
|
||||
Subject: [PATCH v2] arm64: dts: rockchip: add more cpu operating points for
|
||||
RK3328
|
||||
|
||||
This allows for greater max frequency on rk3328 boards,
|
||||
increasing performance.
|
||||
|
||||
It has been included in Armbian (a linux distibution for ARM boards)
|
||||
for a while now without any reported issues
|
||||
|
||||
https://github.com/armbian/build/blob/master/patch/kernel/rockchip64-default/enable-1392mhz-opp.patch
|
||||
https://github.com/armbian/build/blob/master/patch/kernel/rockchip64-default/enable-1512mhz-opp.patch
|
||||
|
||||
Signed-off-by: Leonidas P. Papadakos <papadakospan@gmail.com>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 15 +++++++++++++++
|
||||
1 files changed, 15 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
|
||||
@@ -140,6 +140,21 @@
|
||||
opp-microvolt = <1300000>;
|
||||
clock-latency-ns = <40000>;
|
||||
};
|
||||
+ opp-1392000000 {
|
||||
+ opp-hz = /bits/ 64 <1392000000>;
|
||||
+ opp-microvolt = <1350000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1512000000 {
|
||||
+ opp-hz = /bits/ 64 <1512000000>;
|
||||
+ opp-microvolt = <1400000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
+ opp-1608000000 {
|
||||
+ opp-hz = /bits/ 64 <1608000000>;
|
||||
+ opp-microvolt = <1450000>;
|
||||
+ clock-latency-ns = <40000>;
|
||||
+ };
|
||||
};
|
||||
|
||||
analog_sound: analog-sound {
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
From 04202df5cb497b1934c95211cf43784ef62245a4 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@immortalwrt.org>
|
||||
Date: Mon, 18 Oct 2021 12:47:30 +0800
|
||||
Subject: [PATCH] rockchip: rk3399: overclock to 2.2/1.8 GHz
|
||||
|
||||
It's stable enough to overclock cpu frequency to 2.2/1.8 GHz,
|
||||
and for better performance.
|
||||
|
||||
Co-development-by: gzelvis <gzelvis@gmail.com>
|
||||
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi | 16 ++++++++++++++++
|
||||
1 file changed, 16 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-opp.dtsi
|
||||
@@ -33,6 +33,14 @@
|
||||
opp-hz = /bits/ 64 <1416000000>;
|
||||
opp-microvolt = <1125000 1125000 1250000>;
|
||||
};
|
||||
+ opp06 {
|
||||
+ opp-hz = /bits/ 64 <1608000000>;
|
||||
+ opp-microvolt = <1225000>;
|
||||
+ };
|
||||
+ opp07 {
|
||||
+ opp-hz = /bits/ 64 <1800000000>;
|
||||
+ opp-microvolt = <1275000>;
|
||||
+ };
|
||||
};
|
||||
|
||||
cluster1_opp: opp-table-1 {
|
||||
@@ -72,6 +80,14 @@
|
||||
opp-hz = /bits/ 64 <1800000000>;
|
||||
opp-microvolt = <1200000 1200000 1250000>;
|
||||
};
|
||||
+ opp08 {
|
||||
+ opp-hz = /bits/ 64 <2016000000>;
|
||||
+ opp-microvolt = <1250000>;
|
||||
+ };
|
||||
+ opp09 {
|
||||
+ opp-hz = /bits/ 64 <2208000000>;
|
||||
+ opp-microvolt = <1325000>;
|
||||
+ };
|
||||
};
|
||||
|
||||
gpu_opp_table: opp-table-2 {
|
||||
7
build.sh
7
build.sh
|
|
@ -150,9 +150,10 @@ rm -rf "$OMR_TARGET/${OMR_KERNEL}/source/files" "$OMR_TARGET/${OMR_KERNEL}/sourc
|
|||
#rm -rf "$OMR_TARGET/${OMR_KERNEL}/source/target/linux/mediatek/patches-5.4"
|
||||
#rm -rf "$OMR_TARGET/${OMR_KERNEL}/source/package/boot/uboot-mediatek"
|
||||
#rm -rf "$OMR_TARGET/${OMR_KERNEL}/source/package/boot/arm-trusted-firmware-mediatek"
|
||||
[ "${OMR_KERNEL}" = "5.4" ] && rm -rf "$OMR_TARGET/${OMR_KERNEL}/source/tools/firmware-utils"
|
||||
echo "rm -rf $OMR_TARGET/${OMR_KERNEL}/source/package/boot/uboot-rockchip"
|
||||
rm -rf "${OMR_TARGET}/${OMR_KERNEL}/source/package/boot/uboot-rockchip"
|
||||
|
||||
[ "${OMR_KERNEL}" = "5.4" ] && rm -rf "$OMR_TARGET/${OMR_KERNEL}/source/tools/firmware-utils"
|
||||
if [ "$OMR_TARGET" != "rutx" ]; then
|
||||
# There is many customization to support rutx and this seems to break other ipq40xx, so dirty workaround for now
|
||||
[ -d "$OMR_TARGET/${OMR_KERNEL}/source/target/linux/ipq40xx" ] && mv -f "$OMR_TARGET/${OMR_KERNEL}/source/target/linux/ipq40xx" "$OMR_TARGET/${OMR_KERNEL}/source/target/linux/ipq40xx.old"
|
||||
|
|
@ -601,6 +602,8 @@ if [ "$OMR_KERNEL" = "5.4" ]; then
|
|||
if [ -f target/linux/mvebu/patches-5.4/022-arm64-dts-marvell-armada-37xx-Move-PCIe-max-link-spe.patch ]; then
|
||||
rm -f target/linux/mvebu/patches-5.4/022-arm64-dts-marvell-armada-37xx-Move-PCIe-max-link-spe.patch
|
||||
fi
|
||||
echo "rm -rf $OMR_TARGET/${OMR_KERNEL}/source/package/boot/uboot-rockchip"
|
||||
rm -rf "${OMR_TARGET}/${OMR_KERNEL}/source/package/boot/uboot-rockchip"
|
||||
#rm -f target/linux/rockchip/files/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts
|
||||
echo "CONFIG_VERSION_CODE=5.4" >> ".config"
|
||||
fi
|
||||
|
|
@ -680,7 +683,7 @@ if [ "$OMR_KERNEL" = "6.1" ]; then
|
|||
rm -f package/kernel/rtl8812au-ct/patches/003-*
|
||||
rm -f package/kernel/rtl8812au-ct/patches/004-*
|
||||
rm -f package/kernel/rtl8812au-ct/patches/100-api_update.patch
|
||||
rm -f target/linux/bcm27xx/modules/sound.mk
|
||||
#rm -f target/linux/bcm27xx/modules/sound.mk
|
||||
rm -f package/libs/elfutils/patches/101-no-fts.patch
|
||||
rm -f package/kernel/mwlwifi/patches/001-*
|
||||
rm -f package/kernel/mwlwifi/patches/002-*
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue