From 77292375d2c300a221a8204b82edec90437dced2 Mon Sep 17 00:00:00 2001 From: "Ycarus (Yannick Chabanois)" Date: Mon, 24 Apr 2023 21:35:02 +0200 Subject: [PATCH] Remove from 5.4 what is common --- .../Makefile | 81 - .../pack-firmware.sh | 60 - .../src/bin/rk35/rk3568_bl31_v1.28.elf | Bin 335928 -> 0 bytes .../src/trust.ini | 15 - .../arm-trusted-firmware-rockchip/Makefile | 49 - 5.4/package/boot/uboot-rockchip/Makefile | 304 -- ...hip-rk3568-add-boot-device-detection.patch | 43 - ...k3568-enable-automatic-power-savings.patch | 52 - ...le-rockchip-HACK-build-rk3568-images.patch | 47 - .../004-arm-dts-sync-rk3568-with-linux.patch | 3520 ----------------- ...ckchip-rk356x-HACK-fix-sdmmc-support.patch | 50 - ...rockchip-rk356x-add-quartz64-a-board.patch | 214 - ...p-rk_gpio-support-v2-gpio-controller.patch | 755 ---- ...8-rockchip-allow-sdmmc-at-full-speed.patch | 22 - ...ip-defconfig-add-gpio-v2-to-quartz64.patch | 25 - ...6x-enable-usb2-support-on-quartz64-a.patch | 97 - ...-rk356x-attempt-to-fix-ram-detection.patch | 173 - ...ync-rk3566-device-tree-with-mainline.patch | 1060 ----- ...rockchip-rk356x-add-bpi-r2-pro-board.patch | 795 ---- .../014-uboot-add-Radxa-ROCK-3A-board.patch | 690 ---- .../015-uboot-add-NanoPi-R5S-board.patch | 247 -- .../016-rk356x-ddr-fix-dbw-detect-bug.patch | 42 - ...7-gpio-rockchip-fix-building-for-spl.patch | 44 - ...lk-rockchip-rk3568-fix-reset-handler.patch | 28 - ...-rockchip-handle-bootrom-mode-in-spl.patch | 144 - ...CONFIG_USB_OHCI_NEW-et-al-to-Kconfig.patch | 282 -- ...104-mkimage-add-public-key-for-image.patch | 166 - .../105-Only-build-dtc-if-needed.patch | 125 - .../patches/106-no-kwbimage.patch | 10 - ...rock64pro-disable-CONFIG_USE_PREBOOT.patch | 27 - ...s-rockchip-Add-GuangMiao-G4C-support.patch | 740 ---- ...328-Add-support-for-Orangepi-R1-Plus.patch | 174 - ...Add-support-for-Orangepi-R1-Plus-LTS.patch | 146 - ...Add-support-for-FriendlyARM-NanoPi-R.patch | 184 - ...Add-support-for-FriendlyARM-NanoPi-R.patch | 113 - ...399-Add-support-for-Rongpin-king3399.patch | 68 - ...399-Add-support-for-Rocktech-MPC1903.patch | 784 ---- ...68-Add-support-for-ezpro_mrkaio-m68s.patch | 406 -- ...568-Add-support-for-hinlink-opc-h68k.patch | 415 -- ...k3568-Add-support-for-fastrhino-r66s.patch | 140 - ...ip-rk3568-Add-support-for-Station-P2.patch | 77 - ...hip-rk3568-Add-support-for-radxa_e25.patch | 154 - .../316-uboot-add-NanoPi-R5C-board.patch | 224 -- 43 files changed, 12792 deletions(-) delete mode 100644 5.4/package/boot/arm-trusted-firmware-rockchip-vendor/Makefile delete mode 100755 5.4/package/boot/arm-trusted-firmware-rockchip-vendor/pack-firmware.sh delete mode 100644 5.4/package/boot/arm-trusted-firmware-rockchip-vendor/src/bin/rk35/rk3568_bl31_v1.28.elf delete mode 100644 5.4/package/boot/arm-trusted-firmware-rockchip-vendor/src/trust.ini delete mode 100644 5.4/package/boot/arm-trusted-firmware-rockchip/Makefile delete mode 100644 5.4/package/boot/uboot-rockchip/Makefile delete mode 100644 5.4/package/boot/uboot-rockchip/patches/001-rockchip-rk3568-add-boot-device-detection.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/002-rockchip-rk3568-enable-automatic-power-savings.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/003-Makefile-rockchip-HACK-build-rk3568-images.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/004-arm-dts-sync-rk3568-with-linux.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/005-rockchip-rk356x-HACK-fix-sdmmc-support.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/006-rockchip-rk356x-add-quartz64-a-board.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/007-gpio-rockchip-rk_gpio-support-v2-gpio-controller.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/008-rockchip-allow-sdmmc-at-full-speed.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/009-rockchip-defconfig-add-gpio-v2-to-quartz64.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/010-rockchip-rk356x-enable-usb2-support-on-quartz64-a.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/011-rockchip-rk356x-attempt-to-fix-ram-detection.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/012-resync-rk3566-device-tree-with-mainline.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/013-rockchip-rk356x-add-bpi-r2-pro-board.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/014-uboot-add-Radxa-ROCK-3A-board.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/015-uboot-add-NanoPi-R5S-board.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/016-rk356x-ddr-fix-dbw-detect-bug.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/017-gpio-rockchip-fix-building-for-spl.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/018-clk-rockchip-rk3568-fix-reset-handler.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/019-rockchip-handle-bootrom-mode-in-spl.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/100-Convert-CONFIG_USB_OHCI_NEW-et-al-to-Kconfig.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/104-mkimage-add-public-key-for-image.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/105-Only-build-dtc-if-needed.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/106-no-kwbimage.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/203-rock64pro-disable-CONFIG_USE_PREBOOT.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/301-arm64-dts-rockchip-Add-GuangMiao-G4C-support.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/302-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/303-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus-LTS.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/304-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/305-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch delete mode 100755 5.4/package/boot/uboot-rockchip/patches/306-rockchip-rk3399-Add-support-for-Rongpin-king3399.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/307-rockchip-rk3399-Add-support-for-Rocktech-MPC1903.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/311-rockchip-rk3568-Add-support-for-ezpro_mrkaio-m68s.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/312-rockchip-rk3568-Add-support-for-hinlink-opc-h68k.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/313-rockchip-rk3568-Add-support-for-fastrhino-r66s.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/314-rockchip-rk3568-Add-support-for-Station-P2.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/315-rockchip-rk3568-Add-support-for-radxa_e25.patch delete mode 100644 5.4/package/boot/uboot-rockchip/patches/316-uboot-add-NanoPi-R5C-board.patch diff --git a/5.4/package/boot/arm-trusted-firmware-rockchip-vendor/Makefile b/5.4/package/boot/arm-trusted-firmware-rockchip-vendor/Makefile deleted file mode 100644 index 88e9c070..00000000 --- a/5.4/package/boot/arm-trusted-firmware-rockchip-vendor/Makefile +++ /dev/null @@ -1,81 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -# -# Copyright (C) 2022 ImmortalWrt.org - -include $(TOPDIR)/rules.mk - -PKG_NAME:=arm-trusted-firmware-rockchip-vendor -PKG_RELEASE:=$(AUTORELEASE) - -PKG_SOURCE_PROTO:=git -PKG_SOURCE_URL=https://github.com/rockchip-linux/rkbin.git -PKG_SOURCE_DATE:=2022-08-01 -PKG_SOURCE_VERSION:=b0c100f1a260d807df450019774993c761beb79d -PKG_MIRROR_HASH:=17723ac8f6ec446c759444ee29ba4fe544cebb3785e26d8e10c91c54b9df3f1a - -PKG_MAINTAINER:=Tianling Shen - -MAKE_PATH:=$(PKG_NAME) - -include $(INCLUDE_DIR)/package.mk - -define Package/arm-trusted-firmware-rockchip-vendor - SECTION:=boot - CATEGORY:=Boot Loaders - TITLE:=ARM Trusted Firmware for Rockchip -endef - -define Package/arm-trusted-firmware-rk3328 - $(Package/arm-trusted-firmware-rockchip-vendor) - DEPENDS:=@TARGET_rockchip_armv8 - VARIANT:=rk3328 -endef - -define Package/arm-trusted-firmware-rk3399 - $(Package/arm-trusted-firmware-rockchip-vendor) - DEPENDS:=@TARGET_rockchip_armv8 - VARIANT:=rk3399 -endef - -define Package/arm-trusted-firmware-rk3568 - $(Package/arm-trusted-firmware-rockchip-vendor) - DEPENDS:=@TARGET_rockchip_armv8 - VARIANT:=rk3568 -endef - -define Package/arm-trusted-firmware-rk3588 - $(Package/arm-trusted-firmware-rockchip-vendor) - DEPENDS:=@TARGET_rockchip_armv8 - VARIANT:=rk3588 -endef - -define Build/Configure - $(SED) 's,$$$$(PKG_BUILD_DIR),$(PKG_BUILD_DIR),g' $(PKG_BUILD_DIR)/trust.ini - $(SED) 's,$$$$(VARIANT),$(BUILD_VARIANT),g' $(PKG_BUILD_DIR)/trust.ini - $(call Build/Configure/Default) -endef - -define Build/Compile - $(CURDIR)/pack-firmware.sh build $(BUILD_VARIANT) '$(PKG_BUILD_DIR)' -endef - -define Build/InstallDev - $(CURDIR)/pack-firmware.sh install $(BUILD_VARIANT) '$(PKG_BUILD_DIR)' '$(STAGING_DIR_IMAGE)' -endef - -define Package/arm-trusted-firmware-rk3328/install -endef - -define Package/arm-trusted-firmware-rk3399/install -endef - -define Package/arm-trusted-firmware-rk3568/install -endef - -define Package/arm-trusted-firmware-rk3588/install -endef - -$(eval $(call BuildPackage,arm-trusted-firmware-rk3328)) -$(eval $(call BuildPackage,arm-trusted-firmware-rk3399)) -$(eval $(call BuildPackage,arm-trusted-firmware-rk3568)) -$(eval $(call BuildPackage,arm-trusted-firmware-rk3588)) diff --git a/5.4/package/boot/arm-trusted-firmware-rockchip-vendor/pack-firmware.sh b/5.4/package/boot/arm-trusted-firmware-rockchip-vendor/pack-firmware.sh deleted file mode 100755 index 6dfb8917..00000000 --- a/5.4/package/boot/arm-trusted-firmware-rockchip-vendor/pack-firmware.sh +++ /dev/null @@ -1,60 +0,0 @@ -#!/bin/bash -# Copyright (C) 2021 ImmortalWrt.org - -ACTION="$1" -VARIANT="$2" -PKG_BUILD_DIR="$3" -STAGING_DIR_IMAGE="$4" - -case "$VARIANT" in -"rk3328") - ATF="rk33/rk322xh_bl31_v1.49.elf" - DDR="rk33/rk3328_ddr_333MHz_v1.19.bin" - LOADER="rk33/rk322xh_miniloader_v2.50.bin" - ;; -"rk3399") - ATF="rk33/rk3399_bl31_v1.35.elf" - DDR="rk33/rk3399_ddr_800MHz_v1.27.bin" - LOADER="rk33/rk3399_miniloader_v1.26.bin" - ;; -"rk3568") - ATF="rk35/rk3568_bl31_v1.28.elf" - DDR="rk35/rk3568_ddr_1560MHz_v1.13.bin" - ;; -"rk3588") - ATF="rk35/rk3588_bl31_v1.27.elf" - DDR="rk35/rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.08.bin" - ;; -*) - echo -e "Not compatible with your platform: $VARIANT." - exit 1 - ;; -esac - -set -x -if [ "$ACTION" == "build" ]; then - case "$VARIANT" in - rk33*) - "$PKG_BUILD_DIR"/tools/mkimage -n "$VARIANT" -T "rksd" -d "$PKG_BUILD_DIR/bin/$DDR" "$PKG_BUILD_DIR/$VARIANT-idbloader.bin" - cat "$PKG_BUILD_DIR/bin/$LOADER" >> "$PKG_BUILD_DIR/$VARIANT-idbloader.bin" - "$PKG_BUILD_DIR/tools/trust_merger" --replace "bl31.elf" "$PKG_BUILD_DIR/bin/$ATF" "$PKG_BUILD_DIR/trust.ini" - ;; - esac -elif [ "$ACTION" == "install" ]; then - mkdir -p "$STAGING_DIR_IMAGE" - cp -fp "$PKG_BUILD_DIR/bin/$ATF" "$STAGING_DIR_IMAGE"/ - case "$VARIANT" in - rk33*) - cp -fp "$PKG_BUILD_DIR/tools/loaderimage" "$STAGING_DIR_IMAGE"/ - cp -fp "$PKG_BUILD_DIR/$VARIANT-idbloader.bin" "$STAGING_DIR_IMAGE"/ - cp -fp "$PKG_BUILD_DIR/$VARIANT-trust.bin" "$STAGING_DIR_IMAGE"/ - ;; - rk35*) - cp -fp "$PKG_BUILD_DIR/bin/$DDR" "$STAGING_DIR_IMAGE"/ - ;; - esac -else - echo -e "Unknown operation: $ACTION." - exit 1 -fi -set +x diff --git a/5.4/package/boot/arm-trusted-firmware-rockchip-vendor/src/bin/rk35/rk3568_bl31_v1.28.elf b/5.4/package/boot/arm-trusted-firmware-rockchip-vendor/src/bin/rk35/rk3568_bl31_v1.28.elf deleted file mode 100644 index 459d0662702e4cdc614e7c652f957255b4716467..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 335928 zcmeFaeRvedmH%7aGkQV7MsFY?Fw-N+4osX4;Z-=q>KU+&Uy@*<&9dHHGlQ^0P;S;j z*ozHDBf&Z(%I=TBib=p54fy4O`DGIp8;408Be3Jxv9n7gi~N%H#v?&uCnUQD{30dB zx}VcMEe34g^}WC6{&Sz=d4}q)t~zz-ls~Z zk-x3aDoLKP%DJ9O-h)#HMi=|YkN4T~++RPSUc93};8&+(N;N4f*_Vt=8L$ksA2<_7 zOtn8q%I}3op=%rJb)}{yf~GnajE{Hn&yauERs)|R&G;%(gT9HWA>X9b314MumaV#% z^YiG1p&J~3nNx4e2hiI@{<|Ahg$yVERRk>Gz|xbO_Lm$jNGLOKT=Jd!J?g^yGbLm9 zQs({s*>9f5Z|?`-_lJ%D`}heSBhbnC0;&I^KR>%sbw8i&)BEwI^E3h)0gZr0KqH_L z&EWv3f@eXU8Qni|x?)+p%;%QrAOI$GJIRQmEn zQOTb5cMjVsaQwDUsqUgTHuc|_r%$cfz zS7@W1Hr}P|xzW)bUYQeyS{{Wr_#OS;Q~&(yzvSPy_$OGDs7oc`pO?CKhMTB$Pv<#T z;bT`1Sj(fsy}lL4BV60dgUKD@^#DD~CuLya3`tw~rghnt~nDF|3Klg1{7bm3d z(QI9(%=E&h*o_Pys!st<}YeL*#!=sqW}edjuJH+{stt69>qbJf#|rlQ-8b zKR)pt@((kvrS#9k_o{kTF$is|SB<#1{b*mX?r62cmxH$gZ!^@kX;c53e`D@zi_Gbo zt5n$_dGAb6-Ea9+C_{Z^zWjn|~8w z+@9XMH&0avHr~DPApF!oZxGt{c%y3(zc9aMKYgmRM}ig7H(yFABjxg(l_B^=HbRV1 z$XGvZZIp3kd|QJ)#y4M;J!Y!8s!-i5d0S1@6x+0+-{aj>@kZ!%4Z?Fp6?)+-5B&(< zC6&Ayo~NZRq~2Ic+l^|qBCO~`mY!1eK=>4~?S zef!$XNiVc-Qm031)yO`0`=-d`yVvwr?YJZ{k$%rN)UmhM<{_h%DYGQrXQ+7D0raHZ zoO|ju+V{rs?dC=MMrwuMA3OY}r)}te$(-DEWX;|6@qBwhgHkO^pdWZgwHA`bi|hq5 zCVNE>i|i4L{>Lx1M>3>fpNhkWdSiUzoq4KzB{F=y*a&2sv76J8PdQ&z>P?;<%vYrc zr>U}+!K4$Ky|lMTRWIwLO;w@F4CM<&NHfStgzG`m=n5#aWy!mvP0FuI=T@kCHB~v- zIyk<8td+nIcFSC<5=Moc4k|Uvs8DGeo1PgRo#)AG@O{c2QEHx3XMLb7r_Ow-W7OGc zlV4<`Z&|o7d_%`*fs;Q3?|joef*bwI zl$x1{_*GeuIi#5}Yqp-Lj_|vDb@b3fs!;8_&YiyG=6Q6b9qHeN<<93_SZ>bylymdO%B|b9UHBPmGkZVw+-Yz8`_OUoE-dGN zpK@;Ah2;w0r<|L2zMPDE{YB-@=XvFnZ6|^k@ho|QukK#)!EPNk=uPIhj$cRnscC+%70bd#B`?3CBG$*Vx z?YqBuh27tMg({18GADm&LhDxMX_;&BAyU75cXUS-8!q<&|FpG|cZB{OH>b_|cb=`x zK9l@N#p3>6$usS=S3k1&hW^v!iCftxIN_DYO*QM^ zxIg9e^C_mjcv+7BlTtI|eU?g|iLJ2?MQNi#T~^jR8kn!LbD;OkZM!_x%{(Ny)`4A5 zjcN^#jyA>P9S)6lXb2{r&w8PJU4$$0CAbQn%mo+XnIk`frQq1JNwu;D7{hP^?O%*x zM;5~}o?VRBIWXwCTD3k;TNmS7LwOI|O0EUFUuCfy$Ne9a8|Efn(%z5Kg`Kl1IT&%ab{E69Xv&v2zg)WWxIe)N%Ul z(6UEN=@&c*|KdOHpnXRtb8N&1`5KSGL-NI|2h@1`K=Q?D1FH1u0dP8ClumQjio2g* zI1uF7?&qftumQxe6u0& zS751@HxCPrGTz}5mG(1_81?o@SgDaM@sfnGkZZphG0^QGI&UDKVf;PA%DHEKVAwhL zQ@M}k+*{lyJI>d?iF@>ajNW3E?#R7g!t>so=Sx*OqSOn9%yG8;^PtSlcTD)X1<&^C z;GtlNN;D|{sSfOlV3+avLTk@mxZaR8GB_RcaB|llDl~ifox@)|C+nJtq1#Etwu!y- zY?!P+OTi~zW~Wz1Xdg@z{%h1!>9}c+bWF0-(W}rubT@jn8W9`l)x|YVbbQ86i=FH+ z%U_66KM4QgTLj_17GKS`SRKOWKD8U(6&Q3}i;ib)E5U?B#|>_M^?E^~qcM98)>5Ve zdmyyMC+MhguZ7@KC^eF0T|YB$du9nP+yMdq_> z>(nB~^a%6maprpQe|HxdUDnBIX@WP*?aul;6}_lTFd9fC?+G3{mQyBnQ5lEM%YpPy zbIL4!zcS0M^fNhSW_xAuF+_)V(--R{EB#bXnekp3{0;HrgZt|oeh%f7At3eMe(k+H zeITdI)n1t_9f#+-E7ISgOvjq&@a{F%u(DL*d))tbGEj~TL>XhnoZ!h2>%<*S9`k{h zw}?FazqH6pH$GZ7xc49{-N?!-W<^W$m^@Up)Q-tRMazkt>xafmgHUZml^6J7s;Vp(-KSZ`19m`GIHOGT!;*aY$#+SS){tmleaqh@q>3p zcf15HUKzz$9cRpv@L|3bb;>+L8Ro{ZGRMJL$(ob#+H+6zkm%XBDZ@N@zD#agdv9~- z?4!)l+%j1@4nK9bJ7tbh=1IyxcbK(#qGpR4CLZ%1x(eC#+WsDOL}t7`T+q*#S2%R{ zQ$}RweakF&`*}ZQL}ol05!*nF=9t84;(v1Ida)I z9ogBIuM%EaDYx5HH#VTV&Dgz*=U=hYNTw5ivofC?$oQ;~==4cwpWsIzfu(v zyXrN2s^g=hb7j3?{CRXo2Q+CTRa>&S{|L0L@sWNh7sPjMGuJ!ytnsQWFkQ7$ujwvB z&GpL2x}(kf@`0z}FHZbcZJChx@+{T;62Bi3JL-f-r8@fj1s#3uO0_;*l{}-WA3YO! zaCLt~ePO$;R4StUsYpqD=bk-k#44#Dpw5V_kss?+BfGy=y02rUN|=T5zT~44>PLI~4@aATiTx{v)u*tj7|hP{NB#(f41$n zM%=dJ7q=~SR{np~c6OY8LEGiqSQmW2-h&%kHbXz7oDmoQUSbX}RoAGRqPCiscD9*j zsyt5p3)Xk;81+);a99lllu8`7)tJvahP}gs3OzwNi6IX%Z@6u&-ySsVc`C^oCBLI@ zch#e36mlxDZ&flCKRVtx1wE4ejKKKyXG9-@>MqLc$KQf8x|T0#nsmV!KVYtRs@~GU&5?an}KxwSvfzw+`TX zJNr-AU$^e>Kd|ol53FkvFZAlOPIcN&X4_WEttV@bK?DD{Y}&w4?1f#ra6oOex2xg5 z+b&ocWmCt-Nfq|q;`Ikxn{w6__~XRIS85ot^%Tl*Kmn;+JR2+dL6 zL-{?#!K1YQWAax}ZaVkDjrRRPyRIwB-iXJu;QD)FVXtM|{~fk*2wt%X=}zSFm(-6c zb?_t1L6*oSIPE9zRrs^v-=-Y$ee)His`o9rn4=$Dz4^*udPQYTS*3zH!8i3R6FncHbF&{MqrU^x1XO%C43D zOP@76TCiIYpLHe2r*y*?aAJ%_J z>W_bK{Xa4We_$*`9!KG0w;G-=@}A-Pl*ofQJpUB!2@e_HC8E*(o%4?Ype?#OC z5^K%){HY@5?_8TB`nU|*GWU4;smAyI%GJ~JF&2rX%HHzOV~TiDIWka@`mD48o*88S z?8oi2;2^$3JF%uPGTL^agS8&^&9UX~zFVM#^2kFuZDP+Z@DJfX#Xf1uiQk|zB2!85 zKmi|*vj(M3-#F33B0EjYamT@k)zxNB?CO?S7e2``@}wMXy8gsP@fmP%b$z_6pQ4wR zZFSj7U7(j^wyDHUi#`M?V`405To=QMDI0p0Z+O1=ZAq@%=u?vTz++~4m&6BmktaGNdy~?y!Mu3mWcLLcYG*Q~F{R?Qh=e-eyRMq#{h0nY?~c@|JctBpMoJcnux z^mAgW7}~!Qai4lzAw!e6 zclobO-N5yqz_Fe252%T!1|1A1QgaA^lgYLU$OjHVAMR-W{B8O4rRrU!SIi>x~$Kz==QzZh}dfIM6Z_>Y$ z=Q0N%$3a`{sFC&IUAqvZyx1VGEqCoCHpiqN-ky<pyJX89QlFYe8m4~8Y)ck#OO z{r4Wskh`y?Qa>i1f}DrqdDvysUa$upy7TDVuE3M3RWWCXK1+LB7$@}T^rVt+>|`8L zN6qpZ<&1#%8-la#7d@|}50g@?gSv%gyE*aHQE0qH`Ce!X%?x<&F(d z^UI+va@A~3a%hh-CPJr|IY`!#$60S5HYc6hjeSN=9J}r4a?UW8fB;ZOFn zWK919-4y<1&hcbT=05a&Y<>~nXUy-y#)|(Jcu=*D!$$mudQoH?e{Dxlwk#I;7hh5K@npVZe{F}f8MW;6Z=JfTcm?$`AL$wM6D@4G>l2^fj}+dC zX%p`;_kAv@N}YW#7~md>0Q-SI?hwdDhv-9i_cN>J7DtEw4z;gRb}$ z;sXl3Z{!UC9;i8t`vPbK|h&u=-(u#e{Iwq!lt_S<*7sLk*ObaH1;0; z(b}lvb5w?wWc%m!Uny{?W(}lRoyAWf7mG;Q%%ty)$9Ji1c@f8Mn7UWrQjyxl#z_Z+Wtb#LN-8Fg6obwbsiu~fsHpYpK zvlr1Kz8$ojGjZO0BXqIvEis-E2Q8KLtN2%6p}t}*EIt+Tgj*MHJi{}_`dCo|Eq<_+SyiGI$XtAZALQEkkl06? zv!^P~+EJ+mUlV>dZj>`~`-7I?4Gnlvmftz=REsTNp(8)LA7b<-D-i(Jf` zp&>rBPx-o5&9oP+S`(~qrmn2hCBJ==s+WHHD3_rvMO%Jphw_mU_46&X=c7N0I?eQ< zLHV3>Bhm+ZeeEIPF)qCE-1XBh@b5y)>4$kiKg=!@`aXVj;L18Z)Jz*e>Tdz#>%dpm z1lJ00W_}B0n*^5t`^7dU$U;a$~uy0Cg zL9IU#ZQs~`OKo1Fmwkwd(6!)O>|_PJ7fOtbwdgyPZ-B2inX8^-FD2qb#(ZWAF`cFw z`X8asktIQF&c^yht3O#UWjUAIwC6uJ_AjPvZOh6-L(H4)%HJa8JQ+j(x`H!%cFrxI z*tLf>+LIs0uV1sUUgB6sm}f**guZhIfj0c$+5m6Y^DKr>BUl<>`T8eZIU|qP)ma^O{(_jV$>XLy@Np`QoE-y+C3D7P5fP>s%wN z#1icVQ7~`dS(tmpwaBH6gPbchsAn*58q{&pYyE$?@r!lW!Iqla&3ZGIXS#bD!*Mtp#(@xm;T& z>lN7-m$oKCdlJ8cv~`>|9%GNhqwk%wh3?JqTiOowX6YuOy9&Bu&%D^8G0yRQTV*Xx z|H{<43uCif=QFEjDJ_BjVr0eCl8&aZ$y7!-%nerUV;em>?h8=giNsk=wJ)B+@LM9%*QvHhZZM;Obf z#QWxyBnqxn-Tx=QCd!K}NV(Zl@u414i7@=OU&{Kttb@I)^3Z;KzCrS3F8N#hk-^RG z^?l?!b{+bXCvq%05=NHqFx{AuoMrLqZlJF8*&F9$KGiL8g+a#1nr@63752z()|}YI z{o$L!?A=V66~4(xGk1+7$w$ujTjVQ$^(>2g(Fds;oE~=S(a(_><-GY6+_UFWez?!+ z_md^=xqs%Ra%eHf?r%c|op~17yvwnX1>hYR_#M@DVrQ_|iRXv^AHXv^F==i{=M_WiN-fvkZY{dL#BsQ}}cpZ+qU6dyDaM z*Yi(|wJkQ|Eo_IoHa1hEo008eW5HHS){I6%Y|BI0^)miEYZN2V7FpVV2)PrVNn(vh zJh`tgPh3x5zsK(Z@Q9*A7X8RDmSP(Wh5QgN$@szxoOflILquP_xmjd;Y&;!X_)~{( zWC1LQCDFDMS0JYJedM3Lh)UKwuK!P-oUP=%bJ}y)%HaBtN<0Hi!65T4`?%=f8tO^9o_vvsaro#%+)LS7^jdU#8@x%o zHrMzC73k0$!9F{`l;!#$V}3L7;)e?uGr`oaK0!a4PBSm7C})R|n@@wM@c9SH!yd?5 zYitg1_t+eME06>5cI1`z%arQ5#ceP9js<&SgO&D3gHoqr*b%Xro9Tq_r}R?AhJ_F(>Y5 zVo!`v8F`|=L-_4-FKej(1T)uOsnG2_Kg)B;zng0rw+BewJ&GfHzm?A=j@ zByv(7k}`@jyBXO7Ar_9$uv7dSY}G+K+n%Hzuh^CsSaY4KW&I}O#oBV4?Bh7=%f-Bh z2EF*ZMD)=`!T16m;qPPUr8BqN@y0>?1F-{x_z2=di=Xg)&fbW98^liBB{l^5ih0$> zKXT{$iqP*VBWqBxFE>->F2>d=C$^KbxRNjZ5*k9QoifX?uVO!g)HCG$E}<*sEza%` z2lndV$BrCf4^j9R8iFY?`Z;1JUuCU+-Uhl@UgXOwi8=?+B^bF0o;kfseHDBza=L;sw|!{25Y5&jpL5_#iSzkczGgpMNEI zQ183ctCaq6{Xd09)-D!g={}mJD{Cn6^`+eIoI2mmsq-hU$8Z7{uPvE3#QtRCNukAW z%a~0}{gae`&)oEkBjeJ}S9m^#Klht++Iod+vDNFa8-g_sMRrbdeM*^s-vmdogMy*> z0ZEZ{?61d{bD#CSyu5D4LF#ok&h9#hf7H#Mn?(#-o`2EhH}$uYiadDOj(4&3WB_H| z_JGjf49anSJ;a$McDtK-pl#E}{@{c5_TbCW?G|IO+k0Ox8_VDNHfIlW&dIoX>z->E z!1oXvq%u>Sa|Xu8#NRnT2frk3nl;XQdiW4y?^;yS&T@X@6Uv&Id1lAUychZoJ939_!8eQb7@ z71-Es5G$~0cl|uIU_rfFa9fc|M`v+ez&<H zRW6O`xp|dt9zMYNa^-FwbHY*T)?oL~KfA zmWDPPiD77npEQchT?T)HP@}z$~&>w7eub&{_p^qG9$dma*%KSE`{C6pT@z|f+@Dsv_If-NmiK%gSJHRnOv>F#8y)0}O$?GR^<>U&qx?F4ZD21pI7UAW z@Rl=%=#{g!wa61+_sX{}JcsC>7jW&ZmBn4gC{CLS{%lEU=cehZTlygUEA&kAJbx5N zcE{q}=jfdK{CvE_o0DX3_RdX#WqH(@Z4S?KXwsg-f0>=7;jC4`SK9KSXRq!MKFmT3x^K@0AdhcuO{TOjF+R6P1??)J4Y#`q{C`v@4 ze7iw)?i7Cyo=>Zip6q(-qW#q(u-=+l>-Zn=C_Y^n-yeTqKVzQSK`OovHex?Etov-9 zdOTLmdncS>KGJB67`^xP9r;-D%-3w_38h*V+<|3NByuR=rC`wk7{Y8N!bMo3=; zp9uYx*pKx8ZQ=z%`Y!vgKc1l~WK5cA<5kAJ|HZ?7XW_5%OAq!5=D#qLXMRB+CeerE z^x+Bma4CGdd#Ca)3E#PZrnI|>Hjn4X+h4yiy5pK!)xDPaQRYaIvD+;1Z(NyRjkQC5 zk{=x%-4-J2viEsL(vlyNjLws~dMT?)dk^YlnT6 z#3!7X+OannleSqZ@fK&{qxal-Nc>$eZNj%{W&E0AmC}Ph~G1J_?6H4 z2Bh9s(FaMpNCRKFbU?oEBIi-x!iFX{-P6xl?N_~m$2{azzEhwQUKz0$RPKJoaDs3@$5)V#uem;%<9t(qA2iS={ zb#?RbKFQxr9kJ)TsVC2*?OuH8rHm!dx2dJ!wAcagVjXy7Z+;EBM}It9axrbG-@}~b zwsC&{s{e=a#uLZ^n9pIZZ|#6yZrq18`3}M9pTJqx@0N;lrQ!A;wZ8%{~cpu5awDTQhsDi}|foHN^##iE#b9fb1jsTb9ta@Rz69`>&WL zF^+zpi)2Btpa^-||R7ydYeSwg=gL42}%lt9%PrQ2#79y|gv99UG z=Em_=rA#?=CbE|0?2sd?BA3CNCOPl8QvR64wAE`96Q8&O-3Fh}f}2-Y=nH<1Ea%KI z=d#}h5xM;w{gHP@MUUhi_efNgip`r(zG343!E+cMYB~GUP2Stp0hZRBXRVnOT15VH z;2nckvD>o8Xz@&~pIT<|Ozg!V=jh)0tV(~IawlY+kDf*-x0CxQ^*XrjE&>bMWsG@$ zkNUPMMYx>$`?K_GcuqViWXL;vv=QdHw6jvmtEsc>Z25~isW3+$S~=o{Jc-Qd(s9l@wQ z%Tq2k24m&))pGmlT+dXcm08{{z+ZcJYOJXnzDV)EhF_M_T!!L3**;Ws^PfcDB~>ndE@Mj zu{@JJu}!f~dq%LZmv58!mIe7nki~hBpdIcH+N?<^CpJlyxU%83Yh>dD-ae1m4rBPb zpEnfRr^Uw-xm4?>EpzNQd2*ga=D(;jw@-5RfUdjTod?G3CRhj^_&R+OU8}3I?@3ax z_nq!WA2z;sc<PqZ;#HOgXdK!EG?%-NW&K^B!wqC&B%PxO`58&?tA1=^#Kw?6%e0P6d+GyZh zhGL#&o$dG%qFWwrBDYU4h8E}dqts!oF8dL4(cKvV&RZnGuI+}JF2OxXzQl#X;27bz zlGxd`y(qiMm;69i;v%wAah|o0E=AosSuPgL(8VY>en?#hPz6K8BAK-DES@ zsd;>-q17O^9H&gXi4S;Fc*GCh8TjrHA7p8Gq=Pk}Dm+p>@yf;h6*t|~p8><@*N8)) zufwO&J#1o>{m*C#DQDj9G`XhCI?js8y^?Xkzt_Cs5An!mnj8~^6W>4Ds8nL34%+(P!F%jn74z5eWTZ6>l0>=eo zpU~P?oTxo%rkSzQHth*!BEw_Pm-752(>ePhyoR6ToJF0wP+pf*I{MUBccDIk7w;6` z+rQ{Z!|7*ae_lc`UW8Azn0M)=%_wc+gH-aq{en2YkFl*_L3WSR;X~v@y&Q4;Bj-Bf zUgxegWL~dPNyma%!ctZgC!Fa z!R66I@VU)+*>vWJa6!Cr9Cehex3L!n_%23nn70=k#b0vDX3XrlOgFB*=#X*qif*G- z{H17B_#Uy>!9xEOsUM_GiDSwdgIFGIE=>FfezL?K#0OisYI%RuUfREc@u$rui*=&3 zBjai*wV-_==l;01(R1?3WUTG%vpup0=vNC?;9Jt4rkX;vAi@|@u2IghIyB+MT3u65 zzH=rl%rgVJ2K5Ze3qAK+742i+st_CBj{hm&rI6=G#K-?mc%-e$@mn1p#%x-4pAg5U zJIc4i#LpF8zRa3_e--O9@`NAGm&o4cCwh4n<9jqVd7keo`rxl@RctT)>|wvskaJGRv&x<~is$sh!_#XM`I7zV9X+&p zideZx47;xSLQD#2-HE#*X`qN!^-Z1t2wVYjQ$d2tB#1lTrvj{pA zi5C!eRwE)K)^`kIJ+3`soR2AFM#eKL*Hu%UZ%rBt3zu2SDh`OeZ*%uS$Htky%iKtu z!`c62Z*9jq^g+r_r|*NJv#KD`#y5y&FSia!TV8*p9UCm)duGZ#!z628IYY$zE~$x} z8{&M}4v*e!Y(PJ8hNSt0GeHae;Ovl`A@a@-eKVhLcyNYD&JP{Dee$wD5=+@}sp6Xl z)5;z*3g?Nx@IhyYgg?ihcHWbD#)$#8ZSpOXI?jA_(K(@s&N-op&N(5m5gGa~lGr7=mcHXh%K8YsA_m62H-;i7HgYQZpTvjoe5c&=hT@NVG2mL( z;NY@tPP`~ln>5o#c;P_D*OYu;Z`)O>n6n$43!T7O=Y0G%dDom+QH=fQAF!|RN`!TJ znBQW4OMC-&uay0_`hm^xAaP)e@p}IE&KVElobkqIxmI5%ruT6*Le!>FVysVm2ETMu za@V0ve2<4U^f&mn;X&S!O0M)LK0SlDSULU(@tru|K8&;P8WlVLrK&`4jq1jKaqs<; z6HjvAK^ciRnY@#KHFbluc@P;oXkM8}LUSMO3m-%9F8whJt7rMfSI;uk)V0mTyG+iQ z`KgO7-5z;;30hxe1^tdG8*llYELaVxlUR6OGC6l) zkJ*d!@3@?Wr#7=Vv5t2oJ`FEDtP^*`H*-mL&Of^M->|K@c1QL4e$KlKr(c^u3<6(k zFR6@eSnSmu6UWZ4d3!DrE09<+GBft>uDoL?cmzu(CH@tCk=Uh8KLkIg?{(FQ0{V?V z?#8{H*p+Kf1Pgih%;>&ufylu<>>mt5%R*o0MvajQe9r*Br?Rgec!T`z&Z2~z>5AiP zgGD0?cqdkxM25%O>#a`6`hfRuM|w@{ANCIX`eZ*+Fj@xkgjT=xz-*bA>(Ul=>6C&=N!T>bCK|-uAgm zjgd$8v0nkM&r{wTduI=hcBa$LI@&p!rK_Hcq?eNS6!&1Uow$t1(Dnzj_aa+-_l7+7 zMy#U5Km5UszsY+0pZ_qrBaPqpBI)-@MQ;C?^ZYRPl`T8p5p>qOUY2uhG9Ght?mb;;I_0jf zh4xRNt5|E8v@g7x=sD-dZwY?h-fpa}85S%R-x*PA`GL#}?w*R`yLi++!#tOk?@>z` zu|F|vLzJIj5PSn$vUEyfVbEFIlzH==$@%XUw6hv)PB8w>_9cmv=%Mg>8*7}ytceZe zRs3e<6PvGg#aFK!w(xBjYsYRx@U5GpDzRcAa~^&*WAA*&*vC4qynFSAH;veM)naK86oyE@)-9v_u}iG#Ezd} zuFvk1!r#Qy=dquI*zFkQWuNp>$_-JDGf0l!N=$I@BRt2Z5AyBlSdki$bFWdxPRDw!>GUM~n+;>vQOeEo+CR zlla!fofpiPKjqsmGS~f-cM24BUldy0A1rkD&iSUp$e*%#1LVmW$45y=NDb=9Ubm#; zFG;;;c!sa+T%Y1v<|WDBLm4@nD%bCjFZyu;p51fO?mL5X!00>V3m^YzvNqsa-jT_^ zQy6-Vb(hQ)-a5w^Z;y;l;QL6#U4y(+a3giRb=Y7tc;NRok>{SPc6}3Le0ZPKX)jTy zzjv<(1u5|A*UUgXJhEBtSyAEu*&p_ z{T!qX;m_l(E~k!1=VMvkqB8#bFU$T7f$UyzHXa~0TGqwPKdC4_{OG8;Z}gMI;o(Pg zUiiNRI_=h^|ok;$_S zD*Xpy+(#%cduo|lBO%`?e3d-T^DTVFT4g)tEQ zu&^J(3uUq~!GGQt^JQb|S^2DJ3h#RWc{yC8P7k){&k$LSXXW$~`cfxrsjO^%8(aeR zyi;4{IW$H8WqdcYHvdh(N<^V^@@Z@@aRQmko<)XbP0YMIcW5?ySL8>_>=BWZJ9w5M zPwcdDr7FwJx6>B;Q=`6u8B#{%dI54PWfc8Uuix7rtybuj8?QOHq2IAd60S*G508Mpzd(?OPIG7MeU?35L@CQl3TC(LR}nAI| zYYI8j&36PGTP)+J7&phKM{e2}=eCHMn0*uPHcS7M{5W@pEtPxE?~?r21xwybj-umU zzKow|pNzurKCvC6?48qx^a|`pZ+1L59OT#yZ@z+km&n35S@Zt4M*2Z4{h^yikn#71W(}ta0hkxR& zA*3&2{~By{I-2Es12W|GFS`bEY~4CAkTU|`Kz<4w{@uU5;mMXW*4e#%nFr%V;TaM$ zG2><`O21yBPcla0BY1o}@0VxwPOXmByV$yO-x#(s*D>z7*fx$~>&|t#*k*{Qdf0lr zyQyjm%CHiIsR?G;{S41OVF@NtzMn@jMkBD5=UZQdZ#?HJjHD_MHK3_a9$T)YRW1em}IKum&^c(+SF?(8Zo;$kieDlY(p`P#M$%n|B zqFz1a*JbtIv-@6ILdpE_(Vj{g?5~jmL^j`)-Zu-okl#XRH)wx>m0mUP(+U z!aMLQ;=a?*!;7>p?+B@frzPUFFZW1N;$FE1U+mf})(qLWl^cJIkstJ{wMoWE%CpAY zu1W$4i8XVEr)yAr$7n$!Z)&`8l(=j&x~Tk*?24_$AM5h%YmTd*5B?ATzTb0RjXkxr z!QT!LALosNycwC<==(z|vEPwH>Tw1jO8ms(g|&d3yY;XYT!~vfUXIOLMk?5u*hTPb zd=1(bsl$8ryG^2J-=$yQ02lavU4e<5*;Lf=Gw0YpATGc+u?_aSO@2OXRHr7W`1KZSD(Q>=|@ip?1YSAU<{XBKYli$OO>u0l%f=nL*IPQ=rP&wLl2 zlzO0V_mBRmQSQSlI0vTqRvEE1iDP+V>d`au_{RG)htCMT8hCK_n2l|H%YJhBOblI# zv2Q?o+nh02e0f4W7f4KS#*luSj9E^@uY>Q0pZtnB%Q$xU3~Tu^@%x+CUqY(V zoB1|*Ef}og+RZO<@&{!+dq1A=q4y8LPu+C($0_489_ZUlKiat#{%eUrG*2Z)K|KFC zWMeZ}th#cMoULy?$@eK&UFl2vusLH1*T_D%$U~N9S+msjMrkuJ7`a4 zjj2Kp4;)^rxR)`NZ!SoTO3wD*wn~*A=6%GkGFHv2h;8B5$+#)jBf(@|B0#K3VpMz= z-SOYh5eH+z@C4s*5$yep=VpG3s}|iO_=|i5!Nvr$$oQ$VI>7`PO%sdhOY+R1ZcrJs z4D#ffSnzy_R|(F7Vk@eI@;c?&UVKw@y!K(n&n|4O*^3-(G^d#8vAjPWDSW27CO&b7jc%*L zr>m_8-952@&fm@QXh+DG^?bn2A1fzoxj=MWtMK(S&uigJ)-r+k zc&E%}^2D!SL@K_o*s}&J8-JC#g1A}R(T^v#786V4IR! z%!7CMN-e&n9L}E8`W%4eJoUM}g#Z*8w4dYwA#aJGXOitu|jCU2eKFb*A{Y~DkgXm&%ld~1jCAxqJAHRR-7NV|-V;VTIfp&1e^lvYJ?VDlNal9@ zz`056u;7&}B&CnZ@uc)ISx3rPCa04!=E*DV^zMaRGv>*e%qI`QGSW>(+LP^98B3X)pOuug(I8kq z!gXvXWyz0l-9ACJK12ShZyV{oq^tKBX`3|qsFCid#>TC&`6gITBX+uob!%wzl6V%@1G<23fe16m}6BB?}wW$N2YKN z3?8u`Wpclp{B73bTpskqGny*40kZIBXSjhDmq|akE zLzT_~lXM&(S<2;8?%6_B_6l@&a~@LYOZ-)^$-LUr7zFP)cH6`kP@LOS(~njU`SL>K zhmypJ*5KdDeeCK*cSphPcJF@PqPsJ`{Lo78e%7M9ZJyui-Cs+2>fhqsM;6^3=l*lv z{bv^4-OC;TFUY&}Z{VKipW!}^uQLVz#lqiNsP1R14mDoIdBt7$GaH#NW$Z-u|NYg` z9k(F+gT(a1o^5EtHmtJ}oxynHW1Nps`0K|x3ll@WGQKIHIeDs^?`(!*oO_ge6FNhj zm*0qN$r*+xk*^r?CC^q+R=%ecd%}^UIh>0ft200ySv!jE?Zb!JO}*$p@{TfRB%|9& z8GB`+pXhCmPqnU^vgjVgy!T*1WpR8()v^bDl{Zc;e7Slfx?F+{3;L^zt$9_9UVoz-H6c!lVb#l8u$;OLX+k-B4I z+5ep`$(YB`rH?_QeF{1Uzj5rbV5hz`wQP$M(;_}IAwF2yf#pBti!KKD9?4UzlUcg5~8J~LIwFdyjafR3s!ar8E}hi56CRjE*i z_snviMGpw3Tvwvctz2R=)|nti~M&=8&k@H zjH#moV|nFeK}&_=&=$;uSC!+(M88J8^;KooROIgg+F7p3)aTi6Dmc%JlE0ai^?RZ_ zDZjkH?E{$NkKQaYGk9WinfO%GOBrM78*PegbmY*9Ql9m!^LKCKmdnpxWWXqJ{jQ+c z)d_|3yg33rYxG_IK%WtG*HhiMBzMVp#fz?=!2!9%mTU207M3itqx|iYh@I}VOxon{ zobk7v8kFzU5qxx2_&{F_nUlWz%2~(#(8WM(uz~Ez{3Nm?^OKxAjy*+MqSD5icwZPB zDC7H)L+1t>b1zNY>f)$bOY?(v335%)9c& z{=vV1z6t&0d+C2GOaEKYp99^ypdWl6`a=72=yH`WFiYBU*7MMxv~m2h%q*MzVCeT= zNI%Kf!e6A>V>NtO!gc}2A6)&w z7a|T}6N6~LMnM}pc7J1(x$kGZ7hJBk_03^ElvqR5q;0{D_6)V7(IyZ1Tq|wH=#xBG z>)pTGBs|G;d1frXuQ41;t`)f}2Ad#d>Fe4bgMrvgKR7$@1hA*=(g>7+b6WncPKNgg zlbh5OFP83nD{bukclSN$K(T6#QdjVlJ_#n@gSM=v1_irtHpWMccs6TB`w()AugEw2 zQth);T4Fp3`B=R0)BUT;nDaO%3SNC8|G}!o{SBP+j)~slGsJjqY`k>YVr2CVXm_vV z+_wrWlfTPbM_)SlJG-&ok1q&MzrKHwwWL2-r%Ge_YJuPrWRGMK=Nw~2YC)L$+UZYM zH(#n2EMo2oat-YT;q|xn$0l)}TK=Xjf8%M<)NA|Y?`$eHjW*<+788HThu-^(X|q`2 zZw2|OnW{88O)ZFC!S@AOiv+nBpDb2Q+cj!I=Ua>o{fUW9qP+%uJ~Q7rqt&!IpEdB+ z#8@t6T}OU%gloz*UrRcP^afJouK6>h(?}ahYe+vwdIjk%V1iz3{tK>eC2t;dEaDMMZ-+tZS+&d`|TOM1FPhAq*8|-r4LwIL&?&czA?O#cJVeaNx&fn{(jO44iyJvv) z?a0-Au52w}-#bnpq6N(R@0v3fAV*>1G<)#tR>HfPT?fm$V>7<1tOsTN5g}e9Ye4Cj ztO46MjhnHE^=*XjDm51s&WQXy_34MXiZt7g&da%`ALcAl`XGJTTkfpEw?#@S6On8` zR_?9ovN;D5q#x{2H2xZylYZ2E#{C{Z{1*775Al_xYe;V=WgQk@LwXnKmr3s-T}!%& z^e)m)(pyRCx3P|S2%qu@^6F>(AaNDnJC2`~_GJ#QwXo;vPR@THA68vB=zL){!+%v??A3Pio9q1eQtS%E*#)IpGDf< z>6?+eKNCL=7J}igNd?0pQo-=Iq=Mn^Nd?3IBoz$Lkam*(%64o(kg@RO$bkNr8KWBf z=JaV8j)8@pDs{+VmoR%&ElKL`Tf6T7OsB3|A6Ryyq)vJFJ6vL?b9q9hE}$p;)xuwtz5oA?zo)bODT!CI zW*U@z3F4ootYQ4-F6Bo?dB^Z|%6a$*HnN9$F&_p#y|nG8?Id%qv~83i>(Df;@ni2_ zSytSMi}H$8Uzj;h^g(6gz|zn6!#zgqOlbd+caetRGlR_=g#HO=UrU{4c>YMQO8h<7 zLgP{9<5ke@QTZ(fW9DbgEo+QIc$73oTF3WiS4;mGtF1HL80hcTuR64aJ!#2rFbZ2F zj@wL3_Yr(pzG=~9U8$UP)mN#X$GO6Byn{LYxy!qPv|W3zeg8@RZjZ!+f5wBpCW-dgrI4C;s-iryL-2~s}D zTF_HmkaEnGU8^Z4?dR@+bW(53uJO*4fgKG?{l&a%U5MQ+b?G|xa^2_q<-I@W znzCj|_L{h%SwS2H+D_Z-3(5D*418|kN%D-T*y0K2<35hBPCq1m*;#QB4|O>_Ooz_I zi+Et1#&`f<=URA}11`)xV?5Nqf1BcOTIl1LEV5Vc*?>4>E6+Ur6}h|)xfFd9ne1hJ zjL(}R+lWhgXJm5qHJG&_S5c=I8zOZw$gz_6e4U*ZoNA_nuis9XU?k5>Sz|>fCQh-J z{s7;J^V&YgJMre@jIo(?_hs?f@U!>^*yQZ@xGKiJ$Msj(#pV3oP6ZQHf3_0xJ>S1( zJmhRp8hw#7ME%g;W6Jl$C$}W=7fv|eK9w`aRjF$y@ptw(S9EYsUZTB>7?`Y|@SO~7 zh0I|hr`U__*oR$VXzqq)d`*;ZS{N-+^u;75NFLuXFj|g)ftaS*v5&9)#=FqvRHX-kk4S_=h zyWnG;7%Y5fmv293+^_?eTfW4@>sKCHm3=pF#Y}a&10BUbOsI@ork3Zvi=Ml(aN)Of zWNe%mcF9eSU7-D@zmV?%!rvmXt=Ri0F}*ncy{rvnogr(34kOw44QE}T(v$GR|B}21 z@WrEG@2v@(YwTjwRB2gLB;}c*=It4F=Y=1WdN|3skq3v}^}#zs?)spE@p0+7>jSx# zeImi^EM;DSZf+ZLPAr$6^jA@qP4dbB{@`xLFd~>nD-$Q=j4;m@Gv+;vXPAE5*vtqq zW^9@Bw>zaiYl~KY)wTDG)wQcXR9&%y^0#cp>RFe4sCp-)9{#8NT|a5t=AFtjMv^P5tFPMaWBYFMI6Nb?0MOR-z&+%#Y2;%L)trv)=>Y+x|{`QDR22|17vUDeVb= zf}g|?MK+9VY*)%gg%`?N*b-U0SXthjeAc5G#zD?Kij5FD;=c$sA}@l)AgSQvyiZO4 zWsgmG{&!OLY8&&89d7g=JG@rbkk6dhv~5d#c4A9%VM4xX;KQce=J$17fi65t9PW|T ztLlFo%?n+wRQek7@>bW@qZ5hts-dv?hj^FOA@ zyOq3~O>C%QX1vihc-K}Hwp@=rR`(jqc*m-&aig#Ff5LZUl`4IaILx?>6Q;;_Vv08w zPx)8)9e?lmT{9+{#S<8Z-J+X8d{b~51edQ+Zs^MLDT8$tQ!+EZyDOr~2s2#LCEqQu z4b}Aw^VX}3jeQC4ZR3B+-%l9A_hD}$A-LqOH_QsgF}pXi7az?eR%gl?3Hn`AP&i-u z=;2j3FWy(PanG)zYvX-e_I@fMxbgQNy9z14Z+~Ut1@4QuzI|iyt^&hOzq+cV?Ag_; z*8g^Tekk8i>1)Y*7N6ycFJ|$)L!I6Yo<82aY^QI(W9(^b|CadtgtRq|b{?5omDqB~ z_j74W+W9HzIH!%G_if{fY#WbyW5(Pt)&}w=@ApLD)$x^h-$?qm#Udu-$j1N0-n+*~ zSzU|Y`*~(2laN3z6Ci|0W)eV%RFQBAmBN#RaPbNOmA1A_7_6v0M**u;Q6@J)@xo)G zQBWDc3zOrqR6s~u%LGBZRWTS2?P=?TaIwWIA}X<5-tT&znK-CD?fJc*-yiSi^M=pn znSEbt?X}lld+po0)$k1aR{EMc?>ct!KC--{6yUBAp-0)kS8@yHd961>@`LQjjPZi( z52Kv6Uf_{-3pP#Kr)Mr>7JJ0fC^wb%OotEN*BsXVjd|$fJ<^P^a~9vTcZo8Nml=gC zZqQhZXFpl;#Xb99`t$r5pKy=Kv22y8Ltk{?%GsLJI!ovDBCnxU6?oJUUhhrsKb3bg z(Rni^&9lJy>cDq%WnF6U+WfKNf5r;iV}(64aCh!A%#{a!l0SA(sdsD{d;xD~O24wl z$At5I@Hl5kitd1)WRINeGb&5?-OWeR*O&*3y~vsi({HMwV|@KjY&OEXYmpIJaj@+` zM|Gvd9mxOf0xz)97CrRr#!B5-yCAMJ7SJZKxFRp**|5DFR_v!x?2D0pCVgyE=RL<3 z))dp8+-Jc$6?z5dIXun&w|il`v(wf^&bM@_XLfE!9y14R>(wIXl%yQXzYo9Y&vE~s z$(!gufIl()AMm3$b*Dc}e(>-1|CRVe|3}2rue#%p6QAh+oOsShcgKH8JbOU9{bz`W zp0$ho+Z1xB9Njs8kNQOJi?YURa4PqrLqlKEWjR${<@wMeS>0F3J?+g$)CJ}tWIpzk z1sibwS2gzII+~@-!?7|a{gL%1|UWlq|!S!G^-zur>kG&0v9!vg4DKKQ1GA^{ycPi(^$|)G>Y>~bp{l>@GV9Al;&TiQJqg^dQ)`2a$>*>~7Dt@~ilG4$S zut~@LJ%~^A_rgz`cE@Lto_6Z?_p$v3I+|5}F6oKy_75PQcI);R5TEEDY{v@^_ZB`G zV6<>QR+bVS-#!oATmt_m>R9v#%f3CDzF0;2NWpvPE!s^HWVW1pnTswN?>nrMiQPAI z4Z63;B)MPhI^wN;{n%`uftO3c9b1;Uj`3+Ac3PR|)MBSCXHLO=E~6aSX#<1>u+uJy z*=a@3koa0`v`G?Ae_kIf9=n@#XVp)S%Xkq`%W@^G7CUV{cG|!|m08X`76B{Hby+=j z+H&r+D93;OkX^YIX=-e}lf8fZ#(p@q7CS9qCarW2Y7SY#p}RfMu)Y&3EpQ z^-;IfFE-i$PVBO!dDwXeV&kPP1Nb%iS$Ph1alfwM$9e*L379VpzkIJz=NKw|9lh(A zciR=#++OAwGVk|p>q)W@YNeYd&%p6>57&Kq}Tp)srBXyZE|x5 zYqqja#hFohXZ%iMFXxSK=UizO=_7x7vQqRZ1HD8sul2H)BzzR@Ied(MBYcJ{gSUi# z4ju_rUavxx<-}{aiNGRv)w}q*)Uvii+i6GE6Gir-Ly<V< zZ^IvY(Z)0MV$YUHpJ3%u?$1etrxiURBxg@mb#Cw}_t@g-CGC=DVK0^Cx!l8DDK<~{ zr7kaYN%3&jAD-yJcQk4DkxuR--nUL=a=&t>AAQh4T)v~v&9%sk#;4pS@om3C?|U45 zPxAgfOEvbt`L>cJtgqkYS(O_vCofixtl>XFS)Y(@O{^Tr_c#2PQ0HCgDr0+U z*A4aw>NO?)5b^nac{he}XC&zwfvpc^HUgX62OUZcR{oJR@ADRqz$SV2<2OjNm#^Tu zQ16>6ZLsjdj1eB_Dzp$D3Df6PPS9E#l6awcFWOdkM)<``SiJ8huB*iPDEfLE<|ISNdaZnu_rP%SA3<#eKc9=iFU6lrmG%-RHjsze?H(r+Qj@e9@`r-y6qa|6tRa zkIc9Gp~wT?8sJ<3@0lr2R>yPvp3GTMHE*=0p0?Ul;K`S=Xoui%d;Kzpe2dhO(V8=4 zrIG%8hZ;UwOSb*-blHSA=>4)rx=KcC8FrlXA+ZCUy;-&NXU-695PG<$=bz&34w-lS zn+;nZ^4_kdjMfZ0p9L#AkZy>9c@+ZKcSOzBpOa72f=k zdd`-su8vxvBRJ77HXy5oe^_M97Ptf^ne!#)eJ{Z;Z9V&J()?uBoHT4IQTB-W=o8=H zy}i;)9omDzwtH1grL5OSYqb%VI8sta)v8R1Gbn#tgUbBHpRsR~4wkagNu2OfSi-F` zds$`1^Qu_fJl#Q>H^AusqK+dw(6w=W-;oqQxa@!RV4QqU)h= zx*CamY&pm~8Bdd*ySIzR(RZS?y+%lW?|Qj|etTuIR#PcytiDY7QbxQE=_67{kg}y* zpCdWd;I4Z=Va9|hdpoY>e6!R?*;28RB*5sREZn zuc?$dY?7l!-s2+Nky=lf$cSZx2~2i+SE|6~btI)?W47AW>u{&~V!z{cyQn+DdZgga zI5yH->&z7X@j7#}@|DAqmuul)L;Cf$^Ub16>DMY-IqNE`abDgZ^|9aTK)KQ7lzg}j z`dZMdQoV}`774wDHbM`TZPOzPjDm~MQ{a%dsXNH;Ll5qN?@AeiD0ftWCoMBb{x9is z)XyDkE87a-7lZZ{zpPgo4!b{yE+IV8Pd!#Cd?so7?Ph(Ebk~!vAM^?E^=im#>R!(8 z4o9w(yHTYLF;8UJ@~Y!G?p{Xr>h$}L70eGQi*>^hrIZtw6(7*Qw?UI?`go2b)#AYt z;`<V{}{HMUsIA^FeZ@U`*mZG7i+>0u2MevYKWijU$=43^F zKp$^w)%D99=rjSPUv|JzP^7%As}}02ho8OuWit1~*7RCTR(Cl17O8DR%v#z| z$XM><*_U>{_)=wtBM zgyD`BiT4dJZ_$2(9t<6O)3*rQ<9MrQi`-{m{eG=yOBcT#XU}d4F`v-J^+ZOpHu2a{ za}qcU{Mi4R;n9r}?#s?$4p(Gi2bA{8ino{C$v`lU|BUfC0(sq@B)e=W4|QNIRE z0!K_=-{bqu6)m#^ig@ z>mEWo{g4YxholECH5@w)>AaNbMd$Le9_D2};$_{7eS$4s*0j7{9CL0j>r}FS=w&@h zV3Ik4oT-y~q^$)WnLh~+cQ|}vx3KPWFBqt@l&Z}wMJHlk3-Td{Z$G|XzBzn{@a644 zWP;+&j#A`++$~(H48FbjPT|Y=5qYXobet+_6KGqC4Z4i|i>>fLK*Azdv;^P}=4Dy3 zXNLHZWy(FGPgbz4H}-|mz&Q%n$Zw6c$&vitfm{{*mBF55emBscqAS#hAis+V*Wn4# zM};;DJ;YDA(qrG)9Eml+N?pa;V#5XI^XaN_ht9kx3)`o(&$wacbA+vvFvch=Z2vHG z9bq+uRmZ~?eaC!~usITD(XlivY2_|3m2)9?$-lDUk#sq)`r9z_qfOuzy8CH&zaCm3 z>!%0M9lQz{;Q?tE2fCDwzXrSt@XK6G&ezt!iy|`|X`uxYRt)^-@JQ%F^G;xq`sKX7 z@?K<$%=#H&4YrQCQayi>Ip6YUjJ9w(c9HpS`1jJTvi>SzqC>08hnqJ5cjB6?@J;j~ zHA3JQe#xF|w}*8vw?Eh>?Idj>Z6IwC*C}MIk~Wa}nMF^3jGo(un^#h|&{LZm3!8Yc zIhC+Egq=fA&h4rXF1F}d8lz{By5f8+@QB_Qfv-60(X743T$=e6d^giey9myz4?M(N zRq}MV{k#$8cO;HJEd5jB68q?2;(`I@XMwNfJ2}G4mwdFDw81%L(pPgN4qg*JJ0}ia z%al0yTX^l9IC!py#0js%U+2WZdk*4)#0l@669*5T>P0^IOWOOKIC$VQiKBfq=zdNd z^#4fWXh)&{IdQbZ5#qXe>HcC<+T#FW-Mn<7*!;8QPab3O(#VnKA1uGu_HP_%GLI+y z5ZiBzGBG&gA8z}9Gs=A1@|VQ&k2c@1{6;MQX!BLeKgISBA7k#Y{L^CbW6a-L{#mj3 z67yI1i<1|{;!Dhz@CV;z3_+y@5HfY)s8D#{*y32-=K>1iH&2;4c%cm zc0cic*IeHnX6cJ7Rp`6sQ{7?1?R3ePn2&ddmDpj6FEOzh#Og5Yu#=aV4|Ru4vBUi1 z%=@~-rrBYyjWg>B>xOyc_spudfmPD+m9fgg<@xW?C+&Nrf8I-FTVbb4%m`ykFy8l1 ze9v4E%NInhTWOvcZ~j|%SPcJ(6U=$tVKMwaoL~mJ!@QDrBb;OYxH~MSLmQg;{q8V} zCL7g3;Sg* z=??STVg4j@ba&W1J8YQSytq5;Ry*vN+Z@&%w#W|KoNS)o9Tv31W~G?VLC-jyWjqzR zF7iS8jwKh7=OTxG%{(G5pBDDYnX#}}@(2$y`&@ZSUi4{&ZX3_5spl;HLGmifjGsM{ zGX~X;kQFC3N!>t~AijVyC9WejSF_F{D4lyNSnC6h*|%|i2%D6I>&OS4JO<&i7tqUB z+qR<80}M07e$5^$8JF3&nyD72%ut5n%O2Np86!k~E3XZ!lv}V9J7tayj~Zm-uNhBN zRx4X~5m_rV=~!mZAw}-SWG-#m!`#!;mhl?8Ol;iQXpK7?dzi2HRM`p~ee_q+zdGV& z#_AUsyJ0{U0>=UkItUyBgVg&k!7(M(d_n4xabZV|l~3ET&MGSb-j#|m;%UWeVI%O(1YVENre_eES#*ohLSRfNcca>$YCZ@ZYIMdruQmQ{RJW#? z_r_`Ci-o22H0uZpa&}Z~gmM0hjZ+)dhMwkP;IsMhtGy!cL8pblEaUT3Z1zEDDtsdJ z=?zRWUJFb?cum4uKfbrJHQlBqcgQzQ!C5p_%WRr9thZzfWv=_{W@+F4syY;pLPsYY8p5C9$+e_+3qzb12iRXl9gk+yRxRjz}2o4rLnthrL`zL0~bSu-JjROBiBr2~73*k)~;pS^dIwZbNNqI>=*?-k10 zkH8hznNDzLO-vLAAzT?#@?}(`KEGcmvLt7GN0;`>Me|{ z+QK|j_A`B)X5WjpuSR7yW-0Uidz|x2u_e+r%qh_yU+ZNaCQU=!KIu(24_JO{?AWND zPdEQ;`K@tdBWIS(KUjWi%-E=QW|;f%Z*q8T`8h4qY{SnUh&By6MWCNTmR!ibaS4yl8yX8MB`g#R8yE|#lDx67{8(5uVbNGvE@9{#cAe2obBhI2Y%IDp%lxI~kBvi4 zkNKaL->}m^<}t&TKQ{gh%Ql~}{IRiTbGEtG^2f#ajU?+|`%!z*bjyV}eA2A-95HZOeXWnP0EvE~xu zhky4}iELsnC39`&X<5=2qwuxFY2??0);sAJ$a2Z^efW4yc1C;jIB)wY9nV=k*2i+#k0R$aWq)Bm&LH{AR8a}( z#^MCu-VUQ>BBX8sEm7n)O1QM8q?0`e(!SREO>AFb2JLFe z7t$n#+cMn7U+}v|<1Iwy5&QIHQ{=VGbA%=%p^4xvIJ0-LS>#2>pRgOVXEmgAh5}rK zPK^cswaTB>nENGgDFfJIZPSHaXdASXwD~IcCf+vAg|;{Qp@+O@s)4%~dT}oPCb65x z_I*yYx2sn)3M*=P1cF5_wZhT=3@IH-LV?>N5#`g zyre6KPwBhaI`p&W(daGEtqfjTqV$^%fb#_QN=Mm4mbfM)cLfNIThXnbM5eFdZoDbj zM4{bA6}*tUDQ_#O!UpDD?p+~wjEbxjd@4!nz`iAW0mH&av_UoWlz5@VeX;RDXcAwi zk~o9BviDGaNBAxKNUc2lmU}7XH~NsZFHU}k2$!`R`R(WTf!OaLzhy6(6;Ap;@>>!1 zb-h6NO5S1a_rckwtC0_a@0OYrlXl#rR1Z^&R`ZrscJoVjjy$O?8o3P{RoibFAH|la zIfHG#7Q0(Qn}r;U#x#C@&t92BN3_uKYWCl<7I<+K+-vw<8t0My@W_cAb2>cISX0h= zpQlIzzQfqZqwP(Vq4r-d270mLnC(0KrH{lQK9hP`GV<|_Y9BY3B z<*ZeU#%QF)&d|04I!%~YunqgD^hv>4+ELn2@DqEmwB;0jOWgaoQgD-f&^6%s^|3)<_($~O zj7sCbf=8V0ar!0FW`df3TyZCY&8shkz3fAjw)idZE3v%>*H>!Lch4c-Hz01CgtH#f z3eKX3iJbKs{)*o|9H=GNiL)oA+|~57_Vh z7T60y=`9_#Jw^zQLDB?CqjUa~vzu+a#o2a|#d|gAO^>$yx7dgh`kz-@G)CW9)5f{V zHelZ9+jyZ_NO~<6_73SolzB5{VzZ`?k1~ay~W`!HeO;DeAr8D zdsZ7AK(Fa;ANWz)E#5xDAKiZ1r#jJ(ty?Qdh-WWRb)p~Km|K38ADeh}q944qixc9p zm1{*Vq8}T&R+-WhBJYZop{K#DdWP*F6Fw?IQToKK2@?Vaou`4)3OK zqThlwA>M*D!EeEu;J08+@LRAZ_$^oy{J<(aQ#H@Ojk{__aPPe>D`LE2wQDHdtb2QV z+qzGmtK5Z?^hxN)gXekew8J&)+(=o5ky&RLrf;QY&Q`9QMQ@GJ*L2bc-#&XhiXDo1 zQ`x!Rqgv^gBqlNZ-L8)}Jit{FAtVz$#=6yG>G6zN319wbi%KqCV?%W+LU+&y} zTCs+YtELY0;mYrG7QCD}mY3hx@cT&z^L&2K;5YCxKE7eC^`5?KOW2EjM&!7xb6iHe zA!!Ml!tYV675e#I!EcMlkfljDA2g_8E|>Jq_Tz`R$NnI?N;El`RSP`%2K(wpTj!PK zE}_gik;|M1@X^=Gy6KU0ROYclkIq_UTJ*pMBJ|Lpk42BZF?w)^VMJsc^q8}#YMT#w zNS|Wu@RJJYQ3gHgXe*(Q(80<6M)6OK(L?&bv{5N?OJteIfw{ER*X4kPAAR0S|DPlM zdr?KptMp~zgHkCgCJ%JZC=}q=lld}c?Etni`nr~8So?WJj%dV7oz7dcr{_=0o-cL* zmr7a@%(?u|*U`D0i~42NW#mm?gC05+ztpi-@>q6*L7xb1EO?^8gKRh;efiW?Epb>h zV6c8uzXlxE@0fhh>H7*;I>=Loi_a&eJTLOW_w+w6M{u#ql>Ww9P3w1pT+rFyZ_yyf zrh%Tvm-?x%P4hwreN{PtRhR)Kzq-Gg}3oP_h;!B z@D}gVjp0lkcO!ajSyT?MXc6u>enq{QbSZ1OF&@x%CeZ!0ujsD5l|V1-SHf%ho*0eZ zi_vJmO(Xq}F<7H~g{EHat%*3N7w{(Lny9@e;OT)oS3RAl#tfY1o-Sc2d5U{Zljjf2 zm~>~9JEnAz3&1o7`m(P#bHcQg`2l#RmHlMG?~VmF3_B~>OA0In?3*s5{CK{C*j*>3 z^hqs9`iK4(=~t4z`5&i`mn~zfwvn`)Llk=aE3nX)HX7(3(hhQWW}FYJz%$N=Rl@V| zpR`Gp&<`H8ek1!e_|W71#LzbfBZH()9qC>LJv`g~>CwgR%KJ)~6F?%AnEdTMz)S*&1mqdOAZ46|L zQml=mR|Xl&JFw@X$JufRITc~d+vMvd?|bAGUiXl`Snvv6g^cQ9ts5A`zePNK zb))F$HKcK%oBLK?C3HD1^s?xu1EbI--XG$!hc*#iUF1$8&0_lc#zcKxNB#=$>hK`@ zyDWX(>VxR(S_b+Wy10HheFM1pZRzjK4K4k>ka4-t;$8jdTKLNk+)n}bC!AXhLKm_5 z3T-s+UoyguZ6`xPaT7ehd8OK-VP=4B3>?0~>ACbMeW$1(h z|1LH(doEiY%X3jI&y5eAyZ`ksVv|T{bLCz%M%uOGh-TrYSz`dSLjK9TT%-M?pQ;h9 z@IV1=HJiQXt76dNyt3r{ ztckB(d8d!GvrE{kE8`XX?iHRd>2Io>erAPRHF_SP-rA%QGvF0Jd?ItC*_5T$p-)W; zW<_G{BK&IcYHUBMfgR*(Nf(Um|2X!D^a0^tbHGD#p9OZ)P(O1R?erVY&W;j09`q3U zNn4BVV)X^)?$Ni;HhqV9!rRyfR4HxWO23wU4wPf##jWpu=^cPS%OS-o6^Yk3nUM7~7&N0SzfR&(Ifki8zSMb|EndaSuKGI$*{JixsV zdMqp+7o@%pY$$@;TI?tiuA$pj<7ds{7!t)47^Mx_%Mi028|;tC&yqKE)H!Ze0ZNT z`IT{5-5Z`h^}d|jZ{6TKA^X&U`(!_}4cufd>{swG{Yfui+&Qy$f$)d$jM%G$rk1=U zUc!Su#w>n!q}zNiJT6YLA4S47_&Xwc^sTz7#pX#;wl&X+&6B$Qv3XLr-%DMxCKOLU zkgnRS#={d+$ix-$f=%jTrUW=Yyhu?``^f*ah zLzqr|qRUA-8G{YN)~k7AlzP5W>hOY3^z5~x1&$~-wN`NR4aW|BSyN@re{Wx~{=}1& z>wmswLBS&LwjH9Q-^yL|oo&`ojCT+4MVE-%v@9wdqd#426t+(zeJV z=}Rr8$XcKDGk!~6Z3_F!#Xdqh3nt>d=)qoOu@~LM3!VSbe!uuwC;6`*j;tt5nhmX2y%BqHQ}Qx7y1YMIU1ax-zfH>watNErQjhjrpQ_Z z_Hu*u4LLg>lrMAThfu|MrEqG4+U*akF>FhZX z{AlmKmOsh%)84i}xYmlNy=}jG*7E-bzwnHrU4`G4zz@Q6NwoVR_R1ttruLYO3EX)@ z|Mij%-djK#i}&RFM{KGg(&Re_ERZz9UqQxViA&_mcpa;$!v)MzRt4otc_Gpo_#25s zc2+9(u1J`lu!kg!_E$-ESdcJl%_vA%aIKXtL|DC~Q#F-JJ!^%%fnVzX6L*z}oFZRa z4fXnHLxXx9>gmcdz60T*I?nS5KZ%XwAo5L#ESP57wq+~?7h8rSPdi8}GFT@+{lMa> z0`eV@e3TU>Uh0zbLG~Dc94EdbCO4%l_{)Mt>XCNqtaXeKSe)daNPg)b0;d87*5Zy@ zvL*qBwJ{hDkS`8{)Jh2&sUbo1o?sYuuO`p<#|04I6uXt5q@?GX{ZQ*4C> zwDk9iCxk+(PtgIW#T7{qW zbr*L6f5@A0UbUnR_-|6q(!COwxX)|hJ@+&$WWCFuCA`DB825z8Sdh4u!y0Rw2Y6&H z=Rf3~I$)=9Sg-LEy-E8@U6F#ls~Wj;M()FryKsE8m*m;5dv5lzE*lT8CR`Ez_4S(I zVDLEO9wTMm##%A=a*QNhmYj1+q}vSix`o_jD(lwA{w!;nvM%Ilo|78P(%4&afH2F? zn{MLYCu!JkKL>x{w*FR_#P5%#JIz;#&K$ILhoINiU8<2)8tw0u_HOKNUWPqz9B;o_ zdur*|!n+b5-)E-Lw=F+?+Wy*iXI90^QS@cug$~UwSH@o1@8jFLrn@ZKFI(zQoXep{ zp*IC9wO+A(WNRfpZA8Smae*Ul3xuyN|xgnkChf^U3&X!E5# zAA45%E;fP=&V+e^Rrgm{>e2NJBu|j`mN4OI@vnvM9o!9vp4g&Aflt!$yBhfY8sipe zqr^i$OD7N;mFNXZ;)(Oc^AoQDtCgSMitsp08o#4Bk%^x>Cd(lCD<)- zzLj~_+on9w+6a9fK0%)lJ~W_%LN4SpE*R)O$gnnNWNGEj?}QehE16#G!3AS_h99%d%#oT z(Qo2mHxnkjD}6)Y6#kPokp3-x@NTpE1!eahR$b{upHjnY-QA0RVZHs5?6h?GAn=KO zLh>;VG?!QaBVbgHtsxiiX=dsu!Sa|r7#4&@vnW&3sVXw$|BjFW+fyALRC7sj(j0>Wo#6EtK*_oZQ6jf$MxZ>+9a*cZ%NM_&1&~}zSvormW~N^ZQ9@e z<2d&=AJt;zu<2;#0ca@Y9neCRR=F`ag3z~{w!qFAOU^nn{*PooA#c=xcUFAd_#)wq z7;SHrQ$QZdTp;^WWX#a;$NQnsc_w`oUK_QRK23Bp&lJe7BFzv5qy_ldSmzYQ^_dYWH? zkL4@z+(+9ae5@i5GiTkgLBhN})*pY|Is^LKa0p)463g*lY^q_Cy38~5g(U7HC2pPc z3*OC>-|;>%3%-#3TGFPS^w)f3=vRFysd)v^A-1=q2J1x&Dl=%NfqV&0G&?uw5?+- zyPDr3JG|t__AKRQ$sK@+XK6)_oN&0Bc~8W8NBncf_Rk#7W_!P*R&Dt>jt@gQHhd&KAEEI<8MOARfk($&x^-mDHSvf~!2FO`+&W=RV#aK}zF>9FO0^-fU(a%iFcU29L5%mHMdp5QGw_kE1DANF~6 zL60w?hukIccW89V;ckA4a%3N0(>+^PAJ9E37CY5wFK|txE{i`)CUsq{PL39xMc`c? zgZqZq_es778P~PPpapy0>n_(;2ffgzFK62a@?|Ut4&j^6cNqLsqs&KU>0x+l#ba|F zyfJFOqnda}$?3axTXa*#hD!FFr}8H3{0-Pv;MI-FaI=r{+&8`j&ORkcU5|2J+X);8 zcvGqI9_MQRO}A}hUvZX_dns>X|GU^R{aNM@*`IWPv*Pw1T)p{e`k3J60T;o&2%ZpL zlHcEng$4NDK1YRrev=lK{w=mpiO)|+TM$b-i?7`8aX)>ExfSj7Rr{CWr)<%KDmSus zIAZB(^uZ1JWEC3b=+Zd&cb79GcufGkJ zukNXNHi5Q{v~eRcqPv}jE3=WhtTwL(A7+i+qH)Exbpq4&JoT>PNwwis?gN z*DJPm@41hcFXx7qC)C>;o^mk`=OShHEtnT~#owfouiWPlx8b8J$eqRWL!`rP)F=a7 zy7X~LUC^^K-p+!b*LmJpTXxy!+{9icvO)5R4tou0_9dNXdMM*WdN6A*uq2*Ci0}3G zL*G{D0DON9qR-4>JT7D0*o_}5jUL<%{Dnc)>@yU$ zrW;?}P8}*^BQ^lSc)!GOm$c`nVJCu*%j8Ve8d>9N-4IL;iJS=UKyFCgaa}jMOk+J_ zLt96HH}2Vw*eUNR^Nu()JEl~!`8NGEJ}#l-)Bbk&OzsAY_nkL^N%VigHy&S2{n{+s zt~QIbVw0Ie8~apEuFwnmA1kALX>ZAUz4S3?FcDp)+)F<|53%p{xBC@h+1yM$@L*9~ zrX6z%3@?X;C%XBZ^}~gxh)OZKW+Vi&vXVc~zyi#0FI^E3;* z3w5n|t@Jhh_7~UacOKW4%RPBo^TMo}Rgd&g3w*>qNWBYn-qSWDPBmLPm6c9!7Trwa z{y%IVH~GPtyZ5ZL+k4n|#x*AO%UYu+S#rg%-$5PD`3sX4y|^$dh&|svlOA6D0pubZ)7v~>iedwZD1d|PX%jM?IYZy^fy0ujJD2ged%x&Egbybs!zFdY~kg_ zD-Pa*9VqpRq2#%F4)e46Wk$H4>boL<+!^Io@6L6qthLx5wj*18+}pE(^}GqH_t5~~ z8i&y}o3}N&Bl^uUrB(=i*U(05iHmZd(!v7tfAEP?SG3sZ%2)l4az|D3a^5#4{N4VH zEs{RO-9L4_lQUcO`RiI}y9(W<8d~`VzQ=pDYK!9{gLf2+t~r#Y^A>wx@of!-%JCn5 z>N~_ei&akJMW=y%obgv=eTO3tS(?*~oMHU#eKhoU>>~feoMAg@Zlqph*U>3oo}F2D z>g-4poH>Ylk(~D%a@Ma|5kHrB?oB=_{T$dg zPhg*0GV||J%B#XZTcsRbpDZ${@0;8O)m)3rwdY8En|1Dvy+ih07f9Rpw#xrm0XocJ z@!R#?Hu$T#Z=wxwcZLyOt{f}GHpac&?}|>bMo&I^BVP%Vv0=OJKI&kO7f|jM0dUw3 zY@JPOa_M_V%dK?DM-Pf$Ic}11_f_!uEo~;{aAt*j!rgD4RjEgX=cG&xyaYel->xyv zIpNQN$Sbi)tmPb{@DOruqjlfTsX^SgCH;BlhHaeJ_Bn%DGA>lnZ)IFAqb}AJs0&!& z_d?2%GjfUJp6F7X{cHBa8$omjTi4lP>7uqiklnm+oicBL-$ec-<`urmrVZq5Rk7%9 z-^IR(ED-$*rEO-Q$o4P6&mEXEgYZRAx9t0s{z`3ZTqcQ*HxNAMB!on$U`ie2IQO7^ypHb5Ct?wjb})ejnB?9D66 zXqVZ@4$&{_;8CGp4ScIM3^s3Ky=4z>D|VVj@cb{zlrhU5x4ybtKyVfPKxF!7@UL=m zUpz9sgEDD5^cAgHPsMf*j{l9V9EEVR=rS@FknnwkS^Ymj{w|~+u{UJ1U&sE+J_U`k zHcLLr5SmK9*T}c9m(eBdDSH?M_eaPRFIUpq?eZ0@0;j+$u#N)PEr-uHH^tgEQU1S2 zSQT`TvW7qdfk)~Q`UUj~`?zy$fucScLuH<0z&``$1+07a*U+ZHmBHNE*yj{$p{1k~ zntcyCp1DhP4X7O7{^un>*!zC1`XmHi?>DGVL{>)KDtsVa3m@#OhxfoU3VQ(Yn>Et= z7XJV>al*b7ctP_2Ser6>vu#^wlX&jgZ`^LE_QP^lsN0~NQpza{pSjEEVxLQs)C=D= z3J*$p`i_luH&vHy%)rrvZis!iDU3^;-3!x5#r*6~|tApWRh&Av5b>^)e9 zLv8jsxcd-S_S3u>1<5;dOKGbz-p}Mcfh>pYQQ?j=hpb_;KA^KMrf0CG&0X&j7NEW5 zOWRjEh?BJf2Wy{JIBT6=!llir*ZLlTK8KO%Khf3ZNVXE$JQ91ayx|4ECN-bIZbv;U zecth=mMpeReuwzYT+OxCgJPW{2CqGTAYSgGlXxHHPKcEo#|MkD75^!Cjf9tu z)2IA8`{TZLhk%qRaw_zxeW!rbmli@=l)UR#o)TU{t+p!&}ns<-I{~nz2dz26ZXw z5|^*kCkA;HFi6=FKQv=pdynbk+Ea$8@CAI+){kpX9j=9Yc8qJk@W8nCo+WztD!v)G zbi)yzA05{|HFI2h=0In-hkIoE1qS(txx&3FiT96d?=>zdoH1iu`zNHynCK3t@V$@l zlp)FCoB93x>r#G7xaXVW+CReeEa?$WUpKCOIC1GlYB&XWG6$xGdr)p_>3GWS8NS>* zuKkKVz&5g1xEH_EBT`R#c%vdME@NUwc&ZOLa4ADF!-7}J5FU+z%7qDCxTlZxRGaA1-NB{TORdH0yon7NjGsaxaEOc9`#HCw>)r@ z@~47Z9=J*Qmx5a!xJmh!fmAgG(Ff z4EI_`+Vv&W@%|F_z@?2$ z5BKVzd}L$1jZ%yp@W~-hDfr}oPY!jIflm(jeY|0}hvgPagP4+g%PmdEg^$ zcLn&+cGINIt^}X{;L{%%t^%L_;L{&GjILfCIaa$Qj(>;q9pMkocZUCZkt_V+n56JW z6Wrlrlas^8uSyA@xVA_5^VzB4lQ*P=zr3Yq_|zS}!dayy?Z=m>uA!ds?Gv;ckNX%; zQ=Wi!j3u)*dmjFmCgQcbUQBtSzqJon=%JRA9Okm@WgR%Yo^N@Tnz6S6*pO`>8vwwE7Yg2~)<#Pgba| zdNPv;Tm( zh~R2fJk%J=X^_UiG+C=*wbXHNE(i!d^0N;@*7k$oV4wME4G{cgfh;ubY-3(r_;7VU@S&VXxP) z;1d1dZpm|Qib<* zan|0z$t8RLivGAO7FJGs+?1@|h3~C2wK4z8_;uQ7IQ%N#PHDe1W3QaaSx@^-U_M#M z9JPuzq}~3C-2mR!n#CrFZDsQs#rz%nhuHGqk(sVEc7kaO#w+x&Gwc51&PbKAlmw z${DLqU_MCSa*$3V{RDN-aly+#)~H+io9{6PEfxE7@_F1x@P6`a_6msHEhK&6sWr(G zFE)@MebguELOsk2$Eon}iCTC(dhkcsDt`gIAAfIB*DdJO9Vtf31T|nm1in6yB6rHG z&F>Gjb>j&tX92jeHzK{;J}+s+A9eJyZ2BK-Mwi&nzpBfiu2SmaJxy?lhmViJ5U=|x z>WSAabsWgV4u&j=QnsNc?2~e34*FGoyId(#-p2AV*N`@^B5z!ubjW*R*y%&?iK4B= zZsCJJozP}BJQGV>>81@G^X8TaKX7kW$r9zdS>~jE<+@DD7uwH;ze_1w{4zh~UJ7fD zD)ZJPrM)Tp-QTBvk&j}79|%mg40Cnot3EZmL_3vVB6nkdy-Y1up2VHL>sQ#2wIZ$J>g@Yjh8*5}Th zH>zX;wuu1vy-vHz-mAChpR&*S(R+*r?&x~={UpwC5$4ykQ@d@5mfh!7%T5zzUL|+J zlXg0`S9!qXr#v6rNaJFot}u!3>U-U|UtW_}}g z7;(;8-j<;KD|Om5m-U)fS@(&s{=|Fi-0LvC0GiC6rRFcs#lFjT3g4<9a%%&3PnE{r zXBV5xcc8@y{p1+`c-|L~y_v`Ee)#9Q(IxMoiQVJ-&XX^NutV;YG0)NOP44%a-s#BU z{;u32Ss%jAnyrv2Cp5~qFtLnai`bp23pfK#Uwr_6kvgRO4+yvHRXawmkaf><(olw^ z5gT1RjnG@{%p%XTfprn(bOCG5r*}Vm8?e&8ZM?DauH0QEYl^H@moQHrwMExbPwJ*%QPMTBHHI{VOQ`a*NvANp# zN7-kjvG@CgBd_QR#{N%%QTD0`PESzJnpizjhU6EVx?=T6`G?q}^6%7j$l8Zu!_Iz{ z5(6DfV9!Za)1|DD$Sn)UwjrivyQ1BG2Y)w0iz>>NJ+(e)=C|5SFN(t_wn%|*FtAyB zXedj@1i`BcIw$07k+HT0m_@D%ZKPZ&Q*7m8yA;|;yPcDUG9-=Q6;C6039Suy^N0LK z9?3gL<}7|&{07`s{oew&z%Ru%R z9pWw!_*!7jaqIm>mSVTh6njA*e$#KWb>*8Cv8)+KUO zWVViso-HyO+R_I{ikuc1NFTOr0y<+-0kV{Hbj{p#*eo(^339fY^qmf8Gv$s=rmxLC zHoL^hSkJp4qx{HY%CT$^lFyHR8-;g7F3Fl-0d-Q>D6dj)T5!bbl(A061{n+DW?|XCX@36Q(_MI3DKk2vQOIXa2 zzs+;)?}xGPwAgpgJUe{<_4e0@`ER?y_CI~2{iO(|H`bs1J$BXt4BmF&`hp{`pp{yx2FE{2S$E#N%V%ke&OR>Fn_CYB$>c9S1dv7`;Xv@rTS-|`~PIqyX1ZQ`~06{?GW>OWBzzKD`V;Z z82dgJ`yMQ@`RJqA_hjs=kF~?oVqcZ)N&c8Wq0{#q%AJ;;m3`iT{Gy^h{fdf;&i54( z{>I1ew6%Zydr9{3AEW&Dw~zm-l6wwRs-3pE{)|#T!QFtHhr98Ny5Of}S62S?>Z*Ct z?oQRqaH;bQO-*KFeHtQ4{-3MHs}a_(G<7N8CPB#6qfdU%{QPuJetu@ZJT>U*tJT$4 zj~G9msC(6G{7bU_e@boUA2q5+`PY6{{=Zv2%s;FUxD)&*T=ykT`q6VZ=}ULxgqm}4 zLWLPPVdBX+!5@7>v96&?aMI2raH+WO;L>nIaXoQ^anjllfTydN-Qa|8k)^61?mQfJ z4MaCLP$&G3$4S}&IE1v7rw?C&dl*0q+~>;41gapD1oMe>EwrCdSan0!G% z+FcNsCSMSc^2ug>$!4XO{vqiEZz)gkmGpw2q!;|8T)|KL@+W@DBkfg!n~S>@w+Htg zZa?mixG3%*?gQM1xDz-5z==!7rQtGgvRIjeV=u4r;s)Y|<3{32a6w!hZYAz9TnHz4 zJ8{XlG+YKw7Cv)uc{nd_AZ`dwkh?|C6DahiSIKg2qE)H)TRz)5ECvXakQkVQC zVfjbU)=Jtd1}z zVabFoCoGw;<%A_mmJ za0(Z378NRl^Cl z9&jaR2X?vePga2e$$i$Y(56=JKHbNYqV#)TYn>d>KhJ4!FFo6^wXb^e!9bHMtHG@t zg-M?%PqK1o<@IH*D;KLr9}Mh0pnmn>rltEz8(lQz)BI@X)IDcByHB3Ids*=pAE<_(i6Y{;KJ8@6Jib&J??LYk_O_=taxOt=CVY z&Slg|n%!rbn>wc+JJUd&ra&0t(c6;>B2Iq%b`C^qBT2Nbja+mJueF}>{=~FmN>r1}AwUb?HXI4WG%`y0mYw8|(r-=cy zVZ~+p`!cY4Qd0id#JAzzdrx|LMD@PJc~al}z~i2#2bLaj79wG5C-+t^r_1%(7lq2H zuBopmto63`b_}fUT?-_Rp<3_Sp{?1R-_5QqD$RCWpk>!y(CTpjS?#b=k5pk2*ZptbDag)BR;YeRKqF&NTTs&RpvBPKheOmH7 zGbwQVa1W0=q{DIQgR}-$RKNS$K+?9PhM%46>2XDzfrp;a8(b&<-tgIH=^odujzHCx z-1}T_JaT{O8;{h~Hyq(`U;WRwHyoKvP2cD1*70v`IKtyR_21v>sOY0Sj$0j`v_7iA z^_f*lV9usK_qqN+34fpj$CN&5P(_1_bTOC$w;t*v5Czgd=yTyxZSs@bt0z5E;b|JI ze)Xs;X=&1qM;%j=;P9l=@f@AU51n~@Yop;w8l)Uk264@5=O2@fZ%W!@2z;Zqj<}z% zvviWDexkbHXs#=$|7>*a8K$d&N_`1?xYm+^F&Q~Lv>Rn0hvL@;I z9=H3nCkc+Y{qywB1-s5%xHM(UV}@hOU}|ls_~Pv8`hR;UCF%6023I7h;mG+)=s0vz zXX>`U?%E(>j|rWfrn4^tzQ?it%|Q0HAq~mZny1%VeNufxuaKi(XnlJ7*;=mK>*;d2 zJ^L%v%lGC!w(1e-ys^7ljd^6IZos+dd*EL&b;~K0wA9KGt^_MpMw0Q2eyoS%*&MRwM-nH>4+&+rdD4q0|O>vw@+<(6@bW(F& z>!vuy4lt^&Xh@!{Jn6%eo+%r8Wkb4=)X+;gJj?0fhmv!fA1SPB|JdaYxcj=(a*OL- zTA{PzW69Ux%2ASP{+|Nh|3%iOz-JDRL-TA(+oX!q__2JHy4O`)@tLFel~){BKH{iw zslvMFKPs-jQ8~(8s`$_=jzZ^8KeA&a=PGJ?<|CK8^Sr)Ytt&im>LZ<-mL-+OD0ub$ ztgk4zDQUma{HUZEmt5?2YPGxE@G2aYzS-jAz>oI>pC$3T>9_feaPUd!M_;ACLcbU9 zed#g7bpGvS;jiB=UAJs>U19JD(k+h^@OhJaqw6J+LTe`t{dH3wGV%V)pTGW>o0dIm z#Gsnqo}38PKI4T)rH^%%Mc#NkRP26FHOS~VZI4q@(Z|j^c;@sqfBI!-`?_Pr<+~gW z;Qc~_=l(%zNBx}TS2j4x9jf^HU5>)Kz(;@DGG}T1mV#wle))velT1tU3S0u;h&teZ zcIxH^#)ub|{G=9TZHdQC|Fy{b2i_^oEZ8}CN7AcBb>WGD z>L$Im!l}l%esad;9CTsrWT*Poz^kZo;7zY-!Wq1x`|m+@2r2cUa;4$sxIrfz0>3P zyt6v_^Uisjj^Dfen>ojRDmf)jO;GTjw7mEBPXDvVBo~zyo6(NHvT=(1)@>^VA z{2ur2Cz{YH8+ard7Pul=q6Awqcoj_40B_TOH5+i{~DVm(;NA{3a_lQ_5{v zw)@e7w~FePmyem0uBs<_l9C2iS0ugt`1gukPwPdmzBqY&eTvJhD6ZI|-&@i1FM~E9 z?$p2PH05&jeBfuNHFeyW1BbX6!K=2O*Ba-k<~nVn%jt0i$3HNk^NG4MiJTF^@sIZJTDhz7_4*Y>buZLC@bTj7>Q_|netdG_ zz!S;zt>o)=rWwnG>!dg6-g*9$K^lw9cjtcT!` zT=BhoYl2gz)&%GM2;UVo!Noti7f91uYl4|?7cbkTY=6D0cK2sz^IAI}KXhh9z1`By zOMAb%_(yA3Jo(Cq`s&HP(8(YBR`h$*!2y-xWuGwu6e_pY`RML5HNo+*95$4N1uj)D z@b;()?k~+N-BZz!l+okg`Zn$s{pW!xo<*OhJ9gF6-hsb-pqiM&qFG$m!#%nwyWBN7 zaEIH)|JjFB!{JG4W$BnBqNlh=7hk(ue{Xl=Wm-kU;Uul`&G#nrO@428!|h+B`)V6s zk+S!{vVSt)FZS<#?6U8ze(X&+{D!Qg(!M``@ZAR+4lh;LZ~Z!iLZjaUJF7IaFZLOa%Qe%MXJec@PJevts<)e%#W&Q=omo4`nKiin z<6{^74xY%WUvcQaTW=WS{{88C_jRvmA=)Fe;H|-LT>9FTuO_{%O>APm-*E5ibNcf2 zq})5b!Ku8p&!wPq?oXuodPxZZr=*t z-@CLSB{<%${q-re&p8<-p<~TtN9ULKo~eDtnRRKs%lYxKTYe*b^Y`N=#mg%?AD(=6 z>-hx*NRR@djB9S;urG#hb^iV|vfJrA){t^*tjv^2{X&5wT^Ww&c3xcXu6pQaf3KcA zhIB8_{VL7W$)xEZ&H0k%`iDAmo6c-?qldZ+3r-C8P?nv?Zl8madQMjl$N3Y7*Sj-U zP~t=>@hd!1j9Mwl+3m9Qqo@ISiNyKz7j_kUl zVc8df!XYPm*!;B1p!{&_4e&`s3)K#qI9#~soeiy*NS!y1Yj6k0hqu-~Bd|dK=dQQH zr;e2HU0ZAzN&iemv84Y`EBv!9BGtY#O8B?=k>+KA`mM^b+pV-C#r4k_HNkrK>DV}N zKbPSQi@Cal-|?`-@8VeeZ3*eJ_&tOL^qp*6`M=@zQT{(GcLa;rlBNdN=UZU;wlGP* z823|LynGe={bfR(8I)H^_y>gj-*6|{B=FD5&HBtv^E5Dw{}x!jElkRM3in_F+y$}U zc?n^ss9(m#n0eM(!x(Mvo~OTQw&z_xhjQFz?2jZvN@N{rfGq&R?+bwx8X8 z$D*I#DS5t1S6Ws+v0~EXDN`@K?D8wFylUF?%KxXmZvk(sy3*ZxIFX$MY?FX-UPl49 z#y3eFhd{`XMv83`7r&5gLZ_s%EXj{Xwj4PI;itX`K61>MX6U#rC`o>L0a%gZco=7DPzdsS~z2xEz@qyUE zjYexM8cIfuWHe=TA;E~z9Sijswe8mg8=3)jU478+57h47ToVk`?`ku)8`VXsa%bb_ zO(@7jbTE|Y8|X2*;|Zg_akCK}M)gU>jf$jkT|5zs6ye=oTD2mXiPbRBm+A|}`mU#l ziJ<{1DI}jb&=-!*q6Hf@MQV*{iWsBMG7?Jl#RrV;P+u&H)QTDg4#0FI*RBzXCc}xo z!4&+gKp7U*Cla{LSjpoG@=&BuVO8a>hS~!aL&kM|sb1tO7VQaz4_au#a4H&3MI#%L zKYyUfVC6`n?*OVyCV^-K_XH8rZrf1bSYw1k1I9ocphu0Nq$$<~v$kSkdYIJab!Yd-{jW)AsCymPL;fmplbllq34uc~$wKmilki=rc3y2%2Z?A7| zZ)j;&EmvGIT_CAYq6bxMP&*pau27{(4kZVp0}&%W7)|J+L@{>^^z{$MqW#qBB8JXi zZ73GoMm|t?$cvc~=}BQ`g%cO73GY6VaZ&r0)21XJWvv(Hk0w#DF?AI98)#Wyg$U zFRGT&AMKAP4%&54F2>M+898FKHPs?Xj9sB2ba0VKA~+ZerGm-+aFFd+q7qVJ+9K7} z1t_A?7op-oU4%*^9^M!3?L#@!=RjD+LdjGx7Vio22%_>C$L}}!vf`^Ee-FwXjRSpJ zJQWYeW4f{#P0?gB)DzXrHhZZ?BWTC9O$}&E2dN^W(~BEjeLY4+YzVGvQ5cySK$Gi& zm`2Z`B)1|OmSbgF+g=JIuPoLMU6;*c)!Xh(-_(;lcfbJb-b*6lHwW-f628 z-yG$<+Ap&=RF#E=)O}P$>Zt$AaJ5<7&MeNaxdVNP)KDlE)EzSBS;6SQbRTMKc4%38 zSTGx05Zh(c<{DN(PdbIs!Kb0Q^G_+u<)gG+BrU8GZgIjlhFzD}SZwUf`hUQ%?!hF^A z!kV~Fr(!kpjEXgPwxBU{ygpN28O5ypPRnZpoEC0uIjY8>m$89)gXxczm^o3;0hh~r z+Sh4BT3hx6np!aJtZy~}Y3rb=69!qHJPe}Ojz-WAXfcWqLjro5Idp*OTw+wiIU*yk zbBbF#s^^h!nnzBv*;(@kJU7oJr>4`^SYO{7+}*Hiw}xaosIg@aLiD=D=%?A9*@u3J zs^4CkBNkHVHY0FlYZI)r25T{Oqs3KS9vNo0n9&6rTXuouk+(KA)CL<{^GJ5@38DvR z%WoFm`WqXrt`BamxiU}OmbThpT|-+Q3G~rM@QmJ!T#%&o>h>mxt_$sp4hXrfVA%a4V@j~$R?H`W|xJdYU!X2YLLiZ^l}5X8ooH#69`! zz5TQjHgtk@jg2%+(ukWiCZIjeYpJ8LJ>WkbElQ9!kdPn^-B}6RjM>y`W>G`r>PR>< zf_A7`u8=hN*R}b?f z)>PYJv|Z6YrxtGw1ZjBYg^$A8Z(B08y<(U)8L&-4%VXNTp^v%4p%;$`#3lzRqXuI) zZhA}B>QPLM>$>|?A?bxln+z~lLwPQD^EJ%L=-Esjk8@v%HeS5tp924Z_XlZ z>wa_J0E>U#H_-XUGP;GP=8cWU9)Cl-(b!UZrE!J7p|Kv*ns97iFd6ReqkWTUrpL|< z*cmJVRbt=fEthN!h6ZCX+d?vXo64W)H)vnAkG2CbIW^kM9Zh3;>&hrnp+tW$1TDQ; zv8Fk0w6wO@*BhA99_XVDqOOC+PV5cp-57H@yx!P}tr^<9i9~6KRBuDlKDrq*v%#o0 z&oI+z&#TMXcLyY@p=sz+roEAQDPo z-zHy{5LxG@vVI_iO`pLy+K67EV(Wxb)GykGC-7DcfQH>kIZv7%1K2exCoCwXun0)^;y@{=4b>hBK?2C?!-UGKrx zaxhHW1eF)@;(Mdn)X?al+KfH3=sWiqr_Z~`%o&C;N@^pLl3s=sicPn_6@|Z8$eYsLPNu}T^s7B?G8P(z)RKYZ*HhX zT%)xX8@tuR3jdu>^V^8^@5LAXw(I+Q>B$SaO!;>&&6XRlnDUw(rdEuf$1*vkjBi_V zGyZiffBrjWxFvVfkNa^w!t%?HoAOSkt;f#xll<7v%y7ETcO7TBMcY@J`ejV>#gQ;U zKoAfF{yQMBlz{DBO|Gj58{hQ8k`nUe{%$EOD zo$IBnci^_Dx6&=A+FuRg9k`(MuGUN6MU1TUe}JFp-C%A;JsxnR2-&d{aca~qS>Bn#1rD>wOUDI{n z!ZHWfWWzp9Z~o!|O;7yF1nij~(<^+Gy6;4Zrnml!xo;DFfnG0!*XDiY0!`mLevzi0 ze|Vp!Z~XlhP5<}b{F$boJEZr;6{kOii^45>_vQ4W8uNWd`ex94)WFOPLc%7G2i@{s zRyDHhyiO&s`GnzF!eO9?DV_evEq|Ic-O3QKXMec8}Chg;%Eoa)sGy- zTUC_0?TMp%shmN#n+2wZ$rkBZHc8K}Pdw>Y(hXkYl&f#WvnVNDn<;k>I4+v9&;xz8n> z5LQXy_;{WtZCu0$o;cb>_n;bI&ITSu|G18{q!vMFJk-m&tw1aJod+CvA==s7pP-1>XW^E9gxpmpN?hflf8U5 zvHgm9?0e_2Z>aqCx4=HmiclB2Udg0S_4*>$E6a#(1SNkSe%$QG(C1NitDMX`9yjYD z{1t ze}VZ1=3ivKiTRh9zl!-+nD1czyUc%(`4i0VW&Q`uhnRnZ`6%;0WxkL3x0vr|{#VTJ zXZ~&GhnPRb{6Xd&Pf|UZn))d715WX&OmAg+2h)!eMWg$SLOTV;|LP;u&@gYA!ZYBPJ$Y2OU(mhOa{EXR zl=SXqJ@B4Z^@^55Pq$OjhmO8-sohQ&*~7Jv{(;k-(Ldzcr&LIpiA4$2QbaMnokIS5;sE+~ICyQh^uq*sW35z%RU*7HA5v|@@MWxxJ3?fd7kk9kLy{pe}h56xpA^NuY0x1FZ_ zk$LQ6-jQYh{?oL7cpm$hcVyY0Ykrfz{!Gs|ta@ots$ZCQWZ9os4mFDB3gSV}{(Amean<40-jm zoYsvqz|ghf8Oef59j)) z7RdF!{<_nPI6a+p!SwR{uHH_fcyTJC4LfByRYhv46!4Nt3HSQOLb zMTKTRM_YYct@#DX_djv89)xICeWoxgKJ95jzI`_Zny*C9+Ha#B=i4CX3CJ+@&%^MC zHfC=G1yO0H_I*0bKGE})S>JKrN%{wQKZE8Ils?Z#h<1=1)EY0c_!9JgB>(8Ne6PpU zr}<1K{s_x4f7(kMy`XyD3aagaYWporn{(1#VWyKtdb(axx>kN*j>7eLL;117iQ4mN z5C0(WyT;r+9;W_)@FTf}UmyCbFXHe>gi&@B{MWdy;ePja)+ZUoE9dml_jFR&Urgs? zFKxslKN=4!U)Qr7`;r=OP%XFiE3J9zY`8$K@q#^zY8)-Tl*{F2mgC*Lx}4Z<7LMdE z*|YEgn?`(%C*{Wq&zDcjPp_?ix9t7K*3a8`~k!1l#5QEaAW+cdrd=`b&V)Gb-zh}VgazAQ@LgB76vqjDmql z)PFq6 ze^d_h;cwxbZyjb(VWJ)W7WM9;Og%B@3*dFR)B1mFjvl3pkDgapdZc2n7sOM2%om^Q z>Adl&U&$Ar`=Bf61WkLSY6t!SeA?DYB-j(Q!>>iIYFHnaWWS1CuZKZQuDis!pk z4)BIDF68i14qwOoxy--E*jQxr-b+-TnzJm7{#}vUZt&hy~YLn zjPkST`H*Io9+}GZBe(o)@zV>5pId&m_(v8JAHV*9SJUN@>mOAxTlvf!e~jt=wT5y3 zca^@H@_GsLi(J|K?e1)T(V}er_Ql!!qC%73#`c_S&*E=pdlv6xdlr8)+p~Bl+j~FT z`+xA4@?G%g(d~!Gacdp$s5#FlaG2>YW4@6266TjNzk>M^=Few-1@o(!Kc9Io^Q)P! zVBQPfUJefU#pAu6PmqI_obE#yM~KH~#(3=`1>|SG@!INtEV~w^`bqZ52Rd^n_h3sHjlH`@iZTL6%`lbziwalc|gwiKBNBKgm|Cgb_x37G|~sv{t}-n zhd66KZ0%nR7m!3{_Ae;^)_mBHdO{7E@cmup#nw6-^Hjag2F+TBTk}`Yyz4akI-YRO zjc={5X&q1d8lbv=`_Hc9-;H&;wLe7l%8sw#s#FQu7hw5M?SELf(s*FuS}*mM+R==C zjGXoHg7z^ieC_+10Ukfl?oMkzPWplDbuR6HmYKg0&b$9f{qOJ6KiK=tKb8GY>R&Nl z>0zDfJ5L;j5v+e#K>Y;mGZSz17kS4y7{Px%kCpv4jYZb}`XPX0UG{#(7Oe3m9WVD6 zkY&mxZ7NE+0H5FIzVm$LVwKNA+X2mU5r?K-^8E`iApGp#Gg&y==XJlY`NyA1|84(X zis~7CFNMudx@Pnbx%0d;IX-f`rSDPozI^WYru4lLWn#YdjkSKU)*Zjk{=llAwA*2g zcMZR%`SI^sKmVBUqv~kKPwJiCgYC4&liB*kKcw&1{ut^T^%vHBYA^c1yG?*I`!lq$ zVbwz#XGk9^nf)2s_W_?ZUiU+f_LC59kp3;)U!mWjb)vHOztGVaQTsSYfwF#^UcV6@ zvwi;*;&Q=0x?X4W0dK++pRIRLL>|{@pS_HE6x&VK@9eDaqh`qY_jULlYR2!obbS7O z9lnQ}@%u$B=ik@idnmo%lKZ_)zs=7v_KOJlQO$flKS^Y-Hx~bH`#)s!*V@0P?>Vtw zoAv$dT>Hd&L4xv_Z=cx8zm?DV_J;`rd;K^@0bK5LeQ#FDddS8^Zhat;l|IoNd?!#Z zbiQY)9}}n-raXWBm_WTS<)|NIf3EMd2rvAuRO?&6FQwn>&Q`z4o|pI2K{MYUS@mDb z4RgOe-|us^yqe{CexIx5K9>7T`}p0n-VdkWKNE2F=R?Ne53XVADe*jn^*o5Zed^~y z$Sz&El;T;>k>q(kqL||3dp?Y9Wxns*O#!y&7OZs0fc^Q8Ls|{~LP7frivL^n1lg=t z`gsp4J_)VoLf#Gk$elZR9C7I9aFqH4^99V0GGEC2r9j${`1UNF#jm?7cu`h^Bb5SXCBYBX?tH{9?!LD{%Pj%T$|>< z$~>NH)BM+&_cQ+j^YzTX$b19yFEQW5{431kxi)R@yUgRcHqD=49?!LD{s+wCxi-ze z!F-7MpE4h1{w?PFnEw^?{mj43Jf3UQ_D(U6=h`%n=h*c80?)N+9?!999?!LD9?!99 zeuQ~E$ENw)n8$N$n!l5IJjbT_PiTJT^OjVntoloIj^{6b=k{e!CpX=>c#`4L(=xK5 z?cn_kMBA9pgoFPd_|SVCDC|mnEE!R{v>fkyAifr#T=`~F!h0bo`~W_@znQ^FzsLda zZyE#o-_7S8M-d92LI(+iV@xBQweOhPIJ$*74-g{w> zZ`sJm@qP@FH{(O=g&Fbj9t{ekzLMx&2FYEmmd6d3EhOPHx%qF+qr!kw{djCcq zxel`4(=nUedY{K^^7+E8_j%;e`$r11-up3|d=7kc{5kOXHrbp5pZ_5F8OEoQe8BbG zvH$bf$tS=3!o*|aU-<5`k3aj=t4}=t)K`x@c>I~4KJmFnBgZCoeB{`pkL}qJIo93t z;vE;)@2EKTkH;d9g^xXofQd)D@%JOgdLrGA_IAJ6-E#-zo1pO6u}IHTp<@#Vl#A+; zT!MfgAP5Kof`A|(2nYg#fFK|U2m*qDARq_`0)l`bAP5Kof`A|(2nYg#fFK|U2m*qD zARq_`0)l`bAP5Kof`A|(2nYg#fFK|U2m*qDARq_`0)l`bAP5Kof`A|(2nYg#fFK|U z2m*qDARq_`0)l`bAP5Kof`A|(2nYg#fFK|U2m*qDARq_`0)l`bAP5Kof`A|(2nYg# zfFK|U2m*qDARq_`0)l`bAP5Kof`A|(2nYg#fFK|U2m*qDARq_`0)l`bAP5Kof`A|( z2nYg#fFK|U2m*qDARq_`0)l`bAP5Kof`A|(2nYg#fFK|U2m*qDARq_`0)l`bAP5Ko zf`A|(2nYg#fFK|U2m*qDARq_`0)l`bAP5Kof`A|(2nYg#fFK|U2m*qDARq_`0)l`b zAP5Kof`A|(2nYg#fFK|U2m*qDARq_`0)l`bAP5Kof`A|(2nYg#fFK|U2m*qDARq_` z0)l`bAP5Kof`A|(2nYg#fFK|U2m*qDARq_`0)l`bAP5Kof`A|(2nYg#fFK|U2m*qD zARq_`0)l`bAP5Kog1~<>1RSn(K;7tA`RWeWOY4sR*-J#dpkC$t#tx-^eCO0u`w>_0 zWrtFa7)rfu-K$lqbZw>D?^V9H5k4MLs(s9n4$!@^+&8|~y)toxDdA%fAg<6lZ5_RU5@Q@y=AcWslM$Ta;#6{pOOff^^{jLjN_F z^UC8cXVnEN9q=Pf_l2tD-rZ{dZii~G2Vdv;N;%no7P>dz;aVB?e6>7m^HX`AE)N5{ zlT%aYS!sOV<;Y6saa%eCNXJTR5z=}UX+4OvZiV0Xs)Bt-bJBfao^Jp<(5jI~io4!Fs+?^v(SAT0h0aeTP{IH<8S9rzgN*s^rs z4p7*f98u}Xv1cbv9>!-am858O&>O?dO*{VGQ-o3^kkawai;^0rDF-wO{0vAFHW31aSLN!lAiQ}C(Mse zExzP9%6}=!`v}Uvi0T2#-vfH@^5U0{pWOPAQob)7KUt>xg_}^X-qCg4Y^Oa`_v8`; z1OY)n5D)|e0YN|z5CjAPK|l}?1Ox#=KoAfF1OY)n5D)|e0YN|z5CjAPK|l}?1Ox#= zKoAfF1OY)n5D)|e0YN|z5CjAPK|l}?1Ox#=KoAfF1OY)n5D)|e0YN|z5CjAPK|l}? z1Ox#=KoAfF1OY)n5D)|e0YN|z5CjAPK|l}?1Ox#=KoAfF1OY)n5D)|e0YN|z5CjAP zK|l}?1Ox#=KoAfF1OY)n5D)|e0YN|z5Cr~&5GZ(46@S+7jdv+^$qARb#!zct9#c5? z>vC0kcooj^Q;vPdasFNqXMa6V<{N+2ZJz!1tW#Z+hVBtieZJdLRf_Wh-x|UBZHI9t zAnr%UJifONyY>BBKG-nSj+bxyp(>szQ{(r-p4VZfXTn{e$!=v*k9y@41zh8B>+qZD ztT~*i=EQk(bY`5-p)Rha^XQOn7-z24;;gfE#4Bf&fqR9s_UOz&I_K;HOE0#n^a9BI z;Jr8_&X4+|#Oo^-nJo-}aI+B$vKTDp|ZyCb>Zt)PqZ)NoJs=!`_`%tZS+iTCkY zhmMb$=PCZXJ|}JBAqUQI^TQ^cw|BE+EU*rCobL3b8+wkimhqjCc`q;4zKkH;xvFKH z^migm>lUOZNylZhj8h)J=W;x(E^HZBko(}90pIBC!%pO>Q?*`-vjq2t;0v7{hjZ)n z*>NKd^DH>)JVf`kWo_Zk^V`xFsw#Kq;lQoy9aY}pwQWkdt8R53n!J#FQfJq68P2LS z(o}w&AxA#B3u_36^e57jbS9k>_k@XSae9)@6?CC&D4*nu8eUu43Aw&ks)p{#*GJe_ zOK$n}1Du;k=l-3#;Y$zEnS$TPnUQ3R%I_C#j)zoAmHz5O&WF@+fiB-P&X~j*lvk}q ze(zYO+7*0Ih^Hv+Wu8kH?Ls*ybx5T*k2-PA-~%^4aF2R$`{pG8y}SoDPAG5D;=Zn}bT(yhP`&jd?=~;oQu-)RMbCu9n_)yIOSD z=SMCbErLJq1r}$)m!H9xG|t9cs}}Ej-KpA_!sm~VY#v<#okh_3tCi`%+12U5GUVr& zGaYyf`X|p$2hKrUGv1*!s`k<3e0@<5?>gFJHVQh%+JY z8+W}(IP@aFQ^2g#<2&ecsrD(4+OH|jbo@ZcU4P?ooVCQy`3?h@V6}Ry7N6L?T zkCZE?QDi7prI6Rdr>5GykWslR<7?%|T}G8-sb@3V_4p0I;YT>1^6O{^Z@Lye{HCT$ zAATLwg}mHpQ2A&K6ZaM0chBp{R~TjDNUbUTA?$cn;gaXvtJ~g-vT%BzD}PO`E9&X( z+^SF>Yt!nj9~#eL-^nYf zo;vO=_uu#z-+aeVB`24w60dLFT@QM{hW1r(*T=m7T7IW@vV7n6;+1c@s;b^_T~zhD ztFmfDIqsr5y%KfVUd|zu8I^PA`jV9w`!2YPFu(n?!OPA8E=gxm(R0SXmOrP?sagbI zZa-;-7b1LeI(%m*>w6IXwM@9Z?7DtC)sDWPR9n8#7RHC2ZeNKqT%$qd-seF3p|l-1Kh(L@H|}@_;~?TVf7?914r7e-D5wYY80b>a ze+DfE{SGL`a_4c-Rj8jX)KA29ehWOs|32%z4!RutPe4ik=b+Gc{u0!{xu(Bq#<{ZS zzY&+(4*5cLb>^5-X2bgY4Av_%_1u(OW6G%;{^_BSrzR$M;(SyZOK2SV1+b!V zL*(OmhK>gHya{2)UFSS}2>qKEVP?3a zirPXIWW>`wwP)%VD_Eb-+Esie>eu?cIUH2;8FHrjEUv(a+->}ZvUF-3kJc9Cnko>{ig3jt)4!fOeeB+;7 zq)NvM)s_>k<-p;bhY8p0vv^hM^5NxG%E0)Kb7n8rKAC6Gp3d2`uVD^DbF%N@{Mi$? zoK-`4@bVe9K7`|3+Dki~E#p*nG|$of+#++%W1v2E7V$mmWan9Yk9yfz%J-;io#*ns zp)zL@uRuD4N&l&-PlwJ0mY6@F?d^Y_+7!*bfWJ96bnE#T%{eKI+AxJv8}<$_EB$r2 z7Cg1(XCM6YQ)r{*ICnR(x{Y+th5fDg?4f+T=SaD$OqDvy%G%sz#cit0)8@q-ODPx4 zVXAzv5d!Y&f|tuN&;Cdnew=WftFiwl`1tZ7oDp5B_S0F`3TaUNz=6BtIP3X5XY6kS zjw81RsEs`197{aCVJvav=)@$|^9@R&DAgxF02|a66wiY$M?Bm=qAqV5_qo-@X{UKM zu!65gT*jqjD~)r2$wo8cQky)Ec^=if5$D!Ri9YkQI|Ec+RNmIP!q1$|XAPsCQJ52Q z(pktE!qnDZfL~)y_1K70UEGC_*YiyI_kf}64$SG-*L~C5*!azRaW1(Fb}^ zxQm@`kISvxp0WZ@@gk3Bu}5KFv2bZw(Na(G^0JcU#ih$V=PXyt%gR=i6`xz?Ij>BW z6?@KKRaU+Vic7KRcPKZO-%eGGdl&weDL4Ll@U7l*+%Lj?v0AJ=2=O4qqY80friyT{ z)DqkmIUu>rwB4Wu@K={W5%ENPaHUex9ZMJX`x&to6GZ#$<0Yl}LrU)W%eFI2BALLj7uEB$NvAtqvXRAJT$E+?1(gDiq$AR2#dJ zNi`e`rGl^!!-nqfdf`hAl$An>@O9{@{=QWmGQV$C#g>3+4u39!DZa~68{_z63ybgN z_=~Oh>IE}>)D*gUS7!wJ2GuL;dLKASe>y&=t3x4Z#qLnnMcUI>4Q{jiZ)GG}%^cP4 zn%1Se-1N6{n3ezZr_K1a*a6m;VG`@F&$?l{1C(rL;y;-kf9!MF{`xqcMe1;4kFN$z e52w@5j-OkeS$VgNg7&U9@o%w((QS@3_5T6uro;aL diff --git a/5.4/package/boot/arm-trusted-firmware-rockchip-vendor/src/trust.ini b/5.4/package/boot/arm-trusted-firmware-rockchip-vendor/src/trust.ini deleted file mode 100644 index 17b0177b..00000000 --- a/5.4/package/boot/arm-trusted-firmware-rockchip-vendor/src/trust.ini +++ /dev/null @@ -1,15 +0,0 @@ -[VERSION] -MAJOR=1 -MINOR=0 -[BL30_OPTION] -SEC=0 -[BL31_OPTION] -SEC=1 -PATH=bl31.elf -ADDR=0x10000 -[BL32_OPTION] -SEC=0 -[BL33_OPTION] -SEC=0 -[OUTPUT] -PATH=$(PKG_BUILD_DIR)/$(VARIANT)-trust.bin diff --git a/5.4/package/boot/arm-trusted-firmware-rockchip/Makefile b/5.4/package/boot/arm-trusted-firmware-rockchip/Makefile deleted file mode 100644 index b712a353..00000000 --- a/5.4/package/boot/arm-trusted-firmware-rockchip/Makefile +++ /dev/null @@ -1,49 +0,0 @@ -# -# Copyright (C) 2020 Tobias Maedel -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -include $(TOPDIR)/rules.mk - -PKG_NAME:=arm-trusted-firmware-rockchip -PKG_VERSION:=2.3 -PKG_RELEASE:=1 - -PKG_SOURCE:=atf-v$(PKG_VERSION).tar.gz -PKG_SOURCE_URL:=https://github.com/atf-builds/atf/releases/download/v$(PKG_VERSION)/atf-v$(PKG_VERSION).tar.gz? -PKG_HASH:=bf352298743aed594cf2958dd588e06ab6713fc514bb6f809bf55a85a87134c1 - -PKG_LICENSE:=BSD-3-Clause -PKG_LICENSE_FILES:=license.md - -PKG_MAINTAINER:=Tobias Maedel - -MAKE_PATH:=$(PKG_NAME) - -include $(INCLUDE_DIR)/package.mk - -define Package/arm-trusted-firmware-rockchip - SECTION:=boot - CATEGORY:=Boot Loaders - TITLE:=ARM Trusted Firmware for Rockchip - DEPENDS:=@TARGET_rockchip_armv8 -endef - -define Build/Prepare - $(TAR) -C $(PKG_BUILD_DIR) -xf $(DL_DIR)/$(PKG_SOURCE) -endef - -define Build/Compile -endef - -define Build/InstallDev - $(INSTALL_DIR) -p $(STAGING_DIR_IMAGE) - $(CP) $(PKG_BUILD_DIR)/rk*.elf $(STAGING_DIR_IMAGE)/ -endef - -define Package/arm-trusted-firmware-rockchip/install -endef - -$(eval $(call BuildPackage,arm-trusted-firmware-rockchip)) diff --git a/5.4/package/boot/uboot-rockchip/Makefile b/5.4/package/boot/uboot-rockchip/Makefile deleted file mode 100644 index 1e81b0f1..00000000 --- a/5.4/package/boot/uboot-rockchip/Makefile +++ /dev/null @@ -1,304 +0,0 @@ -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/kernel.mk - -PKG_VERSION:=2022.07 -PKG_RELEASE:=$(AUTORELEASE) - -PKG_HASH:=92b08eb49c24da14c1adbf70a71ae8f37cc53eeb4230e859ad8b6733d13dcf5e - -PKG_MAINTAINER:=Tobias Maedel - -include $(INCLUDE_DIR)/u-boot.mk -include $(INCLUDE_DIR)/package.mk - -define U-Boot/Default - BUILD_TARGET:=rockchip - UENV:=default - HIDDEN:=1 -endef - - -# RK3328 boards - -define U-Boot/nanopi-r2c-rk3328 - BUILD_SUBTARGET:=armv8 - NAME:=NanoPi R2C - BUILD_DEVICES:= \ - friendlyarm_nanopi-r2c - DEPENDS:=+PACKAGE_u-boot-nanopi-r2c-rk3328:arm-trusted-firmware-rk3328 - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk322xh_bl31_v1.49.elf - USE_RKBIN:=1 -endef - -define U-Boot/nanopi-r2s-rk3328 - BUILD_SUBTARGET:=armv8 - NAME:=NanoPi R2S - BUILD_DEVICES:= \ - friendlyarm_nanopi-r2s \ - friendlyarm_nanopi-neo3 - DEPENDS:=+PACKAGE_u-boot-nanopi-r2s-rk3328:arm-trusted-firmware-rk3328 - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk322xh_bl31_v1.49.elf - USE_RKBIN:=1 -endef - -define U-Boot/orangepi-r1-plus-rk3328 - BUILD_SUBTARGET:=armv8 - NAME:=Orange Pi R1 Plus - BUILD_DEVICES:= \ - xunlong_orangepi-r1-plus - DEPENDS:=+PACKAGE_u-boot-orangepi-r1-plus-rk3328:arm-trusted-firmware-rk3328 - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk322xh_bl31_v1.49.elf - USE_RKBIN:=1 -endef - -define U-Boot/orangepi-r1-plus-lts-rk3328 - BUILD_SUBTARGET:=armv8 - NAME:=Orange Pi R1 Plus LTS - BUILD_DEVICES:= \ - xunlong_orangepi-r1-plus-lts - DEPENDS:=+PACKAGE_u-boot-orangepi-r1-plus-lts-rk3328:arm-trusted-firmware-rk3328 - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk322xh_bl31_v1.49.elf - USE_RKBIN:=1 -endef - - -# RK3399 boards - -define U-Boot/guangmiao-g4c-rk3399 - BUILD_SUBTARGET:=armv8 - NAME:=GuangMiao G4C - BUILD_DEVICES:= \ - sharevdi_guangmiao-g4c - DEPENDS:=+PACKAGE_u-boot-guangmiao-g4c-rk3399:arm-trusted-firmware-rockchip - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip - ATF:=rk3399_bl31.elf -endef - -define U-Boot/nanopi-r4s-rk3399 - BUILD_SUBTARGET:=armv8 - NAME:=NanoPi R4S - BUILD_DEVICES:= \ - friendlyarm_nanopi-r4s - DEPENDS:=+PACKAGE_u-boot-nanopi-r4s-rk3399:arm-trusted-firmware-rk3399 - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk3399_bl31_v1.35.elf - USE_RKBIN:=1 -endef - -define U-Boot/nanopi-r4se-rk3399 - BUILD_SUBTARGET:=armv8 - NAME:=NanoPi R4SE - BUILD_DEVICES:= \ - friendlyarm_nanopi-r4se - DEPENDS:=+PACKAGE_u-boot-nanopi-r4se-rk3399:arm-trusted-firmware-rk3399 - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk3399_bl31_v1.35.elf - USE_RKBIN:=1 -endef - -define U-Boot/rock-pi-4-rk3399 - BUILD_SUBTARGET:=armv8 - NAME:=Rock Pi 4 - BUILD_DEVICES:= \ - radxa_rock-pi-4 - DEPENDS:=+PACKAGE_u-boot-rock-pi-4-rk3399:arm-trusted-firmware-rockchip - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip - ATF:=rk3399_bl31.elf -endef - -define U-Boot/rockpro64-rk3399 - BUILD_SUBTARGET:=armv8 - NAME:=RockPro64 - BUILD_DEVICES:= \ - pine64_rockpro64 - DEPENDS:=+PACKAGE_u-boot-rockpro64-rk3399:arm-trusted-firmware-rockchip - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip - ATF:=rk3399_bl31.elf -endef - -define U-Boot/rongpin-king3399-rk3399 - BUILD_SUBTARGET:=armv8 - NAME:=Rongpin King3399 - BUILD_DEVICES:= \ - rongpin_king3399 - DEPENDS:=+PACKAGE_u-boot-rongpin-king3399-rk3399:arm-trusted-firmware-rk3399 - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk3399_bl31_v1.35.elf - USE_RKBIN:=1 -endef - -define U-Boot/rocktech-mpc1903-rk3399 - BUILD_SUBTARGET:=armv8 - NAME:=Rocktech MPC1903 - BUILD_DEVICES:= \ - rocktech_mpc1903 - DEPENDS:=+PACKAGE_u-boot-rocktech-mpc1903-rk3399:arm-trusted-firmware-rk3399 - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk3399_bl31_v1.35.elf - USE_RKBIN:=1 -endef - -# RK3568 boards - -define U-Boot/mrkaio-m68s-rk3568 - BUILD_SUBTARGET:=armv8 - NAME:=Mrkaio M68S - BUILD_DEVICES:= \ - ezpro_mrkaio-m68s - DEPENDS:=+PACKAGE_u-boot-mrkaio-m68s-rk3568:arm-trusted-firmware-rk3568 - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk3568_bl31_v1.28.elf - DDR:=rk3568_ddr_1560MHz_v1.13.bin -endef - -define U-Boot/opc-h68k-rk3568 - BUILD_SUBTARGET:=armv8 - NAME:=OPC-H68K Board - BUILD_DEVICES:= \ - hinlink_opc-h66k \ - hinlink_opc-h68k - DEPENDS:=+PACKAGE_u-boot-opc-h68k-rk3568:arm-trusted-firmware-rk3568 - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk3568_bl31_v1.28.elf - DDR:=rk3568_ddr_1560MHz_v1.13.bin -endef - -define U-Boot/photonicat-rk3568 - BUILD_SUBTARGET:=armv8 - NAME:=Ariaboard Photonicat - BUILD_DEVICES:= \ - ariaboard_photonicat - DEPENDS:=+PACKAGE_u-boot-photonicat-rk3568:arm-trusted-firmware-rk3568 - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk3568_bl31_v1.28.elf - DDR:=rk3568_ddr_1560MHz_v1.13.bin -endef - -define U-Boot/radxa-e25-rk3568 - BUILD_SUBTARGET:=armv8 - NAME:=Radxa E25 - BUILD_DEVICES:= \ - radxa_e25 - DEPENDS:=+PACKAGE_u-boot-radxa-e25-rk3568:arm-trusted-firmware-rk3568 - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk3568_bl31_v1.28.elf - DDR:=rk3568_ddr_1560MHz_v1.13.bin -endef - -define U-Boot/rock-3a-rk3568 - BUILD_SUBTARGET:=armv8 - NAME:=ROCK3 Model A - BUILD_DEVICES:= \ - radxa_rock-3a - DEPENDS:=+PACKAGE_u-boot-rock-3a-rk3568:arm-trusted-firmware-rk3568 - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk3568_bl31_v1.28.elf - DDR:=rk3568_ddr_1560MHz_v1.13.bin -endef - -define U-Boot/r66s-rk3568 - BUILD_SUBTARGET:=armv8 - NAME:=R66S/R68S - BUILD_DEVICES:= \ - fastrhino_r66s \ - fastrhino_r68s - DEPENDS:=+PACKAGE_u-boot-r66s-rk3568:arm-trusted-firmware-rk3568 - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk3568_bl31_v1.28.elf - DDR:=rk3568_ddr_1560MHz_v1.13.bin -endef - -define U-Boot/station-p2-rk3568 - BUILD_SUBTARGET:=armv8 - NAME:=StationP2 - BUILD_DEVICES:= \ - firefly_station-p2 - DEPENDS:=+PACKAGE_u-boot-station-p2-rk3568:arm-trusted-firmware-rk3568 - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk3568_bl31_v1.28.elf - DDR:=rk3568_ddr_1560MHz_v1.13.bin -endef - -define U-Boot/nanopi-r5s-rk3568 - BUILD_SUBTARGET:=armv8 - NAME:=NanoPi R5S - BUILD_DEVICES:= \ - friendlyarm_nanopi-r5s - DEPENDS:=+PACKAGE_u-boot-nanopi-r5s-rk3568:arm-trusted-firmware-rk3568 - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk3568_bl31_v1.28.elf - DDR:=rk3568_ddr_1560MHz_v1.13.bin -endef - -define U-Boot/nanopi-r5c-rk3568 - BUILD_SUBTARGET:=armv8 - NAME:=NanoPi R5C - BUILD_DEVICES:= \ - friendlyarm_nanopi-r5c - DEPENDS:=+PACKAGE_u-boot-nanopi-r5c-rk3568:arm-trusted-firmware-rk3568 - PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip-vendor - ATF:=rk3568_bl31_v1.28.elf - DDR:=rk3568_ddr_1560MHz_v1.13.bin -endef - -UBOOT_TARGETS := \ - mrkaio-m68s-rk3568 \ - opc-h68k-rk3568 \ - photonicat-rk3568 \ - radxa-e25-rk3568 \ - rock-3a-rk3568 \ - r66s-rk3568 \ - station-p2-rk3568 \ - guangmiao-g4c-rk3399 \ - nanopi-r4s-rk3399 \ - nanopi-r4se-rk3399 \ - nanopi-r5s-rk3568 \ - nanopi-r5c-rk3568 \ - rock-pi-4-rk3399 \ - rockpro64-rk3399 \ - rongpin-king3399-rk3399 \ - rocktech-mpc1903-rk3399 \ - nanopi-r2c-rk3328 \ - nanopi-r2s-rk3328 \ - orangepi-r1-plus-rk3328 \ - orangepi-r1-plus-lts-rk3328 - -UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes - -UBOOT_MAKE_FLAGS += \ - BL31=$(STAGING_DIR_IMAGE)/$(ATF) - -define Build/Configure - $(call Build/Configure/U-Boot) - - $(SED) 's/CONFIG_TOOLS_LIBCRYPTO=y/# CONFIG_TOOLS_LIBCRYPTO is not set/' $(PKG_BUILD_DIR)/.config - $(SED) 's#CONFIG_MKIMAGE_DTC_PATH=.*#CONFIG_MKIMAGE_DTC_PATH="$(PKG_BUILD_DIR)/scripts/dtc/dtc"#g' $(PKG_BUILD_DIR)/.config - echo 'CONFIG_IDENT_STRING=" OpenWrt"' >> $(PKG_BUILD_DIR)/.config -ifneq ($(DDR),) - $(CP) $(STAGING_DIR_IMAGE)/$(DDR) $(PKG_BUILD_DIR)/ram_init.bin -endif -endef - -define Build/InstallDev - $(INSTALL_DIR) $(STAGING_DIR_IMAGE) -ifneq ($(USE_RKBIN),) - $(STAGING_DIR_IMAGE)/loaderimage --pack --uboot $(PKG_BUILD_DIR)/u-boot-dtb.bin $(PKG_BUILD_DIR)/uboot.img 0x200000 - $(CP) $(PKG_BUILD_DIR)/uboot.img $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-uboot.img -else - $(CP) $(PKG_BUILD_DIR)/idbloader.img $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-idbloader.img - $(CP) $(PKG_BUILD_DIR)/u-boot.itb $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-u-boot.itb -endif -endef - -define Package/u-boot/install/default -endef - -$(eval $(call BuildPackage/U-Boot)) diff --git a/5.4/package/boot/uboot-rockchip/patches/001-rockchip-rk3568-add-boot-device-detection.patch b/5.4/package/boot/uboot-rockchip/patches/001-rockchip-rk3568-add-boot-device-detection.patch deleted file mode 100644 index b3dd3099..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/001-rockchip-rk3568-add-boot-device-detection.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 9b92a43a4f5acf4cba14fd9d473b3120688532dc Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Sun, 19 Dec 2021 08:10:24 -0500 -Subject: [PATCH 01/11] rockchip: rk3568: add boot device detection - -Enable spl to detect which device it was booted from. - -Signed-off-by: Peter Geis ---- - arch/arm/mach-rockchip/rk3568/rk3568.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/arch/arm/mach-rockchip/rk3568/rk3568.c -+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c -@@ -7,6 +7,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -23,6 +24,7 @@ - #define SGRF_SOC_CON4 0x10 - #define EMMC_HPROT_SECURE_CTRL 0x03 - #define SDMMC0_HPROT_SECURE_CTRL 0x01 -+ - /* PMU_GRF_GPIO0D_IOMUX_L */ - enum { - GPIO0D1_SHIFT = 4, -@@ -43,6 +45,12 @@ enum { - UART2_IO_SEL_M0 = 0, - }; - -+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { -+ [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe310000", -+ [BROM_BOOTSOURCE_SPINOR] = "/spi@fe300000/flash@0", -+ [BROM_BOOTSOURCE_SD] = "/mmc@fe2b0000", -+}; -+ - static struct mm_region rk3568_mem_map[] = { - { - .virt = 0x0UL, diff --git a/5.4/package/boot/uboot-rockchip/patches/002-rockchip-rk3568-enable-automatic-power-savings.patch b/5.4/package/boot/uboot-rockchip/patches/002-rockchip-rk3568-enable-automatic-power-savings.patch deleted file mode 100644 index f38d9f4d..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/002-rockchip-rk3568-enable-automatic-power-savings.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 09d877cf076cbb67c79054e12bbb7c63a91faa71 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Sun, 19 Dec 2021 08:11:56 -0500 -Subject: [PATCH 02/11] rockchip: rk3568: enable automatic power savings - -Enable automatic clock gating, solves the 7c temperature difference on -SoQuartz. - -Signed-off-by: Peter Geis ---- - arch/arm/mach-rockchip/rk3568/rk3568.c | 23 +++++++++++++++++++++++ - 1 file changed, 23 insertions(+) - ---- a/arch/arm/mach-rockchip/rk3568/rk3568.c -+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c -@@ -25,6 +25,15 @@ - #define EMMC_HPROT_SECURE_CTRL 0x03 - #define SDMMC0_HPROT_SECURE_CTRL 0x01 - -+#define PMU_BASE_ADDR 0xfdd90000 -+#define PMU_NOC_AUTO_CON0 (0x70) -+#define PMU_NOC_AUTO_CON1 (0x74) -+#define EDP_PHY_GRF_BASE 0xfdcb0000 -+#define EDP_PHY_GRF_CON0 (EDP_PHY_GRF_BASE + 0x00) -+#define EDP_PHY_GRF_CON10 (EDP_PHY_GRF_BASE + 0x28) -+#define CPU_GRF_BASE 0xfdc30000 -+#define GRF_CORE_PVTPLL_CON0 (0x10) -+ - /* PMU_GRF_GPIO0D_IOMUX_L */ - enum { - GPIO0D1_SHIFT = 4, -@@ -99,6 +108,20 @@ void board_debug_uart_init(void) - int arch_cpu_init(void) - { - #ifdef CONFIG_SPL_BUILD -+ /* -+ * When perform idle operation, corresponding clock can -+ * be opened or gated automatically. -+ */ -+ writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0); -+ writel(0x000f000f, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1); -+ -+ /* Disable eDP phy by default */ -+ writel(0x00070007, EDP_PHY_GRF_CON10); -+ writel(0x0ff10ff1, EDP_PHY_GRF_CON0); -+ -+ /* Set core pvtpll ring length */ -+ writel(0x00ff002b, CPU_GRF_BASE + GRF_CORE_PVTPLL_CON0); -+ - /* Set the emmc sdmmc0 to secure */ - rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (EMMC_HPROT_SECURE_CTRL << 11 - | SDMMC0_HPROT_SECURE_CTRL << 4)); diff --git a/5.4/package/boot/uboot-rockchip/patches/003-Makefile-rockchip-HACK-build-rk3568-images.patch b/5.4/package/boot/uboot-rockchip/patches/003-Makefile-rockchip-HACK-build-rk3568-images.patch deleted file mode 100644 index 5a817301..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/003-Makefile-rockchip-HACK-build-rk3568-images.patch +++ /dev/null @@ -1,47 +0,0 @@ -From ddbcec939789d1f7264134b3628ffb649ec88168 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Sun, 19 Dec 2021 08:20:33 -0500 -Subject: [PATCH 03/11] Makefile: rockchip: HACK: build rk3568 images - -This is a hack to build rk3568 images. -It seems makefile can't cope with the format mkimage expects for -multiple file entries, so hack around the situation. - -Signed-off-by: Peter Geis ---- - Makefile | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/Makefile -+++ b/Makefile -@@ -1047,6 +1047,9 @@ quiet_cmd_mkimage = MKIMAGE $@ - cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ - >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT)) - -+cmd_mkimage_combined = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $(COMBINED_FILE):$< $@ \ -+ >$(MKIMAGEOUTPUT) $(if $(KBUILD_VERBOSE:0=), && cat $(MKIMAGEOUTPUT)) -+ - quiet_cmd_mkfitimage = MKIMAGE $@ - cmd_mkfitimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) \ - -f $(U_BOOT_ITS) -p $(CONFIG_FIT_EXTERNAL_OFFSET) $@ \ -@@ -1491,6 +1494,7 @@ u-boot-with-spl.bin: $(SPL_IMAGE) $(SPL_ - ifeq ($(CONFIG_ARCH_ROCKCHIP),y) - - # TPL + SPL -+ifneq ($(CONFIG_SYS_SOC),$(filter $(CONFIG_SYS_SOC),"rk3568" "rk3566")) - ifeq ($(CONFIG_SPL)$(CONFIG_TPL),yy) - MKIMAGEFLAGS_u-boot-tpl-rockchip.bin = -n $(CONFIG_SYS_SOC) -T rksd - tpl/u-boot-tpl-rockchip.bin: tpl/u-boot-tpl.bin FORCE -@@ -1502,6 +1506,12 @@ MKIMAGEFLAGS_idbloader.img = -n $(CONFIG - idbloader.img: spl/u-boot-spl.bin FORCE - $(call if_changed,mkimage) - endif -+else -+MKIMAGEFLAGS_idbloader.img = -n $(CONFIG_SYS_SOC) -T rksd -+COMBINED_FILE = ram_init.bin -+idbloader.img: spl/u-boot-spl.bin FORCE -+ $(call if_changed,mkimage_combined) -+endif - - ifeq ($(CONFIG_ARM64),y) - OBJCOPYFLAGS_u-boot-rockchip.bin = -I binary -O binary \ diff --git a/5.4/package/boot/uboot-rockchip/patches/004-arm-dts-sync-rk3568-with-linux.patch b/5.4/package/boot/uboot-rockchip/patches/004-arm-dts-sync-rk3568-with-linux.patch deleted file mode 100644 index 422f1c4d..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/004-arm-dts-sync-rk3568-with-linux.patch +++ /dev/null @@ -1,3520 +0,0 @@ -From 25624318957d560ce58be672fe2fa8537716afc7 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Sun, 19 Dec 2021 15:14:47 -0500 -Subject: [PATCH 04/11] arm: dts: sync rk3568 with linux - -Signed-off-by: Peter Geis ---- - arch/arm/dts/Makefile | 3 +- - arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi | 24 + - arch/arm/dts/rk3566-quartz64-a.dts | 860 +++++++++++ - arch/arm/dts/rk3566.dtsi | 32 + - arch/arm/dts/rk3568-evb.dts | 5 + - arch/arm/dts/rk3568-pinctrl.dtsi | 9 + - arch/arm/dts/rk3568.dtsi | 860 ++--------- - arch/arm/dts/rk356x.dtsi | 1630 ++++++++++++++++++++ - arch/arm/mach-rockchip/rk3568/rk3568.c | 2 +- - 9 files changed, 2672 insertions(+), 753 deletions(-) - create mode 100644 arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi - create mode 100644 arch/arm/dts/rk3566-quartz64-a.dts - create mode 100644 arch/arm/dts/rk3566.dtsi - create mode 100644 arch/arm/dts/rk356x.dtsi - ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -164,7 +164,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ - rk3399pro-rock-pi-n10.dtb - - dtb-$(CONFIG_ROCKCHIP_RK3568) += \ -- rk3568-evb.dtb -+ rk3568-evb.dtb \ -+ rk3566-quartz64-a.dtb - - dtb-$(CONFIG_ROCKCHIP_RV1108) += \ - rv1108-elgin-r1.dtb \ ---- /dev/null -+++ b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi -@@ -0,0 +1,24 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd -+ */ -+ -+#include "rk3568-u-boot.dtsi" -+ -+/ { -+ chosen { -+ stdout-path = &uart2; -+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; -+ }; -+}; -+ -+&sdmmc0 { -+ u-boot,dm-spl; -+ status = "okay"; -+}; -+ -+&uart2 { -+ clock-frequency = <24000000>; -+ u-boot,dm-spl; -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/dts/rk3566-quartz64-a.dts -@@ -0,0 +1,860 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+ -+#include -+#include -+#include "rk3566.dtsi" -+ -+/ { -+ model = "Pine64 RK3566 Quartz64-A Board"; -+ compatible = "pine64,quartz64-a", "rockchip,rk3566"; -+ -+ aliases { -+ ethernet0 = &gmac1; -+ mmc0 = &sdmmc0; -+ mmc1 = &sdhci; -+ }; -+ -+ chosen: chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ battery_cell: battery-cell { -+ compatible = "simple-battery"; -+ charge-full-design-microamp-hours = <2500000>; -+ charge-term-current-microamp = <300000>; -+ constant-charge-current-max-microamp = <2000000>; -+ constant-charge-voltage-max-microvolt = <4200000>; -+ factory-internal-resistance-micro-ohms = <180000>; -+ voltage-max-design-microvolt = <4106000>; -+ voltage-min-design-microvolt = <3625000>; -+ -+ ocv-capacity-celsius = <20>; -+ ocv-capacity-table-0 = <4106000 100>, <4071000 95>, <4018000 90>, <3975000 85>, -+ <3946000 80>, <3908000 75>, <3877000 70>, <3853000 65>, -+ <3834000 60>, <3816000 55>, <3802000 50>, <3788000 45>, -+ <3774000 40>, <3760000 35>, <3748000 30>, <3735000 25>, -+ <3718000 20>, <3697000 15>, <3685000 10>, <3625000 0>; -+ }; -+ -+ gmac1_clkin: external-gmac1-clock { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ clock-output-names = "gmac1_clkin"; -+ #clock-cells = <0>; -+ }; -+ -+ fan: gpio_fan { -+ compatible = "gpio-fan"; -+ gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; -+ gpio-fan,speed-map = <0 0 -+ 4500 1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&fan_en_h>; -+ #cooling-cells = <2>; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ led-work { -+ label = "work-led"; -+ default-state = "off"; -+ gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&work_led_enable_h>; -+ retain-state-suspended; -+ }; -+ -+ led-diy { -+ label = "diy-led"; -+ default-state = "on"; -+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "heartbeat"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&diy_led_enable_h>; -+ retain-state-suspended; -+ }; -+ }; -+ -+ rk817-sound { -+ compatible = "simple-audio-card"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hp_det_h>; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,hp-det-gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; -+ simple-audio-card,name = "Analog RK817"; -+ simple-audio-card,mclk-fs = <256>; -+ simple-audio-card,widgets = -+ "Microphone", "Mic Jack", -+ "Headphone", "Headphones", -+ "Speaker", "Speaker"; -+ simple-audio-card,routing = -+ "MICL", "Mic Jack", -+ "Headphones", "HPOL", -+ "Headphones", "HPOR", -+ "Speaker", "SPKO"; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&i2s1_8ch>; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&rk817>; -+ }; -+ }; -+ -+ spdif_dit: spdif-dit { -+ compatible = "linux,spdif-dit"; -+ #sound-dai-cells = <0>; -+ }; -+ -+ spdif_sound: spdif-sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,name = "SPDIF"; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&spdif>; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&spdif_dit>; -+ }; -+ }; -+ -+ sdio_pwrseq: sdio-pwrseq { -+ status = "okay"; -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&rk817 1>; -+ clock-names = "ext_clock"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_enable_h>; -+ reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>; -+ post-power-on-delay-ms = <100>; -+ power-off-delay-us = <5000000>; -+ }; -+ -+ spdif_sound: spdif-sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,name = "SPDIF"; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&spdif>; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&spdif_dit>; -+ }; -+ }; -+ -+ spdif_dit: spdif-dit { -+ compatible = "linux,spdif-dit"; -+ #sound-dai-cells = <0>; -+ }; -+ -+ vcc12v_dcin: vcc12v_dcin { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc12v_dcin"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ }; -+ -+ /* vbus feeds the rk817 usb input. -+ * With no battery attached, also feeds vcc_bat+ -+ * via ON/OFF_BAT jumper -+ */ -+ vbus: vbus { -+ compatible = "regulator-fixed"; -+ regulator-name = "vbus"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc12v_dcin>; -+ }; -+ -+ vcc5v0_usb: vcc5v0_usb { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_usb"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc12v_dcin>; -+ }; -+ -+ /* all four ports are controlled by one gpio -+ * the host ports are sourced from vcc5v0_usb -+ * the otg port is sourced from vcc5v0_midu -+ */ -+ vcc5v0_usb20_host: vcc5v0_usb20_host { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_usb20_host"; -+ enable-active-high; -+ gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_usb20_host_en_h>; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_usb>; -+ }; -+ -+ vcc5v0_usb20_otg: vcc5v0_usb20_otg { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_usb20_otg"; -+ enable-active-high; -+ gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&dcdc_boost>; -+ }; -+ -+ vcc3v3_pcie_p: vcc3v3_pcie_p { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_enable_h>; -+ regulator-name = "vcc3v3_pcie_p"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_3v3>; -+ }; -+ -+ vcc3v3_sd: vcc3v3_sd { -+ compatible = "regulator-fixed"; -+ enable-active-low; -+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc_sd_h>; -+ regulator-boot-on; -+ regulator-name = "vcc3v3_sd"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_3v3>; -+ }; -+ -+ /* sourced from vbus and vcc_bat+ via rk817 sw5 */ -+ vcc_sys: vcc_sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <4400000>; -+ regulator-max-microvolt = <4400000>; -+ vin-supply = <&vbus>; -+ }; -+ -+ /* sourced from vcc_sys, sdio module operates internally at 3.3v */ -+ vcc_wl: vcc_wl { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_wl"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_sys>; -+ }; -+}; -+ -+&combphy1_usq { -+ status = "okay"; -+ rockchip,enable-ssc; -+}; -+ -+&combphy2_psq { -+ status = "okay"; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu2 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu3 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu_thermal { -+ trips { -+ cpu_hot: cpu_hot { -+ temperature = <55000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ }; -+ -+ cooling-maps { -+ map1 { -+ trip = <&cpu_hot>; -+ cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+}; -+ -+&gmac1 { -+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; -+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; -+ clock_in_out = "input"; -+ phy-supply = <&vcc_3v3>; -+ phy-mode = "rgmii"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmac1m0_miim -+ &gmac1m0_tx_bus2 -+ &gmac1m0_rx_bus2 -+ &gmac1m0_rgmii_clk -+ &gmac1m0_clkinout -+ &gmac1m0_rgmii_bus>; -+ snps,reset-gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>; -+ snps,reset-active-low; -+ /* Reset time is 20ms, 100ms for rtl8211f */ -+ snps,reset-delays-us = <0 20000 100000>; -+ tx_delay = <0x30>; -+ rx_delay = <0x10>; -+ phy-handle = <&rgmii_phy1>; -+ status = "okay"; -+}; -+ -+&hdmi { -+ status = "okay"; -+ avdd-0v9-supply = <&vdda_0v9>; -+ avdd-1v8-supply = <&vcc_1v8>; -+}; -+ -+&hdmi_in_vp0 { -+ status = "okay"; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ vdd_cpu: regulator@1c { -+ compatible = "tcs,tcs4525"; -+ reg = <0x1c>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu"; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1150000>; -+ regulator-ramp-delay = <2300>; -+ regulator-always-on; -+ regulator-boot-on; -+ vin-supply = <&vcc_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ rk817: pmic@20 { -+ compatible = "rockchip,rk817"; -+ reg = <0x20>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>; -+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; -+ clock-names = "mclk"; -+ clocks = <&cru I2S1_MCLKOUT_TX>; -+ clock-output-names = "rk808-clkout1", "rk808-clkout2"; -+ #clock-cells = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; -+ rockchip,system-power-controller; -+ #sound-dai-cells = <0>; -+ wakeup-source; -+ -+ vcc1-supply = <&vcc_sys>; -+ vcc2-supply = <&vcc_sys>; -+ vcc3-supply = <&vcc_sys>; -+ vcc4-supply = <&vcc_sys>; -+ vcc5-supply = <&vcc_sys>; -+ vcc6-supply = <&vcc_sys>; -+ vcc7-supply = <&vcc_sys>; -+ vcc8-supply = <&vcc_sys>; -+ vcc9-supply = <&dcdc_boost>; -+ -+ regulators { -+ vdd_logic: DCDC_REG1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-init-microvolt = <900000>; -+ regulator-ramp-delay = <6001>; -+ regulator-initial-mode = <0x2>; -+ regulator-name = "vdd_logic"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ vdd_gpu: DCDC_REG2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-init-microvolt = <900000>; -+ regulator-ramp-delay = <6001>; -+ regulator-initial-mode = <0x2>; -+ regulator-name = "vdd_gpu"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1100000>; -+ regulator-initial-mode = <0x2>; -+ regulator-name = "vcc_ddr"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_3v3: DCDC_REG4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-initial-mode = <0x2>; -+ regulator-name = "vcc_3v3"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcca1v8_pmu: LDO_REG1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcca1v8_pmu"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vdda_0v9: LDO_REG2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ regulator-name = "vdda_0v9"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_pmu: LDO_REG3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ regulator-name = "vdda0v9_pmu"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ vccio_acodec: LDO_REG4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vccio_acodec"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd: LDO_REG5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vccio_sd"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_pmu: LDO_REG6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc3v3_pmu"; -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcc_1v8: LDO_REG7 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc_1v8"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc1v8_dvp: LDO_REG8 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc1v8_dvp"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc2v8_dvp: LDO_REG9 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <2800000>; -+ regulator-max-microvolt = <2800000>; -+ regulator-name = "vcc2v8_dvp"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ dcdc_boost: BOOST { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-name = "boost"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ otg_switch: OTG_SWITCH { -+ regulator-name = "otg_switch"; -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ -+ rk817_battery: battery { -+ monitored-battery = <&battery_cell>; -+ rockchip,resistor-sense-micro-ohms = <10000>; -+ rockchip,sleep-enter-current-microamp = <300000>; -+ rockchip,sleep-filter-current-microamp = <100000>; -+ }; -+ }; -+}; -+ -+&i2s1_8ch { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s1m0_sclktx -+ &i2s1m0_lrcktx -+ &i2s1m0_sdi0 -+ &i2s1m0_sdo0>; -+ rockchip,trcm-sync-tx-only; -+ status = "okay"; -+}; -+ -+&mdio1 { -+ rgmii_phy1: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <0>; -+ }; -+}; -+ -+&pcie2x1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_reset_h>; -+ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ vpcie3v3-supply = <&vcc3v3_pcie_p>; -+}; -+ -+&pinctrl { -+ bt { -+ bt_enable_h: bt-enable-h { -+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ bt_host_wake_l: bt-host-wake-l { -+ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ bt_wake_l: bt-wake-l { -+ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ fan { -+ fan_en_h: fan-en-h { -+ rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ leds { -+ work_led_enable_h: work-led-enable-h { -+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ diy_led_enable_h: diy-led-enable-h { -+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pcie { -+ pcie_enable_h: pcie-enable-h { -+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ pcie_reset_h: pcie-reset-h { -+ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ hp_det_h: hp-det-h { -+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ sdio-pwrseq { -+ wifi_enable_h: wifi-enable-h { -+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ usb2 { -+ vcc5v0_usb20_host_en_h: vcc5v0-usb20-host-en_h { -+ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ vcc_sd { -+ vcc_sd_h: vcc-sd-h { -+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&pmu_io_domains { -+ status = "okay"; -+ pmuio1-supply = <&vcc3v3_pmu>; -+ pmuio2-supply = <&vcc3v3_pmu>; -+ vccio1-supply = <&vccio_acodec>; -+ vccio2-supply = <&vcc_1v8>; -+ vccio3-supply = <&vccio_sd>; -+ vccio4-supply = <&vcc_1v8>; -+ vccio5-supply = <&vcc_3v3>; -+ vccio6-supply = <&vcc1v8_dvp>; -+ vccio7-supply = <&vcc_3v3>; -+}; -+ -+/* sata1 is muxed with the usb3 port */ -+&sata1 { -+ status = "okay"; -+}; -+ -+/* sata2 is muxed with the pcie2 slot*/ -+&sata2 { -+ status = "disabled"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ mmc-hs200-1_8v; -+ non-removable; -+ vmmc-supply = <&vcc_3v3>; -+ vqmmc-supply = <&vcc_1v8>; -+ status = "okay"; -+}; -+ -+&sdmmc0 { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; -+ disable-wp; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc3v3_sd>; -+ vqmmc-supply = <&vccio_sd>; -+ status = "okay"; -+}; -+ -+&spdif { -+ status = "okay"; -+}; -+ -+&sdmmc1 { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cap-sdio-irq; -+ disable-wp; -+ keep-power-in-suspend; -+ mmc-pwrseq = <&sdio_pwrseq>; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc_wl>; -+ vqmmc-supply = <&vcc_1v8>; -+ status = "okay"; -+}; -+ -+&sfc { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <108000000>; -+ spi-rx-bus-width = <4>; -+ spi-tx-bus-width = <1>; -+ }; -+}; -+ -+&tsadc { -+ /* tshut mode 0:CRU 1:GPIO */ -+ rockchip,hw-tshut-mode = <1>; -+ /* tshut polarity 0:LOW 1:HIGH */ -+ rockchip,hw-tshut-polarity = <0>; -+ status = "okay"; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_xfer>; -+ status = "okay"; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; -+ status = "okay"; -+ uart-has-rtscts; -+ -+ bluetooth { -+ compatible = "brcm,bcm43438-bt"; -+ clocks = <&rk817 1>; -+ clock-names = "lpo"; -+ device-wake-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; -+ host-wake-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; -+ shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; -+ vbat-supply = <&vcc_sys>; -+ vddio-supply = <&vcca1v8_pmu>; -+ }; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&u2phy0_host { -+ phy-supply = <&vcc5v0_usb20_host>; -+ status = "okay"; -+}; -+ -+&u2phy0_otg { -+ phy-supply = <&vcc5v0_usb20_otg>; -+ status = "okay"; -+}; -+ -+&u2phy1_host { -+ phy-supply = <&vcc5v0_usb20_host>; -+ status = "okay"; -+}; -+ -+&u2phy1_otg { -+ phy-supply = <&vcc5v0_usb20_host>; -+ status = "okay"; -+}; -+ -+&usb2phy0 { -+ status = "okay"; -+}; -+ -+&usb2phy1 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3 { -+ status = "okay"; -+}; -+ -+&usbdrd30 { -+ status = "okay"; -+}; -+ -+/* usb3 controller is muxed with sata1 */ -+&usbhost_dwc3 { -+ status = "disabled"; -+}; -+ -+/* usb3 controller is muxed with sata1 */ -+&usbhost30 { -+ status = "disabled"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; -+ -+&vop { -+ status = "okay"; -+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; -+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; -+}; -+ -+&vop_mmu { -+ status = "okay"; -+}; -+ -+&vp0_out_hdmi { -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/dts/rk3566.dtsi -@@ -0,0 +1,32 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include "rk356x.dtsi" -+ -+/ { -+ compatible = "rockchip,rk3566"; -+}; -+ -+&pipegrf { -+ compatible = "rockchip,rk3566-pipegrf", "syscon"; -+}; -+ -+&power { -+ power-domain@RK3568_PD_PIPE { -+ reg = ; -+ clocks = <&cru PCLK_PIPE>; -+ pm_qos = <&qos_pcie2x1>, -+ <&qos_sata1>, -+ <&qos_sata2>, -+ <&qos_usb3_0>, -+ <&qos_usb3_1>; -+ #power-domain-cells = <0>; -+ }; -+}; -+ -+&usbdrd_dwc3 { -+ phys = <&u2phy0_otg>; -+ phy-names = "usb2-phy"; -+ extcon = <&usb2phy0>; -+ maximum-speed = "high-speed"; -+ snps,dis_u2_susphy_quirk; -+}; ---- a/arch/arm/dts/rk3568-evb.dts -+++ b/arch/arm/dts/rk3568-evb.dts -@@ -74,6 +74,11 @@ - status = "okay"; - }; - -+&sdmmc0 { -+ status = "okay"; -+ max-frequency = <52000000>; -+}; -+ - &uart2 { - status = "okay"; - }; ---- a/arch/arm/dts/rk3568-pinctrl.dtsi -+++ b/arch/arm/dts/rk3568-pinctrl.dtsi -@@ -3108,4 +3108,13 @@ - <4 RK_PA0 3 &pcfg_pull_none_drv_level_2>; - }; - }; -+ -+ tsadc { -+ /omit-if-no-ref/ -+ tsadc_pin: tsadc-pin { -+ rockchip,pins = -+ /* tsadc_pin */ -+ <0 RK_PA1 0 &pcfg_pull_none>; -+ }; -+ }; - }; ---- a/arch/arm/dts/rk3568.dtsi -+++ b/arch/arm/dts/rk3568.dtsi -@@ -3,777 +3,135 @@ - * Copyright (c) 2021 Rockchip Electronics Co., Ltd. - */ - --#include --#include --#include --#include --#include --#include --#include -+#include "rk356x.dtsi" - - / { - compatible = "rockchip,rk3568"; - -- interrupt-parent = <&gic>; -- #address-cells = <2>; -- #size-cells = <2>; -- -- aliases { -- gpio0 = &gpio0; -- gpio1 = &gpio1; -- gpio2 = &gpio2; -- gpio3 = &gpio3; -- gpio4 = &gpio4; -- i2c0 = &i2c0; -- i2c1 = &i2c1; -- i2c2 = &i2c2; -- i2c3 = &i2c3; -- i2c4 = &i2c4; -- i2c5 = &i2c5; -- serial0 = &uart0; -- serial1 = &uart1; -- serial2 = &uart2; -- serial3 = &uart3; -- serial4 = &uart4; -- serial5 = &uart5; -- serial6 = &uart6; -- serial7 = &uart7; -- serial8 = &uart8; -- serial9 = &uart9; -- }; -- -- cpus { -- #address-cells = <2>; -- #size-cells = <0>; -- -- cpu0: cpu@0 { -- device_type = "cpu"; -- compatible = "arm,cortex-a55"; -- reg = <0x0 0x0>; -- clocks = <&scmi_clk 0>; -- enable-method = "psci"; -- operating-points-v2 = <&cpu0_opp_table>; -- }; -- -- cpu1: cpu@100 { -- device_type = "cpu"; -- compatible = "arm,cortex-a55"; -- reg = <0x0 0x100>; -- enable-method = "psci"; -- operating-points-v2 = <&cpu0_opp_table>; -- }; -- -- cpu2: cpu@200 { -- device_type = "cpu"; -- compatible = "arm,cortex-a55"; -- reg = <0x0 0x200>; -- enable-method = "psci"; -- operating-points-v2 = <&cpu0_opp_table>; -- }; -- -- cpu3: cpu@300 { -- device_type = "cpu"; -- compatible = "arm,cortex-a55"; -- reg = <0x0 0x300>; -- enable-method = "psci"; -- operating-points-v2 = <&cpu0_opp_table>; -- }; -+ sata0: sata@fc000000 { -+ compatible = "snps,dwc-ahci"; -+ reg = <0 0xfc000000 0 0x1000>; -+ clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>, -+ <&cru CLK_SATA0_RXOOB>; -+ clock-names = "sata", "pmalive", "rxoob"; -+ interrupts = ; -+ interrupt-names = "hostc"; -+ phys = <&combphy0_us PHY_TYPE_SATA>; -+ phy-names = "sata-phy"; -+ ports-implemented = <0x1>; -+ power-domains = <&power RK3568_PD_PIPE>; -+ status = "disabled"; - }; - -- cpu0_opp_table: cpu0-opp-table { -- compatible = "operating-points-v2"; -- opp-shared; -- -- opp-408000000 { -- opp-hz = /bits/ 64 <408000000>; -- opp-microvolt = <900000 900000 1150000>; -- clock-latency-ns = <40000>; -- }; -- -- opp-600000000 { -- opp-hz = /bits/ 64 <600000000>; -- opp-microvolt = <900000 900000 1150000>; -- }; -- -- opp-816000000 { -- opp-hz = /bits/ 64 <816000000>; -- opp-microvolt = <900000 900000 1150000>; -- opp-suspend; -- }; -- -- opp-1104000000 { -- opp-hz = /bits/ 64 <1104000000>; -- opp-microvolt = <900000 900000 1150000>; -- }; -- -- opp-1416000000 { -- opp-hz = /bits/ 64 <1416000000>; -- opp-microvolt = <900000 900000 1150000>; -- }; -- -- opp-1608000000 { -- opp-hz = /bits/ 64 <1608000000>; -- opp-microvolt = <975000 975000 1150000>; -- }; -+ qos_pcie3x1: qos@fe190080 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe190080 0x0 0x20>; -+ }; -+ -+ qos_pcie3x2: qos@fe190100 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe190100 0x0 0x20>; -+ }; -+ -+ qos_sata0: qos@fe190200 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe190200 0x0 0x20>; -+ }; -+ -+ gmac0: ethernet@fe2a0000 { -+ compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; -+ reg = <0x0 0xfe2a0000 0x0 0x10000>; -+ interrupts = , -+ ; -+ interrupt-names = "macirq", "eth_wake_irq"; -+ clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>, -+ <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>, -+ <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>, -+ <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>, -+ <&cru PCLK_XPCS>; -+ clock-names = "stmmaceth", "mac_clk_rx", -+ "mac_clk_tx", "clk_mac_refout", -+ "aclk_mac", "pclk_mac", -+ "clk_mac_speed", "ptp_ref", -+ "pclk_xpcs"; -+ resets = <&cru SRST_A_GMAC0>; -+ reset-names = "stmmaceth"; -+ rockchip,grf = <&grf>; -+ snps,axi-config = <&gmac0_stmmac_axi_setup>; -+ snps,mixed-burst; -+ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; -+ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; -+ snps,tso; -+ status = "disabled"; - -- opp-1800000000 { -- opp-hz = /bits/ 64 <1800000000>; -- opp-microvolt = <1050000 1050000 1150000>; -+ mdio0: mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <0x1>; -+ #size-cells = <0x0>; - }; - -- opp-1992000000 { -- opp-hz = /bits/ 64 <1992000000>; -- opp-microvolt = <1150000 1150000 1150000>; -+ gmac0_stmmac_axi_setup: stmmac-axi-config { -+ snps,blen = <0 0 0 0 16 8 4>; -+ snps,rd_osr_lmt = <8>; -+ snps,wr_osr_lmt = <4>; - }; -- }; - -- firmware { -- scmi: scmi { -- compatible = "arm,scmi-smc"; -- arm,smc-id = <0x82000010>; -- shmem = <&scmi_shmem>; -- #address-cells = <1>; -- #size-cells = <0>; -- -- scmi_clk: protocol@14 { -- reg = <0x14>; -- #clock-cells = <1>; -- }; -+ gmac0_mtl_rx_setup: rx-queues-config { -+ snps,rx-queues-to-use = <1>; -+ queue0 {}; - }; - -- }; -- -- pmu { -- compatible = "arm,cortex-a55-pmu"; -- interrupts = , -- , -- , -- ; -- interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; -- }; -- -- psci { -- compatible = "arm,psci-1.0"; -- method = "smc"; -- }; -- -- timer { -- compatible = "arm,armv8-timer"; -- interrupts = , -- , -- , -- ; -- arm,no-tick-in-suspend; -- }; -- -- xin24m: xin24m { -- compatible = "fixed-clock"; -- clock-frequency = <24000000>; -- clock-output-names = "xin24m"; -- #clock-cells = <0>; -- }; -- -- xin32k: xin32k { -- compatible = "fixed-clock"; -- clock-frequency = <32768>; -- clock-output-names = "xin32k"; -- pinctrl-0 = <&clk32k_out0>; -- pinctrl-names = "default"; -- #clock-cells = <0>; -- }; -- -- sram@10f000 { -- compatible = "mmio-sram"; -- reg = <0x0 0x0010f000 0x0 0x100>; -- -- #address-cells = <1>; -- #size-cells = <1>; -- ranges = <0 0x0 0x0010f000 0x100>; -- -- scmi_shmem: sram@0 { -- compatible = "arm,scmi-shmem"; -- reg = <0x0 0x100>; -+ gmac0_mtl_tx_setup: tx-queues-config { -+ snps,tx-queues-to-use = <1>; -+ queue0 {}; - }; - }; - -- gic: interrupt-controller@fd400000 { -- compatible = "arm,gic-v3"; -- reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ -- <0x0 0xfd460000 0 0x80000>; /* GICR */ -- interrupts = ; -- interrupt-controller; -- #interrupt-cells = <3>; -- mbi-alias = <0x0 0xfd100000>; -- mbi-ranges = <296 24>; -- msi-controller; -- }; -- -- pmugrf: syscon@fdc20000 { -- compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; -- reg = <0x0 0xfdc20000 0x0 0x10000>; -- }; -- -- grf: syscon@fdc60000 { -- compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; -- reg = <0x0 0xfdc60000 0x0 0x10000>; -- }; -- -- pmucru: clock-controller@fdd00000 { -- compatible = "rockchip,rk3568-pmucru"; -- reg = <0x0 0xfdd00000 0x0 0x1000>; -- #clock-cells = <1>; -- #reset-cells = <1>; -- }; -- -- cru: clock-controller@fdd20000 { -- compatible = "rockchip,rk3568-cru"; -- reg = <0x0 0xfdd20000 0x0 0x1000>; -- #clock-cells = <1>; -- #reset-cells = <1>; -- }; -- -- i2c0: i2c@fdd40000 { -- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; -- reg = <0x0 0xfdd40000 0x0 0x1000>; -- interrupts = ; -- clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; -- clock-names = "i2c", "pclk"; -- pinctrl-0 = <&i2c0_xfer>; -- pinctrl-names = "default"; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- uart0: serial@fdd50000 { -- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; -- reg = <0x0 0xfdd50000 0x0 0x100>; -- interrupts = ; -- clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; -- clock-names = "baudclk", "apb_pclk"; -- dmas = <&dmac0 0>, <&dmac0 1>; -- pinctrl-0 = <&uart0_xfer>; -- pinctrl-names = "default"; -- reg-io-width = <4>; -- reg-shift = <2>; -- status = "disabled"; -- }; -- -- pwm0: pwm@fdd70000 { -- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfdd70000 0x0 0x10>; -- clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm0m0_pins>; -- pinctrl-names = "active"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- pwm1: pwm@fdd70010 { -- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfdd70010 0x0 0x10>; -- clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm1m0_pins>; -- pinctrl-names = "active"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- pwm2: pwm@fdd70020 { -- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfdd70020 0x0 0x10>; -- clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm2m0_pins>; -- pinctrl-names = "active"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- pwm3: pwm@fdd70030 { -- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfdd70030 0x0 0x10>; -- clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm3_pins>; -- pinctrl-names = "active"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- sdmmc2: mmc@fe000000 { -- compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; -- reg = <0x0 0xfe000000 0x0 0x4000>; -- interrupts = ; -- clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, -- <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; -- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; -- fifo-depth = <0x100>; -- max-frequency = <150000000>; -- resets = <&cru SRST_SDMMC2>; -- reset-names = "reset"; -- status = "disabled"; -- }; -- -- sdmmc0: mmc@fe2b0000 { -- compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; -- reg = <0x0 0xfe2b0000 0x0 0x4000>; -- interrupts = ; -- clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, -- <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; -- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; -- fifo-depth = <0x100>; -- max-frequency = <150000000>; -- resets = <&cru SRST_SDMMC0>; -- reset-names = "reset"; -- status = "disabled"; -- }; -- -- sdmmc1: mmc@fe2c0000 { -- compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; -- reg = <0x0 0xfe2c0000 0x0 0x4000>; -- interrupts = ; -- clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, -- <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; -- clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; -- fifo-depth = <0x100>; -- max-frequency = <150000000>; -- resets = <&cru SRST_SDMMC1>; -- reset-names = "reset"; -- status = "disabled"; -- }; -- -- sdhci: mmc@fe310000 { -- compatible = "rockchip,rk3568-dwcmshc"; -- reg = <0x0 0xfe310000 0x0 0x10000>; -- interrupts = ; -- assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; -- assigned-clock-rates = <200000000>, <24000000>; -- clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, -- <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, -- <&cru TCLK_EMMC>; -- clock-names = "core", "bus", "axi", "block", "timer"; -- status = "disabled"; -- }; -- -- dmac0: dmac@fe530000 { -- compatible = "arm,pl330", "arm,primecell"; -- reg = <0x0 0xfe530000 0x0 0x4000>; -- interrupts = , -- ; -- arm,pl330-periph-burst; -- clocks = <&cru ACLK_BUS>; -- clock-names = "apb_pclk"; -- #dma-cells = <1>; -- }; -- -- dmac1: dmac@fe550000 { -- compatible = "arm,pl330", "arm,primecell"; -- reg = <0x0 0xfe550000 0x0 0x4000>; -- interrupts = , -- ; -- arm,pl330-periph-burst; -- clocks = <&cru ACLK_BUS>; -- clock-names = "apb_pclk"; -- #dma-cells = <1>; -- }; -- -- i2c1: i2c@fe5a0000 { -- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; -- reg = <0x0 0xfe5a0000 0x0 0x1000>; -- interrupts = ; -- clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; -- clock-names = "i2c", "pclk"; -- pinctrl-0 = <&i2c1_xfer>; -- pinctrl-names = "default"; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- i2c2: i2c@fe5b0000 { -- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; -- reg = <0x0 0xfe5b0000 0x0 0x1000>; -- interrupts = ; -- clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; -- clock-names = "i2c", "pclk"; -- pinctrl-0 = <&i2c2m0_xfer>; -- pinctrl-names = "default"; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- i2c3: i2c@fe5c0000 { -- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; -- reg = <0x0 0xfe5c0000 0x0 0x1000>; -- interrupts = ; -- clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; -- clock-names = "i2c", "pclk"; -- pinctrl-0 = <&i2c3m0_xfer>; -- pinctrl-names = "default"; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- i2c4: i2c@fe5d0000 { -- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; -- reg = <0x0 0xfe5d0000 0x0 0x1000>; -- interrupts = ; -- clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; -- clock-names = "i2c", "pclk"; -- pinctrl-0 = <&i2c4m0_xfer>; -- pinctrl-names = "default"; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- i2c5: i2c@fe5e0000 { -- compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; -- reg = <0x0 0xfe5e0000 0x0 0x1000>; -- interrupts = ; -- clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; -- clock-names = "i2c", "pclk"; -- pinctrl-0 = <&i2c5m0_xfer>; -- pinctrl-names = "default"; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- }; -- -- wdt: watchdog@fe600000 { -- compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; -- reg = <0x0 0xfe600000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; -- clock-names = "tclk", "pclk"; -- }; -- -- uart1: serial@fe650000 { -- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; -- reg = <0x0 0xfe650000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; -- clock-names = "baudclk", "apb_pclk"; -- dmas = <&dmac0 2>, <&dmac0 3>; -- pinctrl-0 = <&uart1m0_xfer>; -- pinctrl-names = "default"; -- reg-io-width = <4>; -- reg-shift = <2>; -- status = "disabled"; -- }; -- -- uart2: serial@fe660000 { -- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; -- reg = <0x0 0xfe660000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; -- clock-names = "baudclk", "apb_pclk"; -- dmas = <&dmac0 4>, <&dmac0 5>; -- pinctrl-0 = <&uart2m0_xfer>; -- pinctrl-names = "default"; -- reg-io-width = <4>; -- reg-shift = <2>; -- status = "disabled"; -- }; -- -- uart3: serial@fe670000 { -- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; -- reg = <0x0 0xfe670000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; -- clock-names = "baudclk", "apb_pclk"; -- dmas = <&dmac0 6>, <&dmac0 7>; -- pinctrl-0 = <&uart3m0_xfer>; -- pinctrl-names = "default"; -- reg-io-width = <4>; -- reg-shift = <2>; -- status = "disabled"; -- }; -- -- uart4: serial@fe680000 { -- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; -- reg = <0x0 0xfe680000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; -- clock-names = "baudclk", "apb_pclk"; -- dmas = <&dmac0 8>, <&dmac0 9>; -- pinctrl-0 = <&uart4m0_xfer>; -- pinctrl-names = "default"; -- reg-io-width = <4>; -- reg-shift = <2>; -- status = "disabled"; -- }; -- -- uart5: serial@fe690000 { -- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; -- reg = <0x0 0xfe690000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; -- clock-names = "baudclk", "apb_pclk"; -- dmas = <&dmac0 10>, <&dmac0 11>; -- pinctrl-0 = <&uart5m0_xfer>; -- pinctrl-names = "default"; -- reg-io-width = <4>; -- reg-shift = <2>; -- status = "disabled"; -- }; -- -- uart6: serial@fe6a0000 { -- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; -- reg = <0x0 0xfe6a0000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; -- clock-names = "baudclk", "apb_pclk"; -- dmas = <&dmac0 12>, <&dmac0 13>; -- pinctrl-0 = <&uart6m0_xfer>; -- pinctrl-names = "default"; -- reg-io-width = <4>; -- reg-shift = <2>; -- status = "disabled"; -- }; -- -- uart7: serial@fe6b0000 { -- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; -- reg = <0x0 0xfe6b0000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; -- clock-names = "baudclk", "apb_pclk"; -- dmas = <&dmac0 14>, <&dmac0 15>; -- pinctrl-0 = <&uart7m0_xfer>; -- pinctrl-names = "default"; -- reg-io-width = <4>; -- reg-shift = <2>; -- status = "disabled"; -- }; -- -- uart8: serial@fe6c0000 { -- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; -- reg = <0x0 0xfe6c0000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; -- clock-names = "baudclk", "apb_pclk"; -- dmas = <&dmac0 16>, <&dmac0 17>; -- pinctrl-0 = <&uart8m0_xfer>; -- pinctrl-names = "default"; -- reg-io-width = <4>; -- reg-shift = <2>; -- status = "disabled"; -- }; -- -- uart9: serial@fe6d0000 { -- compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; -- reg = <0x0 0xfe6d0000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; -- clock-names = "baudclk", "apb_pclk"; -- dmas = <&dmac0 18>, <&dmac0 19>; -- pinctrl-0 = <&uart9m0_xfer>; -- pinctrl-names = "default"; -- reg-io-width = <4>; -- reg-shift = <2>; -- status = "disabled"; -- }; -- -- pwm4: pwm@fe6e0000 { -- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfe6e0000 0x0 0x10>; -- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm4_pins>; -- pinctrl-names = "active"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- pwm5: pwm@fe6e0010 { -- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfe6e0010 0x0 0x10>; -- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm5_pins>; -- pinctrl-names = "active"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- pwm6: pwm@fe6e0020 { -- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfe6e0020 0x0 0x10>; -- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm6_pins>; -- pinctrl-names = "active"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- pwm7: pwm@fe6e0030 { -- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfe6e0030 0x0 0x10>; -- clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm7_pins>; -- pinctrl-names = "active"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- pwm8: pwm@fe6f0000 { -- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfe6f0000 0x0 0x10>; -- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm8m0_pins>; -- pinctrl-names = "active"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- pwm9: pwm@fe6f0010 { -- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfe6f0010 0x0 0x10>; -- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm9m0_pins>; -- pinctrl-names = "active"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- pwm10: pwm@fe6f0020 { -- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfe6f0020 0x0 0x10>; -- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm10m0_pins>; -- pinctrl-names = "active"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- pwm11: pwm@fe6f0030 { -- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfe6f0030 0x0 0x10>; -- clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm11m0_pins>; -- pinctrl-names = "active"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- pwm12: pwm@fe700000 { -- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfe700000 0x0 0x10>; -- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm12m0_pins>; -- pinctrl-names = "active"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- pwm13: pwm@fe700010 { -- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfe700010 0x0 0x10>; -- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm13m0_pins>; -- pinctrl-names = "active"; -- #pwm-cells = <3>; -- status = "disabled"; -- }; -- -- pwm14: pwm@fe700020 { -- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfe700020 0x0 0x10>; -- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm14m0_pins>; -- pinctrl-names = "active"; -- #pwm-cells = <3>; -+ combphy0_us: phy@fe820000 { -+ compatible = "rockchip,rk3568-naneng-combphy"; -+ reg = <0x0 0xfe820000 0x0 0x100>; -+ #phy-cells = <1>; -+ assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; -+ assigned-clock-rates = <100000000>; -+ clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>, -+ <&cru PCLK_PIPE>; -+ clock-names = "ref", "apb", "pipe"; -+ resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; -+ reset-names = "combphy-apb", "combphy"; -+ rockchip,pipe-grf = <&pipegrf>; -+ rockchip,pipe-phy-grf = <&pipe_phy_grf0>; - status = "disabled"; - }; -+}; - -- pwm15: pwm@fe700030 { -- compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -- reg = <0x0 0xfe700030 0x0 0x10>; -- clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; -- clock-names = "pwm", "pclk"; -- pinctrl-0 = <&pwm15m0_pins>; -- pinctrl-names = "active"; -- #pwm-cells = <3>; -- status = "disabled"; -+&cpu0_opp_table { -+ opp-1992000000 { -+ opp-hz = /bits/ 64 <1992000000>; -+ opp-microvolt = <1150000 1150000 1150000>; - }; -+}; - -- pinctrl: pinctrl { -- compatible = "rockchip,rk3568-pinctrl"; -- rockchip,grf = <&grf>; -- rockchip,pmu = <&pmugrf>; -- #address-cells = <2>; -- #size-cells = <2>; -- ranges; -- -- gpio0: gpio@fdd60000 { -- compatible = "rockchip,gpio-bank"; -- reg = <0x0 0xfdd60000 0x0 0x100>; -- interrupts = ; -- clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; -- gpio-controller; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- }; -- -- gpio1: gpio@fe740000 { -- compatible = "rockchip,gpio-bank"; -- reg = <0x0 0xfe740000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; -- gpio-controller; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- }; -- -- gpio2: gpio@fe750000 { -- compatible = "rockchip,gpio-bank"; -- reg = <0x0 0xfe750000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; -- gpio-controller; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- }; -- -- gpio3: gpio@fe760000 { -- compatible = "rockchip,gpio-bank"; -- reg = <0x0 0xfe760000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; -- gpio-controller; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- }; -+&pipegrf { -+ compatible = "rockchip,rk3568-pipegrf", "syscon"; -+}; - -- gpio4: gpio@fe770000 { -- compatible = "rockchip,gpio-bank"; -- reg = <0x0 0xfe770000 0x0 0x100>; -- interrupts = ; -- clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; -- gpio-controller; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- }; -+&power { -+ power-domain@RK3568_PD_PIPE { -+ reg = ; -+ clocks = <&cru PCLK_PIPE>; -+ pm_qos = <&qos_pcie2x1>, -+ <&qos_pcie3x1>, -+ <&qos_pcie3x2>, -+ <&qos_sata0>, -+ <&qos_sata1>, -+ <&qos_sata2>, -+ <&qos_usb3_0>, -+ <&qos_usb3_1>; -+ #power-domain-cells = <0>; - }; - }; - --#include "rk3568-pinctrl.dtsi" -+&usbdrd_dwc3 { -+ phys = <&u2phy0_otg>, <&combphy0_us PHY_TYPE_USB3>; -+ phy-names = "usb2-phy", "usb3-phy"; -+}; ---- /dev/null -+++ b/arch/arm/dts/rk356x.dtsi -@@ -0,0 +1,1630 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/ { -+ interrupt-parent = <&gic>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ aliases { -+ gpio0 = &gpio0; -+ gpio1 = &gpio1; -+ gpio2 = &gpio2; -+ gpio3 = &gpio3; -+ gpio4 = &gpio4; -+ i2c0 = &i2c0; -+ i2c1 = &i2c1; -+ i2c2 = &i2c2; -+ i2c3 = &i2c3; -+ i2c4 = &i2c4; -+ i2c5 = &i2c5; -+ serial0 = &uart0; -+ serial1 = &uart1; -+ serial2 = &uart2; -+ serial3 = &uart3; -+ serial4 = &uart4; -+ serial5 = &uart5; -+ serial6 = &uart6; -+ serial7 = &uart7; -+ serial8 = &uart8; -+ serial9 = &uart9; -+ }; -+ -+ cpus { -+ #address-cells = <2>; -+ #size-cells = <0>; -+ -+ cpu0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a55"; -+ reg = <0x0 0x0>; -+ clocks = <&scmi_clk 0>; -+ #cooling-cells = <2>; -+ enable-method = "psci"; -+ operating-points-v2 = <&cpu0_opp_table>; -+ }; -+ -+ cpu1: cpu@100 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a55"; -+ reg = <0x0 0x100>; -+ #cooling-cells = <2>; -+ enable-method = "psci"; -+ operating-points-v2 = <&cpu0_opp_table>; -+ }; -+ -+ cpu2: cpu@200 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a55"; -+ reg = <0x0 0x200>; -+ #cooling-cells = <2>; -+ enable-method = "psci"; -+ operating-points-v2 = <&cpu0_opp_table>; -+ }; -+ -+ cpu3: cpu@300 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a55"; -+ reg = <0x0 0x300>; -+ #cooling-cells = <2>; -+ enable-method = "psci"; -+ operating-points-v2 = <&cpu0_opp_table>; -+ }; -+ }; -+ -+ cpu0_opp_table: opp-table-0 { -+ compatible = "operating-points-v2"; -+ opp-shared; -+ -+ opp-408000000 { -+ opp-hz = /bits/ 64 <408000000>; -+ opp-microvolt = <900000 900000 1150000>; -+ clock-latency-ns = <40000>; -+ }; -+ -+ opp-600000000 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt = <900000 900000 1150000>; -+ }; -+ -+ opp-816000000 { -+ opp-hz = /bits/ 64 <816000000>; -+ opp-microvolt = <900000 900000 1150000>; -+ opp-suspend; -+ }; -+ -+ opp-1104000000 { -+ opp-hz = /bits/ 64 <1104000000>; -+ opp-microvolt = <900000 900000 1150000>; -+ }; -+ -+ opp-1416000000 { -+ opp-hz = /bits/ 64 <1416000000>; -+ opp-microvolt = <900000 900000 1150000>; -+ }; -+ -+ opp-1608000000 { -+ opp-hz = /bits/ 64 <1608000000>; -+ opp-microvolt = <975000 975000 1150000>; -+ }; -+ -+ opp-1800000000 { -+ opp-hz = /bits/ 64 <1800000000>; -+ opp-microvolt = <1050000 1050000 1150000>; -+ }; -+ }; -+ -+ gpu_opp_table: gpu-opp-table { -+ compatible = "operating-points-v2"; -+ -+ opp-200000000 { -+ opp-hz = /bits/ 64 <200000000>; -+ opp-microvolt = <825000>; -+ }; -+ -+ opp-300000000 { -+ opp-hz = /bits/ 64 <300000000>; -+ opp-microvolt = <825000>; -+ }; -+ -+ opp-400000000 { -+ opp-hz = /bits/ 64 <400000000>; -+ opp-microvolt = <825000>; -+ }; -+ -+ opp-600000000 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt = <825000>; -+ }; -+ -+ opp-700000000 { -+ opp-hz = /bits/ 64 <700000000>; -+ opp-microvolt = <900000>; -+ }; -+ -+ opp-800000000 { -+ opp-hz = /bits/ 64 <800000000>; -+ opp-microvolt = <1000000>; -+ }; -+ }; -+ -+ firmware { -+ scmi: scmi { -+ compatible = "arm,scmi-smc"; -+ arm,smc-id = <0x82000010>; -+ shmem = <&scmi_shmem>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ scmi_clk: protocol@14 { -+ reg = <0x14>; -+ #clock-cells = <1>; -+ }; -+ }; -+ }; -+ -+ pmu { -+ compatible = "arm,cortex-a55-pmu"; -+ interrupts = , -+ , -+ , -+ ; -+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; -+ }; -+ -+ psci { -+ compatible = "arm,psci-1.0"; -+ method = "smc"; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = , -+ , -+ , -+ ; -+ arm,no-tick-in-suspend; -+ }; -+ -+ xin24m: xin24m { -+ compatible = "fixed-clock"; -+ clock-frequency = <24000000>; -+ clock-output-names = "xin24m"; -+ #clock-cells = <0>; -+ }; -+ -+ xin32k: xin32k { -+ compatible = "fixed-clock"; -+ clock-frequency = <32768>; -+ clock-output-names = "xin32k"; -+ pinctrl-0 = <&clk32k_out0>; -+ pinctrl-names = "default"; -+ #clock-cells = <0>; -+ }; -+ -+ sram@10f000 { -+ compatible = "mmio-sram"; -+ reg = <0x0 0x0010f000 0x0 0x100>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0 0x0 0x0010f000 0x100>; -+ -+ scmi_shmem: sram@0 { -+ compatible = "arm,scmi-shmem"; -+ reg = <0x0 0x100>; -+ }; -+ }; -+ -+ sata1: sata@fc400000 { -+ compatible = "snps,dwc-ahci"; -+ reg = <0 0xfc400000 0 0x1000>; -+ clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, -+ <&cru CLK_SATA1_RXOOB>; -+ clock-names = "sata", "pmalive", "rxoob"; -+ interrupts = ; -+ interrupt-names = "hostc"; -+ phys = <&combphy1_usq PHY_TYPE_SATA>; -+ phy-names = "sata-phy"; -+ ports-implemented = <0x1>; -+ power-domains = <&power RK3568_PD_PIPE>; -+ status = "disabled"; -+ }; -+ -+ sata2: sata@fc800000 { -+ compatible = "snps,dwc-ahci"; -+ reg = <0 0xfc800000 0 0x1000>; -+ clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, -+ <&cru CLK_SATA2_RXOOB>; -+ clock-names = "sata", "pmalive", "rxoob"; -+ interrupts = ; -+ interrupt-names = "hostc"; -+ phys = <&combphy2_psq PHY_TYPE_SATA>; -+ phy-names = "sata-phy"; -+ ports-implemented = <0x1>; -+ power-domains = <&power RK3568_PD_PIPE>; -+ status = "disabled"; -+ }; -+ -+ usbdrd30: usbdrd { -+ compatible = "rockchip,rk3399-dwc3", "snps,dwc3"; -+ clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, -+ <&cru ACLK_USB3OTG0>, <&cru PCLK_PIPE>; -+ clock-names = "ref_clk", "suspend_clk", -+ "bus_clk", "pipe_clk"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ status = "disabled"; -+ -+ usbdrd_dwc3: dwc3@fcc00000 { -+ compatible = "snps,dwc3"; -+ reg = <0x0 0xfcc00000 0x0 0x400000>; -+ interrupts = ; -+ dr_mode = "host"; -+ phys = <&u2phy0_otg>, <&combphy0_us PHY_TYPE_USB3>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ phy_type = "utmi_wide"; -+ power-domains = <&power RK3568_PD_PIPE>; -+ resets = <&cru SRST_USB3OTG0>; -+ reset-names = "usb3-otg"; -+ snps,dis_enblslpm_quirk; -+ snps,dis-u2-freeclk-exists-quirk; -+ snps,dis-del-phy-power-chg-quirk; -+ snps,dis-tx-ipgap-linecheck-quirk; -+ snps,xhci-trb-ent-quirk; -+ status = "disabled"; -+ }; -+ }; -+ -+ usbhost30: usbhost { -+ compatible = "rockchip,rk3399-dwc3", "snps,dwc3"; -+ clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, -+ <&cru ACLK_USB3OTG1>, <&cru PCLK_PIPE>; -+ clock-names = "ref_clk", "suspend_clk", -+ "bus_clk", "pipe_clk"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ assigned-clocks = <&cru CLK_PCIEPHY1_REF>; -+ assigned-clock-rates = <25000000>; -+ ranges; -+ status = "disabled"; -+ -+ usbhost_dwc3: dwc3@fd000000 { -+ compatible = "snps,dwc3"; -+ reg = <0x0 0xfd000000 0x0 0x400000>; -+ interrupts = ; -+ dr_mode = "host"; -+ phys = <&u2phy0_host>, <&combphy1_usq PHY_TYPE_USB3>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ phy_type = "utmi_wide"; -+ power-domains = <&power RK3568_PD_PIPE>; -+ resets = <&cru SRST_USB3OTG1>; -+ reset-names = "usb3-host"; -+ snps,dis_enblslpm_quirk; -+ snps,dis-u2-freeclk-exists-quirk; -+ snps,dis_u2_susphy_quirk; -+ snps,dis-del-phy-power-chg-quirk; -+ snps,dis-tx-ipgap-linecheck-quirk; -+ status = "disabled"; -+ }; -+ }; -+ -+ gic: interrupt-controller@fd400000 { -+ compatible = "arm,gic-v3"; -+ reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ -+ <0x0 0xfd460000 0 0x80000>; /* GICR */ -+ interrupts = ; -+ interrupt-controller; -+ #interrupt-cells = <3>; -+ mbi-alias = <0x0 0xfd410000>; -+ mbi-ranges = <296 24>; -+ msi-controller; -+ }; -+ -+ usb_host0_ehci: usb@fd800000 { -+ compatible = "generic-ehci"; -+ reg = <0x0 0xfd800000 0x0 0x40000>; -+ interrupts = ; -+ clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, -+ <&cru PCLK_USB>; -+ phys = <&u2phy1_otg>; -+ phy-names = "usb2-phy"; -+ status = "disabled"; -+ }; -+ -+ usb_host0_ohci: usb@fd840000 { -+ compatible = "generic-ohci"; -+ reg = <0x0 0xfd840000 0x0 0x40000>; -+ interrupts = ; -+ clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, -+ <&cru PCLK_USB>; -+ phys = <&u2phy1_otg>; -+ phy-names = "usb2-phy"; -+ status = "disabled"; -+ }; -+ -+ usb_host1_ehci: usb@fd880000 { -+ compatible = "generic-ehci"; -+ reg = <0x0 0xfd880000 0x0 0x40000>; -+ interrupts = ; -+ clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, -+ <&cru PCLK_USB>; -+ phys = <&u2phy1_host>; -+ phy-names = "usb2-phy"; -+ status = "disabled"; -+ }; -+ -+ usb_host1_ohci: usb@fd8c0000 { -+ compatible = "generic-ohci"; -+ reg = <0x0 0xfd8c0000 0x0 0x40000>; -+ interrupts = ; -+ clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, -+ <&cru PCLK_USB>; -+ phys = <&u2phy1_host>; -+ phy-names = "usb2-phy"; -+ status = "disabled"; -+ }; -+ -+ pmugrf: syscon@fdc20000 { -+ compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; -+ reg = <0x0 0xfdc20000 0x0 0x10000>; -+ -+ pmu_io_domains: io-domains { -+ compatible = "rockchip,rk3568-pmu-io-voltage-domain"; -+ status = "disabled"; -+ }; -+ }; -+ -+ pipegrf: syscon@fdc50000 { -+ reg = <0x0 0xfdc50000 0x0 0x1000>; -+ }; -+ -+ grf: syscon@fdc60000 { -+ compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; -+ reg = <0x0 0xfdc60000 0x0 0x10000>; -+ }; -+ -+ pipe_phy_grf0: syscon@fdc70000 { -+ compatible = "rockchip,pipe-phy-grf", "syscon"; -+ reg = <0x0 0xfdc70000 0x0 0x1000>; -+ }; -+ -+ pipe_phy_grf1: syscon@fdc80000 { -+ compatible = "rockchip,pipe-phy-grf", "syscon"; -+ reg = <0x0 0xfdc80000 0x0 0x1000>; -+ }; -+ -+ pipe_phy_grf2: syscon@fdc90000 { -+ compatible = "rockchip,pipe-phy-grf", "syscon"; -+ reg = <0x0 0xfdc90000 0x0 0x1000>; -+ }; -+ -+ usb2phy0_grf: syscon@fdca0000 { -+ compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; -+ reg = <0x0 0xfdca0000 0x0 0x8000>; -+ }; -+ -+ usb2phy1_grf: syscon@fdca8000 { -+ compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; -+ reg = <0x0 0xfdca8000 0x0 0x8000>; -+ }; -+ -+ pmucru: clock-controller@fdd00000 { -+ compatible = "rockchip,rk3568-pmucru"; -+ reg = <0x0 0xfdd00000 0x0 0x1000>; -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ }; -+ -+ cru: clock-controller@fdd20000 { -+ compatible = "rockchip,rk3568-cru"; -+ reg = <0x0 0xfdd20000 0x0 0x1000>; -+ #clock-cells = <1>; -+ #reset-cells = <1>; -+ assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>; -+ assigned-clock-rates = <1200000000>, <200000000>; -+ rockchip,grf = <&grf>; -+ }; -+ -+ i2c0: i2c@fdd40000 { -+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; -+ reg = <0x0 0xfdd40000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; -+ clock-names = "i2c", "pclk"; -+ pinctrl-0 = <&i2c0_xfer>; -+ pinctrl-names = "default"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ uart0: serial@fdd50000 { -+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; -+ reg = <0x0 0xfdd50000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; -+ clock-names = "baudclk", "apb_pclk"; -+ dmas = <&dmac0 0>, <&dmac0 1>; -+ dma-names = "tx", "rx"; -+ pinctrl-0 = <&uart0_xfer>; -+ pinctrl-names = "default"; -+ reg-io-width = <4>; -+ reg-shift = <2>; -+ status = "disabled"; -+ }; -+ -+ pwm0: pwm@fdd70000 { -+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfdd70000 0x0 0x10>; -+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm0m0_pins>; -+ pinctrl-names = "active"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm1: pwm@fdd70010 { -+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfdd70010 0x0 0x10>; -+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm1m0_pins>; -+ pinctrl-names = "active"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm2: pwm@fdd70020 { -+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfdd70020 0x0 0x10>; -+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm2m0_pins>; -+ pinctrl-names = "active"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm3: pwm@fdd70030 { -+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfdd70030 0x0 0x10>; -+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm3_pins>; -+ pinctrl-names = "active"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pmu: power-management@fdd90000 { -+ compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; -+ reg = <0x0 0xfdd90000 0x0 0x1000>; -+ -+ power: power-controller { -+ compatible = "rockchip,rk3568-power-controller"; -+ #power-domain-cells = <1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* These power domains are grouped by VD_GPU */ -+ power-domain@RK3568_PD_GPU { -+ reg = ; -+ clocks = <&cru ACLK_GPU_PRE>, -+ <&cru PCLK_GPU_PRE>; -+ pm_qos = <&qos_gpu>; -+ #power-domain-cells = <0>; -+ }; -+ -+ /* These power domains are grouped by VD_LOGIC */ -+ power-domain@RK3568_PD_VI { -+ reg = ; -+ clocks = <&cru HCLK_VI>, -+ <&cru PCLK_VI>; -+ pm_qos = <&qos_isp>, -+ <&qos_vicap0>, -+ <&qos_vicap1>; -+ #power-domain-cells = <0>; -+ }; -+ -+ power-domain@RK3568_PD_VO { -+ reg = ; -+ clocks = <&cru HCLK_VO>, -+ <&cru PCLK_VO>, -+ <&cru ACLK_VOP_PRE>; -+ pm_qos = <&qos_hdcp>, -+ <&qos_vop_m0>, -+ <&qos_vop_m1>; -+ #power-domain-cells = <0>; -+ }; -+ -+ power-domain@RK3568_PD_RGA { -+ reg = ; -+ clocks = <&cru HCLK_RGA_PRE>, -+ <&cru PCLK_RGA_PRE>; -+ pm_qos = <&qos_ebc>, -+ <&qos_iep>, -+ <&qos_jpeg_dec>, -+ <&qos_jpeg_enc>, -+ <&qos_rga_rd>, -+ <&qos_rga_wr>; -+ #power-domain-cells = <0>; -+ }; -+ -+ power-domain@RK3568_PD_VPU { -+ reg = ; -+ clocks = <&cru HCLK_VPU_PRE>; -+ pm_qos = <&qos_vpu>; -+ #power-domain-cells = <0>; -+ }; -+ -+ power-domain@RK3568_PD_RKVDEC { -+ clocks = <&cru HCLK_RKVDEC_PRE>; -+ reg = ; -+ pm_qos = <&qos_rkvdec>; -+ #power-domain-cells = <0>; -+ }; -+ -+ power-domain@RK3568_PD_RKVENC { -+ reg = ; -+ clocks = <&cru HCLK_RKVENC_PRE>; -+ pm_qos = <&qos_rkvenc_rd_m0>, -+ <&qos_rkvenc_rd_m1>, -+ <&qos_rkvenc_wr_m0>; -+ #power-domain-cells = <0>; -+ }; -+ }; -+ }; -+ -+ gpu: gpu@fde60000 { -+ compatible = "rockchip,rk3568-mali", "arm,mali-bifrost"; -+ reg = <0x0 0xfde60000 0x0 0x4000>; -+ -+ interrupts = , -+ , -+ ; -+ interrupt-names = "job", "mmu", "gpu"; -+ clocks = <&scmi_clk 1>, <&cru CLK_GPU>; -+ clock-names = "core", "bus"; -+ operating-points-v2 = <&gpu_opp_table>; -+ #cooling-cells = <2>; -+ power-domains = <&power RK3568_PD_GPU>; -+ status = "disabled"; -+ }; -+ -+ sdmmc2: mmc@fe000000 { -+ compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; -+ reg = <0x0 0xfe000000 0x0 0x4000>; -+ interrupts = ; -+ clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, -+ <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; -+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; -+ fifo-depth = <0x100>; -+ max-frequency = <150000000>; -+ resets = <&cru SRST_SDMMC2>; -+ reset-names = "reset"; -+ status = "disabled"; -+ }; -+ -+ gmac1: ethernet@fe010000 { -+ compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; -+ reg = <0x0 0xfe010000 0x0 0x10000>; -+ interrupts = , -+ ; -+ interrupt-names = "macirq", "eth_wake_irq"; -+ clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, -+ <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, -+ <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, -+ <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>; -+ clock-names = "stmmaceth", "mac_clk_rx", -+ "mac_clk_tx", "clk_mac_refout", -+ "aclk_mac", "pclk_mac", -+ "clk_mac_speed", "ptp_ref"; -+ resets = <&cru SRST_A_GMAC1>; -+ reset-names = "stmmaceth"; -+ rockchip,grf = <&grf>; -+ snps,axi-config = <&gmac1_stmmac_axi_setup>; -+ snps,mixed-burst; -+ snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; -+ snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; -+ snps,tso; -+ status = "disabled"; -+ -+ mdio1: mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <0x1>; -+ #size-cells = <0x0>; -+ }; -+ -+ gmac1_stmmac_axi_setup: stmmac-axi-config { -+ snps,blen = <0 0 0 0 16 8 4>; -+ snps,rd_osr_lmt = <8>; -+ snps,wr_osr_lmt = <4>; -+ }; -+ -+ gmac1_mtl_rx_setup: rx-queues-config { -+ snps,rx-queues-to-use = <1>; -+ queue0 {}; -+ }; -+ -+ gmac1_mtl_tx_setup: tx-queues-config { -+ snps,tx-queues-to-use = <1>; -+ queue0 {}; -+ }; -+ }; -+ -+ display_subsystem: display-subsystem { -+ compatible = "rockchip,display-subsystem"; -+ ports = <&vop_out>; -+ }; -+ -+ vop: vop@fe040000 { -+ compatible = "rockchip,rk3568-vop"; -+ reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; -+ reg-names = "regs", "gamma_lut"; -+ rockchip,grf = <&grf>; -+ interrupts = ; -+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; -+ clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2"; -+ iommus = <&vop_mmu>; -+ power-domains = <&power RK3568_PD_VO>; -+ status = "disabled"; -+ -+ vop_out: ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ vp0: port@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0>; -+ -+ vp0_out_hdmi: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&hdmi_in_vp0>; -+ status = "disabled"; -+ }; -+ }; -+ -+ vp1: port@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <1>; -+ -+ vp1_out_hdmi: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&hdmi_in_vp1>; -+ status = "disabled"; -+ }; -+ }; -+ -+ vp2: port@2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <2>; -+ -+ vp2_out_hdmi: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&hdmi_in_vp2>; -+ status = "disabled"; -+ }; -+ }; -+ }; -+ }; -+ -+ vop_mmu: iommu@fe043e00 { -+ compatible = "rockchip,rk3568-iommu"; -+ reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>; -+ interrupts = ; -+ interrupt-names = "vop_mmu"; -+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; -+ clock-names = "aclk", "iface"; -+ #iommu-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ hdmi: hdmi@fe0a0000 { -+ compatible = "rockchip,rk3568-dw-hdmi"; -+ reg = <0x0 0xfe0a0000 0x0 0x20000>; -+ interrupts = ; -+ clocks = <&cru PCLK_HDMI_HOST>, -+ <&cru CLK_HDMI_SFR>, -+ <&cru CLK_HDMI_CEC>, -+ <&cru HCLK_VOP>; -+ clock-names = "iahb", "isfr", "cec", "hclk"; -+ power-domains = <&power RK3568_PD_VO>; -+ reg-io-width = <4>; -+ rockchip,grf = <&grf>; -+ #sound-dai-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; -+ status = "disabled"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ hdmi_in: port@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ hdmi_in_vp0: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&vp0_out_hdmi>; -+ status = "disabled"; -+ }; -+ -+ hdmi_in_vp1: endpoint@1 { -+ reg = <1>; -+ remote-endpoint = <&vp1_out_hdmi>; -+ status = "disabled"; -+ }; -+ -+ hdmi_in_vp2: endpoint@2 { -+ reg = <2>; -+ remote-endpoint = <&vp2_out_hdmi>; -+ status = "disabled"; -+ }; -+ }; -+ }; -+ }; -+ -+ qos_gpu: qos@fe128000 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe128000 0x0 0x20>; -+ }; -+ -+ qos_rkvenc_rd_m0: qos@fe138080 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe138080 0x0 0x20>; -+ }; -+ -+ qos_rkvenc_rd_m1: qos@fe138100 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe138100 0x0 0x20>; -+ }; -+ -+ qos_rkvenc_wr_m0: qos@fe138180 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe138180 0x0 0x20>; -+ }; -+ -+ qos_isp: qos@fe148000 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe148000 0x0 0x20>; -+ }; -+ -+ qos_vicap0: qos@fe148080 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe148080 0x0 0x20>; -+ }; -+ -+ qos_vicap1: qos@fe148100 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe148100 0x0 0x20>; -+ }; -+ -+ qos_vpu: qos@fe150000 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe150000 0x0 0x20>; -+ }; -+ -+ qos_ebc: qos@fe158000 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe158000 0x0 0x20>; -+ }; -+ -+ qos_iep: qos@fe158100 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe158100 0x0 0x20>; -+ }; -+ -+ qos_jpeg_dec: qos@fe158180 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe158180 0x0 0x20>; -+ }; -+ -+ qos_jpeg_enc: qos@fe158200 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe158200 0x0 0x20>; -+ }; -+ -+ qos_rga_rd: qos@fe158280 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe158280 0x0 0x20>; -+ }; -+ -+ qos_rga_wr: qos@fe158300 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe158300 0x0 0x20>; -+ }; -+ -+ qos_npu: qos@fe180000 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe180000 0x0 0x20>; -+ }; -+ -+ qos_pcie2x1: qos@fe190000 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe190000 0x0 0x20>; -+ }; -+ -+ qos_sata1: qos@fe190280 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe190280 0x0 0x20>; -+ }; -+ -+ qos_sata2: qos@fe190300 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe190300 0x0 0x20>; -+ }; -+ -+ qos_usb3_0: qos@fe190380 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe190380 0x0 0x20>; -+ }; -+ -+ qos_usb3_1: qos@fe190400 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe190400 0x0 0x20>; -+ }; -+ -+ qos_rkvdec: qos@fe198000 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe198000 0x0 0x20>; -+ }; -+ -+ qos_hdcp: qos@fe1a8000 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe1a8000 0x0 0x20>; -+ }; -+ -+ qos_vop_m0: qos@fe1a8080 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe1a8080 0x0 0x20>; -+ }; -+ -+ qos_vop_m1: qos@fe1a8100 { -+ compatible = "rockchip,rk3568-qos", "syscon"; -+ reg = <0x0 0xfe1a8100 0x0 0x20>; -+ }; -+ -+ pcie2x1: pcie@fe260000 { -+ compatible = "rockchip,rk3568-pcie"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ bus-range = <0x0 0xf>; -+ assigned-clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, -+ <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, -+ <&cru CLK_PCIE20_AUX_NDFT>; -+ clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, -+ <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, -+ <&cru CLK_PCIE20_AUX_NDFT>; -+ clock-names = "aclk_mst", "aclk_slv", -+ "aclk_dbi", "pclk", "aux"; -+ device_type = "pci"; -+ interrupts = , -+ , -+ , -+ , -+ ; -+ interrupt-names = "sys", "pmc", "msi", "legacy", "err"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0 0 0 1 &pcie_intc 0>, -+ <0 0 0 2 &pcie_intc 1>, -+ <0 0 0 3 &pcie_intc 2>, -+ <0 0 0 4 &pcie_intc 3>; -+ linux,pci-domain = <0>; -+ num-ib-windows = <6>; -+ num-ob-windows = <2>; -+ max-link-speed = <2>; -+ msi-map = <0x0 &gic 0x0 0x1000>; -+ num-lanes = <1>; -+ phys = <&combphy2_psq PHY_TYPE_PCIE>; -+ phy-names = "pcie-phy"; -+ power-domains = <&power RK3568_PD_PIPE>; -+ reg = <0x3 0xc0000000 0x0 0x400000>, -+ <0x0 0xfe260000 0x0 0x10000>, -+ <0x3 0x3f800000 0x0 0x800000>; -+ ranges = <0x1000000 0x0 0x7f700000 0x3 0x3f700000 0x0 0x00100000 -+ 0x2000000 0x0 0x40000000 0x3 0x00000000 0x0 0x3f700000>; -+ reg-names = "dbi", "apb", "config"; -+ resets = <&cru SRST_PCIE20_POWERUP>; -+ reset-names = "pipe"; -+ status = "disabled"; -+ -+ pcie_intc: legacy-interrupt-controller { -+ #address-cells = <0>; -+ #interrupt-cells = <1>; -+ interrupt-controller; -+ interrupt-parent = <&gic>; -+ interrupts = ; -+ }; -+ -+ }; -+ -+ sdmmc0: mmc@fe2b0000 { -+ compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; -+ reg = <0x0 0xfe2b0000 0x0 0x4000>; -+ interrupts = ; -+ clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, -+ <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; -+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; -+ fifo-depth = <0x100>; -+ max-frequency = <150000000>; -+ resets = <&cru SRST_SDMMC0>; -+ reset-names = "reset"; -+ status = "disabled"; -+ }; -+ -+ sdmmc1: mmc@fe2c0000 { -+ compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; -+ reg = <0x0 0xfe2c0000 0x0 0x4000>; -+ interrupts = ; -+ clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, -+ <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; -+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; -+ fifo-depth = <0x100>; -+ max-frequency = <150000000>; -+ resets = <&cru SRST_SDMMC1>; -+ reset-names = "reset"; -+ status = "disabled"; -+ }; -+ -+ sfc: spi@fe300000 { -+ compatible = "rockchip,sfc"; -+ reg = <0x0 0xfe300000 0x0 0x4000>; -+ interrupts = ; -+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; -+ clock-names = "clk_sfc", "hclk_sfc"; -+ pinctrl-0 = <&fspi_pins>; -+ pinctrl-names = "default"; -+ status = "disabled"; -+ }; -+ -+ sdhci: mmc@fe310000 { -+ compatible = "rockchip,rk3568-dwcmshc"; -+ reg = <0x0 0xfe310000 0x0 0x10000>; -+ interrupts = ; -+ assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>; -+ assigned-clock-rates = <200000000>, <24000000>; -+ clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, -+ <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, -+ <&cru TCLK_EMMC>; -+ clock-names = "core", "bus", "axi", "block", "timer"; -+ status = "disabled"; -+ }; -+ -+ spdif: spdif@fe460000 { -+ compatible = "rockchip,rk3568-spdif"; -+ reg = <0x0 0xfe460000 0x0 0x1000>; -+ interrupts = ; -+ clock-names = "mclk", "hclk"; -+ clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; -+ dmas = <&dmac1 1>; -+ dma-names = "tx"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spdifm0_tx>; -+ #sound-dai-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2s1_8ch: i2s@fe410000 { -+ compatible = "rockchip,rk3568-i2s-tdm"; -+ reg = <0x0 0xfe410000 0x0 0x1000>; -+ interrupts = ; -+ assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>; -+ assigned-clock-rates = <1188000000>, <1188000000>; -+ clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, -+ <&cru HCLK_I2S1_8CH>; -+ clock-names = "mclk_tx", "mclk_rx", "hclk"; -+ dmas = <&dmac1 3>, <&dmac1 2>; -+ dma-names = "rx", "tx"; -+ resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; -+ reset-names = "tx-m", "rx-m"; -+ rockchip,grf = <&grf>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx -+ &i2s1m0_lrcktx &i2s1m0_lrckrx -+ &i2s1m0_sdi0 &i2s1m0_sdi1 -+ &i2s1m0_sdi2 &i2s1m0_sdi3 -+ &i2s1m0_sdo0 &i2s1m0_sdo1 -+ &i2s1m0_sdo2 &i2s1m0_sdo3>; -+ #sound-dai-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ dmac0: dmac@fe530000 { -+ compatible = "arm,pl330", "arm,primecell"; -+ reg = <0x0 0xfe530000 0x0 0x4000>; -+ interrupts = , -+ ; -+ arm,pl330-periph-burst; -+ clocks = <&cru ACLK_BUS>; -+ clock-names = "apb_pclk"; -+ #dma-cells = <1>; -+ }; -+ -+ dmac1: dmac@fe550000 { -+ compatible = "arm,pl330", "arm,primecell"; -+ reg = <0x0 0xfe550000 0x0 0x4000>; -+ interrupts = , -+ ; -+ arm,pl330-periph-burst; -+ clocks = <&cru ACLK_BUS>; -+ clock-names = "apb_pclk"; -+ #dma-cells = <1>; -+ }; -+ -+ i2c1: i2c@fe5a0000 { -+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; -+ reg = <0x0 0xfe5a0000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; -+ clock-names = "i2c", "pclk"; -+ pinctrl-0 = <&i2c1_xfer>; -+ pinctrl-names = "default"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2c2: i2c@fe5b0000 { -+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; -+ reg = <0x0 0xfe5b0000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; -+ clock-names = "i2c", "pclk"; -+ pinctrl-0 = <&i2c2m0_xfer>; -+ pinctrl-names = "default"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2c3: i2c@fe5c0000 { -+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; -+ reg = <0x0 0xfe5c0000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; -+ clock-names = "i2c", "pclk"; -+ pinctrl-0 = <&i2c3m0_xfer>; -+ pinctrl-names = "default"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2c4: i2c@fe5d0000 { -+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; -+ reg = <0x0 0xfe5d0000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; -+ clock-names = "i2c", "pclk"; -+ pinctrl-0 = <&i2c4m0_xfer>; -+ pinctrl-names = "default"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2c5: i2c@fe5e0000 { -+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c"; -+ reg = <0x0 0xfe5e0000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; -+ clock-names = "i2c", "pclk"; -+ pinctrl-0 = <&i2c5m0_xfer>; -+ pinctrl-names = "default"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ wdt: watchdog@fe600000 { -+ compatible = "rockchip,rk3568-wdt", "snps,dw-wdt"; -+ reg = <0x0 0xfe600000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; -+ clock-names = "tclk", "pclk"; -+ }; -+ -+ uart1: serial@fe650000 { -+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; -+ reg = <0x0 0xfe650000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; -+ clock-names = "baudclk", "apb_pclk"; -+ dmas = <&dmac0 2>, <&dmac0 3>; -+ dma-names = "tx", "rx"; -+ pinctrl-0 = <&uart1m0_xfer>; -+ pinctrl-names = "default"; -+ reg-io-width = <4>; -+ reg-shift = <2>; -+ status = "disabled"; -+ }; -+ -+ uart2: serial@fe660000 { -+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; -+ reg = <0x0 0xfe660000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; -+ clock-names = "baudclk", "apb_pclk"; -+ dmas = <&dmac0 4>, <&dmac0 5>; -+ dma-names = "tx", "rx"; -+ pinctrl-0 = <&uart2m0_xfer>; -+ pinctrl-names = "default"; -+ reg-io-width = <4>; -+ reg-shift = <2>; -+ status = "disabled"; -+ }; -+ -+ uart3: serial@fe670000 { -+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; -+ reg = <0x0 0xfe670000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; -+ clock-names = "baudclk", "apb_pclk"; -+ dmas = <&dmac0 6>, <&dmac0 7>; -+ dma-names = "tx", "rx"; -+ pinctrl-0 = <&uart3m0_xfer>; -+ pinctrl-names = "default"; -+ reg-io-width = <4>; -+ reg-shift = <2>; -+ status = "disabled"; -+ }; -+ -+ uart4: serial@fe680000 { -+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; -+ reg = <0x0 0xfe680000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; -+ clock-names = "baudclk", "apb_pclk"; -+ dmas = <&dmac0 8>, <&dmac0 9>; -+ dma-names = "tx", "rx"; -+ pinctrl-0 = <&uart4m0_xfer>; -+ pinctrl-names = "default"; -+ reg-io-width = <4>; -+ reg-shift = <2>; -+ status = "disabled"; -+ }; -+ -+ uart5: serial@fe690000 { -+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; -+ reg = <0x0 0xfe690000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; -+ clock-names = "baudclk", "apb_pclk"; -+ dmas = <&dmac0 10>, <&dmac0 11>; -+ dma-names = "tx", "rx"; -+ pinctrl-0 = <&uart5m0_xfer>; -+ pinctrl-names = "default"; -+ reg-io-width = <4>; -+ reg-shift = <2>; -+ status = "disabled"; -+ }; -+ -+ uart6: serial@fe6a0000 { -+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; -+ reg = <0x0 0xfe6a0000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; -+ clock-names = "baudclk", "apb_pclk"; -+ dmas = <&dmac0 12>, <&dmac0 13>; -+ dma-names = "tx", "rx"; -+ pinctrl-0 = <&uart6m0_xfer>; -+ pinctrl-names = "default"; -+ reg-io-width = <4>; -+ reg-shift = <2>; -+ status = "disabled"; -+ }; -+ -+ uart7: serial@fe6b0000 { -+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; -+ reg = <0x0 0xfe6b0000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; -+ clock-names = "baudclk", "apb_pclk"; -+ dmas = <&dmac0 14>, <&dmac0 15>; -+ dma-names = "tx", "rx"; -+ pinctrl-0 = <&uart7m0_xfer>; -+ pinctrl-names = "default"; -+ reg-io-width = <4>; -+ reg-shift = <2>; -+ status = "disabled"; -+ }; -+ -+ uart8: serial@fe6c0000 { -+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; -+ reg = <0x0 0xfe6c0000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; -+ clock-names = "baudclk", "apb_pclk"; -+ dmas = <&dmac0 16>, <&dmac0 17>; -+ dma-names = "tx", "rx"; -+ pinctrl-0 = <&uart8m0_xfer>; -+ pinctrl-names = "default"; -+ reg-io-width = <4>; -+ reg-shift = <2>; -+ status = "disabled"; -+ }; -+ -+ uart9: serial@fe6d0000 { -+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; -+ reg = <0x0 0xfe6d0000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; -+ clock-names = "baudclk", "apb_pclk"; -+ dmas = <&dmac0 18>, <&dmac0 19>; -+ dma-names = "tx", "rx"; -+ pinctrl-0 = <&uart9m0_xfer>; -+ pinctrl-names = "default"; -+ reg-io-width = <4>; -+ reg-shift = <2>; -+ status = "disabled"; -+ }; -+ -+ thermal_zones: thermal-zones { -+ cpu_thermal: cpu-thermal { -+ polling-delay-passive = <100>; -+ polling-delay = <1000>; -+ -+ thermal-sensors = <&tsadc 0>; -+ -+ trips { -+ cpu_alert0: cpu_alert0 { -+ temperature = <70000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ cpu_alert1: cpu_alert1 { -+ temperature = <75000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ cpu_crit: cpu_crit { -+ temperature = <95000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&cpu_alert0>; -+ cooling-device = -+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ -+ gpu_thermal: gpu-thermal { -+ polling-delay-passive = <20>; /* milliseconds */ -+ polling-delay = <1000>; /* milliseconds */ -+ -+ thermal-sensors = <&tsadc 1>; -+ }; -+ }; -+ -+ tsadc: tsadc@fe710000 { -+ compatible = "rockchip,rk3568-tsadc"; -+ reg = <0x0 0xfe710000 0x0 0x100>; -+ interrupts = ; -+ assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; -+ assigned-clock-rates = <17000000>, <700000>; -+ clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; -+ clock-names = "tsadc", "apb_pclk"; -+ resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>, -+ <&cru SRST_TSADCPHY>; -+ rockchip,grf = <&grf>; -+ rockchip,hw-tshut-temp = <95000>; -+ pinctrl-names = "init", "default", "sleep"; -+ pinctrl-0 = <&tsadc_pin>; -+ pinctrl-1 = <&tsadc_shutorg>; -+ pinctrl-2 = <&tsadc_pin>; -+ #thermal-sensor-cells = <1>; -+ status = "disabled"; -+ }; -+ -+ saradc: saradc@fe720000 { -+ compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; -+ reg = <0x0 0xfe720000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; -+ clock-names = "saradc", "apb_pclk"; -+ resets = <&cru SRST_P_SARADC>; -+ reset-names = "saradc-apb"; -+ #io-channel-cells = <1>; -+ status = "disabled"; -+ }; -+ -+ pwm4: pwm@fe6e0000 { -+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfe6e0000 0x0 0x10>; -+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm4_pins>; -+ pinctrl-names = "active"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm5: pwm@fe6e0010 { -+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfe6e0010 0x0 0x10>; -+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm5_pins>; -+ pinctrl-names = "active"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm6: pwm@fe6e0020 { -+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfe6e0020 0x0 0x10>; -+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm6_pins>; -+ pinctrl-names = "active"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm7: pwm@fe6e0030 { -+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfe6e0030 0x0 0x10>; -+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm7_pins>; -+ pinctrl-names = "active"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm8: pwm@fe6f0000 { -+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfe6f0000 0x0 0x10>; -+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm8m0_pins>; -+ pinctrl-names = "active"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm9: pwm@fe6f0010 { -+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfe6f0010 0x0 0x10>; -+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm9m0_pins>; -+ pinctrl-names = "active"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm10: pwm@fe6f0020 { -+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfe6f0020 0x0 0x10>; -+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm10m0_pins>; -+ pinctrl-names = "active"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm11: pwm@fe6f0030 { -+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfe6f0030 0x0 0x10>; -+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm11m0_pins>; -+ pinctrl-names = "active"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm12: pwm@fe700000 { -+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfe700000 0x0 0x10>; -+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm12m0_pins>; -+ pinctrl-names = "active"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm13: pwm@fe700010 { -+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfe700010 0x0 0x10>; -+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm13m0_pins>; -+ pinctrl-names = "active"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm14: pwm@fe700020 { -+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfe700020 0x0 0x10>; -+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm14m0_pins>; -+ pinctrl-names = "active"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ pwm15: pwm@fe700030 { -+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; -+ reg = <0x0 0xfe700030 0x0 0x10>; -+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; -+ clock-names = "pwm", "pclk"; -+ pinctrl-0 = <&pwm15m0_pins>; -+ pinctrl-names = "active"; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ -+ combphy1_usq: phy@fe830000 { -+ compatible = "rockchip,rk3568-naneng-combphy"; -+ reg = <0x0 0xfe830000 0x0 0x100>; -+ #phy-cells = <1>; -+ assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; -+ assigned-clock-rates = <100000000>; -+ clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>, -+ <&cru PCLK_PIPE>; -+ clock-names = "ref", "apb", "pipe"; -+ resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>; -+ reset-names = "combphy-apb", "combphy"; -+ rockchip,pipe-grf = <&pipegrf>; -+ rockchip,pipe-phy-grf = <&pipe_phy_grf1>; -+ status = "disabled"; -+ }; -+ -+ combphy2_psq: phy@fe840000 { -+ compatible = "rockchip,rk3568-naneng-combphy"; -+ reg = <0x0 0xfe840000 0x0 0x100>; -+ #phy-cells = <1>; -+ assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; -+ assigned-clock-rates = <100000000>; -+ clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>, -+ <&cru PCLK_PIPE>; -+ clock-names = "ref", "apb", "pipe"; -+ resets = <&cru SRST_P_PIPEPHY2>, <&cru SRST_PIPEPHY2>; -+ reset-names = "combphy-apb", "combphy"; -+ rockchip,pipe-grf = <&pipegrf>; -+ rockchip,pipe-phy-grf = <&pipe_phy_grf2>; -+ status = "disabled"; -+ }; -+ -+ usb2phy0: usb2-phy@fe8a0000 { -+ compatible = "rockchip,rk3568-usb2phy"; -+ reg = <0x0 0xfe8a0000 0x0 0x10000>; -+ clocks = <&pmucru CLK_USBPHY0_REF>; -+ clock-names = "phyclk"; -+ #clock-cells = <0>; -+ clock-output-names = "usb480m_phy"; -+ interrupts = ; -+ rockchip,usbgrf = <&usb2phy0_grf>; -+ status = "disabled"; -+ -+ u2phy0_host: host-port { -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ u2phy0_otg: otg-port { -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ }; -+ -+ usb2phy1: usb2-phy@fe8b0000 { -+ compatible = "rockchip,rk3568-usb2phy"; -+ reg = <0x0 0xfe8b0000 0x0 0x10000>; -+ clocks = <&pmucru CLK_USBPHY1_REF>; -+ clock-names = "phyclk"; -+ #clock-cells = <0>; -+ interrupts = ; -+ rockchip,usbgrf = <&usb2phy1_grf>; -+ status = "disabled"; -+ -+ u2phy1_host: host-port { -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ u2phy1_otg: otg-port { -+ #phy-cells = <0>; -+ status = "disabled"; -+ }; -+ }; -+ -+ pinctrl: pinctrl { -+ compatible = "rockchip,rk3568-pinctrl"; -+ rockchip,grf = <&grf>; -+ rockchip,pmu = <&pmugrf>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ gpio0: gpio@fdd60000 { -+ compatible = "rockchip,gpio-bank"; -+ reg = <0x0 0xfdd60000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio1: gpio@fe740000 { -+ compatible = "rockchip,gpio-bank"; -+ reg = <0x0 0xfe740000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio2: gpio@fe750000 { -+ compatible = "rockchip,gpio-bank"; -+ reg = <0x0 0xfe750000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio3: gpio@fe760000 { -+ compatible = "rockchip,gpio-bank"; -+ reg = <0x0 0xfe760000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio4: gpio@fe770000 { -+ compatible = "rockchip,gpio-bank"; -+ reg = <0x0 0xfe770000 0x0 0x100>; -+ interrupts = ; -+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ }; -+}; -+ -+#include "rk3568-pinctrl.dtsi" ---- a/arch/arm/mach-rockchip/rk3568/rk3568.c -+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c -@@ -55,7 +55,7 @@ enum { - }; - - const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { -- [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe310000", -+ [BROM_BOOTSOURCE_EMMC] = "/mmc@fe310000", - [BROM_BOOTSOURCE_SPINOR] = "/spi@fe300000/flash@0", - [BROM_BOOTSOURCE_SD] = "/mmc@fe2b0000", - }; diff --git a/5.4/package/boot/uboot-rockchip/patches/005-rockchip-rk356x-HACK-fix-sdmmc-support.patch b/5.4/package/boot/uboot-rockchip/patches/005-rockchip-rk356x-HACK-fix-sdmmc-support.patch deleted file mode 100644 index 10e4dd11..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/005-rockchip-rk356x-HACK-fix-sdmmc-support.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 01e8a38985a90043abddc5c5bcd049c74bb29a53 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Sun, 19 Dec 2021 18:52:18 -0500 -Subject: [PATCH 05/11] rockchip: rk356x: HACK: fix sdmmc support - -HACK: lock mmc0 to initial frequency and disable dw-mmc control of power -line. - -The sdmmc on quartz64-a is powered by the sdmmc0 power line, which is -active low. -Even though it is set as a gpio, it still seems to be triggered by the -dw-mmc driver toggling the power line. -Downstream fixes this by setting this to "0" instead of "1" using -kconfigs. - -Also, for some reason the controller will only operate at initial -frequencies. - -Signed-off-by: Peter Geis ---- - arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi | 4 +++- - drivers/mmc/dw_mmc.c | 3 ++- - 2 files changed, 5 insertions(+), 2 deletions(-) - ---- a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi -+++ b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi -@@ -13,8 +13,10 @@ - }; - - &sdmmc0 { -+ max-frequency = <400000>; -+ bus-width = <4>; - u-boot,dm-spl; -- status = "okay"; -+ u-boot,spl-fifo-mode; - }; - - &uart2 { ---- a/drivers/mmc/dw_mmc.c -+++ b/drivers/mmc/dw_mmc.c -@@ -529,7 +529,8 @@ static int dwmci_init(struct mmc *mmc) - if (host->board_init) - host->board_init(host); - -- dwmci_writel(host, DWMCI_PWREN, 1); -+// dwmci_writel(host, DWMCI_PWREN, 1); -+ dwmci_writel(host, DWMCI_PWREN, 0); - - if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) { - debug("%s[%d] Fail-reset!!\n", __func__, __LINE__); diff --git a/5.4/package/boot/uboot-rockchip/patches/006-rockchip-rk356x-add-quartz64-a-board.patch b/5.4/package/boot/uboot-rockchip/patches/006-rockchip-rk356x-add-quartz64-a-board.patch deleted file mode 100644 index 0a5d784b..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/006-rockchip-rk356x-add-quartz64-a-board.patch +++ /dev/null @@ -1,214 +0,0 @@ -From 9f623c0e96fc7c3b5c9b7a81f0a3017c47033ec7 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Sun, 19 Dec 2021 18:57:36 -0500 -Subject: [PATCH 06/11] rockchip: rk356x: add quartz64-a board - -Signed-off-by: Peter Geis ---- - arch/arm/mach-rockchip/rk3568/Kconfig | 12 ++- - board/pine64/quartz64-a-rk3566/Kconfig | 15 ++++ - board/pine64/quartz64-a-rk3566/Makefile | 4 + - .../quartz64-a-rk3566/quartz64-a-rk3566.c | 1 + - configs/quartz64-a-rk3566_defconfig | 77 +++++++++++++++++++ - include/configs/quartz64-a-rk3566.h | 14 ++++ - include/dt-bindings/power/rk3568-power.h | 32 ++++++++ - 7 files changed, 154 insertions(+), 1 deletion(-) - create mode 100644 board/pine64/quartz64-a-rk3566/Kconfig - create mode 100644 board/pine64/quartz64-a-rk3566/Makefile - create mode 100644 board/pine64/quartz64-a-rk3566/quartz64-a-rk3566.c - create mode 100644 configs/quartz64-a-rk3566_defconfig - create mode 100644 include/configs/quartz64-a-rk3566.h - create mode 100644 include/dt-bindings/power/rk3568-power.h - ---- a/arch/arm/mach-rockchip/rk3568/Kconfig -+++ b/arch/arm/mach-rockchip/rk3568/Kconfig -@@ -1,11 +1,20 @@ - if ROCKCHIP_RK3568 - -+choice -+ prompt "RK3568/RK3566 board select" -+ - config TARGET_EVB_RK3568 - bool "RK3568 evaluation board" -- select BOARD_LATE_INIT - help - RK3568 EVB is a evaluation board for Rockchp RK3568. - -+config TARGET_QUARTZ64_A_RK3566 -+ bool "Quartz64 Model A RK3566 development board" -+ help -+ Quartz64 Model A RK3566 is a development board from Pine64. -+ -+endchoice -+ - config ROCKCHIP_BOOT_MODE_REG - default 0xfdc20200 - -@@ -19,5 +28,6 @@ config SYS_MALLOC_F_LEN - default 0x2000 - - source "board/rockchip/evb_rk3568/Kconfig" -+source "board/pine64/quartz64-a-rk3566/Kconfig" - - endif ---- /dev/null -+++ b/board/pine64/quartz64-a-rk3566/Kconfig -@@ -0,0 +1,15 @@ -+if TARGET_QUARTZ64_A_RK3566 -+ -+config SYS_BOARD -+ default "quartz64-a-rk3566" -+ -+config SYS_VENDOR -+ default "pine64" -+ -+config SYS_CONFIG_NAME -+ default "quartz64-a-rk3566" -+ -+config BOARD_SPECIFIC_OPTIONS # dummy -+ def_bool y -+ -+endif ---- /dev/null -+++ b/board/pine64/quartz64-a-rk3566/Makefile -@@ -0,0 +1,4 @@ -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+obj-y += quartz64-a-rk3566.o ---- /dev/null -+++ b/board/pine64/quartz64-a-rk3566/quartz64-a-rk3566.c -@@ -0,0 +1 @@ -+// SPDX-License-Identifier: GPL-2.0+ ---- /dev/null -+++ b/configs/quartz64-a-rk3566_defconfig -@@ -0,0 +1,77 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00a00000 -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_DEFAULT_DEVICE_TREE="rk3566-quartz64-a" -+CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y -+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_MMC=y -+CONFIG_SPL_SERIAL=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_TARGET_QUARTZ64_A_RK3566=y -+CONFIG_DEBUG_UART_BASE=0xFE660000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0xc00800 -+CONFIG_API=y -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-quartz64-a.dtb" -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_SEPARATE_BSS=y -+CONFIG_SPL_ATF=y -+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y -+CONFIG_CMD_BIND=y -+CONFIG_CMD_CLK=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_PMIC=y -+CONFIG_CMD_REGULATOR=y -+# CONFIG_SPL_DOS_PARTITION is not set -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_LIVE=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_SPL_REGMAP=y -+CONFIG_SPL_SYSCON=y -+CONFIG_SPL_CLK=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_SPL_MMC_HS200_SUPPORT=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_PMIC_RK8XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_SPL_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_SPL_RAM=y -+CONFIG_DM_RESET=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSRESET=y -+CONFIG_SYSRESET_PSCI=y -+CONFIG_ERRNO_STR=y ---- /dev/null -+++ b/include/configs/quartz64-a-rk3566.h -@@ -0,0 +1,14 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+ -+#ifndef __QUARTZ64_A_RK3566_H -+#define __QUARTZ64_A_RK3566_H -+ -+#include -+ -+#define CONFIG_SUPPORT_EMMC_RPMB -+ -+#define ROCKCHIP_DEVICE_SETTINGS \ -+ "stdout=serial,vidconsole\0" \ -+ "stderr=serial,vidconsole\0" -+ -+#endif ---- /dev/null -+++ b/include/dt-bindings/power/rk3568-power.h -@@ -0,0 +1,32 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__ -+#define __DT_BINDINGS_POWER_RK3568_POWER_H__ -+ -+/* VD_CORE */ -+#define RK3568_PD_CPU_0 0 -+#define RK3568_PD_CPU_1 1 -+#define RK3568_PD_CPU_2 2 -+#define RK3568_PD_CPU_3 3 -+#define RK3568_PD_CORE_ALIVE 4 -+ -+/* VD_PMU */ -+#define RK3568_PD_PMU 5 -+ -+/* VD_NPU */ -+#define RK3568_PD_NPU 6 -+ -+/* VD_GPU */ -+#define RK3568_PD_GPU 7 -+ -+/* VD_LOGIC */ -+#define RK3568_PD_VI 8 -+#define RK3568_PD_VO 9 -+#define RK3568_PD_RGA 10 -+#define RK3568_PD_VPU 11 -+#define RK3568_PD_CENTER 12 -+#define RK3568_PD_RKVDEC 13 -+#define RK3568_PD_RKVENC 14 -+#define RK3568_PD_PIPE 15 -+#define RK3568_PD_LOGIC_ALIVE 16 -+ -+#endif diff --git a/5.4/package/boot/uboot-rockchip/patches/007-gpio-rockchip-rk_gpio-support-v2-gpio-controller.patch b/5.4/package/boot/uboot-rockchip/patches/007-gpio-rockchip-rk_gpio-support-v2-gpio-controller.patch deleted file mode 100644 index 3066eaaf..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/007-gpio-rockchip-rk_gpio-support-v2-gpio-controller.patch +++ /dev/null @@ -1,755 +0,0 @@ -From 3a4d973a743bc76cc734db9616f9053f45fa922f Mon Sep 17 00:00:00 2001 -From: Jianqun Xu -Date: Thu, 28 May 2020 11:01:58 +0800 -Subject: [PATCH 07/11] gpio/rockchip: rk_gpio support v2 gpio controller - -The v2 gpio controller add write enable bit for some register, -such as data register, data direction register and so on. - -This patch support v2 gpio controller by redefine the read and -write operation functions. - -Also adds support for the rk3568 pinctrl device. - -Squash all fixes into this commit. - -Change-Id: I2adbcca06a37c48e6f494b89833cd034ba0dae29 -Signed-off-by: Jianqun Xu -Signed-off-by: Peter Geis ---- - arch/arm/include/asm/arch-rockchip/gpio.h | 36 ++ - drivers/gpio/Kconfig | 13 + - drivers/gpio/rk_gpio.c | 89 ++++- - drivers/pinctrl/rockchip/Makefile | 1 + - drivers/pinctrl/rockchip/pinctrl-rk3568.c | 360 ++++++++++++++++++ - .../pinctrl/rockchip/pinctrl-rockchip-core.c | 11 +- - drivers/pinctrl/rockchip/pinctrl-rockchip.h | 42 ++ - 7 files changed, 530 insertions(+), 22 deletions(-) - create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3568.c - ---- a/arch/arm/include/asm/arch-rockchip/gpio.h -+++ b/arch/arm/include/asm/arch-rockchip/gpio.h -@@ -6,6 +6,7 @@ - #ifndef _ASM_ARCH_GPIO_H - #define _ASM_ARCH_GPIO_H - -+#ifndef CONFIG_ROCKCHIP_GPIO_V2 - struct rockchip_gpio_regs { - u32 swport_dr; - u32 swport_ddr; -@@ -23,6 +24,41 @@ struct rockchip_gpio_regs { - u32 ls_sync; - }; - check_member(rockchip_gpio_regs, ls_sync, 0x60); -+#else -+struct rockchip_gpio_regs { -+ u32 swport_dr_l; /* ADDRESS OFFSET: 0x0000 */ -+ u32 swport_dr_h; /* ADDRESS OFFSET: 0x0004 */ -+ u32 swport_ddr_l; /* ADDRESS OFFSET: 0x0008 */ -+ u32 swport_ddr_h; /* ADDRESS OFFSET: 0x000c */ -+ u32 int_en_l; /* ADDRESS OFFSET: 0x0010 */ -+ u32 int_en_h; /* ADDRESS OFFSET: 0x0014 */ -+ u32 int_mask_l; /* ADDRESS OFFSET: 0x0018 */ -+ u32 int_mask_h; /* ADDRESS OFFSET: 0x001c */ -+ u32 int_type_l; /* ADDRESS OFFSET: 0x0020 */ -+ u32 int_type_h; /* ADDRESS OFFSET: 0x0024 */ -+ u32 int_polarity_l; /* ADDRESS OFFSET: 0x0028 */ -+ u32 int_polarity_h; /* ADDRESS OFFSET: 0x002c */ -+ u32 int_bothedge_l; /* ADDRESS OFFSET: 0x0030 */ -+ u32 int_bothedge_h; /* ADDRESS OFFSET: 0x0034 */ -+ u32 debounce_l; /* ADDRESS OFFSET: 0x0038 */ -+ u32 debounce_h; /* ADDRESS OFFSET: 0x003c */ -+ u32 dbclk_div_en_l; /* ADDRESS OFFSET: 0x0040 */ -+ u32 dbclk_div_en_h; /* ADDRESS OFFSET: 0x0044 */ -+ u32 dbclk_div_con; /* ADDRESS OFFSET: 0x0048 */ -+ u32 reserved004c; /* ADDRESS OFFSET: 0x004c */ -+ u32 int_status; /* ADDRESS OFFSET: 0x0050 */ -+ u32 reserved0054; /* ADDRESS OFFSET: 0x0054 */ -+ u32 int_rawstatus; /* ADDRESS OFFSET: 0x0058 */ -+ u32 reserved005c; /* ADDRESS OFFSET: 0x005c */ -+ u32 port_eoi_l; /* ADDRESS OFFSET: 0x0060 */ -+ u32 port_eoi_h; /* ADDRESS OFFSET: 0x0064 */ -+ u32 reserved0068[2]; /* ADDRESS OFFSET: 0x0068 */ -+ u32 ext_port; /* ADDRESS OFFSET: 0x0070 */ -+ u32 reserved0074; /* ADDRESS OFFSET: 0x0074 */ -+ u32 ver_id; /* ADDRESS OFFSET: 0x0078 */ -+}; -+check_member(rockchip_gpio_regs, ver_id, 0x0078); -+#endif - - enum gpio_pu_pd { - GPIO_PULL_NORMAL = 0, ---- a/drivers/gpio/Kconfig -+++ b/drivers/gpio/Kconfig -@@ -341,6 +341,19 @@ config ROCKCHIP_GPIO - The GPIOs for a device are defined in the device tree with one node - for each bank. - -+config ROCKCHIP_GPIO_V2 -+ bool "Rockchip GPIO driver version 2.0" -+ depends on ROCKCHIP_GPIO -+ default n -+ help -+ Support GPIO access on Rockchip SoCs. The GPIOs are arranged into -+ a number of banks (different for each SoC type) each with 32 GPIOs. -+ The GPIOs for a device are defined in the device tree with one node -+ for each bank. -+ -+ Support version 2.0 GPIO controller, which support write enable bits -+ for some registers, such as dr, ddr. -+ - config SANDBOX_GPIO - bool "Enable sandbox GPIO driver" - depends on SANDBOX && DM && DM_GPIO ---- a/drivers/gpio/rk_gpio.c -+++ b/drivers/gpio/rk_gpio.c -@@ -2,12 +2,15 @@ - /* - * (C) Copyright 2015 Google, Inc - * -- * (C) Copyright 2008-2014 Rockchip Electronics -+ * (C) Copyright 2008-2020 Rockchip Electronics - * Peter, Software Engineering, . -+ * Jianqun Xu, Software Engineering, . - */ - - #include - #include -+#include -+#include - #include - #include - #include -@@ -17,12 +20,34 @@ - #include - #include - --enum { -- ROCKCHIP_GPIOS_PER_BANK = 32, --}; -+#include "../pinctrl/rockchip/pinctrl-rockchip.h" - - #define OFFSET_TO_BIT(bit) (1UL << (bit)) - -+#ifdef CONFIG_ROCKCHIP_GPIO_V2 -+#define REG_L(R) (R##_l) -+#define REG_H(R) (R##_h) -+#define READ_REG(REG) ((readl(REG_L(REG)) & 0xFFFF) | \ -+ ((readl(REG_H(REG)) & 0xFFFF) << 16)) -+#define WRITE_REG(REG, VAL) \ -+{\ -+ writel(((VAL) & 0xFFFF) | 0xFFFF0000, REG_L(REG)); \ -+ writel((((VAL) & 0xFFFF0000) >> 16) | 0xFFFF0000, REG_H(REG));\ -+} -+#define CLRBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) & ~(MASK)) -+#define SETBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) | (MASK)) -+#define CLRSETBITS_LE32(REG, MASK, VAL) WRITE_REG(REG, \ -+ (READ_REG(REG) & ~(MASK)) | (VAL)) -+ -+#else -+#define READ_REG(REG) readl(REG) -+#define WRITE_REG(REG, VAL) writel(VAL, REG) -+#define CLRBITS_LE32(REG, MASK) clrbits_le32(REG, MASK) -+#define SETBITS_LE32(REG, MASK) setbits_le32(REG, MASK) -+#define CLRSETBITS_LE32(REG, MASK, VAL) clrsetbits_le32(REG, MASK, VAL) -+#endif -+ -+ - struct rockchip_gpio_priv { - struct rockchip_gpio_regs *regs; - struct udevice *pinctrl; -@@ -35,7 +60,7 @@ static int rockchip_gpio_direction_input - struct rockchip_gpio_priv *priv = dev_get_priv(dev); - struct rockchip_gpio_regs *regs = priv->regs; - -- clrbits_le32(®s->swport_ddr, OFFSET_TO_BIT(offset)); -+ CLRBITS_LE32(®s->swport_ddr, OFFSET_TO_BIT(offset)); - - return 0; - } -@@ -47,8 +72,8 @@ static int rockchip_gpio_direction_outpu - struct rockchip_gpio_regs *regs = priv->regs; - int mask = OFFSET_TO_BIT(offset); - -- clrsetbits_le32(®s->swport_dr, mask, value ? mask : 0); -- setbits_le32(®s->swport_ddr, mask); -+ CLRSETBITS_LE32(®s->swport_dr, mask, value ? mask : 0); -+ SETBITS_LE32(®s->swport_ddr, mask); - - return 0; - } -@@ -68,7 +93,7 @@ static int rockchip_gpio_set_value(struc - struct rockchip_gpio_regs *regs = priv->regs; - int mask = OFFSET_TO_BIT(offset); - -- clrsetbits_le32(®s->swport_dr, mask, value ? mask : 0); -+ CLRSETBITS_LE32(®s->swport_dr, mask, value ? mask : 0); - - return 0; - } -@@ -86,8 +111,8 @@ static int rockchip_gpio_get_function(st - ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset); - if (ret) - return ret; -- is_output = readl(®s->swport_ddr) & OFFSET_TO_BIT(offset); -- -+ is_output = READ_REG(®s->swport_ddr) & OFFSET_TO_BIT(offset); -+ - return is_output ? GPIOF_OUTPUT : GPIOF_INPUT; - #endif - } -@@ -142,19 +167,49 @@ static int rockchip_gpio_probe(struct ud - { - struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); - struct rockchip_gpio_priv *priv = dev_get_priv(dev); -- char *end; -- int ret; -+ struct rockchip_pinctrl_priv *pctrl_priv; -+ struct rockchip_pin_bank *bank; -+ char *end = NULL; -+ static int gpio; -+ int id = -1, ret; - - priv->regs = dev_read_addr_ptr(dev); - ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl); -- if (ret) -+ if (ret) { -+ dev_err(dev, "failed to get pinctrl device %d\n", ret); - return ret; -+ } -+ -+ pctrl_priv = dev_get_priv(priv->pinctrl); -+ if (!pctrl_priv) { -+ dev_err(dev, "failed to get pinctrl priv\n"); -+ return -EINVAL; -+ } - -- uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK; - end = strrchr(dev->name, '@'); -- priv->bank = trailing_strtoln(dev->name, end); -- priv->name[0] = 'A' + priv->bank; -- uc_priv->bank_name = priv->name; -+ if (end) -+ id = trailing_strtoln(dev->name, end); -+ else -+ dev_read_alias_seq(dev, &id); -+ -+ if (id < 0) -+ id = gpio++; -+ -+ if (id >= pctrl_priv->ctrl->nr_banks) { -+ dev_err(dev, "bank id invalid\n"); -+ return -EINVAL; -+ } -+ -+ bank = &pctrl_priv->ctrl->pin_banks[id]; -+ if (bank->bank_num != id) { -+ dev_err(dev, "bank id mismatch with pinctrl\n"); -+ return -EINVAL; -+ } -+ -+ priv->bank = bank->bank_num; -+ uc_priv->gpio_count = bank->nr_pins; -+ uc_priv->gpio_base = bank->pin_base; -+ uc_priv->bank_name = bank->name; - - return 0; - } ---- a/drivers/pinctrl/rockchip/Makefile -+++ b/drivers/pinctrl/rockchip/Makefile -@@ -14,4 +14,5 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl - obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o - obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o - obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o -+obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o - obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o ---- /dev/null -+++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c -@@ -0,0 +1,360 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "pinctrl-rockchip.h" -+ -+static struct rockchip_mux_route_data rk3568_mux_route_data[] = { -+ MR_TOPGRF(RK_GPIO0, RK_PB3, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(0, 0, 0)), /* CAN0 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(0, 0, 1)), /* CAN0 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 0)), /* CAN1 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 1)), /* CAN1 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO4, RK_PB5, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(4, 4, 0)), /* CAN2 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO2, RK_PB2, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(4, 4, 1)), /* CAN2 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO4, RK_PC4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(6, 6, 0)), /* EDPDP_HPDIN IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO0, RK_PC2, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(6, 6, 1)), /* EDPDP_HPDIN IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PB1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 0)), /* GMAC1 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO4, RK_PA7, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 1)), /* GMAC1 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO4, RK_PD1, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 0)), /* HDMITX IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO0, RK_PC7, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 1)), /* HDMITX IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO0, RK_PB6, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 0)), /* I2C2 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO4, RK_PB4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 1)), /* I2C2 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO1, RK_PA0, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(0, 0, 0)), /* I2C3 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(0, 0, 1)), /* I2C3 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO4, RK_PB2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(2, 2, 0)), /* I2C4 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO2, RK_PB1, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(2, 2, 1)), /* I2C4 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PB4, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(4, 4, 0)), /* I2C5 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO4, RK_PD0, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(4, 4, 1)), /* I2C5 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 0)), /* PWM4 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 1)), /* PWM4 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 0)), /* PWM5 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 1)), /* PWM5 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 0)), /* PWM6 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 1)), /* PWM6 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 0)), /* PWM7 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 1)), /* PWM7 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(14, 14, 0)), /* SDMMC2 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(14, 14, 1)), /* SDMMC2 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO0, RK_PB5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(0, 0, 0)), /* SPI0 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO2, RK_PD3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(0, 0, 1)), /* SPI0 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO2, RK_PB5, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 0)), /* SPI1 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO3, RK_PC3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 1)), /* SPI1 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(4, 4, 0)), /* SPI2 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(4, 4, 1)), /* SPI2 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO4, RK_PB3, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(6, 6, 0)), /* SPI3 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(6, 6, 1)), /* SPI3 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO2, RK_PB4, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(8, 8, 0)), /* UART1 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(10, 10, 0)), /* UART2 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(10, 10, 1)), /* UART2 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(12, 12, 0)), /* UART3 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(12, 12, 1)), /* UART3 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(14, 14, 0)), /* UART4 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(14, 14, 1)), /* UART4 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO2, RK_PA2, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(0, 0, 0)), /* UART5 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO3, RK_PC2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(0, 0, 1)), /* UART5 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO2, RK_PA4, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 0)), /* UART6 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 1)), /* UART6 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(5, 4, 0)), /* UART7 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 1)), /* UART7 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */ -+ MR_TOPGRF(RK_GPIO2, RK_PC5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(6, 6, 0)), /* UART8 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(6, 6, 1)), /* UART8 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(9, 8, 0)), /* UART9 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 1)), /* UART9 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO4, RK_PA4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 2)), /* UART9 IO mux selection M2 */ -+ MR_TOPGRF(RK_GPIO1, RK_PA2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(11, 10, 0)), /* I2S1 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(11, 10, 1)), /* I2S1 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(11, 10, 2)), /* I2S1 IO mux selection M2 */ -+ MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(12, 12, 0)), /* I2S2 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO4, RK_PB6, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(12, 12, 1)), /* I2S2 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(14, 14, 0)), /* I2S3 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(14, 14, 1)), /* I2S3 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(0, 0, 0)), /* PDM IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(0, 0, 1)), /* PDM IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO0, RK_PA5, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(3, 2, 0)), /* PCIE20 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 1)), /* PCIE20 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO1, RK_PB0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 2)), /* PCIE20 IO mux selection M2 */ -+ MR_TOPGRF(RK_GPIO0, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO2, RK_PD2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO1, RK_PA5, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux selection M2 */ -+ MR_TOPGRF(RK_GPIO0, RK_PA6, RK_FUNC_2, 0x0314, RK_GENMASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux selection M0 */ -+ MR_TOPGRF(RK_GPIO2, RK_PD4, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux selection M1 */ -+ MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux selection M2 */ -+}; -+ -+static int rk3568_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) -+{ -+ struct rockchip_pinctrl_priv *priv = bank->priv; -+ int iomux_num = (pin / 8); -+ struct regmap *regmap; -+ int reg, ret, mask; -+ u8 bit; -+ u32 data; -+ -+ debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); -+ -+ if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) -+ regmap = priv->regmap_pmu; -+ else -+ regmap = priv->regmap_base; -+ -+ reg = bank->iomux[iomux_num].offset; -+ if ((pin % 8) >= 4) -+ reg += 0x4; -+ bit = (pin % 4) * 4; -+ mask = 0xf; -+ -+ data = (mask << (bit + 16)); -+ data |= (mux & mask) << bit; -+ ret = regmap_write(regmap, reg, data); -+ -+ return ret; -+} -+ -+#define RK3568_PULL_PMU_OFFSET 0x20 -+#define RK3568_PULL_GRF_OFFSET 0x80 -+#define RK3568_PULL_BITS_PER_PIN 2 -+#define RK3568_PULL_PINS_PER_REG 8 -+#define RK3568_PULL_BANK_STRIDE 0x10 -+ -+static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, -+ int pin_num, struct regmap **regmap, -+ int *reg, u8 *bit) -+{ -+ struct rockchip_pinctrl_priv *info = bank->priv; -+ -+ if (bank->bank_num == 0) { -+ *regmap = info->regmap_pmu; -+ *reg = RK3568_PULL_PMU_OFFSET; -+ *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE; -+ } else { -+ *regmap = info->regmap_base; -+ *reg = RK3568_PULL_GRF_OFFSET; -+ *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE; -+ } -+ -+ *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4); -+ *bit = (pin_num % RK3568_PULL_PINS_PER_REG); -+ *bit *= RK3568_PULL_BITS_PER_PIN; -+} -+ -+#define RK3568_DRV_PMU_OFFSET 0x70 -+#define RK3568_DRV_GRF_OFFSET 0x200 -+#define RK3568_DRV_BITS_PER_PIN 8 -+#define RK3568_DRV_PINS_PER_REG 2 -+#define RK3568_DRV_BANK_STRIDE 0x40 -+ -+static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, -+ int pin_num, struct regmap **regmap, -+ int *reg, u8 *bit) -+{ -+ struct rockchip_pinctrl_priv *info = bank->priv; -+ -+ /* The first 32 pins of the first bank are located in PMU */ -+ if (bank->bank_num == 0) { -+ *regmap = info->regmap_pmu; -+ *reg = RK3568_DRV_PMU_OFFSET; -+ } else { -+ *regmap = info->regmap_base; -+ *reg = RK3568_DRV_GRF_OFFSET; -+ *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE; -+ } -+ -+ *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4); -+ *bit = (pin_num % RK3568_DRV_PINS_PER_REG); -+ *bit *= RK3568_DRV_BITS_PER_PIN; -+} -+ -+#define RK3568_SCHMITT_BITS_PER_PIN 2 -+#define RK3568_SCHMITT_PINS_PER_REG 8 -+#define RK3568_SCHMITT_BANK_STRIDE 0x10 -+#define RK3568_SCHMITT_GRF_OFFSET 0xc0 -+#define RK3568_SCHMITT_PMUGRF_OFFSET 0x30 -+ -+static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, -+ int pin_num, struct regmap **regmap, -+ int *reg, u8 *bit) -+{ -+ struct rockchip_pinctrl_priv *info = bank->priv; -+ -+ if (bank->bank_num == 0) { -+ *regmap = info->regmap_pmu; -+ *reg = RK3568_SCHMITT_PMUGRF_OFFSET; -+ } else { -+ *regmap = info->regmap_base; -+ *reg = RK3568_SCHMITT_GRF_OFFSET; -+ *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE; -+ } -+ -+ *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4); -+ *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG; -+ *bit *= RK3568_SCHMITT_BITS_PER_PIN; -+ -+ return 0; -+} -+ -+static int rk3568_set_pull(struct rockchip_pin_bank *bank, -+ int pin_num, int pull) -+{ -+ struct regmap *regmap; -+ int reg, ret; -+ u8 bit, type; -+ u32 data; -+ -+ if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) -+ return -ENOTSUPP; -+ -+ rk3568_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); -+ type = bank->pull_type[pin_num / 8]; -+ ret = rockchip_translate_pull_value(type, pull); -+ if (ret < 0) { -+ debug("unsupported pull setting %d\n", pull); -+ return ret; -+ } -+ -+ /* enable the write to the equivalent lower bits */ -+ data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); -+ -+ data |= (ret << bit); -+ ret = regmap_write(regmap, reg, data); -+ -+ return ret; -+} -+ -+static int rk3568_set_drive(struct rockchip_pin_bank *bank, -+ int pin_num, int strength) -+{ -+ struct regmap *regmap; -+ int reg; -+ u32 data; -+ u8 bit; -+ int drv = (1 << (strength + 1)) - 1; -+ int ret = 0; -+ -+ rk3568_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); -+ -+ /* enable the write to the equivalent lower bits */ -+ data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << (bit + 16); -+ data |= (drv << bit); -+ -+ ret = regmap_write(regmap, reg, data); -+ if (ret) -+ return ret; -+ -+ if (bank->bank_num == 1 && pin_num == 21) -+ reg = 0x0840; -+ else if (bank->bank_num == 2 && pin_num == 2) -+ reg = 0x0844; -+ else if (bank->bank_num == 2 && pin_num == 8) -+ reg = 0x0848; -+ else if (bank->bank_num == 3 && pin_num == 0) -+ reg = 0x084c; -+ else if (bank->bank_num == 3 && pin_num == 6) -+ reg = 0x0850; -+ else if (bank->bank_num == 4 && pin_num == 0) -+ reg = 0x0854; -+ else -+ return 0; -+ -+ data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << 16; -+ data |= drv; -+ -+ return regmap_write(regmap, reg, data); -+} -+ -+static int rk3568_set_schmitt(struct rockchip_pin_bank *bank, -+ int pin_num, int enable) -+{ -+ struct regmap *regmap; -+ int reg; -+ u32 data; -+ u8 bit; -+ -+ rk3568_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit); -+ -+ /* enable the write to the equivalent lower bits */ -+ data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16); -+ data |= (enable << bit); -+ -+ return regmap_write(regmap, reg, data); -+} -+static struct rockchip_pin_bank rk3568_pin_banks[] = { -+ PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, -+ IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, -+ IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT, -+ IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT), -+ PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT, -+ IOMUX_WIDTH_4BIT, -+ IOMUX_WIDTH_4BIT, -+ IOMUX_WIDTH_4BIT), -+ PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT, -+ IOMUX_WIDTH_4BIT, -+ IOMUX_WIDTH_4BIT, -+ IOMUX_WIDTH_4BIT), -+ PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT, -+ IOMUX_WIDTH_4BIT, -+ IOMUX_WIDTH_4BIT, -+ IOMUX_WIDTH_4BIT), -+ PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, -+ IOMUX_WIDTH_4BIT, -+ IOMUX_WIDTH_4BIT, -+ IOMUX_WIDTH_4BIT), -+}; -+ -+static const struct rockchip_pin_ctrl rk3568_pin_ctrl = { -+ .pin_banks = rk3568_pin_banks, -+ .nr_banks = ARRAY_SIZE(rk3568_pin_banks), -+ .nr_pins = 160, -+ .grf_mux_offset = 0x0, -+ .pmu_mux_offset = 0x0, -+ .iomux_routes = rk3568_mux_route_data, -+ .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data), -+ .set_mux = rk3568_set_mux, -+ .set_pull = rk3568_set_pull, -+ .set_drive = rk3568_set_drive, -+ .set_schmitt = rk3568_set_schmitt, -+}; -+ -+static const struct udevice_id rk3568_pinctrl_ids[] = { -+ { -+ .compatible = "rockchip,rk3568-pinctrl", -+ .data = (ulong)&rk3568_pin_ctrl -+ }, -+ { } -+}; -+ -+U_BOOT_DRIVER(pinctrl_rk3568) = { -+ .name = "rockchip_rk3568_pinctrl", -+ .id = UCLASS_PINCTRL, -+ .of_match = rk3568_pinctrl_ids, -+ .priv_auto = sizeof(struct rockchip_pinctrl_priv), -+ .ops = &rockchip_pinctrl_ops, -+#if !CONFIG_IS_ENABLED(OF_PLATDATA) -+ .bind = dm_scan_fdt_dev, -+#endif -+ .probe = rockchip_pinctrl_probe, -+}; ---- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c -+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c -@@ -400,7 +400,7 @@ static int rockchip_pinctrl_set_state(st - int prop_len, param; - const u32 *data; - ofnode node; --#ifdef CONFIG_OF_LIVE -+#if CONFIG_IS_ENABLED(OF_LIVE) - const struct device_node *np; - struct property *pp; - #else -@@ -440,7 +440,7 @@ static int rockchip_pinctrl_set_state(st - node = ofnode_get_by_phandle(conf); - if (!ofnode_valid(node)) - return -ENODEV; --#ifdef CONFIG_OF_LIVE -+#if CONFIG_IS_ENABLED(OF_LIVE) - np = ofnode_to_np(node); - for (pp = np->properties; pp; pp = pp->next) { - prop_name = pp->name; -@@ -515,13 +515,14 @@ static struct rockchip_pin_ctrl *rockchi - - /* preset iomux offset value, set new start value */ - if (iom->offset >= 0) { -- if (iom->type & IOMUX_SOURCE_PMU) -+ if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU)) - pmu_offs = iom->offset; - else - grf_offs = iom->offset; - } else { /* set current iomux offset */ -- iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? -- pmu_offs : grf_offs; -+ iom->offset = ((iom->type & IOMUX_SOURCE_PMU) || -+ (iom->type & IOMUX_L_SOURCE_PMU)) ? -+ pmu_offs : grf_offs; - } - - /* preset drv offset value, set new start value */ ---- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h -+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h -@@ -6,9 +6,13 @@ - #ifndef __DRIVERS_PINCTRL_ROCKCHIP_H - #define __DRIVERS_PINCTRL_ROCKCHIP_H - -+#include - #include - #include - -+#define RK_GENMASK_VAL(h, l, v) \ -+ (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l)))) -+ - /** - * Encode variants of iomux registers into a type variable - */ -@@ -18,6 +22,8 @@ - #define IOMUX_UNROUTED BIT(3) - #define IOMUX_WIDTH_3BIT BIT(4) - #define IOMUX_8WIDTH_2BIT BIT(5) -+#define IOMUX_WRITABLE_32BIT BIT(6) -+#define IOMUX_L_SOURCE_PMU BIT(7) - - /** - * Defined some common pins constants -@@ -63,6 +69,21 @@ enum rockchip_pin_pull_type { - }; - - /** -+ * enum mux route register type, should be invalid/default/topgrf/pmugrf. -+ * INVALID: means do not need to set mux route -+ * DEFAULT: means same regmap as pin iomux -+ * TOPGRF: means mux route setting in topgrf -+ * PMUGRF: means mux route setting in pmugrf -+ */ -+enum rockchip_pin_route_type { -+ ROUTE_TYPE_DEFAULT = 0, -+ ROUTE_TYPE_TOPGRF = 1, -+ ROUTE_TYPE_PMUGRF = 2, -+ -+ ROUTE_TYPE_INVALID = -1, -+}; -+ -+/** - * @drv_type: drive strength variant using rockchip_perpin_drv_type - * @offset: if initialized to -1 it will be autocalculated, by specifying - * an initial offset value the relevant source offset can be reset -@@ -220,6 +241,25 @@ struct rockchip_pin_bank { - .pull_type[3] = pull3, \ - } - -+#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ -+ { \ -+ .bank_num = ID, \ -+ .pin = PIN, \ -+ .func = FUNC, \ -+ .route_offset = REG, \ -+ .route_val = VAL, \ -+ .route_type = FLAG, \ -+ } -+ -+#define MR_DEFAULT(ID, PIN, FUNC, REG, VAL) \ -+ PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_DEFAULT) -+ -+#define MR_TOPGRF(ID, PIN, FUNC, REG, VAL) \ -+ PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_TOPGRF) -+ -+#define MR_PMUGRF(ID, PIN, FUNC, REG, VAL) \ -+ PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_PMUGRF) -+ - /** - * struct rockchip_mux_recalced_data: recalculate a pin iomux data. - * @num: bank number. -@@ -241,6 +281,7 @@ struct rockchip_mux_recalced_data { - * @bank_num: bank number. - * @pin: index at register or used to calc index. - * @func: the min pin. -+ * @route_type: the register type. - * @route_offset: the max pin. - * @route_val: the register offset. - */ -@@ -248,6 +289,7 @@ struct rockchip_mux_route_data { - u8 bank_num; - u8 pin; - u8 func; -+ enum rockchip_pin_route_type route_type : 8; - u32 route_offset; - u32 route_val; - }; diff --git a/5.4/package/boot/uboot-rockchip/patches/008-rockchip-allow-sdmmc-at-full-speed.patch b/5.4/package/boot/uboot-rockchip/patches/008-rockchip-allow-sdmmc-at-full-speed.patch deleted file mode 100644 index 3ad9d5b8..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/008-rockchip-allow-sdmmc-at-full-speed.patch +++ /dev/null @@ -1,22 +0,0 @@ -From 16cc17fc2cf2f308f5ac20b829d427114c6e59fa Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Mon, 20 Dec 2021 08:50:48 -0500 -Subject: [PATCH 08/11] rockchip: allow sdmmc at full speed - -Adding pinctrl and gpio support fixed quartz64-a sdmmc. - -Signed-off-by: Peter Geis ---- - arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi | 1 - - 1 file changed, 1 deletion(-) - ---- a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi -+++ b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi -@@ -13,7 +13,6 @@ - }; - - &sdmmc0 { -- max-frequency = <400000>; - bus-width = <4>; - u-boot,dm-spl; - u-boot,spl-fifo-mode; diff --git a/5.4/package/boot/uboot-rockchip/patches/009-rockchip-defconfig-add-gpio-v2-to-quartz64.patch b/5.4/package/boot/uboot-rockchip/patches/009-rockchip-defconfig-add-gpio-v2-to-quartz64.patch deleted file mode 100644 index c0ca879b..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/009-rockchip-defconfig-add-gpio-v2-to-quartz64.patch +++ /dev/null @@ -1,25 +0,0 @@ -From d3b3e9c1045e9fa0aff987a036b30cf380809e35 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Mon, 20 Dec 2021 10:11:52 -0500 -Subject: [PATCH 09/11] rockchip: defconfig: add gpio-v2 to quartz64 - -Signed-off-by: Peter Geis ---- - configs/quartz64-a-rk3566_defconfig | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/configs/quartz64-a-rk3566_defconfig -+++ b/configs/quartz64-a-rk3566_defconfig -@@ -42,10 +42,12 @@ CONFIG_CMD_REGULATOR=y - CONFIG_SPL_OF_CONTROL=y - CONFIG_OF_LIVE=y - CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_SPL_DM_WARN=y - CONFIG_SPL_REGMAP=y - CONFIG_SPL_SYSCON=y - CONFIG_SPL_CLK=y - CONFIG_ROCKCHIP_GPIO=y -+CONFIG_ROCKCHIP_GPIO_V2=y - CONFIG_SYS_I2C_ROCKCHIP=y - CONFIG_MISC=y - CONFIG_MMC_HS200_SUPPORT=y diff --git a/5.4/package/boot/uboot-rockchip/patches/010-rockchip-rk356x-enable-usb2-support-on-quartz64-a.patch b/5.4/package/boot/uboot-rockchip/patches/010-rockchip-rk356x-enable-usb2-support-on-quartz64-a.patch deleted file mode 100644 index a70c45a8..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/010-rockchip-rk356x-enable-usb2-support-on-quartz64-a.patch +++ /dev/null @@ -1,97 +0,0 @@ -From 981df845d960a9078893dad88e1dd82dfcb4a148 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Wed, 22 Dec 2021 19:40:32 -0500 -Subject: [PATCH 10/11] rockchip: rk356x: enable usb2 support on quartz64-a - -Signed-off-by: Peter Geis ---- - arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi | 22 ++++++++++++++++++++++ - configs/quartz64-a-rk3566_defconfig | 17 +++++++++++++++++ - include/configs/quartz64-a-rk3566.h | 3 +++ - 3 files changed, 42 insertions(+) - ---- a/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi -+++ b/arch/arm/dts/rk3566-quartz64-a-u-boot.dtsi -@@ -12,12 +12,34 @@ - }; - }; - -+&gmac1 { -+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; -+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; -+ status = "disabled"; -+}; -+ - &sdmmc0 { - bus-width = <4>; - u-boot,dm-spl; - u-boot,spl-fifo-mode; - }; - -+&usb_host0_ehci { -+ vbus-supply = <&vcc5v0_usb20_host>; -+}; -+ -+&usb_host0_ohci { -+ vbus-supply = <&vcc5v0_usb20_host>; -+}; -+ -+&usb_host1_ehci { -+ vbus-supply = <&vcc5v0_usb20_host>; -+}; -+ -+&usb_host1_ohci { -+ vbus-supply = <&vcc5v0_usb20_host>; -+}; -+ - &uart2 { - clock-frequency = <24000000>; - u-boot,dm-spl; ---- a/configs/quartz64-a-rk3566_defconfig -+++ b/configs/quartz64-a-rk3566_defconfig -@@ -22,6 +22,7 @@ CONFIG_FIT=y - CONFIG_FIT_VERBOSE=y - CONFIG_SPL_LOAD_FIT=y - CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-quartz64-a.dtb" -+# CONFIG_SYS_DEVICE_NULLDEV is not set - # CONFIG_DISPLAY_CPUINFO is not set - CONFIG_DISPLAY_BOARDINFO_LATE=y - # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -@@ -35,6 +36,7 @@ CONFIG_CMD_GPIO=y - CONFIG_CMD_GPT=y - CONFIG_CMD_I2C=y - CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y - # CONFIG_CMD_SETEXPR is not set - CONFIG_CMD_PMIC=y - CONFIG_CMD_REGULATOR=y -@@ -76,4 +78,19 @@ CONFIG_BAUDRATE=1500000 - CONFIG_DEBUG_UART_SHIFT=2 - CONFIG_SYSRESET=y - CONFIG_SYSRESET_PSCI=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GENERIC=y -+CONFIG_ROCKCHIP_USB2_PHY=y -+CONFIG_USB_KEYBOARD=y -+CONFIG_USB_HOST_ETHER=y -+CONFIG_USB_ETHER_LAN75XX=y -+CONFIG_USB_ETHER_LAN78XX=y -+CONFIG_USB_ETHER_SMSC95XX=y - CONFIG_ERRNO_STR=y ---- a/include/configs/quartz64-a-rk3566.h -+++ b/include/configs/quartz64-a-rk3566.h -@@ -11,4 +11,7 @@ - "stdout=serial,vidconsole\0" \ - "stderr=serial,vidconsole\0" - -+#define CONFIG_USB_OHCI_NEW -+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -+ - #endif diff --git a/5.4/package/boot/uboot-rockchip/patches/011-rockchip-rk356x-attempt-to-fix-ram-detection.patch b/5.4/package/boot/uboot-rockchip/patches/011-rockchip-rk356x-attempt-to-fix-ram-detection.patch deleted file mode 100644 index 736de6b2..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/011-rockchip-rk356x-attempt-to-fix-ram-detection.patch +++ /dev/null @@ -1,173 +0,0 @@ -From ea6da572fe3cee637319f1e7e588c059622c815e Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Wed, 22 Dec 2021 19:52:38 -0500 -Subject: [PATCH 11/11] rockchip: rk356x: attempt to fix ram detection - -Signed-off-by: Peter Geis ---- - arch/arm/mach-rockchip/rk3568/rk3568.c | 29 ++++++++++++++++++++++++ - arch/arm/mach-rockchip/sdram.c | 31 ++++++++++++++------------ - common/board_f.c | 7 ++++++ - configs/quartz64-a-rk3566_defconfig | 1 + - include/configs/rk3568_common.h | 5 +++++ - 5 files changed, 59 insertions(+), 14 deletions(-) - ---- a/arch/arm/mach-rockchip/rk3568/rk3568.c -+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c -@@ -5,6 +5,7 @@ - - #include - #include -+#include - #include - #include - #include -@@ -135,3 +136,31 @@ int arch_cpu_init(void) - #endif - return 0; - } -+ -+#ifdef CONFIG_OF_SYSTEM_SETUP -+int ft_system_setup(void *blob, struct bd_info *bd) -+{ -+ int ret; -+ int areas = 1; -+ u64 start[2], size[2]; -+ -+ /* Reserve the io address space. */ -+ if (gd->ram_top > SDRAM_UPPER_ADDR_MIN) { -+ start[0] = gd->bd->bi_dram[0].start; -+ size[0] = SDRAM_LOWER_ADDR_MAX - gd->bd->bi_dram[0].start; -+ -+ /* Add the upper 4GB address space */ -+ start[1] = SDRAM_UPPER_ADDR_MIN; -+ size[1] = gd->ram_top - SDRAM_UPPER_ADDR_MIN; -+ areas = 2; -+ -+ ret = fdt_set_usable_memory(blob, start, size, areas); -+ if (ret) { -+ printf("Cannot set usable memory\n"); -+ return ret; -+ } -+ } -+ -+ return 0; -+}; -+#endif ---- a/arch/arm/mach-rockchip/sdram.c -+++ b/arch/arm/mach-rockchip/sdram.c -@@ -3,6 +3,8 @@ - * Copyright (C) 2017 Rockchip Electronics Co., Ltd. - */ - -+#define DEBUG -+ - #include - #include - #include -@@ -98,8 +100,7 @@ size_t rockchip_sdram_size(phys_addr_t r - SYS_REG_COL_MASK); - cs1_col = cs0_col; - bk = 3 - ((sys_reg2 >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); -- if ((sys_reg3 >> SYS_REG_VERSION_SHIFT & -- SYS_REG_VERSION_MASK) == 0x2) { -+ if ((sys_reg3 >> SYS_REG_VERSION_SHIFT & SYS_REG_VERSION_MASK) >= 0x2) { - cs1_col = 9 + (sys_reg3 >> SYS_REG_CS1_COL_SHIFT(ch) & - SYS_REG_CS1_COL_MASK); - if (((sys_reg3 >> SYS_REG_EXTEND_CS0_ROW_SHIFT(ch) & -@@ -136,7 +137,7 @@ size_t rockchip_sdram_size(phys_addr_t r - SYS_REG_BW_MASK)); - row_3_4 = sys_reg2 >> SYS_REG_ROW_3_4_SHIFT(ch) & - SYS_REG_ROW_3_4_MASK; -- if (dram_type == DDR4) { -+ if ((dram_type == DDR4) && (sys_reg3 >> SYS_REG_VERSION_SHIFT & SYS_REG_VERSION_MASK) != 0x3){ - dbw = (sys_reg2 >> SYS_REG_DBW_SHIFT(ch)) & - SYS_REG_DBW_MASK; - bg = (dbw == 2) ? 2 : 1; -@@ -150,15 +151,11 @@ size_t rockchip_sdram_size(phys_addr_t r - chipsize_mb = chipsize_mb * 3 / 4; - size_mb += chipsize_mb; - if (rank > 1) -- debug("rank %d cs0_col %d cs1_col %d bk %d cs0_row %d\ -- cs1_row %d bw %d row_3_4 %d\n", -- rank, cs0_col, cs1_col, bk, cs0_row, -- cs1_row, bw, row_3_4); -+ debug("rank=%d cs0_col=%d cs1_col=%d bk=%d cs0_row=%d cs1_row=%d bg=%d bw=%d row_3_4=%d\n", -+ rank, cs0_col, cs1_col, bk, cs0_row, cs1_row, bg, bw, row_3_4); - else -- debug("rank %d cs0_col %d bk %d cs0_row %d\ -- bw %d row_3_4 %d\n", -- rank, cs0_col, bk, cs0_row, -- bw, row_3_4); -+ debug("rank %d cs0_col %d bk %d cs0_row %d bw %d row_3_4 %d\n", -+ rank, cs0_col, bk, cs0_row, bw, row_3_4); - } - - /* -@@ -176,9 +173,11 @@ size_t rockchip_sdram_size(phys_addr_t r - * 2. update board_get_usable_ram_top() and dram_init_banksize() - * to reserve memory for peripheral space after previous update. - */ -+ -+#ifndef __aarch64__ - if (size_mb > (SDRAM_MAX_SIZE >> 20)) - size_mb = (SDRAM_MAX_SIZE >> 20); -- -+#endif - return (size_t)size_mb << 20; - } - -@@ -208,6 +207,10 @@ int dram_init(void) - ulong board_get_usable_ram_top(ulong total_size) - { - unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE; -- -- return (gd->ram_top > top) ? top : gd->ram_top; -+#ifdef SDRAM_UPPER_ADDR_MIN -+ if (gd->ram_top > SDRAM_UPPER_ADDR_MIN) -+ return gd->ram_top; -+ else -+#endif -+ return (gd->ram_top > top) ? top : gd->ram_top; - } ---- a/common/board_f.c -+++ b/common/board_f.c -@@ -345,7 +345,14 @@ static int setup_dest_addr(void) - #endif - gd->ram_top = gd->ram_base + get_effective_memsize(); - gd->ram_top = board_get_usable_ram_top(gd->mon_len); -+#ifdef SDRAM_LOWER_ADDR_MAX -+ if (gd->ram_top > SDRAM_LOWER_ADDR_MAX) -+ gd->relocaddr = SDRAM_LOWER_ADDR_MAX; -+ else -+ gd->relocaddr = gd->ram_top; -+#else - gd->relocaddr = gd->ram_top; -+#endif - debug("Ram top: %08lX\n", (ulong)gd->ram_top); - #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) - /* ---- a/configs/quartz64-a-rk3566_defconfig -+++ b/configs/quartz64-a-rk3566_defconfig -@@ -21,6 +21,7 @@ CONFIG_API=y - CONFIG_FIT=y - CONFIG_FIT_VERBOSE=y - CONFIG_SPL_LOAD_FIT=y -+CONFIG_OF_SYSTEM_SETUP=y - CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-quartz64-a.dtb" - # CONFIG_SYS_DEVICE_NULLDEV is not set - # CONFIG_DISPLAY_CPUINFO is not set ---- a/include/configs/rk3568_common.h -+++ b/include/configs/rk3568_common.h -@@ -24,6 +24,11 @@ - #define CONFIG_SYS_SDRAM_BASE 0 - #define SDRAM_MAX_SIZE 0xf0000000 - -+#ifdef CONFIG_OF_SYSTEM_SETUP -+#define SDRAM_LOWER_ADDR_MAX 0xf0000000 -+#define SDRAM_UPPER_ADDR_MIN 0x100000000 -+#endif -+ - #ifndef CONFIG_SPL_BUILD - #define ENV_MEM_LAYOUT_SETTINGS \ - "scriptaddr=0x00c00000\0" \ diff --git a/5.4/package/boot/uboot-rockchip/patches/012-resync-rk3566-device-tree-with-mainline.patch b/5.4/package/boot/uboot-rockchip/patches/012-resync-rk3566-device-tree-with-mainline.patch deleted file mode 100644 index 11c79135..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/012-resync-rk3566-device-tree-with-mainline.patch +++ /dev/null @@ -1,1060 +0,0 @@ -From 07cb5e592c2fe682d7f176282a16f389c94f46c8 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Tue, 18 Jan 2022 19:20:40 -0500 -Subject: [PATCH 12/13] resync rk3566 device tree with mainline - -Signed-off-by: Peter Geis ---- - arch/arm/dts/rk3566-quartz64-a.dts | 285 ++++++++++++++++++++--- - arch/arm/dts/rk3566.dtsi | 8 +- - arch/arm/dts/rk3568.dtsi | 29 ++- - arch/arm/dts/rk356x.dtsi | 297 ++++++++++++------------ - include/dt-bindings/soc/rockchip,vop2.h | 14 ++ - 5 files changed, 442 insertions(+), 191 deletions(-) - create mode 100644 include/dt-bindings/soc/rockchip,vop2.h - ---- a/arch/arm/dts/rk3566-quartz64-a.dts -+++ b/arch/arm/dts/rk3566-quartz64-a.dts -@@ -4,6 +4,7 @@ - - #include - #include -+#include - #include "rk3566.dtsi" - - / { -@@ -55,6 +56,17 @@ - #cooling-cells = <2>; - }; - -+ hdmi-con { -+ compatible = "hdmi-connector"; -+ type = "c"; -+ -+ port { -+ hdmi_con_in: endpoint { -+ remote-endpoint = <&hdmi_out_con>; -+ }; -+ }; -+ }; -+ - leds { - compatible = "gpio-leds"; - -@@ -196,7 +208,7 @@ - enable-active-high; - gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; -- pinctrl-0 = <&vcc5v0_usb20_host_en_h>; -+ pinctrl-0 = <&vcc5v0_usb20_host_en>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_usb>; -@@ -248,6 +260,29 @@ - vin-supply = <&vbus>; - }; - -+ vcc_sys_ebc: vcc_sys_ebc { -+ compatible = "regulator-fixed"; -+ gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc_sys_ebc_h>; -+ regulator-boot-on; -+ regulator-name = "vcc_sys_ebc"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc_sys>; -+ }; -+ -+ vcc_lcd_en: vcc_lcd_en { -+ compatible = "regulator-fixed"; -+// gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; -+ regulator-always-on; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc_lcd_en_h>; -+ regulator-name = "vcc_lcd_en"; -+ vin-supply = <&vcc_sys>; -+ }; -+ - /* sourced from vcc_sys, sdio module operates internally at 3.3v */ - vcc_wl: vcc_wl { - compatible = "regulator-fixed"; -@@ -258,14 +293,21 @@ - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_sys>; - }; -+ -+ backlight: backlight { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm14 0 1000000 0>; -+ brightness-levels = <0 4 8 16 32 64 128 255>; -+ default-brightness-level = <6>; -+ }; - }; - --&combphy1_usq { -+&combphy1 { - status = "okay"; - rockchip,enable-ssc; - }; - --&combphy2_psq { -+&combphy2 { - status = "okay"; - }; - -@@ -302,6 +344,39 @@ - }; - }; - -+&ebc { -+ panel,width = <1872>; -+ panel,height = <1404>; -+ panel,vir_width = <1872>; -+ panel,vir_height = <1404>; -+ panel,sdck = <33300000>; -+ panel,lsl = <11>; -+ panel,lbl = <8>; -+ panel,ldl = <234>; -+ panel,lel = <23>; -+ panel,gdck-sta = <10>; -+ panel,lgonl = <215>; -+ panel,fsl = <1>; -+ panel,fbl = <4>; -+ panel,fdl = <1404>; -+ panel,fel = <12>; -+ panel,mirror = <1>; -+ panel,panel_16bit = <1>; -+ panel,panel_color = <0>; -+ panel,width-mm = <157>; -+ panel,height-mm = <210>; -+ -+ io-channels = <&ebc_pmic 0>; -+ panel-supply = <&v3p3>; -+ vcom-supply = <&vcom>; -+ vdrive-supply = <&vdrive>; -+ status = "okay"; -+}; -+ -+&eink { -+ status = "okay"; -+}; -+ - &gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; -@@ -325,19 +400,28 @@ - status = "okay"; - }; - --&hdmi { -+&gpu { -+ mali-supply = <&vdd_gpu>; - status = "okay"; -+}; -+ -+&hdmi { - avdd-0v9-supply = <&vdda_0v9>; - avdd-1v8-supply = <&vcc_1v8>; -+ status = "okay"; - }; - --&hdmi_in_vp0 { -- status = "okay"; -+&hdmi_in { -+ hdmi_in_vp0: endpoint@0 { -+ reg = <0>; -+ remote-endpoint = <&vp0_out_hdmi>; -+ }; - }; - --&gpu { -- mali-supply = <&vdd_gpu>; -- status = "okay"; -+&hdmi_out { -+ hdmi_out_con: endpoint { -+ remote-endpoint = <&hdmi_con_in>; -+ }; - }; - - &i2c0 { -@@ -357,6 +441,7 @@ - - regulator-state-mem { - regulator-off-in-suspend; -+ regulator-suspend-microvolt = <900000>; - }; - }; - -@@ -420,8 +505,6 @@ - vcc_ddr: DCDC_REG3 { - regulator-always-on; - regulator-boot-on; -- regulator-min-microvolt = <1100000>; -- regulator-max-microvolt = <1100000>; - regulator-initial-mode = <0x2>; - regulator-name = "vcc_ddr"; - regulator-state-mem { -@@ -571,6 +654,55 @@ - }; - }; - -+&i2c1 { -+ status = "okay"; -+ -+ ebc_pmic: pmic@68 { -+ compatible = "ti,tps65185"; -+ reg = <0x68>; -+ interrupt-parent = <&gpio4>; -+ interrupts = ; -+ #io-channel-cells = <1>; -+ pinctrl-0 = <&ebc_pmic_pins>; -+ pinctrl-names = "default"; -+ powerup-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; -+ pwr_good-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; -+ vcom_ctrl-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; -+ vin-supply = <&vcc_sys_ebc>; -+ vin3p3-supply = <&vcc_sys_ebc>; -+ wakeup-gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>; -+ ti,up-sequence = <1>, <0>, <2>, <3>; -+ ti,up-delay-ms = <3>, <3>, <3>, <3>; -+ ti,down-sequence = <2>, <3>, <1>, <0>; -+ ti,down-delay-ms = <3>, <6>, <6>, <6>; -+ -+ regulators { -+ v3p3: v3p3 { -+ regulator-name = "v3p3"; -+ regulator-always-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ vcom: vcom { -+ regulator-name = "vcom"; -+ regulator-min-microvolt = <1450000>; -+ regulator-max-microvolt = <1450000>; -+ }; -+ -+ vdrive: vdrive { -+ regulator-name = "vdrive"; -+ regulator-min-microvolt = <15000000>; -+ regulator-max-microvolt = <15000000>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c3 { -+ status = "okay"; -+}; -+ - &i2s1_8ch { - pinctrl-names = "default"; - pinctrl-0 = <&i2s1m0_sclktx -@@ -611,6 +743,21 @@ - }; - }; - -+ ebc_pmic { -+ ebc_pmic_pins: ebc-pmic-pins { -+ rockchip,pins = /* wakeup */ -+ <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>, -+ /* int */ -+ <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, -+ /* pwr_good */ -+ <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>, -+ /* pwrup */ -+ <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, -+ /* vcom_ctrl */ -+ <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ - fan { - fan_en_h: fan-en-h { - rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; -@@ -654,7 +801,7 @@ - }; - - usb2 { -- vcc5v0_usb20_host_en_h: vcc5v0-usb20-host-en_h { -+ vcc5v0_usb20_host_en: vcc5v0-usb20-host-en { - rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -@@ -664,6 +811,18 @@ - rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -+ -+ vcc_sys_ebc { -+ vcc_sys_ebc_h: vcc-sys-ebc-h { -+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ vcc_lcd_en { -+ vcc_lcd_en_h: vcc-lcd-en-h { -+ rockchip,pins = <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; - }; - - &pmu_io_domains { -@@ -681,12 +840,15 @@ - - /* sata1 is muxed with the usb3 port */ - &sata1 { -- status = "okay"; -+ status = "disabled"; -+// status = "okay"; - }; - - /* sata2 is muxed with the pcie2 slot*/ - &sata2 { -+ target-supply = <&vcc3v3_pcie_p>; - status = "disabled"; -+// status = "okay"; - }; - - &sdhci { -@@ -783,6 +945,10 @@ - status = "okay"; - }; - -+&u2phy0 { -+ status = "okay"; -+}; -+ - &u2phy0_host { - phy-supply = <&vcc5v0_usb20_host>; - status = "okay"; -@@ -793,25 +959,17 @@ - status = "okay"; - }; - --&u2phy1_host { -- phy-supply = <&vcc5v0_usb20_host>; -+&u2phy1 { - status = "okay"; - }; - --&u2phy1_otg { -+&u2phy1_host { - phy-supply = <&vcc5v0_usb20_host>; - status = "okay"; - }; - --&usb2phy0 { -- status = "okay"; --}; -- --&usb2phy1 { -- status = "okay"; --}; -- --&usbdrd_dwc3 { -+&u2phy1_otg { -+ phy-supply = <&vcc5v0_usb20_host>; - status = "okay"; - }; - -@@ -820,13 +978,9 @@ - }; - - /* usb3 controller is muxed with sata1 */ --&usbhost_dwc3 { -- status = "disabled"; --}; -- --/* usb3 controller is muxed with sata1 */ - &usbhost30 { -- status = "disabled"; -+// status = "disabled"; -+ status = "okay"; - }; - - &usb_host0_ehci { -@@ -846,15 +1000,80 @@ - }; - - &vop { -- status = "okay"; - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; - assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; -+ status = "okay"; - }; - - &vop_mmu { - status = "okay"; - }; - --&vp0_out_hdmi { -+&vp0 { -+ vp0_out_hdmi: endpoint@RK3568_VOP2_EP_HDMI { -+ reg = ; -+ remote-endpoint = <&hdmi_in_vp0>; -+ }; -+}; -+/* -+&video_phy0 { -+ status = "okay"; -+}; -+ -+&dsi0 { -+ status = "okay"; -+ clock-master; -+ -+ mipi_panel: panel@0 { -+ compatible = "feiyang,fy07024di26a30d"; -+ reg = <0>; -+ backlight = <&backlight>; -+ reset-gpios = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; -+ width-mm = <154>; -+ height-mm = <86>; -+ rotation = <0>; -+// avdd-supply = <&avdd>; -+// dvdd-supply = <&vcc3v3_s0>; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ -+ mipi_in_panel: endpoint { -+ remote-endpoint = <&mipi_out_panel>; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&dsi0_in { -+ dsi0_in_vp1: endpoint@1 { -+ reg = <1>; -+ remote-endpoint = <&vp1_out_dsi0>; -+ }; -+}; -+ -+&dsi0_out { -+ mipi_out_panel: endpoint { -+ remote-endpoint = <&mipi_in_panel>; -+ }; -+ -+}; -+ -+&vp1 { -+ vp1_out_dsi0: endpoint@RK3568_VOP2_EP_MIPI0 { -+ reg = ; -+ remote-endpoint = <&dsi0_in_vp1>; -+ }; -+}; -+ -+&pwm14 { - status = "okay"; -+ pinctrl-0 = <&pwm14m1_pins>; -+ pinctrl-names = "default"; - }; -+*/ ---- a/arch/arm/dts/rk3566.dtsi -+++ b/arch/arm/dts/rk3566.dtsi -@@ -23,10 +23,14 @@ - }; - }; - --&usbdrd_dwc3 { -+&usbdrd30 { - phys = <&u2phy0_otg>; - phy-names = "usb2-phy"; -- extcon = <&usb2phy0>; -+ extcon = <&u2phy0>; - maximum-speed = "high-speed"; - snps,dis_u2_susphy_quirk; - }; -+ -+&vop { -+ compatible = "rockchip,rk3566-vop"; -+}; ---- a/arch/arm/dts/rk3568.dtsi -+++ b/arch/arm/dts/rk3568.dtsi -@@ -16,13 +16,18 @@ - clock-names = "sata", "pmalive", "rxoob"; - interrupts = ; - interrupt-names = "hostc"; -- phys = <&combphy0_us PHY_TYPE_SATA>; -+ phys = <&combphy0 PHY_TYPE_SATA>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; - power-domains = <&power RK3568_PD_PIPE>; - status = "disabled"; - }; - -+ pipe_phy_grf0: syscon@fdc70000 { -+ compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; -+ reg = <0x0 0xfdc70000 0x0 0x1000>; -+ }; -+ - qos_pcie3x1: qos@fe190080 { - compatible = "rockchip,rk3568-qos", "syscon"; - reg = <0x0 0xfe190080 0x0 0x20>; -@@ -87,19 +92,19 @@ - }; - }; - -- combphy0_us: phy@fe820000 { -+ combphy0: phy@fe820000 { - compatible = "rockchip,rk3568-naneng-combphy"; - reg = <0x0 0xfe820000 0x0 0x100>; -- #phy-cells = <1>; -- assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; -- assigned-clock-rates = <100000000>; -- clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>, -+ clocks = <&pmucru CLK_PCIEPHY0_REF>, -+ <&cru PCLK_PIPEPHY0>, - <&cru PCLK_PIPE>; - clock-names = "ref", "apb", "pipe"; -- resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; -- reset-names = "combphy-apb", "combphy"; -+ assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; -+ assigned-clock-rates = <100000000>; -+ resets = <&cru SRST_PIPEPHY0>; - rockchip,pipe-grf = <&pipegrf>; - rockchip,pipe-phy-grf = <&pipe_phy_grf0>; -+ #phy-cells = <1>; - status = "disabled"; - }; - }; -@@ -131,7 +136,11 @@ - }; - }; - --&usbdrd_dwc3 { -- phys = <&u2phy0_otg>, <&combphy0_us PHY_TYPE_USB3>; -+&usbdrd30 { -+ phys = <&u2phy0_otg>, <&combphy0 PHY_TYPE_USB3>; - phy-names = "usb2-phy", "usb3-phy"; - }; -+ -+&vop { -+ compatible = "rockchip,rk3568-vop"; -+}; ---- a/arch/arm/dts/rk356x.dtsi -+++ b/arch/arm/dts/rk356x.dtsi -@@ -159,6 +159,11 @@ - }; - }; - -+ display_subsystem: display-subsystem { -+ compatible = "rockchip,display-subsystem"; -+ ports = <&vop_out>; -+ }; -+ - firmware { - scmi: scmi { - compatible = "arm,scmi-smc"; -@@ -234,7 +239,7 @@ - clock-names = "sata", "pmalive", "rxoob"; - interrupts = ; - interrupt-names = "hostc"; -- phys = <&combphy1_usq PHY_TYPE_SATA>; -+ phys = <&combphy1 PHY_TYPE_SATA>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; - power-domains = <&power RK3568_PD_PIPE>; -@@ -249,7 +254,7 @@ - clock-names = "sata", "pmalive", "rxoob"; - interrupts = ; - interrupt-names = "hostc"; -- phys = <&combphy2_psq PHY_TYPE_SATA>; -+ phys = <&combphy2 PHY_TYPE_SATA>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; - power-domains = <&power RK3568_PD_PIPE>; -@@ -258,66 +263,46 @@ - - usbdrd30: usbdrd { - compatible = "rockchip,rk3399-dwc3", "snps,dwc3"; -+ reg = <0x0 0xfcc00000 0x0 0x400000>; -+ interrupts = ; - clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, - <&cru ACLK_USB3OTG0>, <&cru PCLK_PIPE>; - clock-names = "ref_clk", "suspend_clk", - "bus_clk", "pipe_clk"; -- #address-cells = <2>; -- #size-cells = <2>; -- ranges; -+ dr_mode = "host"; -+ phy_type = "utmi_wide"; -+ power-domains = <&power RK3568_PD_PIPE>; -+ resets = <&cru SRST_USB3OTG0>; -+ reset-names = "usb3-otg"; -+ snps,dis_enblslpm_quirk; -+ snps,dis-u2-freeclk-exists-quirk; -+ snps,dis-del-phy-power-chg-quirk; -+ snps,dis-tx-ipgap-linecheck-quirk; -+ snps,xhci-trb-ent-quirk; - status = "disabled"; -- -- usbdrd_dwc3: dwc3@fcc00000 { -- compatible = "snps,dwc3"; -- reg = <0x0 0xfcc00000 0x0 0x400000>; -- interrupts = ; -- dr_mode = "host"; -- phys = <&u2phy0_otg>, <&combphy0_us PHY_TYPE_USB3>; -- phy-names = "usb2-phy", "usb3-phy"; -- phy_type = "utmi_wide"; -- power-domains = <&power RK3568_PD_PIPE>; -- resets = <&cru SRST_USB3OTG0>; -- reset-names = "usb3-otg"; -- snps,dis_enblslpm_quirk; -- snps,dis-u2-freeclk-exists-quirk; -- snps,dis-del-phy-power-chg-quirk; -- snps,dis-tx-ipgap-linecheck-quirk; -- snps,xhci-trb-ent-quirk; -- status = "disabled"; -- }; - }; - - usbhost30: usbhost { - compatible = "rockchip,rk3399-dwc3", "snps,dwc3"; -+ reg = <0x0 0xfd000000 0x0 0x400000>; -+ interrupts = ; - clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, - <&cru ACLK_USB3OTG1>, <&cru PCLK_PIPE>; - clock-names = "ref_clk", "suspend_clk", - "bus_clk", "pipe_clk"; -- #address-cells = <2>; -- #size-cells = <2>; -- assigned-clocks = <&cru CLK_PCIEPHY1_REF>; -- assigned-clock-rates = <25000000>; -- ranges; -- status = "disabled"; -- -- usbhost_dwc3: dwc3@fd000000 { -- compatible = "snps,dwc3"; -- reg = <0x0 0xfd000000 0x0 0x400000>; -- interrupts = ; -- dr_mode = "host"; -- phys = <&u2phy0_host>, <&combphy1_usq PHY_TYPE_USB3>; -- phy-names = "usb2-phy", "usb3-phy"; -- phy_type = "utmi_wide"; -- power-domains = <&power RK3568_PD_PIPE>; -- resets = <&cru SRST_USB3OTG1>; -- reset-names = "usb3-host"; -- snps,dis_enblslpm_quirk; -- snps,dis-u2-freeclk-exists-quirk; -- snps,dis_u2_susphy_quirk; -- snps,dis-del-phy-power-chg-quirk; -- snps,dis-tx-ipgap-linecheck-quirk; -- status = "disabled"; -- }; -+ dr_mode = "host"; -+ phys = <&u2phy0_host>, <&combphy1 PHY_TYPE_USB3>; -+ phy-names = "usb2-phy", "usb3-phy"; -+ phy_type = "utmi_wide"; -+ power-domains = <&power RK3568_PD_PIPE>; -+ resets = <&cru SRST_USB3OTG1>; -+ reset-names = "usb3-host"; -+ snps,dis_enblslpm_quirk; -+ snps,dis-u2-freeclk-exists-quirk; -+ snps,dis_u2_susphy_quirk; -+ snps,dis-del-phy-power-chg-quirk; -+ snps,dis-tx-ipgap-linecheck-quirk; -+ status = "disabled"; - }; - - gic: interrupt-controller@fd400000 { -@@ -339,7 +324,7 @@ - clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, - <&cru PCLK_USB>; - phys = <&u2phy1_otg>; -- phy-names = "usb2-phy"; -+ phy-names = "usb"; - status = "disabled"; - }; - -@@ -350,7 +335,7 @@ - clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, - <&cru PCLK_USB>; - phys = <&u2phy1_otg>; -- phy-names = "usb2-phy"; -+ phy-names = "usb"; - status = "disabled"; - }; - -@@ -361,7 +346,7 @@ - clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, - <&cru PCLK_USB>; - phys = <&u2phy1_host>; -- phy-names = "usb2-phy"; -+ phy-names = "usb"; - status = "disabled"; - }; - -@@ -372,7 +357,7 @@ - clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, - <&cru PCLK_USB>; - phys = <&u2phy1_host>; -- phy-names = "usb2-phy"; -+ phy-names = "usb"; - status = "disabled"; - }; - -@@ -395,21 +380,17 @@ - reg = <0x0 0xfdc60000 0x0 0x10000>; - }; - -- pipe_phy_grf0: syscon@fdc70000 { -- compatible = "rockchip,pipe-phy-grf", "syscon"; -- reg = <0x0 0xfdc70000 0x0 0x1000>; -- }; -- - pipe_phy_grf1: syscon@fdc80000 { -- compatible = "rockchip,pipe-phy-grf", "syscon"; -+ compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; - reg = <0x0 0xfdc80000 0x0 0x1000>; - }; - - pipe_phy_grf2: syscon@fdc90000 { -- compatible = "rockchip,pipe-phy-grf", "syscon"; -+ compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; - reg = <0x0 0xfdc90000 0x0 0x1000>; - }; - -+ - usb2phy0_grf: syscon@fdca0000 { - compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; - reg = <0x0 0xfdca0000 0x0 0x8000>; -@@ -604,6 +585,28 @@ - status = "disabled"; - }; - -+ ebc: ebc@fdec0000 { -+ compatible = "rockchip,rk3568-ebc-tcon"; -+ reg = <0x0 0xfdec0000 0x0 0x5000>; -+ interrupts = ; -+ clocks = <&cru HCLK_EBC>, <&cru DCLK_EBC>; -+ clock-names = "hclk", "dclk"; -+ pinctrl-0 = <&ebc_pins>; -+ pinctrl-names = "default"; -+ power-domains = <&power RK3568_PD_RGA>; -+ rockchip,grf = <&grf>; -+ status = "disabled"; -+ }; -+ -+ eink: eink@fdf00000 { -+ compatible = "rockchip,rk3568-eink-tcon"; -+ reg = <0x0 0xfdf00000 0x0 0x74>; -+ clocks = <&cru PCLK_EINK>, <&cru HCLK_EINK>; -+ clock-names = "pclk", "hclk"; -+ interrupts = ; -+ status = "disabled"; -+ }; -+ - sdmmc2: mmc@fe000000 { - compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x0 0xfe000000 0x0 0x4000>; -@@ -665,21 +668,15 @@ - }; - }; - -- display_subsystem: display-subsystem { -- compatible = "rockchip,display-subsystem"; -- ports = <&vop_out>; -- }; -- - vop: vop@fe040000 { -- compatible = "rockchip,rk3568-vop"; - reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; - reg-names = "regs", "gamma_lut"; -- rockchip,grf = <&grf>; - interrupts = ; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; - clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2"; - iommus = <&vop_mmu>; - power-domains = <&power RK3568_PD_VO>; -+ rockchip,grf = <&grf>; - status = "disabled"; - - vop_out: ports { -@@ -687,39 +684,21 @@ - #size-cells = <0>; - - vp0: port@0 { -+ reg = <0>; - #address-cells = <1>; - #size-cells = <0>; -- reg = <0>; -- -- vp0_out_hdmi: endpoint@0 { -- reg = <0>; -- remote-endpoint = <&hdmi_in_vp0>; -- status = "disabled"; -- }; - }; - - vp1: port@1 { -+ reg = <1>; - #address-cells = <1>; - #size-cells = <0>; -- reg = <1>; -- -- vp1_out_hdmi: endpoint@0 { -- reg = <0>; -- remote-endpoint = <&hdmi_in_vp1>; -- status = "disabled"; -- }; - }; - - vp2: port@2 { -+ reg = <2>; - #address-cells = <1>; - #size-cells = <0>; -- reg = <2>; -- -- vp2_out_hdmi: endpoint@0 { -- reg = <0>; -- remote-endpoint = <&hdmi_in_vp2>; -- status = "disabled"; -- }; - }; - }; - }; -@@ -728,7 +707,6 @@ - compatible = "rockchip,rk3568-iommu"; - reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>; - interrupts = ; -- interrupt-names = "vop_mmu"; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; -@@ -742,14 +720,15 @@ - clocks = <&cru PCLK_HDMI_HOST>, - <&cru CLK_HDMI_SFR>, - <&cru CLK_HDMI_CEC>, -+ <&pmucru CLK_HDMI_REF>, - <&cru HCLK_VOP>; -- clock-names = "iahb", "isfr", "cec", "hclk"; -+ clock-names = "iahb", "isfr", "cec", "ref", "hclk"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; - power-domains = <&power RK3568_PD_VO>; - reg-io-width = <4>; - rockchip,grf = <&grf>; - #sound-dai-cells = <0>; -- pinctrl-names = "default"; -- pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; - status = "disabled"; - - ports { -@@ -760,24 +739,12 @@ - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; -+ }; - -- hdmi_in_vp0: endpoint@0 { -- reg = <0>; -- remote-endpoint = <&vp0_out_hdmi>; -- status = "disabled"; -- }; -- -- hdmi_in_vp1: endpoint@1 { -- reg = <1>; -- remote-endpoint = <&vp1_out_hdmi>; -- status = "disabled"; -- }; -- -- hdmi_in_vp2: endpoint@2 { -- reg = <2>; -- remote-endpoint = <&vp2_out_hdmi>; -- status = "disabled"; -- }; -+ hdmi_out: port@1 { -+ reg = <1>; -+ #address-cells = <1>; -+ #size-cells = <0>; - }; - }; - }; -@@ -934,7 +901,7 @@ - max-link-speed = <2>; - msi-map = <0x0 &gic 0x0 0x1000>; - num-lanes = <1>; -- phys = <&combphy2_psq PHY_TYPE_PCIE>; -+ phys = <&combphy2 PHY_TYPE_PCIE>; - phy-names = "pcie-phy"; - power-domains = <&power RK3568_PD_PIPE>; - reg = <0x3 0xc0000000 0x0 0x400000>, -@@ -1048,6 +1015,43 @@ - status = "disabled"; - }; - -+ i2s2_2ch: i2s@fe420000 { -+ compatible = "rockchip,rk3568-i2s-tdm"; -+ reg = <0x0 0xfe420000 0x0 0x1000>; -+ interrupts = ; -+ clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; -+ clock-names = "mclk_tx", "mclk_rx", "hclk"; -+ dmas = <&dmac1 4>, <&dmac1 5>; -+ dma-names = "tx", "rx"; -+ rockchip,cru = <&cru>; -+ rockchip,grf = <&grf>; -+ pinctrl-0 = <&i2s2m0_sclktx -+ &i2s2m0_lrcktx -+ &i2s2m0_sdi -+ &i2s2m0_sdo>; -+ pinctrl-names = "default"; -+ #sound-dai-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ pdm: pdm@fe440000 { -+ compatible = "rockchip,rk3568-pdm", "rockchip,pdm"; -+ reg = <0x0 0xfe440000 0x0 0x1000>; -+ clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; -+ clock-names = "pdm_clk", "pdm_hclk"; -+ dmas = <&dmac1 9>; -+ dma-names = "rx"; -+ pinctrl-0 = <&pdmm0_clk -+ &pdmm0_clk1 -+ &pdmm0_sdi0 -+ &pdmm0_sdi1 -+ &pdmm0_sdi2 -+ &pdmm0_sdi3>; -+ pinctrl-names = "default"; -+ #sound-dai-cells = <0>; -+ status = "disabled"; -+ }; -+ - dmac0: dmac@fe530000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x0 0xfe530000 0x0 0x4000>; -@@ -1487,47 +1491,15 @@ - status = "disabled"; - }; - -- combphy1_usq: phy@fe830000 { -- compatible = "rockchip,rk3568-naneng-combphy"; -- reg = <0x0 0xfe830000 0x0 0x100>; -- #phy-cells = <1>; -- assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; -- assigned-clock-rates = <100000000>; -- clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>, -- <&cru PCLK_PIPE>; -- clock-names = "ref", "apb", "pipe"; -- resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>; -- reset-names = "combphy-apb", "combphy"; -- rockchip,pipe-grf = <&pipegrf>; -- rockchip,pipe-phy-grf = <&pipe_phy_grf1>; -- status = "disabled"; -- }; -- -- combphy2_psq: phy@fe840000 { -- compatible = "rockchip,rk3568-naneng-combphy"; -- reg = <0x0 0xfe840000 0x0 0x100>; -- #phy-cells = <1>; -- assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; -- assigned-clock-rates = <100000000>; -- clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>, -- <&cru PCLK_PIPE>; -- clock-names = "ref", "apb", "pipe"; -- resets = <&cru SRST_P_PIPEPHY2>, <&cru SRST_PIPEPHY2>; -- reset-names = "combphy-apb", "combphy"; -- rockchip,pipe-grf = <&pipegrf>; -- rockchip,pipe-phy-grf = <&pipe_phy_grf2>; -- status = "disabled"; -- }; -- -- usb2phy0: usb2-phy@fe8a0000 { -+ u2phy0: usb2phy@fe8a0000 { - compatible = "rockchip,rk3568-usb2phy"; - reg = <0x0 0xfe8a0000 0x0 0x10000>; - clocks = <&pmucru CLK_USBPHY0_REF>; - clock-names = "phyclk"; -- #clock-cells = <0>; -- clock-output-names = "usb480m_phy"; -+ clock-output-names = "clk_usbphy0_480m"; - interrupts = ; - rockchip,usbgrf = <&usb2phy0_grf>; -+ #clock-cells = <0>; - status = "disabled"; - - u2phy0_host: host-port { -@@ -1541,14 +1513,15 @@ - }; - }; - -- usb2phy1: usb2-phy@fe8b0000 { -+ u2phy1: usb2phy@fe8b0000 { - compatible = "rockchip,rk3568-usb2phy"; - reg = <0x0 0xfe8b0000 0x0 0x10000>; - clocks = <&pmucru CLK_USBPHY1_REF>; - clock-names = "phyclk"; -- #clock-cells = <0>; -+ clock-output-names = "clk_usbphy1_480m"; - interrupts = ; - rockchip,usbgrf = <&usb2phy1_grf>; -+ #clock-cells = <0>; - status = "disabled"; - - u2phy1_host: host-port { -@@ -1562,6 +1535,38 @@ - }; - }; - -+ combphy1: phy@fe830000 { -+ compatible = "rockchip,rk3568-naneng-combphy"; -+ reg = <0x0 0xfe830000 0x0 0x100>; -+ clocks = <&pmucru CLK_PCIEPHY1_REF>, -+ <&cru PCLK_PIPEPHY1>, -+ <&cru PCLK_PIPE>; -+ clock-names = "ref", "apb", "pipe"; -+ assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; -+ assigned-clock-rates = <100000000>; -+ resets = <&cru SRST_PIPEPHY1>; -+ rockchip,pipe-grf = <&pipegrf>; -+ rockchip,pipe-phy-grf = <&pipe_phy_grf1>; -+ #phy-cells = <1>; -+ status = "disabled"; -+ }; -+ -+ combphy2: phy@fe840000 { -+ compatible = "rockchip,rk3568-naneng-combphy"; -+ reg = <0x0 0xfe840000 0x0 0x100>; -+ clocks = <&pmucru CLK_PCIEPHY2_REF>, -+ <&cru PCLK_PIPEPHY2>, -+ <&cru PCLK_PIPE>; -+ clock-names = "ref", "apb", "pipe"; -+ assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; -+ assigned-clock-rates = <100000000>; -+ resets = <&cru SRST_PIPEPHY2>; -+ rockchip,pipe-grf = <&pipegrf>; -+ rockchip,pipe-phy-grf = <&pipe_phy_grf2>; -+ #phy-cells = <1>; -+ status = "disabled"; -+ }; -+ - pinctrl: pinctrl { - compatible = "rockchip,rk3568-pinctrl"; - rockchip,grf = <&grf>; ---- /dev/null -+++ b/include/dt-bindings/soc/rockchip,vop2.h -@@ -0,0 +1,14 @@ -+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ -+ -+#ifndef __DT_BINDINGS_ROCKCHIP_VOP2_H -+#define __DT_BINDINGS_ROCKCHIP_VOP2_H -+ -+#define RK3568_VOP2_EP_RGB 0 -+#define RK3568_VOP2_EP_HDMI 1 -+#define RK3568_VOP2_EP_EDP 2 -+#define RK3568_VOP2_EP_MIPI0 3 -+#define RK3568_VOP2_EP_LVDS0 4 -+#define RK3568_VOP2_EP_MIPI1 5 -+#define RK3568_VOP2_EP_LVDS1 6 -+ -+#endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */ diff --git a/5.4/package/boot/uboot-rockchip/patches/013-rockchip-rk356x-add-bpi-r2-pro-board.patch b/5.4/package/boot/uboot-rockchip/patches/013-rockchip-rk356x-add-bpi-r2-pro-board.patch deleted file mode 100644 index 0728caea..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/013-rockchip-rk356x-add-bpi-r2-pro-board.patch +++ /dev/null @@ -1,795 +0,0 @@ -From 89d609d74e4ef84e0e3d399d8763b268b60302fc Mon Sep 17 00:00:00 2001 -From: Marty Jones -Date: Sat, 28 May 2022 20:19:38 -0400 -Subject: [PATCH] rockchip: rk356x: add bpi r2 pro board - -Signed-off-by: Marty Jones ---- - arch/arm/dts/Makefile | 1 + - arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi | 47 ++ - arch/arm/dts/rk3568-bpi-r2-pro.dts | 532 ++++++++++++++++++ - arch/arm/mach-rockchip/rk3568/Kconfig | 6 + - board/rockchip/bpi-r2-pro-rk3568/Kconfig | 15 + - board/rockchip/bpi-r2-pro-rk3568/Makefile | 7 + - .../bpi-r2-pro-rk3568/bpi-r2-pro-rk3568.c | 4 + - configs/bpi-r2-pro-rk3568_defconfig | 97 ++++ - include/configs/bpi-r2-pro-rk3568.h | 15 + - 9 files changed, 724 insertions(+) - create mode 100644 arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi - create mode 100644 arch/arm/dts/rk3568-bpi-r2-pro.dts - create mode 100644 board/rockchip/bpi-r2-pro-rk3568/Kconfig - create mode 100644 board/rockchip/bpi-r2-pro-rk3568/Makefile - create mode 100644 board/rockchip/bpi-r2-pro-rk3568/bpi-r2-pro-rk3568.c - create mode 100644 configs/bpi-r2-pro-rk3568_defconfig - create mode 100644 include/configs/bpi-r2-pro-rk3568.h - ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -164,6 +164,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ - rk3399pro-rock-pi-n10.dtb - - dtb-$(CONFIG_ROCKCHIP_RK3568) += \ -+ rk3568-bpi-r2-pro.dtb \ - rk3568-evb.dtb \ - rk3566-quartz64-a.dtb - ---- /dev/null -+++ b/arch/arm/dts/rk3568-bpi-r2-pro-u-boot.dtsi -@@ -0,0 +1,47 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd -+ */ -+ -+#include "rk3568-u-boot.dtsi" -+ -+/ { -+ chosen { -+ stdout-path = &uart2; -+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; -+ }; -+}; -+ -+&gmac1 { -+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; -+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; -+ status = "disabled"; -+}; -+ -+&sdmmc0 { -+ bus-width = <4>; -+ u-boot,dm-spl; -+ u-boot,spl-fifo-mode; -+}; -+ -+&usb_host0_ehci { -+ vbus-supply = <&vcc5v0_usb_host>; -+}; -+ -+&usb_host0_ohci { -+ vbus-supply = <&vcc5v0_usb_host>; -+}; -+ -+&usb_host1_ehci { -+ vbus-supply = <&vcc5v0_usb_host>; -+}; -+ -+&usb_host1_ohci { -+ vbus-supply = <&vcc5v0_usb_host>; -+}; -+ -+&uart2 { -+ clock-frequency = <24000000>; -+ u-boot,dm-spl; -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/dts/rk3568-bpi-r2-pro.dts -@@ -0,0 +1,532 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Author: Frank Wunderlich -+ * -+ */ -+ -+/dts-v1/; -+#include -+#include -+#include -+#include "rk3568.dtsi" -+ -+/ { -+ model = "Bananapi-R2 Pro (RK3568) DDR4 Board"; -+ compatible = "rockchip,rk3568-bpi-r2pro", "rockchip,rk3568"; -+ -+ aliases { -+ ethernet0 = &gmac0; -+ ethernet1 = &gmac1; -+ mmc0 = &sdmmc0; -+ mmc1 = &sdhci; -+ }; -+ -+ chosen: chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&blue_led_pin &green_led_pin>; -+ -+ blue_led: led-0 { -+ color = ; -+ default-state = "off"; -+ function = LED_FUNCTION_STATUS; -+ gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ green_led: led-1 { -+ color = ; -+ default-state = "on"; -+ function = LED_FUNCTION_POWER; -+ gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+ -+ dc_12v: dc-12v { -+ compatible = "regulator-fixed"; -+ regulator-name = "dc_12v"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ }; -+ -+ vcc3v3_sys: vcc3v3-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&dc_12v>; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&dc_12v>; -+ }; -+ -+ vcc5v0_usb: vcc5v0_usb { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_usb"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&dc_12v>; -+ }; -+ -+ vcc5v0_usb_host: vcc5v0-usb-host { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_usb_host_en>; -+ regulator-name = "vcc5v0_usb_host"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_usb>; -+ }; -+ -+ vcc5v0_usb_otg: vcc5v0-usb-otg { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_usb_otg_en>; -+ regulator-name = "vcc5v0_usb_otg"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_usb>; -+ }; -+}; -+ -+&combphy0 { -+ /* used for USB3 */ -+ status = "okay"; -+}; -+ -+&combphy1 { -+ /* used for USB3 */ -+ status = "okay"; -+}; -+ -+&combphy2 { -+ /* used for SATA */ -+ status = "okay"; -+}; -+ -+&gmac0 { -+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; -+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; -+ clock_in_out = "input"; -+ phy-mode = "rgmii"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmac0_miim -+ &gmac0_tx_bus2 -+ &gmac0_rx_bus2 -+ &gmac0_rgmii_clk -+ &gmac0_rgmii_bus>; -+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; -+ snps,reset-active-low; -+ /* Reset time is 20ms, 100ms for rtl8211f */ -+ snps,reset-delays-us = <0 20000 100000>; -+ tx_delay = <0x4f>; -+ rx_delay = <0x0f>; -+ status = "okay"; -+ -+ fixed-link { -+ speed = <1000>; -+ full-duplex; -+ pause; -+ }; -+}; -+ -+&gmac1 { -+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; -+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; -+ clock_in_out = "output"; -+ phy-handle = <&rgmii_phy1>; -+ phy-mode = "rgmii"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmac1m1_miim -+ &gmac1m1_tx_bus2 -+ &gmac1m1_rx_bus2 -+ &gmac1m1_rgmii_clk -+ &gmac1m1_rgmii_bus>; -+ -+ snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; -+ snps,reset-active-low; -+ /* Reset time is 20ms, 100ms for rtl8211f */ -+ snps,reset-delays-us = <0 20000 100000>; -+ -+ tx_delay = <0x3c>; -+ rx_delay = <0x2f>; -+ -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ rk809: pmic@20 { -+ compatible = "rockchip,rk809"; -+ reg = <0x20>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ #clock-cells = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int>; -+ rockchip,system-power-controller; -+ vcc1-supply = <&vcc3v3_sys>; -+ vcc2-supply = <&vcc3v3_sys>; -+ vcc3-supply = <&vcc3v3_sys>; -+ vcc4-supply = <&vcc3v3_sys>; -+ vcc5-supply = <&vcc3v3_sys>; -+ vcc6-supply = <&vcc3v3_sys>; -+ vcc7-supply = <&vcc3v3_sys>; -+ vcc8-supply = <&vcc3v3_sys>; -+ vcc9-supply = <&vcc3v3_sys>; -+ wakeup-source; -+ -+ regulators { -+ vdd_logic: DCDC_REG1 { -+ regulator-name = "vdd_logic"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: DCDC_REG2 { -+ regulator-name = "vdd_gpu"; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vdd_npu: DCDC_REG4 { -+ regulator-name = "vdd_npu"; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: DCDC_REG5 { -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_image: LDO_REG1 { -+ regulator-name = "vdda0v9_image"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda_0v9: LDO_REG2 { -+ regulator-name = "vdda_0v9"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_pmu: LDO_REG3 { -+ regulator-name = "vdda0v9_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ vccio_acodec: LDO_REG4 { -+ regulator-name = "vccio_acodec"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd: LDO_REG5 { -+ regulator-name = "vccio_sd"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_pmu: LDO_REG6 { -+ regulator-name = "vcc3v3_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcca_1v8: LDO_REG7 { -+ regulator-name = "vcca_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcca1v8_pmu: LDO_REG8 { -+ regulator-name = "vcca1v8_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcca1v8_image: LDO_REG9 { -+ regulator-name = "vcca1v8_image"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v3: SWITCH_REG1 { -+ regulator-name = "vcc_3v3"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_sd: SWITCH_REG2 { -+ regulator-name = "vcc3v3_sd"; -+ regulator-always-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&i2c5 { -+ /* pin 3 (SDA) + 4 (SCL) of header con2 */ -+ status = "disabled"; -+}; -+ -+&mdio1 { -+ rgmii_phy1: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <0x0>; -+ }; -+}; -+ -+&pinctrl { -+ leds { -+ blue_led_pin: blue-led-pin { -+ rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ green_led_pin: green-led-pin { -+ rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int: pmic_int { -+ rockchip,pins = -+ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ usb { -+ vcc5v0_usb_host_en: vcc5v0_usb_host_en { -+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { -+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&pmu_io_domains { -+ pmuio1-supply = <&vcc3v3_pmu>; -+ pmuio2-supply = <&vcc3v3_pmu>; -+ vccio1-supply = <&vccio_acodec>; -+ vccio3-supply = <&vccio_sd>; -+ vccio4-supply = <&vcc_3v3>; -+ vccio5-supply = <&vcc_3v3>; -+ vccio6-supply = <&vcc_1v8>; -+ vccio7-supply = <&vcc_3v3>; -+ status = "okay"; -+}; -+ -+&pwm8 { -+ /* fan 5v - gnd - pwm */ -+ status = "okay"; -+}; -+ -+&pwm10 { -+ /* pin 7 of header con2 */ -+ status = "disabled"; -+}; -+ -+&pwm11 { -+ /* pin 15 of header con2 */ -+ status = "disabled"; -+}; -+ -+ -+&pwm13 { -+ /* pin 24 of header con2 */ -+ /* shared with uart9 */ -+ pinctrl-0 = <&pwm13m1_pins>; -+ status = "disabled"; -+}; -+ -+&saradc { -+ vref-supply = <&vcca_1v8>; -+ status = "okay"; -+}; -+ -+&sata2 { -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ max-frequency = <200000000>; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; -+ status = "okay"; -+}; -+ -+&sdmmc0 { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; -+ disable-wp; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc3v3_sd>; -+ vqmmc-supply = <&vccio_sd>; -+ status = "okay"; -+}; -+ -+&tsadc { -+ status = "okay"; -+}; -+ -+&uart0 { -+ /* pin 8 (TX) + 10 (RX) (RTS:16, CTS:18) of header con2 */ -+ status = "disabled"; -+}; -+ -+&uart2 { -+ /* debug-uart */ -+ status = "okay"; -+}; -+ -+&uart7 { -+ /* pin 11 (TX) + 13 (RX) of header con2 */ -+ pinctrl-0 = <&uart7m1_xfer>; -+ status = "disabled"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; ---- a/arch/arm/mach-rockchip/rk3568/Kconfig -+++ b/arch/arm/mach-rockchip/rk3568/Kconfig -@@ -3,6 +3,11 @@ if ROCKCHIP_RK3568 - choice - prompt "RK3568/RK3566 board select" - -+config TARGET_BPI_R2_PRO_RK3568 -+ bool "Banana Pi R2 Pro RK3566 development board" -+ help -+ Banana Pi R2 Pro is a development board Rockchp RK3568. -+ - config TARGET_EVB_RK3568 - bool "RK3568 evaluation board" - help -@@ -27,6 +32,7 @@ config SYS_SOC - config SYS_MALLOC_F_LEN - default 0x2000 - -+source "board/rockchip/bpi-r2-pro-rk3568/Kconfig" - source "board/rockchip/evb_rk3568/Kconfig" - source "board/pine64/quartz64-a-rk3566/Kconfig" - ---- /dev/null -+++ b/board/rockchip/bpi-r2-pro-rk3568/Kconfig -@@ -0,0 +1,15 @@ -+if TARGET_BPI_R2_PRO_RK3568 -+ -+config SYS_BOARD -+ default "bpi-r2-pro-rk3568" -+ -+config SYS_VENDOR -+ default "rockchip" -+ -+config SYS_CONFIG_NAME -+ default "bpi-r2-pro-rk3568" -+ -+config BOARD_SPECIFIC_OPTIONS # dummy -+ def_bool y -+ -+endif ---- /dev/null -+++ b/board/rockchip/bpi-r2-pro-rk3568/Makefile -@@ -0,0 +1,7 @@ -+# -+# (C) Copyright 2021 Rockchip Electronics Co., Ltd -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+obj-y += bpi-r2-pro-rk3568.o ---- /dev/null -+++ b/board/rockchip/bpi-r2-pro-rk3568/bpi-r2-pro-rk3568.c -@@ -0,0 +1,4 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd -+ */ ---- /dev/null -+++ b/configs/bpi-r2-pro-rk3568_defconfig -@@ -0,0 +1,97 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00a00000 -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_DEFAULT_DEVICE_TREE="rk3568-bpi-r2-pro" -+CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y -+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_MMC=y -+CONFIG_SPL_SERIAL=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_TARGET_BPI_R2_PRO_RK3568=y -+CONFIG_DEBUG_UART_BASE=0xFE660000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0xc00800 -+CONFIG_API=y -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_OF_SYSTEM_SETUP=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-bpi-r2-pro.dtb" -+# CONFIG_SYS_DEVICE_NULLDEV is not set -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_SEPARATE_BSS=y -+CONFIG_SPL_ATF=y -+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y -+CONFIG_CMD_BIND=y -+CONFIG_CMD_CLK=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_PMIC=y -+CONFIG_CMD_REGULATOR=y -+# CONFIG_SPL_DOS_PARTITION is not set -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_LIVE=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_SPL_DM_WARN=y -+CONFIG_SPL_REGMAP=y -+CONFIG_SPL_SYSCON=y -+CONFIG_SPL_CLK=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_ROCKCHIP_GPIO_V2=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_SPL_MMC_HS200_SUPPORT=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_PMIC_RK8XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_SPL_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_SPL_RAM=y -+CONFIG_DM_RESET=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSRESET=y -+CONFIG_SYSRESET_PSCI=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GENERIC=y -+CONFIG_ROCKCHIP_USB2_PHY=y -+CONFIG_USB_KEYBOARD=y -+CONFIG_USB_HOST_ETHER=y -+CONFIG_USB_ETHER_LAN75XX=y -+CONFIG_USB_ETHER_LAN78XX=y -+CONFIG_USB_ETHER_SMSC95XX=y -+CONFIG_ERRNO_STR=y ---- /dev/null -+++ b/include/configs/bpi-r2-pro-rk3568.h -@@ -0,0 +1,15 @@ -+#ifndef __BPI_R2_PRO_RK3568_H -+#define __BPI_R2_PRO_RK3568_H -+ -+#include -+ -+#define CONFIG_SUPPORT_EMMC_RPMB -+ -+#define ROCKCHIP_DEVICE_SETTINGS \ -+ "stdout=serial,vidconsole\0" \ -+ "stderr=serial,vidconsole\0" -+ -+#define CONFIG_USB_OHCI_NEW -+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -+ -+#endif diff --git a/5.4/package/boot/uboot-rockchip/patches/014-uboot-add-Radxa-ROCK-3A-board.patch b/5.4/package/boot/uboot-rockchip/patches/014-uboot-add-Radxa-ROCK-3A-board.patch deleted file mode 100644 index 4f38e695..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/014-uboot-add-Radxa-ROCK-3A-board.patch +++ /dev/null @@ -1,690 +0,0 @@ -From 443eb96a82563a3b38a3c9548853a5a266dfd072 Mon Sep 17 00:00:00 2001 -From: Marty Jones -Date: Sun, 29 May 2022 06:09:59 -0400 -Subject: [PATCH] uboot: add Radxa ROCK 3A board - -Signed-off-by: Marty Jones ---- - arch/arm/dts/Makefile | 3 +- - arch/arm/dts/rk3568-rock-3a-u-boot.dtsi | 25 + - arch/arm/dts/rk3568-rock-3a.dts | 525 ++++++++++++++++++++ - arch/arm/mach-rockchip/rk3568/Kconfig | 6 + - board/radxa/rock-3a-rk3568/Kconfig | 15 + - board/radxa/rock-3a-rk3568/Makefile | 4 + - board/radxa/rock-3a-rk3568/rock-3a-rk3568.c | 1 + - configs/rock-3a-rk3568_defconfig | 97 ++++ - include/configs/rock-3a-rk3568.h | 17 + - 9 files changed, 692 insertions(+), 1 deletion(-) - create mode 100644 arch/arm/dts/rk3568-rock-3a-u-boot.dtsi - create mode 100644 arch/arm/dts/rk3568-rock-3a.dts - create mode 100644 configs/rock-3a-rk3568_defconfig - create mode 100644 include/configs/rock-3a-rk3568.h - ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -166,7 +166,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ - dtb-$(CONFIG_ROCKCHIP_RK3568) += \ - rk3568-bpi-r2-pro.dtb \ - rk3568-evb.dtb \ -- rk3566-quartz64-a.dtb -+ rk3566-quartz64-a.dtb \ -+ rk3568-rock-3a.dtb - - dtb-$(CONFIG_ROCKCHIP_RV1108) += \ - rv1108-elgin-r1.dtb \ ---- /dev/null -+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi -@@ -0,0 +1,24 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd -+ */ -+ -+#include "rk3568-u-boot.dtsi" -+ -+/ { -+ chosen { -+ stdout-path = &uart2; -+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; -+ }; -+}; -+ -+&sdmmc0 { -+ bus-width = <4>; -+ u-boot,spl-fifo-mode; -+}; -+ -+&uart2 { -+ u-boot,dm-spl; -+ clock-frequency = <24000000>; -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/dts/rk3568-rock-3a.dts -@@ -0,0 +1,525 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+#include -+#include -+#include -+#include "rk3568.dtsi" -+ -+/ { -+ model = "Radxa ROCK3 Model A"; -+ compatible = "radxa,rock3a", "rockchip,rk3568"; -+ -+ aliases { -+ ethernet0 = &gmac1; -+ mmc0 = &sdmmc0; -+ mmc1 = &sdhci; -+ }; -+ -+ chosen: chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ led_user: led-0 { -+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; -+ function = LED_FUNCTION_HEARTBEAT; -+ color = ; -+ linux,default-trigger = "heartbeat"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&led_user_en>; -+ }; -+ }; -+ -+ rk809-sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,name = "Analog RK809"; -+ simple-audio-card,mclk-fs = <256>; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&i2s1_8ch>; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&rk809>; -+ }; -+ }; -+ -+ vcc12v_dcin: vcc12v-dcin { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc12v_dcin"; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ vcc3v3_sys: vcc3v3-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc12v_dcin>; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc12v_dcin>; -+ }; -+ -+ vcc5v0_usb: vcc5v0-usb { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_usb"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc12v_dcin>; -+ }; -+ -+ vcc5v0_usb_host: vcc5v0-usb-host { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_usb_host_en>; -+ regulator-name = "vcc5v0_usb_host"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_usb>; -+ }; -+ -+ vcc5v0_usb_hub: vcc5v0-usb-hub-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_usb_hub_en>; -+ regulator-name = "vcc5v0_usb_hub"; -+ regulator-always-on; -+ vin-supply = <&vcc5v0_usb>; -+ }; -+ -+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_usb_otg_en>; -+ regulator-name = "vcc5v0_usb_otg"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc5v0_usb>; -+ }; -+}; -+ -+&combphy0 { -+ status = "okay"; -+}; -+ -+&combphy1 { -+ status = "okay"; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu2 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu3 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&gmac1 { -+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; -+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; -+ assigned-clock-rates = <0>, <125000000>; -+ clock_in_out = "output"; -+ phy-handle = <&rgmii_phy1>; -+ phy-mode = "rgmii-id"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmac1m1_miim -+ &gmac1m1_tx_bus2 -+ &gmac1m1_rx_bus2 -+ &gmac1m1_rgmii_clk -+ &gmac1m1_rgmii_bus>; -+ status = "okay"; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ vdd_cpu: regulator@1c { -+ compatible = "tcs,tcs4525"; -+ reg = <0x1c>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1150000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ rk809: pmic@20 { -+ compatible = "rockchip,rk809"; -+ reg = <0x20>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>; -+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; -+ #clock-cells = <1>; -+ clock-names = "mclk"; -+ clocks = <&cru I2S1_MCLKOUT_TX>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; -+ rockchip,system-power-controller; -+ #sound-dai-cells = <0>; -+ vcc1-supply = <&vcc3v3_sys>; -+ vcc2-supply = <&vcc3v3_sys>; -+ vcc3-supply = <&vcc3v3_sys>; -+ vcc4-supply = <&vcc3v3_sys>; -+ vcc5-supply = <&vcc3v3_sys>; -+ vcc6-supply = <&vcc3v3_sys>; -+ vcc7-supply = <&vcc3v3_sys>; -+ vcc8-supply = <&vcc3v3_sys>; -+ vcc9-supply = <&vcc3v3_sys>; -+ wakeup-source; -+ -+ regulators { -+ vdd_logic: DCDC_REG1 { -+ regulator-name = "vdd_logic"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: DCDC_REG2 { -+ regulator-name = "vdd_gpu"; -+ regulator-always-on; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vdd_npu: DCDC_REG4 { -+ regulator-name = "vdd_npu"; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: DCDC_REG5 { -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_image: LDO_REG1 { -+ regulator-name = "vdda0v9_image"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda_0v9: LDO_REG2 { -+ regulator-name = "vdda_0v9"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_pmu: LDO_REG3 { -+ regulator-name = "vdda0v9_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ vccio_acodec: LDO_REG4 { -+ regulator-name = "vccio_acodec"; -+ regulator-always-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd: LDO_REG5 { -+ regulator-name = "vccio_sd"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_pmu: LDO_REG6 { -+ regulator-name = "vcc3v3_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcca_1v8: LDO_REG7 { -+ regulator-name = "vcca_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcca1v8_pmu: LDO_REG8 { -+ regulator-name = "vcca1v8_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcca1v8_image: LDO_REG9 { -+ regulator-name = "vcca1v8_image"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v3: SWITCH_REG1 { -+ regulator-name = "vcc_3v3"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_sd: SWITCH_REG2 { -+ regulator-name = "vcc3v3_sd"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ -+ codec { -+ mic-in-differential; -+ }; -+ }; -+}; -+ -+&i2s1_8ch { -+ rockchip,trcm-sync-tx-only; -+ status = "okay"; -+}; -+ -+&mdio1 { -+ rgmii_phy1: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <0x0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <ð_phy_rst>; -+ reset-assert-us = <20000>; -+ reset-deassert-us = <100000>; -+ reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; -+ }; -+}; -+ -+&pinctrl { -+ ethernet { -+ eth_phy_rst: eth_phy_rst { -+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ leds { -+ led_user_en: led_user_en { -+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int: pmic_int { -+ rockchip,pins = -+ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ usb { -+ vcc5v0_usb_host_en: vcc5v0_usb_host_en { -+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ vcc5v0_usb_hub_en: vcc5v0_usb_hub_en { -+ rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { -+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -+ -+&pmu_io_domains { -+ pmuio1-supply = <&vcc3v3_pmu>; -+ pmuio2-supply = <&vcc3v3_pmu>; -+ vccio1-supply = <&vccio_acodec>; -+ vccio2-supply = <&vcc_1v8>; -+ vccio3-supply = <&vccio_sd>; -+ vccio4-supply = <&vcc_1v8>; -+ vccio5-supply = <&vcc_3v3>; -+ vccio6-supply = <&vcc_1v8>; -+ vccio7-supply = <&vcc_3v3>; -+ status = "okay"; -+}; -+ -+&saradc { -+ vref-supply = <&vcca_1v8>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ max-frequency = <200000000>; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; -+ vmmc-supply = <&vcc_3v3>; -+ vqmmc-supply = <&vcc_1v8>; -+ status = "okay"; -+}; -+ -+&sdmmc0 { -+ bus-width = <4>; -+ cap-sd-highspeed; -+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; -+ disable-wp; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc3v3_sd>; -+ vqmmc-supply = <&vccio_sd>; -+ status = "okay"; -+}; -+ -+&tsadc { -+ rockchip,hw-tshut-mode = <1>; -+ rockchip,hw-tshut-polarity = <0>; -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; ---- /dev/null -+++ b/configs/rock-3a-rk3568_defconfig -@@ -0,0 +1,98 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00a00000 -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_DEFAULT_DEVICE_TREE="rk3568-rock-3a" -+CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y -+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_MMC=y -+CONFIG_SPL_SERIAL=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_TARGET_EVB_RK3568=y -+CONFIG_DEBUG_UART_BASE=0xFE660000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0xc00800 -+CONFIG_API=y -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_OF_SYSTEM_SETUP=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rock-3a.dtb" -+# CONFIG_SYS_DEVICE_NULLDEV is not set -+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_SEPARATE_BSS=y -+CONFIG_SPL_ATF=y -+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y -+CONFIG_CMD_BIND=y -+CONFIG_CMD_CLK=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_PMIC=y -+CONFIG_CMD_REGULATOR=y -+# CONFIG_SPL_DOS_PARTITION is not set -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_LIVE=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_SPL_DM_WARN=y -+CONFIG_SPL_REGMAP=y -+CONFIG_SPL_SYSCON=y -+CONFIG_SPL_CLK=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_ROCKCHIP_GPIO_V2=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_SPL_MMC_HS200_SUPPORT=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_PMIC_RK8XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_SPL_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_SPL_RAM=y -+CONFIG_DM_RESET=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSRESET=y -+CONFIG_SYSRESET_PSCI=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GENERIC=y -+CONFIG_ROCKCHIP_USB2_PHY=y -+CONFIG_USB_KEYBOARD=y -+CONFIG_USB_HOST_ETHER=y -+CONFIG_USB_ETHER_LAN75XX=y -+CONFIG_USB_ETHER_LAN78XX=y -+CONFIG_USB_ETHER_SMSC95XX=y -+CONFIG_ERRNO_STR=y diff --git a/5.4/package/boot/uboot-rockchip/patches/015-uboot-add-NanoPi-R5S-board.patch b/5.4/package/boot/uboot-rockchip/patches/015-uboot-add-NanoPi-R5S-board.patch deleted file mode 100644 index b527a261..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/015-uboot-add-NanoPi-R5S-board.patch +++ /dev/null @@ -1,247 +0,0 @@ -From 872197ee382688701f85fc486a14dc02d2113811 Mon Sep 17 00:00:00 2001 -From: Marty Jones -Date: Tue, 31 May 2022 00:51:23 -0400 -Subject: [PATCH] uboot: add NanoPi R5S board - -Signed-off-by: Marty Jones ---- - arch/arm/dts/Makefile | 1 + - arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi | 25 +++++ - arch/arm/dts/rk3568-nanopi-r5s.dts | 9 ++ - arch/arm/mach-rockchip/rk3568/Kconfig | 6 ++ - board/friendlyelec/nanopi-r5s-rk3568/Kconfig | 15 +++ - board/friendlyelec/nanopi-r5s-rk3568/Makefile | 4 + - .../nanopi-r5s-rk3568/nanopi-r5s-rk3568.c | 4 + - configs/nanopi-r5s-rk3568_defconfig | 97 +++++++++++++++++++ - include/configs/nanopi-r5s-rk3568.h | 17 ++++ - 9 files changed, 178 insertions(+) - create mode 100644 arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi - create mode 100644 arch/arm/dts/rk3568-nanopi-r5s.dts - create mode 100644 board/friendlyelec/nanopi-r5s-rk3568/Kconfig - create mode 100644 board/friendlyelec/nanopi-r5s-rk3568/Makefile - create mode 100644 board/friendlyelec/nanopi-r5s-rk3568/nanopi-r5s-rk3568.c - create mode 100644 configs/nanopi-r5s-rk3568_defconfig - create mode 100644 include/configs/nanopi-r5s-rk3568.h - ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -166,6 +166,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ - dtb-$(CONFIG_ROCKCHIP_RK3568) += \ - rk3568-bpi-r2-pro.dtb \ - rk3568-evb.dtb \ -+ rk3568-nanopi-r5s.dtb \ - rk3566-quartz64-a.dtb \ - rk3568-rock-3a.dtb - ---- /dev/null -+++ b/arch/arm/dts/rk3568-nanopi-r5s-u-boot.dtsi -@@ -0,0 +1,25 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd -+ */ -+ -+#include "rk3568-u-boot.dtsi" -+ -+/ { -+ chosen { -+ stdout-path = &uart2; -+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; -+ }; -+}; -+ -+&sdmmc0 { -+ bus-width = <4>; -+ u-boot,dm-spl; -+ u-boot,spl-fifo-mode; -+}; -+ -+&uart2 { -+ clock-frequency = <24000000>; -+ u-boot,dm-spl; -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/dts/rk3568-nanopi-r5s.dts -@@ -0,0 +1,9 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+#include "rk3568-evb.dts" -+ -+/ { -+ model = "FriendlyElec NanoPi R5S"; -+ compatible = "friendlyelec,nanopi-r5s", "rockchip,rk3568"; -+}; ---- a/arch/arm/mach-rockchip/rk3568/Kconfig -+++ b/arch/arm/mach-rockchip/rk3568/Kconfig -@@ -13,6 +13,11 @@ config TARGET_EVB_RK3568 - help - RK3568 EVB is a evaluation board for Rockchp RK3568. - -+config TARGET_NANOPI_R5S_RK3568 -+ bool "NanoPi R5S board" -+ help -+ NanoPi R5S FriendlyElec is a board for Rockchp RK3568. -+ - config TARGET_QUARTZ64_A_RK3566 - bool "Quartz64 Model A RK3566 development board" - help -@@ -39,6 +44,7 @@ config SYS_MALLOC_F_LEN - - source "board/rockchip/bpi-r2-pro-rk3568/Kconfig" - source "board/rockchip/evb_rk3568/Kconfig" -+source "board/friendlyelec/nanopi-r5s-rk3568/Kconfig" - source "board/pine64/quartz64-a-rk3566/Kconfig" - source "board/radxa/rock-3a-rk3568/Kconfig" - ---- /dev/null -+++ b/board/friendlyelec/nanopi-r5s-rk3568/Kconfig -@@ -0,0 +1,15 @@ -+if TARGET_NANOPI_R5S_RK3568 -+ -+config SYS_BOARD -+ default "nanopi-r5s-rk3568" -+ -+config SYS_VENDOR -+ default "friendlyelec" -+ -+config SYS_CONFIG_NAME -+ default "nanopi-r5s-rk3568" -+ -+config BOARD_SPECIFIC_OPTIONS # dummy -+ def_bool y -+ -+endif ---- /dev/null -+++ b/board/friendlyelec/nanopi-r5s-rk3568/Makefile -@@ -0,0 +1,4 @@ -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+obj-y += nanopi-r5s-rk3568.o ---- /dev/null -+++ b/board/friendlyelec/nanopi-r5s-rk3568/nanopi-r5s-rk3568.c -@@ -0,0 +1,4 @@ -+ // SPDX-License-Identifier: GPL-2.0+ -+/* -+ * -+ */ ---- /dev/null -+++ b/configs/nanopi-r5s-rk3568_defconfig -@@ -0,0 +1,98 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00a00000 -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s" -+CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y -+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_MMC=y -+CONFIG_SPL_SERIAL=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_TARGET_NANOPI_R5S_RK3568=y -+CONFIG_DEBUG_UART_BASE=0xFE660000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0xc00800 -+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 -+CONFIG_API=y -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_OF_SYSTEM_SETUP=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb" -+# CONFIG_SYS_DEVICE_NULLDEV is not set -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_SEPARATE_BSS=y -+CONFIG_SPL_ATF=y -+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y -+CONFIG_CMD_BIND=y -+CONFIG_CMD_CLK=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_PMIC=y -+CONFIG_CMD_REGULATOR=y -+# CONFIG_SPL_DOS_PARTITION is not set -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_LIVE=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_SPL_DM_WARN=y -+CONFIG_SPL_REGMAP=y -+CONFIG_SPL_SYSCON=y -+CONFIG_SPL_CLK=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_ROCKCHIP_GPIO_V2=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_SPL_MMC_HS200_SUPPORT=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_PMIC_RK8XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_SPL_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_SPL_RAM=y -+CONFIG_DM_RESET=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSRESET=y -+CONFIG_SYSRESET_PSCI=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GENERIC=y -+CONFIG_ROCKCHIP_USB2_PHY=y -+CONFIG_USB_KEYBOARD=y -+CONFIG_USB_HOST_ETHER=y -+CONFIG_USB_ETHER_LAN75XX=y -+CONFIG_USB_ETHER_LAN78XX=y -+CONFIG_USB_ETHER_SMSC95XX=y -+CONFIG_ERRNO_STR=y ---- /dev/null -+++ b/include/configs/nanopi-r5s-rk3568.h -@@ -0,0 +1,14 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+ -+#ifndef __NANOPI_R5S_RK3568_H -+#define __NANOPI_R5S_RK3568_H -+ -+#include -+ -+#define CONFIG_SUPPORT_EMMC_RPMB -+ -+#define ROCKCHIP_DEVICE_SETTINGS \ -+ "stdout=serial,vidconsole\0" \ -+ "stderr=serial,vidconsole\0" -+ -+#endif diff --git a/5.4/package/boot/uboot-rockchip/patches/016-rk356x-ddr-fix-dbw-detect-bug.patch b/5.4/package/boot/uboot-rockchip/patches/016-rk356x-ddr-fix-dbw-detect-bug.patch deleted file mode 100644 index 563c6c29..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/016-rk356x-ddr-fix-dbw-detect-bug.patch +++ /dev/null @@ -1,42 +0,0 @@ -From c9a8a3b5fb4ae210c5a5acb1538b0e961c5d1421 Mon Sep 17 00:00:00 2001 -From: Tang Yun ping -Date: Wed, 23 Jun 2021 19:48:59 +0800 -Subject: [PATCH] rk356x: ddr: fix dbw detect bug - -Signed-off-by: Tang Yun ping -Change-Id: Ifadad00853eb0ad43a68f12335fd243e6a1bc04b ---- - drivers/ram/rockchip/sdram_common.c | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - ---- a/drivers/ram/rockchip/sdram_common.c -+++ b/drivers/ram/rockchip/sdram_common.c -@@ -299,22 +299,22 @@ int sdram_detect_dbw(struct sdram_cap_info *cap_info, u32 dram_type) - bw = cap_info->bw; - cs_cap = (1 << (row + col + bk + bw - 20)); - if (bw == 2) { -- if (cs_cap <= 0x2000000) /* 256Mb */ -+ if (cs_cap <= 0x20) /* 256Mb */ - die_bw_0 = (col < 9) ? 2 : 1; -- else if (cs_cap <= 0x10000000) /* 2Gb */ -+ else if (cs_cap <= 0x100) /* 2Gb */ - die_bw_0 = (col < 10) ? 2 : 1; -- else if (cs_cap <= 0x40000000) /* 8Gb */ -+ else if (cs_cap <= 0x400) /* 8Gb */ - die_bw_0 = (col < 11) ? 2 : 1; - else - die_bw_0 = (col < 12) ? 2 : 1; - if (cs > 1) { - row = cap_info->cs1_row; - cs_cap = (1 << (row + col + bk + bw - 20)); -- if (cs_cap <= 0x2000000) /* 256Mb */ -+ if (cs_cap <= 0x20) /* 256Mb */ - die_bw_0 = (col < 9) ? 2 : 1; -- else if (cs_cap <= 0x10000000) /* 2Gb */ -+ else if (cs_cap <= 0x100) /* 2Gb */ - die_bw_0 = (col < 10) ? 2 : 1; -- else if (cs_cap <= 0x40000000) /* 8Gb */ -+ else if (cs_cap <= 0x400) /* 8Gb */ - die_bw_0 = (col < 11) ? 2 : 1; - else - die_bw_0 = (col < 12) ? 2 : 1; diff --git a/5.4/package/boot/uboot-rockchip/patches/017-gpio-rockchip-fix-building-for-spl.patch b/5.4/package/boot/uboot-rockchip/patches/017-gpio-rockchip-fix-building-for-spl.patch deleted file mode 100644 index 9632bbf5..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/017-gpio-rockchip-fix-building-for-spl.patch +++ /dev/null @@ -1,44 +0,0 @@ -From c7496009386dbac8f8d18a94258031f30683d7c6 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Sun, 20 Feb 2022 07:59:02 -0500 -Subject: [PATCH] gpio: rockchip: fix building for spl - -Signed-off-by: Peter Geis ---- - drivers/gpio/rk_gpio.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/common/spl/Kconfig -+++ b/common/spl/Kconfig -@@ -454,6 +454,11 @@ config SPL_FIT_IMAGE_TINY - ensure this information is available to the next image - invoked). - -+config SPL_ADC -+ bool "Support ADC drivers in SPL" -+ help -+ Enable ADC drivers in SPL. -+ - config SPL_CACHE - bool "Support CACHE drivers" - help ---- a/drivers/Makefile -+++ b/drivers/Makefile -@@ -1,5 +1,6 @@ - # SPDX-License-Identifier: GPL-2.0+ - -+obj-$(CONFIG_$(SPL_)ADC) += adc/ - obj-$(CONFIG_$(SPL_TPL_)BOOTCOUNT_LIMIT) += bootcount/ - obj-$(CONFIG_$(SPL_TPL_)BUTTON) += button/ - obj-$(CONFIG_$(SPL_TPL_)CACHE) += cache/ ---- a/drivers/gpio/rk_gpio.c -+++ b/drivers/gpio/rk_gpio.c -@@ -118,7 +118,7 @@ static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset) - } - - /* Simple SPL interface to GPIOs */ --#ifdef CONFIG_SPL_BUILD -+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ROCKCHIP_GPIO_V2) - - enum { - PULL_NONE_1V8 = 0, diff --git a/5.4/package/boot/uboot-rockchip/patches/018-clk-rockchip-rk3568-fix-reset-handler.patch b/5.4/package/boot/uboot-rockchip/patches/018-clk-rockchip-rk3568-fix-reset-handler.patch deleted file mode 100644 index 632394a8..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/018-clk-rockchip-rk3568-fix-reset-handler.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 5011ceb0da47f7c3d54d20b45b7df884e6e92ac5 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Sun, 20 Feb 2022 07:58:38 -0500 -Subject: [PATCH] clk: rockchip: rk3568: fix reset handler - -Signed-off-by: Peter Geis ---- - drivers/clk/rockchip/clk_rk3568.c | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/drivers/clk/rockchip/clk_rk3568.c -+++ b/drivers/clk/rockchip/clk_rk3568.c -@@ -14,6 +14,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -2934,6 +2935,7 @@ static int rk3568_clk_bind(struct udevice *dev) - glb_srst_fst); - priv->glb_srst_snd_value = offsetof(struct rk3568_cru, - glb_srsr_snd); -+ dev_set_priv(sys_child, priv); - } - - #if CONFIG_IS_ENABLED(RESET_ROCKCHIP) diff --git a/5.4/package/boot/uboot-rockchip/patches/019-rockchip-handle-bootrom-mode-in-spl.patch b/5.4/package/boot/uboot-rockchip/patches/019-rockchip-handle-bootrom-mode-in-spl.patch deleted file mode 100644 index df7acc39..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/019-rockchip-handle-bootrom-mode-in-spl.patch +++ /dev/null @@ -1,144 +0,0 @@ -From 79cb33b9da0c9475486ca0759341057854b25e38 Mon Sep 17 00:00:00 2001 -From: Peter Geis -Date: Sun, 20 Feb 2022 07:57:50 -0500 -Subject: [PATCH] rockchip: handle bootrom mode in spl - -Signed-off-by: Peter Geis ---- - arch/arm/mach-rockchip/Makefile | 6 +-- - arch/arm/mach-rockchip/boot_mode.c | 4 +- - arch/arm/mach-rockchip/rk3568/rk3568.c | 54 +++++++++++++++++++++++++- - 3 files changed, 59 insertions(+), 5 deletions(-) - ---- a/arch/arm/mach-rockchip/Makefile -+++ b/arch/arm/mach-rockchip/Makefile -@@ -15,13 +15,13 @@ obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-board-tpl.o - - obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o - --ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) -- - # Always include boot_mode.o, as we bypass it (i.e. turn it off) - # inside of boot_mode.c when CONFIG_BOOT_MODE_REG is 0. This way, - # we can have the preprocessor correctly recognise both 0x0 and 0 - # meaning "turn it off". --obj-y += boot_mode.o -+obj-$(CONFIG_ARCH_ROCKCHIP) += boot_mode.o -+ -+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) - obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o - obj-$(CONFIG_MISC_INIT_R) += misc.o - endif ---- a/arch/arm/mach-rockchip/boot_mode.c -+++ b/arch/arm/mach-rockchip/boot_mode.c -@@ -51,7 +51,7 @@ __weak int rockchip_dnl_key_pressed(void) - ret = -ENODEV; - uclass_foreach_dev(dev, uc) { - if (!strncmp(dev->name, "saradc", 6)) { -- ret = adc_channel_single_shot(dev->name, 1, &val); -+ ret = adc_channel_single_shot(dev->name, 0, &val); - break; - } - } -@@ -89,6 +89,7 @@ int setup_boot_mode(void) - boot_mode = readl(reg); - debug("%s: boot mode 0x%08x\n", __func__, boot_mode); - -+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) - /* Clear boot mode */ - writel(BOOT_NORMAL, reg); - -@@ -102,6 +103,7 @@ int setup_boot_mode(void) - env_set("preboot", "setenv preboot; ums mmc 0"); - break; - } -+#endif - - return 0; - } ---- a/arch/arm/mach-rockchip/rk3568/rk3568.c -+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c -@@ -9,19 +9,30 @@ - #include - #include - #include -+#include - #include - #include - #include - - #define PMUGRF_BASE 0xfdc20000 - #define GRF_BASE 0xfdc60000 -+#define GRF_GPIO1B_IOMUX_H 0x0c -+#define GRF_GPIO1C_IOMUX_L 0x10 -+#define GRF_GPIO1C_IOMUX_H 0x14 -+#define GRF_GPIO1D_IOMUX_L 0x18 -+#define GRF_GPIO1D_IOMUX_H 0x1c -+#define GRF_GPIO2A_IOMUX_L 0x20 - #define GRF_GPIO1B_DS_2 0x218 - #define GRF_GPIO1B_DS_3 0x21c - #define GRF_GPIO1C_DS_0 0x220 - #define GRF_GPIO1C_DS_1 0x224 - #define GRF_GPIO1C_DS_2 0x228 - #define GRF_GPIO1C_DS_3 0x22c --#define SGRF_BASE 0xFDD18000 -+#define GRF_GPIO1D_DS_0 0x230 -+#define GRF_GPIO1D_DS_1 0x234 -+#define GRF_GPIO1D_DS_2 0x238 -+#define SGRF_BASE 0xfdd18000 -+#define SGRF_SOC_CON3 0x0c - #define SGRF_SOC_CON4 0x10 - #define EMMC_HPROT_SECURE_CTRL 0x03 - #define SDMMC0_HPROT_SECURE_CTRL 0x01 -@@ -133,6 +144,24 @@ int arch_cpu_init(void) - writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1); - writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2); - writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3); -+ -+ /* emmc, sfc, and sdmmc iomux */ -+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1B_IOMUX_H); -+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1C_IOMUX_L); -+ writel((0x7777UL << 16) | (0x2111), GRF_BASE + GRF_GPIO1C_IOMUX_H); -+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1D_IOMUX_L); -+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO1D_IOMUX_H); -+ writel((0x7777UL << 16) | (0x1111), GRF_BASE + GRF_GPIO2A_IOMUX_L); -+ -+ /* set the fspi d0~3 cs0 to level 2 */ -+ writel(0x3f000700, GRF_BASE + GRF_GPIO1C_DS_3); -+ writel(0x3f000700, GRF_BASE + GRF_GPIO1D_DS_0); -+ writel(0x3f3f0707, GRF_BASE + GRF_GPIO1D_DS_1); -+ writel(0x003f0007, GRF_BASE + GRF_GPIO1D_DS_2); -+ -+ /* Set the fspi to secure */ -+ writel(((0x1 << 14) << 16) | (0x0 << 14), SGRF_BASE + SGRF_SOC_CON3); -+ - #endif - return 0; - } -@@ -164,3 +193,26 @@ int ft_system_setup(void *blob, struct bd_info *bd) - return 0; - }; - #endif -+ -+#ifdef CONFIG_SPL_BUILD -+ -+void __weak led_setup(void) -+{ -+} -+ -+void spl_board_init(void) -+{ -+ led_setup(); -+ -+#if defined(SPL_DM_REGULATOR) -+ /* -+ * Turning the eMMC and SPI back on (if disabled via the Qseven -+ * BIOS_ENABLE) signal is done through a always-on regulator). -+ */ -+ if (regulators_enable_boot_on(false)) -+ debug("%s: Cannot enable boot on regulator\n", __func__); -+#endif -+ -+ setup_boot_mode(); -+} -+#endif diff --git a/5.4/package/boot/uboot-rockchip/patches/100-Convert-CONFIG_USB_OHCI_NEW-et-al-to-Kconfig.patch b/5.4/package/boot/uboot-rockchip/patches/100-Convert-CONFIG_USB_OHCI_NEW-et-al-to-Kconfig.patch deleted file mode 100644 index ff5a97f3..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/100-Convert-CONFIG_USB_OHCI_NEW-et-al-to-Kconfig.patch +++ /dev/null @@ -1,282 +0,0 @@ -From cd6a45a41fb2c19884ac87afade87b4d53601929 Mon Sep 17 00:00:00 2001 -From: Tom Rini -Date: Sat, 25 Jun 2022 11:02:31 -0400 -Subject: [PATCH] Convert CONFIG_USB_OHCI_NEW et al to Kconfig - -This converts the following to Kconfig: - CONFIG_SYS_OHCI_SWAP_REG_ACCESS - CONFIG_SYS_USB_OHCI_CPU_INIT - CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS - CONFIG_SYS_USB_OHCI_SLOT_NAME - CONFIG_USB_ATMEL - CONFIG_USB_ATMEL_CLK_SEL_PLLB - CONFIG_USB_ATMEL_CLK_SEL_UPLL - CONFIG_USB_OHCI_LPC32XX - CONFIG_USB_OHCI_NEW - -Signed-off-by: Tom Rini ---- - -diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig -index 4d6d235cb125..c81437300c74 100644 ---- a/configs/evb-rk3328_defconfig -+++ b/configs/evb-rk3328_defconfig -@@ -99,6 +99,7 @@ CONFIG_USB_EHCI_HCD=y - CONFIG_USB_EHCI_GENERIC=y - CONFIG_USB_OHCI_HCD=y - CONFIG_USB_OHCI_GENERIC=y -+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 - CONFIG_USB_DWC2=y - CONFIG_USB_DWC3=y - # CONFIG_USB_DWC3_GADGET is not set -diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig -index 41793ca7e486..15c2e1698c20 100644 ---- a/configs/nanopi-r2s-rk3328_defconfig -+++ b/configs/nanopi-r2s-rk3328_defconfig -@@ -102,6 +102,7 @@ CONFIG_USB_EHCI_HCD=y - CONFIG_USB_EHCI_GENERIC=y - CONFIG_USB_OHCI_HCD=y - CONFIG_USB_OHCI_GENERIC=y -+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 - CONFIG_USB_DWC2=y - CONFIG_USB_DWC3=y - # CONFIG_USB_DWC3_GADGET is not set -diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig -index ab25abc1a031..43b90c7879b7 100644 ---- a/configs/roc-cc-rk3328_defconfig -+++ b/configs/roc-cc-rk3328_defconfig -@@ -108,6 +108,7 @@ CONFIG_USB_EHCI_HCD=y - CONFIG_USB_EHCI_GENERIC=y - CONFIG_USB_OHCI_HCD=y - CONFIG_USB_OHCI_GENERIC=y -+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 - CONFIG_USB_DWC2=y - CONFIG_USB_DWC3=y - # CONFIG_USB_DWC3_GADGET is not set -diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig -index 1d51a267b93a..7d95e171f7f4 100644 ---- a/configs/rock-pi-e-rk3328_defconfig -+++ b/configs/rock-pi-e-rk3328_defconfig -@@ -109,6 +109,7 @@ CONFIG_USB_EHCI_HCD=y - CONFIG_USB_EHCI_GENERIC=y - CONFIG_USB_OHCI_HCD=y - CONFIG_USB_OHCI_GENERIC=y -+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 - CONFIG_USB_DWC2=y - CONFIG_USB_DWC3=y - # CONFIG_USB_DWC3_GADGET is not set -diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig -index 640fe558d414..bc333a5e2a6a 100644 ---- a/configs/rock64-rk3328_defconfig -+++ b/configs/rock64-rk3328_defconfig -@@ -106,6 +106,7 @@ CONFIG_USB_EHCI_HCD=y - CONFIG_USB_EHCI_GENERIC=y - CONFIG_USB_OHCI_HCD=y - CONFIG_USB_OHCI_GENERIC=y -+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 - CONFIG_USB_DWC2=y - CONFIG_USB_DWC3=y - # CONFIG_USB_DWC3_GADGET is not set -diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig -index 78e50dbfbcb7..bb5b2143691d 100644 ---- a/configs/rock960-rk3399_defconfig -+++ b/configs/rock960-rk3399_defconfig -@@ -74,6 +74,7 @@ CONFIG_USB_EHCI_HCD=y - CONFIG_USB_EHCI_GENERIC=y - CONFIG_USB_OHCI_HCD=y - CONFIG_USB_OHCI_GENERIC=y -+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 - CONFIG_USB_DWC3=y - CONFIG_USB_KEYBOARD=y - CONFIG_USB_HOST_ETHER=y -diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig -index 4d2a5b32e31c..ef28fe6a937a 100644 ---- a/configs/rockpro64-rk3399_defconfig -+++ b/configs/rockpro64-rk3399_defconfig -@@ -87,6 +87,7 @@ CONFIG_USB_EHCI_HCD=y - CONFIG_USB_EHCI_GENERIC=y - CONFIG_USB_OHCI_HCD=y - CONFIG_USB_OHCI_GENERIC=y -+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 - CONFIG_USB_DWC3=y - CONFIG_USB_DWC3_GENERIC=y - CONFIG_USB_KEYBOARD=y -diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig -index 0b82c2fdaf71..31ae9f74e7ac 100644 ---- a/drivers/usb/host/Kconfig -+++ b/drivers/usb/host/Kconfig -@@ -297,10 +297,17 @@ config USB_EHCI_TXFIFO_THRESH - Enables support for the on-chip EHCI controller on FSL chips. - endif # USB_EHCI_HCD - -+config USB_OHCI_NEW -+ bool -+ -+config SYS_USB_OHCI_CPU_INIT -+ bool -+ - config USB_OHCI_HCD - bool "OHCI HCD (USB 1.1) support" - depends on DM && OF_CONTROL - select USB_HOST -+ select USB_OHCI_NEW - ---help--- - The Open Host Controller Interface (OHCI) is a standard for accessing - USB 1.1 host controller hardware. It does more in hardware than Intel's -@@ -332,6 +339,19 @@ config USB_OHCI_DA8XX - - endif # USB_OHCI_HCD - -+config SYS_USB_OHCI_SLOT_NAME -+ string "Display name for the OHCI controller" -+ depends on USB_OHCI_NEW && !DM_USB -+ -+config SYS_USB_OHCI_MAX_ROOT_PORTS -+ int "Maximal number of ports of the root hub" -+ depends on USB_OHCI_NEW -+ default 1 if ARCH_SUNXI -+ -+config SYS_OHCI_SWAP_REG_ACCESS -+ bool "Perform byte swapping on OHCI controller register accesses" -+ depends on USB_OHCI_NEW -+ - config USB_UHCI_HCD - bool "UHCI HCD (most Intel and VIA) support" - select USB_HOST -@@ -381,3 +401,27 @@ config USB_R8A66597_HCD - ---help--- - This enables support for the on-chip Renesas R8A66597 USB 2.0 - controller, present in various RZ and SH SoCs. -+ -+config USB_ATMEL -+ bool "AT91 OHCI USB support" -+ depends on ARCH_AT91 -+ select SYS_USB_OHCI_CPU_INIT -+ select USB_OHCI_NEW -+ -+choice -+ prompt "Clock for OHCI" -+ depends on USB_ATMEL -+ -+config USB_ATMEL_CLK_SEL_PLLB -+ bool "PLLB" -+ -+config USB_ATMEL_CLK_SEL_UPLL -+ bool "UPLL" -+ -+endchoice -+ -+config USB_OHCI_LPC32XX -+ bool "LPC32xx USB OHCI support" -+ depends on ARCH_LPC32XX -+ select SYS_USB_OHCI_CPU_INIT -+ select USB_OHCI_NEW -diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c -index 8ceabaf45c1b..9b955c1bd678 100644 ---- a/drivers/usb/host/ohci-at91.c -+++ b/drivers/usb/host/ohci-at91.c -@@ -5,9 +5,6 @@ - */ - - #include -- --#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) -- - #include - - int usb_cpu_init(void) -@@ -65,5 +62,3 @@ int usb_cpu_init_fail(void) - { - return usb_cpu_stop(); - } -- --#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */ -diff --git a/drivers/usb/host/ohci-generic.c b/drivers/usb/host/ohci-generic.c -index 163f0ef17b11..5d23058aaf6a 100644 ---- a/drivers/usb/host/ohci-generic.c -+++ b/drivers/usb/host/ohci-generic.c -@@ -14,10 +14,6 @@ - #include - #include "ohci.h" - --#if !defined(CONFIG_USB_OHCI_NEW) --# error "Generic OHCI driver requires CONFIG_USB_OHCI_NEW" --#endif -- - struct generic_ohci { - ohci_t ohci; - struct clk *clocks; /* clock list */ -diff --git a/drivers/usb/host/ohci.h b/drivers/usb/host/ohci.h -index a38cd25eb85f..7699f2e6b15a 100644 ---- a/drivers/usb/host/ohci.h -+++ b/drivers/usb/host/ohci.h -@@ -151,7 +151,7 @@ struct ohci_hcca { - * Maximum number of root hub ports. - */ - #ifndef CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS --# error "CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS undefined!" -+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 - #endif - - /* -diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h -index 492b7b4df128..b7e850370b31 100644 ---- a/include/configs/evb_rk3399.h -+++ b/include/configs/evb_rk3399.h -@@ -15,7 +15,4 @@ - - #define SDRAM_BANK_SIZE (2UL << 30) - --#define CONFIG_USB_OHCI_NEW --#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -- - #endif -diff --git a/include/configs/gru.h b/include/configs/gru.h -index b1084bb21d4d..be2dc79968c0 100644 ---- a/include/configs/gru.h -+++ b/include/configs/gru.h -@@ -13,7 +13,4 @@ - - #include - --#define CONFIG_USB_OHCI_NEW --#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -- - #endif -diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h -index 90183579202d..165b78ff3309 100644 ---- a/include/configs/rk3328_common.h -+++ b/include/configs/rk3328_common.h -@@ -30,8 +30,4 @@ - "partitions=" PARTS_DEFAULT \ - BOOTENV - --/* rockchip ohci host driver */ --#define CONFIG_USB_OHCI_NEW --#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 -- - #endif -diff --git a/include/configs/rock960_rk3399.h b/include/configs/rock960_rk3399.h -index 2edad710284f..6099d2fa55a6 100644 ---- a/include/configs/rock960_rk3399.h -+++ b/include/configs/rock960_rk3399.h -@@ -14,7 +14,4 @@ - #include - - #define SDRAM_BANK_SIZE (2UL << 30) -- --#define CONFIG_USB_OHCI_NEW --#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - #endif -diff --git a/include/configs/rockpro64_rk3399.h b/include/configs/rockpro64_rk3399.h -index 903e9df527c1..9195b9b99e41 100644 ---- a/include/configs/rockpro64_rk3399.h -+++ b/include/configs/rockpro64_rk3399.h -@@ -14,7 +14,4 @@ - #include - - #define SDRAM_BANK_SIZE (2UL << 30) -- --#define CONFIG_USB_OHCI_NEW --#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - #endif diff --git a/5.4/package/boot/uboot-rockchip/patches/104-mkimage-add-public-key-for-image.patch b/5.4/package/boot/uboot-rockchip/patches/104-mkimage-add-public-key-for-image.patch deleted file mode 100644 index 8c8e79cf..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/104-mkimage-add-public-key-for-image.patch +++ /dev/null @@ -1,166 +0,0 @@ ---- a/include/image.h -+++ b/include/image.h -@@ -1020,21 +1020,6 @@ int fit_image_hash_get_value(const void - - int fit_set_timestamp(void *fit, int noffset, time_t timestamp); - --/** -- * fit_pre_load_data() - add public key to fdt blob -- * -- * Adds public key to the node pre load. -- * -- * @keydir: Directory containing keys -- * @keydest: FDT blob to write public key -- * @fit: Pointer to the FIT format image header -- * -- * returns: -- * 0, on success -- * < 0, on failure -- */ --int fit_pre_load_data(const char *keydir, void *keydest, void *fit); -- - int fit_cipher_data(const char *keydir, void *keydest, void *fit, - const char *comment, int require_keys, - const char *engine_id, const char *cmdname); ---- a/tools/fit_image.c -+++ b/tools/fit_image.c -@@ -59,9 +59,6 @@ static int fit_add_file_data(struct imag - ret = fit_set_timestamp(ptr, 0, time); - } - -- if (!ret) -- ret = fit_pre_load_data(params->keydir, dest_blob, ptr); -- - if (!ret) { - ret = fit_cipher_data(params->keydir, dest_blob, ptr, - params->comment, ---- a/tools/image-host.c -+++ b/tools/image-host.c -@@ -14,11 +14,6 @@ - #include - #include - --#include --#include -- --#define IMAGE_PRE_LOAD_PATH "/image/pre-load/sig" -- - /** - * fit_set_hash_value - set hash value in requested has node - * @fit: pointer to the FIT format image header -@@ -1116,115 +1111,6 @@ static int fit_config_add_verification_d - return 0; - } - --/* -- * 0) open file (open) -- * 1) read certificate (PEM_read_X509) -- * 2) get public key (X509_get_pubkey) -- * 3) provide der format (d2i_RSAPublicKey) -- */ --static int read_pub_key(const char *keydir, const void *name, -- unsigned char **pubkey, int *pubkey_len) --{ -- char path[1024]; -- EVP_PKEY *key = NULL; -- X509 *cert; -- FILE *f; -- int ret; -- -- memset(path, 0, 1024); -- snprintf(path, sizeof(path), "%s/%s.crt", keydir, (char *)name); -- -- /* Open certificate file */ -- f = fopen(path, "r"); -- if (!f) { -- fprintf(stderr, "Couldn't open RSA certificate: '%s': %s\n", -- path, strerror(errno)); -- return -EACCES; -- } -- -- /* Read the certificate */ -- cert = NULL; -- if (!PEM_read_X509(f, &cert, NULL, NULL)) { -- printf("Couldn't read certificate"); -- ret = -EINVAL; -- goto err_cert; -- } -- -- /* Get the public key from the certificate. */ -- key = X509_get_pubkey(cert); -- if (!key) { -- printf("Couldn't read public key\n"); -- ret = -EINVAL; -- goto err_pubkey; -- } -- -- /* Get DER form */ -- ret = i2d_PublicKey(key, pubkey); -- if (ret < 0) { -- printf("Couldn't get DER form\n"); -- ret = -EINVAL; -- goto err_pubkey; -- } -- -- *pubkey_len = ret; -- ret = 0; -- --err_pubkey: -- X509_free(cert); --err_cert: -- fclose(f); -- return ret; --} -- --int fit_pre_load_data(const char *keydir, void *keydest, void *fit) --{ -- int pre_load_noffset; -- const void *algo_name; -- const void *key_name; -- unsigned char *pubkey = NULL; -- int ret, pubkey_len; -- -- if (!keydir || !keydest || !fit) -- return 0; -- -- /* Search node pre-load sig */ -- pre_load_noffset = fdt_path_offset(keydest, IMAGE_PRE_LOAD_PATH); -- if (pre_load_noffset < 0) { -- ret = 0; -- goto out; -- } -- -- algo_name = fdt_getprop(keydest, pre_load_noffset, "algo-name", NULL); -- key_name = fdt_getprop(keydest, pre_load_noffset, "key-name", NULL); -- -- /* Check that all mandatory properties are present */ -- if (!algo_name || !key_name) { -- if (!algo_name) -- printf("The property algo-name is missing in the node %s\n", -- IMAGE_PRE_LOAD_PATH); -- if (!key_name) -- printf("The property key-name is missing in the node %s\n", -- IMAGE_PRE_LOAD_PATH); -- ret = -EINVAL; -- goto out; -- } -- -- /* Read public key */ -- ret = read_pub_key(keydir, key_name, &pubkey, &pubkey_len); -- if (ret < 0) -- goto out; -- -- /* Add the public key to the device tree */ -- ret = fdt_setprop(keydest, pre_load_noffset, "public-key", -- pubkey, pubkey_len); -- if (ret) -- printf("Can't set public-key in node %s (ret = %d)\n", -- IMAGE_PRE_LOAD_PATH, ret); -- -- out: -- return ret; --} -- - int fit_cipher_data(const char *keydir, void *keydest, void *fit, - const char *comment, int require_keys, - const char *engine_id, const char *cmdname) diff --git a/5.4/package/boot/uboot-rockchip/patches/105-Only-build-dtc-if-needed.patch b/5.4/package/boot/uboot-rockchip/patches/105-Only-build-dtc-if-needed.patch deleted file mode 100644 index ad040770..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/105-Only-build-dtc-if-needed.patch +++ /dev/null @@ -1,125 +0,0 @@ ---- a/Makefile -+++ b/Makefile -@@ -413,13 +413,7 @@ PERL = perl - PYTHON ?= python - PYTHON2 = python2 - PYTHON3 ?= python3 -- --# The devicetree compiler and pylibfdt are automatically built unless DTC is --# provided. If DTC is provided, it is assumed the pylibfdt is available too. --DTC_INTREE := $(objtree)/scripts/dtc/dtc --DTC ?= $(DTC_INTREE) --DTC_MIN_VERSION := 010406 -- -+DTC ?= $(objtree)/scripts/dtc/dtc - CHECK = sparse - - CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \ -@@ -2070,29 +2064,9 @@ endif - - endif - --# Check dtc and pylibfdt, if DTC is provided, else build them - PHONY += scripts_dtc - scripts_dtc: scripts_basic -- $(Q)if test "$(DTC)" = "$(DTC_INTREE)"; then \ -- $(MAKE) $(build)=scripts/dtc; \ -- else \ -- if ! $(DTC) -v >/dev/null; then \ -- echo '*** Failed to check dtc version: $(DTC)'; \ -- false; \ -- else \ -- if test "$(call dtc-version)" -lt $(DTC_MIN_VERSION); then \ -- echo '*** Your dtc is too old, please upgrade to dtc $(DTC_MIN_VERSION) or newer'; \ -- false; \ -- else \ -- if [ -n "$(CONFIG_PYLIBFDT)" ]; then \ -- if ! echo "import libfdt" | $(PYTHON3) 2>/dev/null; then \ -- echo '*** pylibfdt does not seem to be available with $(PYTHON3)'; \ -- false; \ -- fi; \ -- fi; \ -- fi; \ -- fi; \ -- fi -+ $(Q)$(MAKE) $(build)=scripts/dtc - - # --------------------------------------------------------------------------- - quiet_cmd_cpp_lds = LDS $@ ---- a/doc/build/gcc.rst -+++ b/doc/build/gcc.rst -@@ -131,27 +131,6 @@ Further important build parameters are - * O= - generate all output files in directory , including .config - * V=1 - verbose build - --Devicetree compiler --~~~~~~~~~~~~~~~~~~~ -- --Boards that use `CONFIG_OF_CONTROL` (i.e. almost all of them) need the --devicetree compiler (dtc). Those with `CONFIG_PYLIBFDT` need pylibfdt, a Python --library for accessing devicetree data. Suitable versions of these are included --in the U-Boot tree in `scripts/dtc` and built automatically as needed. -- --To use the system versions of these, use the DTC parameter, for example -- --.. code-block:: bash -- -- DTC=/usr/bin/dtc make -- --In this case, dtc and pylibfdt are not built. The build checks that the version --of dtc is new enough. It also makes sure that pylibfdt is present, if needed --(see `scripts_dtc` in the Makefile). -- --Note that the :doc:`tools` are always built with the included version of libfdt --so it is not possible to build U-Boot tools with a system libfdt, at present. -- - Other build targets - ~~~~~~~~~~~~~~~~~~~ - ---- a/dts/Kconfig -+++ b/dts/Kconfig -@@ -5,6 +5,9 @@ - config SUPPORT_OF_CONTROL - bool - -+config DTC -+ bool -+ - config PYLIBFDT - bool - -@@ -21,6 +24,7 @@ menu "Device Tree Control" - - config OF_CONTROL - bool "Run-time configuration via Device Tree" -+ select DTC - select OF_LIBFDT if !OF_PLATDATA - select OF_REAL if !OF_PLATDATA - help ---- a/scripts/Makefile -+++ b/scripts/Makefile -@@ -10,3 +10,4 @@ always := $(hostprogs-y) - - # Let clean descend into subdirs - subdir- += basic kconfig dtc -+subdir-$(CONFIG_DTC) += dtc ---- a/scripts/dtc-version.sh -+++ b/scripts/dtc-version.sh -@@ -10,16 +10,11 @@ - dtc="$*" - - if [ ${#dtc} -eq 0 ]; then -- echo "Error: No dtc command specified" -+ echo "Error: No dtc command specified." - printf "Usage:\n\t$0 \n" - exit 1 - fi - --if ! which $dtc >/dev/null ; then -- echo "Error: Cannot find dtc: $dtc" -- exit 1 --fi -- - MAJOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 1) - MINOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 2) - PATCH=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 3 | cut -d - -f 1) diff --git a/5.4/package/boot/uboot-rockchip/patches/106-no-kwbimage.patch b/5.4/package/boot/uboot-rockchip/patches/106-no-kwbimage.patch deleted file mode 100644 index 65d14f5b..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/106-no-kwbimage.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/tools/Makefile -+++ b/tools/Makefile -@@ -119,7 +119,6 @@ dumpimage-mkimage-objs := aisimage.o \ - imximage.o \ - imx8image.o \ - imx8mimage.o \ -- kwbimage.o \ - lib/md5.o \ - lpc32xximage.o \ - mxsimage.o \ diff --git a/5.4/package/boot/uboot-rockchip/patches/203-rock64pro-disable-CONFIG_USE_PREBOOT.patch b/5.4/package/boot/uboot-rockchip/patches/203-rock64pro-disable-CONFIG_USE_PREBOOT.patch deleted file mode 100644 index f6308183..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/203-rock64pro-disable-CONFIG_USE_PREBOOT.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 2114d68b3c755ec8043ae9e43ac8e9753e0cec84 Mon Sep 17 00:00:00 2001 -From: Marty Jones -Date: Sun, 17 Jan 2021 15:26:09 -0500 -Subject: [PATCH] rockpro64: disable CONFIG_USE_PREBOOT - -On commit https://github.com/u-boot/u-boot/commit/f81f9f0ebac596bae7f27db095f4f0272b606cc3 -CONFIG_USE_PREBOOT was enabled on the RockPro64. - -When the board is booting, U-Boot hangs as soon as it disables the USB -controller. This is a workaround until a final solution is deployed -upstream. - -Signed-off-by: Marty Jones ---- - configs/rockpro64-rk3399_defconfig | 1 - - 1 file changed, 1 deletion(-) - ---- a/configs/rockpro64-rk3399_defconfig -+++ b/configs/rockpro64-rk3399_defconfig -@@ -12,7 +12,6 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y - CONFIG_SPL_SPI_SUPPORT=y - CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64" - CONFIG_DEBUG_UART=y --CONFIG_USE_PREBOOT=y - CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb" - CONFIG_DISPLAY_BOARDINFO_LATE=y - CONFIG_MISC_INIT_R=y diff --git a/5.4/package/boot/uboot-rockchip/patches/301-arm64-dts-rockchip-Add-GuangMiao-G4C-support.patch b/5.4/package/boot/uboot-rockchip/patches/301-arm64-dts-rockchip-Add-GuangMiao-G4C-support.patch deleted file mode 100644 index fae269b7..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/301-arm64-dts-rockchip-Add-GuangMiao-G4C-support.patch +++ /dev/null @@ -1,740 +0,0 @@ ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -124,6 +124,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ - rk3399-ficus.dtb \ - rk3399-firefly.dtb \ - rk3399-gru-bob.dtb \ -+ rk3399-guangmiao-g4c.dtb \ - rk3399-gru-kevin.dtb \ - rk3399-khadas-edge.dtb \ - rk3399-khadas-edge-captain.dtb \ ---- /dev/null -+++ b/configs/guangmiao-g4c-rk3399_defconfig -@@ -0,0 +1,57 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_ROCKCHIP_RK3399=y -+CONFIG_TARGET_EVB_RK3399=y -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_SYS_LOAD_ADDR=0x800800 -+CONFIG_DEBUG_UART_BASE=0xFF1A0000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEBUG_UART=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-guangmiao-g4c.dtb" -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 -+CONFIG_TPL=y -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TIME=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_DEFAULT_DEVICE_TREE="rk3399-guangmiao-g4c" -+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM_RK3399_LPDDR4=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_HOST_ETHER=y -+CONFIG_USB_ETHER_ASIX=y -+CONFIG_USB_ETHER_ASIX88179=y -+CONFIG_USB_ETHER_MCS7830=y -+CONFIG_USB_ETHER_RTL8152=y -+CONFIG_USB_ETHER_SMSC95XX=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_ERRNO_STR=y ---- /dev/null -+++ b/arch/arm/dts/rk3399-guangmiao-g4c-u-boot.dtsi -@@ -0,0 +1,18 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+#include "rk3399-u-boot.dtsi" -+#include "rk3399-sdram-lpddr4-100.dtsi" -+ -+/ { -+ chosen { -+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; -+ }; -+}; -+ -+&sdmmc { -+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>; -+}; -+ -+&vdd_log { -+ regulator-init-microvolt = <950000>; -+}; ---- /dev/null -+++ b/arch/arm/dts/rk3399-guangmiao-g4c.dts -@@ -0,0 +1,646 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+#include -+#include "rk3399.dtsi" -+#include "rk3399-opp.dtsi" -+ -+/ { -+ model = "SHAREVDI GuangMiao G4C"; -+ compatible = "sharevdi,guangmiao-g4c", "rockchip,rk3399"; -+ -+ /delete-node/ display-subsystem; -+ -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ clkin_gmac: external-gmac-clock { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ clock-output-names = "clkin_gmac"; -+ #clock-cells = <0>; -+ }; -+ -+ vcc_sys: vcc-sys { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-name = "vcc_sys"; -+ }; -+ -+ vcc3v3_sys: vcc3v3-sys { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc3v3_sys"; -+ vin-supply = <&vcc_sys>; -+ }; -+ -+ vcc_0v9: vcc-0v9 { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ regulator-name = "vcc_0v9"; -+ vin-supply = <&vcc3v3_sys>; -+ }; -+ -+ vcc5v0_host0: vcc5v0-host0 { -+ compatible = "regulator-fixed"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vcc5v0_host0"; -+ vin-supply = <&vcc_sys>; -+ }; -+ -+ vdd_log: vdd-log { -+ compatible = "pwm-regulator"; -+ pwms = <&pwm2 0 25000 1>; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-name = "vdd_log"; -+ vin-supply = <&vcc_sys>; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ autorepeat; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&reset_button_pin>; -+ -+ reset { -+ debounce-interval = <100>; -+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; -+ label = "reset"; -+ linux,code = ; -+ wakeup-source; -+ }; -+ }; -+ -+ gpio-leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&lan_led_pin>, <&status_led_pin>, <&wan_led_pin>; -+ -+ lan_led: led-lan { -+ gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; -+ label = "green:lan"; -+ }; -+ -+ status_led: led-status { -+ gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; -+ label = "green:status"; -+ }; -+ -+ wan_led: led-wan { -+ gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; -+ label = "green:wan"; -+ }; -+ }; -+}; -+ -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&emmc_phy { -+ status = "okay"; -+}; -+ -+&gmac { -+ assigned-clock-parents = <&clkin_gmac>; -+ assigned-clocks = <&cru SCLK_RMII_SRC>; -+ clock_in_out = "input"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_pmeb>, <&phy_rstb>; -+ phy-handle = <&rtl8211e>; -+ phy-mode = "rgmii"; -+ phy-supply = <&vcc3v3_s3>; -+ tx_delay = <0x28>; -+ rx_delay = <0x11>; -+ status = "okay"; -+ -+ mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ rtl8211e: ethernet-phy@1 { -+ reg = <1>; -+ interrupt-parent = <&gpio3>; -+ interrupts = ; -+ reset-assert-us = <10000>; -+ reset-deassert-us = <30000>; -+ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ -+&i2c0 { -+ clock-frequency = <400000>; -+ i2c-scl-rising-time-ns = <160>; -+ i2c-scl-falling-time-ns = <30>; -+ status = "okay"; -+ -+ vdd_cpu_b: regulator@40 { -+ compatible = "silergy,syr827"; -+ reg = <0x40>; -+ fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&cpu_b_sleep>; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-name = "vdd_cpu_b"; -+ regulator-ramp-delay = <1000>; -+ vin-supply = <&vcc_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: regulator@41 { -+ compatible = "silergy,syr828"; -+ reg = <0x41>; -+ fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gpu_sleep>; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-name = "vdd_gpu"; -+ regulator-ramp-delay = <1000>; -+ vin-supply = <&vcc_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ rk808: pmic@1b { -+ compatible = "rockchip,rk808"; -+ reg = <0x1b>; -+ clock-output-names = "rtc_clko_soc", "rtc_clko_wifi"; -+ #clock-cells = <1>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int_l>; -+ rockchip,system-power-controller; -+ wakeup-source; -+ -+ vcc1-supply = <&vcc_sys>; -+ vcc2-supply = <&vcc_sys>; -+ vcc3-supply = <&vcc_sys>; -+ vcc4-supply = <&vcc_sys>; -+ vcc6-supply = <&vcc_sys>; -+ vcc7-supply = <&vcc_sys>; -+ vcc8-supply = <&vcc_3v0>; -+ vcc9-supply = <&vcc_sys>; -+ vcc10-supply = <&vcc_sys>; -+ vcc11-supply = <&vcc_sys>; -+ vcc12-supply = <&vcc_sys>; -+ vddio-supply = <&vcc_3v0>; -+ -+ regulators { -+ vdd_center: DCDC_REG1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-name = "vdd_center"; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_l: DCDC_REG2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-name = "vdd_cpu_l"; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vcc_ddr"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: DCDC_REG4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc_1v8"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc_vldo1: LDO_REG1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc_vldo1"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_vldo2: LDO_REG2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcc_vldo2"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcca_1v8: LDO_REG3 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcca_1v8"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc_sdio: LDO_REG4 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-name = "vcc_sdio"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcc3v0_sd: LDO_REG5 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-name = "vcc3v0_sd"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ -+ vcc_1v5: LDO_REG6 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <1500000>; -+ regulator-name = "vcc_1v5"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1500000>; -+ }; -+ }; -+ -+ vcca1v8_codec: LDO_REG7 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-name = "vcca1v8_codec"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v0: LDO_REG8 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ regulator-name = "vcc_3v0"; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ -+ vcc3v3_s3: SWITCH_REG1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vcc3v3_s3"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_s0: SWITCH_REG2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vcc3v3_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&i2c3 { -+ i2c-scl-rising-time-ns = <450>; -+ i2c-scl-falling-time-ns = <15>; -+ status = "okay"; -+}; -+ -+&io_domains { -+ bt656-supply = <&vcc_1v8>; -+ audio-supply = <&vcca1v8_codec>; -+ sdmmc-supply = <&vcc_sdio>; -+ gpio1830-supply = <&vcc_3v0>; -+ status = "okay"; -+}; -+ -+&pcie_phy { -+ assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; -+ assigned-clock-rates = <100000000>; -+ assigned-clocks = <&cru SCLK_PCIEPHY_REF>; -+ status = "okay"; -+}; -+ -+&pcie0 { -+ ep-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; -+ max-link-speed = <1>; -+ num-lanes = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_clkreqnb_cpm>; -+ vpcie0v9-supply = <&vcc_0v9>; -+ vpcie1v8-supply = <&vcca_1v8>; -+ vpcie3v3-supply = <&vcc3v3_sys>; -+ status = "okay"; -+}; -+ -+&pinctrl { -+ gpio-leds { -+ lan_led_pin: lan-led-pin { -+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ status_led_pin: status-led-pin { -+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ wan_led_pin: wan-led-pin { -+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ gmac { -+ phy_intb: phy-intb { -+ rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ phy_pmeb: phy-pmeb { -+ rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ phy_rstb: phy-rstb { -+ rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pmic { -+ cpu_b_sleep: cpu-b-sleep { -+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ gpu_sleep: gpu-sleep { -+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ rockchip-key { -+ reset_button_pin: reset-button-pin { -+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ sdio { -+ bt_reg_on_h: bt-reg-on-h { -+ /* external pullup to VCC1V8_PMUPLL */ -+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ sdmmc { -+ sdmmc0_det_l: sdmmc0-det-l { -+ rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; -+ -+&pmu_io_domains { -+ pmu1830-supply = <&vcc_3v0>; -+ status = "okay"; -+}; -+ -+&pwm0 { -+ status = "okay"; -+}; -+ -+&pwm1 { -+ status = "okay"; -+}; -+ -+&pwm2 { -+ pinctrl-names = "active"; -+ pinctrl-0 = <&pwm2_pin_pull_down>; -+ status = "okay"; -+}; -+ -+&saradc { -+ vref-supply = <&vcc_1v8>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ mmc-hs200-1_8v; -+ non-removable; -+ status = "okay"; -+}; -+ -+&sdmmc { -+ bus-width = <4>; -+ cap-mmc-highspeed; -+ cap-sd-highspeed; -+ cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; -+ disable-wp; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>; -+ vqmmc-supply = <&vcc_sdio>; -+ status = "okay"; -+}; -+ -+&tcphy0 { -+ status = "okay"; -+}; -+ -+&tcphy1 { -+ status = "okay"; -+}; -+ -+&tsadc { -+ rockchip,hw-tshut-mode = <1>; -+ rockchip,hw-tshut-polarity = <1>; -+ status = "okay"; -+}; -+ -+&u2phy0 { -+ status = "okay"; -+}; -+ -+&u2phy0_host { -+ phy-supply = <&vcc5v0_host0>; -+ status = "okay"; -+}; -+ -+&u2phy0_otg { -+ status = "okay"; -+}; -+ -+&u2phy1 { -+ status = "okay"; -+}; -+ -+&u2phy1_host { -+ phy-supply = <&vcc5v0_host0>; -+ status = "okay"; -+}; -+ -+&u2phy1_otg { -+ status = "okay"; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&usbdrd3_0 { -+ status = "okay"; -+}; -+ -+&usbdrd3_1 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3_0 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3_1 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; -+ -+&vopb { -+ status = "okay"; -+}; -+ -+&vopb_mmu { -+ status = "okay"; -+}; -+ -+&vopl { -+ status = "okay"; -+}; -+ -+&vopl_mmu { -+ status = "okay"; -+}; diff --git a/5.4/package/boot/uboot-rockchip/patches/302-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus.patch b/5.4/package/boot/uboot-rockchip/patches/302-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus.patch deleted file mode 100644 index d7940c96..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/302-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus.patch +++ /dev/null @@ -1,174 +0,0 @@ ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -109,6 +109,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ - dtb-$(CONFIG_ROCKCHIP_RK3328) += \ - rk3328-evb.dtb \ - rk3328-nanopi-r2s.dtb \ -+ rk3328-orangepi-r1-plus.dtb \ - rk3328-roc-cc.dtb \ - rk3328-rock64.dtb \ - rk3328-rock-pi-e.dtb ---- /dev/null -+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi -@@ -0,0 +1,1 @@ -+#include "rk3328-nanopi-r2s-u-boot.dtsi" ---- /dev/null -+++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts -@@ -0,0 +1,38 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+#include "rk3328-nanopi-r2s.dts" -+ -+/ { -+ model = "Xunlong Orange Pi R1 Plus"; -+ compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328"; -+}; -+ -+&lan_led { -+ label = "orangepi-r1-plus:green:lan"; -+}; -+ -+&spi0 { -+ status = "okay"; -+ -+ flash@0 { -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <10000000>; -+ }; -+}; -+ -+&sys_led { -+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; -+ label = "orangepi-r1-plus:red:sys"; -+}; -+ -+&sys_led_pin { -+ rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; -+}; -+ -+&uart1 { -+ status = "okay"; -+}; -+ -+&wan_led { -+ label = "orangepi-r1-plus:green:wan"; -+}; ---- a/board/rockchip/evb_rk3328/MAINTAINERS -+++ b/board/rockchip/evb_rk3328/MAINTAINERS -@@ -12,6 +12,13 @@ F: configs/nanopi-r2s-rk3328_defconfig - F: arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi - F: arch/arm/dts/rk3328-nanopi-r2s.dts - -+ORANGEPI-R1-PLUS-RK3328 -+M: Shenzhen Xunlong Software CO.,Limited -+S: Maintained -+F: configs/orangepi-r1-plus-rk3328_defconfig -+F: arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi -+F: arch/arm/dts/rk3328-orangepi-r1-plus.dts -+ - ROC-RK3328-CC - M: Loic Devulder - M: Chen-Yu Tsai ---- /dev/null -+++ b/configs/orangepi-r1-plus-rk3328_defconfig -@@ -0,0 +1,100 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_SPL_GPIO_SUPPORT=y -+CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_ROCKCHIP_RK3328=y -+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_TPL_LIBCOMMON_SUPPORT=y -+CONFIG_TPL_LIBGENERIC_SUPPORT=y -+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_SYS_LOAD_ADDR=0x800800 -+CONFIG_DEBUG_UART_BASE=0xFF130000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SYSINFO=y -+CONFIG_DEBUG_UART=y -+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 -+# CONFIG_ANDROID_BOOT_IMAGE is not set -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb" -+CONFIG_MISC_INIT_R=y -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_TPL_SYS_MALLOC_SIMPLE=y -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_I2C_SUPPORT=y -+CONFIG_SPL_POWER_SUPPORT=y -+CONFIG_SPL_ATF=y -+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TIME=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_TPL_OF_CONTROL=y -+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus" -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_TPL_OF_PLATDATA=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_TPL_DM=y -+CONFIG_REGMAP=y -+CONFIG_SPL_REGMAP=y -+CONFIG_TPL_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_SPL_SYSCON=y -+CONFIG_TPL_SYSCON=y -+CONFIG_CLK=y -+CONFIG_SPL_CLK=y -+CONFIG_FASTBOOT_BUF_ADDR=0x800800 -+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_SF_DEFAULT_SPEED=20000000 -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PINCTRL=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_DM_REGULATOR=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_SPL_DM_REGULATOR_FIXED=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM=y -+CONFIG_SPL_RAM=y -+CONFIG_TPL_RAM=y -+CONFIG_DM_RESET=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSRESET=y -+# CONFIG_TPL_SYSRESET is not set -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 -+CONFIG_USB_DWC2=y -+CONFIG_USB_DWC3=y -+# CONFIG_USB_DWC3_GADGET is not set -+CONFIG_USB_GADGET=y -+CONFIG_USB_GADGET_DWC2_OTG=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_TPL_TINY_MEMSET=y -+CONFIG_ERRNO_STR=y diff --git a/5.4/package/boot/uboot-rockchip/patches/303-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus-LTS.patch b/5.4/package/boot/uboot-rockchip/patches/303-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus-LTS.patch deleted file mode 100644 index 0f3f17f7..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/303-rockchip-rk3328-Add-support-for-Orangepi-R1-Plus-LTS.patch +++ /dev/null @@ -1,146 +0,0 @@ -From 68836b81f7d6328a1a5a6cce5a00bf4010f742e5 Mon Sep 17 00:00:00 2001 -From: baiywt -Date: Wed, 24 Nov 2021 19:59:38 +0800 -Subject: [PATCH] Add support for Orangepi R1 Plus LTS - ---- - arch/arm/dts/Makefile | 1 + - arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts | 7 ++ - configs/orangepi-r1-plus-lts-rk3328_defconfig | 98 +++++++++++++++++++ - 3 files changed, 106 insertions(+) - create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts - create mode 100644 configs/orangepi-r1-plus-lts-rk3328_defconfig - -diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index adfe6c3f..3d4e0f59 100644 ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -110,6 +110,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \ - rk3328-evb.dtb \ - rk3328-nanopi-r2s.dtb \ - rk3328-orangepi-r1-plus.dtb \ -+ rk3328-orangepi-r1-plus-lts.dtb \ - rk3328-roc-cc.dtb \ - rk3328-rock64.dtb \ - rk3328-rock-pi-e.dtb -diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts -new file mode 100644 -index 00000000..e6225b0c ---- /dev/null -+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts -@@ -0,0 +1,7 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+#include "rk3328-orangepi-r1-plus.dts" -+ -+/ { -+ model = "Xunlong Orange Pi R1 Plus LTS"; -+ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328"; -+}; -diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig b/configs/orangepi-r1-plus-lts-rk3328_defconfig -new file mode 100644 -index 00000000..3cb3b5c3 ---- /dev/null -+++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig -@@ -0,0 +1,100 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_SPL_GPIO_SUPPORT=y -+CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_ROCKCHIP_RK3328=y -+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_TPL_LIBCOMMON_SUPPORT=y -+CONFIG_TPL_LIBGENERIC_SUPPORT=y -+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_DEBUG_UART_BASE=0xFF130000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SYSINFO=y -+CONFIG_SYS_LOAD_ADDR=0x800800 -+CONFIG_DEBUG_UART=y -+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 -+# CONFIG_ANDROID_BOOT_IMAGE is not set -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb" -+CONFIG_MISC_INIT_R=y -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_TPL_SYS_MALLOC_SIMPLE=y -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_I2C_SUPPORT=y -+CONFIG_SPL_POWER_SUPPORT=y -+CONFIG_SPL_ATF=y -+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TIME=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_TPL_OF_CONTROL=y -+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts" -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_TPL_OF_PLATDATA=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_TPL_DM=y -+CONFIG_REGMAP=y -+CONFIG_SPL_REGMAP=y -+CONFIG_TPL_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_SPL_SYSCON=y -+CONFIG_TPL_SYSCON=y -+CONFIG_CLK=y -+CONFIG_SPL_CLK=y -+CONFIG_FASTBOOT_BUF_ADDR=0x800800 -+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_SF_DEFAULT_SPEED=20000000 -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PINCTRL=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_DM_REGULATOR=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_SPL_DM_REGULATOR_FIXED=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM=y -+CONFIG_SPL_RAM=y -+CONFIG_TPL_RAM=y -+CONFIG_DM_RESET=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSRESET=y -+# CONFIG_TPL_SYSRESET is not set -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 -+CONFIG_USB_DWC2=y -+CONFIG_USB_DWC3=y -+# CONFIG_USB_DWC3_GADGET is not set -+CONFIG_USB_GADGET=y -+CONFIG_USB_GADGET_DWC2_OTG=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_TPL_TINY_MEMSET=y -+CONFIG_ERRNO_STR=y --- -2.25.1 diff --git a/5.4/package/boot/uboot-rockchip/patches/304-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch b/5.4/package/boot/uboot-rockchip/patches/304-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch deleted file mode 100644 index 39022fdd..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/304-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch +++ /dev/null @@ -1,184 +0,0 @@ -diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index d3e89ca3ba..d5f64ac432 100644 ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -108,6 +108,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \ - - dtb-$(CONFIG_ROCKCHIP_RK3328) += \ - rk3328-evb.dtb \ -+ rk3328-nanopi-r2c.dtb \ - rk3328-nanopi-r2s.dtb \ - rk3328-orangepi-r1-plus.dtb \ - rk3328-roc-cc.dtb \ -diff --git a/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi -new file mode 100644 -index 0000000000..c2e86d0f0e ---- /dev/null -+++ b/arch/arm/dts/rk3328-nanopi-r2c-u-boot.dtsi -@@ -0,0 +1,7 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd -+ * (C) Copyright 2021 Tianling Shen -+ */ -+ -+#include "rk3328-nanopi-r2s-u-boot.dtsi" -diff --git a/arch/arm/dts/rk3328-nanopi-r2c.dts b/arch/arm/dts/rk3328-nanopi-r2c.dts -new file mode 100644 -index 0000000000..adf91a0306 ---- /dev/null -+++ b/arch/arm/dts/rk3328-nanopi-r2c.dts -@@ -0,0 +1,47 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. -+ * (http://www.friendlyarm.com) -+ * -+ * Copyright (c) 2021 Tianling Shen -+ */ -+ -+/dts-v1/; -+ -+#include "rk3328-nanopi-r2s.dts" -+ -+/ { -+ model = "FriendlyElec NanoPi R2C"; -+ compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328"; -+}; -+ -+&gmac2io { -+ phy-handle = <&yt8521s>; -+ -+ mdio { -+ /delete-node/ ethernet-phy@1; -+ -+ yt8521s: ethernet-phy@3 { -+ compatible = "ethernet-phy-id0000.011a", -+ "ethernet-phy-ieee802.3-c22"; -+ reg = <3>; -+ pinctrl-0 = <ð_phy_reset_pin>; -+ pinctrl-names = "default"; -+ reset-assert-us = <10000>; -+ reset-deassert-us = <50000>; -+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; -+ -+&lan_led { -+ label = "nanopi-r2c:green:lan"; -+}; -+ -+&sys_led { -+ label = "nanopi-r2c:red:sys"; -+}; -+ -+&wan_led { -+ label = "nanopi-r2c:green:wan"; -+}; -diff --git a/configs/nanopi-r2c-rk3328_defconfig b/configs/nanopi-r2c-rk3328_defconfig -new file mode 100644 -index 0000000000..7bc7a3274f ---- /dev/null -+++ b/configs/nanopi-r2c-rk3328_defconfig -@@ -0,0 +1,100 @@ -+CONFIG_ARM=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_SPL_GPIO_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2c" -+CONFIG_ROCKCHIP_RK3328=y -+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_TPL_LIBCOMMON_SUPPORT=y -+CONFIG_TPL_LIBGENERIC_SUPPORT=y -+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_DEBUG_UART_BASE=0xFF130000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SYS_LOAD_ADDR=0x800800 -+CONFIG_DEBUG_UART=y -+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 -+# CONFIG_ANDROID_BOOT_IMAGE is not set -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb" -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_MISC_INIT_R=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_TPL_SYS_MALLOC_SIMPLE=y -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_I2C_SUPPORT=y -+CONFIG_SPL_POWER_SUPPORT=y -+CONFIG_SPL_ATF=y -+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TIME=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_TPL_OF_CONTROL=y -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_TPL_OF_PLATDATA=y -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_TPL_DM=y -+CONFIG_REGMAP=y -+CONFIG_SPL_REGMAP=y -+CONFIG_TPL_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_SPL_SYSCON=y -+CONFIG_TPL_SYSCON=y -+CONFIG_CLK=y -+CONFIG_SPL_CLK=y -+CONFIG_FASTBOOT_BUF_ADDR=0x800800 -+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_SF_DEFAULT_SPEED=20000000 -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PINCTRL=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_DM_REGULATOR=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_SPL_DM_REGULATOR_FIXED=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM=y -+CONFIG_SPL_RAM=y -+CONFIG_TPL_RAM=y -+CONFIG_DM_RESET=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSINFO=y -+CONFIG_SYSRESET=y -+# CONFIG_TPL_SYSRESET is not set -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 -+CONFIG_USB_DWC2=y -+CONFIG_USB_DWC3=y -+# CONFIG_USB_DWC3_GADGET is not set -+CONFIG_USB_GADGET=y -+CONFIG_USB_GADGET_DWC2_OTG=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_TPL_TINY_MEMSET=y -+CONFIG_ERRNO_STR=y diff --git a/5.4/package/boot/uboot-rockchip/patches/305-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch b/5.4/package/boot/uboot-rockchip/patches/305-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch deleted file mode 100644 index ca6f8095..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/305-rockchip-rk3399-Add-support-for-FriendlyARM-NanoPi-R.patch +++ /dev/null @@ -1,113 +0,0 @@ ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -157,6 +157,7 @@ - rk3399-nanopi-m4b.dtb \ - rk3399-nanopi-neo4.dtb \ - rk3399-nanopi-r4s.dtb \ -+ rk3399-nanopi-r4se.dtb \ - rk3399-orangepi.dtb \ - rk3399-pinebook-pro.dtb \ - rk3399-puma-haikou.dtb \ ---- /dev/null -+++ b/arch/arm/dts/rk3399-nanopi-r4se.dts -@@ -0,0 +1,32 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * FriendlyElec NanoPC-T4 board device tree source -+ * -+ * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd. -+ * (http://www.friendlyarm.com) -+ * -+ * Copyright (c) 2018 Collabora Ltd. -+ * -+ * Copyright (c) 2020 Jensen Huang -+ */ -+ -+/dts-v1/; -+#include "rk3399-nanopi-r4s.dts" -+ -+/ { -+ model = "FriendlyElec NanoPi R4SE"; -+ compatible = "friendlyarm,nanopi-r4se", "rockchip,rk3399"; -+}; -+ -+&emmc_phy { -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ non-removable; -+ status = "okay"; -+}; -+&sdmmc { -+ pinctrl-0 = <&sdmmc_cd>; -+}; ---- /dev/null -+++ b/configs/nanopi-r4se-rk3399_defconfig -@@ -0,0 +1,65 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_COUNTER_FREQUENCY=24000000 -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4se" -+CONFIG_ROCKCHIP_RK3399=y -+CONFIG_TARGET_EVB_RK3399=y -+CONFIG_DEBUG_UART_BASE=0xFF1A0000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SYS_LOAD_ADDR=0x800800 -+CONFIG_DEBUG_UART=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4se.dtb" -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 -+CONFIG_TPL=y -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TIME=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM_RK3399_LPDDR4=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_KEYBOARD=y -+CONFIG_USB_HOST_ETHER=y -+CONFIG_USB_ETHER_ASIX=y -+CONFIG_USB_ETHER_ASIX88179=y -+CONFIG_USB_ETHER_MCS7830=y -+CONFIG_USB_ETHER_RTL8152=y -+CONFIG_USB_ETHER_SMSC95XX=y -+CONFIG_DM_VIDEO=y -+CONFIG_DISPLAY=y -+CONFIG_VIDEO_ROCKCHIP=y -+CONFIG_DISPLAY_ROCKCHIP_HDMI=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_ERRNO_STR=y diff --git a/5.4/package/boot/uboot-rockchip/patches/306-rockchip-rk3399-Add-support-for-Rongpin-king3399.patch b/5.4/package/boot/uboot-rockchip/patches/306-rockchip-rk3399-Add-support-for-Rongpin-king3399.patch deleted file mode 100755 index 837f5864..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/306-rockchip-rk3399-Add-support-for-Rongpin-king3399.patch +++ /dev/null @@ -1,68 +0,0 @@ ---- /dev/null -+++ b/configs/rongpin-king3399-rk3399_defconfig -@@ -0,0 +1,65 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_COUNTER_FREQUENCY=24000000 -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4se" -+CONFIG_ROCKCHIP_RK3399=y -+CONFIG_TARGET_EVB_RK3399=y -+CONFIG_DEBUG_UART_BASE=0xFF1A0000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SYS_LOAD_ADDR=0x800800 -+CONFIG_DEBUG_UART=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4se.dtb" -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 -+CONFIG_TPL=y -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TIME=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM_RK3399_LPDDR4=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_KEYBOARD=y -+CONFIG_USB_HOST_ETHER=y -+CONFIG_USB_ETHER_ASIX=y -+CONFIG_USB_ETHER_ASIX88179=y -+CONFIG_USB_ETHER_MCS7830=y -+CONFIG_USB_ETHER_RTL8152=y -+CONFIG_USB_ETHER_SMSC95XX=y -+CONFIG_DM_VIDEO=y -+CONFIG_DISPLAY=y -+CONFIG_VIDEO_ROCKCHIP=y -+CONFIG_DISPLAY_ROCKCHIP_HDMI=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_ERRNO_STR=y diff --git a/5.4/package/boot/uboot-rockchip/patches/307-rockchip-rk3399-Add-support-for-Rocktech-MPC1903.patch b/5.4/package/boot/uboot-rockchip/patches/307-rockchip-rk3399-Add-support-for-Rocktech-MPC1903.patch deleted file mode 100644 index bdccbc01..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/307-rockchip-rk3399-Add-support-for-Rocktech-MPC1903.patch +++ /dev/null @@ -1,784 +0,0 @@ ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -165,6 +165,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ - rk3399-rock-pi-4b.dtb \ - rk3399-rock-pi-4c.dtb \ - rk3399-rock960.dtb \ -+ rk3399-mpc1903.dtb \ - rk3399-rockpro64.dtb \ - rk3399pro-rock-pi-n10.dtb - ---- /dev/null -+++ b/arch/arm/dts/rk3399-mpc1903.dts -@@ -0,0 +1,688 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+#include -+#include "rk3399.dtsi" -+#include "rk3399-opp.dtsi" -+ -+/ { -+ model = "Rocktech MPC1903"; -+ compatible = "rocktech,mpc1903", "rockchip,rk3399"; -+ -+ aliases { -+ mmc0 = &sdmmc; -+ mmc1 = &sdhci; -+ }; -+ -+ chosen { -+ stdout-path = "serial2:1500000n8"; -+ }; -+ -+ clkin_gmac: external-gmac-clock { -+ compatible = "fixed-clock"; -+ clock-frequency = <125000000>; -+ clock-output-names = "clkin_gmac"; -+ #clock-cells = <0>; -+ }; -+ -+ vcc12v_dcin: dc-12v { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc12v_dcin"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ }; -+ -+ sdio_pwrseq: sdio-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&rk808 1>; -+ clock-names = "ext_clock"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_enable_h>; -+ reset-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_LOW>; -+ }; -+ -+ vcc5v0_sys: vcc-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc12v_dcin>; -+ }; -+ -+ vcc3v3_sys: vcc3v3-sys { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc5v0_host: vcc5v0-host-regulator { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_host_en>; -+ regulator-name = "vcc5v0_host"; -+ regulator-always-on; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc_lan: vcc-phy-regulator { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_lan"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ vdd_log: vdd-log { -+ compatible = "pwm-regulator"; -+ pwms = <&pwm2 0 25000 1>; -+ regulator-name = "vdd_log"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1400000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&status_led_pin>; -+ -+ status_led: led-status-led { -+ label = "status_led"; -+ linux,default-trigger = "heartbeat"; -+ gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ hub_control { -+ compatible = "rocktech,hub-control"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hub_pwr>; -+ hub-pwr-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ }; -+}; -+ -+&cpu_l0 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l1 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l2 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_l3 { -+ cpu-supply = <&vdd_cpu_l>; -+}; -+ -+&cpu_b0 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&cpu_b1 { -+ cpu-supply = <&vdd_cpu_b>; -+}; -+ -+&emmc_phy { -+ status = "okay"; -+}; -+ -+&gmac { -+ assigned-clocks = <&cru SCLK_RMII_SRC>; -+ assigned-clock-parents = <&clkin_gmac>; -+ clock_in_out = "input"; -+ phy-supply = <&vcc_lan>; -+ phy-mode = "rmgii"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rgmii_pins>; -+ snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; -+ snps,reset-active-low; -+ snps,reset-delays-us = <0 10000 50000>; -+ tx_delay = <0x28>; -+ rx_delay = <0x11>; -+ status = "okay"; -+}; -+ -+&gpu { -+ mali-supply = <&vdd_gpu>; -+ status = "okay"; -+}; -+ -+&hdmi { -+ ddc-i2c-bus = <&i2c3>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hdmi_i2c_xfer>; -+ status = "okay"; -+}; -+ -+&hdmi_sound { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ clock-frequency = <400000>; -+ i2c-scl-rising-time-ns = <168>; -+ i2c-scl-falling-time-ns = <4>; -+ status = "okay"; -+ -+ rk808: pmic@1b { -+ compatible = "rockchip,rk808"; -+ reg = <0x1b>; -+ interrupt-parent = <&gpio1>; -+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>; -+ #clock-cells = <1>; -+ clock-output-names = "xin32k", "rk808-clkout2"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int_l>; -+ rockchip,system-power-controller; -+ wakeup-source; -+ -+ vcc1-supply = <&vcc5v0_sys>; -+ vcc2-supply = <&vcc5v0_sys>; -+ vcc3-supply = <&vcc5v0_sys>; -+ vcc4-supply = <&vcc5v0_sys>; -+ vcc6-supply = <&vcc5v0_sys>; -+ vcc7-supply = <&vcc5v0_sys>; -+ vcc8-supply = <&vcc3v3_sys>; -+ vcc9-supply = <&vcc5v0_sys>; -+ vcc10-supply = <&vcc5v0_sys>; -+ vcc11-supply = <&vcc5v0_sys>; -+ vcc12-supply = <&vcc3v3_sys>; -+ vddio-supply = <&vcc_3v0>; -+ -+ regulators { -+ vdd_center: DCDC_REG1 { -+ regulator-name = "vdd_center"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_cpu_l: DCDC_REG2 { -+ regulator-name = "vdd_cpu_l"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <750000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: DCDC_REG4 { -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ gen_1v8: LDO_REG1 { -+ regulator-name = "gen_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ gen_3v0: LDO_REG2 { -+ regulator-name = "gen_3v0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ -+ vcc1v8_pmu: LDO_REG3 { -+ regulator-name = "vcc1v8_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc_sdio: LDO_REG4 { -+ regulator-name = "vcc_sdio"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ -+ vcca3v0_codec: LDO_REG5 { -+ regulator-name = "vcca3v0_codec"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v5: LDO_REG6 { -+ regulator-name = "vcc_1v5"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <1500000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc1v8_codec: LDO_REG7 { -+ regulator-name = "vcc1v8_codec"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcc_3v0: LDO_REG8 { -+ regulator-name = "vcc_3v0"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3000000>; -+ regulator-max-microvolt = <3000000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3000000>; -+ }; -+ }; -+ -+ vcc3v3_s3: SWITCH_REG1 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vcc3v3_s3"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_s0: SWITCH_REG2 { -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-name = "vcc3v3_s0"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+ -+ vdd_cpu_b: regulator@40 { -+ compatible = "silergy,syr827"; -+ reg = <0x40>; -+ fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vsel1_pin>; -+ regulator-name = "vdd_cpu_b"; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-ramp-delay = <1000>; -+ regulator-always-on; -+ regulator-boot-on; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: regulator@41 { -+ compatible = "silergy,syr828"; -+ reg = <0x41>; -+ fcs,suspend-voltage-selector = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vsel2_pin>; -+ regulator-name = "vdd_gpu"; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1500000>; -+ regulator-ramp-delay = <1000>; -+ regulator-always-on; -+ regulator-boot-on; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ rtc: pcf85263@51 { -+ compatible = "nxp,pcf85263"; -+ reg = <0x51>; -+ pinctrl-0 = <&rtc_int>; -+ rtc_int_gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; -+ }; -+}; -+ -+&i2c1 { -+ i2c-scl-rising-time-ns = <300>; -+ i2c-scl-falling-time-ns = <15>; -+ status = "okay"; -+}; -+ -+&i2s2 { -+ status = "okay"; -+}; -+ -+&i2c4 { -+ i2c-scl-rising-time-ns = <600>; -+ i2c-scl-falling-time-ns = <20>; -+ status = "okay"; -+}; -+ -+&i2c6 { -+ status = "okay"; -+}; -+ -+&i2s0 { -+ rockchip,i2s-broken-burst-len; -+ rockchip,playback-channels = <8>; -+ rockchip,capture-channels = <8>; -+ status = "okay"; -+}; -+ -+&i2s2 { -+ rockchip,bclk-fs = <128>; -+ status = "okay"; -+}; -+ -+&io_domains { -+ status = "okay"; -+ -+ bt656-supply = <&vcc_3v0>; -+ audio-supply = <&vcc1v8_codec>; -+ sdmmc-supply = <&vcc_sdio>; -+ gpio1830-supply = <&vcc_3v0>; -+}; -+ -+&pmu_io_domains { -+ status = "okay"; -+ -+ pmu1830-supply = <&vcc_3v0>; -+}; -+ -+&pinctrl { -+ bt { -+ uart0_gpios: uart0-gpios { -+ rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ pmic { -+ pmic_int_l: pmic-int-l { -+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ vsel1_pin: vsel1-pin { -+ rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ vsel2_pin: vsel2-pin { -+ rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ usb2 { -+ vcc5v0_host_en: vcc5v0-host-en { -+ rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ -+ hub_pwr: hub-pwr { -+ rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ wifi { -+ wifi_enable_h: wifi-enable-h { -+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ rtc { -+ rtc_int: rtc-int { -+ rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ led { -+ status_led_pin: status-led-pin { -+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+ -+ rockchip-key { -+ power_key: power-key { -+ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; -+ -+&pwm0 { -+ status = "okay"; -+}; -+ -+&pwm1 { -+ status = "okay"; -+}; -+ -+&pwm2 { -+ status = "okay"; -+}; -+ -+&saradc { -+ status = "okay"; -+ vref-supply = <&vcc_1v8>; -+}; -+ -+&sdio0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ bus-width = <4>; -+ clock-frequency = <50000000>; -+ cap-sdio-irq; -+ cap-sd-highspeed; -+ keep-power-in-suspend; -+ mmc-pwrseq = <&sdio_pwrseq>; -+ non-removable; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; -+ sd-uhs-sdr104; -+ status = "okay"; -+}; -+ -+&sdmmc { -+ clock-freq-min-max = <400000 150000000>; -+ bus-width = <4>; -+ cap-mmc-highspeed; -+ cap-sd-highspeed; -+ supports-sd; -+ disable-wp; -+ num-slots = <1>; -+ vqmmc-supply = <&vcc_sdio>; -+ max-frequency = <150000000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>; -+ status = "okay"; -+}; -+ -+&sdhci { -+ bus-width = <8>; -+ keep-power-in-suspend; -+ mmc-hs400-1_8v; -+ mmc-hs400-enhanced-strobe; -+ non-removable; -+ supports-emmc; -+ status = "okay"; -+}; -+ -+&tcphy0 { -+ status = "okay"; -+}; -+ -+&tcphy1 { -+ status = "okay"; -+}; -+ -+&tsadc { -+ status = "okay"; -+ rockchip,hw-tshut-temp = <120000>; -+ /* tshut mode 0:CRU 1:GPIO */ -+ rockchip,hw-tshut-mode = <1>; -+ /* tshut polarity 0:LOW 1:HIGH */ -+ rockchip,hw-tshut-polarity = <1>; -+}; -+ -+&u2phy0 { -+ status = "okay"; -+}; -+ -+ -+&u2phy0_otg { -+ status = "okay"; -+}; -+ -+&u2phy0_host { -+ status = "okay"; -+}; -+ -+&u2phy1 { -+ status = "okay"; -+}; -+ -+&u2phy1_otg { -+ status = "okay"; -+}; -+ -+&u2phy1_host { -+ status = "okay"; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; -+}; -+ -+&uart2 { -+ status = "okay"; -+}; -+ -+&usb_host0_ehci { -+ status = "okay"; -+}; -+ -+&usb_host0_ohci { -+ status = "okay"; -+}; -+ -+&usb_host1_ehci { -+ status = "okay"; -+}; -+ -+&usb_host1_ohci { -+ status = "okay"; -+}; -+ -+&usbdrd3_0 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3_0 { -+ status = "okay"; -+ dr_mode = "host"; -+}; -+ -+&usbdrd3_1 { -+ status = "okay"; -+}; -+ -+&usbdrd_dwc3_1 { -+ status = "okay"; -+ dr_mode = "host"; -+}; -+ -+&vopb { -+ status = "okay"; -+}; -+ -+&vopb_mmu { -+ status = "okay"; -+}; -+ -+&vopl { -+ status = "okay"; -+}; -+ -+&vopl_mmu { -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/dts/rk3399-mpc1903-u-boot.dtsi -@@ -0,0 +1,14 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+ -+#include "rk3399-u-boot.dtsi" -+#include "rk3399-sdram-lpddr3-4GB-1600.dtsi" -+ -+/ { -+ chosen { -+ u-boot,spl-boot-order = "same-as-spl", &sdhci, &sdmmc; -+ }; -+}; -+ -+&sdmmc { -+ pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>; -+}; ---- /dev/null -+++ b/configs/rocktech-mpc1903-rk3399_defconfig -@@ -0,0 +1,63 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_COUNTER_FREQUENCY=24000000 -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00200000 -+CONFIG_ENV_OFFSET=0x3F8000 -+CONFIG_ROCKCHIP_RK3399=y -+CONFIG_TARGET_EVB_RK3399=y -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_SYS_LOAD_ADDR=0x800800 -+CONFIG_DEBUG_UART_BASE=0xFF1A0000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEBUG_UART=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-mpc1903.dtb" -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 -+CONFIG_TPL=y -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TIME=y -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_DEFAULT_DEVICE_TREE="rk3399-mpc1903" -+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_ENV_IS_IN_MMC=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_HOST_ETHER=y -+CONFIG_USB_ETHER_ASIX=y -+CONFIG_USB_ETHER_ASIX88179=y -+CONFIG_USB_ETHER_MCS7830=y -+CONFIG_USB_ETHER_RTL8152=y -+CONFIG_USB_ETHER_SMSC95XX=y -+CONFIG_DM_VIDEO=y -+CONFIG_DISPLAY=y -+CONFIG_VIDEO_ROCKCHIP=y -+CONFIG_DISPLAY_ROCKCHIP_HDMI=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_ERRNO_STR=y diff --git a/5.4/package/boot/uboot-rockchip/patches/311-rockchip-rk3568-Add-support-for-ezpro_mrkaio-m68s.patch b/5.4/package/boot/uboot-rockchip/patches/311-rockchip-rk3568-Add-support-for-ezpro_mrkaio-m68s.patch deleted file mode 100644 index f780ecb6..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/311-rockchip-rk3568-Add-support-for-ezpro_mrkaio-m68s.patch +++ /dev/null @@ -1,406 +0,0 @@ ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ - dtb-$(CONFIG_ROCKCHIP_RK3568) += \ - rk3568-bpi-r2-pro.dtb \ - rk3568-evb.dtb \ -+ rk3568-mrkaio-m68s.dtb \ - rk3568-nanopi-r5s.dtb \ - rk3566-quartz64-a.dtb \ - rk3568-rock-3a.dtb ---- /dev/null -+++ b/arch/arm/dts/rk3568-mrkaio-m68s-u-boot.dtsi -@@ -0,0 +1,21 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include "rk3568-u-boot.dtsi" -+ -+/ { -+ chosen { -+ stdout-path = &uart2; -+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; -+ }; -+}; -+ -+&sdmmc0 { -+ bus-width = <4>; -+ u-boot,spl-fifo-mode; -+}; -+ -+&uart2 { -+ u-boot,dm-spl; -+ clock-frequency = <24000000>; -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/dts/rk3568-mrkaio-m68s.dts -@@ -0,0 +1,268 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include "rk3568-evb.dts" -+ -+/ { -+ model = "EZPRO Mrkaio M68S"; -+ compatible = "ezpro,mrkaio-m68s", "rockchip,rk3568"; -+ -+ aliases { -+ mmc0 = &sdmmc0; -+ mmc1 = &sdhci; -+ }; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu2 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu3 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ vdd_cpu: regulator@1c { -+ compatible = "tcs,tcs4525"; -+ reg = <0x1c>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <712500>; -+ regulator-max-microvolt = <1150000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ rk809: pmic@20 { -+ compatible = "rockchip,rk809"; -+ reg = <0x20>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ #clock-cells = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int>; -+ rockchip,system-power-controller; -+ -+ vcc1-supply = <&vcc3v3_sys>; -+ vcc2-supply = <&vcc3v3_sys>; -+ vcc3-supply = <&vcc3v3_sys>; -+ vcc4-supply = <&vcc3v3_sys>; -+ vcc5-supply = <&vcc3v3_sys>; -+ vcc6-supply = <&vcc3v3_sys>; -+ vcc7-supply = <&vcc3v3_sys>; -+ vcc8-supply = <&vcc3v3_sys>; -+ vcc9-supply = <&vcc3v3_sys>; -+ wakeup-source; -+ -+ regulators { -+ vdd_logic: DCDC_REG1 { -+ regulator-name = "vdd_logic"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: DCDC_REG2 { -+ regulator-name = "vdd_gpu"; -+ regulator-always-on; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vdd_npu: DCDC_REG4 { -+ regulator-name = "vdd_npu"; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: DCDC_REG5 { -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_image: LDO_REG1 { -+ regulator-name = "vdda0v9_image"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda_0v9: LDO_REG2 { -+ regulator-name = "vdda_0v9"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_pmu: LDO_REG3 { -+ regulator-name = "vdda0v9_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ vccio_acodec: LDO_REG4 { -+ regulator-name = "vccio_acodec"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd: LDO_REG5 { -+ regulator-name = "vccio_sd"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_pmu: LDO_REG6 { -+ regulator-name = "vcc3v3_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcca_1v8: LDO_REG7 { -+ regulator-name = "vcca_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcca1v8_pmu: LDO_REG8 { -+ regulator-name = "vcca1v8_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcca1v8_image: LDO_REG9 { -+ regulator-name = "vcca1v8_image"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v3: SWITCH_REG1 { -+ regulator-name = "vcc_3v3"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_sd: SWITCH_REG2 { -+ regulator-name = "vcc3v3_sd"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&pinctrl { -+ pmic { -+ pmic_int: pmic_int { -+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/configs/mrkaio-m68s-rk3568_defconfig -@@ -0,0 +1,98 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00a00000 -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_DEFAULT_DEVICE_TREE="rk3568-mrkaio-m68s" -+CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y -+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_MMC=y -+CONFIG_SPL_SERIAL=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_TARGET_EVB_RK3568=y -+CONFIG_DEBUG_UART_BASE=0xFE660000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0xc00800 -+CONFIG_API=y -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_OF_SYSTEM_SETUP=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-mrkaio-m68s.dtb" -+# CONFIG_SYS_DEVICE_NULLDEV is not set -+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_SEPARATE_BSS=y -+CONFIG_SPL_ATF=y -+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y -+CONFIG_CMD_BIND=y -+CONFIG_CMD_CLK=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_PMIC=y -+CONFIG_CMD_REGULATOR=y -+# CONFIG_SPL_DOS_PARTITION is not set -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_LIVE=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_SPL_DM_WARN=y -+CONFIG_SPL_REGMAP=y -+CONFIG_SPL_SYSCON=y -+CONFIG_SPL_CLK=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_ROCKCHIP_GPIO_V2=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_SPL_MMC_HS200_SUPPORT=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_PMIC_RK8XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_SPL_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_SPL_RAM=y -+CONFIG_DM_RESET=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSRESET=y -+CONFIG_SYSRESET_PSCI=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GENERIC=y -+CONFIG_ROCKCHIP_USB2_PHY=y -+CONFIG_USB_KEYBOARD=y -+CONFIG_USB_HOST_ETHER=y -+CONFIG_USB_ETHER_LAN75XX=y -+CONFIG_USB_ETHER_LAN78XX=y -+CONFIG_USB_ETHER_SMSC95XX=y -+CONFIG_ERRNO_STR=y diff --git a/5.4/package/boot/uboot-rockchip/patches/312-rockchip-rk3568-Add-support-for-hinlink-opc-h68k.patch b/5.4/package/boot/uboot-rockchip/patches/312-rockchip-rk3568-Add-support-for-hinlink-opc-h68k.patch deleted file mode 100644 index 69a685d3..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/312-rockchip-rk3568-Add-support-for-hinlink-opc-h68k.patch +++ /dev/null @@ -1,415 +0,0 @@ ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ - dtb-$(CONFIG_ROCKCHIP_RK3568) += \ - rk3568-bpi-r2-pro.dtb \ - rk3568-evb.dtb \ -+ rk3568-opc-h68k.dtb \ - rk3568-mrkaio-m68s.dtb \ - rk3568-nanopi-r5s.dtb \ - rk3566-quartz64-a.dtb \ ---- /dev/null -+++ b/arch/arm/dts/rk3568-opc-h68k-u-boot.dtsi -@@ -0,0 +1,21 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include "rk3568-u-boot.dtsi" -+ -+/ { -+ chosen { -+ stdout-path = &uart2; -+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; -+ }; -+}; -+ -+&sdmmc0 { -+ bus-width = <4>; -+ u-boot,spl-fifo-mode; -+}; -+ -+&uart2 { -+ u-boot,dm-spl; -+ clock-frequency = <24000000>; -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/dts/rk3568-opc-h68k.dts -@@ -0,0 +1,277 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include "rk3568-evb.dts" -+ -+/ { -+ model = "HINLINK OPC-H68K Board"; -+ compatible = "hinlink,opc-h68k", "rockchip,rk3568"; -+ -+ aliases { -+ mmc0 = &sdmmc0; -+ mmc1 = &sdhci; -+ }; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu1 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu2 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&cpu3 { -+ cpu-supply = <&vdd_cpu>; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ vdd_cpu: regulator@1c { -+ compatible = "tcs,tcs4525"; -+ reg = <0x1c>; -+ fcs,suspend-voltage-selector = <1>; -+ regulator-name = "vdd_cpu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <800000>; -+ regulator-max-microvolt = <1150000>; -+ regulator-ramp-delay = <2300>; -+ vin-supply = <&vcc5v0_sys>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ rk809: pmic@20 { -+ compatible = "rockchip,rk809"; -+ reg = <0x20>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ assigned-clocks = <&cru I2S1_MCLKOUT_TX>; -+ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; -+ #clock-cells = <1>; -+ clock-names = "mclk"; -+ clocks = <&cru I2S1_MCLKOUT_TX>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; -+ rockchip,system-power-controller; -+ #sound-dai-cells = <0>; -+ vcc1-supply = <&vcc3v3_sys>; -+ vcc2-supply = <&vcc3v3_sys>; -+ vcc3-supply = <&vcc3v3_sys>; -+ vcc4-supply = <&vcc3v3_sys>; -+ vcc5-supply = <&vcc3v3_sys>; -+ vcc6-supply = <&vcc3v3_sys>; -+ vcc7-supply = <&vcc3v3_sys>; -+ vcc8-supply = <&vcc3v3_sys>; -+ vcc9-supply = <&vcc3v3_sys>; -+ wakeup-source; -+ -+ regulators { -+ vdd_logic: DCDC_REG1 { -+ regulator-name = "vdd_logic"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdd_gpu: DCDC_REG2 { -+ regulator-name = "vdd_gpu"; -+ regulator-always-on; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_ddr: DCDC_REG3 { -+ regulator-name = "vcc_ddr"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-initial-mode = <0x2>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ }; -+ }; -+ -+ vdd_npu: DCDC_REG4 { -+ regulator-name = "vdd_npu"; -+ regulator-init-microvolt = <900000>; -+ regulator-initial-mode = <0x2>; -+ regulator-min-microvolt = <500000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-ramp-delay = <6001>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_1v8: DCDC_REG5 { -+ regulator-name = "vcc_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_image: LDO_REG1 { -+ regulator-name = "vdda0v9_image"; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda_0v9: LDO_REG2 { -+ regulator-name = "vdda_0v9"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vdda0v9_pmu: LDO_REG3 { -+ regulator-name = "vdda0v9_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <900000>; -+ regulator-max-microvolt = <900000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <900000>; -+ }; -+ }; -+ -+ vccio_acodec: LDO_REG4 { -+ regulator-name = "vccio_acodec"; -+ regulator-always-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vccio_sd: LDO_REG5 { -+ regulator-name = "vccio_sd"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_pmu: LDO_REG6 { -+ regulator-name = "vcc3v3_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <3300000>; -+ }; -+ }; -+ -+ vcca_1v8: LDO_REG7 { -+ regulator-name = "vcca_1v8"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcca1v8_pmu: LDO_REG8 { -+ regulator-name = "vcca1v8_pmu"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-on-in-suspend; -+ regulator-suspend-microvolt = <1800000>; -+ }; -+ }; -+ -+ vcca1v8_image: LDO_REG9 { -+ regulator-name = "vcca1v8_image"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc_3v3: SWITCH_REG1 { -+ regulator-name = "vcc_3v3"; -+ regulator-always-on; -+ regulator-boot-on; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ -+ vcc3v3_sd: SWITCH_REG2 { -+ regulator-name = "vcc3v3_sd"; -+ -+ regulator-state-mem { -+ regulator-off-in-suspend; -+ }; -+ }; -+ }; -+ -+ codec { -+ mic-in-differential; -+ }; -+ }; -+}; -+ -+&pinctrl { -+ pmic { -+ pmic_int: pmic_int { -+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/configs/opc-h68k-rk3568_defconfig -@@ -0,0 +1,98 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00a00000 -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_DEFAULT_DEVICE_TREE="rk3568-opc-h68k" -+CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y -+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_MMC=y -+CONFIG_SPL_SERIAL=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_TARGET_EVB_RK3568=y -+CONFIG_DEBUG_UART_BASE=0xFE660000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0xc00800 -+CONFIG_API=y -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_OF_SYSTEM_SETUP=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-opc-h68k.dtb" -+# CONFIG_SYS_DEVICE_NULLDEV is not set -+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_SEPARATE_BSS=y -+CONFIG_SPL_ATF=y -+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y -+CONFIG_CMD_BIND=y -+CONFIG_CMD_CLK=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_PMIC=y -+CONFIG_CMD_REGULATOR=y -+# CONFIG_SPL_DOS_PARTITION is not set -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_LIVE=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_SPL_DM_WARN=y -+CONFIG_SPL_REGMAP=y -+CONFIG_SPL_SYSCON=y -+CONFIG_SPL_CLK=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_ROCKCHIP_GPIO_V2=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_SPL_MMC_HS200_SUPPORT=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_PMIC_RK8XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_SPL_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_SPL_RAM=y -+CONFIG_DM_RESET=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSRESET=y -+CONFIG_SYSRESET_PSCI=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GENERIC=y -+CONFIG_ROCKCHIP_USB2_PHY=y -+CONFIG_USB_KEYBOARD=y -+CONFIG_USB_HOST_ETHER=y -+CONFIG_USB_ETHER_LAN75XX=y -+CONFIG_USB_ETHER_LAN78XX=y -+CONFIG_USB_ETHER_SMSC95XX=y -+CONFIG_ERRNO_STR=y diff --git a/5.4/package/boot/uboot-rockchip/patches/313-rockchip-rk3568-Add-support-for-fastrhino-r66s.patch b/5.4/package/boot/uboot-rockchip/patches/313-rockchip-rk3568-Add-support-for-fastrhino-r66s.patch deleted file mode 100644 index e7f7d6ae..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/313-rockchip-rk3568-Add-support-for-fastrhino-r66s.patch +++ /dev/null @@ -1,140 +0,0 @@ ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -171,6 +171,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \ - dtb-$(CONFIG_ROCKCHIP_RK3568) += \ - rk3568-bpi-r2-pro.dtb \ - rk3568-evb.dtb \ -+ rk3568-r66s.dtb \ - rk3568-opc-h68k.dtb \ - rk3568-mrkaio-m68s.dtb \ - rk3568-nanopi-r5s.dtb \ ---- /dev/null -+++ b/arch/arm/dts/rk3568-r66s-u-boot.dtsi -@@ -0,0 +1,21 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include "rk3568-u-boot.dtsi" -+ -+/ { -+ chosen { -+ stdout-path = &uart2; -+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; -+ }; -+}; -+ -+&sdmmc0 { -+ bus-width = <4>; -+ u-boot,spl-fifo-mode; -+}; -+ -+&uart2 { -+ u-boot,dm-spl; -+ clock-frequency = <24000000>; -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/dts/rk3568-r66s.dts -@@ -0,0 +1,2 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+#include "rk3568-evb.dts" ---- /dev/null -+++ b/configs/r66s-rk3568_defconfig -@@ -0,0 +1,98 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00a00000 -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_DEFAULT_DEVICE_TREE="rk3568-r66s" -+CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y -+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_MMC=y -+CONFIG_SPL_SERIAL=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_TARGET_EVB_RK3568=y -+CONFIG_DEBUG_UART_BASE=0xFE660000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0xc00800 -+CONFIG_API=y -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_OF_SYSTEM_SETUP=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-r66s.dtb" -+# CONFIG_SYS_DEVICE_NULLDEV is not set -+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_SEPARATE_BSS=y -+CONFIG_SPL_ATF=y -+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y -+CONFIG_CMD_BIND=y -+CONFIG_CMD_CLK=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_PMIC=y -+CONFIG_CMD_REGULATOR=y -+# CONFIG_SPL_DOS_PARTITION is not set -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_LIVE=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_SPL_DM_WARN=y -+CONFIG_SPL_REGMAP=y -+CONFIG_SPL_SYSCON=y -+CONFIG_SPL_CLK=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_ROCKCHIP_GPIO_V2=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_SPL_MMC_HS200_SUPPORT=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_PMIC_RK8XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_SPL_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_SPL_RAM=y -+CONFIG_DM_RESET=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSRESET=y -+CONFIG_SYSRESET_PSCI=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GENERIC=y -+CONFIG_ROCKCHIP_USB2_PHY=y -+CONFIG_USB_KEYBOARD=y -+CONFIG_USB_HOST_ETHER=y -+CONFIG_USB_ETHER_LAN75XX=y -+CONFIG_USB_ETHER_LAN78XX=y -+CONFIG_USB_ETHER_SMSC95XX=y -+CONFIG_ERRNO_STR=y diff --git a/5.4/package/boot/uboot-rockchip/patches/314-rockchip-rk3568-Add-support-for-Station-P2.patch b/5.4/package/boot/uboot-rockchip/patches/314-rockchip-rk3568-Add-support-for-Station-P2.patch deleted file mode 100644 index 3df47445..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/314-rockchip-rk3568-Add-support-for-Station-P2.patch +++ /dev/null @@ -1,77 +0,0 @@ -From 18e3719c5d5b1573c29d137c1244ca23277750b2 Mon Sep 17 00:00:00 2001 -From: huangjf -Date: Thu, 7 Apr 2022 16:22:56 +0800 -Subject: [PATCH] rockchip: rk3568: Add support for Station P2 - ---- - configs/station-p2-rk3568_defconfig | 59 +++++++++++++++++++++++++++++ - 1 file changed, 59 insertions(+) - create mode 100644 configs/station-p2-rk3568_defconfig - -diff --git a/configs/station-p2-rk3568_defconfig b/configs/station-p2-rk3568_defconfig -new file mode 100644 -index 0000000000..435be99edf ---- /dev/null -+++ b/configs/station-p2-rk3568_defconfig -@@ -0,0 +1,59 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00a00000 -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb" -+CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y -+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_MMC=y -+CONFIG_SPL_SERIAL=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_TARGET_EVB_RK3568=y -+CONFIG_DEBUG_UART_BASE=0xFE660000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0xc00800 -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb" -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_SEPARATE_BSS=y -+CONFIG_SPL_ATF=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_MMC=y -+# CONFIG_CMD_SETEXPR is not set -+# CONFIG_SPL_DOS_PARTITION is not set -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_LIVE=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_SPL_REGMAP=y -+CONFIG_SPL_SYSCON=y -+CONFIG_SPL_CLK=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_SUPPORT_EMMC_RPMB=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_SPL_RAM=y -+CONFIG_DM_RESET=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSRESET=y -+CONFIG_ERRNO_STR=y --- -2.20.1 diff --git a/5.4/package/boot/uboot-rockchip/patches/315-rockchip-rk3568-Add-support-for-radxa_e25.patch b/5.4/package/boot/uboot-rockchip/patches/315-rockchip-rk3568-Add-support-for-radxa_e25.patch deleted file mode 100644 index 0c2f9b1e..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/315-rockchip-rk3568-Add-support-for-radxa_e25.patch +++ /dev/null @@ -1,154 +0,0 @@ ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -177,7 +177,8 @@ rk3568-evb.dtb \ - rk3568-mrkaio-m68s.dtb \ - rk3568-nanopi-r5s.dtb \ - rk3566-quartz64-a.dtb \ -- rk3568-rock-3a.dtb -+ rk3568-rock-3a.dtb \ -+ rk3568-radxa-e25.dtb - - dtb-$(CONFIG_ROCKCHIP_RV1108) += \ - rv1108-elgin-r1.dtb \ ---- /dev/null -+++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi -@@ -0,0 +1,21 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include "rk3568-u-boot.dtsi" -+ -+/ { -+ chosen { -+ stdout-path = &uart2; -+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; -+ }; -+}; -+ -+&sdmmc0 { -+ bus-width = <4>; -+ u-boot,spl-fifo-mode; -+}; -+ -+&uart2 { -+ u-boot,dm-spl; -+ clock-frequency = <24000000>; -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm/dts/rk3568-radxa-e25.dts -@@ -0,0 +1,13 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include "rk3568-evb.dts" -+ -+/ { -+ model = "Radxa E25"; -+ compatible = "radxa,e25", "rockchip,rk3568"; -+ -+ aliases { -+ mmc0 = &sdmmc0; -+ mmc1 = &sdhci; -+ }; -+}; ---- /dev/null -+++ b/configs/radxa-e25-rk3568_defconfig -@@ -0,0 +1,99 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00a00000 -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_DEFAULT_DEVICE_TREE="rk3568-radxa-e25" -+CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y -+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_MMC=y -+CONFIG_SPL_SERIAL=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_TARGET_EVB_RK3568=y -+CONFIG_DEBUG_UART_BASE=0xFE660000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0xc00800 -+CONFIG_API=y -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_OF_SYSTEM_SETUP=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-radxa-e25.dtb" -+# CONFIG_SYS_DEVICE_NULLDEV is not set -+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=1 -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_SEPARATE_BSS=y -+CONFIG_SPL_ADC=y -+CONFIG_SPL_ATF=y -+CONFIG_SPL_BOARD_INIT=y -+CONFIG_CMD_ADC=y -+CONFIG_CMD_BIND=y -+CONFIG_CMD_CLK=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_PMIC=y -+CONFIG_CMD_REGULATOR=y -+# CONFIG_SPL_DOS_PARTITION is not set -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_LIVE=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_SPL_DM_WARN=y -+CONFIG_SPL_REGMAP=y -+CONFIG_SPL_SYSCON=y -+CONFIG_SPL_CLK=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_ROCKCHIP_GPIO_V2=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_SPL_MMC_HS200_SUPPORT=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_PMIC_RK8XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_SPL_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_SPL_RAM=y -+CONFIG_DM_RESET=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GENERIC=y -+CONFIG_ROCKCHIP_USB2_PHY=y -+CONFIG_USB_KEYBOARD=y -+CONFIG_USB_HOST_ETHER=y -+CONFIG_USB_ETHER_LAN75XX=y -+CONFIG_USB_ETHER_LAN78XX=y -+CONFIG_USB_ETHER_SMSC95XX=y -+CONFIG_ERRNO_STR=y diff --git a/5.4/package/boot/uboot-rockchip/patches/316-uboot-add-NanoPi-R5C-board.patch b/5.4/package/boot/uboot-rockchip/patches/316-uboot-add-NanoPi-R5C-board.patch deleted file mode 100644 index 93722b55..00000000 --- a/5.4/package/boot/uboot-rockchip/patches/316-uboot-add-NanoPi-R5C-board.patch +++ /dev/null @@ -1,224 +0,0 @@ ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -179,7 +179,8 @@ - rk3568-photonicat.dtb \ - rk3566-quartz64-a.dtb \ - rk3568-rock-3a.dtb \ -- rk3568-radxa-e25.dtb -+ rk3568-radxa-e25.dtb \ -+ rk3568-nanopi-r5c.dtb - - dtb-$(CONFIG_ROCKCHIP_RV1108) += \ - rv1108-elgin-r1.dtb \ ---- /dev/null -+++ b/arch/arm/dts/rk3568-nanopi-r5c.dts -@@ -0,0 +1,9 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+/dts-v1/; -+#include "rk3568-evb.dts" -+ -+/ { -+ model = "FriendlyElec NanoPi R5C"; -+ compatible = "friendlyelec,nanopi-r5c", "rockchip,rk3568"; -+}; ---- /dev/null -+++ b/arch/arm/dts/rk3568-nanopi-r5c-u-boot.dtsi -@@ -0,0 +1,25 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd -+ */ -+ -+#include "rk3568-u-boot.dtsi" -+ -+/ { -+ chosen { -+ stdout-path = &uart2; -+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci; -+ }; -+}; -+ -+&sdmmc0 { -+ bus-width = <4>; -+ u-boot,dm-spl; -+ u-boot,spl-fifo-mode; -+}; -+ -+&uart2 { -+ clock-frequency = <24000000>; -+ u-boot,dm-spl; -+ status = "okay"; -+}; ---- a/arch/arm/mach-rockchip/rk3568/Kconfig -+++ b/arch/arm/mach-rockchip/rk3568/Kconfig -@@ -18,6 +18,11 @@ - help - NanoPi R5S FriendlyElec is a board for Rockchp RK3568. - -+config TARGET_NANOPI_R5C_RK3568 -+ bool "NanoPi R5C board" -+ help -+ NanoPi R5C FriendlyElec is a board for Rockchp RK3568. -+ - config TARGET_QUARTZ64_A_RK3566 - bool "Quartz64 Model A RK3566 development board" - help -@@ -40,6 +45,7 @@ - source "board/rockchip/bpi-r2-pro-rk3568/Kconfig" - source "board/rockchip/evb_rk3568/Kconfig" - source "board/friendlyelec/nanopi-r5s-rk3568/Kconfig" -+source "board/friendlyelec/nanopi-r5c-rk3568/Kconfig" - source "board/pine64/quartz64-a-rk3566/Kconfig" - - endif ---- /dev/null -+++ b/board/friendlyelec/nanopi-r5c-rk3568/Kconfig -@@ -0,0 +1,15 @@ -+if TARGET_NANOPI_R5C_RK3568 -+ -+config SYS_BOARD -+ default "nanopi-r5c-rk3568" -+ -+config SYS_VENDOR -+ default "friendlyelec" -+ -+config SYS_CONFIG_NAME -+ default "nanopi-r5c-rk3568" -+ -+config BOARD_SPECIFIC_OPTIONS # dummy -+ def_bool y -+ -+endif ---- /dev/null -+++ b/board/friendlyelec/nanopi-r5c-rk3568/Makefile -@@ -0,0 +1,4 @@ -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+obj-y += nanopi-r5c-rk3568.o ---- /dev/null -+++ b/board/friendlyelec/nanopi-r5c-rk3568/nanopi-r5c-rk3568.c -@@ -0,0 +1,4 @@ -+ // SPDX-License-Identifier: GPL-2.0+ -+/* -+ * -+ */ ---- /dev/null -+++ b/configs/nanopi-r5c-rk3568_defconfig -@@ -0,0 +1,98 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SYS_TEXT_BASE=0x00a00000 -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5c" -+CONFIG_ROCKCHIP_RK3568=y -+CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y -+CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y -+CONFIG_SPL_MMC=y -+CONFIG_SPL_SERIAL=y -+CONFIG_SPL_STACK_R_ADDR=0x600000 -+CONFIG_TARGET_NANOPI_R5C_RK3568=y -+CONFIG_DEBUG_UART_BASE=0xFE660000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEBUG_UART=y -+CONFIG_SYS_LOAD_ADDR=0xc00800 -+CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS=2 -+CONFIG_API=y -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_OF_SYSTEM_SETUP=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5c.dtb" -+# CONFIG_SYS_DEVICE_NULLDEV is not set -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_SPL_STACK_R=y -+CONFIG_SPL_SEPARATE_BSS=y -+CONFIG_SPL_ATF=y -+CONFIG_SPL_ATF_LOAD_IMAGE_V2=y -+CONFIG_CMD_BIND=y -+CONFIG_CMD_CLK=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_USB=y -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_PMIC=y -+CONFIG_CMD_REGULATOR=y -+# CONFIG_SPL_DOS_PARTITION is not set -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_LIVE=y -+CONFIG_NET_RANDOM_ETHADDR=y -+CONFIG_SPL_DM_WARN=y -+CONFIG_SPL_REGMAP=y -+CONFIG_SPL_SYSCON=y -+CONFIG_SPL_CLK=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_ROCKCHIP_GPIO_V2=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_MMC_HS200_SUPPORT=y -+CONFIG_SPL_MMC_HS200_SUPPORT=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_DM_ETH=y -+CONFIG_ETH_DESIGNWARE=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_POWER_DOMAIN=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_SPL_PMIC_RK8XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_SPL_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_SPL_RAM=y -+CONFIG_DM_RESET=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYSRESET=y -+CONFIG_SYSRESET_PSCI=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GENERIC=y -+CONFIG_ROCKCHIP_USB2_PHY=y -+CONFIG_USB_KEYBOARD=y -+CONFIG_USB_HOST_ETHER=y -+CONFIG_USB_ETHER_LAN75XX=y -+CONFIG_USB_ETHER_LAN78XX=y -+CONFIG_USB_ETHER_SMSC95XX=y -+CONFIG_ERRNO_STR=y ---- /dev/null -+++ b/include/configs/nanopi-r5c-rk3568.h -@@ -0,0 +1,14 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+ -+#ifndef __NANOPI_R5C_RK3568_H -+#define __NANOPI_R5C_RK3568_H -+ -+#include -+ -+#define CONFIG_SUPPORT_EMMC_RPMB -+ -+#define ROCKCHIP_DEVICE_SETTINGS \ -+ "stdout=serial,vidconsole\0" \ -+ "stderr=serial,vidconsole\0" -+ -+#endif