From 7829e2185fd4c060df3d010e9a3cf84e0dda0737 Mon Sep 17 00:00:00 2001
From: suyuan168 <175338101@qq.com>
Date: Mon, 4 Jul 2022 17:13:13 +0800
Subject: [PATCH] Update qcom-ipq4019-nhx4019.dts

---
 .../arm/boot/dts/qcom-ipq4019-nhx4019.dts     | 91 +++++++++++++++++++
 1 file changed, 91 insertions(+)

diff --git a/root/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-nhx4019.dts b/root/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-nhx4019.dts
index 348183eb..3d3f7ebb 100755
--- a/root/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-nhx4019.dts
+++ b/root/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-nhx4019.dts
@@ -138,6 +138,45 @@
 			gpio = <&tlmm 0 GPIO_ACTIVE_HIGH>;
 		};
 
+		3vpower {
+			label = "nhx:3vpower";
+			gpio = <&tlmm 19 GPIO_ACTIVE_HIGH>;
+		};
+
+		m2power {
+			label = "nhx:m2power";
+			gpio = <&tlmm 48 GPIO_ACTIVE_LOW>;
+		};
+
+		m2reset {
+			label = "nhx:m2reset";
+			gpio = <&tlmm 49 GPIO_ACTIVE_LOW>;
+		};
+
+		m2dcpower {
+			label = "nhx:m2dcpower";
+			gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>;
+		};
+
+		pcie1dcpower {
+			label = "nhx:pcie1dcpower";
+			gpio = <&tlmm 50 GPIO_ACTIVE_HIGH>;
+		};
+
+		pcie1rst {
+			label = "nhx:pcie1rst";
+			gpio = <&tlmm 42 GPIO_ACTIVE_LOW>;
+		};
+
+		pcie2dcpower {
+			label = "nhx:pcie2dcpower";
+			gpio = <&tlmm 46 GPIO_ACTIVE_HIGH>;
+		};
+
+		pcie2rst {
+			label = "nhx:pcie2rst";
+			gpio = <&tlmm 43 GPIO_ACTIVE_LOW>;
+		};
 	};
 
 	keys {
@@ -149,6 +188,58 @@
 			linux,code = <KEY_RESTART>;
 		};
 	};
+
+	gpio_export {
+		compatible = "gpio-export";
+		#size-cells = <0>;
+
+		3vpower {
+			gpio-export,name = "3v-power";
+			gpio-export,output = <1>;
+			gpio = <&tlmm 19 GPIO_ACTIVE_HIGH>;
+		};
+
+		m2power {
+			gpio-export,name = "m2-power";
+			gpio-export,output = <1>;
+			gpio = <&tlmm 48 GPIO_ACTIVE_LOW>;
+		};
+
+		m2reset {
+			gpio-export,name = "m2-reset";
+			gpio-export,output = <1>;
+			gpio = <&tlmm 49 GPIO_ACTIVE_LOW>;
+		};
+
+		m2dcpower {
+			gpio-export,name = "m2dc-power";
+			gpio-export,output = <1>;
+			gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>;
+		};
+
+		pcie1dcpower {
+			gpio-export,name = "pcie1dc-power";
+			gpio-export,output = <1>;
+			gpio = <&tlmm 50 GPIO_ACTIVE_HIGH>;
+		};
+
+		pcie1rst {
+			gpio-export,name = "pcie1-rst";
+			gpio-export,output = <1>;
+			gpio = <&tlmm 42 GPIO_ACTIVE_LOW>;
+		};
+
+		pcie2dcpower {
+			gpio-export,name = "pcie2dc-power";
+			gpio-export,output = <1>;
+			gpio = <&tlmm 46 GPIO_ACTIVE_HIGH>;
+		};
+		pcie2rst {
+			gpio-export,name = "pcie2-rst";
+			gpio-export,output = <1>;
+			gpio = <&tlmm 43 GPIO_ACTIVE_LOW>;
+		};
+	};
 };
 
 &blsp_dma {