From 788b4dbd8c55debdd293de595ecd47f07a11249f Mon Sep 17 00:00:00 2001 From: suyuan168 <175338101@qq.com> Date: Thu, 6 Jan 2022 00:07:11 +0800 Subject: [PATCH] fix 806x --- root/target/linux/ipq806x/Makefile | 26 + .../ipq806x/base-files/etc/board.d/01_leds | 75 ++ .../ipq806x/base-files/etc/board.d/02_network | 94 ++ .../etc/hotplug.d/firmware/11-ath10k-caldata | 122 +++ .../etc/hotplug.d/ieee80211/10_fix_wifi_mac | 39 + .../ipq806x/base-files/etc/init.d/bootcount | 20 + .../ipq806x/base-files/etc/init.d/cpufreq | 17 + .../linux/ipq806x/base-files/etc/inittab | 4 + .../etc/uci-defaults/04_led_migration | 7 + .../base-files/lib/preinit/04_reorder_eth | 13 + .../lib/preinit/05_set_iface_mac_ipq806x.sh | 14 + .../ipq806x/base-files/lib/upgrade/asrock.sh | 54 + .../ipq806x/base-files/lib/upgrade/buffalo.sh | 44 + .../ipq806x/base-files/lib/upgrade/linksys.sh | 102 ++ .../base-files/lib/upgrade/platform.sh | 71 ++ .../ipq806x/base-files/lib/upgrade/zyxel.sh | 124 +++ .../sbin/asrock_g10_back_to_factory | 15 + .../ipq806x/{config-5.15 => config-5.10} | 9 +- .../arm/boot/dts/qcom-ipq8062-wg2600hp3.dts | 468 +++++++++ .../files/arch/arm/boot/dts/qcom-ipq8062.dtsi | 98 ++ .../boot/dts/qcom-ipq8064-ad7200-c2600.dtsi | 364 +++++++ .../arch/arm/boot/dts/qcom-ipq8064-ad7200.dts | 135 +++ .../arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 121 +++ .../arch/arm/boot/dts/qcom-ipq8064-ap161.dts | 159 +++ .../arch/arm/boot/dts/qcom-ipq8064-c2600.dts | 119 +++ .../arch/arm/boot/dts/qcom-ipq8064-d7800.dts | 371 +++++++ .../arch/arm/boot/dts/qcom-ipq8064-db149.dts | 163 +++ .../arm/boot/dts/qcom-ipq8064-ea7500-v1.dts | 91 ++ .../arch/arm/boot/dts/qcom-ipq8064-ea8500.dts | 128 +++ .../arm/boot/dts/qcom-ipq8064-eax500.dtsi | 207 ++++ .../arch/arm/boot/dts/qcom-ipq8064-g10.dts | 250 +++++ .../arch/arm/boot/dts/qcom-ipq8064-r7500.dts | 316 ++++++ .../arm/boot/dts/qcom-ipq8064-r7500v2.dts | 369 +++++++ .../arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts | 317 ++++++ .../arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi | 69 ++ .../arm/boot/dts/qcom-ipq8064-vr2600v.dts | 393 +++++++ .../arm/boot/dts/qcom-ipq8064-wg2600hp.dts | 436 ++++++++ .../arch/arm/boot/dts/qcom-ipq8064-wpq864.dts | 465 +++++++++ .../arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts | 520 ++++++++++ .../arm/boot/dts/qcom-ipq8065-nbg6817.dts | 316 ++++++ .../arm/boot/dts/qcom-ipq8065-nighthawk.dtsi | 439 ++++++++ .../arch/arm/boot/dts/qcom-ipq8065-r7800.dts | 48 + .../boot/dts/qcom-ipq8065-rt4230w-rev6.dts | 321 ++++++ .../arch/arm/boot/dts/qcom-ipq8065-xr500.dts | 54 + .../files/arch/arm/boot/dts/qcom-ipq8065.dtsi | 167 +++ .../boot/dts/qcom-ipq8068-cryptid-common.dtsi | 239 +++++ .../arm/boot/dts/qcom-ipq8068-ecw5410.dts | 332 ++++++ .../arch/arm/boot/dts/qcom-ipq8068-mr42.dts | 204 ++++ .../arch/arm/boot/dts/qcom-ipq8068-mr52.dts | 230 +++++ root/target/linux/ipq806x/generic/target.mk | 1 + root/target/linux/ipq806x/image/Makefile | 473 +++++++++ root/target/linux/ipq806x/modules.mk | 16 + ...ings-qcom_adm-Fix-channel-specifiers.patch | 0 ...ically-select-PCI_DOMAINS-if-PCI-is-.patch | 0 ...arch-arm-force-ZRELADDR-on-arch-qcom.patch | 2 +- .../0065-arm-override-compiler-flags.patch | 21 + ...Mangle-bootloader-s-kernel-arguments.patch | 4 +- .../0069-arm-boot-add-dts-files.patch | 6 +- .../0072-add-ipq806x-with-no-clocks.patch | 10 + .../082-ipq8064-dtsi-tweaks.patch | 220 ++++ .../083-ipq8064-dtsi-additions.patch | 846 +++++++++++++++ .../084-ipq8064-v1.0-dtsi-cleanup.patch | 0 .../085-ipq8064-v1.0-dtsi-additions.patch | 0 .../086-ipq8064-fix-duplicate-node.patch | 4 +- ...qcom-cpufreq-nvmem-support-specific-.patch | 0 ...7-1-ipq806x-gcc-add-missing-clk-flag.patch | 22 +- .../097-2-ipq806x-lcc-add-missing-reset.patch | 0 ...com-krait-add-missing-enable-disable.patch | 0 ...missing-clk-and-reset-for-crypto-eng.patch | 10 +- ...q-add-Krait-dedicated-scaling-driver.patch | 681 ++++++++++++ ...ufreq-add-qcom-krait-cpufreq-binding.patch | 0 ...add-fab-scaling-support-with-cpufreq.patch | 243 +++++ ...m_nandc-add-boot_layout_mode-support.patch | 239 +++++ ...vicetree-mtd-qcom_nandc-document-qco.patch | 42 + ...-v5.11-dmaengine-qcom-add_ADM_driver.patch | 965 ++++++++++++++++++ ....12-mtd-parsers-Add-Qcom-SMEM-parser.patch | 217 ++++ ...-dwmac-ipq806x-qsgmii-pcs-all-ch-ctl.patch | 2 +- ...conflicts-with-OpenWrt-auto-mounting.patch | 0 ...M-dts-qcom-reduce-pci-IO-size-to-64K.patch | 6 +- ...hermal-tsens-Add-VER_0-tsens-version.patch | 285 ++++++ ...al-tsens-Don-t-hardcode-sensor-slope.patch | 28 + ...l-tsens-Convert-msm8960-to-reg_field.patch | 119 +++ ...al-tsens-Use-init_common-for-msm8960.patch | 81 ++ ...tsens-Fix-bug-in-sensor-enable-for-m.patch | 66 ++ ...tsens-Replace-custom-8960-apis-with-.patch | 109 ++ ...tsens-Drop-unused-define-for-msm8960.patch | 65 ++ ...-tsens-Add-support-for-ipq8064-tsens.patch | 26 + ...rmal-tsens-Document-ipq8064-bindings.patch | 112 ++ ...al-tsens-Fix-wrong-slope-on-msm-8960.patch | 32 + ...ns-init-debugfs-only-with-successful.patch | 0 ...tsens-simplify-debugfs-init-function.patch | 0 ...c-explicitly-deassert-gmac-ahb-reset.patch | 75 ++ ...s-qcom-add-ahb-reset-to-ipq806x-gmac.patch | 64 ++ .../850-soc-add-qualcomm-syscon.patch | 0 .../900-arm-add-cmdline-override.patch | 2 +- .../997-device_tree_cmdline.patch | 0 .../082-ipq8064-dtsi-tweaks.patch | 77 -- .../083-ipq8064-dtsi-additions.patch | 355 ------- .../patches-5.15/851-add-gsbi1-dts.patch | 44 - 99 files changed, 13809 insertions(+), 520 deletions(-) create mode 100755 root/target/linux/ipq806x/Makefile create mode 100755 root/target/linux/ipq806x/base-files/etc/board.d/01_leds create mode 100755 root/target/linux/ipq806x/base-files/etc/board.d/02_network create mode 100755 root/target/linux/ipq806x/base-files/etc/hotplug.d/firmware/11-ath10k-caldata create mode 100755 root/target/linux/ipq806x/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac create mode 100755 root/target/linux/ipq806x/base-files/etc/init.d/bootcount create mode 100755 root/target/linux/ipq806x/base-files/etc/init.d/cpufreq create mode 100755 root/target/linux/ipq806x/base-files/etc/inittab create mode 100755 root/target/linux/ipq806x/base-files/etc/uci-defaults/04_led_migration create mode 100755 root/target/linux/ipq806x/base-files/lib/preinit/04_reorder_eth create mode 100755 root/target/linux/ipq806x/base-files/lib/preinit/05_set_iface_mac_ipq806x.sh create mode 100755 root/target/linux/ipq806x/base-files/lib/upgrade/asrock.sh create mode 100755 root/target/linux/ipq806x/base-files/lib/upgrade/buffalo.sh create mode 100755 root/target/linux/ipq806x/base-files/lib/upgrade/linksys.sh create mode 100755 root/target/linux/ipq806x/base-files/lib/upgrade/platform.sh create mode 100755 root/target/linux/ipq806x/base-files/lib/upgrade/zyxel.sh create mode 100755 root/target/linux/ipq806x/base-files/sbin/asrock_g10_back_to_factory rename root/target/linux/ipq806x/{config-5.15 => config-5.10} (98%) create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062.dtsi create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ap148.dts create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ap161.dts create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-c2600.dts create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-d7800.dts create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-db149.dts create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-g10.dts create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500.dts create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-r7800.dts create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-xr500.dts create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065.dtsi create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr42.dts create mode 100755 root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr52.dts create mode 100755 root/target/linux/ipq806x/generic/target.mk create mode 100755 root/target/linux/ipq806x/image/Makefile create mode 100755 root/target/linux/ipq806x/modules.mk rename root/target/linux/ipq806x/{patches-5.15 => patches-5.10}/0001-dtbindings-qcom_adm-Fix-channel-specifiers.patch (100%) rename root/target/linux/ipq806x/{patches-5.15 => patches-5.10}/0033-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch (100%) rename root/target/linux/ipq806x/{patches-5.15 => patches-5.10}/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch (97%) create mode 100755 root/target/linux/ipq806x/patches-5.10/0065-arm-override-compiler-flags.patch rename root/target/linux/ipq806x/{patches-5.15 => patches-5.10}/0067-generic-Mangle-bootloader-s-kernel-arguments.patch (97%) rename root/target/linux/ipq806x/{patches-5.15 => patches-5.10}/0069-arm-boot-add-dts-files.patch (89%) create mode 100755 root/target/linux/ipq806x/patches-5.10/0072-add-ipq806x-with-no-clocks.patch create mode 100755 root/target/linux/ipq806x/patches-5.10/082-ipq8064-dtsi-tweaks.patch create mode 100755 root/target/linux/ipq806x/patches-5.10/083-ipq8064-dtsi-additions.patch rename root/target/linux/ipq806x/{patches-5.15 => patches-5.10}/084-ipq8064-v1.0-dtsi-cleanup.patch (100%) rename root/target/linux/ipq806x/{patches-5.15 => patches-5.10}/085-ipq8064-v1.0-dtsi-additions.patch (100%) rename root/target/linux/ipq806x/{patches-5.15 => patches-5.10}/086-ipq8064-fix-duplicate-node.patch (98%) rename root/target/linux/ipq806x/{patches-5.15 => patches-5.10}/093-drivers-cpufreq-qcom-cpufreq-nvmem-support-specific-.patch (100%) rename root/target/linux/ipq806x/{patches-5.15 => patches-5.10}/097-1-ipq806x-gcc-add-missing-clk-flag.patch (83%) rename root/target/linux/ipq806x/{patches-5.15 => patches-5.10}/097-2-ipq806x-lcc-add-missing-reset.patch (100%) rename root/target/linux/ipq806x/{patches-5.15 => patches-5.10}/097-3-clk-qcom-krait-add-missing-enable-disable.patch (100%) rename root/target/linux/ipq806x/{patches-5.15 => patches-5.10}/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch (96%) create mode 100755 root/target/linux/ipq806x/patches-5.10/098-1-cpufreq-add-Krait-dedicated-scaling-driver.patch rename root/target/linux/ipq806x/{patches-5.15 => patches-5.10}/098-2-Documentation-cpufreq-add-qcom-krait-cpufreq-binding.patch (100%) create mode 100755 root/target/linux/ipq806x/patches-5.10/098-3-add-fab-scaling-support-with-cpufreq.patch create mode 100755 root/target/linux/ipq806x/patches-5.10/099-1-mtd-nand-raw-qcom_nandc-add-boot_layout_mode-support.patch create mode 100755 root/target/linux/ipq806x/patches-5.10/099-2-Documentation-devicetree-mtd-qcom_nandc-document-qco.patch create mode 100755 root/target/linux/ipq806x/patches-5.10/100-v5.11-dmaengine-qcom-add_ADM_driver.patch create mode 100755 root/target/linux/ipq806x/patches-5.10/101-5.12-mtd-parsers-Add-Qcom-SMEM-parser.patch rename root/target/linux/ipq806x/{patches-5.15 => patches-5.10}/101-dwmac-ipq806x-qsgmii-pcs-all-ch-ctl.patch (97%) rename root/target/linux/ipq806x/{patches-5.15 => patches-5.10}/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch (100%) rename root/target/linux/ipq806x/{patches-5.15 => patches-5.10}/103-ARM-dts-qcom-reduce-pci-IO-size-to-64K.patch (96%) create mode 100755 root/target/linux/ipq806x/patches-5.10/104-1-drivers-thermal-tsens-Add-VER_0-tsens-version.patch create mode 100755 root/target/linux/ipq806x/patches-5.10/104-2-drivers-thermal-tsens-Don-t-hardcode-sensor-slope.patch create mode 100755 root/target/linux/ipq806x/patches-5.10/104-3-drivers-thermal-tsens-Convert-msm8960-to-reg_field.patch create mode 100755 root/target/linux/ipq806x/patches-5.10/104-4-drivers-thermal-tsens-Use-init_common-for-msm8960.patch create mode 100755 root/target/linux/ipq806x/patches-5.10/104-5-drivers-thermal-tsens-Fix-bug-in-sensor-enable-for-m.patch create mode 100755 root/target/linux/ipq806x/patches-5.10/104-6-drivers-thermal-tsens-Replace-custom-8960-apis-with-.patch create mode 100755 root/target/linux/ipq806x/patches-5.10/104-7-drivers-thermal-tsens-Drop-unused-define-for-msm8960.patch create mode 100755 root/target/linux/ipq806x/patches-5.10/104-8-drivers-thermal-tsens-Add-support-for-ipq8064-tsens.patch create mode 100755 root/target/linux/ipq806x/patches-5.10/104-9-dt-bindings-thermal-tsens-Document-ipq8064-bindings.patch create mode 100755 root/target/linux/ipq806x/patches-5.10/105-10-drivers-thermal-tsens-Fix-wrong-slope-on-msm-8960.patch rename root/target/linux/ipq806x/{patches-5.15 => patches-5.10}/107-1-thermal-qcom-tsens-init-debugfs-only-with-successful.patch (100%) rename root/target/linux/ipq806x/{patches-5.15 => patches-5.10}/107-2-thermal-qcom-tsens-simplify-debugfs-init-function.patch (100%) create mode 100755 root/target/linux/ipq806x/patches-5.10/108-v5.14-net-stmmac-explicitly-deassert-gmac-ahb-reset.patch create mode 100755 root/target/linux/ipq806x/patches-5.10/109-v5.15-arm-dts-qcom-add-ahb-reset-to-ipq806x-gmac.patch rename root/target/linux/ipq806x/{patches-5.15 => patches-5.10}/850-soc-add-qualcomm-syscon.patch (100%) rename root/target/linux/ipq806x/{patches-5.15 => patches-5.10}/900-arm-add-cmdline-override.patch (95%) rename root/target/linux/ipq806x/{patches-5.15 => patches-5.10}/997-device_tree_cmdline.patch (100%) delete mode 100755 root/target/linux/ipq806x/patches-5.15/082-ipq8064-dtsi-tweaks.patch delete mode 100755 root/target/linux/ipq806x/patches-5.15/083-ipq8064-dtsi-additions.patch delete mode 100755 root/target/linux/ipq806x/patches-5.15/851-add-gsbi1-dts.patch diff --git a/root/target/linux/ipq806x/Makefile b/root/target/linux/ipq806x/Makefile new file mode 100755 index 00000000..1735235b --- /dev/null +++ b/root/target/linux/ipq806x/Makefile @@ -0,0 +1,26 @@ +# Copyright (c) 2013 The Linux Foundation. All rights reserved. +# +include $(TOPDIR)/rules.mk + +ARCH:=arm +BOARD:=ipq806x +BOARDNAME:=Qualcomm Atheros IPQ806X +FEATURES:=squashfs nand fpu ramdisk +CPU_TYPE:=cortex-a15 +CPU_SUBTYPE:=neon-vfpv4 +SUBTARGETS:=generic + +KERNEL_PATCHVER:=5.10 + +KERNELNAME:=zImage Image dtbs + +include $(INCLUDE_DIR)/target.mk +DEFAULT_PACKAGES += \ + kmod-leds-gpio kmod-gpio-button-hotplug swconfig \ + kmod-ata-ahci kmod-ata-ahci-platform \ + kmod-usb-ohci kmod-usb2 kmod-usb-ledtrig-usbport \ + kmod-phy-qcom-ipq806x-usb kmod-usb3 kmod-usb-dwc3-qcom \ + kmod-ath10k-ct wpad-basic-wolfssl \ + uboot-envtools + +$(eval $(call BuildTarget)) diff --git a/root/target/linux/ipq806x/base-files/etc/board.d/01_leds b/root/target/linux/ipq806x/base-files/etc/board.d/01_leds new file mode 100755 index 00000000..2b259b90 --- /dev/null +++ b/root/target/linux/ipq806x/base-files/etc/board.d/01_leds @@ -0,0 +1,75 @@ +# +# Copyright (C) 2015 OpenWrt.org +# + +. /lib/functions/uci-defaults.sh + +board_config_update + +board=$(board_name) + +case "$board" in +buffalo,wxr-2533dhp) + ucidef_set_led_wlan "wlan" "WLAN" "white:wireless" "phy0tpt" + ucidef_set_led_switch "wan" "WAN" "white:internet" "switch0" "0x20" + ;; +compex,wpq864) + ucidef_set_led_usbport "usb" "USB" "green:usb" "usb1-port1" "usb2-port1" + ucidef_set_led_usbport "pcie-usb" "PCIe USB" "green:usb-pcie" "usb3-port1" + ;; +edgecore,ecw5410) + ucidef_set_led_wlan "wlan2g" "WLAN2G" "green:wlan2g" "phy1tpt" + ucidef_set_led_wlan "wlan5g" "WLAN5G" "green:wlan5g" "phy0tpt" + ;; +meraki,mr52) + ucidef_set_led_netdev "eth0" "eth0" "green:lan1" "eth0" + ucidef_set_led_netdev "eth1" "eth1" "green:lan2" "eth1" + ;; +nec,wg2600hp) + ucidef_set_led_wlan "wlan2g" "WLAN2G" "green:wlan2g" "phy1tpt" + ucidef_set_led_wlan "wlan5g" "WLAN5G" "green:wlan5g" "phy0tpt" + ucidef_set_led_switch "wan" "WAN" "green:active" "switch0" "0x2" + ;; +nec,wg2600hp3) + ucidef_set_led_switch "wan" "WAN" "green:active" "switch0" "0x2" + ;; +netgear,d7800 |\ +netgear,r7500 |\ +netgear,r7500v2 |\ +netgear,r7800 |\ +netgear,xr500) + ucidef_set_led_usbport "usb1" "USB 1" "white:usb1" "usb1-port1" "usb2-port1" + ucidef_set_led_usbport "usb2" "USB 2" "white:usb2" "usb3-port1" "usb4-port1" + ucidef_set_led_switch "wan" "WAN" "white:wan" "switch0" "0x20" + ucidef_set_led_ide "esata" "eSATA" "white:esata" + ;; +tplink,ad7200) + ucidef_set_led_usbport "usb1" "USB 1" "blue:usb1" "usb1-port1" "usb2-port1" + ucidef_set_led_usbport "usb2" "USB 2" "blue:usb3" "usb3-port1" "usb4-port1" + ucidef_set_led_switch "wan" "wan" "blue:wan" "switch0" "0x02" + ucidef_set_led_switch "lan" "lan" "blue:lan" "switch0" "0x3c" + ucidef_set_led_wlan "wlan2g" "wlan2g" "blue:wlan2g" "phy2tpt" + ucidef_set_led_wlan "wlan5g" "wlan5g" "blue:wlan5g" "phy1tpt" + ucidef_set_led_netdev "wlan60g" "wlan60g" "blue:wlan60g" "wlan0" + ;; +tplink,c2600) + ucidef_set_led_usbport "usb1" "USB 1" "white:usb_2" "usb1-port1" "usb2-port1" + ucidef_set_led_usbport "usb2" "USB 2" "white:usb_4" "usb3-port1" "usb4-port1" + ucidef_set_led_switch "wan" "wan" "white:wan" "switch0" "0x20" + ucidef_set_led_switch "lan" "lan" "white:lan" "switch0" "0x1e" + ;; +tplink,vr2600v) + ucidef_set_led_usbport "usb" "USB" "white:usb" "usb1-port1" "usb2-port1" "usb3-port1" "usb4-port1" + ucidef_set_led_switch "lan" "lan" "white:lan" "switch0" "0x1e" + ucidef_set_led_wlan "wlan2g" "WLAN2G" "white:wlan2g" "phy0tpt" + ucidef_set_led_wlan "wlan5g" "WLAN5G" "white:wlan5g" "phy1tpt" + ucidef_set_led_switch "wan" "wan" "white:wan" "switch0" "0x20" + ;; +zyxel,nbg6817) + ucidef_set_led_netdev "wan" "WAN" "white:internet" "eth1" + ;; +esac + +board_config_flush + +exit 0 diff --git a/root/target/linux/ipq806x/base-files/etc/board.d/02_network b/root/target/linux/ipq806x/base-files/etc/board.d/02_network new file mode 100755 index 00000000..4cb691f3 --- /dev/null +++ b/root/target/linux/ipq806x/base-files/etc/board.d/02_network @@ -0,0 +1,94 @@ +# +# Copyright (c) 2015 The Linux Foundation. All rights reserved. +# Copyright (c) 2011-2015 OpenWrt.org +# + +. /lib/functions/uci-defaults.sh +. /lib/functions/system.sh + +board_config_update + +board=$(board_name) + +case "$board" in +askey,rt4230w-rev6 |\ +asrock,g10 |\ +nec,wg2600hp) + ucidef_add_switch "switch0" \ + "2:lan" "3:lan" "4:lan" "5:lan" "6@eth1" "1:wan" "0@eth0" + ;; +buffalo,wxr-2533dhp |\ +compex,wpq864 |\ +netgear,d7800 |\ +netgear,r7500 |\ +netgear,r7500v2 |\ +qcom,ipq8064-ap148 |\ +tplink,vr2600v) + ucidef_add_switch "switch0" \ + "1:lan" "2:lan" "3:lan" "4:lan" "6@eth1" "5:wan" "0@eth0" + ;; +edgecore,ecw5410) + ucidef_set_interfaces_lan_wan "eth1" "eth0" + ;; +linksys,ea7500-v1) + hw_mac_addr=$(mtd_get_mac_ascii devinfo hw_mac_addr) + ucidef_add_switch "switch0" \ + "2:lan:1" "3:lan:2" "4:lan:3" "5:lan:4" "6@eth1" "1:wan" "0@eth0" + ucidef_set_interface_macaddr "lan" "$hw_mac_addr" + ucidef_set_interface_macaddr "wan" "$hw_mac_addr" + ;; +linksys,ea8500) + hw_mac_addr=$(mtd_get_mac_ascii devinfo hw_mac_addr) + ucidef_add_switch "switch0" \ + "1:lan" "2:lan" "3:lan" "4:lan" "6@eth1" "5:wan" "0@eth0" + ucidef_set_interface_macaddr "lan" "$hw_mac_addr" + ucidef_set_interface_macaddr "wan" "$hw_mac_addr" + ;; +meraki,mr42) + ucidef_set_interface_lan "eth0" + ;; +meraki,mr52) + ucidef_set_interfaces_lan_wan "eth0" "eth1" + ;; +nec,wg2600hp3) + ucidef_add_switch "switch0" \ + "2:lan" "3:lan" "4:lan" "5:lan" "0@eth1" "1:wan" "6@eth0" + ;; +netgear,r7800 |\ +netgear,xr500 |\ +tplink,c2600) + ucidef_add_switch "switch0" \ + "1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1" "6@eth1" "5:wan" "0@eth0" + ;; +qcom,ipq8064-ap161) + ucidef_set_interface_lan "eth1 eth2" + ucidef_add_switch "switch0" \ + "0:lan" "1:lan" "2:lan" "3u@eth1" "6:wan" "4u@eth0" + ;; +qcom,ipq8064-db149) + ucidef_set_interface_lan "eth1 eth2 eth3" + ucidef_add_switch "switch0" \ + "1:lan" "2:lan" "3:lan" "4:lan" "6u@eth1" "5:wan" "0u@eth0" + ;; +tplink,ad7200) + ucidef_add_switch "switch0" \ + "2:lan:1" "3:lan:2" "4:lan:3" "5:lan:4" "6@eth1" "1:wan" "0@eth0" + ;; +ubnt,unifi-ac-hd) + ucidef_set_interface_lan "eth0 eth1" + ;; +zyxel,nbg6817) + hw_mac_addr=$(mtd_get_mac_ascii 0:appsblenv ethaddr) + ucidef_add_switch "switch0" \ + "1:lan" "2:lan" "3:lan" "4:lan" "6@eth1" "5:wan" "0@eth0" + ucidef_set_interface_macaddr "lan" "$(macaddr_add $hw_mac_addr 2)" + ucidef_set_interface_macaddr "wan" "$(macaddr_add $hw_mac_addr 3)" + ;; +*) + echo "Unsupported hardware. Network interfaces not intialized" + ;; +esac + +board_config_flush + +exit 0 diff --git a/root/target/linux/ipq806x/base-files/etc/hotplug.d/firmware/11-ath10k-caldata b/root/target/linux/ipq806x/base-files/etc/hotplug.d/firmware/11-ath10k-caldata new file mode 100755 index 00000000..78315d45 --- /dev/null +++ b/root/target/linux/ipq806x/base-files/etc/hotplug.d/firmware/11-ath10k-caldata @@ -0,0 +1,122 @@ +#!/bin/sh + +[ -e /lib/firmware/$FIRMWARE ] && exit 0 + +. /lib/functions/caldata.sh + +board=$(board_name) + +case "$FIRMWARE" in +"ath10k/cal-pci-0000:01:00.0.bin") + case "$board" in + meraki,mr52) + CI_UBIPART=art + caldata_extract_ubi "ART" 0x1000 0x844 + ;; + esac + ;; +"ath10k/pre-cal-pci-0000:01:00.0.bin") + case $board in + askey,rt4230w-rev6) + caldata_extract "0:ART" 0x1000 0x2f20 + ;; + asrock,g10) + caldata_extract "0:art" 0x1000 0x2f20 + ;; + buffalo,wxr-2533dhp |\ + nec,wg2600hp |\ + nec,wg2600hp3 |\ + tplink,vr2600v) + caldata_extract "ART" 0x1000 0x2f20 + ;; + linksys,ea7500-v1 |\ + linksys,ea8500) + caldata_extract "art" 0x1000 0x2f20 + ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii devinfo hw_mac_addr) 1) + ;; + meraki,mr42) + CI_UBIPART=art + caldata_extract_ubi "ART" 0x1000 0x2f20 + ;; + netgear,d7800 |\ + netgear,r7500v2 |\ + netgear,r7800 |\ + netgear,xr500) + caldata_extract "art" 0x1000 0x2f20 + ;; + tplink,ad7200 |\ + tplink,c2600) + caldata_extract "radio" 0x1000 0x2f20 + ;; + zyxel,nbg6817) + caldata_extract "0:art" 0x1000 0x2f20 + ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii 0:appsblenv ethaddr) 1) + ;; + esac + ;; +"ath10k/pre-cal-pci-0001:01:00.0.bin") + case $board in + askey,rt4230w-rev6) + caldata_extract "0:ART" 0x5000 0x2f20 + ;; + asrock,g10) + caldata_extract "0:art" 0x5000 0x2f20 + ;; + buffalo,wxr-2533dhp |\ + nec,wg2600hp |\ + nec,wg2600hp3 |\ + tplink,vr2600v) + caldata_extract "ART" 0x5000 0x2f20 + ;; + edgecore,ecw5410) + caldata_extract "0:art" 0x1000 0x2f20 + ;; + linksys,ea7500-v1 |\ + linksys,ea8500) + caldata_extract "art" 0x5000 0x2f20 + ath10k_patch_mac $(macaddr_add $(mtd_get_mac_ascii devinfo hw_mac_addr) 2) + ;; + meraki,mr42 |\ + meraki,mr52) + CI_UBIPART=art + caldata_extract_ubi "ART" 0x5000 0x2f20 + ;; + netgear,d7800 |\ + netgear,r7500v2 |\ + netgear,r7800 |\ + netgear,xr500) + caldata_extract "art" 0x5000 0x2f20 + ;; + tplink,ad7200 |\ + tplink,c2600) + caldata_extract "radio" 0x5000 0x2f20 + ;; + zyxel,nbg6817) + caldata_extract "0:art" 0x5000 0x2f20 + ath10k_patch_mac $(mtd_get_mac_ascii 0:appsblenv ethaddr) + ;; + esac + ;; +"ath10k/cal-pci-0002:01:00.0.bin") + case "$board" in + meraki,mr42) + CI_UBIPART=art + caldata_extract_ubi "ART" 0x9000 0x844 + ;; + esac + ;; +"ath10k/pre-cal-pci-0002:01:00.0.bin") + case $board in + edgecore,ecw5410) + caldata_extract "0:art" 0x5000 0x2f20 + ;; + meraki,mr52) + CI_UBIPART=art + caldata_extract_ubi "ART" 0x9000 0x2f20 + ;; + esac + ;; +*) + exit 1 + ;; +esac diff --git a/root/target/linux/ipq806x/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac b/root/target/linux/ipq806x/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac new file mode 100755 index 00000000..5af3a5b8 --- /dev/null +++ b/root/target/linux/ipq806x/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac @@ -0,0 +1,39 @@ +#!/bin/ash + +[ "$ACTION" == "add" ] || exit 0 + +PHYNBR=${DEVPATH##*/phy} + +[ -n $PHYNBR ] || exit 0 + +. /lib/functions.sh +. /lib/functions/system.sh + +board=$(board_name) + +case "$board" in + ubnt,unifi-ac-hd) + macaddr_add $(mtd_get_mac_binary EEPROM 0x6) $(($PHYNBR + 1)) > /sys${DEVPATH}/macaddress + ;; +esac + +OPATH=${DEVPATH##/devices/platform/} +OPATH=${OPATH%%/ieee*} + +# 10 radios is enough for anyone! +for i in $(seq 0 9); + do + BUS=$(uci get wireless.@wifi-device[$i].path) + if [ "$BUS " == "$OPATH " ] + then + PHYNAME=${DEVPATH##*ieee80211/} + NPHYNAME=$(uci get wireless.@wifi-device[$i].phyname) + if [ "$NPHYNAME " != " " ] + then + if [ "$PHYNAME " != "$NPHYNAME " ] + then + iw $PHYNAME set name $NPHYNAME + fi + fi + fi +done diff --git a/root/target/linux/ipq806x/base-files/etc/init.d/bootcount b/root/target/linux/ipq806x/base-files/etc/init.d/bootcount new file mode 100755 index 00000000..cb32a4ed --- /dev/null +++ b/root/target/linux/ipq806x/base-files/etc/init.d/bootcount @@ -0,0 +1,20 @@ +#!/bin/sh /etc/rc.common + +START=99 + +. "$IPKG_INSTROOT/lib/upgrade/asrock.sh" + +boot() { + case $(board_name) in + asrock,g10) + asrock_bootconfig_mangle "bootcheck" && reboot + ;; + edgecore,ecw5410) + fw_setenv bootcount 0 + ;; + linksys,ea7500-v1 |\ + linksys,ea8500) + mtd resetbc s_env || true + ;; + esac +} diff --git a/root/target/linux/ipq806x/base-files/etc/init.d/cpufreq b/root/target/linux/ipq806x/base-files/etc/init.d/cpufreq new file mode 100755 index 00000000..19278902 --- /dev/null +++ b/root/target/linux/ipq806x/base-files/etc/init.d/cpufreq @@ -0,0 +1,17 @@ +#!/bin/sh /etc/rc.common + +START=15 + +boot() { + local governor + + governor=$(cat /sys/devices/system/cpu/cpufreq/policy0/scaling_governor) + + if [ "$governor" = "ondemand" ]; then + # Effective only with ondemand + echo 600000 > /sys/devices/system/cpu/cpufreq/policy0/scaling_min_freq + echo 600000 > /sys/devices/system/cpu/cpufreq/policy1/scaling_min_freq + echo 10 > /sys/devices/system/cpu/cpufreq/ondemand/sampling_down_factor + echo 50 > /sys/devices/system/cpu/cpufreq/ondemand/up_threshold + fi +} diff --git a/root/target/linux/ipq806x/base-files/etc/inittab b/root/target/linux/ipq806x/base-files/etc/inittab new file mode 100755 index 00000000..809bba5e --- /dev/null +++ b/root/target/linux/ipq806x/base-files/etc/inittab @@ -0,0 +1,4 @@ +# Copyright (c) 2013 The Linux Foundation. All rights reserved. +::sysinit:/etc/init.d/rcS S boot +::shutdown:/etc/init.d/rcS K shutdown +ttyMSM0::askfirst:/usr/libexec/login.sh diff --git a/root/target/linux/ipq806x/base-files/etc/uci-defaults/04_led_migration b/root/target/linux/ipq806x/base-files/etc/uci-defaults/04_led_migration new file mode 100755 index 00000000..e56062ba --- /dev/null +++ b/root/target/linux/ipq806x/base-files/etc/uci-defaults/04_led_migration @@ -0,0 +1,7 @@ +. /lib/functions/migrations.sh + +remove_devicename_leds + +migrations_apply system + +exit 0 diff --git a/root/target/linux/ipq806x/base-files/lib/preinit/04_reorder_eth b/root/target/linux/ipq806x/base-files/lib/preinit/04_reorder_eth new file mode 100755 index 00000000..9f584736 --- /dev/null +++ b/root/target/linux/ipq806x/base-files/lib/preinit/04_reorder_eth @@ -0,0 +1,13 @@ +. /lib/functions.sh + +preinit_reorder_eth() { + case $(board_name) in + ubnt,unifi-ac-hd) + ip link set eth0 name ethtmp + ip link set eth1 name eth0 + ip link set ethtmp name eth1 + ;; + esac +} + +boot_hook_add preinit_main preinit_reorder_eth diff --git a/root/target/linux/ipq806x/base-files/lib/preinit/05_set_iface_mac_ipq806x.sh b/root/target/linux/ipq806x/base-files/lib/preinit/05_set_iface_mac_ipq806x.sh new file mode 100755 index 00000000..ca8d0b15 --- /dev/null +++ b/root/target/linux/ipq806x/base-files/lib/preinit/05_set_iface_mac_ipq806x.sh @@ -0,0 +1,14 @@ +. /lib/functions.sh + +preinit_set_mac_address() { + case $(board_name) in + asrock,g10) + lan_mac=$(mtd_get_mac_ascii hwconfig HW.LAN.MAC.Address) + wan_mac=$(mtd_get_mac_ascii hwconfig HW.WAN.MAC.Address) + ip link set dev eth0 address "${lan_mac}" + ip link set dev eth1 address "${wan_mac}" + ;; + esac +} + +boot_hook_add preinit_main preinit_set_mac_address diff --git a/root/target/linux/ipq806x/base-files/lib/upgrade/asrock.sh b/root/target/linux/ipq806x/base-files/lib/upgrade/asrock.sh new file mode 100755 index 00000000..9645b646 --- /dev/null +++ b/root/target/linux/ipq806x/base-files/lib/upgrade/asrock.sh @@ -0,0 +1,54 @@ +. /lib/functions.sh + +asrock_bootconfig_mangle() { + local mtdnum="$(find_mtd_index 0:bootconfig)" + + if [ -z "$mtdnum" ]; then + echo "cannot find bootconfig mtd partition" + return 1 + fi + dd if=/dev/mtd$mtdnum of=/tmp/mtd$mtdnum bs=1k + + local partition_byte="$(dd if=/tmp/mtd$mtdnum bs=1 skip=52 count=1)" + local upgrade_byte="$(dd if=/tmp/mtd$mtdnum bs=1 skip=4 count=1)" + + if [ $1 = "bootcheck" ]; then + if [ ! -s $upgrade_byte ]; then + dd if=/dev/mtd$mtdnum of=/tmp/mtd$mtdnum bs=1k + printf '\x00' | dd of=/tmp/mtd$mtdnum conv=notrunc bs=1 seek=4 + printf '\x00' | dd of=/tmp/mtd$mtdnum conv=notrunc bs=1 seek=56 + else + return 1 + fi + elif [ $1 = "sysupgrade" ]; then + printf '\x01' | dd of=/tmp/mtd$mtdnum conv=notrunc bs=1 seek=4 + printf '\x01' | dd of=/tmp/mtd$mtdnum conv=notrunc bs=1 seek=56 + fi + + if [ -s $partition_byte ]; then + printf '\x01' | dd of=/tmp/mtd$mtdnum conv=notrunc bs=1 seek=52 + else + printf '\x00' | dd of=/tmp/mtd$mtdnum conv=notrunc bs=1 seek=52 + fi + + mtd write /tmp/mtd$mtdnum /dev/mtd$mtdnum + return 0 +} + +asrock_upgrade_prepare() { + local ubidev="$( nand_find_ubi ubi )" + + #Set upgrade flag. If something goes wrong, router will boot with + #factory firmware. + asrock_bootconfig_mangle 'sysupgrade' + + if [ $? -ne 0 ]; then + echo "cannot find bootconfig mtd partition" + exit 1 + fi + + # Just delete these partitions if present and use + # OpenWrt's standard names for those. + ubirmvol /dev/$ubidev -N ubi_rootfs &> /dev/null || true + ubirmvol /dev/$ubidev -N ubi_rootfs_data &> /dev/null || true +} diff --git a/root/target/linux/ipq806x/base-files/lib/upgrade/buffalo.sh b/root/target/linux/ipq806x/base-files/lib/upgrade/buffalo.sh new file mode 100755 index 00000000..6a51de4e --- /dev/null +++ b/root/target/linux/ipq806x/base-files/lib/upgrade/buffalo.sh @@ -0,0 +1,44 @@ +# Copyright (C) 2018 OpenWrt.org +# + +. /lib/functions.sh + +# The mtd partition 'ubi' and 'rootfs_1' on NAND flash are os-image +# partitions. These partitions are called as "Bank1/Bank2" in U-Boot +# on WXR-2533DHP, and they are checked conditions when booting. +# Then, U-Boot checks kernel and rootfs volumes in ubi, but U-Boot +# needs "ubi_rootfs" as rootfs volume name. And, U-Boot checks the +# checksum at the end of rootfs (ubi_rootfs). +# When U-Boot writes os-image into the Bank, only kernel, rootfs +# (ubi_rootfs) and rootfs_data (ubi_rootfs_data) volumes are wrote +# into the Bank. (not full ubi image) +# +# == U-Boot Behaviors == +# - Bank1/Bank2 images are good, images are different +# -> writes os-image to Bank1 from Bank2 +# (this behavior is used to firmware upgrade in stock firmware) +# - Bank1 image is broken (or checksum error) +# -> writes os-image to Bank1 from Bank2 +# - Bank2 image is broken (or checksum error) +# -> writes os-image to Bank2 from Bank1 +# - Bank1/Bank2 images are broken (or checksum error) +# -> start tftp + +buffalo_upgrade_prepare_ubi() { + local ubidev="$( nand_find_ubi ubi )" + local mtdnum2="$( find_mtd_index rootfs_1 )" + + if [ ! "$mtdnum2" ]; then + echo "cannot find second ubi mtd partition rootfs_1" + return 1 + fi + + local ubidev2="$( nand_find_ubi rootfs_1 )" + if [ ! "$ubidev2" ] && [ -n "$mtdnum2" ]; then + ubiattach -m "$mtdnum2" + ubidev2="$( nand_find_ubi rootfs_1 )" + fi + + ubirmvol /dev/$ubidev -N ubi_rootfs_data &> /dev/null || true + ubirmvol /dev/$ubidev2 -N kernel &> /dev/null || true +} diff --git a/root/target/linux/ipq806x/base-files/lib/upgrade/linksys.sh b/root/target/linux/ipq806x/base-files/lib/upgrade/linksys.sh new file mode 100755 index 00000000..29f47634 --- /dev/null +++ b/root/target/linux/ipq806x/base-files/lib/upgrade/linksys.sh @@ -0,0 +1,102 @@ +# +# Copyright (C) 2014-2015 OpenWrt.org +# + +linksys_get_target_firmware() { + + local cur_boot_part mtd_ubi0 + + cur_boot_part=$(/usr/sbin/fw_printenv -n boot_part) + if [ -z "${cur_boot_part}" ] ; then + mtd_ubi0=$(cat /sys/devices/virtual/ubi/ubi0/mtd_num) + case $(egrep ^mtd${mtd_ubi0}: /proc/mtd | cut -d '"' -f 2) in + kernel1|rootfs1) + cur_boot_part=1 + ;; + kernel2|rootfs2) + cur_boot_part=2 + ;; + esac + >&2 printf "Current boot_part='%s' selected from ubi0/mtd_num='%s'" \ + "${cur_boot_part}" "${mtd_ubi0}" + fi + + case $cur_boot_part in + 1) + fw_setenv -s - <<-EOF + boot_part 2 + auto_recovery yes + EOF + printf "kernel2" + return + ;; + 2) + fw_setenv -s - <<-EOF + boot_part 1 + auto_recovery yes + EOF + printf "kernel1" + return + ;; + *) + return + ;; + esac +} + +platform_do_upgrade_linksys() { + local magic_long="$(get_magic_long "$1")" + + mkdir -p /var/lock + local part_label="$(linksys_get_target_firmware)" + touch /var/lock/fw_printenv.lock + + if [ ! -n "$part_label" ] + then + echo "cannot find target partition" + exit 1 + fi + + local target_mtd=$(find_mtd_part $part_label) + + [ "$magic_long" = "73797375" ] && { + CI_KERNPART="$part_label" + if [ "$part_label" = "kernel1" ] + then + CI_UBIPART="rootfs1" + else + CI_UBIPART="rootfs2" + fi + + + # remove "squashfs" vol (in case we are flashing over a stock image, which is also UBI) + + local mtdnum="$( find_mtd_index "$CI_UBIPART" )" + if [ ! "$mtdnum" ]; then + echo "cannot find ubi mtd partition $CI_UBIPART" + return 1 + fi + + local ubidev="$( nand_find_ubi "$CI_UBIPART" )" + if [ ! "$ubidev" ]; then + ubiattach -m "$mtdnum" + sync + ubidev="$( nand_find_ubi "$CI_UBIPART" )" + fi + + if [ "$ubidev" ]; then + + local squash_ubivol="$( nand_find_volume $ubidev squashfs )" + + # kill volume + [ "$squash_ubivol" ] && ubirmvol /dev/$ubidev -N squashfs || true + fi + + + # complete std upgrade + nand_upgrade_tar "$1" + } + [ "$magic_long" = "27051956" ] && { + get_image "$1" | mtd write - $part_label + } +} diff --git a/root/target/linux/ipq806x/base-files/lib/upgrade/platform.sh b/root/target/linux/ipq806x/base-files/lib/upgrade/platform.sh new file mode 100755 index 00000000..3d96457d --- /dev/null +++ b/root/target/linux/ipq806x/base-files/lib/upgrade/platform.sh @@ -0,0 +1,71 @@ +PART_NAME=firmware +REQUIRE_IMAGE_METADATA=1 + +RAMFS_COPY_BIN='fw_printenv fw_setenv' +RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock' + +platform_check_image() { + return 0; +} + +platform_do_upgrade() { + case "$(board_name)" in + askey,rt4230w-rev6 |\ + compex,wpq864|\ + netgear,d7800 |\ + netgear,r7500 |\ + netgear,r7500v2 |\ + netgear,r7800 |\ + netgear,xr500 |\ + qcom,ipq8064-ap148 |\ + qcom,ipq8064-ap161) + nand_do_upgrade "$1" + ;; + asrock,g10) + asrock_upgrade_prepare + nand_do_upgrade "$1" + ;; + buffalo,wxr-2533dhp) + buffalo_upgrade_prepare_ubi + CI_ROOTPART="ubi_rootfs" + nand_do_upgrade "$1" + ;; + edgecore,ecw5410) + part="$(awk -F 'ubi.mtd=' '{printf $2}' /proc/cmdline | sed -e 's/ .*$//')" + if [ "$part" = "rootfs1" ]; then + fw_setenv active 2 || exit 1 + CI_UBIPART="rootfs2" + else + fw_setenv active 1 || exit 1 + CI_UBIPART="rootfs1" + fi + nand_do_upgrade "$1" + ;; + linksys,ea7500-v1 |\ + linksys,ea8500) + platform_do_upgrade_linksys "$1" + ;; + meraki,mr42 |\ + meraki,mr52) + CI_KERNPART="bootkernel2" + nand_do_upgrade "$1" + ;; + tplink,ad7200 |\ + tplink,c2600) + PART_NAME="os-image:rootfs" + MTD_CONFIG_ARGS="-s 0x200000" + default_do_upgrade "$1" + ;; + tplink,vr2600v) + PART_NAME="kernel:rootfs" + MTD_CONFIG_ARGS="-s 0x200000" + default_do_upgrade "$1" + ;; + zyxel,nbg6817) + zyxel_do_upgrade "$1" + ;; + *) + default_do_upgrade "$1" + ;; + esac +} diff --git a/root/target/linux/ipq806x/base-files/lib/upgrade/zyxel.sh b/root/target/linux/ipq806x/base-files/lib/upgrade/zyxel.sh new file mode 100755 index 00000000..f5501822 --- /dev/null +++ b/root/target/linux/ipq806x/base-files/lib/upgrade/zyxel.sh @@ -0,0 +1,124 @@ +# +# Copyright (C) 2016 lede-project.org +# + +zyxel_get_rootfs() { + local rootfsdev + + if read cmdline < /proc/cmdline; then + case "$cmdline" in + *root=*) + rootfsdev="${cmdline##*root=}" + rootfsdev="${rootfsdev%% *}" + ;; + esac + + echo "${rootfsdev}" + fi +} + +zyxel_do_flash() { + local tar_file=$1 + local kernel=$2 + local rootfs=$3 + local dualflagmtd=$4 + + # keep sure its unbound + losetup --detach-all || { + echo Failed to detach all loop devices. Skip this try. + reboot -f + } + + # use the first found directory in the tar archive + local board_dir=$(tar tf $tar_file | grep -m 1 '^sysupgrade-.*/$') + board_dir=${board_dir%/} + + echo "flashing kernel to $kernel" + tar xf $tar_file ${board_dir}/kernel -O >$kernel + + echo "flashing rootfs to ${rootfs}" + tar xf $tar_file ${board_dir}/root -O >"${rootfs}" + + # a padded rootfs is needed for overlay fs creation + local offset=$(tar xf $tar_file ${board_dir}/root -O | wc -c) + [ $offset -lt 65536 ] && { + echo Wrong size for rootfs: $offset + sleep 10 + reboot -f + } + + # Mount loop for rootfs_data + local loopdev="$(losetup -f)" + losetup -o $offset $loopdev $rootfs || { + echo "Failed to mount looped rootfs_data." + sleep 10 + reboot -f + } + + echo "Format new rootfs_data at position ${offset}." + mkfs.ext4 -F -L rootfs_data $loopdev + mkdir /tmp/new_root + mount -t ext4 $loopdev /tmp/new_root && { + echo "Saving config to rootfs_data at position ${offset}." + cp -v "$UPGRADE_BACKUP" "/tmp/new_root/$BACKUP_FILE" + umount /tmp/new_root + } + + # flashing successful, toggle the dualflag + case "$rootfs" in + "/dev/mmcblk0p5") + printf "\xff" >$dualflagmtd + ;; + "/dev/mmcblk0p8") + printf "\x01" >$dualflagmtd + ;; + esac + + # Cleanup + losetup -d $loopdev >/dev/null 2>&1 + sync + umount -a + reboot -f +} + +zyxel_do_upgrade() { + local tar_file="$1" + local board=$(board_name) + local rootfs="$(zyxel_get_rootfs)" + local kernel= + + [ -b "${rootfs}" ] || return 1 + case "$board" in + zyxel,nbg6817) + local dualflagmtd="$(find_mtd_part 0:dual_flag)" + [ -b $dualflagmtd ] || return 1 + + case "$rootfs" in + "/dev/mmcblk0p5") + # booted from the primary partition set + # write to the alternative set + kernel="/dev/mmcblk0p7" + rootfs="/dev/mmcblk0p8" + ;; + "/dev/mmcblk0p8") + # booted from the alternative partition set + # write to the primary set + kernel="/dev/mmcblk0p4" + rootfs="/dev/mmcblk0p5" + ;; + *) + return 1 + ;; + esac + ;; + *) + return 1 + ;; + esac + + zyxel_do_flash $tar_file $kernel $rootfs $dualflagmtd + + nand_do_upgrade "$1" + + return 0 +} diff --git a/root/target/linux/ipq806x/base-files/sbin/asrock_g10_back_to_factory b/root/target/linux/ipq806x/base-files/sbin/asrock_g10_back_to_factory new file mode 100755 index 00000000..0ab6f176 --- /dev/null +++ b/root/target/linux/ipq806x/base-files/sbin/asrock_g10_back_to_factory @@ -0,0 +1,15 @@ +#!/bin/sh + +. /lib/upgrade/asrock.sh + +case $(board_name) in +asrock,g10) + asrock_bootconfig_mangle "factory" + if [ $? -eq 0 ]; then + reboot + fi + ;; +*) + echo "Unsupported hardware." + ;; +esac diff --git a/root/target/linux/ipq806x/config-5.15 b/root/target/linux/ipq806x/config-5.10 similarity index 98% rename from root/target/linux/ipq806x/config-5.15 rename to root/target/linux/ipq806x/config-5.10 index 77d1bbda..35da3dd3 100755 --- a/root/target/linux/ipq806x/config-5.15 +++ b/root/target/linux/ipq806x/config-5.10 @@ -99,24 +99,17 @@ CONFIG_CRC16=y # CONFIG_CRC32_SARWATE is not set CONFIG_CRC32_SLICEBY8=y CONFIG_CRYPTO_ACOMP2=y -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_DEV_QCOM_RNG=y CONFIG_CRYPTO_DRBG=y CONFIG_CRYPTO_DRBG_HMAC=y CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_HASH_INFO=y CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_HW=y CONFIG_CRYPTO_JITTERENTROPY=y CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_NULL2=y CONFIG_CRYPTO_RNG=y CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_SHA256=y @@ -144,6 +137,7 @@ CONFIG_DWMAC_IPQ806X=y CONFIG_DYNAMIC_DEBUG=y CONFIG_EDAC_ATOMIC_SCRUB=y CONFIG_EDAC_SUPPORT=y +CONFIG_ETHERNET_PACKET_MANGLE=y CONFIG_FIXED_PHY=y CONFIG_FIX_EARLYCON_MEM=y CONFIG_FW_LOADER_PAGED_BUF=y @@ -219,7 +213,6 @@ CONFIG_KRAITCC=y CONFIG_KRAIT_CLOCKS=y CONFIG_KRAIT_L2_ACCESSORS=y CONFIG_LIBFDT=y -CONFIG_LLD_VERSION=0 CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_LOCK_SPIN_ON_OWNER=y CONFIG_LZO_COMPRESS=y diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts new file mode 100755 index 00000000..8f1bb745 --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062-wg2600hp3.dts @@ -0,0 +1,468 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq8062.dtsi" +#include + +/delete-node/ &nand_pins; + +/ { + model = "NEC Platforms Aterm WG2600HP3"; + compatible = "nec,wg2600hp3", "qcom,ipq8062", "qcom,ipq8064"; + + memory { + device_type = "memory"; + reg = <0x42000000 0x1e000000>; + }; + + aliases { + label-mac-device = &gmac2; + + led-boot = &led_power_green; + led-failsafe = &led_power_red; + led-running = &led_power_green; + led-upgrade = &led_power_red; + }; + + keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&buttons_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + mode0 { + label = "mode0"; + gpios = <&qcom_pinmux 40 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + debounce-interval = <60>; + wakeup-source; + }; + + mode1 { + label = "mode1"; + gpios = <&qcom_pinmux 41 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&leds_pins>; + pinctrl-names = "default"; + + led_power_green: power_green { + label = "green:power"; + gpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>; + }; + + led_power_red: power_red { + label = "red:power"; + gpios = <&qcom_pinmux 35 GPIO_ACTIVE_HIGH>; + }; + + active_green { + label = "green:active"; + gpios = <&qcom_pinmux 42 GPIO_ACTIVE_HIGH>; + }; + + active_red { + label = "red:active"; + gpios = <&qcom_pinmux 38 GPIO_ACTIVE_HIGH>; + }; + + wlan2g_green { + label = "green:wlan2g"; + gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy1tpt"; + }; + + wlan2g_red { + label = "red:wlan2g"; + gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; + }; + + wlan5g_green { + label = "green:wlan5g"; + gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tpt"; + }; + + wlan5g_red { + label = "red:wlan5g"; + gpios = <&qcom_pinmux 58 GPIO_ACTIVE_HIGH>; + }; + + tv_green { + label = "green:tv"; + gpios = <&qcom_pinmux 46 GPIO_ACTIVE_HIGH>; + }; + + tv_red { + label = "red:tv"; + gpios = <&qcom_pinmux 36 GPIO_ACTIVE_HIGH>; + }; + + converter_green { + label = "green:converter"; + gpios = <&qcom_pinmux 43 GPIO_ACTIVE_HIGH>; + }; + + converter_red { + label = "red:converter"; + gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + pinctrl-0 = <&akro_pins>; + pinctrl-names = "default"; + + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + bias-pull-down; + }; + + data { + pins = "gpio18", "gpio19"; + drive-strength = <10>; + }; + + cs { + pins = "gpio20"; + drive-strength = <10>; + }; + + clk { + pins = "gpio21"; + drive-strength = <12>; + }; + }; + + buttons_pins: buttons_pins { + mux { + pins = "gpio22", "gpio24", "gpio40", + "gpio41"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + leds_pins: leds_pins { + mux { + pins = "gpio14", "gpio15", "gpio35", + "gpio36", "gpio38", "gpio42", + "gpio43", "gpio46", "gpio55", + "gpio56", "gpio57", "gpio58"; + function = "gpio"; + bias-pull-down; + }; + + akro2 { + pins = "gpio15", "gpio35", "gpio38", + "gpio42", "gpio43", "gpio46", + "gpio55", "gpio56", "gpio57", + "gpio58"; + drive-strength = <2>; + }; + + akro4 { + pins = "gpio14", "gpio36"; + drive-strength = <4>; + }; + }; + + /* + * Stock firmware has the following settings, so let's do the same. + * I don't sure why these are required. + */ + akro_pins: akro_pinmux { + akro { + pins = "gpio17", "gpio26", "gpio47"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + reset { + pins = "gpio45"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + gmac0_rgmii { + pins = "gpio25"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + }; +}; + +&gsbi5 { + status = "okay"; + qcom,mode = ; + + spi@1a280000 { + status = "okay"; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SBL1"; + reg = <0x0000000 0x0020000>; + read-only; + }; + + partition@20000 { + label = "MIBIB"; + reg = <0x0020000 0x0020000>; + read-only; + }; + + partition@40000 { + label = "SBL2"; + reg = <0x0040000 0x0040000>; + read-only; + }; + + partition@80000 { + label = "SBL3"; + reg = <0x0080000 0x0080000>; + read-only; + }; + + partition@100000 { + label = "DDRCONFIG"; + reg = <0x0100000 0x0010000>; + read-only; + }; + + partition@110000 { + label = "SSD"; + reg = <0x0110000 0x0010000>; + read-only; + }; + + partition@120000 { + label = "TZ"; + reg = <0x0120000 0x0080000>; + read-only; + }; + + partition@1a0000 { + label = "RPM"; + reg = <0x01a0000 0x0080000>; + read-only; + }; + + partition@220000 { + label = "APPSBL"; + reg = <0x0220000 0x0080000>; + read-only; + }; + + partition@2a0000 { + label = "APPSBLENV"; + reg = <0x02a0000 0x0010000>; + read-only; + }; + + factory: partition@2b0000 { + label = "PRODUCTDATA"; + reg = <0x02b0000 0x0030000>; + read-only; + }; + + partition@2e0000 { + label = "ART"; + reg = <0x02e0000 0x0040000>; + read-only; + }; + + partition@320000 { + label = "TP"; + reg = <0x0320000 0x0040000>; + read-only; + }; + + partition@360000 { + label = "TINY"; + reg = <0x0360000 0x0500000>; + read-only; + }; + + partition@860000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x0860000 0x17a0000>; + }; + }; + }; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&pcie0 { + status = "okay"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + + qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3"; + + nvmem-cells = <&macaddr_PRODUCTDATA_12>; + nvmem-cell-names = "mac-address"; + }; + }; +}; + +&pcie1 { + status = "okay"; + force_gen1 = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + reg = <0x00010000 0 0 0 0>; + + ieee80211-freq-limit = <2400000 2483000>; + qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3"; + + nvmem-cells = <&macaddr_PRODUCTDATA_c>; + nvmem-cell-names = "mac-address"; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x04 0x80080080 /* PAD0_MODE */ + 0x0c 0x06000000 /* PAD6_MODE */ + 0x10 0x002613a0 /* PWS_REG */ + 0x50 0xcc36cc36 /* LED_CTRL0 */ + 0x54 0xca36ca36 /* LED_CTRL1 */ + 0x58 0xc936c936 /* LED_CTRL2 */ + 0x5c 0x03ffff00 /* LED_CTRL3 */ + 0x7c 0x0000004e /* PORT0_STATUS */ + 0x94 0x0000004e /* PORT6_STATUS */ + 0xe0 0xc74164de /* SGMII_CTRL */ + 0xe4 0x0006a545 /* MAC_PWR_SEL */ + >; + }; +}; + +&gmac1 { + status = "okay"; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + phy-mode = "rgmii"; + qcom,id = <1>; + mdiobus = <&mdio0>; + nvmem-cells = <&macaddr_factory_0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + mdiobus = <&mdio0>; + nvmem-cells = <&macaddr_factory_6>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&factory { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_factory_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_factory_6: macaddr@6 { + reg = <0x6 0x6>; + }; + + macaddr_PRODUCTDATA_c: macaddr@c { + reg = <0xc 0x6>; + }; + + macaddr_PRODUCTDATA_12: macaddr@12 { + reg = <0x12 0x6>; + }; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062.dtsi b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062.dtsi new file mode 100755 index 00000000..f1681f4c --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8062.dtsi @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include "qcom-ipq8064.dtsi" + +/ { + model = "Qualcomm IPQ8062"; + compatible = "qcom,ipq8062", "qcom,ipq8064"; + + aliases { + serial0 = &gsbi4_serial; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + rsvd@41200000 { + reg = <0x41200000 0x300000>; + no-map; + }; + }; +}; + +&gsbi4 { + qcom,mode = ; + status = "okay"; + + serial@16340000 { + status = "okay"; + }; + /* + * The i2c device on gsbi4 should not be enabled. + * On ipq806x designs gsbi4 i2c is meant for exclusive + * RPM usage. Turning this on in kernel manifests as + * i2c failure for the RPM. + */ +}; + +&opp_table0 { + /delete-node/opp-1200000000; + /delete-node/opp-1400000000; + + /* + * Voltage thresholds are + */ + opp-384000000 { + opp-microvolt-speed0-pvs0-v0 = <950000 902500 997500>; + opp-microvolt-speed0-pvs1-v0 = <900000 855000 945000>; + opp-microvolt-speed0-pvs2-v0 = <850000 807500 892500>; + opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>; + }; + + opp-600000000 { + opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>; + opp-microvolt-speed0-pvs1-v0 = <950000 945000 955000>; + opp-microvolt-speed0-pvs2-v0 = <900000 895000 905000>; + opp-microvolt-speed0-pvs3-v0 = <850000 845000 855000>; + }; + + opp-800000000 { + opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>; + opp-microvolt-speed0-pvs1-v0 = <1000000 995000 1005000>; + opp-microvolt-speed0-pvs2-v0 = <950000 945000 955000>; + opp-microvolt-speed0-pvs3-v0 = <900000 895000 905000>; + }; + + opp-1000000000 { + opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>; + opp-microvolt-speed0-pvs1-v0 = <1050000 997500 1102500>; + opp-microvolt-speed0-pvs2-v0 = <1000000 995000 1005000>; + opp-microvolt-speed0-pvs3-v0 = <950000 945000 955000>; + }; +}; + +&pcie0 { + compatible = "qcom,pcie-ipq8064-v2"; +}; + +&pcie1 { + compatible = "qcom,pcie-ipq8064-v2"; +}; + +&pcie2 { + compatible = "qcom,pcie-ipq8064-v2"; +}; + +&smb208_s2a { + regulator-max-microvolt = <1150000>; +}; + +&smb208_s2b { + regulator-max-microvolt = <1150000>; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi new file mode 100755 index 00000000..5842c34c --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ad7200-c2600.dtsi @@ -0,0 +1,364 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq8064-v2.0.dtsi" + +#include + +/ { + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + aliases { + mdio-gpio0 = &mdio0; + label-mac-device = &gmac2; + }; +}; + +&qcom_pinmux { + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + bias-pull-down; + }; + + data { + pins = "gpio18", "gpio19"; + drive-strength = <10>; + }; + + cs { + pins = "gpio20"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + }; + + clk { + pins = "gpio21"; + drive-strength = <12>; + }; + }; + + usb0_pwr_en_pin: usb0_pwr_en_pin { + mux { + pins = "gpio25"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + output-high; + }; + }; + + usb1_pwr_en_pin: usb1_pwr_en_pin { + mux { + pins = "gpio23"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + output-high; + }; + }; +}; + +&gsbi5 { + qcom,mode = ; + status = "okay"; + + spi@1a280000 { + status = "okay"; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SBL1"; + reg = <0x0 0x20000>; + read-only; + }; + + partition@20000 { + label = "MIBIB"; + reg = <0x20000 0x20000>; + read-only; + }; + + partition@40000 { + label = "SBL2"; + reg = <0x40000 0x20000>; + read-only; + }; + + partition@60000 { + label = "SBL3"; + reg = <0x60000 0x30000>; + read-only; + }; + + partition@90000 { + label = "DDRCONFIG"; + reg = <0x90000 0x10000>; + read-only; + }; + + partition@a0000 { + label = "SSD"; + reg = <0xa0000 0x10000>; + read-only; + }; + + partition@b0000 { + label = "TZ"; + reg = <0xb0000 0x30000>; + read-only; + }; + + partition@e0000 { + label = "RPM"; + reg = <0xe0000 0x20000>; + read-only; + }; + + partition@100000 { + label = "fs-uboot"; + reg = <0x100000 0x70000>; + read-only; + }; + + partition@170000 { + label = "uboot-env"; + reg = <0x170000 0x40000>; + read-only; + }; + + partition@1b0000 { + label = "radio"; + reg = <0x1b0000 0x40000>; + read-only; + }; + + partition@1f0000 { + label = "os-image"; + reg = <0x1f0000 0x400000>; + }; + + partition@5f0000 { + label = "rootfs"; + reg = <0x5f0000 0x1900000>; + }; + + defaultmac: partition@1ef0000 { + label = "default-mac"; + reg = <0x1ef0000 0x00200>; + read-only; + }; + + partition@1ef0200 { + label = "pin"; + reg = <0x1ef0200 0x00200>; + read-only; + }; + + partition@1ef0400 { + label = "product-info"; + reg = <0x1ef0400 0x0fc00>; + read-only; + }; + + partition@1f00000 { + label = "partition-table"; + reg = <0x1f00000 0x10000>; + read-only; + }; + + partition@1f10000 { + label = "soft-version"; + reg = <0x1f10000 0x10000>; + read-only; + }; + + partition@1f20000 { + label = "support-list"; + reg = <0x1f20000 0x10000>; + read-only; + }; + + partition@1f30000 { + label = "profile"; + reg = <0x1f30000 0x10000>; + read-only; + }; + + partition@1f40000 { + label = "default-config"; + reg = <0x1f40000 0x10000>; + read-only; + }; + + partition@1f50000 { + label = "user-config"; + reg = <0x1f50000 0x40000>; + read-only; + }; + + partition@1f90000 { + label = "qos-db"; + reg = <0x1f90000 0x40000>; + read-only; + }; + + partition@1fd0000 { + label = "usb-config"; + reg = <0x1fd0000 0x10000>; + read-only; + }; + + partition@1fe0000 { + label = "log"; + reg = <0x1fe0000 0x20000>; + read-only; + }; + }; + }; + }; +}; + +&usb3_0 { + status = "okay"; + + pinctrl-0 = <&usb0_pwr_en_pin>; + pinctrl-names = "default"; +}; + +&usb3_1 { + status = "okay"; + + pinctrl-0 = <&usb1_pwr_en_pin>; + pinctrl-names = "default"; +}; + +&pcie0 { + status = "okay"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "pci168c,0040"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_defaultmac_8>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <(-1)>; + }; + }; +}; + +&pcie1 { + status = "okay"; + max-link-speed = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "pci168c,0040"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_defaultmac_8>; + nvmem-cell-names = "mac-address"; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x80 /* PAD6_MODE */ + 0x000e4 0x6a545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + >; + }; + + phy4: ethernet-phy@4 { + reg = <4>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + nvmem-cells = <&macaddr_defaultmac_8>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <1>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + + nvmem-cells = <&macaddr_defaultmac_8>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&defaultmac { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_defaultmac_8: macaddr@8 { + reg = <0x8 0x6>; + }; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts new file mode 100755 index 00000000..6cb21fc4 --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ad7200.dts @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq8064-ad7200-c2600.dtsi" + +/ { + model = "TP-Link Talon AD7200"; + compatible = "tplink,ad7200", "qcom,ipq8064"; + + aliases { + led-boot = &led_status; + led-failsafe = &led_status; + led-running = &led_status; + led-upgrade = &led_status; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wifi { + label = "wifi"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + led_enable { + label = "led-enable"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + lan { + label = "blue:lan"; + gpios = <&qcom_pinmux 2 GPIO_ACTIVE_HIGH>; + }; + + usb1 { + label = "blue:usb1"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + wlan5g { + label = "blue:wlan5g"; + gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>; + }; + + usb3 { + label = "blue:usb3"; + gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>; + }; + + wlan2g { + label = "blue:wlan2g"; + gpios = <&qcom_pinmux 17 GPIO_ACTIVE_HIGH>; + }; + + wan_orange { + label = "orange:wan"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; + }; + + wan_blue { + label = "blue:wan"; + gpios = <&qcom_pinmux 33 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "blue:wps"; + gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; + }; + + wlan60g { + label = "blue:wlan60g"; + gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; + }; + + led_status: status { + label = "blue:status"; + gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio53", "gpio54", "gpio67"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio2", "gpio8", "gpio15", "gpio16", "gpio17", "gpio26", + "gpio33", "gpio55", "gpio56", "gpio66"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&pcie2 { + status = "okay"; + max-link-speed = <1>; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ap148.dts new file mode 100755 index 00000000..29476e38 --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ap148.dts @@ -0,0 +1,121 @@ +#include "qcom-ipq8064-v1.0.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ8064/AP-148"; + compatible = "qcom,ipq8064-ap148", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + rsvd@41200000 { + reg = <0x41200000 0x300000>; + no-map; + }; + }; + + aliases { + mdio-gpio0 = &mdio0; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&flash { + partitions { + compatible = "qcom,smem-part"; + }; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; + max-link-speed = <1>; +}; + +&nand_controller { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "qcom,smem-part"; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x80 /* PAD6_MODE */ + 0x000e4 0x6a545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + >; + }; + + phy4: ethernet-phy@4 { + reg = <4>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ap161.dts b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ap161.dts new file mode 100755 index 00000000..914c3705 --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ap161.dts @@ -0,0 +1,159 @@ +#include "qcom-ipq8064-v1.0.dtsi" + +/ { + model = "Qualcomm IPQ8064/AP161"; + compatible = "qcom,ipq8064-ap161", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + rsvd@41200000 { + reg = <0x41200000 0x300000>; + no-map; + }; + }; + + aliases { + mdio-gpio0 = &mdio0; + }; +}; + +&qcom_pinmux { + rgmii2_pins: rgmii2_pins { + mux { + pins = "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32", + "gpio51", "gpio52", "gpio59", + "gpio60", "gpio61", "gpio62", + "gpio2", "gpio66"; + }; + }; +}; + +&flash { + partitions { + compatible = "qcom,smem-part"; + }; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; + max-link-speed = <1>; +}; + +&pcie2 { + status = "okay"; +}; + +&nand_controller { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "qcom,smem-part"; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x20080 /* PAD6_MODE */ + 0x000e4 0x6a545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + >; + }; + + phy4: ethernet-phy@4 { + reg = <4>; + qca,phy-rgmii-en; + qca,txclk-delay-en; + qca,rxclk-delay-en; + }; + + phy3: ethernet-phy@3 { + device_type = "ethernet-phy"; + reg = <3>; + }; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <0>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + mdiobus = <&mdio0>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <1>; + mdiobus = <&mdio0>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + mdiobus = <&mdio0>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&adm_dma { + status = "okay"; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-c2600.dts b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-c2600.dts new file mode 100755 index 00000000..cef1aba3 --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-c2600.dts @@ -0,0 +1,119 @@ +#include "qcom-ipq8064-ad7200-c2600.dtsi" + +/ { + model = "TP-Link Archer C2600"; + compatible = "tplink,c2600", "qcom,ipq8064"; + + aliases { + led-boot = &power; + led-failsafe = &general; + led-running = &power; + led-upgrade = &general; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wifi { + label = "wifi"; + gpios = <&qcom_pinmux 49 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + ledswitch { + label = "ledswitch"; + gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + lan { + label = "white:lan"; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_HIGH>; + }; + + usb4 { + label = "white:usb_4"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + usb2 { + label = "white:usb_2"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + wps { + label = "white:wps"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + wan_amber { + label = "amber:wan"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; + }; + + wan_white { + label = "white:wan"; + gpios = <&qcom_pinmux 33 GPIO_ACTIVE_LOW>; + }; + + power: power { + label = "white:power"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + general: general { + label = "white:general"; + gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio16", "gpio54", "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio6", "gpio7", "gpio8", "gpio9", "gpio26", "gpio33", + "gpio53", "gpio66"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-d7800.dts b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-d7800.dts new file mode 100755 index 00000000..940e0143 --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-d7800.dts @@ -0,0 +1,371 @@ +#include "qcom-ipq8064-v2.0.dtsi" + +#include + +/ { + model = "Netgear Nighthawk X4 D7800"; + compatible = "netgear,d7800", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0xe000000>; + device_type = "memory"; + }; + + aliases { + mdio-gpio0 = &mdio0; + + led-boot = &power_white; + led-failsafe = &power_amber; + led-running = &power_white; + led-upgrade = &power_amber; + }; + + chosen { + bootargs = "rootfstype=squashfs noinitrd"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wifi { + label = "wifi"; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + usb1 { + label = "white:usb1"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + usb2 { + label = "white:usb2"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + power_amber: power_amber { + label = "amber:power"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + wan_white { + label = "white:wan"; + gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; + }; + + wan_amber { + label = "amber:wan"; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; + }; + + wps { + label = "white:wps"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; + }; + + esata { + label = "white:esata"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + }; + + power_white: power_white { + label = "white:power"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + wifi { + label = "white:wifi"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio6", "gpio54", "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23", + "gpio24","gpio26", "gpio53", "gpio64"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + usb0_pwr_en_pins: usb0_pwr_en_pins { + mux { + pins = "gpio15"; + function = "gpio"; + drive-strength = <12>; + bias-pull-down; + output-high; + }; + }; + + usb1_pwr_en_pins: usb1_pwr_en_pins { + mux { + pins = "gpio16", "gpio68"; + function = "gpio"; + drive-strength = <12>; + bias-pull-down; + output-high; + }; + }; +}; + +&sata_phy { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; + + pinctrl-0 = <&usb0_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&usb3_1 { + status = "okay"; + + pinctrl-0 = <&usb1_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&pcie0 { + status = "okay"; + reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "pci168c,0040"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_art_6>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <(1)>; + }; + }; +}; + +&pcie1 { + status = "okay"; + reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pcie1_pins>; + pinctrl-names = "default"; + max-link-speed = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "pci168c,0040"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_art_6>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <(2)>; + }; + }; +}; + +&nand_controller { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + nand-is-boot-medium; + qcom,boot_pages_size = <0x1180000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qcadata@0 { + label = "qcadata"; + reg = <0x0000000 0x0c80000>; + read-only; + }; + + APPSBL@c80000 { + label = "APPSBL"; + reg = <0x0c80000 0x0500000>; + read-only; + }; + + APPSBLENV@1180000 { + label = "APPSBLENV"; + reg = <0x1180000 0x0080000>; + read-only; + }; + + art: art@1200000 { + label = "art"; + reg = <0x1200000 0x0140000>; + read-only; + }; + + artbak: art@1340000 { + label = "artbak"; + reg = <0x1340000 0x0140000>; + read-only; + }; + + kernel@1480000 { + label = "kernel"; + reg = <0x1480000 0x0400000>; + }; + + ubi@1880000 { + label = "ubi"; + reg = <0x1880000 0x1C00000>; + }; + + netgear@3480000 { + label = "netgear"; + reg = <0x3480000 0x4480000>; + read-only; + }; + + reserve@7900000 { + label = "reserve"; + reg = <0x7900000 0x0700000>; + read-only; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x80 /* PAD6_MODE */ + 0x000e4 0x6a545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + >; + }; + + phy4: ethernet-phy@4 { + reg = <4>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + nvmem-cells = <&macaddr_art_6>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + + nvmem-cells = <&macaddr_art_0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&art { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-db149.dts b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-db149.dts new file mode 100755 index 00000000..8e8d942f --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-db149.dts @@ -0,0 +1,163 @@ +#include "qcom-ipq8064-v1.0.dtsi" + +/ { + model = "Qualcomm IPQ8064/DB149"; + compatible = "qcom,ipq8064-db149", "qcom,ipq8064"; + + aliases { + serial0 = &gsbi2_serial; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + rsvd@41200000 { + reg = <0x41200000 0x300000>; + no-map; + }; + }; +}; + +&qcom_pinmux { + rgmii0_pins: rgmii0_pins { + mux { + pins = "gpio2", "gpio66"; + drive-strength = <8>; + bias-disable; + }; + }; +}; + +&gsbi2 { + qcom,mode = ; + status = "okay"; + + gsbi2_serial: serial@12490000 { + status = "okay"; + }; +}; + +&gsbi4 { + status = "disabled"; +}; + +&gsbi4_serial { + status = "disabled"; +}; + +&flash { + m25p,fast-read; + + partition@0 { + label = "lowlevel_init"; + reg = <0x0 0x1b0000>; + }; + + partition@1 { + label = "u-boot"; + reg = <0x1b0000 0x80000>; + }; + + partition@2 { + label = "u-boot-env"; + reg = <0x230000 0x40000>; + }; + + partition@3 { + label = "caldata"; + reg = <0x270000 0x40000>; + }; + + partition@4 { + label = "firmware"; + reg = <0x2b0000 0x1d50000>; + }; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x80 /* PAD6_MODE */ + 0x000e4 0x6a545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + >; + }; + + phy4: ethernet-phy@4 { + reg = <4>; + }; + + phy6: ethernet-phy@6 { + reg = <6>; + }; + + phy7: ethernet-phy@7 { + reg = <7>; + }; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <0>; + phy-handle = <&phy4>; + + pinctrl-0 = <&rgmii0_pins>; + pinctrl-names = "default"; +}; + +&gmac1 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <1>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + phy-handle = <&phy6>; +}; + +&gmac3 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <3>; + phy-handle = <&phy7>; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts new file mode 100755 index 00000000..9d82d52d --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ea7500-v1.dts @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq8064-eax500.dtsi" + +/ { + model = "Linksys EA7500 V1 WiFi Router"; + compatible = "linksys,ea7500-v1", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0xe000000>; + device_type = "memory"; + }; + + aliases { + led-boot = &led_power; + led-failsafe = &led_power; + led-running = &led_power; + led-upgrade = &led_power; + }; + + chosen { + /* look for root deviceblock nbr in this bootarg */ + find-rootblock = "ubi.mtd="; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + led_power: power { + label = "white:power"; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio65", "gpio68"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio6"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&partitions { + partition@5f80000 { + label = "sysdiag"; + reg = <0x5f80000 0x100000>; + }; + + partition@6080000 { + label = "syscfg"; + reg = <0x6080000 0x1f80000>; + }; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts new file mode 100755 index 00000000..1c6a4bda --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-ea8500.dts @@ -0,0 +1,128 @@ +#include "qcom-ipq8064-eax500.dtsi" + +/ { + model = "Linksys EA8500 WiFi Router"; + compatible = "linksys,ea8500", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + aliases { + mdio-gpio0 = &mdio0; + + led-boot = &led_power; + led-failsafe = &led_power; + led-running = &led_power; + led-upgrade = &led_power; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wifi { + label = "wifi"; + gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + wps { + label = "green:wps"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + }; + + led_power: power { + label = "white:power"; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + + wifi { + label = "green:wifi"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio65", "gpio67", "gpio68"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio6", "gpio53", "gpio54"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&sata_phy { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&partitions { + partition@5f80000 { + label = "syscfg"; + reg = <0x5f80000 0x2080000>; + }; +}; + +&mdio0 { + phy4: ethernet-phy@4 { + reg = <4>; + }; +}; + +&gmac1 { + qcom,phy_mdio_addr = <4>; + qcom,poll_required = <1>; + qcom,rgmii_delay = <0>; + qcom,emulation = <0>; +}; + +/* LAN */ +&gmac2 { + qcom,phy_mdio_addr = <0>; /* none */ + qcom,poll_required = <0>; /* no polling */ + qcom,rgmii_delay = <0>; + qcom,emulation = <0>; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi new file mode 100755 index 00000000..98c4b2d2 --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-eax500.dtsi @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq8064-v2.0.dtsi" + +#include + +/ { + chosen { + bootargs = "console=ttyMSM0,115200n8"; + /* append to bootargs adding the root deviceblock nbr from bootloader */ + append-rootblock = "ubi.mtd="; + }; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; + + max-link-speed = <1>; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie2 { + status = "okay"; +}; + +&nand_controller { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + nand-is-boot-medium; + qcom,boot_pages_size = <0x0c80000>; + + partitions: partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SBL1"; + reg = <0x0000000 0x0040000>; + read-only; + }; + + partition@40000 { + label = "MIBIB"; + reg = <0x0040000 0x0140000>; + read-only; + }; + + partition@180000 { + label = "SBL2"; + reg = <0x0180000 0x0140000>; + read-only; + }; + + partition@2c0000 { + label = "SBL3"; + reg = <0x02c0000 0x0280000>; + read-only; + }; + + partition@540000 { + label = "DDRCONFIG"; + reg = <0x0540000 0x0120000>; + read-only; + }; + + partition@660000 { + label = "SSD"; + reg = <0x0660000 0x0120000>; + read-only; + }; + + partition@780000 { + label = "TZ"; + reg = <0x0780000 0x0280000>; + read-only; + }; + + partition@a00000 { + label = "RPM"; + reg = <0x0a00000 0x0280000>; + read-only; + }; + + art: partition@c80000 { + label = "art"; + reg = <0x0c80000 0x0140000>; + read-only; + }; + + partition@dc0000 { + label = "APPSBL"; + reg = <0x0dc0000 0x0100000>; + read-only; + }; + + partition@ec0000 { + label = "u_env"; + reg = <0x0ec0000 0x0040000>; + }; + + partition@f00000 { + label = "s_env"; + reg = <0x0f00000 0x0040000>; + }; + + partition@f40000 { + label = "devinfo"; + reg = <0x0f40000 0x0040000>; + }; + + partition@f80000 { + label = "kernel1"; + reg = <0x0f80000 0x2800000>; /* 3 MB spill to rootfs */ + }; + + partition@1280000 { + label = "rootfs1"; + reg = <0x1280000 0x2500000>; + }; + + partition@3780000 { + label = "kernel2"; + reg = <0x3780000 0x2800000>; + }; + + partition@3a80000 { + label = "rootfs2"; + reg = <0x3a80000 0x2500000>; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x80 /* PAD6_MODE */ + 0x00010 0x2613a0 /* PWS_REG */ + 0x000e4 0x6a545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + >; + }; +}; + +&gmac1 { + status = "okay"; + + phy-mode = "rgmii"; + qcom,id = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + + phy-mode = "sgmii"; + qcom,id = <2>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&adm_dma { + status = "okay"; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-g10.dts b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-g10.dts new file mode 100755 index 00000000..45efb2b4 --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-g10.dts @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-ipq8064-v2.0.dtsi" + +#include +#include + +/ { + compatible = "asrock,g10", "qcom,ipq8064"; + model = "ASRock G10"; + + aliases { + ethernet0 = &gmac1; + ethernet1 = &gmac0; + + led-boot = &led_status_blue; + led-failsafe = &led_status_amber; + led-running = &led_status_blue; + led-upgrade = &led_status_amber; + }; + + chosen { + bootargs-override = "console=ttyMSM0,115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + /* + * this is a bit misleading. Because there are about seven + * multicolor LEDs connected all wired together in parallel. + */ + + status_yellow { + label = "yellow:status"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + led_status_amber: status_amber { + label = "amber:status"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + led_status_blue: status_blue { + label = "blue:status"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + /* + * LED is declared in vendors boardfile but it's not + * working and the manual doesn't mention anything + * about the LED being white. + + status_white { + label = "white:status"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + }; + */ + }; + + i2c-gpio { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "i2c-gpio"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>, /* sda */ + <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>; /* scl */ + i2c-gpio,delay-us = <5>; + i2c-gpio,scl-output-only; + + mcu@50 { + reg = <0x50>; + compatible = "sonix,sn8f25e21"; + }; + }; + + keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + ir-remote { + label = "ir-remote"; + gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps5g { + label = "wps5g"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps2g { + label = "wps2g"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&gmac1 { + status = "okay"; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + phy-mode = "rgmii"; + qcom,id = <1>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + + phy-mode = "sgmii"; + qcom,id = <2>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gsbi4_serial { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x80 /* PAD6_MODE */ + 0x000e4 0x6a545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + >; + }; +}; + +&nand_controller { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "qcom,smem-part"; + }; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&qcom_pinmux { + led_pins: led_pins { + mux { + pins = "gpio7", "gpio8", "gpio9", "gpio26"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + button_pins: button_pins { + mux { + pins = "gpio15", "gpio16", "gpio64", "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + uart0_pins: uart0_pins { + mux { + pins = "gpio10", "gpio11"; + function = "gsbi4"; + drive-strength = <10>; + bias-disable; + }; + }; +}; + +&rpm { + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&tcsr { + qcom,usb-ctrl-select = ; +}; + +/delete-node/ &pcie2_pins; +/delete-node/ &pcie2; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500.dts b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500.dts new file mode 100755 index 00000000..c7d26a07 --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500.dts @@ -0,0 +1,316 @@ +#include "qcom-ipq8064-v1.0.dtsi" + +#include +#include + +/ { + model = "Netgear Nighthawk X4 R7500"; + compatible = "netgear,r7500", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0xe000000>; + device_type = "memory"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + rsvd@41200000 { + reg = <0x41200000 0x300000>; + no-map; + }; + }; + + aliases { + mdio-gpio0 = &mdio0; + + led-boot = &power_white; + led-failsafe = &power_amber; + led-running = &power_white; + led-upgrade = &power_amber; + }; + + chosen { + bootargs = "rootfstype=squashfs noinitrd"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wifi { + label = "wifi"; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + usb1 { + label = "white:usb1"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + usb2 { + label = "white:usb2"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + power_amber: power_amber { + label = "amber:power"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + wan_white { + label = "white:wan"; + gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; + }; + + wan_amber { + label = "amber:wan"; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; + }; + + wps { + label = "white:wps"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; + }; + + esata { + label = "white:esata"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + }; + + power_white: power_white { + label = "white:power"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + wifi { + label = "white:wifi"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio6", "gpio54", "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23", + "gpio24","gpio26", "gpio53", "gpio64"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&gsbi5 { + status = "disabled"; + + spi@1a280000 { + status = "disabled"; + }; +}; + +&usb3_0 { + clocks = <&gcc USB30_1_MASTER_CLK>; + status = "okay"; +}; + +&usb3_1 { + clocks = <&gcc USB30_0_MASTER_CLK>; + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; + max-link-speed = <1>; +}; + +&nand_controller { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + nand-is-boot-medium; + qcom,boot_pages_size = <0x1180000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qcadata@0 { + label = "qcadata"; + reg = <0x0000000 0x0c80000>; + read-only; + }; + + APPSBL@c80000 { + label = "APPSBL"; + reg = <0x0c80000 0x0500000>; + read-only; + }; + + APPSBLENV@1180000 { + label = "APPSBLENV"; + reg = <0x1180000 0x0080000>; + read-only; + }; + + art: art@1200000 { + label = "art"; + reg = <0x1200000 0x0140000>; + read-only; + }; + + kernel@1340000 { + label = "kernel"; + reg = <0x1340000 0x0400000>; + }; + + ubi@1740000 { + label = "ubi"; + reg = <0x1740000 0x1600000>; + }; + + netgear@2d40000 { + label = "netgear"; + reg = <0x2d40000 0x0c00000>; + read-only; + }; + + reserve@3940000 { + label = "reserve"; + reg = <0x3940000 0x46c0000>; + read-only; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x80 /* PAD6_MODE */ + 0x000e4 0x6a545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + >; + }; + + phy4: ethernet-phy@4 { + reg = <4>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + nvmem-cells = <&macaddr_art_6>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + + nvmem-cells = <&macaddr_art_0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&tcsr { + qcom,usb-ctrl-select = ; + compatible = "qcom,tcsr"; +}; + +&adm_dma { + status = "okay"; +}; + +&art { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts new file mode 100755 index 00000000..f2bd1705 --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-r7500v2.dts @@ -0,0 +1,369 @@ +#include "qcom-ipq8064-v2.0.dtsi" + +#include + +/ { + model = "Netgear Nighthawk X4 R7500v2"; + compatible = "netgear,r7500v2", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + reserved-memory { + rsvd@5fe00000 { + reg = <0x5fe00000 0x200000>; + reusable; + }; + }; + + aliases { + mdio-gpio0 = &mdio0; + + led-boot = &power; + led-failsafe = &power; + led-running = &power; + led-upgrade = &power; + }; + + chosen { + bootargs = "rootfstype=squashfs noinitrd"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wifi { + label = "wifi"; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + usb1 { + label = "amber:usb1"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + usb3 { + label = "amber:usb3"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + status { + label = "amber:status"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + internet { + label = "white:internet"; + gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; + }; + + wan { + label = "white:wan"; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; + }; + + wps { + label = "white:wps"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; + }; + + esata { + label = "white:esata"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + }; + + power: power { + label = "white:power"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + wifi { + label = "white:wifi"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio6", "gpio54", "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23", + "gpio24","gpio26", "gpio53", "gpio64"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + usb0_pwr_en_pins: usb0_pwr_en_pins { + mux { + pins = "gpio15"; + function = "gpio"; + drive-strength = <12>; + bias-pull-down; + output-high; + }; + }; + + usb1_pwr_en_pins: usb1_pwr_en_pins { + mux { + pins = "gpio16", "gpio68"; + function = "gpio"; + drive-strength = <12>; + bias-pull-down; + output-high; + }; + }; +}; + +&sata_phy { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; + + pinctrl-0 = <&usb0_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&usb3_1 { + status = "okay"; + + pinctrl-0 = <&usb1_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&pcie0 { + status = "okay"; + reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "pci168c,0040"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_art_6>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <(1)>; + }; + }; +}; + +&pcie1 { + status = "okay"; + reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pcie1_pins>; + pinctrl-names = "default"; + max-link-speed = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "pci168c,0040"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_art_6>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <(2)>; + }; + }; +}; + +&nand_controller { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + nand-is-boot-medium; + qcom,boot_pages_size = <0x1180000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qcadata@0 { + label = "qcadata"; + reg = <0x0000000 0x0c80000>; + read-only; + }; + + APPSBL@c80000 { + label = "APPSBL"; + reg = <0x0c80000 0x0500000>; + read-only; + }; + + APPSBLENV@1180000 { + label = "APPSBLENV"; + reg = <0x1180000 0x0080000>; + read-only; + }; + + art: art@1200000 { + label = "art"; + reg = <0x1200000 0x0140000>; + read-only; + }; + + artbak: art@1340000 { + label = "artbak"; + reg = <0x1340000 0x0140000>; + read-only; + }; + + kernel@1480000 { + label = "kernel"; + reg = <0x1480000 0x0400000>; + }; + + ubi@1880000 { + label = "ubi"; + reg = <0x1880000 0x6080000>; + }; + + reserve@7900000 { + label = "reserve"; + reg = <0x7900000 0x0700000>; + read-only; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x80 /* PAD6_MODE */ + 0x000e4 0xaa545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + >; + }; + + phy4: ethernet-phy@4 { + reg = <4>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + nvmem-cells = <&macaddr_art_6>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + + nvmem-cells = <&macaddr_art_0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&art { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts new file mode 100755 index 00000000..a50204fe --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-unifi-ac-hd.dts @@ -0,0 +1,317 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq8064-v2.0.dtsi" + +#include +#include + +/ { + model = "Ubiquiti UniFi AC HD"; + compatible = "ubnt,unifi-ac-hd", "qcom,ipq8064"; + + aliases { + label-mac-device = &gmac2; + led-boot = &led_dome_white; + led-failsafe = &led_dome_white; + led-running = &led_dome_blue; + led-upgrade = &led_dome_blue; + mdio-gpio0 = &mdio0; + ethernet0 = &gmac2; + ethernet1 = &gmac1; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + led_dome_blue: dome_blue { + label = "blue:dome"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + led_dome_white: dome_white { + label = "white:dome"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + }; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio68"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio9", "gpio53"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + drive-strength = <10>; + bias-none; + }; + + cs { + pins = "gpio20"; + drive-strength = <12>; + }; + }; +}; + +&CPU_SPC { + status = "disabled"; +}; + +&gsbi5 { + status = "okay"; + + qcom,mode = ; + + spi@1a280000 { + status = "okay"; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + cs-gpios = <&qcom_pinmux 20 0>; + + flash@0 { + compatible = "mx25u25635f", "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SBL1"; + reg = <0x0 0x20000>; + read-only; + }; + + partition@20000 { + label = "MIBIB"; + reg = <0x20000 0x10000>; + read-only; + }; + + partition@30000 { + label = "SBL2"; + reg = <0x30000 0x20000>; + read-only; + }; + + partition@50000 { + label = "SBL3"; + reg = <0x50000 0x30000>; + read-only; + }; + + partition@80000 { + label = "DDRCONFIG"; + reg = <0x80000 0x10000>; + read-only; + }; + + partition@90000 { + label = "SSD"; + reg = <0x90000 0x10000>; + read-only; + }; + + partition@a0000 { + label = "TZ"; + reg = <0xa0000 0x30000>; + read-only; + }; + + partition@d0000 { + label = "RPM"; + reg = <0xd0000 0x20000>; + read-only; + }; + + partition@f0000 { + label = "APPSBL"; + reg = <0xf0000 0xc0000>; + read-only; + }; + + partition@1b0000 { + label = "APPSBLENV"; + reg = <0x1b0000 0x10000>; + read-only; + }; + + eeprom: partition@1c0000 { + label = "EEPROM"; + reg = <0x1c0000 0x10000>; + read-only; + }; + + partition@1d0000 { + label = "bootselect"; + reg = <0x1d0000 0x10000>; + }; + + partition@1e0000 { + compatible = "denx,fit"; + label = "firmware"; + reg = <0x1e0000 0xe70000>; + }; + + partition@1050000 { + label = "kernel1"; + reg = <0x1050000 0xe70000>; + read-only; + }; + + partition@1ec0000 { + label = "debug"; + reg = <0x1ec0000 0x100000>; + read-only; + }; + + partition@1fc0000 { + label = "cfg"; + reg = <0x1fc0000 0x40000>; + read-only; + }; + }; + }; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&nand_controller { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + nand-ecc-strength = <4>; + nand-bus-width = <8>; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy4: ethernet-phy@4 { + reg = <4>; + }; + + phy5: ethernet-phy@5 { + reg = <5>; + }; +}; + +&gmac1 { + status = "okay"; + + mdiobus = <&mdio0>; + phy-handle = <&phy5>; + phy-mode = "sgmii"; + qcom,id = <1>; + + nvmem-cells = <&macaddr_eeprom_6>; + nvmem-cell-names = "mac-address"; +}; + +&gmac2 { + status = "okay"; + + mdiobus = <&mdio0>; + phy-handle = <&phy4>; + phy-mode = "sgmii"; + qcom,id = <2>; + + nvmem-cells = <&macaddr_eeprom_0>; + nvmem-cell-names = "mac-address"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&tcsr { + status = "okay"; +}; + +&hs_phy_0 { + status = "okay"; +}; + +&ss_phy_0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&hs_phy_1 { + status = "okay"; +}; + +&ss_phy_1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&eeprom { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_eeprom_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_eeprom_6: macaddr@6 { + reg = <0x6 0x6>; + }; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi new file mode 100755 index 00000000..b9ee86a8 --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi @@ -0,0 +1,69 @@ +#include "qcom-ipq8064.dtsi" + +/ { + aliases { + serial0 = &gsbi4_serial; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + rsvd@41200000 { + reg = <0x41200000 0x300000>; + no-map; + }; + }; +}; + +&gsbi4 { + qcom,mode = ; + status = "okay"; + + serial@16340000 { + status = "okay"; + }; + /* + * The i2c device on gsbi4 should not be enabled. + * On ipq806x designs gsbi4 i2c is meant for exclusive + * RPM usage. Turning this on in kernel manifests as + * i2c failure for the RPM. + */ +}; + +&CPU_SPC { + status = "okay"; +}; + +&pcie0 { + compatible = "qcom,pcie-ipq8064-v2"; +}; + +&pcie1 { + compatible = "qcom,pcie-ipq8064-v2"; +}; + +&pcie2 { + compatible = "qcom,pcie-ipq8064-v2"; +}; + +&sata { + ports-implemented = <0x1>; +}; + +&ss_phy_0 { + qcom,rx-eq = <2>; + qcom,tx-deamp_3_5db = <32>; + qcom,mpll = <5>; +}; + +&ss_phy_1 { + qcom,rx-eq = <2>; + qcom,tx-deamp_3_5db = <32>; + qcom,mpll = <5>; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts new file mode 100755 index 00000000..863c5d7b --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-vr2600v.dts @@ -0,0 +1,393 @@ +#include "qcom-ipq8064-v2.0.dtsi" + +#include + +/ { + model = "TP-Link Archer VR2600v"; + compatible = "tplink,vr2600v", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + aliases { + mdio-gpio0 = &mdio0; + + led-boot = &power; + led-failsafe = &general; + led-running = &power; + led-upgrade = &general; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wifi { + label = "wifi"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + dect { + label = "dect"; + gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + ledswitch { + label = "ledswitch"; + gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + dsl { + label = "white:dsl"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + usb { + label = "white:usb"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + lan { + label = "white:lan"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + wlan2g { + label = "white:wlan2g"; + gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>; + }; + + wlan5g { + label = "white:wlan5g"; + gpios = <&qcom_pinmux 17 GPIO_ACTIVE_HIGH>; + }; + + power: power { + label = "white:power"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + phone { + label = "white:phone"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + }; + + wan { + label = "white:wan"; + gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; + }; + + general: general { + label = "white:general"; + gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + led_pins: led_pins { + mux { + pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio17", + "gpio26", "gpio53", "gpio56", "gpio66"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + button_pins: button_pins { + mux { + pins = "gpio54", "gpio64", "gpio65", "gpio67", "gpio68"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + bias-pull-down; + }; + + data { + pins = "gpio18", "gpio19"; + drive-strength = <10>; + }; + + cs { + pins = "gpio20"; + drive-strength = <10>; + bias-pull-up; + }; + + clk { + pins = "gpio21"; + drive-strength = <12>; + }; + }; +}; + +&gsbi5 { + qcom,mode = ; + status = "okay"; + + spi4: spi@1a280000 { + status = "okay"; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + W25Q128@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + + SBL1@0 { + label = "SBL1"; + reg = <0x0 0x20000>; + read-only; + }; + + MIBIB@20000 { + label = "MIBIB"; + reg = <0x20000 0x20000>; + read-only; + }; + + SBL2@40000 { + label = "SBL2"; + reg = <0x40000 0x40000>; + read-only; + }; + + SBL3@80000 { + label = "SBL3"; + reg = <0x80000 0x80000>; + read-only; + }; + + DDRCONFIG@100000 { + label = "DDRCONFIG"; + reg = <0x100000 0x10000>; + read-only; + }; + + SSD@110000 { + label = "SSD"; + reg = <0x110000 0x10000>; + read-only; + }; + + TZ@120000 { + label = "TZ"; + reg = <0x120000 0x80000>; + read-only; + }; + + RPM@1a0000 { + label = "RPM"; + reg = <0x1a0000 0x80000>; + read-only; + }; + + APPSBL@220000 { + label = "APPSBL"; + reg = <0x220000 0x80000>; + read-only; + }; + + APPSBLENV@2a0000 { + label = "APPSBLENV"; + reg = <0x2a0000 0x40000>; + read-only; + }; + + OLDART@2e0000 { + label = "OLDART"; + reg = <0x2e0000 0x40000>; + read-only; + }; + + kernel@320000 { + label = "kernel"; + reg = <0x320000 0x300000>; + }; + + rootfs@620000 { + label = "rootfs"; + reg = <0x620000 0x960000>; + }; + + defaultmac: default-mac@0xfaf100 { + label = "default-mac"; + reg = <0xfaf100 0x00200>; + read-only; + }; + + ART@fc0000 { + label = "ART"; + reg = <0xfc0000 0x40000>; + read-only; + }; + }; + }; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "pci168c,0040"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_defaultmac_0>; + nvmem-cell-names = "mac-address"; + mtd-mac-address-increment = <(-1)>; + }; + }; +}; + +&pcie1 { + status = "okay"; + max-link-speed = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "pci168c,0040"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_defaultmac_0>; + nvmem-cell-names = "mac-address"; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x80 /* PAD6_MODE */ + 0x000e4 0x6a545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + >; + }; + + phy4: ethernet-phy@4 { + reg = <4>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + nvmem-cells = <&macaddr_defaultmac_0>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <1>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + + nvmem-cells = <&macaddr_defaultmac_0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&defaultmac { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_defaultmac_0: macaddr@0 { + reg = <0x0 0x6>; + }; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts new file mode 100755 index 00000000..45da4a2b --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wg2600hp.dts @@ -0,0 +1,436 @@ +#include "qcom-ipq8064-v2.0.dtsi" + +#include + +/ { + model = "NEC Aterm WG2600HP"; + compatible = "nec,wg2600hp", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + aliases { + mdio-gpio0 = &mdio0; + + led-boot = &power_green; + led-failsafe = &power_red; + led-running = &power_green; + led-upgrade = &power_green; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + bridge { + label = "bridge"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + debounce-interval = <60>; + wakeup-source; + }; + + converter { + label = "converter"; + gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + converter_green { + label = "green:converter"; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_HIGH>; + }; + + power_red: power_red { + label = "red:power"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + active_green { + label = "green:active"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + active_red { + label = "red:active"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + power_green: power_green { + label = "green:power"; + gpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>; + }; + + converter_red { + label = "red:converter"; + gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>; + }; + + wlan2g_green { + label = "green:wlan2g"; + gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; + }; + + wlan2g_red { + label = "red:wlan2g"; + gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>; + }; + + wlan5g_green { + label = "green:wlan5g"; + gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>; + }; + + wlan5g_red { + label = "red:wlan5g"; + gpios = <&qcom_pinmux 58 GPIO_ACTIVE_HIGH>; + }; + + tv_green { + label = "green:tv"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; + }; + + tv_red { + label = "red:tv"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&CPU_SPC { + status = "disabled"; +}; + +&adm_dma { + status = "okay"; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x06000000 /* PAD0_MODE */ + 0x0000c 0x00080080 /* PAD6_MODE */ + 0x000e4 0x0006a545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x0000004e /* PORT0_STATUS */ + 0x00094 0x0000004e /* PORT6_STATUS */ + >; + }; + + ethernet-phy@4 { + reg = <4>; + }; +}; + +&gmac1 { + status = "okay"; + + phy-mode = "rgmii"; + qcom,id = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + nvmem-cells = <&macaddr_PRODUCTDATA_6>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + + phy-mode = "sgmii"; + qcom,id = <2>; + + nvmem-cells = <&macaddr_PRODUCTDATA_0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gsbi5 { + status = "okay"; + + qcom,mode = ; + + spi@1a280000 { + status = "okay"; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + SBL1@0 { + label = "SBL1"; + reg = <0x0 0x20000>; + read-only; + }; + + MIBIB@20000 { + label = "MIBIB"; + reg = <0x20000 0x20000>; + read-only; + }; + + SBL2@40000 { + label = "SBL2"; + reg = <0x40000 0x40000>; + read-only; + }; + + SBL3@80000 { + label = "SBL3"; + reg = <0x80000 0x80000>; + read-only; + }; + + DDRCONFIG@100000 { + label = "DDRCONFIG"; + reg = <0x100000 0x10000>; + read-only; + }; + + SSD@110000 { + label = "SSD"; + reg = <0x110000 0x10000>; + read-only; + }; + + TZ@120000 { + label = "TZ"; + reg = <0x120000 0x80000>; + read-only; + }; + + RPM@1a0000 { + label = "RPM"; + reg = <0x1a0000 0x80000>; + read-only; + }; + + APPSBL@220000 { + label = "APPSBL"; + reg = <0x220000 0x80000>; + read-only; + }; + + APPSBLENV@2a0000 { + label = "APPSBLENV"; + reg = <0x2a0000 0x10000>; + }; + + PRODUCTDATA: PRODUCTDATA@2b0000 { + label = "PRODUCTDATA"; + reg = <0x2b0000 0x30000>; + read-only; + }; + + ART@2e0000 { + label = "ART"; + reg = <0x2e0000 0x40000>; + read-only; + }; + + TP@320000 { + label = "TP"; + reg = <0x320000 0x40000>; + read-only; + }; + + TINY@360000 { + label = "TINY"; + reg = <0x360000 0x500000>; + read-only; + }; + + firmware@860000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x860000 0x17a0000>; + }; + }; + }; + }; +}; + +&usb3_0 { + status = "okay"; + + pinctrl-0 = <&usb_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "pci168c,0040"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_PRODUCTDATA_12>; + nvmem-cell-names = "mac-address"; + }; + }; +}; + +&pcie1 { + status = "okay"; + max-link-speed = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "pci168c,0040"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_PRODUCTDATA_c>; + nvmem-cell-names = "mac-address"; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio16", "gpio54", "gpio24", "gpio25"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio6", "gpio7", "gpio8", "gpio9", "gpio14", + "gpio15", "gpio55", "gpio56", "gpio57", "gpio58", + "gpio64", "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + bias-pull-down; + }; + + data { + pins = "gpio18", "gpio19"; + drive-strength = <10>; + }; + + cs { + pins = "gpio20"; + drive-strength = <10>; + bias-pull-up; + }; + + clk { + pins = "gpio21"; + drive-strength = <12>; + }; + }; + + usb_pwr_en_pins: usb_pwr_en_pins { + mux { + pins = "gpio22"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + output-high; + }; + }; +}; + +&PRODUCTDATA { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_PRODUCTDATA_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_PRODUCTDATA_6: macaddr@6 { + reg = <0x6 0x6>; + }; + + macaddr_PRODUCTDATA_c: macaddr@c { + reg = <0xc 0x6>; + }; + + macaddr_PRODUCTDATA_12: macaddr@12 { + reg = <0x12 0x6>; + }; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts new file mode 100755 index 00000000..ec5d5047 --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wpq864.dts @@ -0,0 +1,465 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (C) 2017 Christian Mehlis + * Copyright (C) 2018 Mathias Kresin + * All rights reserved. + */ + +#include "qcom-ipq8064-v1.0.dtsi" + +#include +#include + +/ { + compatible = "compex,wpq864", "qcom,ipq8064"; + model = "Compex WPQ864"; + + aliases { + mdio-gpio0 = &mdio0; + ethernet0 = &gmac1; + ethernet1 = &gmac0; + + led-boot = &led_pass; + led-failsafe = &led_fail; + led-running = &led_pass; + led-upgrade = &led_pass; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + rss4 { + label = "green:rss4"; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; + }; + + rss3 { + label = "green:rss3"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + rss2 { + label = "orange:rss2"; + gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>; + }; + + rss1 { + label = "red:rss1"; + gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; + }; + + led_pass: pass { + label = "green:pass"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + }; + + led_fail: fail { + label = "green:fail"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + usb { + label = "green:usb"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + usb-pcie { + label = "green:usb-pcie"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + }; + + keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + beeper { + compatible = "gpio-beeper"; + + pinctrl-0 = <&beeper_pins>; + pinctrl-names = "default"; + + gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>; + }; +}; + +&rpm { + pinctrl-0 = <&rpm_pins>; + pinctrl-names = "default"; +}; + +&nand_controller { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + mt29f2g08abbeah4@0 { + compatible = "qcom,nandcs"; + + reg = <0>; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + nand-is-boot-medium; + qcom,boot_pages_size = <0x1180000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + SBL1@0 { + label = "SBL1"; + reg = <0x0000000 0x0040000>; + read-only; + }; + + MIBIB@40000 { + label = "MIBIB"; + reg = <0x0040000 0x0140000>; + read-only; + }; + + SBL2@180000 { + label = "SBL2"; + reg = <0x0180000 0x0140000>; + read-only; + }; + + SBL3@2c0000 { + label = "SBL3"; + reg = <0x02c0000 0x0280000>; + read-only; + }; + + DDRCONFIG@540000 { + label = "DDRCONFIG"; + reg = <0x0540000 0x0120000>; + read-only; + }; + + SSD@660000 { + label = "SSD"; + reg = <0x0660000 0x0120000>; + read-only; + }; + + TZ@780000 { + label = "TZ"; + reg = <0x0780000 0x0280000>; + read-only; + }; + + RPM@a00000 { + label = "RPM"; + reg = <0x0a00000 0x0280000>; + read-only; + }; + + APPSBL@c80000 { + label = "APPSBL"; + reg = <0x0c80000 0x0500000>; + read-only; + }; + + APPSBLENV@1180000 { + label = "APPSBLENV"; + reg = <0x1180000 0x0080000>; + }; + + ART@1200000 { + label = "ART"; + reg = <0x1200000 0x0140000>; + }; + + ubi@1340000 { + label = "ubi"; + reg = <0x1340000 0x4000000>; + }; + + BOOTCONFIG@5340000 { + label = "BOOTCONFIG"; + reg = <0x5340000 0x0060000>; + }; + + SBL2-1@53a0000- { + label = "SBL2_1"; + reg = <0x53a0000 0x0140000>; + read-only; + }; + + SBL3-1@54e0000 { + label = "SBL3_1"; + reg = <0x54e0000 0x0280000>; + read-only; + }; + + DDRCONFIG-1@5760000 { + label = "DDRCONFIG_1"; + reg = <0x5760000 0x0120000>; + read-only; + }; + + SSD-1@5880000 { + label = "SSD_1"; + reg = <0x5880000 0x0120000>; + read-only; + }; + + TZ-1@59a0000 { + label = "TZ_1"; + reg = <0x59a0000 0x0280000>; + read-only; + }; + + RPM-1@5c20000 { + label = "RPM_1"; + reg = <0x5c20000 0x0280000>; + read-only; + }; + + BOOTCONFIG1@5ea0000 { + label = "BOOTCONFIG1"; + reg = <0x5ea0000 0x0060000>; + }; + + APPSBL-1@5f00000 { + label = "APPSBL_1"; + reg = <0x5f00000 0x0500000>; + read-only; + }; + + ubi-1@6400000 { + label = "ubi_1"; + reg = <0x6400000 0x4000000>; + }; + + unused@a400000 { + label = "unused"; + reg = <0xa400000 0x5c00000>; + }; + }; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x80 /* PAD6_MODE */ + 0x000e4 0x6a545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + >; + }; + + ethernet-phy@4 { + reg = <4>; + }; +}; + +&gmac1 { + status = "okay"; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + phy-mode = "rgmii"; + qcom,id = <1>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + + phy-mode = "sgmii"; + qcom,id = <2>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gsbi4_serial { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; +}; + +&flash { + compatible = "jedec,spi-nor"; +}; + +&sata_phy { + status = "disabled"; +}; + +&sata { + status = "disabled"; +}; + +&ss_phy_0 { /* USB3 port 0 SS phy */ + status = "okay"; + + rx_eq = <2>; + tx_deamp_3_5db = <32>; + mpll = <160>; +}; + +&ss_phy_1 { /* USB3 port 1 SS phy */ + status = "okay"; + + rx_eq = <2>; + tx_deamp_3_5db = <32>; + mpll = <160>; +}; + +&pcie0 { + status = "okay"; + + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + /delete-property/ perst-gpios; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie2 { + status = "okay"; + + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + /delete-property/ perst-gpios; +}; + +&qcom_pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinctrl0 { + pcie0_pcie2_perst { + pins = "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio7", "gpio8", "gpio9", "gpio22", + "gpio23", "gpio24", "gpio25", "gpio53"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + button_pins: button_pins { + mux { + pins = "gpio54"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + beeper_pins: beeper_pins { + mux { + pins = "gpio55"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + rpm_pins: rpm_pins { + mux { + pins = "gpio12", "gpio13"; + function = "gsbi4"; + drive-strength = <10>; + bias-disable; + }; + }; + + uart0_pins: uart0_pins { + mux { + pins = "gpio10", "gpio11"; + function = "gsbi4"; + drive-strength = <10>; + bias-disable; + }; + }; + + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19"; + function = "gsbi5"; + drive-strength = <10>; + bias-pull-down; + }; + + clk { + pins = "gpio21"; + function = "gsbi5"; + drive-strength = <12>; + bias-pull-down; + }; + + cs { + pins = "gpio20"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + }; + }; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&tcsr { + qcom,usb-ctrl-select = ; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts new file mode 100755 index 00000000..4b4e8736 --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8064-wxr-2533dhp.dts @@ -0,0 +1,520 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +#include "qcom-ipq8064-v2.0.dtsi" + +#include + +/ { + model = "Buffalo WXR-2533DHP"; + compatible = "buffalo,wxr-2533dhp", "qcom,ipq8064"; + + memory@42000000 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + aliases { + led-boot = &power; + led-failsafe = &diag; + led-running = &power; + led-upgrade = &power; + }; + + chosen { + /* use "ubi_rootfs" volume in "ubi" partition as rootfs */ + bootargs = "ubi.block=0,1 root=/dev/ubiblock0_1 rootfstype=squashfs"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + usb { + label = "green:usb"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "usbport"; + trigger-sources = <&hub_port0 &hub_port1>; + }; + + guestport { + label = "green:guestport"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + diag: diag { + label = "orange:diag"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + internet_orange { + label = "orange:internet"; + gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>; + }; + + internet_white { + label = "white:internet"; + gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; + }; + + wireless_orange { + label = "orange:wireless"; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; + }; + + wireless_white { + label = "white:wireless"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; + }; + + router_orange { + label = "orange:router"; + gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>; + }; + + router_white { + label = "white:router"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; + }; + + power: power { + label = "white:power"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + }; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + power { + label = "power"; + gpios = <&qcom_pinmux 58 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + eject { + label = "eject"; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + guest { + label = "guest"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + ap { + label = "ap"; + gpios = <&qcom_pinmux 55 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + debounce-interval = <60>; + wakeup-source; + }; + + router { + label = "router"; + gpios = <&qcom_pinmux 56 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + debounce-interval = <60>; + wakeup-source; + }; + + auto { + label = "auto"; + gpios = <&qcom_pinmux 57 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + debounce-interval = <60>; + wakeup-source; + }; + }; +}; + +&nand_controller { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + cs@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + ubi@0 { + label = "ubi"; + reg = <0x0000000 0x4000000>; + }; + + rootfs_1@4000000 { + label = "rootfs_1"; + reg = <0x4000000 0x4000000>; + }; + }; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x07600000 /* PAD0_MODE */ + 0x00008 0x01000000 /* PAD5_MODE */ + 0x0000c 0x00000080 /* PAD6_MODE */ + 0x00050 0xcc35cc35 /* LED_CTRL0 */ + 0x00054 0xca35ca35 /* LED_CTRL1 */ + 0x00058 0xc935c935 /* LED_CTRL2 */ + 0x0005c 0x03ffff00 /* LED_CTRL3 */ + 0x000e4 0x0006a545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x0000007e /* PORT0_STATUS */ + 0x00094 0x0000007e /* PORT6_STATUS */ + >; + }; + + ethernet-phy@4 { + reg = <4>; + }; +}; + +&gmac1 { + status = "okay"; + + phy-mode = "rgmii"; + qcom,id = <1>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + nvmem-cells = <&macaddr_ART_6>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + + phy-mode = "sgmii"; + qcom,id = <2>; + + nvmem-cells = <&macaddr_ART_0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gsbi4_serial { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; +}; + +&gsbi5 { + status = "okay"; + qcom,mode = ; + + spi@1a280000 { + status = "okay"; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + SBL1@0 { + label = "SBL1"; + reg = <0x0 0x10000>; + read-only; + }; + + MIBIB@10000 { + label = "MIBIB"; + reg = <0x10000 0x20000>; + read-only; + }; + + SBL2@30000 { + label = "SBL2"; + reg = <0x30000 0x30000>; + read-only; + }; + + SBL3@60000 { + label = "SBL3"; + reg = <0x60000 0x30000>; + read-only; + }; + + DDRCONFIG@90000 { + label = "DDRCONFIG"; + reg = <0x90000 0x10000>; + read-only; + }; + + SSD@a0000 { + label = "SSD"; + reg = <0xa0000 0x10000>; + read-only; + }; + + TZ@b0000 { + label = "TZ"; + reg = <0xb0000 0x30000>; + read-only; + }; + + RPM@e0000 { + label = "RPM"; + reg = <0xe0000 0x20000>; + read-only; + }; + + APPSBL@100000 { + label = "APPSBL"; + reg = <0x100000 0x70000>; + read-only; + }; + + APPSBLENV@170000 { + label = "APPSBLENV"; + reg = <0x170000 0x10000>; + read-only; + }; + + ART: ART@180000 { + label = "ART"; + reg = <0x180000 0x40000>; + read-only; + }; + + BOOTCONFIG@1c0000 { + label = "BOOTCONFIG"; + reg = <0x1c0000 0x10000>; + read-only; + }; + + APPSBL_1@1d0000 { + label = "APPSBL_1"; + reg = <0x1d0000 0x70000>; + read-only; + }; + }; + }; + }; +}; + +&usb3_0 { + status = "okay"; + + pinctrl-0 = <&usb_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&usb3_1 { + status = "okay"; +}; + +&dwc3_0 { + #address-cells = <1>; + #size-cells = <0>; + + hub_port0: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; +}; + +&dwc3_1 { + #address-cells = <1>; + #size-cells = <0>; + + hub_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; +}; + +&pcie0 { + status = "okay"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "pci168c,0040"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_ART_1e>; + nvmem-cell-names = "mac-address"; + }; + }; +}; + +&pcie1 { + status = "okay"; + max-link-speed = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "pci168c,0040"; + reg = <0x00010000 0 0 0 0>; + + nvmem-cells = <&macaddr_ART_18>; + nvmem-cell-names = "mac-address"; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio6", "gpio54", "gpio55", "gpio56", "gpio57", + "gpio58", "gpio64", "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio22", + "gpio23", "gpio24", "gpio25", "gpio26", "gpio53"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + uart0_pins: uart0_pins { + mux { + pins = "gpio10", "gpio11"; + function = "gsbi4"; + drive-strength = <12>; + bias-disable; + }; + }; + + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + bias-pull-down; + }; + + data { + pins = "gpio18", "gpio19"; + drive-strength = <10>; + }; + + cs{ + pins = "gpio20"; + drive-strength = <10>; + bias-pull-up; + }; + + clk { + pins = "gpio21"; + drive-strength = <12>; + }; + }; + + usb_pwr_en_pins: usb_pwr_en_pins { + mux{ + pins = "gpio68"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + output-high; + }; + }; +}; + +&ART { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_ART_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_ART_6: macaddr@6 { + reg = <0x6 0x6>; + }; + + macaddr_ART_18: macaddr@18 { + reg = <0x18 0x6>; + }; + + macaddr_ART_1e: macaddr@1e { + reg = <0x1e 0x6>; + }; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts new file mode 100755 index 00000000..969ca724 --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nbg6817.dts @@ -0,0 +1,316 @@ +#include "qcom-ipq8065.dtsi" + +#include + +/ { + model = "ZyXEL NBG6817"; + compatible = "zyxel,nbg6817", "qcom,ipq8065", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + aliases { + mdio-gpio0 = &mdio0; + sdcc1 = &sdcc1; + + led-boot = &power; + led-failsafe = &power; + led-running = &power; + led-upgrade = &power; + }; + + chosen { + bootargs = "rootfstype=squashfs,ext4 rootwait noinitrd fstools_ignore_partname=1"; + append-rootblock = "root=/dev/mmcblk0p"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wifi { + label = "wifi"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + internet { + label = "white:internet"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; + }; + + power: power { + label = "white:power"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + wifi2g { + label = "amber:wifi2g"; + gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>; + }; + + /* wifi2g amber from the manual is missing */ + + wifi5g { + label = "amber:wifi5g"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + }; + + /* wifi5g amber from the manual is missing */ + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio53", "gpio54", "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio9", "gpio26", "gpio33", "gpio64"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + mdio0_pins: mdio0_pins { + clk { + pins = "gpio1"; + input-disable; + }; + }; + + rgmii2_pins: rgmii2_pins { + tx { + pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32" ; + input-disable; + }; + }; + + spi_pins: spi_pins { + cs { + pins = "gpio20"; + drive-strength = <12>; + }; + }; + + usb0_pwr_en_pins: usb0_pwr_en_pins { + mux { + pins = "gpio16", "gpio17"; + function = "gpio"; + drive-strength = <12>; + }; + + pwr { + pins = "gpio17"; + bias-pull-down; + output-high; + }; + + ovc { + pins = "gpio16"; + bias-pull-up; + }; + }; + + usb1_pwr_en_pins: usb1_pwr_en_pins { + mux { + pins = "gpio14", "gpio15"; + function = "gpio"; + drive-strength = <12>; + }; + + pwr { + pins = "gpio14"; + bias-pull-down; + output-high; + }; + + ovc { + pins = "gpio15"; + bias-pull-up; + }; + }; +}; + +&gsbi5 { + qcom,mode = ; + status = "okay"; + + spi4: spi@1a280000 { + status = "okay"; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + m25p80@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <51200000>; + reg = <0>; + + partitions { + compatible = "qcom,smem-part"; + }; + }; + }; +}; + +&usb3_0 { + status = "okay"; + + pinctrl-0 = <&usb0_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&usb3_1 { + status = "okay"; + + pinctrl-0 = <&usb1_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&pcie0 { + status = "okay"; + reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; +}; + +&pcie1 { + status = "okay"; + reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pcie1_pins>; + pinctrl-names = "default"; + max-link-speed = <1>; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + + phy0: ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x80 /* PAD6_MODE */ + 0x000e4 0xaa545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + 0x00970 0x1e864443 /* QM_PORT0_CTRL0 */ + 0x00974 0x000001c6 /* QM_PORT0_CTRL1 */ + 0x00978 0x19008643 /* QM_PORT1_CTRL0 */ + 0x0097c 0x000001c6 /* QM_PORT1_CTRL1 */ + 0x00980 0x19008643 /* QM_PORT2_CTRL0 */ + 0x00984 0x000001c6 /* QM_PORT2_CTRL1 */ + 0x00988 0x19008643 /* QM_PORT3_CTRL0 */ + 0x0098c 0x000001c6 /* QM_PORT3_CTRL1 */ + 0x00990 0x19008643 /* QM_PORT4_CTRL0 */ + 0x00994 0x000001c6 /* QM_PORT4_CTRL1 */ + 0x00998 0x1e864443 /* QM_PORT5_CTRL0 */ + 0x0099c 0x000001c6 /* QM_PORT5_CTRL1 */ + 0x009a0 0x1e864443 /* QM_PORT6_CTRL0 */ + 0x009a4 0x000001c6 /* QM_PORT6_CTRL1 */ + >; + }; + + phy4: ethernet-phy@4 { + reg = <4>; + qca,ar8327-initvals = < + 0x000e4 0x6a545 /* MAC_POWER_SEL */ + 0x0000c 0x80 /* PAD6_MODE */ + >; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <1>; + qcom,phy_mdio_addr = <4>; + qcom,poll_required = <0>; + qcom,rgmii_delay = <1>; + qcom,phy_mii_type = <0>; + qcom,emulation = <0>; + qcom,irq = <255>; + mdiobus = <&mdio0>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <2>; + qcom,phy_mdio_addr = <0>; /* none */ + qcom,poll_required = <0>; /* no polling */ + qcom,rgmii_delay = <0>; + qcom,phy_mii_type = <1>; + qcom,emulation = <0>; + qcom,irq = <258>; + mdiobus = <&mdio0>; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&amba { + sdcc1: sdcc@12400000 { + status = "okay"; + }; +}; + +&adm_dma { + status = "okay"; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi new file mode 100755 index 00000000..a1fde4d6 --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-nighthawk.dtsi @@ -0,0 +1,439 @@ +#include "qcom-ipq8065.dtsi" + +#include + +/ { + memory@0 { + reg = <0x42000000 0x1e000000>; + device_type = "memory"; + }; + + reserved-memory { + rsvd@5fe00000 { + reg = <0x5fe00000 0x200000>; + reusable; + }; + }; + + aliases { + label-mac-device = &gmac2; + + led-boot = &power_white; + led-failsafe = &power_amber; + led-running = &power_white; + led-upgrade = &power_amber; + + mdio-gpio0 = &mdio0; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + wifi { + label = "wifi"; + gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + power_white: power_white { + label = "white:power"; + gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + power_amber: power_amber { + label = "amber:power"; + gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; + }; + + wan_white { + label = "white:wan"; + gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; + }; + + wan_amber { + label = "amber:wan"; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; + }; + + wifi { + label = "white:wifi"; + gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>; + }; + + wps { + label = "white:wps"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio6", "gpio54", "gpio65"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio7", "gpio8", "gpio9", + "gpio22", "gpio23", "gpio24", + "gpio26", "gpio53", "gpio64"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + mdio0_pins: mdio0_pins { + clk { + pins = "gpio1"; + input-disable; + }; + }; + + rgmii2_pins: rgmii2_pins { + tx { + pins = "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio32"; + input-disable; + }; + }; + + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + bias-pull-down; + }; + + data { + pins = "gpio18", "gpio19"; + drive-strength = <10>; + }; + + cs { + pins = "gpio20"; + drive-strength = <10>; + bias-pull-up; + }; + + clk { + pins = "gpio21"; + drive-strength = <12>; + }; + }; + + spi6_pins: spi6_pins { + mux { + pins = "gpio55", "gpio56", "gpio58"; + function = "gsbi6"; + bias-pull-down; + }; + + mosi { + pins = "gpio55"; + drive-strength = <12>; + }; + + miso { + pins = "gpio56"; + drive-strength = <14>; + }; + + cs { + pins = "gpio57"; + drive-strength = <12>; + bias-pull-up; + }; + + clk { + pins = "gpio58"; + drive-strength = <12>; + }; + + reset { + pins = "gpio33"; + drive-strength = <10>; + bias-pull-down; + output-high; + }; + }; + + usb0_pwr_en_pins: usb0_pwr_en_pins { + mux { + pins = "gpio15"; + function = "gpio"; + drive-strength = <12>; + bias-pull-down; + output-high; + }; + }; + + usb1_pwr_en_pins: usb1_pwr_en_pins { + mux { + pins = "gpio16", "gpio68"; + function = "gpio"; + drive-strength = <12>; + bias-pull-down; + output-high; + }; + }; +}; + +&nand_controller { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + nand-is-boot-medium; + qcom,boot_pages_size = <0x1180000>; + + partitions: partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "qcadata"; + reg = <0x0000000 0x0c80000>; + read-only; + }; + + partition@c80000 { + label = "APPSBL"; + reg = <0x0c80000 0x0500000>; + read-only; + }; + + partition@1180000 { + label = "APPSBLENV"; + reg = <0x1180000 0x0080000>; + read-only; + }; + + art: partition@1200000 { + label = "art"; + reg = <0x1200000 0x0140000>; + read-only; + }; + + partition@1340000 { + label = "artbak"; + reg = <0x1340000 0x0140000>; + read-only; + }; + + partition@1480000 { + label = "kernel"; + reg = <0x1480000 0x0400000>; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x80 /* PAD6_MODE */ + 0x000e4 0xaa545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + 0x00970 0x1e864443 /* QM_PORT0_CTRL0 */ + 0x00974 0x000001c6 /* QM_PORT0_CTRL1 */ + 0x00978 0x19008643 /* QM_PORT1_CTRL0 */ + 0x0097c 0x000001c6 /* QM_PORT1_CTRL1 */ + 0x00980 0x19008643 /* QM_PORT2_CTRL0 */ + 0x00984 0x000001c6 /* QM_PORT2_CTRL1 */ + 0x00988 0x19008643 /* QM_PORT3_CTRL0 */ + 0x0098c 0x000001c6 /* QM_PORT3_CTRL1 */ + 0x00990 0x19008643 /* QM_PORT4_CTRL0 */ + 0x00994 0x000001c6 /* QM_PORT4_CTRL1 */ + 0x00998 0x1e864443 /* QM_PORT5_CTRL0 */ + 0x0099c 0x000001c6 /* QM_PORT5_CTRL1 */ + 0x009a0 0x1e864443 /* QM_PORT6_CTRL0 */ + 0x009a4 0x000001c6 /* QM_PORT6_CTRL1 */ + >; + qca,ar8327-vlans = < + 0x1 0x5e /* VLAN1 Ports 1/2/3/4/6 */ + 0x2 0x21 /* VLAN2 Ports 0/5 */ + >; + }; + + phy4: ethernet-phy@4 { + reg = <4>; + qca,ar8327-initvals = < + 0x000e4 0x6a545 /* MAC_POWER_SEL */ + 0x0000c 0x80 /* PAD6_MODE */ + >; + }; +}; + +&gmac1 { + status = "okay"; + + phy-mode = "rgmii"; + qcom,id = <1>; + qcom,phy_mdio_addr = <4>; + qcom,poll_required = <0>; + qcom,rgmii_delay = <1>; + qcom,phy_mii_type = <0>; + qcom,emulation = <0>; + qcom,irq = <255>; + mdiobus = <&mdio0>; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + nvmem-cells = <&macaddr_art_6>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac2 { + status = "okay"; + + phy-mode = "sgmii"; + qcom,id = <2>; + qcom,phy_mdio_addr = <0>; /* none */ + qcom,poll_required = <0>; /* no polling */ + qcom,rgmii_delay = <0>; + qcom,phy_mii_type = <1>; + qcom,emulation = <0>; + qcom,irq = <258>; + mdiobus = <&mdio0>; + + nvmem-cells = <&macaddr_art_0>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&sata_phy { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; + + pinctrl-0 = <&usb0_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&usb3_1 { + status = "okay"; + + pinctrl-0 = <&usb1_pwr_en_pins>; + pinctrl-names = "default"; +}; + +&pcie0 { + status = "okay"; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi0: wifi@1,0 { + compatible = "pci168c,0046"; + reg = <0x00010000 0 0 0 0>; + }; + }; +}; + +&pcie1 { + status = "okay"; + + max-link-speed = <1>; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi1: wifi@1,0 { + compatible = "pci168c,0046"; + reg = <0x00010000 0 0 0 0>; + }; + }; +}; + +&art { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_art_6: macaddr@6 { + reg = <0x6 0x6>; + }; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-r7800.dts b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-r7800.dts new file mode 100755 index 00000000..48beaf31 --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-r7800.dts @@ -0,0 +1,48 @@ +#include "qcom-ipq8065-nighthawk.dtsi" + +/ { + model = "Netgear Nighthawk X4S R7800"; + compatible = "netgear,r7800", "qcom,ipq8065", "qcom,ipq8064"; +}; + +&leds { + usb1 { + label = "white:usb1"; + gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>; + }; + + usb2 { + label = "white:usb2"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + esata { + label = "white:esata"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + }; +}; + +&partitions { + partition@1880000 { + label = "ubi"; + reg = <0x1880000 0x6080000>; + }; + + partition@7900000 { + label = "reserve"; + reg = <0x7900000 0x0700000>; + read-only; + }; +}; + +&wifi0 { + nvmem-cells = <&macaddr_art_6>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <(1)>; +}; + +&wifi1 { + nvmem-cells = <&macaddr_art_6>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <(2)>; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts new file mode 100755 index 00000000..0ad2dfa5 --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts @@ -0,0 +1,321 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "qcom-ipq8065.dtsi" +#include + +/ { + model = "Askey RT4230W REV6"; + compatible = "askey,rt4230w-rev6", "qcom,ipq8065", "qcom,ipq8064"; + + memory@0 { + reg = <0x42000000 0x3e000000>; + device_type = "memory"; + }; + + aliases { + led-boot = &ledctrl3; + led-failsafe = &ledctrl1; + led-running = &ledctrl2; + led-upgrade = &ledctrl3; + }; + + chosen { + bootargs = "rootfstype=squashfs noinitrd"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + wps { + label = "wps"; + gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + ledctrl1: ledctrl1 { + label = "ledctrl1"; + gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>; + }; + + ledctrl2: ledctrl2 { + label = "ledctrl2"; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; + }; + + ledctrl3: ledctrl3 { + label = "ledctrl3"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&qcom_pinmux { + button_pins: button_pins { + mux { + pins = "gpio54", "gpio68"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio22", "gpio23", "gpio24"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + rgmii2_pins: rgmii2_pins { + mux { + pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", + "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62"; + function = "rgmii2"; + drive-strength = <8>; + bias-disable; + }; + + tx { + pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32"; + input-disable; + }; + }; +}; + +&nand_controller { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand@0 { + reg = <0>; + compatible = "qcom,nandcs"; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "0:SBL1"; + reg = <0x0000000 0x0040000>; + read-only; + }; + partition@40000 { + label = "0:MIBIB"; + reg = <0x0040000 0x0140000>; + read-only; + }; + partition@180000 { + label = "0:SBL2"; + reg = <0x0180000 0x0140000>; + read-only; + }; + partition@2c0000 { + label = "0:SBL3"; + reg = <0x02c0000 0x0280000>; + read-only; + }; + partition@540000 { + label = "0:DDRCONFIG"; + reg = <0x0540000 0x0120000>; + read-only; + }; + partition@660000 { + label = "0:SSD"; + reg = <0x0660000 0x0120000>; + read-only; + }; + partition@780000 { + label = "0:TZ"; + reg = <0x0780000 0x0280000>; + read-only; + }; + partition@a00000 { + label = "0:RPM"; + reg = <0x0a00000 0x0280000>; + read-only; + }; + partition@c80000 { + label = "0:APPSBL"; + reg = <0x0c80000 0x0500000>; + read-only; + }; + partition@1180000 { + label = "0:APPSBLENV"; + reg = <0x1180000 0x0080000>; + }; + ART: partition@1200000 { + label = "0:ART"; + reg = <0x1200000 0x0140000>; + read-only; + }; + partition@1340000 { + label = "0:BOOTCONFIG"; + reg = <0x1340000 0x0060000>; + read-only; + }; + partition@13a0000 { + label = "0:SBL2_1"; + reg = <0x13a0000 0x0140000>; + read-only; + }; + partition@14e0000 { + label = "0:SBL3_1"; + reg = <0x14e0000 0x0280000>; + read-only; + }; + partition@1760000 { + label = "0:DDRCONFIG_1"; + reg = <0x1760000 0x0120000>; + read-only; + }; + partition@1880000 { + label = "0:SSD_1"; + reg = <0x1880000 0x0120000>; + read-only; + }; + partition@19a0000 { + label = "0:TZ_1"; + reg = <0x19a0000 0x0280000>; + read-only; + }; + partition@1c20000 { + label = "0:RPM_1"; + reg = <0x1c20000 0x0280000>; + read-only; + }; + partition@1ea0000 { + label = "0:BOOTCONFIG1"; + reg = <0x1ea0000 0x0060000>; + read-only; + }; + partition@1f00000 { + label = "0:APPSBL_1"; + reg = <0x1f00000 0x0500000>; + read-only; + }; + partition@2400000 { + label = "ubi"; + reg = <0x2400000 0x1a000000>; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0x0>; + qca,ar8327-initvals = < + 0x00004 0x7600000 /* PAD0_MODE */ + 0x00008 0x1000000 /* PAD5_MODE */ + 0x0000c 0x80 /* PAD6_MODE */ + 0x000e4 0xaa545 /* MAC_POWER_SEL */ + 0x000e0 0xc74164de /* SGMII_CTRL */ + 0x0007c 0x4e /* PORT0_STATUS */ + 0x00094 0x4e /* PORT6_STATUS */ + 0x00050 0xcf02cf02 /* LED_CTRL_0 */ + 0x00054 0xc832c832 /* LED_CTRL_1 */ + >; + }; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + qcom,id = <0>; + + nvmem-cells = <&macaddr_ART_0>; + nvmem-cell-names = "mac-address"; + + pinctrl-0 = <&rgmii2_pins>; + pinctrl-names = "default"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "sgmii"; + qcom,id = <1>; + + nvmem-cells = <&macaddr_ART_6>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; + clocks = <&gcc USB30_1_MASTER_CLK>; +}; + +&usb3_1 { + status = "okay"; + clocks = <&gcc USB30_0_MASTER_CLK>; +}; + +&pcie0 { + status = "okay"; + reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pcie0_pins>; + pinctrl-names = "default"; +}; + +&pcie1 { + status = "okay"; + reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&pcie1_pins>; + pinctrl-names = "default"; + max-link-speed = <1>; +}; + +&ART { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_ART_0: macaddr@0 { + reg = <0x0 0x6>; + }; + + macaddr_ART_6: macaddr@6 { + reg = <0x6 0x6>; + }; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-xr500.dts b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-xr500.dts new file mode 100755 index 00000000..b7f00a7a --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-xr500.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include "qcom-ipq8065-nighthawk.dtsi" + +/ { + model = "Netgear Nighthawk XR500"; + compatible = "netgear,xr500", "qcom,ipq8065", "qcom,ipq8064"; + +}; + +&leds { + usb1 { + label = "white:usb1"; + gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>; + }; + + usb2 { + label = "white:usb2"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>; + }; +}; + +&partitions { + partition@1880000 { + label = "ubi"; + reg = <0x1880000 0xce00000>; + }; + + partition@e680000 { + label = "reserve"; + reg = <0xe680000 0x0780000>; + read-only; + }; +}; + +&wifi0 { + nvmem-cells = <&macaddr_art_c>; + nvmem-cell-names = "mac-address"; +}; + +&wifi1 { + nvmem-cells = <&macaddr_art_0>; + nvmem-cell-names = "mac-address"; +}; + +&art { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_art_c: macaddr@c { + reg = <0xc 0x6>; + }; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065.dtsi b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065.dtsi new file mode 100755 index 00000000..c70a5cba --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065.dtsi @@ -0,0 +1,167 @@ +#include "qcom-ipq8064.dtsi" + +/ { + model = "Qualcomm IPQ8065"; + compatible = "qcom,ipq8065", "qcom,ipq8064"; + + aliases { + serial0 = &gsbi4_serial; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + rsvd@41200000 { + reg = <0x41200000 0x300000>; + no-map; + }; + }; +}; + +&gsbi4 { + qcom,mode = ; + status = "okay"; + + serial@16340000 { + status = "okay"; + }; + /* + * The i2c device on gsbi4 should not be enabled. + * On ipq806x designs gsbi4 i2c is meant for exclusive + * RPM usage. Turning this on in kernel manifests as + * i2c failure for the RPM. + */ +}; + +&pcie0 { + compatible = "qcom,pcie-ipq8064-v2"; +}; + +&pcie1 { + compatible = "qcom,pcie-ipq8064-v2"; +}; + +&pcie2 { + compatible = "qcom,pcie-ipq8064-v2"; +}; + +&sata { + ports-implemented = <0x1>; +}; + +&smb208_s2a { + regulator-min-microvolt = <775000>; + regulator-max-microvolt = <1275000>; +}; + +&smb208_s2b { + regulator-min-microvolt = <775000>; + regulator-max-microvolt = <1275000>; +}; + +&ss_phy_0 { + qcom,rx-eq = <2>; + qcom,tx-deamp_3_5db = <32>; + qcom,mpll = <5>; +}; + +&ss_phy_1 { + qcom,rx-eq = <2>; + qcom,tx-deamp_3_5db = <32>; + qcom,mpll = <5>; +}; + +&opp_table_l2 { + /delete-node/opp-1200000000; + + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <1150000>; + clock-latency-ns = <100000>; + opp-level = <2>; + }; +}; + +&opp_table0 { + /* + * On ipq8065 1.2 ghz freq is not present + * Remove it to make cpufreq work and not + * complain for missing definition + */ + + /delete-node/opp-1200000000; + + /* + * Voltage thresholds are + */ + opp-384000000 { + opp-microvolt-speed0-pvs0-v0 = <975000 926250 1023750>; + opp-microvolt-speed0-pvs1-v0 = <950000 902500 997500>; + opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>; + opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>; + opp-microvolt-speed0-pvs4-v0 = <875000 831250 918750>; + opp-microvolt-speed0-pvs5-v0 = <825000 783750 866250>; + opp-microvolt-speed0-pvs6-v0 = <775000 736250 813750>; + }; + + opp-600000000 { + opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>; + opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>; + opp-microvolt-speed0-pvs2-v0 = <950000 902500 997500>; + opp-microvolt-speed0-pvs3-v0 = <925000 878750 971250>; + opp-microvolt-speed0-pvs4-v0 = <900000 855000 945000>; + opp-microvolt-speed0-pvs5-v0 = <850000 807500 892500>; + opp-microvolt-speed0-pvs6-v0 = <800000 760000 840000>; + }; + + opp-800000000 { + opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>; + opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>; + opp-microvolt-speed0-pvs2-v0 = <1000000 950000 1050000>; + opp-microvolt-speed0-pvs3-v0 = <975000 926250 1023750>; + opp-microvolt-speed0-pvs4-v0 = <950000 902500 997500>; + opp-microvolt-speed0-pvs5-v0 = <900000 855000 945000>; + opp-microvolt-speed0-pvs6-v0 = <850000 807500 892500>; + }; + + opp-1000000000 { + opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>; + opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>; + opp-microvolt-speed0-pvs2-v0 = <1050000 997500 1102500>; + opp-microvolt-speed0-pvs3-v0 = <1025000 973750 1076250>; + opp-microvolt-speed0-pvs4-v0 = <1000000 950000 1050000>; + opp-microvolt-speed0-pvs5-v0 = <950000 902500 997500>; + opp-microvolt-speed0-pvs6-v0 = <900000 855000 945000>; + }; + + opp-1400000000 { + opp-microvolt-speed0-pvs0-v0 = <1175000 1116250 1233750>; + opp-microvolt-speed0-pvs1-v0 = <1150000 1092500 1207500>; + opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>; + opp-microvolt-speed0-pvs3-v0 = <1100000 1045000 1155000>; + opp-microvolt-speed0-pvs4-v0 = <1075000 1021250 1128750>; + opp-microvolt-speed0-pvs5-v0 = <1025000 973750 1076250>; + opp-microvolt-speed0-pvs6-v0 = <975000 926250 1023750>; + opp-level = <1>; + }; + + opp-1725000000 { + opp-hz = /bits/ 64 <1725000000>; + opp-microvolt-speed0-pvs0-v0 = <1262500 1199375 1325625>; + opp-microvolt-speed0-pvs1-v0 = <1225000 1163750 1286250>; + opp-microvolt-speed0-pvs2-v0 = <1200000 1140000 1260000>; + opp-microvolt-speed0-pvs3-v0 = <1175000 1116250 1233750>; + opp-microvolt-speed0-pvs4-v0 = <1150000 1092500 1207500>; + opp-microvolt-speed0-pvs5-v0 = <1100000 1045000 1155000>; + opp-microvolt-speed0-pvs6-v0 = <1050000 997500 1102500>; + opp-supported-hw = <0x1>; + clock-latency-ns = <100000>; + opp-level = <2>; + }; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi new file mode 100755 index 00000000..10ab4821 --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-cryptid-common.dtsi @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT + +#include "qcom-ipq8064-v2.0.dtsi" + +/ { + memory { + device_type = "memory"; + linux,usable-memory = <0x41500000 0x1ea00000>; + reg = <0x40000000 0x20000000>; + }; + + cpus { + idle-states { + CPU_SPC: spc { + status = "disabled"; + }; + }; + }; + + chosen { + bootargs-append = " console=ttyMSM0,115200n8 ubi.mtd=ubi ubi.mtd=art"; + }; +}; + +&qcom_pinmux { + mdio0_pins_active: mdio0_pins_active { + mux { + pins = "gpio0", "gpio1"; + function = "mdio"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + + clk { + pins = "gpio1"; + input-disable; + }; + }; + + phy_active: phy_active { + phy { + pins = "gpio6", "gpio7"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + output-high; + }; + }; + + uart1_pins: uart1_pins { + mux { + pins = "gpio51", "gpio52"; + function = "gsbi1"; + drive-strength = <4>; + bias-disable; + }; + }; +}; + +&gsbi1 { + status = "okay"; + qcom,mode = ; + + serial@12450000 { + status = "okay"; + + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + }; +}; + +&pcie0 { + status = "okay"; + + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + /delete-property/ perst-gpios; + + bridge@0,0 { + reg = <0x0 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi0: wifi@1,0 { + compatible = "qcom,ath10k"; + status = "okay"; + reg = <0x10000 0 0 0 0>; + }; + }; +}; + +&pcie1 { + status = "okay"; + + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + /delete-property/ perst-gpios; + + bridge@0,0 { + reg = <0x0 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi1: wifi@1,0 { + compatible = "qcom,ath10k"; + status = "okay"; + reg = <0x10000 0 0 0 0>; + }; + }; +}; + +&pcie2 { + status = "okay"; + + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + /delete-property/ perst-gpios; + + bridge@0,0 { + reg = <0x0 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi2: wifi@1,0 { + compatible = "qcom,ath10k"; + status = "okay"; + reg = <0x10000 0 0 0 0>; + }; + }; +}; + +&adm_dma { + status = "okay"; +}; + +&nand_controller { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand@0 { + compatible = "qcom,nandcs"; + + reg = <0>; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + nand-is-boot-medium; + qcom,boot_pages_size = <0x2140000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "sbl1"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "mibib"; + reg = <0x40000 0x140000>; + read-only; + }; + + partition@180000 { + label = "sbl2"; + reg = <0x180000 0x140000>; + read-only; + }; + + partition@2c0000 { + label = "sbl3"; + reg = <0x2c0000 0x280000>; + read-only; + }; + + partition@540000 { + label = "ddrconfig"; + reg = <0x540000 0x120000>; + read-only; + }; + + partition@660000 { + label = "ssd"; + reg = <0x660000 0x120000>; + read-only; + }; + + partition@780000 { + label = "tz"; + reg = <0x780000 0x280000>; + read-only; + }; + + partition@a00000 { + label = "rpm"; + reg = <0xa00000 0x280000>; + read-only; + }; + + partition@1fc0000 { + label = "u-boot"; + reg = <0x1fc0000 0x180000>; + read-only; + }; + + partition@21c0000 { + label = "bootkernel1"; + reg = <0x21c0000 0xa80000>; + }; + + partition@2c40000 { + label = "bootkernel2"; + reg = <0x2c40000 0xa80000>; + }; + + partition@36c0000 { + label = "ubi"; + reg = <0x36c0000 0x46c0000>; + }; + + partition@7d80000 { + label = "art"; + reg = <0x7d80000 0x200000>; + read-only; + }; + }; + }; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts new file mode 100755 index 00000000..377bb096 --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-ecw5410.dts @@ -0,0 +1,332 @@ +#include "qcom-ipq8064-v2.0.dtsi" + +#include +#include + +/ { + model = "Edgecore ECW5410"; + compatible = "edgecore,ecw5410", "qcom,ipq8064"; + + reserved-memory { + nss@40000000 { + reg = <0x40000000 0x1000000>; + no-map; + }; + + smem: smem@41000000 { + reg = <0x41000000 0x200000>; + no-map; + }; + + wifi_dump@44000000 { + reg = <0x44000000 0x600000>; + no-map; + }; + }; + + cpus { + idle-states { + CPU_SPC: spc { + status = "disabled"; + }; + }; + }; + + aliases { + serial1 = &gsbi1_serial; + ethernet0 = &gmac2; + ethernet1 = &gmac3; + + led-boot = &led_power_green; + led-failsafe = &led_power_red; + led-running = &led_power_green; + led-upgrade = &led_power_green; + }; + + chosen { + bootargs-append = " console=ttyMSM0,115200n8 root=/dev/ubiblock0_1"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + led_power_green: power_green { + label = "green:power"; + gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>; + }; + + wlan2g_green { + label = "green:wlan2g"; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_LOW>; + }; + + wlan2g_yellow { + label = "yellow:wlan2g"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>; + }; + + wlan5g_green { + label = "green:wlan5g"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; + }; + + led_power_red: power_red { + label = "red:power"; + gpios = <&qcom_pinmux 28 GPIO_ACTIVE_LOW>; + }; + + wlan5g_yellow { + label = "yellow:wlan5g"; + gpios = <&qcom_pinmux 59 GPIO_ACTIVE_LOW>; + }; + }; +}; + + +&qcom_pinmux { + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19"; + function = "gsbi5"; + drive-strength = <10>; + bias-pull-down; + }; + + clk { + pins = "gpio21"; + function = "gsbi5"; + drive-strength = <12>; + bias-pull-down; + }; + + cs { + pins = "gpio20"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio16", "gpio23", "gpio24", "gpio26", + "gpio28", "gpio59"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + button_pins: button_pins { + mux { + pins = "gpio25"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + uart1_pins: uart1_pins { + mux { + pins = "gpio51", "gpio52", "gpio53", "gpio54"; + function = "gsbi1"; + drive-strength = <12>; + bias-none; + }; + }; +}; + +&gsbi1 { + qcom,mode = ; + status = "okay"; + + serial@12450000 { + status = "okay"; + + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + }; +}; + +&gsbi5 { + qcom,mode = ; + status = "okay"; + + spi4: spi@1a280000 { + status = "okay"; + spi-max-frequency = <50000000>; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>; + + m25p80@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + + partitions { + compatible = "qcom,smem-part"; + }; + }; + }; +}; + +&hs_phy_0 { /* USB3 port 0 HS phy */ + status = "okay"; +}; + +&hs_phy_1 { /* USB3 port 1 HS phy */ + status = "okay"; +}; + +&ss_phy_0 { /* USB3 port 0 SS phy */ + status = "okay"; +}; + +&ss_phy_1 { /* USB3 port 1 SS phy */ + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; + + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + /delete-property/ perst-gpios; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + status = "okay"; + reg = <0x00010000 0 0 0 0>; + qcom,ath10k-calibration-variant = "Edgecore-ECW5410-L"; + }; + }; +}; + +&pcie2 { + status = "okay"; + + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + /delete-property/ perst-gpios; + + bridge@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi@1,0 { + compatible = "qcom,ath10k"; + status = "okay"; + reg = <0x00010000 0 0 0 0>; + qcom,ath10k-calibration-variant = "Edgecore-ECW5410-L"; + }; + }; +}; + +&nand_controller { + status = "okay"; + + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + + nand@0 { + compatible = "qcom,nandcs"; + + reg = <0>; + + nand-ecc-strength = <4>; + nand-bus-width = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + rootfs1@0 { + label = "rootfs1"; + reg = <0x0000000 0x4000000>; + }; + + rootfs2@4000000 { + label = "rootfs2"; + reg = <0x4000000 0x4000000>; + }; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins>; + pinctrl-names = "default"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&gmac2 { + status = "okay"; + + qcom,id = <2>; + mdiobus = <&mdio0>; + + phy-mode = "sgmii"; + phy-handle = <&phy1>; +}; + +&gmac3 { + status = "okay"; + + qcom,id = <3>; + mdiobus = <&mdio0>; + + phy-mode = "sgmii"; + phy-handle = <&phy0>; +}; + +&adm_dma { + status = "okay"; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr42.dts b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr42.dts new file mode 100755 index 00000000..ccf2554c --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr42.dts @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT + +#include "qcom-ipq8068-cryptid-common.dtsi" + +#include + +/ { + model = "Meraki MR42"; + compatible = "meraki,mr42", "qcom,ipq8064"; + + aliases { + serial1 = &gsbi1_serial; + ethernet0 = &gmac3; + + led-boot = &led_active; + led-failsafe = &led_power; + led-running = &led_active; + led-upgrade = &led_active; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + led_power: power { + label = "orange:power"; + gpios = <&qcom_pinmux 31 GPIO_ACTIVE_HIGH>; + }; + + led_active: active { + label = "white:active"; + gpios = <&qcom_pinmux 32 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&gmac3 { + status = "okay"; + + qcom,id = <3>; + mdiobus = <&mdio0>; + + phy-mode = "sgmii"; + phy-handle = <&phy2>; + + nvmem-cells = <&mac_address>; + nvmem-cell-names = "mac-address"; +}; + +&gsbi2 { + status = "okay"; + qcom,mode = ; +}; + +&gsbi2_i2c { + status = "okay"; + + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + ina2xx@40 { + compatible = "ina219"; + shunt-resistor = <40000>; + reg = <0x40>; + }; + + eeprom@56 { + compatible = "atmel,24c64"; + pagesize = <32>; + reg = <0x56>; + read-only; + #address-cells = <1>; + #size-cells = <1>; + + mac_address: mac-address@66 { + reg = <0x66 0x6>; + }; + }; +}; + +&gsbi6 { + qcom,mode = ; + status = "okay"; +}; + +&gsbi6_i2c { + status = "okay"; + + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + tlc591xx@40 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ti,tlc59108"; + reg = <0x40>; + + red@0 { + label = "red:user"; + reg = <0x0>; + }; + + green@1 { + label = "green:user"; + reg = <0x1>; + }; + + blue@2 { + label = "blue:user"; + reg = <0x2>; + }; + }; +}; + +&mdio0 { + status = "okay"; + + pinctrl-0 = <&mdio0_pins_active>, <&phy_active>; + pinctrl-names = "default"; + + phy2: ethernet-phy2 { + reg = <2>; + + reset-gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + reset-assert-us = <24000>; + + eee-broken-100tx; + eee-broken-1000t; + }; +}; + +&qcom_pinmux { + i2c0_pins: i2c0_pins { + mux { + pins = "gpio24", "gpio25"; + function = "gsbi2"; + drive-strength = <2>; + bias-pull-up; + input; + }; + }; + + button_pins: button_pins { + mux { + pins = "gpio26"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c1_pins: i2c1_pins { + mux { + pins = "gpio29", "gpio30"; + function = "gsbi6"; + drive-strength = <2>; + bias-pull-up; + input; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio31", "gpio32"; + function = "gpio"; + drive-strength = <12>; + bias-pull-down; + output-low; + }; + }; +}; + +&wifi0 { + nvmem-cells = <&mac_address>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <1>; +}; + +&wifi1 { + nvmem-cells = <&mac_address>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <2>; +}; + +&wifi2 { + nvmem-cells = <&mac_address>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <3>; +}; diff --git a/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr52.dts b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr52.dts new file mode 100755 index 00000000..e1c23325 --- /dev/null +++ b/root/target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8068-mr52.dts @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT + +#include "qcom-ipq8068-cryptid-common.dtsi" + +#include + +/ { + model = "Meraki MR52"; + compatible = "meraki,mr52", "qcom,ipq8064"; + + aliases { + serial1 = &gsbi1_serial; + mdio-gpio0 = &mdio_gpio0; + ethernet0 = &gmac2; + ethernet1 = &gmac3; + + led-boot = &led_active; + led-failsafe = &led_power; + led-running = &led_active; + led-upgrade = &led_active; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&button_pins>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <60>; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&led_pins>; + pinctrl-names = "default"; + + led_power: power { + label = "orange:power"; + gpios = <&qcom_pinmux 19 GPIO_ACTIVE_HIGH>; + }; + + lan2_green { + label = "green:lan2"; + gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>; + }; + + lan1_green { + label = "green:lan1"; + gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>; + }; + + led_active: active { + label = "white:active"; + gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>; + }; + + lan2_orange { + label = "orange:lan2"; + gpios = <&qcom_pinmux 60 GPIO_ACTIVE_HIGH>; + }; + + lan1_orange { + label = "orange:lan1"; + gpios = <&qcom_pinmux 62 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&gmac2 { + status = "okay"; + + qcom,id = <2>; + mdiobus = <&mdio0>; + + phy-mode = "sgmii"; + phy-handle = <&phy0>; + + nvmem-cells = <&mac_address>; + nvmem-cell-names = "mac-address"; +}; + +&gmac3 { + status = "okay"; + + qcom,id = <3>; + mdiobus = <&mdio_gpio0>; + + phy-mode = "sgmii"; + phy-handle = <&phy4>; + + nvmem-cells = <&mac_address>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <1>; +}; + +&gsbi7 { + status = "okay"; + qcom,mode = ; +}; + +&gsbi7_i2c { + status = "okay"; + + pinctrl-0 = <&i2c_pins>; + pinctrl-names = "default"; + + ina2xx@45 { + compatible = "ina219"; + shunt-resistor = <80000>; + reg = <0x45>; + }; + + tlc591xx@49 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ti,tlc59108"; + reg = <0x49>; + + red@0 { + label = "red:user"; + reg = <0x0>; + }; + + green@1 { + label = "green:user"; + reg = <0x1>; + }; + + blue@2 { + label = "blue:user"; + reg = <0x2>; + }; + }; + + eeprom@52 { + compatible = "atmel,24c64"; + pagesize = <32>; + reg = <0x52>; + read-only; + #address-cells = <1>; + #size-cells = <1>; + + mac_address: mac-address@66 { + reg = <0x66 0x6>; + }; + }; +}; + +&qcom_pinmux { + i2c_pins: i2c_pins { + mux { + pins = "gpio8", "gpio9"; + function = "gsbi7"; + drive-strength = <2>; + bias-pull-up; + input; + }; + }; + + led_pins: led_pins { + mux { + pins = "gpio19", "gpio26"; + function = "gpio"; + drive-strength = <12>; + bias-pull-down; + output-low; + }; + }; + + button_pins: button_pins { + mux { + pins = "gpio25"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + input; + }; + }; +}; + +&soc { + mdio_gpio0: mdio { + compatible = "virtual,mdio-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + status = "okay"; + + pinctrl-0 = <&mdio0_pins_active>, <&phy_active>; + pinctrl-names = "default"; + + gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH + &qcom_pinmux 0 GPIO_ACTIVE_HIGH>; + + phy0: ethernet-phy0 { + reg = <0>; + reset-gpios = <&qcom_pinmux 7 GPIO_ACTIVE_LOW>; + reset-assert-us = <24000>; + }; + + phy4: ethernet-phy4 { + reg = <4>; + reset-gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>; + reset-assert-us = <24000>; + }; + }; +}; + +&wifi0 { + nvmem-cells = <&mac_address>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <4>; +}; + +&wifi1 { + nvmem-cells = <&mac_address>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <3>; +}; + +&wifi2 { + nvmem-cells = <&mac_address>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <2>; +}; diff --git a/root/target/linux/ipq806x/generic/target.mk b/root/target/linux/ipq806x/generic/target.mk new file mode 100755 index 00000000..f5cb1fb1 --- /dev/null +++ b/root/target/linux/ipq806x/generic/target.mk @@ -0,0 +1 @@ +BOARDNAME:=Generic diff --git a/root/target/linux/ipq806x/image/Makefile b/root/target/linux/ipq806x/image/Makefile new file mode 100755 index 00000000..fc0080cf --- /dev/null +++ b/root/target/linux/ipq806x/image/Makefile @@ -0,0 +1,473 @@ +# Copyright (c) 2014 The Linux Foundation. All rights reserved. +# +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +DEVICE_VARS += NETGEAR_BOARD_ID NETGEAR_HW_ID +DEVICE_VARS += TPLINK_BOARD_ID + +define Build/buffalo-rootfs-cksum + ( \ + echo -ne "\x$$(od -A n -t u1 $@ | tr -s ' ' '\n' | \ + $(STAGING_DIR_HOST)/bin/awk '{s+=$$0}END{printf "%x", 255-s%256}')"; \ + ) >> $@ +endef + +define Build/edimax-header + $(eval edimax_model=$(word 1,$(1))) + + $(STAGING_DIR_HOST)/bin/mkedimaximg \ + -b -s CSYS -m $(edimax_model) \ + -f 0x70000 -S 0x1200000 \ + -i $@ -o $@.new + @mv $@.new $@ +endef + +define Device/Default + PROFILES := Default + KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts) + KERNEL_LOADADDR = 0x42208000 + DEVICE_DTS = $$(SOC)-$(lastword $(subst _, ,$(1))) + DEVICE_DTS_CONFIG := config@1 + IMAGES := sysupgrade.bin + IMAGE/sysupgrade.bin = sysupgrade-tar | append-metadata + IMAGE/sysupgrade.bin/squashfs := +endef + +define Device/LegacyImage + KERNEL_SUFFIX := -uImage + KERNEL = kernel-bin | append-dtb | uImage none + KERNEL_NAME := zImage +endef + +define Device/FitImage + KERNEL_SUFFIX := -fit-uImage.itb + KERNEL = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb + KERNEL_NAME := Image +endef + +define Device/FitImageLzma + KERNEL_SUFFIX := -fit-uImage.itb + KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb + KERNEL_NAME := Image +endef + +define Device/UbiFit + KERNEL_IN_UBI := 1 + IMAGES := nand-factory.bin nand-sysupgrade.bin + IMAGE/nand-factory.bin := append-ubi + IMAGE/nand-sysupgrade.bin := sysupgrade-tar | append-metadata +endef + +define Device/DniImage + KERNEL_SUFFIX := -uImage + KERNEL = kernel-bin | append-dtb | uImage none + KERNEL_NAME := zImage + NETGEAR_BOARD_ID := + NETGEAR_HW_ID := + UBINIZE_OPTS := -E 5 + IMAGES += factory.img + IMAGE/factory.img := append-kernel | pad-offset $$$$(BLOCKSIZE) 64 | append-uImage-fakehdr filesystem | pad-to $$$$(KERNEL_SIZE) | append-ubi | netgear-dni + IMAGE/sysupgrade.bin := append-kernel | pad-offset $$$$(BLOCKSIZE) 64 | append-uImage-fakehdr filesystem | sysupgrade-tar kernel=$$$$@ | append-metadata +endef + +define Device/TpSafeImage + KERNEL_SUFFIX := -uImage + KERNEL = kernel-bin | append-dtb | uImage none + KERNEL_NAME := zImage + TPLINK_BOARD_ID := + IMAGES += factory.bin + IMAGE/factory.bin := append-rootfs | tplink-safeloader factory + IMAGE/sysupgrade.bin := append-rootfs | tplink-safeloader sysupgrade | append-metadata +endef + +define Device/ZyXELImage + KERNEL_SUFFIX := -uImage + KERNEL = kernel-bin | append-dtb | uImage none | pad-to $$(KERNEL_SIZE) + KERNEL_NAME := zImage + IMAGES += factory.bin + IMAGE/factory.bin := append-rootfs | pad-rootfs | pad-to $$$$(BLOCKSIZE) | zyxel-ras-image separate-kernel + IMAGE/sysupgrade.bin/squashfs := append-rootfs | pad-to $$$$(BLOCKSIZE) | sysupgrade-tar rootfs=$$$$@ | append-metadata +endef + +define Device/askey_rt4230w-rev6 + $(call Device/LegacyImage) + DEVICE_VENDOR := Askey + DEVICE_MODEL := RT4230W + DEVICE_VARIANT := REV6 + SOC := qcom-ipq8065 + BLOCKSIZE := 128k + PAGESIZE := 2048 + DEVICE_PACKAGES := ath10k-firmware-qca9984-ct + KERNEL_IN_UBI := 1 +endef +TARGET_DEVICES += askey_rt4230w-rev6 + +define Device/asrock_g10 + $(call Device/FitImage) + $(call Device/UbiFit) + SOC := qcom-ipq8064 + DEVICE_VENDOR := ASRock + DEVICE_MODEL := G10 + BLOCKSIZE := 128k + PAGESIZE := 2048 + KERNEL_SIZE := 5332k + DEVICE_PACKAGES := kmod-i2c-gpio ath10k-firmware-qca99x0-ct + IMAGE/nand-factory.bin := append-ubi | edimax-header RN67 +endef +TARGET_DEVICES += asrock_g10 + +define Device/buffalo_wxr-2533dhp + $(call Device/LegacyImage) + SOC := qcom-ipq8064 + DEVICE_VENDOR := Buffalo + DEVICE_MODEL := WXR-2533DHP + BLOCKSIZE := 128k + PAGESIZE := 2048 + IMAGE_SIZE := 65536k + KERNEL_IN_UBI := 1 + IMAGE/sysupgrade.bin := append-rootfs | buffalo-rootfs-cksum | \ + sysupgrade-tar rootfs=$$$$@ | append-metadata + DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct +endef +TARGET_DEVICES += buffalo_wxr-2533dhp + +define Device/compex_wpq864 + $(call Device/FitImage) + $(call Device/UbiFit) + DEVICE_VENDOR := Compex + DEVICE_MODEL := WPQ864 + BLOCKSIZE := 128k + PAGESIZE := 2048 + SOC := qcom-ipq8064 + DEVICE_PACKAGES := kmod-gpio-beeper +endef +TARGET_DEVICES += compex_wpq864 + +define Device/edgecore_ecw5410 + $(call Device/FitImage) + $(call Device/UbiFit) + DEVICE_VENDOR := Edgecore + DEVICE_MODEL := ECW5410 + SOC := qcom-ipq8068 + BLOCKSIZE := 128k + PAGESIZE := 2048 + DEVICE_DTS_CONFIG := config@v2.0-ap160 + DEVICE_PACKAGES := ath10k-firmware-qca9984-ct ipq-wifi-edgecore_ecw5410 +endef +TARGET_DEVICES += edgecore_ecw5410 + +define Device/linksys_ea7500-v1 + $(call Device/LegacyImage) + DEVICE_VENDOR := Linksys + DEVICE_MODEL := EA7500 + DEVICE_VARIANT := v1 + SOC := qcom-ipq8064 + PAGESIZE := 2048 + BLOCKSIZE := 128k + KERNEL_SIZE := 3072k + KERNEL = kernel-bin | append-dtb | uImage none | append-uImage-fakehdr filesystem + UBINIZE_OPTS := -E 5 + IMAGES := factory.bin sysupgrade.bin + IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | pad-to $$$$(PAGESIZE) + DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct +endef +TARGET_DEVICES += linksys_ea7500-v1 + +define Device/linksys_ea8500 + $(call Device/LegacyImage) + DEVICE_VENDOR := Linksys + DEVICE_MODEL := EA8500 + SOC := qcom-ipq8064 + PAGESIZE := 2048 + BLOCKSIZE := 128k + KERNEL_SIZE := 3072k + KERNEL = kernel-bin | append-dtb | uImage none | append-uImage-fakehdr filesystem + BOARD_NAME := ea8500 + SUPPORTED_DEVICES += ea8500 + UBINIZE_OPTS := -E 5 + IMAGES += factory.bin + IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi + DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct +endef +TARGET_DEVICES += linksys_ea8500 + +define Device/meraki_mr42 + $(call Device/FitImage) + DEVICE_VENDOR := Cisco Meraki + DEVICE_MODEL := MR42 + SOC := qcom-ipq8068 + BLOCKSIZE := 128k + PAGESIZE := 2048 + KERNEL_LOADADDR = 0x44208000 + DEVICE_PACKAGES := -swconfig -kmod-ata-ahci -kmod-ata-ahci-platform \ + -kmod-usb-ohci -kmod-usb2 -kmod-usb-ledtrig-usbport \ + -kmod-phy-qcom-ipq806x-usb -kmod-usb3 -kmod-usb-dwc3-qcom \ + -uboot-envtools ath10k-firmware-qca9887-ct \ + ath10k-firmware-qca99x0-ct kmod-eeprom-at24 kmod-hwmon-ina2xx \ + kmod-leds-tlc591xx +endef +TARGET_DEVICES += meraki_mr42 + +define Device/meraki_mr52 + $(call Device/FitImage) + DEVICE_VENDOR := Cisco Meraki + DEVICE_MODEL := MR52 + SOC := qcom-ipq8068 + BLOCKSIZE := 128k + PAGESIZE := 2048 + KERNEL_LOADADDR = 0x44208000 + DEVICE_DTS_CONFIG := config@2 + DEVICE_PACKAGES := -swconfig -kmod-ata-ahci -kmod-ata-ahci-platform \ + -kmod-usb-ohci -kmod-usb2 -kmod-usb-ledtrig-usbport \ + -kmod-phy-qcom-ipq806x-usb -kmod-usb3 -kmod-usb-dwc3-qcom \ + -uboot-envtools ath10k-firmware-qca9887-ct \ + ath10k-firmware-qca9984-ct kmod-eeprom-at24 kmod-hwmon-ina2xx \ + kmod-leds-tlc591xx +endef +TARGET_DEVICES += meraki_mr52 + +define Device/nec_wg2600hp + $(call Device/LegacyImage) + DEVICE_VENDOR := NEC + DEVICE_MODEL := Aterm WG2600HP + SOC := qcom-ipq8064 + BLOCKSIZE := 64k + BOARD_NAME := wg2600hp + IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata + DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct +endef +TARGET_DEVICES += nec_wg2600hp + +define Device/nec_wg2600hp3 + $(call Device/LegacyImage) + DEVICE_VENDOR := NEC Platforms + DEVICE_MODEL := Aterm WG2600HP3 + SOC := qcom-ipq8062 + BLOCKSIZE := 64k + IMAGES := sysupgrade.bin + IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata + DEVICE_PACKAGES := -kmod-ata-ahci -kmod-ata-ahci-platform -kmod-usb-ohci -kmod-usb2 \ + -kmod-usb-ledtrig-usbport -kmod-usb-phy-qcom-dwc3 -kmod-usb3 -kmod-usb-dwc3-qcom \ + ath10k-firmware-qca9984-ct ipq-wifi-nec_wg2600hp3 +endef +TARGET_DEVICES += nec_wg2600hp3 + +define Device/netgear_d7800 + $(call Device/DniImage) + DEVICE_VENDOR := NETGEAR + DEVICE_MODEL := Nighthawk X4 D7800 + SOC := qcom-ipq8064 + KERNEL_SIZE := 4096k + NETGEAR_BOARD_ID := D7800 + NETGEAR_HW_ID := 29764958+0+128+512+4x4+4x4 + BLOCKSIZE := 128k + PAGESIZE := 2048 + BOARD_NAME := d7800 + SUPPORTED_DEVICES += d7800 + DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct +endef +TARGET_DEVICES += netgear_d7800 + +define Device/netgear_r7500 + $(call Device/DniImage) + DEVICE_VENDOR := NETGEAR + DEVICE_MODEL := Nighthawk X4 R7500 + DEVICE_VARIANT := v1 + SOC := qcom-ipq8064 + KERNEL_SIZE := 4096k + NETGEAR_BOARD_ID := R7500 + NETGEAR_HW_ID := 29764841+0+128+256+3x3+4x4 + BLOCKSIZE := 128k + PAGESIZE := 2048 + BOARD_NAME := r7500 + SUPPORTED_DEVICES += r7500 + DEVICE_PACKAGES := ath10k-firmware-qca988x-ct +endef +TARGET_DEVICES += netgear_r7500 + +define Device/netgear_r7500v2 + $(call Device/DniImage) + DEVICE_VENDOR := NETGEAR + DEVICE_MODEL := Nighthawk X4 R7500 + DEVICE_VARIANT := v2 + SOC := qcom-ipq8064 + KERNEL_SIZE := 4096k + NETGEAR_BOARD_ID := R7500v2 + NETGEAR_HW_ID := 29764958+0+128+512+3x3+4x4 + BLOCKSIZE := 128k + PAGESIZE := 2048 + BOARD_NAME := r7500v2 + SUPPORTED_DEVICES += r7500v2 + DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct ath10k-firmware-qca988x-ct +endef +TARGET_DEVICES += netgear_r7500v2 + +define Device/netgear_r7800 + $(call Device/DniImage) + DEVICE_VENDOR := NETGEAR + DEVICE_MODEL := Nighthawk X4S R7800 + SOC := qcom-ipq8065 + KERNEL_SIZE := 4096k + NETGEAR_BOARD_ID := R7800 + NETGEAR_HW_ID := 29764958+0+128+512+4x4+4x4+cascade + BLOCKSIZE := 128k + PAGESIZE := 2048 + BOARD_NAME := r7800 + SUPPORTED_DEVICES += r7800 + DEVICE_PACKAGES := ath10k-firmware-qca9984-ct +endef +TARGET_DEVICES += netgear_r7800 + +define Device/netgear_xr500 + $(call Device/DniImage) + DEVICE_VENDOR := NETGEAR + DEVICE_MODEL := Nighthawk XR500 + SOC := qcom-ipq8065 + KERNEL_SIZE := 4096k + NETGEAR_BOARD_ID := XR500 + NETGEAR_HW_ID := 29764958+0+256+512+4x4+4x4+cascade + BLOCKSIZE := 128k + PAGESIZE := 2048 + DEVICE_PACKAGES := ath10k-firmware-qca9984-ct +endef +TARGET_DEVICES += netgear_xr500 + +define Device/qcom_ipq8064-ap148 + $(call Device/FitImage) + $(call Device/UbiFit) + DEVICE_VENDOR := Qualcomm + DEVICE_MODEL := AP148 + DEVICE_VARIANT := standard + SOC := qcom-ipq8064 + DEVICE_DTS := qcom-ipq8064-ap148 + KERNEL_INSTALL := 1 + BLOCKSIZE := 128k + PAGESIZE := 2048 + BOARD_NAME := ap148 + SUPPORTED_DEVICES += ap148 + DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct +endef +TARGET_DEVICES += qcom_ipq8064-ap148 + +define Device/qcom_ipq8064-ap148-legacy + $(call Device/LegacyImage) + $(call Device/UbiFit) + DEVICE_VENDOR := Qualcomm + DEVICE_MODEL := AP148 + DEVICE_VARIANT := legacy + SOC := qcom-ipq8064 + DEVICE_DTS := qcom-ipq8064-ap148 + BLOCKSIZE := 128k + PAGESIZE := 2048 + BOARD_NAME := ap148 + SUPPORTED_DEVICES := qcom,ipq8064-ap148 ap148 + DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct +endef +TARGET_DEVICES += qcom_ipq8064-ap148-legacy + +define Device/qcom_ipq8064-ap161 + $(call Device/FitImage) + $(call Device/UbiFit) + DEVICE_VENDOR := Qualcomm + DEVICE_MODEL := AP161 + SOC := qcom-ipq8064 + DEVICE_DTS := qcom-ipq8064-ap161 + KERNEL_INSTALL := 1 + BLOCKSIZE := 128k + PAGESIZE := 2048 + BOARD_NAME := ap161 + DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct +endef +TARGET_DEVICES += qcom_ipq8064-ap161 + +define Device/qcom_ipq8064-db149 + $(call Device/FitImage) + DEVICE_VENDOR := Qualcomm + DEVICE_MODEL := DB149 + SOC := qcom-ipq8064 + DEVICE_DTS := qcom-ipq8064-db149 + KERNEL_INSTALL := 1 + BOARD_NAME := db149 + DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct +endef +TARGET_DEVICES += qcom_ipq8064-db149 + +define Device/tplink_ad7200 + $(call Device/TpSafeImage) + DEVICE_VENDOR := TP-Link + DEVICE_MODEL := AD7200 + DEVICE_VARIANT := v1/v2 + DEVICE_ALT0_VENDOR := TP-Link + DEVICE_ALT0_MODEL := Talon AD7200 + DEVICE_ALT0_VARIANT := v1/v2 + SOC := qcom-ipq8064 + BLOCKSIZE := 128k + PAGESIZE := 2048 + TPLINK_BOARD_ID := AD7200 + DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct kmod-wil6210 +endef +TARGET_DEVICES += tplink_ad7200 + +define Device/tplink_c2600 + $(call Device/TpSafeImage) + DEVICE_VENDOR := TP-Link + DEVICE_MODEL := Archer C2600 + DEVICE_VARIANT := v1 + SOC := qcom-ipq8064 + BLOCKSIZE := 128k + PAGESIZE := 2048 + BOARD_NAME := c2600 + SUPPORTED_DEVICES += c2600 + TPLINK_BOARD_ID := C2600 + DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct +endef +TARGET_DEVICES += tplink_c2600 + +define Device/tplink_vr2600v + DEVICE_VENDOR := TP-Link + DEVICE_MODEL := Archer VR2600v + DEVICE_VARIANT := v1 + KERNEL_SUFFIX := -uImage + KERNEL = kernel-bin | append-dtb | uImage none + KERNEL_NAME := zImage + KERNEL_SIZE := 3072k + SOC := qcom-ipq8064 + BLOCKSIZE := 128k + PAGESIZE := 2048 + BOARD_NAME := vr2600v + SUPPORTED_DEVICES += vr2600v + DEVICE_PACKAGES := ath10k-firmware-qca99x0-ct + IMAGE/sysupgrade.bin := pad-extra 512 | append-kernel | pad-to $$$$(KERNEL_SIZE) | append-rootfs | pad-rootfs | append-metadata +endef +TARGET_DEVICES += tplink_vr2600v + +define Device/ubnt_unifi-ac-hd + $(call Device/FitImageLzma) + DEVICE_VENDOR := Ubiquiti + DEVICE_MODEL := UniFi AC HD + SOC := qcom-ipq8064 + BLOCKSIZE := 64k + IMAGE_SIZE := 14784k + DEVICE_PACKAGES := ath10k-firmware-qca9984-ct + IMAGE/sysupgrade.bin := append-kernel | pad-to $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | check-size | append-metadata +endef +TARGET_DEVICES += ubnt_unifi-ac-hd + +define Device/zyxel_nbg6817 + DEVICE_VENDOR := ZyXEL + DEVICE_MODEL := NBG6817 + SOC := qcom-ipq8065 + KERNEL_SIZE := 4096k + BLOCKSIZE := 64k + BOARD_NAME := nbg6817 + RAS_BOARD := NBG6817 + RAS_ROOTFS_SIZE := 20934k + RAS_VERSION := "V1.99(OWRT.9999)C0" + SUPPORTED_DEVICES += nbg6817 + DEVICE_PACKAGES := ath10k-firmware-qca9984-ct e2fsprogs kmod-fs-ext4 losetup + $(call Device/ZyXELImage) +endef +TARGET_DEVICES += zyxel_nbg6817 + +$(eval $(call BuildImage)) diff --git a/root/target/linux/ipq806x/modules.mk b/root/target/linux/ipq806x/modules.mk new file mode 100755 index 00000000..605504b0 --- /dev/null +++ b/root/target/linux/ipq806x/modules.mk @@ -0,0 +1,16 @@ +define KernelPackage/phy-qcom-ipq806x-usb + TITLE:=Qualcomm IPQ806x DWC3 USB PHY driver + DEPENDS:=@TARGET_ipq806x + KCONFIG:= CONFIG_PHY_QCOM_IPQ806X_USB + FILES:= \ + $(LINUX_DIR)/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.ko + AUTOLOAD:=$(call AutoLoad,45,phy-qcom-ipq806x-usb,1) + $(call AddDepends/usb) +endef + +define KernelPackage/phy-qcom-ipq806x-usb/description + This driver provides support for the integrated DesignWare + USB3 IP Core within the QCOM SoCs. +endef + +$(eval $(call KernelPackage,phy-qcom-ipq806x-usb)) diff --git a/root/target/linux/ipq806x/patches-5.15/0001-dtbindings-qcom_adm-Fix-channel-specifiers.patch b/root/target/linux/ipq806x/patches-5.10/0001-dtbindings-qcom_adm-Fix-channel-specifiers.patch similarity index 100% rename from root/target/linux/ipq806x/patches-5.15/0001-dtbindings-qcom_adm-Fix-channel-specifiers.patch rename to root/target/linux/ipq806x/patches-5.10/0001-dtbindings-qcom_adm-Fix-channel-specifiers.patch diff --git a/root/target/linux/ipq806x/patches-5.15/0033-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch b/root/target/linux/ipq806x/patches-5.10/0033-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch similarity index 100% rename from root/target/linux/ipq806x/patches-5.15/0033-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch rename to root/target/linux/ipq806x/patches-5.10/0033-ARM-qcom-automatically-select-PCI_DOMAINS-if-PCI-is-.patch diff --git a/root/target/linux/ipq806x/patches-5.15/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch b/root/target/linux/ipq806x/patches-5.10/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch similarity index 97% rename from root/target/linux/ipq806x/patches-5.15/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch rename to root/target/linux/ipq806x/patches-5.10/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch index b56480de..b73218e7 100755 --- a/root/target/linux/ipq806x/patches-5.15/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch +++ b/root/target/linux/ipq806x/patches-5.10/0060-HACK-arch-arm-force-ZRELADDR-on-arch-qcom.patch @@ -33,7 +33,7 @@ Signed-off-by: Mathieu Olivari --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig -@@ -321,7 +321,7 @@ config ARCH_MULTIPLATFORM +@@ -322,7 +322,7 @@ config ARCH_MULTIPLATFORM select ARCH_SELECT_MEMORY_MODEL select ARM_HAS_SG_CHAIN select ARM_PATCH_PHYS_VIRT diff --git a/root/target/linux/ipq806x/patches-5.10/0065-arm-override-compiler-flags.patch b/root/target/linux/ipq806x/patches-5.10/0065-arm-override-compiler-flags.patch new file mode 100755 index 00000000..a1a0371f --- /dev/null +++ b/root/target/linux/ipq806x/patches-5.10/0065-arm-override-compiler-flags.patch @@ -0,0 +1,21 @@ +From 4d8e29642661397a339ac3485f212c6360445421 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Thu, 9 Mar 2017 09:33:32 +0100 +Subject: [PATCH 65/69] arm: override compiler flags + +Signed-off-by: John Crispin +--- + arch/arm/Makefile | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm/Makefile ++++ b/arch/arm/Makefile +@@ -61,7 +61,7 @@ KBUILD_CFLAGS += $(call cc-option,-fno-i + # macro, but instead defines a whole series of macros which makes + # testing for a specific architecture or later rather impossible. + arch-$(CONFIG_CPU_32v7M) =-D__LINUX_ARM_ARCH__=7 -march=armv7-m +-arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 -march=armv7-a ++arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 -mcpu=cortex-a15 + arch-$(CONFIG_CPU_32v6) =-D__LINUX_ARM_ARCH__=6 -march=armv6 + # Only override the compiler option if ARMv6. The ARMv6K extensions are + # always available in ARMv7 diff --git a/root/target/linux/ipq806x/patches-5.15/0067-generic-Mangle-bootloader-s-kernel-arguments.patch b/root/target/linux/ipq806x/patches-5.10/0067-generic-Mangle-bootloader-s-kernel-arguments.patch similarity index 97% rename from root/target/linux/ipq806x/patches-5.15/0067-generic-Mangle-bootloader-s-kernel-arguments.patch rename to root/target/linux/ipq806x/patches-5.10/0067-generic-Mangle-bootloader-s-kernel-arguments.patch index c38e0a46..8f669319 100755 --- a/root/target/linux/ipq806x/patches-5.15/0067-generic-Mangle-bootloader-s-kernel-arguments.patch +++ b/root/target/linux/ipq806x/patches-5.10/0067-generic-Mangle-bootloader-s-kernel-arguments.patch @@ -22,7 +22,7 @@ Signed-off-by: Adrian Panella --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig -@@ -1780,6 +1780,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN +@@ -1781,6 +1781,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN The command-line arguments provided by the boot loader will be appended to the the device tree bootargs property. @@ -189,7 +189,7 @@ Signed-off-by: Adrian Panella static int kernel_init(void *); extern void init_IRQ(void); -@@ -905,6 +909,18 @@ asmlinkage __visible void __init __no_sa +@@ -906,6 +910,18 @@ asmlinkage __visible void __init __no_sa pr_notice("Kernel command line: %s\n", saved_command_line); /* parameters may set static keys */ jump_label_init(); diff --git a/root/target/linux/ipq806x/patches-5.15/0069-arm-boot-add-dts-files.patch b/root/target/linux/ipq806x/patches-5.10/0069-arm-boot-add-dts-files.patch similarity index 89% rename from root/target/linux/ipq806x/patches-5.15/0069-arm-boot-add-dts-files.patch rename to root/target/linux/ipq806x/patches-5.10/0069-arm-boot-add-dts-files.patch index d057c0dc..49ff2180 100755 --- a/root/target/linux/ipq806x/patches-5.15/0069-arm-boot-add-dts-files.patch +++ b/root/target/linux/ipq806x/patches-5.10/0069-arm-boot-add-dts-files.patch @@ -10,7 +10,7 @@ Signed-off-by: John Crispin --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile -@@ -907,9 +907,27 @@ dtb-$(CONFIG_ARCH_QCOM) += \ +@@ -907,8 +907,29 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-ipq4019-ap.dk04.1-c3.dtb \ qcom-ipq4019-ap.dk07.1-c1.dtb \ qcom-ipq4019-ap.dk07.1-c2.dtb \ @@ -33,8 +33,10 @@ Signed-off-by: John Crispin + qcom-ipq8065-nbg6817.dtb \ + qcom-ipq8065-r7800.dtb \ + qcom-ipq8065-rt4230w-rev6.dtb \ ++ qcom-ipq8065-xr500.dtb \ + qcom-ipq8068-ecw5410.dtb \ - qcom-msm8226-samsung-s3ve3g.dtb \ ++ qcom-ipq8068-mr42.dtb \ ++ qcom-ipq8068-mr52.dtb \ qcom-msm8660-surf.dtb \ qcom-msm8960-cdp.dtb \ qcom-msm8974-fairphone-fp2.dtb \ diff --git a/root/target/linux/ipq806x/patches-5.10/0072-add-ipq806x-with-no-clocks.patch b/root/target/linux/ipq806x/patches-5.10/0072-add-ipq806x-with-no-clocks.patch new file mode 100755 index 00000000..62bba1d7 --- /dev/null +++ b/root/target/linux/ipq806x/patches-5.10/0072-add-ipq806x-with-no-clocks.patch @@ -0,0 +1,10 @@ +--- a/drivers/firmware/qcom_scm.c ++++ b/drivers/firmware/qcom_scm.c +@@ -1275,6 +1275,7 @@ static const struct of_device_id qcom_sc + SCM_HAS_BUS_CLK) + }, + { .compatible = "qcom,scm-ipq4019" }, ++ { .compatible = "qcom,scm-ipq806x" }, + { .compatible = "qcom,scm-msm8660", .data = (void *) SCM_HAS_CORE_CLK }, + { .compatible = "qcom,scm-msm8960", .data = (void *) SCM_HAS_CORE_CLK }, + { .compatible = "qcom,scm-msm8916", .data = (void *)(SCM_HAS_CORE_CLK | diff --git a/root/target/linux/ipq806x/patches-5.10/082-ipq8064-dtsi-tweaks.patch b/root/target/linux/ipq806x/patches-5.10/082-ipq8064-dtsi-tweaks.patch new file mode 100755 index 00000000..d6a45937 --- /dev/null +++ b/root/target/linux/ipq806x/patches-5.10/082-ipq8064-dtsi-tweaks.patch @@ -0,0 +1,220 @@ +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -20,7 +20,7 @@ + #address-cells = <1>; + #size-cells = <0>; + +- cpu@0 { ++ cpu0: cpu@0 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; + device_type = "cpu"; +@@ -30,7 +30,7 @@ + qcom,saw = <&saw0>; + }; + +- cpu@1 { ++ cpu1: cpu@1 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; + device_type = "cpu"; +@@ -67,7 +67,7 @@ + no-map; + }; + +- smem@41000000 { ++ smem: smem@41000000 { + reg = <0x41000000 0x200000>; + no-map; + }; +@@ -128,6 +128,7 @@ + gpio-ranges = <&qcom_pinmux 0 0 69>; + #gpio-cells = <2>; + interrupt-controller; ++ #address-cells = <0>; + #interrupt-cells = <2>; + interrupts = ; + +@@ -155,6 +156,7 @@ + function = "pcie3_rst"; + drive-strength = <12>; + bias-disable; ++ output-low; + }; + }; + +@@ -190,6 +192,7 @@ + intc: interrupt-controller@2000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; ++ #address-cells = <0>; + #interrupt-cells = <3>; + reg = <0x02000000 0x1000>, + <0x02002000 0x1000>; +@@ -219,21 +222,23 @@ + acc0: clock-controller@2088000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02088000 0x1000>, <0x02008000 0x1000>; ++ clock-output-names = "acpu0_aux"; + }; + + acc1: clock-controller@2098000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02098000 0x1000>, <0x02008000 0x1000>; ++ clock-output-names = "acpu1_aux"; + }; + + saw0: regulator@2089000 { +- compatible = "qcom,saw2"; ++ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + + saw1: regulator@2099000 { +- compatible = "qcom,saw2"; ++ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon"; + reg = <0x02099000 0x1000>, <0x02009000 0x1000>; + regulator; + }; +@@ -251,7 +256,7 @@ + + syscon-tcsr = <&tcsr>; + +- serial@12490000 { ++ gsbi2_serial: serial@12490000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x12490000 0x1000>, + <0x12480000 0x1000>; +@@ -261,7 +266,7 @@ + status = "disabled"; + }; + +- i2c@124a0000 { ++ gsbi2_i2c: i2c@124a0000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x124a0000 0x1000>; + interrupts = ; +@@ -326,7 +331,7 @@ + + syscon-tcsr = <&tcsr>; + +- serial@1a240000 { ++ gsbi5_serial: serial@1a240000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x1a240000 0x1000>, + <0x1a200000 0x1000>; +@@ -397,7 +402,7 @@ + status = "disabled"; + }; + +- sata@29000000 { ++ sata: sata@29000000 { + compatible = "qcom,ipq806x-ahci", "generic-ahci"; + reg = <0x29000000 0x180>; + +@@ -430,13 +435,35 @@ + reg = <0x00700000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; ++ ++ tsens_calib: calib@400 { ++ reg = <0x400 0xb>; ++ }; ++ tsens_backup: backup@410 { ++ reg = <0x410 0xb>; ++ }; ++ speedbin_efuse: speedbin@0c0 { ++ reg = <0x0c0 0x4>; ++ }; + }; + + gcc: clock-controller@900000 { +- compatible = "qcom,gcc-ipq8064"; ++ compatible = "qcom,gcc-ipq8064", "syscon"; + reg = <0x00900000 0x4000>; + #clock-cells = <1>; + #reset-cells = <1>; ++ #power-domain-cells = <1>; ++ ++ tsens: thermal-sensor@900000 { ++ compatible = "qcom,ipq8064-tsens"; ++ ++ nvmem-cells = <&tsens_calib>, <&tsens_backup>; ++ nvmem-cell-names = "calib", "calib_backup"; ++ interrupts = ; ++ interrupt-names = "uplow"; ++ #thermal-sensor-cells = <1>; ++ #qcom,sensors = <11>; ++ }; + }; + + tcsr: syscon@1a400000 { +@@ -622,7 +649,7 @@ + + gmac0: ethernet@37000000 { + device_type = "network"; +- compatible = "qcom,ipq806x-gmac"; ++ compatible = "qcom,ipq806x-gmac", "snps,dwmac"; + reg = <0x37000000 0x200000>; + interrupts = ; + interrupt-names = "macirq"; +@@ -645,7 +672,7 @@ + + gmac1: ethernet@37200000 { + device_type = "network"; +- compatible = "qcom,ipq806x-gmac"; ++ compatible = "qcom,ipq806x-gmac", "snps,dwmac"; + reg = <0x37200000 0x200000>; + interrupts = ; + interrupt-names = "macirq"; +@@ -668,7 +695,7 @@ + + gmac2: ethernet@37400000 { + device_type = "network"; +- compatible = "qcom,ipq806x-gmac"; ++ compatible = "qcom,ipq806x-gmac", "snps,dwmac"; + reg = <0x37400000 0x200000>; + interrupts = ; + interrupt-names = "macirq"; +@@ -691,7 +718,7 @@ + + gmac3: ethernet@37600000 { + device_type = "network"; +- compatible = "qcom,ipq806x-gmac"; ++ compatible = "qcom,ipq806x-gmac", "snps,dwmac"; + reg = <0x37600000 0x200000>; + interrupts = ; + interrupt-names = "macirq"; +@@ -740,13 +767,13 @@ + qcom,ee = <0>; + }; + +- amba { +- compatible = "simple-bus"; ++ amba: amba { ++ compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + +- sdcc@12400000 { ++ sdcc1: sdcc@12400000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; +@@ -760,13 +787,12 @@ + non-removable; + cap-sd-highspeed; + cap-mmc-highspeed; +- mmc-ddr-1_8v; + vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; + dma-names = "tx", "rx"; + }; + +- sdcc@12180000 { ++ sdcc3: sdcc@12180000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; diff --git a/root/target/linux/ipq806x/patches-5.10/083-ipq8064-dtsi-additions.patch b/root/target/linux/ipq806x/patches-5.10/083-ipq8064-dtsi-additions.patch new file mode 100755 index 00000000..2667bd63 --- /dev/null +++ b/root/target/linux/ipq806x/patches-5.10/083-ipq8064-dtsi-additions.patch @@ -0,0 +1,846 @@ +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -8,6 +8,8 @@ + #include + #include + #include ++#include ++#include + + / { + #address-cells = <1>; +@@ -28,6 +30,16 @@ + next-level-cache = <&L2>; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; ++ clocks = <&kraitcc 0>, <&kraitcc 4>; ++ clock-names = "cpu", "l2"; ++ clock-latency = <100000>; ++ cpu-supply = <&smb208_s2a>; ++ operating-points-v2 = <&opp_table0>; ++ voltage-tolerance = <5>; ++ cooling-min-state = <0>; ++ cooling-max-state = <10>; ++ #cooling-cells = <2>; ++ cpu-idle-states = <&CPU_SPC>; + }; + + cpu1: cpu@1 { +@@ -38,14 +50,350 @@ + next-level-cache = <&L2>; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; ++ clocks = <&kraitcc 1>, <&kraitcc 4>; ++ clock-names = "cpu", "l2"; ++ clock-latency = <100000>; ++ cpu-supply = <&smb208_s2b>; ++ operating-points-v2 = <&opp_table0>; ++ voltage-tolerance = <5>; ++ cooling-min-state = <0>; ++ cooling-max-state = <10>; ++ #cooling-cells = <2>; ++ cpu-idle-states = <&CPU_SPC>; ++ }; ++ ++ idle-states { ++ CPU_SPC: spc { ++ compatible = "qcom,idle-state-spc"; ++ status = "disabled"; ++ entry-latency-us = <400>; ++ exit-latency-us = <900>; ++ min-residency-us = <3000>; ++ }; + }; ++ }; + +- L2: l2-cache { +- compatible = "cache"; +- cache-level = <2>; ++ opp_table_l2: opp_table_l2 { ++ compatible = "operating-points-v2"; ++ ++ opp-384000000 { ++ opp-hz = /bits/ 64 <384000000>; ++ opp-microvolt = <1100000>; ++ clock-latency-ns = <100000>; ++ opp-level = <0>; ++ }; ++ ++ opp-1000000000 { ++ opp-hz = /bits/ 64 <1000000000>; ++ opp-microvolt = <1100000>; ++ clock-latency-ns = <100000>; ++ opp-level = <1>; ++ }; ++ ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <1150000>; ++ clock-latency-ns = <100000>; ++ opp-level = <2>; ++ }; ++ }; ++ ++ opp_table0: opp_table0 { ++ compatible = "operating-points-v2-kryo-cpu"; ++ nvmem-cells = <&speedbin_efuse>; ++ ++ /* ++ * Voltage thresholds are ++ */ ++ opp-384000000 { ++ opp-hz = /bits/ 64 <384000000>; ++ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>; ++ opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>; ++ opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>; ++ opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>; ++ opp-supported-hw = <0x1>; ++ clock-latency-ns = <100000>; ++ opp-level = <0>; ++ }; ++ ++ opp-600000000 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>; ++ opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>; ++ opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>; ++ opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>; ++ opp-supported-hw = <0x1>; ++ clock-latency-ns = <100000>; ++ opp-level = <1>; ++ }; ++ ++ opp-800000000 { ++ opp-hz = /bits/ 64 <800000000>; ++ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>; ++ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>; ++ opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>; ++ opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>; ++ opp-supported-hw = <0x1>; ++ clock-latency-ns = <100000>; ++ opp-level = <1>; ++ }; ++ ++ opp-1000000000 { ++ opp-hz = /bits/ 64 <1000000000>; ++ opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>; ++ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>; ++ opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>; ++ opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>; ++ opp-supported-hw = <0x1>; ++ clock-latency-ns = <100000>; ++ opp-level = <1>; ++ }; ++ ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>; ++ opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>; ++ opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>; ++ opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>; ++ opp-supported-hw = <0x1>; ++ clock-latency-ns = <100000>; ++ opp-level = <2>; ++ }; ++ ++ opp-1400000000 { ++ opp-hz = /bits/ 64 <1400000000>; ++ opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>; ++ opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>; ++ opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>; ++ opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>; ++ opp-supported-hw = <0x1>; ++ clock-latency-ns = <100000>; ++ opp-level = <2>; + }; + }; + ++ thermal-zones { ++ tsens_tz_sensor0 { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsens 0>; ++ ++ trips { ++ cpu-critical { ++ temperature = <105000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ ++ cpu-hot { ++ temperature = <95000>; ++ hysteresis = <2000>; ++ type = "hot"; ++ }; ++ }; ++ }; ++ ++ tsens_tz_sensor1 { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsens 1>; ++ ++ trips { ++ cpu-critical { ++ temperature = <105000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ ++ cpu-hot { ++ temperature = <95000>; ++ hysteresis = <2000>; ++ type = "hot"; ++ }; ++ }; ++ }; ++ ++ tsens_tz_sensor2 { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsens 2>; ++ ++ trips { ++ cpu-critical { ++ temperature = <105000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ ++ cpu-hot { ++ temperature = <95000>; ++ hysteresis = <2000>; ++ type = "hot"; ++ }; ++ }; ++ }; ++ ++ tsens_tz_sensor3 { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsens 3>; ++ ++ trips { ++ cpu-critical { ++ temperature = <105000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ ++ cpu-hot { ++ temperature = <95000>; ++ hysteresis = <2000>; ++ type = "hot"; ++ }; ++ }; ++ }; ++ ++ tsens_tz_sensor4 { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsens 4>; ++ ++ trips { ++ cpu-critical { ++ temperature = <105000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ ++ cpu-hot { ++ temperature = <95000>; ++ hysteresis = <2000>; ++ type = "hot"; ++ }; ++ }; ++ }; ++ ++ tsens_tz_sensor5 { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsens 5>; ++ ++ trips { ++ cpu-critical { ++ temperature = <105000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ ++ cpu-hot { ++ temperature = <95000>; ++ hysteresis = <2000>; ++ type = "hot"; ++ }; ++ }; ++ }; ++ ++ tsens_tz_sensor6 { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsens 6>; ++ ++ trips { ++ cpu-critical { ++ temperature = <105000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ ++ cpu-hot { ++ temperature = <95000>; ++ hysteresis = <2000>; ++ type = "hot"; ++ }; ++ }; ++ }; ++ ++ tsens_tz_sensor7 { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsens 7>; ++ ++ trips { ++ cpu-critical { ++ temperature = <105000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ ++ cpu-hot { ++ temperature = <95000>; ++ hysteresis = <2000>; ++ type = "hot"; ++ }; ++ }; ++ }; ++ ++ tsens_tz_sensor8 { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsens 8>; ++ ++ trips { ++ cpu-critical { ++ temperature = <105000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ ++ cpu-hot { ++ temperature = <95000>; ++ hysteresis = <2000>; ++ type = "hot"; ++ }; ++ }; ++ }; ++ ++ tsens_tz_sensor9 { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsens 9>; ++ ++ trips { ++ cpu-critical { ++ temperature = <105000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ ++ cpu-hot { ++ temperature = <95000>; ++ hysteresis = <2000>; ++ type = "hot"; ++ }; ++ }; ++ }; ++ ++ tsens_tz_sensor10 { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&tsens 10>; ++ ++ trips { ++ cpu-critical { ++ temperature = <105000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ ++ cpu-hot { ++ temperature = <95000>; ++ hysteresis = <2000>; ++ type = "hot"; ++ }; ++ }; ++ }; ++ }; ++ + memory { + device_type = "memory"; + reg = <0x0 0x0>; +@@ -93,6 +441,15 @@ + }; + }; + ++ fab-scaling { ++ compatible = "qcom,fab-scaling"; ++ clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>; ++ clock-names = "apps-fab-clk", "ddr-fab-clk"; ++ fab_freq_high = <533000000>; ++ fab_freq_nominal = <400000000>; ++ cpu_freq_threshold = <1000000000>; ++ }; ++ + firmware { + scm { + compatible = "qcom,scm-ipq806x", "qcom,scm"; +@@ -120,6 +477,78 @@ + reg-names = "lpass-lpaif"; + }; + ++ L2: l2-cache { ++ compatible = "qcom,krait-cache", "cache"; ++ cache-level = <2>; ++ qcom,saw = <&saw_l2>; ++ ++ clocks = <&kraitcc 4>; ++ clock-names = "l2"; ++ l2-supply = <&smb208_s1a>; ++ operating-points-v2 = <&opp_table_l2>; ++ }; ++ ++ rpm: rpm@108000 { ++ compatible = "qcom,rpm-ipq8064"; ++ reg = <0x108000 0x1000>; ++ qcom,ipc = <&l2cc 0x8 2>; ++ ++ interrupts = , ++ , ++ ; ++ interrupt-names = "ack", "err", "wakeup"; ++ ++ clocks = <&gcc RPM_MSG_RAM_H_CLK>; ++ clock-names = "ram"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ rpmcc: clock-controller { ++ compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; ++ #clock-cells = <1>; ++ }; ++ ++ regulators { ++ compatible = "qcom,rpm-smb208-regulators"; ++ ++ smb208_s1a: s1a { ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1150000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ ++ smb208_s1b: s1b { ++ regulator-min-microvolt = <1050000>; ++ regulator-max-microvolt = <1150000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ ++ smb208_s2a: s2a { ++ regulator-min-microvolt = < 800000>; ++ regulator-max-microvolt = <1250000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ ++ smb208_s2b: s2b { ++ regulator-min-microvolt = < 800000>; ++ regulator-max-microvolt = <1250000>; ++ ++ qcom,switch-mode-frequency = <1200000>; ++ }; ++ }; ++ }; ++ ++ rng@1a500000 { ++ compatible = "qcom,prng"; ++ reg = <0x1a500000 0x200>; ++ clocks = <&gcc PRNG_CLK>; ++ clock-names = "core"; ++ }; ++ + qcom_pinmux: pinmux@800000 { + compatible = "qcom,ipq8064-pinctrl"; + reg = <0x800000 0x4000>; +@@ -160,6 +589,15 @@ + }; + }; + ++ i2c4_pins: i2c4_pinmux { ++ mux { ++ pins = "gpio12", "gpio13"; ++ function = "gsbi4"; ++ drive-strength = <12>; ++ bias-disable; ++ }; ++ }; ++ + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; +@@ -169,6 +607,53 @@ + }; + }; + ++ nand_pins: nand_pins { ++ disable { ++ pins = "gpio34", "gpio35", "gpio36", ++ "gpio37", "gpio38"; ++ function = "nand"; ++ drive-strength = <10>; ++ bias-disable; ++ }; ++ ++ pullups { ++ pins = "gpio39"; ++ function = "nand"; ++ drive-strength = <10>; ++ bias-pull-up; ++ }; ++ ++ hold { ++ pins = "gpio40", "gpio41", "gpio42", ++ "gpio43", "gpio44", "gpio45", ++ "gpio46", "gpio47"; ++ function = "nand"; ++ drive-strength = <10>; ++ bias-bus-hold; ++ }; ++ }; ++ ++ mdio0_pins: mdio0_pins { ++ mux { ++ pins = "gpio0", "gpio1"; ++ function = "mdio"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ }; ++ ++ rgmii2_pins: rgmii2_pins { ++ mux { ++ pins = "gpio27", "gpio28", "gpio29", ++ "gpio30", "gpio31", "gpio32", ++ "gpio51", "gpio52", "gpio59", ++ "gpio60", "gpio61", "gpio62"; ++ function = "rgmii2"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ }; ++ + leds_pins: leds_pins { + mux { + pins = "gpio7", "gpio8", "gpio9", +@@ -231,6 +716,17 @@ + clock-output-names = "acpu1_aux"; + }; + ++ l2cc: clock-controller@2011000 { ++ compatible = "qcom,kpss-gcc", "syscon"; ++ reg = <0x2011000 0x1000>; ++ clock-output-names = "acpu_l2_aux"; ++ }; ++ ++ kraitcc: clock-controller { ++ compatible = "qcom,krait-cc-v1"; ++ #clock-cells = <1>; ++ }; ++ + saw0: regulator@2089000 { + compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; +@@ -243,6 +739,52 @@ + regulator; + }; + ++ saw_l2: regulator@02012000 { ++ compatible = "qcom,saw2", "syscon"; ++ reg = <0x02012000 0x1000>; ++ regulator; ++ }; ++ ++ sic_non_secure: sic-non-secure@12100000 { ++ compatible = "syscon"; ++ reg = <0x12100000 0x10000>; ++ }; ++ ++ gsbi1: gsbi@12440000 { ++ compatible = "qcom,gsbi-v1.0.0"; ++ cell-index = <1>; ++ reg = <0x12440000 0x100>; ++ clocks = <&gcc GSBI1_H_CLK>; ++ clock-names = "iface"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ status = "disabled"; ++ ++ syscon-tcsr = <&tcsr>; ++ ++ gsbi1_serial: serial@12450000 { ++ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; ++ reg = <0x12450000 0x100>, ++ <0x12400000 0x03>; ++ interrupts = ; ++ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; ++ clock-names = "core", "iface"; ++ status = "disabled"; ++ }; ++ ++ gsbi1_i2c: i2c@12460000 { ++ compatible = "qcom,i2c-qup-v1.1.1"; ++ reg = <0x12460000 0x1000>; ++ interrupts = ; ++ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; ++ clock-names = "core", "iface"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ }; ++ + gsbi2: gsbi@12480000 { + compatible = "qcom,gsbi-v1.0.0"; + cell-index = <2>; +@@ -368,6 +910,33 @@ + }; + }; + ++ gsbi6: gsbi@16500000 { ++ status = "disabled"; ++ compatible = "qcom,gsbi-v1.0.0"; ++ cell-index = <6>; ++ reg = <0x16500000 0x100>; ++ clocks = <&gcc GSBI6_H_CLK>; ++ clock-names = "iface"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ syscon-tcsr = <&tcsr>; ++ ++ gsbi6_i2c: i2c@16580000 { ++ compatible = "qcom,i2c-qup-v1.1.1"; ++ reg = <0x16580000 0x1000>; ++ interrupts = ; ++ ++ clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; ++ clock-names = "core", "iface"; ++ status = "disabled"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ }; ++ + gsbi7: gsbi@16600000 { + status = "disabled"; + compatible = "qcom,gsbi-v1.0.0"; +@@ -389,6 +958,19 @@ + clock-names = "core", "iface"; + status = "disabled"; + }; ++ ++ gsbi7_i2c: i2c@16680000 { ++ compatible = "qcom,i2c-qup-v1.1.1"; ++ reg = <0x16680000 0x1000>; ++ interrupts = ; ++ ++ clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; ++ clock-names = "core", "iface"; ++ status = "disabled"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; + }; + + sata_phy: sata-phy@1b400000 { +@@ -478,6 +1060,95 @@ + #reset-cells = <1>; + }; + ++ sfpb_mutex_block: syscon@1200600 { ++ compatible = "syscon"; ++ reg = <0x01200600 0x100>; ++ }; ++ ++ hs_phy_0: hs_phy_0 { ++ compatible = "qcom,ipq806x-usb-phy-hs"; ++ reg = <0x110f8800 0x30>; ++ clocks = <&gcc USB30_0_UTMI_CLK>; ++ clock-names = "ref"; ++ #phy-cells = <0>; ++ }; ++ ++ ss_phy_0: ss_phy_0 { ++ compatible = "qcom,ipq806x-usb-phy-ss"; ++ reg = <0x110f8830 0x30>; ++ clocks = <&gcc USB30_0_MASTER_CLK>; ++ clock-names = "ref"; ++ #phy-cells = <0>; ++ }; ++ ++ usb3_0: usb3@110f8800 { ++ compatible = "qcom,dwc3", "syscon"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ reg = <0x110f8800 0x8000>; ++ clocks = <&gcc USB30_0_MASTER_CLK>; ++ clock-names = "core"; ++ ++ ranges; ++ ++ resets = <&gcc USB30_0_MASTER_RESET>; ++ reset-names = "master"; ++ ++ status = "disabled"; ++ ++ dwc3_0: dwc3@11000000 { ++ compatible = "snps,dwc3"; ++ reg = <0x11000000 0xcd00>; ++ interrupts = ; ++ phys = <&hs_phy_0>, <&ss_phy_0>; ++ phy-names = "usb2-phy", "usb3-phy"; ++ dr_mode = "host"; ++ snps,dis_u3_susphy_quirk; ++ }; ++ }; ++ ++ hs_phy_1: hs_phy_1 { ++ compatible = "qcom,ipq806x-usb-phy-hs"; ++ reg = <0x100f8800 0x30>; ++ clocks = <&gcc USB30_1_UTMI_CLK>; ++ clock-names = "ref"; ++ #phy-cells = <0>; ++ }; ++ ++ ss_phy_1: ss_phy_1 { ++ compatible = "qcom,ipq806x-usb-phy-ss"; ++ reg = <0x100f8830 0x30>; ++ clocks = <&gcc USB30_1_MASTER_CLK>; ++ clock-names = "ref"; ++ #phy-cells = <0>; ++ }; ++ ++ usb3_1: usb3@100f8800 { ++ compatible = "qcom,dwc3", "syscon"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ reg = <0x100f8800 0x8000>; ++ clocks = <&gcc USB30_1_MASTER_CLK>; ++ clock-names = "core"; ++ ++ ranges; ++ ++ resets = <&gcc USB30_1_MASTER_RESET>; ++ reset-names = "master"; ++ ++ status = "disabled"; ++ ++ dwc3_1: dwc3@10000000 { ++ compatible = "snps,dwc3"; ++ reg = <0x10000000 0xcd00>; ++ interrupts = ; ++ phys = <&hs_phy_1>, <&ss_phy_1>; ++ phy-names = "usb2-phy", "usb3-phy"; ++ dr_mode = "host"; ++ snps,dis_u3_susphy_quirk; ++ }; ++ }; ++ + pcie0: pci@1b500000 { + compatible = "qcom,pcie-ipq8064"; + reg = <0x1b500000 0x1000 +@@ -739,6 +1410,59 @@ + status = "disabled"; + }; + ++ adm_dma: dma@18300000 { ++ compatible = "qcom,adm"; ++ reg = <0x18300000 0x100000>; ++ interrupts = ; ++ #dma-cells = <1>; ++ ++ clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; ++ clock-names = "core", "iface"; ++ ++ resets = <&gcc ADM0_RESET>, ++ <&gcc ADM0_PBUS_RESET>, ++ <&gcc ADM0_C0_RESET>, ++ <&gcc ADM0_C1_RESET>, ++ <&gcc ADM0_C2_RESET>; ++ reset-names = "clk", "pbus", "c0", "c1", "c2"; ++ qcom,ee = <0>; ++ ++ status = "disabled"; ++ }; ++ ++ nand_controller: nand-controller@1ac00000 { ++ compatible = "qcom,ipq806x-nand"; ++ reg = <0x1ac00000 0x800>; ++ ++ clocks = <&gcc EBI2_CLK>, ++ <&gcc EBI2_AON_CLK>; ++ clock-names = "core", "aon"; ++ ++ dmas = <&adm_dma 3>; ++ dma-names = "rxtx"; ++ qcom,cmd-crci = <15>; ++ qcom,data-crci = <3>; ++ ++ status = "disabled"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ mdio0: mdio@37000000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ compatible = "qcom,ipq8064-mdio", "syscon"; ++ reg = <0x37000000 0x200000>; ++ resets = <&gcc GMAC_CORE1_RESET>; ++ reset-names = "stmmaceth"; ++ clocks = <&gcc GMAC_CORE1_CLK>; ++ clock-names = "stmmaceth"; ++ ++ status = "disabled"; ++ }; ++ + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; +@@ -814,4 +1538,17 @@ + }; + }; + }; ++ ++ sfpb_mutex: sfpb-mutex { ++ compatible = "qcom,sfpb-mutex"; ++ syscon = <&sfpb_mutex_block 4 4>; ++ ++ #hwlock-cells = <1>; ++ }; ++ ++ smem { ++ compatible = "qcom,smem"; ++ memory-region = <&smem>; ++ hwlocks = <&sfpb_mutex 3>; ++ }; + }; diff --git a/root/target/linux/ipq806x/patches-5.15/084-ipq8064-v1.0-dtsi-cleanup.patch b/root/target/linux/ipq806x/patches-5.10/084-ipq8064-v1.0-dtsi-cleanup.patch similarity index 100% rename from root/target/linux/ipq806x/patches-5.15/084-ipq8064-v1.0-dtsi-cleanup.patch rename to root/target/linux/ipq806x/patches-5.10/084-ipq8064-v1.0-dtsi-cleanup.patch diff --git a/root/target/linux/ipq806x/patches-5.15/085-ipq8064-v1.0-dtsi-additions.patch b/root/target/linux/ipq806x/patches-5.10/085-ipq8064-v1.0-dtsi-additions.patch similarity index 100% rename from root/target/linux/ipq806x/patches-5.15/085-ipq8064-v1.0-dtsi-additions.patch rename to root/target/linux/ipq806x/patches-5.10/085-ipq8064-v1.0-dtsi-additions.patch diff --git a/root/target/linux/ipq806x/patches-5.15/086-ipq8064-fix-duplicate-node.patch b/root/target/linux/ipq806x/patches-5.10/086-ipq8064-fix-duplicate-node.patch similarity index 98% rename from root/target/linux/ipq806x/patches-5.15/086-ipq8064-fix-duplicate-node.patch rename to root/target/linux/ipq806x/patches-5.10/086-ipq8064-fix-duplicate-node.patch index 8423fd13..747fa8c0 100755 --- a/root/target/linux/ipq806x/patches-5.15/086-ipq8064-fix-duplicate-node.patch +++ b/root/target/linux/ipq806x/patches-5.10/086-ipq8064-fix-duplicate-node.patch @@ -4,7 +4,7 @@ device_type = "memory"; }; -- mdio0: mdio@0 { +- mdio0: mdio-0 { - status = "okay"; - compatible = "virtual,mdio-gpio"; - gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>, @@ -71,7 +71,7 @@ - }; - }; - - mdio1: mdio@1 { + mdio1: mdio-1 { status = "okay"; compatible = "virtual,mdio-gpio"; @@ -216,6 +149,68 @@ diff --git a/root/target/linux/ipq806x/patches-5.15/093-drivers-cpufreq-qcom-cpufreq-nvmem-support-specific-.patch b/root/target/linux/ipq806x/patches-5.10/093-drivers-cpufreq-qcom-cpufreq-nvmem-support-specific-.patch similarity index 100% rename from root/target/linux/ipq806x/patches-5.15/093-drivers-cpufreq-qcom-cpufreq-nvmem-support-specific-.patch rename to root/target/linux/ipq806x/patches-5.10/093-drivers-cpufreq-qcom-cpufreq-nvmem-support-specific-.patch diff --git a/root/target/linux/ipq806x/patches-5.15/097-1-ipq806x-gcc-add-missing-clk-flag.patch b/root/target/linux/ipq806x/patches-5.10/097-1-ipq806x-gcc-add-missing-clk-flag.patch similarity index 83% rename from root/target/linux/ipq806x/patches-5.15/097-1-ipq806x-gcc-add-missing-clk-flag.patch rename to root/target/linux/ipq806x/patches-5.10/097-1-ipq806x-gcc-add-missing-clk-flag.patch index 3067ec77..3b4900fa 100755 --- a/root/target/linux/ipq806x/patches-5.15/097-1-ipq806x-gcc-add-missing-clk-flag.patch +++ b/root/target/linux/ipq806x/patches-5.10/097-1-ipq806x-gcc-add-missing-clk-flag.patch @@ -69,7 +69,7 @@ Signed-off-by: Ansuel Smith }, }, }; -@@ -1293,6 +1295,7 @@ static struct clk_rcg sdc1_src = { +@@ -1424,6 +1426,7 @@ static struct clk_rcg tsif_ref_src = { .parent_names = gcc_pxo_pll8, .num_parents = 2, .ops = &clk_rcg_ops, @@ -77,23 +77,7 @@ Signed-off-by: Ansuel Smith }, } }; -@@ -1341,6 +1344,7 @@ static struct clk_rcg sdc3_src = { - .parent_names = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, -+ .flags = CLK_SET_RATE_GATE, - }, - } - }; -@@ -1424,6 +1428,7 @@ static struct clk_rcg tsif_ref_src = { - .parent_names = gcc_pxo_pll8, - .num_parents = 2, - .ops = &clk_rcg_ops, -+ .flags = CLK_SET_RATE_GATE, - }, - } - }; -@@ -2694,7 +2699,8 @@ static struct clk_dyn_rcg ubi32_core1_sr +@@ -2694,7 +2697,8 @@ static struct clk_dyn_rcg ubi32_core1_sr .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, @@ -103,7 +87,7 @@ Signed-off-by: Ansuel Smith }, }, }; -@@ -2747,7 +2753,8 @@ static struct clk_dyn_rcg ubi32_core2_sr +@@ -2747,7 +2751,8 @@ static struct clk_dyn_rcg ubi32_core2_sr .parent_names = gcc_pxo_pll8_pll14_pll18_pll0, .num_parents = 5, .ops = &clk_dyn_rcg_ops, diff --git a/root/target/linux/ipq806x/patches-5.15/097-2-ipq806x-lcc-add-missing-reset.patch b/root/target/linux/ipq806x/patches-5.10/097-2-ipq806x-lcc-add-missing-reset.patch similarity index 100% rename from root/target/linux/ipq806x/patches-5.15/097-2-ipq806x-lcc-add-missing-reset.patch rename to root/target/linux/ipq806x/patches-5.10/097-2-ipq806x-lcc-add-missing-reset.patch diff --git a/root/target/linux/ipq806x/patches-5.15/097-3-clk-qcom-krait-add-missing-enable-disable.patch b/root/target/linux/ipq806x/patches-5.10/097-3-clk-qcom-krait-add-missing-enable-disable.patch similarity index 100% rename from root/target/linux/ipq806x/patches-5.15/097-3-clk-qcom-krait-add-missing-enable-disable.patch rename to root/target/linux/ipq806x/patches-5.10/097-3-clk-qcom-krait-add-missing-enable-disable.patch diff --git a/root/target/linux/ipq806x/patches-5.15/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch b/root/target/linux/ipq806x/patches-5.10/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch similarity index 96% rename from root/target/linux/ipq806x/patches-5.15/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch rename to root/target/linux/ipq806x/patches-5.10/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch index f8f4924d..d1e047ca 100755 --- a/root/target/linux/ipq806x/patches-5.15/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch +++ b/root/target/linux/ipq806x/patches-5.10/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch @@ -107,7 +107,7 @@ Signed-off-by: Ansuel Smith { 64000000, P_PLL8, 3, 1, 2 }, { 96000000, P_PLL8, 4, 0, 0 }, { 192000000, P_PLL8, 2, 0, 0 }, -@@ -2647,7 +2703,9 @@ static const struct freq_tbl clk_tbl_nss +@@ -2645,7 +2701,9 @@ static const struct freq_tbl clk_tbl_nss { 110000000, P_PLL18, 1, 1, 5 }, { 275000000, P_PLL18, 2, 0, 0 }, { 550000000, P_PLL18, 1, 0, 0 }, @@ -117,7 +117,7 @@ Signed-off-by: Ansuel Smith { } }; -@@ -2759,6 +2817,186 @@ static struct clk_dyn_rcg ubi32_core2_sr +@@ -2757,6 +2815,186 @@ static struct clk_dyn_rcg ubi32_core2_sr }, }; @@ -304,7 +304,7 @@ Signed-off-by: Ansuel Smith static struct clk_regmap *gcc_ipq806x_clks[] = { [PLL0] = &pll0.clkr, [PLL0_VOTE] = &pll0_vote, -@@ -2766,6 +3004,7 @@ static struct clk_regmap *gcc_ipq806x_cl +@@ -2764,6 +3002,7 @@ static struct clk_regmap *gcc_ipq806x_cl [PLL4_VOTE] = &pll4_vote, [PLL8] = &pll8.clkr, [PLL8_VOTE] = &pll8_vote, @@ -312,7 +312,7 @@ Signed-off-by: Ansuel Smith [PLL14] = &pll14.clkr, [PLL14_VOTE] = &pll14_vote, [PLL18] = &pll18.clkr, -@@ -2880,6 +3119,12 @@ static struct clk_regmap *gcc_ipq806x_cl +@@ -2878,6 +3117,12 @@ static struct clk_regmap *gcc_ipq806x_cl [PLL9] = &hfpll0.clkr, [PLL10] = &hfpll1.clkr, [PLL12] = &hfpll_l2.clkr, @@ -325,7 +325,7 @@ Signed-off-by: Ansuel Smith }; static const struct qcom_reset_map gcc_ipq806x_resets[] = { -@@ -3011,6 +3256,11 @@ static const struct qcom_reset_map gcc_i +@@ -3009,6 +3254,11 @@ static const struct qcom_reset_map gcc_i [GMAC_CORE3_RESET] = { 0x3cfc, 0 }, [GMAC_CORE4_RESET] = { 0x3d1c, 0 }, [GMAC_AHB_RESET] = { 0x3e24, 0 }, diff --git a/root/target/linux/ipq806x/patches-5.10/098-1-cpufreq-add-Krait-dedicated-scaling-driver.patch b/root/target/linux/ipq806x/patches-5.10/098-1-cpufreq-add-Krait-dedicated-scaling-driver.patch new file mode 100755 index 00000000..76968622 --- /dev/null +++ b/root/target/linux/ipq806x/patches-5.10/098-1-cpufreq-add-Krait-dedicated-scaling-driver.patch @@ -0,0 +1,681 @@ +From cc41a266280cad0b55319e614167c88dff344248 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Sat, 22 Feb 2020 16:33:10 +0100 +Subject: [PATCH 1/8] cpufreq: add Krait dedicated scaling driver + +This new driver is based on generic cpufreq-dt driver. +Krait SoCs have 2-4 cpu and one shared L2 cache that can +operate at different frequency based on the maximum cpu clk +across all core. +L2 frequency and voltage are scaled on every frequency change +if needed. On Krait SoCs is present a bug that can cause +transition problem between frequency bin, to workaround this +on more than one transition, the L2 frequency is first set to the +base rate and then to the target rate. +The L2 frequency use the OPP framework and use the opp-level +bindings to link the l2 freq to different cpu freq. This is needed +as the Krait l2 clk are note mapped 1:1 to the core clks and some +of the l2 clk is set based on a range of the cpu clks. If the driver +find a broken config (for example no opp-level set) the l2 scaling is +skipped. + +Signed-off-by: Ansuel Smith +--- + drivers/cpufreq/Kconfig.arm | 14 +- + drivers/cpufreq/Makefile | 2 + + drivers/cpufreq/qcom-cpufreq-krait.c | 589 +++++++++++++++++++++++++++ + 3 files changed, 604 insertions(+), 1 deletion(-) + create mode 100644 drivers/cpufreq/qcom-cpufreq-krait.c + +--- a/drivers/cpufreq/Kconfig.arm ++++ b/drivers/cpufreq/Kconfig.arm +@@ -150,6 +150,18 @@ config ARM_QCOM_CPUFREQ_HW + The driver implements the cpufreq interface for this HW engine. + Say Y if you want to support CPUFreq HW. + ++config ARM_QCOM_CPUFREQ_KRAIT ++ tristate "CPU Frequency scaling support for Krait SoCs" ++ depends on ARCH_QCOM || COMPILE_TEST ++ select PM_OPP ++ select ARM_QCOM_CPUFREQ_NVMEM ++ help ++ This adds the CPUFreq driver for Qualcomm Krait SoC based boards. ++ This scale the cache clk and regulator based on the different cpu ++ clks when scaling the different cores clk. ++ ++ If in doubt, say N. ++ + config ARM_RASPBERRYPI_CPUFREQ + tristate "Raspberry Pi cpufreq support" + depends on CLK_RASPBERRYPI || COMPILE_TEST +@@ -339,4 +351,4 @@ config ARM_PXA2xx_CPUFREQ + help + This add the CPUFreq driver support for Intel PXA2xx SOCs. + +- If in doubt, say N. ++ If in doubt, say N. +\ No newline at end of file +--- a/drivers/cpufreq/Makefile ++++ b/drivers/cpufreq/Makefile +@@ -63,6 +63,7 @@ obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2 + obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o + obj-$(CONFIG_ARM_QCOM_CPUFREQ_HW) += qcom-cpufreq-hw.o + obj-$(CONFIG_ARM_QCOM_CPUFREQ_NVMEM) += qcom-cpufreq-nvmem.o ++obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRAIT) += qcom-cpufreq-krait.o + obj-$(CONFIG_ARM_RASPBERRYPI_CPUFREQ) += raspberrypi-cpufreq.o + obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o + obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o +@@ -86,6 +87,7 @@ obj-$(CONFIG_ARM_TEGRA186_CPUFREQ) += te + obj-$(CONFIG_ARM_TEGRA194_CPUFREQ) += tegra194-cpufreq.o + obj-$(CONFIG_ARM_TI_CPUFREQ) += ti-cpufreq.o + obj-$(CONFIG_ARM_VEXPRESS_SPC_CPUFREQ) += vexpress-spc-cpufreq.o ++obj-$(CONFIG_ARM_KRAIT_CPUFREQ) += krait-cpufreq.o + + + ################################################################################## +--- /dev/null ++++ b/drivers/cpufreq/qcom-cpufreq-krait.c +@@ -0,0 +1,603 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "cpufreq-dt.h" ++ ++static struct platform_device *l2_pdev; ++ ++struct private_data { ++ struct opp_table *opp_table; ++ struct device *cpu_dev; ++ const char *reg_name; ++ bool have_static_opps; ++}; ++ ++static int set_target(struct cpufreq_policy *policy, unsigned int index) ++{ ++ struct private_data *priv = policy->driver_data; ++ unsigned long freq = policy->freq_table[index].frequency; ++ unsigned long target_freq = freq * 1000; ++ struct dev_pm_opp *opp; ++ unsigned int level; ++ int cpu, ret; ++ ++ if (l2_pdev) { ++ int policy_cpu = policy->cpu; ++ ++ /* find the max freq across all core */ ++ for_each_present_cpu(cpu) ++ if (cpu != policy_cpu) ++ target_freq = max( ++ target_freq, ++ (unsigned long)cpufreq_quick_get(cpu)); ++ ++ opp = dev_pm_opp_find_freq_exact(priv->cpu_dev, target_freq, ++ true); ++ if (IS_ERR(opp)) { ++ dev_err(&l2_pdev->dev, "failed to find OPP for %ld\n", ++ target_freq); ++ return PTR_ERR(opp); ++ } ++ level = dev_pm_opp_get_level(opp); ++ dev_pm_opp_put(opp); ++ ++ /* ++ * Hardware constraint: ++ * Krait CPU cannot operate at 384MHz with L2 at 1Ghz. ++ * Assume index 0 with the idle freq and level > 0 as ++ * any L2 freq > 384MHz. ++ * Skip CPU freq change in this corner case. ++ */ ++ if (unlikely(index == 0 && level != 0)) { ++ dev_err(priv->cpu_dev, "Krait CPU can't operate at idle freq with L2 at 1GHz"); ++ return -EINVAL; ++ } ++ ++ opp = dev_pm_opp_find_level_exact(&l2_pdev->dev, level); ++ if (IS_ERR(opp)) { ++ dev_err(&l2_pdev->dev, ++ "failed to find level OPP for %d\n", level); ++ return PTR_ERR(opp); ++ } ++ target_freq = dev_pm_opp_get_freq(opp); ++ dev_pm_opp_put(opp); ++ ++ ret = dev_pm_opp_set_rate(&l2_pdev->dev, target_freq); ++ if (ret) ++ return ret; ++ } ++ ++ ret = dev_pm_opp_set_rate(priv->cpu_dev, freq * 1000); ++ if (ret) ++ return ret; ++ ++ arch_set_freq_scale(policy->related_cpus, freq, ++ policy->cpuinfo.max_freq); ++ ++ return 0; ++} ++ ++/* ++ * An earlier version of opp-v1 bindings used to name the regulator ++ * "cpu0-supply", we still need to handle that for backwards compatibility. ++ */ ++static const char *find_supply_name(struct device *dev) ++{ ++ struct device_node *np; ++ struct property *pp; ++ int cpu = dev->id; ++ const char *name = NULL; ++ ++ np = of_node_get(dev->of_node); ++ ++ /* This must be valid for sure */ ++ if (WARN_ON(!np)) ++ return NULL; ++ ++ /* Try "cpu0" for older DTs */ ++ if (!cpu) { ++ pp = of_find_property(np, "cpu0-supply", NULL); ++ if (pp) { ++ name = "cpu0"; ++ goto node_put; ++ } ++ } ++ ++ pp = of_find_property(np, "cpu-supply", NULL); ++ if (pp) { ++ name = "cpu"; ++ goto node_put; ++ } ++ ++ dev_dbg(dev, "no regulator for cpu%d\n", cpu); ++node_put: ++ of_node_put(np); ++ return name; ++} ++ ++static int resources_available(void) ++{ ++ struct device *cpu_dev; ++ struct regulator *cpu_reg; ++ struct clk *cpu_clk; ++ int ret = 0; ++ const char *name; ++ ++ cpu_dev = get_cpu_device(0); ++ if (!cpu_dev) { ++ pr_err("failed to get cpu0 device\n"); ++ return -ENODEV; ++ } ++ ++ cpu_clk = clk_get(cpu_dev, NULL); ++ ret = PTR_ERR_OR_ZERO(cpu_clk); ++ if (ret) { ++ /* ++ * If cpu's clk node is present, but clock is not yet ++ * registered, we should try defering probe. ++ */ ++ if (ret == -EPROBE_DEFER) ++ dev_dbg(cpu_dev, "clock not ready, retry\n"); ++ else ++ dev_err(cpu_dev, "failed to get clock: %d\n", ret); ++ ++ return ret; ++ } ++ ++ clk_put(cpu_clk); ++ ++ name = find_supply_name(cpu_dev); ++ /* Platform doesn't require regulator */ ++ if (!name) ++ return 0; ++ ++ cpu_reg = regulator_get_optional(cpu_dev, name); ++ ret = PTR_ERR_OR_ZERO(cpu_reg); ++ if (ret) { ++ /* ++ * If cpu's regulator supply node is present, but regulator is ++ * not yet registered, we should try defering probe. ++ */ ++ if (ret == -EPROBE_DEFER) ++ dev_dbg(cpu_dev, "cpu0 regulator not ready, retry\n"); ++ else ++ dev_dbg(cpu_dev, "no regulator for cpu0: %d\n", ret); ++ ++ return ret; ++ } ++ ++ regulator_put(cpu_reg); ++ return 0; ++} ++ ++static int cpufreq_init(struct cpufreq_policy *policy) ++{ ++ struct cpufreq_frequency_table *freq_table; ++ struct opp_table *opp_table = NULL; ++ unsigned int transition_latency; ++ struct private_data *priv; ++ struct device *cpu_dev; ++ bool fallback = false; ++ struct clk *cpu_clk; ++ const char *name; ++ int ret; ++ ++ cpu_dev = get_cpu_device(policy->cpu); ++ if (!cpu_dev) { ++ pr_err("failed to get cpu%d device\n", policy->cpu); ++ return -ENODEV; ++ } ++ ++ cpu_clk = clk_get(cpu_dev, NULL); ++ if (IS_ERR(cpu_clk)) { ++ ret = PTR_ERR(cpu_clk); ++ dev_err(cpu_dev, "%s: failed to get clk: %d\n", __func__, ret); ++ return ret; ++ } ++ ++ /* Get OPP-sharing information from "operating-points-v2" bindings */ ++ ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, policy->cpus); ++ if (ret) { ++ if (ret != -ENOENT) ++ goto out_put_clk; ++ ++ /* ++ * operating-points-v2 not supported, fallback to old method of ++ * finding shared-OPPs for backward compatibility if the ++ * platform hasn't set sharing CPUs. ++ */ ++ if (dev_pm_opp_get_sharing_cpus(cpu_dev, policy->cpus)) ++ fallback = true; ++ } ++ ++ /* ++ * OPP layer will be taking care of regulators now, but it needs to know ++ * the name of the regulator first. ++ */ ++ name = find_supply_name(cpu_dev); ++ if (name) { ++ opp_table = dev_pm_opp_set_regulators(cpu_dev, &name, 1); ++ if (IS_ERR(opp_table)) { ++ ret = PTR_ERR(opp_table); ++ dev_err(cpu_dev, ++ "Failed to set regulator for cpu%d: %d\n", ++ policy->cpu, ret); ++ goto out_put_clk; ++ } ++ } ++ ++ priv = kzalloc(sizeof(*priv), GFP_KERNEL); ++ if (!priv) { ++ ret = -ENOMEM; ++ goto out_put_regulator; ++ } ++ ++ priv->reg_name = name; ++ priv->opp_table = opp_table; ++ ++ /* ++ * Initialize OPP tables for all policy->cpus. They will be shared by ++ * all CPUs which have marked their CPUs shared with OPP bindings. ++ * ++ * For platforms not using operating-points-v2 bindings, we do this ++ * before updating policy->cpus. Otherwise, we will end up creating ++ * duplicate OPPs for policy->cpus. ++ * ++ * OPPs might be populated at runtime, don't check for error here ++ */ ++ if (!dev_pm_opp_of_cpumask_add_table(policy->cpus)) ++ priv->have_static_opps = true; ++ ++ /* ++ * But we need OPP table to function so if it is not there let's ++ * give platform code chance to provide it for us. ++ */ ++ ret = dev_pm_opp_get_opp_count(cpu_dev); ++ if (ret <= 0) { ++ dev_dbg(cpu_dev, "OPP table is not ready, deferring probe\n"); ++ ret = -EPROBE_DEFER; ++ goto out_free_opp; ++ } ++ ++ if (fallback) { ++ cpumask_setall(policy->cpus); ++ ++ /* ++ * OPP tables are initialized only for policy->cpu, do it for ++ * others as well. ++ */ ++ ret = dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus); ++ if (ret) ++ dev_err(cpu_dev, ++ "%s: failed to mark OPPs as shared: %d\n", ++ __func__, ret); ++ } ++ ++ ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); ++ if (ret) { ++ dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret); ++ goto out_free_opp; ++ } ++ ++ priv->cpu_dev = cpu_dev; ++ ++ policy->driver_data = priv; ++ policy->clk = cpu_clk; ++ policy->freq_table = freq_table; ++ ++ policy->suspend_freq = dev_pm_opp_get_suspend_opp_freq(cpu_dev) / 1000; ++ ++ transition_latency = dev_pm_opp_get_max_transition_latency(cpu_dev); ++ if (!transition_latency) ++ transition_latency = CPUFREQ_ETERNAL; ++ ++ policy->cpuinfo.transition_latency = transition_latency; ++ policy->dvfs_possible_from_any_cpu = true; ++ ++ dev_pm_opp_of_register_em(cpu_dev, policy->cpus); ++ ++ return 0; ++ ++out_free_opp: ++ if (priv->have_static_opps) ++ dev_pm_opp_of_cpumask_remove_table(policy->cpus); ++ kfree(priv); ++out_put_regulator: ++ if (name) ++ dev_pm_opp_put_regulators(opp_table); ++out_put_clk: ++ clk_put(cpu_clk); ++ ++ return ret; ++} ++ ++static int cpufreq_online(struct cpufreq_policy *policy) ++{ ++ /* We did light-weight tear down earlier, nothing to do here */ ++ return 0; ++} ++ ++static int cpufreq_offline(struct cpufreq_policy *policy) ++{ ++ /* ++ * Preserve policy->driver_data and don't free resources on light-weight ++ * tear down. ++ */ ++ return 0; ++} ++ ++static int cpufreq_exit(struct cpufreq_policy *policy) ++{ ++ struct private_data *priv = policy->driver_data; ++ ++ dev_pm_opp_free_cpufreq_table(priv->cpu_dev, &policy->freq_table); ++ if (priv->have_static_opps) ++ dev_pm_opp_of_cpumask_remove_table(policy->related_cpus); ++ if (priv->reg_name) ++ dev_pm_opp_put_regulators(priv->opp_table); ++ ++ clk_put(policy->clk); ++ kfree(priv); ++ ++ return 0; ++} ++ ++static struct cpufreq_driver krait_cpufreq_driver = { ++ .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK | ++ CPUFREQ_IS_COOLING_DEV, ++ .verify = cpufreq_generic_frequency_table_verify, ++ .target_index = set_target, ++ .get = cpufreq_generic_get, ++ .init = cpufreq_init, ++ .exit = cpufreq_exit, ++ .online = cpufreq_online, ++ .offline = cpufreq_offline, ++ .name = "krait-cpufreq", ++ .suspend = cpufreq_generic_suspend, ++}; ++ ++struct krait_data { ++ unsigned long idle_freq; ++ bool regulator_enabled; ++}; ++ ++static int krait_cache_set_opp(struct dev_pm_set_opp_data *data) ++{ ++ unsigned long old_freq = data->old_opp.rate, freq = data->new_opp.rate; ++ struct dev_pm_opp_supply *supply = &data->new_opp.supplies[0]; ++ struct regulator *reg = data->regulators[0]; ++ struct clk *clk = data->clk; ++ struct krait_data *kdata; ++ unsigned long idle_freq; ++ int ret; ++ ++ kdata = (struct krait_data *)dev_get_drvdata(data->dev); ++ idle_freq = kdata->idle_freq; ++ ++ /* Scaling up? Scale voltage before frequency */ ++ if (freq >= old_freq) { ++ ret = regulator_set_voltage_triplet(reg, supply->u_volt_min, ++ supply->u_volt, ++ supply->u_volt_max); ++ if (ret) ++ goto exit; ++ } ++ ++ /* ++ * Set to idle bin if switching from normal to high bin ++ * or vice versa. It has been notice that a bug is triggered ++ * in cache scaling when more than one bin is scaled, to fix ++ * this we first need to transition to the base rate and then ++ * to target rate ++ */ ++ if (likely(freq != idle_freq && old_freq != idle_freq)) { ++ ret = clk_set_rate(clk, idle_freq); ++ if (ret) ++ goto exit; ++ } ++ ++ ret = clk_set_rate(clk, freq); ++ if (ret) ++ goto exit; ++ ++ /* Scaling down? Scale voltage after frequency */ ++ if (freq < old_freq) { ++ ret = regulator_set_voltage_triplet(reg, supply->u_volt_min, ++ supply->u_volt, ++ supply->u_volt_max); ++ } ++ ++ if (unlikely(!kdata->regulator_enabled)) { ++ ret = regulator_enable(reg); ++ if (ret < 0) ++ dev_warn(data->dev, "Failed to enable regulator: %d", ret); ++ else ++ kdata->regulator_enabled = true; ++ } ++ ++exit: ++ return ret; ++}; ++ ++static int krait_cache_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct krait_data *data; ++ struct opp_table *table; ++ struct dev_pm_opp *opp; ++ struct device *cpu_dev; ++ int ret; ++ ++ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); ++ if (!data) ++ return -ENOMEM; ++ ++ table = dev_pm_opp_set_regulators(dev, (const char *[]){ "l2" }, 1); ++ if (IS_ERR(table)) { ++ ret = PTR_ERR(table); ++ if (ret != -EPROBE_DEFER) ++ dev_err(dev, "failed to set regulators %d\n", ret); ++ ++ return ret; ++ } ++ ++ ret = PTR_ERR_OR_ZERO( ++ dev_pm_opp_register_set_opp_helper(dev, krait_cache_set_opp)); ++ if (ret) ++ return ret; ++ ++ ret = dev_pm_opp_of_add_table(dev); ++ if (ret) { ++ dev_err(dev, "failed to parse L2 freq thresholds\n"); ++ return ret; ++ } ++ ++ opp = dev_pm_opp_find_freq_ceil(dev, &data->idle_freq); ++ dev_pm_opp_put(opp); ++ ++ /* ++ * Check opp-level configuration ++ * At least 2 level must be set or the cache will always be scaled ++ * the idle freq causing some performance problem ++ * ++ * In case of invalid configuration, the l2 scaling is skipped ++ */ ++ cpu_dev = get_cpu_device(0); ++ if (!cpu_dev) { ++ pr_err("failed to get cpu0 device\n"); ++ return -ENODEV; ++ } ++ ++ /* ++ * Check if we have at least opp-level 1, 0 should always be set to ++ * the idle freq ++ */ ++ opp = dev_pm_opp_find_level_exact(dev, 1); ++ if (IS_ERR(opp)) { ++ dev_err(dev, ++ "Invalid configuration found of l2 opp. Can't find opp-level 1"); ++ goto invalid_conf; ++ } ++ dev_pm_opp_put(opp); ++ ++ /* ++ * Check if we have at least opp-level 1 in the cpu opp, 0 should always ++ * be set to the idle freq ++ */ ++ opp = dev_pm_opp_find_level_exact(cpu_dev, 1); ++ if (IS_ERR(opp)) { ++ dev_err(dev, ++ "Invalid configuration found of cpu opp. Can't find opp-level 1"); ++ goto invalid_conf; ++ } ++ dev_pm_opp_put(opp); ++ ++ platform_set_drvdata(pdev, data); ++ ++ /* The l2 scaling is enabled by linking the cpufreq driver */ ++ l2_pdev = pdev; ++ ++ return 0; ++ ++invalid_conf: ++ dev_pm_opp_remove_table(dev); ++ dev_pm_opp_put_regulators(table); ++ dev_pm_opp_unregister_set_opp_helper(table); ++ ++ return -EINVAL; ++}; ++ ++static int krait_cache_remove(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct opp_table *table = dev_pm_opp_get_opp_table(dev); ++ ++ dev_pm_opp_remove_table(dev); ++ dev_pm_opp_put_regulators(table); ++ dev_pm_opp_unregister_set_opp_helper(table); ++ ++ return 0; ++}; ++ ++static const struct of_device_id krait_cache_match_table[] = { ++ { .compatible = "qcom,krait-cache" }, ++ {} ++}; ++ ++static struct platform_driver krait_cache_driver = { ++ .driver = { ++ .name = "krait-cache", ++ .of_match_table = krait_cache_match_table, ++ }, ++ .probe = krait_cache_probe, ++ .remove = krait_cache_remove, ++}; ++module_platform_driver(krait_cache_driver); ++ ++static int krait_cpufreq_probe(struct platform_device *pdev) ++{ ++ struct cpufreq_dt_platform_data *data = dev_get_platdata(&pdev->dev); ++ int ret; ++ ++ /* ++ * All per-cluster (CPUs sharing clock/voltages) initialization is done ++ * from ->init(). In probe(), we just need to make sure that clk and ++ * regulators are available. Else defer probe and retry. ++ * ++ * FIXME: Is checking this only for CPU0 sufficient ? ++ */ ++ ret = resources_available(); ++ if (ret) ++ return ret; ++ ++ if (data) { ++ if (data->have_governor_per_policy) ++ krait_cpufreq_driver.flags |= ++ CPUFREQ_HAVE_GOVERNOR_PER_POLICY; ++ ++ krait_cpufreq_driver.resume = data->resume; ++ if (data->suspend) ++ krait_cpufreq_driver.suspend = data->suspend; ++ } ++ ++ ret = cpufreq_register_driver(&krait_cpufreq_driver); ++ if (ret) ++ dev_err(&pdev->dev, "failed register driver: %d\n", ret); ++ ++ return ret; ++} ++ ++static int krait_cpufreq_remove(struct platform_device *pdev) ++{ ++ cpufreq_unregister_driver(&krait_cpufreq_driver); ++ return 0; ++} ++ ++static struct platform_driver krait_cpufreq_platdrv = { ++ .driver = { ++ .name = "krait-cpufreq", ++ }, ++ .probe = krait_cpufreq_probe, ++ .remove = krait_cpufreq_remove, ++}; ++module_platform_driver(krait_cpufreq_platdrv); ++ ++MODULE_ALIAS("platform:krait-cpufreq"); ++MODULE_AUTHOR("Ansuel Smith "); ++MODULE_DESCRIPTION("Dedicated Krait SoC cpufreq driver"); ++MODULE_LICENSE("GPL"); diff --git a/root/target/linux/ipq806x/patches-5.15/098-2-Documentation-cpufreq-add-qcom-krait-cpufreq-binding.patch b/root/target/linux/ipq806x/patches-5.10/098-2-Documentation-cpufreq-add-qcom-krait-cpufreq-binding.patch similarity index 100% rename from root/target/linux/ipq806x/patches-5.15/098-2-Documentation-cpufreq-add-qcom-krait-cpufreq-binding.patch rename to root/target/linux/ipq806x/patches-5.10/098-2-Documentation-cpufreq-add-qcom-krait-cpufreq-binding.patch diff --git a/root/target/linux/ipq806x/patches-5.10/098-3-add-fab-scaling-support-with-cpufreq.patch b/root/target/linux/ipq806x/patches-5.10/098-3-add-fab-scaling-support-with-cpufreq.patch new file mode 100755 index 00000000..8ce3f062 --- /dev/null +++ b/root/target/linux/ipq806x/patches-5.10/098-3-add-fab-scaling-support-with-cpufreq.patch @@ -0,0 +1,243 @@ +--- a/drivers/clk/qcom/Makefile ++++ b/drivers/clk/qcom/Makefile +@@ -15,6 +15,7 @@ clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-k + clk-qcom-y += clk-hfpll.o + clk-qcom-y += reset.o + clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o ++clk-qcom-y += fab_scaling.o + + # Keep alphabetically sorted by config + obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o +--- /dev/null ++++ b/drivers/clk/qcom/fab_scaling.c +@@ -0,0 +1,172 @@ ++/* ++ * Copyright (c) 2015, The Linux Foundation. All rights reserved. ++ * ++ * Permission to use, copy, modify, and/or distribute this software for any ++ * purpose with or without fee is hereby granted, provided that the above ++ * copyright notice and this permission notice appear in all copies. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES ++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES ++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF ++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++struct qcom_fab_scaling_data { ++ u32 fab_freq_high; ++ u32 fab_freq_nominal; ++ u32 cpu_freq_threshold; ++ struct clk *apps_fab_clk; ++ struct clk *ddr_fab_clk; ++}; ++ ++static struct qcom_fab_scaling_data *drv_data; ++ ++int scale_fabrics(unsigned long max_cpu_freq) ++{ ++ struct clk *apps_fab_clk = drv_data->apps_fab_clk, ++ *ddr_fab_clk = drv_data->ddr_fab_clk; ++ unsigned long target_freq, cur_freq; ++ int ret; ++ ++ /* Skip fab scaling if the driver is not ready */ ++ if (!apps_fab_clk || !ddr_fab_clk) ++ return 0; ++ ++ if (max_cpu_freq > drv_data->cpu_freq_threshold) ++ target_freq = drv_data->fab_freq_high; ++ else ++ target_freq = drv_data->fab_freq_nominal; ++ ++ cur_freq = clk_get_rate(ddr_fab_clk); ++ ++ if (target_freq != cur_freq) { ++ ret = clk_set_rate(apps_fab_clk, target_freq); ++ if (ret) ++ return ret; ++ ret = clk_set_rate(ddr_fab_clk, target_freq); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL(scale_fabrics); ++ ++static int ipq806x_fab_scaling_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node; ++ struct clk *apps_fab_clk, *ddr_fab_clk; ++ int ret; ++ ++ if (!np) ++ return -ENODEV; ++ ++ drv_data = kzalloc(sizeof(*drv_data), GFP_KERNEL); ++ if (!drv_data) ++ return -ENOMEM; ++ ++ if (of_property_read_u32(np, "fab_freq_high", &drv_data->fab_freq_high)) { ++ pr_err("FABRICS turbo freq not found. Using defaults...\n"); ++ drv_data->fab_freq_high = 533000000; ++ } ++ ++ if (of_property_read_u32(np, "fab_freq_nominal", &drv_data->fab_freq_nominal)) { ++ pr_err("FABRICS nominal freq not found. Using defaults...\n"); ++ drv_data->fab_freq_nominal = 400000000; ++ } ++ ++ if (of_property_read_u32(np, "cpu_freq_threshold", &drv_data->cpu_freq_threshold)) { ++ pr_err("FABRICS cpu freq threshold not found. Using defaults...\n"); ++ drv_data->cpu_freq_threshold = 1000000000; ++ } ++ ++ apps_fab_clk = devm_clk_get(&pdev->dev, "apps-fab-clk"); ++ ret = PTR_ERR_OR_ZERO(apps_fab_clk); ++ if (ret) { ++ /* ++ * If apps fab clk node is present, but clock is not yet ++ * registered, we should try defering probe. ++ */ ++ if (ret != -EPROBE_DEFER) { ++ pr_err("Failed to get APPS FABRIC clock: %d\n", ret); ++ ret = -ENODEV; ++ } ++ goto err; ++ } ++ ++ clk_prepare_enable(apps_fab_clk); ++ clk_set_rate(apps_fab_clk, drv_data->fab_freq_high); ++ drv_data->apps_fab_clk = apps_fab_clk; ++ ++ ddr_fab_clk = devm_clk_get(&pdev->dev, "ddr-fab-clk"); ++ ret = PTR_ERR_OR_ZERO(ddr_fab_clk); ++ if (ret) { ++ /* ++ * If ddr fab clk node is present, but clock is not yet ++ * registered, we should try defering probe. ++ */ ++ if (ret != -EPROBE_DEFER) { ++ pr_err("Failed to get DDR FABRIC clock: %d\n", ret); ++ ddr_fab_clk = NULL; ++ ret = -ENODEV; ++ } ++ goto err; ++ } ++ ++ clk_prepare_enable(ddr_fab_clk); ++ clk_set_rate(ddr_fab_clk, drv_data->fab_freq_high); ++ drv_data->ddr_fab_clk = ddr_fab_clk; ++ ++ return 0; ++err: ++ kfree(drv_data); ++ return ret; ++} ++ ++static int ipq806x_fab_scaling_remove(struct platform_device *pdev) ++{ ++ kfree(drv_data); ++ return 0; ++} ++ ++static const struct of_device_id fab_scaling_ipq806x_match_table[] = { ++ { .compatible = "qcom,fab-scaling" }, ++ { } ++}; ++ ++static struct platform_driver fab_scaling_ipq806x_driver = { ++ .probe = ipq806x_fab_scaling_probe, ++ .remove = ipq806x_fab_scaling_remove, ++ .driver = { ++ .name = "fab-scaling", ++ .of_match_table = fab_scaling_ipq806x_match_table, ++ }, ++}; ++ ++static int __init fab_scaling_ipq806x_init(void) ++{ ++ return platform_driver_register(&fab_scaling_ipq806x_driver); ++} ++late_initcall(fab_scaling_ipq806x_init); ++ ++static void __exit fab_scaling_ipq806x_exit(void) ++{ ++ platform_driver_unregister(&fab_scaling_ipq806x_driver); ++} ++module_exit(fab_scaling_ipq806x_exit); +--- /dev/null ++++ b/include/linux/fab_scaling.h +@@ -0,0 +1,31 @@ ++/* ++ * Copyright (c) 2015, The Linux Foundation. All rights reserved. ++ * ++ * Permission to use, copy, modify, and/or distribute this software for any ++ * purpose with or without fee is hereby granted, provided that the above ++ * copyright notice and this permission notice appear in all copies. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES ++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES ++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF ++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ++ */ ++ ++ ++#ifndef __FAB_SCALING_H ++#define __FAB_SCALING_H ++ ++/** ++ * scale_fabrics - Scale DDR and APPS FABRICS ++ * ++ * This function monitors all the registered clocks and does APPS ++ * and DDR FABRIC scaling based on the idle frequencies with which ++ * it was registered. ++ * ++ */ ++int scale_fabrics(unsigned long max_cpu_freq); ++ ++#endif +--- a/drivers/cpufreq/qcom-cpufreq-krait.c ++++ b/drivers/cpufreq/qcom-cpufreq-krait.c +@@ -15,6 +15,7 @@ + #include + #include + #include ++#include + + #include "cpufreq-dt.h" + +@@ -68,6 +69,13 @@ static int set_target(struct cpufreq_pol + return -EINVAL; + } + ++ /* ++ * Scale fabrics with max freq across all cores ++ */ ++ ret = scale_fabrics(target_freq); ++ if (ret) ++ return ret; ++ + opp = dev_pm_opp_find_level_exact(&l2_pdev->dev, level); + if (IS_ERR(opp)) { + dev_err(&l2_pdev->dev, diff --git a/root/target/linux/ipq806x/patches-5.10/099-1-mtd-nand-raw-qcom_nandc-add-boot_layout_mode-support.patch b/root/target/linux/ipq806x/patches-5.10/099-1-mtd-nand-raw-qcom_nandc-add-boot_layout_mode-support.patch new file mode 100755 index 00000000..6106dfb8 --- /dev/null +++ b/root/target/linux/ipq806x/patches-5.10/099-1-mtd-nand-raw-qcom_nandc-add-boot_layout_mode-support.patch @@ -0,0 +1,239 @@ +From 6949d651e3be3ebbfedb6bbd5b541cfda6ee58a9 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Wed, 10 Feb 2021 10:40:17 +0100 +Subject: [PATCH 1/2] mtd: nand: raw: qcom_nandc: add boot_layout_mode support + +ipq806x nand have a special ecc configuration for the boot pages. The +use of the non-boot pages configuration on boot pages cause I/O error +and can cause broken data written to the nand. Add support for this +special configuration if the page to be read/write is in the size of the +boot pages set by the dts. + +Signed-off-by: Ansuel Smith +--- + drivers/mtd/nand/raw/qcom_nandc.c | 82 +++++++++++++++++++++++++++++-- + 1 file changed, 77 insertions(+), 5 deletions(-) + +--- a/drivers/mtd/nand/raw/qcom_nandc.c ++++ b/drivers/mtd/nand/raw/qcom_nandc.c +@@ -159,6 +159,11 @@ + /* NAND_CTRL bits */ + #define BAM_MODE_EN BIT(0) + ++ ++#define UD_SIZE_BYTES_MASK (0x3ff << UD_SIZE_BYTES) ++#define SPARE_SIZE_BYTES_MASK (0xf << SPARE_SIZE_BYTES) ++#define ECC_NUM_DATA_BYTES_MASK (0x3ff << ECC_NUM_DATA_BYTES) ++ + /* + * the NAND controller performs reads/writes with ECC in 516 byte chunks. + * the driver calls the chunks 'step' or 'codeword' interchangeably +@@ -430,6 +435,13 @@ struct qcom_nand_controller { + * @cfg0, cfg1, cfg0_raw..: NANDc register configurations needed for + * ecc/non-ecc mode for the current nand flash + * device ++ * ++ * @boot_pages_conf: keep track of the current ecc configuration used by ++ * the driver for read/write operation. (boot pages ++ * have different configuration than normal page) ++ * @boot_pages: number of pages starting from 0 used as boot pages ++ * where the driver will use the boot pages ecc ++ * configuration for read/write operation + */ + struct qcom_nand_host { + struct nand_chip chip; +@@ -452,6 +464,9 @@ struct qcom_nand_host { + u32 ecc_bch_cfg; + u32 clrflashstatus; + u32 clrreadstatus; ++ ++ bool boot_pages_conf; ++ u32 boot_pages; + }; + + /* +@@ -460,12 +475,14 @@ struct qcom_nand_host { + * @ecc_modes - ecc mode for NAND + * @is_bam - whether NAND controller is using BAM + * @is_qpic - whether NAND CTRL is part of qpic IP ++ * @has_boot_pages - whether NAND has different ecc settings for boot pages + * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset + */ + struct qcom_nandc_props { + u32 ecc_modes; + bool is_bam; + bool is_qpic; ++ bool has_boot_pages; + u32 dev_cmd_reg_start; + }; + +@@ -1604,7 +1621,7 @@ qcom_nandc_read_cw_raw(struct mtd_info * + data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); + oob_size1 = host->bbm_size; + +- if (cw == (ecc->steps - 1)) { ++ if (cw == (ecc->steps - 1) && !host->boot_pages_conf) { + data_size2 = ecc->size - data_size1 - + ((ecc->steps - 1) * 4); + oob_size2 = (ecc->steps * 4) + host->ecc_bytes_hw + +@@ -1685,7 +1702,7 @@ check_for_erased_page(struct qcom_nand_h + } + + for_each_set_bit(cw, &uncorrectable_cws, ecc->steps) { +- if (cw == (ecc->steps - 1)) { ++ if (cw == (ecc->steps - 1) && !host->boot_pages_conf) { + data_size = ecc->size - ((ecc->steps - 1) * 4); + oob_size = (ecc->steps * 4) + host->ecc_bytes_hw; + } else { +@@ -1844,7 +1861,7 @@ static int read_page_ecc(struct qcom_nan + for (i = 0; i < ecc->steps; i++) { + int data_size, oob_size; + +- if (i == (ecc->steps - 1)) { ++ if (i == (ecc->steps - 1) && !host->boot_pages_conf) { + data_size = ecc->size - ((ecc->steps - 1) << 2); + oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + + host->spare_bytes; +@@ -1941,6 +1958,30 @@ static int copy_last_cw(struct qcom_nand + return ret; + } + ++static void ++check_boot_pages_conf(struct qcom_nand_host *host, int page) ++{ ++ bool boot_pages_conf = page < host->boot_pages; ++ ++ /* Skip conf write if we are already in the correct mode */ ++ if (boot_pages_conf != host->boot_pages_conf) { ++ host->boot_pages_conf = boot_pages_conf; ++ ++ host->cw_data = boot_pages_conf ? 512 : 516; ++ host->spare_bytes = host->cw_size - host->ecc_bytes_hw - ++ host->bbm_size - host->cw_data; ++ ++ host->cfg0 &= ~(SPARE_SIZE_BYTES_MASK | UD_SIZE_BYTES_MASK); ++ host->cfg0 |= host->spare_bytes << SPARE_SIZE_BYTES | ++ host->cw_data << UD_SIZE_BYTES; ++ ++ host->ecc_bch_cfg &= ~ECC_NUM_DATA_BYTES_MASK; ++ host->ecc_bch_cfg |= host->cw_data << ECC_NUM_DATA_BYTES; ++ host->ecc_buf_cfg = (boot_pages_conf ? 0x1ff : 0x203) << ++ NUM_STEPS; ++ } ++} ++ + /* implements ecc->read_page() */ + static int qcom_nandc_read_page(struct nand_chip *chip, uint8_t *buf, + int oob_required, int page) +@@ -1949,6 +1990,9 @@ static int qcom_nandc_read_page(struct n + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); + u8 *data_buf, *oob_buf = NULL; + ++ if (host->boot_pages) ++ check_boot_pages_conf(host, page); ++ + nand_read_page_op(chip, page, 0, NULL, 0); + data_buf = buf; + oob_buf = oob_required ? chip->oob_poi : NULL; +@@ -1968,6 +2012,9 @@ static int qcom_nandc_read_page_raw(stru + int cw, ret; + u8 *data_buf = buf, *oob_buf = chip->oob_poi; + ++ if (host->boot_pages) ++ check_boot_pages_conf(host, page); ++ + for (cw = 0; cw < ecc->steps; cw++) { + ret = qcom_nandc_read_cw_raw(mtd, chip, data_buf, oob_buf, + page, cw); +@@ -1988,6 +2035,9 @@ static int qcom_nandc_read_oob(struct na + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); + struct nand_ecc_ctrl *ecc = &chip->ecc; + ++ if (host->boot_pages) ++ check_boot_pages_conf(host, page); ++ + clear_read_regs(nandc); + clear_bam_transaction(nandc); + +@@ -2008,6 +2058,9 @@ static int qcom_nandc_write_page(struct + u8 *data_buf, *oob_buf; + int i, ret; + ++ if (host->boot_pages) ++ check_boot_pages_conf(host, page); ++ + nand_prog_page_begin_op(chip, page, 0, NULL, 0); + + clear_read_regs(nandc); +@@ -2023,7 +2076,7 @@ static int qcom_nandc_write_page(struct + for (i = 0; i < ecc->steps; i++) { + int data_size, oob_size; + +- if (i == (ecc->steps - 1)) { ++ if (i == (ecc->steps - 1) && !host->boot_pages_conf) { + data_size = ecc->size - ((ecc->steps - 1) << 2); + oob_size = (ecc->steps << 2) + host->ecc_bytes_hw + + host->spare_bytes; +@@ -2080,6 +2133,9 @@ static int qcom_nandc_write_page_raw(str + u8 *data_buf, *oob_buf; + int i, ret; + ++ if (host->boot_pages) ++ check_boot_pages_conf(host, page); ++ + nand_prog_page_begin_op(chip, page, 0, NULL, 0); + clear_read_regs(nandc); + clear_bam_transaction(nandc); +@@ -2098,7 +2154,7 @@ static int qcom_nandc_write_page_raw(str + data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1); + oob_size1 = host->bbm_size; + +- if (i == (ecc->steps - 1)) { ++ if (i == (ecc->steps - 1) && !host->boot_pages_conf) { + data_size2 = ecc->size - data_size1 - + ((ecc->steps - 1) << 2); + oob_size2 = (ecc->steps << 2) + host->ecc_bytes_hw + +@@ -2158,6 +2214,9 @@ static int qcom_nandc_write_oob(struct n + int data_size, oob_size; + int ret; + ++ if (host->boot_pages) ++ check_boot_pages_conf(host, page); ++ + host->use_ecc = true; + clear_bam_transaction(nandc); + +@@ -2806,6 +2865,7 @@ static int qcom_nand_host_init_and_regis + struct nand_chip *chip = &host->chip; + struct mtd_info *mtd = nand_to_mtd(chip); + struct device *dev = nandc->dev; ++ u32 boot_pages_size; + int ret; + + ret = of_property_read_u32(dn, "reg", &host->cs); +@@ -2866,6 +2926,17 @@ static int qcom_nand_host_init_and_regis + if (ret) + nand_cleanup(chip); + ++ if (nandc->props->has_boot_pages && ++ of_property_read_bool(dn, "nand-is-boot-medium")) { ++ ret = of_property_read_u32(dn, "qcom,boot_pages_size", ++ &boot_pages_size); ++ if (ret) ++ dev_warn(dev, "can't get boot pages size"); ++ else ++ /* Convert size to nand pages */ ++ host->boot_pages = boot_pages_size / mtd->writesize; ++ } ++ + return ret; + } + +@@ -3032,6 +3103,7 @@ static int qcom_nandc_remove(struct plat + static const struct qcom_nandc_props ipq806x_nandc_props = { + .ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT), + .is_bam = false, ++ .has_boot_pages = true, + .dev_cmd_reg_start = 0x0, + }; + diff --git a/root/target/linux/ipq806x/patches-5.10/099-2-Documentation-devicetree-mtd-qcom_nandc-document-qco.patch b/root/target/linux/ipq806x/patches-5.10/099-2-Documentation-devicetree-mtd-qcom_nandc-document-qco.patch new file mode 100755 index 00000000..79036cb0 --- /dev/null +++ b/root/target/linux/ipq806x/patches-5.10/099-2-Documentation-devicetree-mtd-qcom_nandc-document-qco.patch @@ -0,0 +1,42 @@ +From 6fb003a7a117f97a35b078ba726c84adeae29c4c Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Wed, 10 Feb 2021 10:54:19 +0100 +Subject: [PATCH 2/2] Documentation: devicetree: mtd: qcom_nandc: document + qcom,boot_layout_size binding + +Document new qcom,boot_layout_size binding used to apply special +read/write confituation to boots partitions. + +Signed-off-by: Ansuel Smith +--- + Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +--- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt ++++ b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt +@@ -52,6 +52,15 @@ Optional properties: + be used according to chip requirement and available + OOB size. + ++EBI2 specific properties: ++- nand-is-boot-medium: nand contains boot partitions and different ecc configuration ++ should be used for these partitions. ++- qcom,boot_pages_size: should contain the size of the total boot partitions ++ where the boot layout read/write specific configuration ++ should be used. The boot layout is considered from the ++ start of the nand to the value set in this binding. ++ Only used in combination with 'nand-is-boot-medium'. ++ + Each nandcs device node may optionally contain a 'partitions' sub-node, which + further contains sub-nodes describing the flash partition mapping. See + partition.txt for more detail. +@@ -80,6 +89,9 @@ nand-controller@1ac00000 { + nand-ecc-strength = <4>; + nand-bus-width = <8>; + ++ nand-is-boot-medium; ++ qcom,boot_pages_size: <0x58a0000>; ++ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; diff --git a/root/target/linux/ipq806x/patches-5.10/100-v5.11-dmaengine-qcom-add_ADM_driver.patch b/root/target/linux/ipq806x/patches-5.10/100-v5.11-dmaengine-qcom-add_ADM_driver.patch new file mode 100755 index 00000000..2d24da01 --- /dev/null +++ b/root/target/linux/ipq806x/patches-5.10/100-v5.11-dmaengine-qcom-add_ADM_driver.patch @@ -0,0 +1,965 @@ +From 5c9f8c2dbdbe53818bcde6aa6695e1331e5f841f Mon Sep 17 00:00:00 2001 +From: Jonathan McDowell +Date: Sat, 14 Nov 2020 14:02:33 +0000 +Subject: dmaengine: qcom: Add ADM driver + +Add the DMA engine driver for the QCOM Application Data Mover (ADM) DMA +controller found in the MSM8x60 and IPQ/APQ8064 platforms. + +The ADM supports both memory to memory transactions and memory +to/from peripheral device transactions. The controller also provides +flow control capabilities for transactions to/from peripheral devices. + +The initial release of this driver supports slave transfers to/from +peripherals and also incorporates CRCI (client rate control interface) +flow control. + +The hardware only supports a 32 bit physical address, so specifying +!PHYS_ADDR_T_64BIT gives maximum COMPILE_TEST coverage without having to +spend effort on kludging things in the code that will never actually be +needed on real hardware. + +Signed-off-by: Andy Gross +Signed-off-by: Thomas Pedersen +Signed-off-by: Jonathan McDowell +Link: https://lore.kernel.org/r/20201114140233.GM32650@earth.li +Signed-off-by: Vinod Koul +--- + drivers/dma/qcom/Kconfig | 11 + + drivers/dma/qcom/Makefile | 1 + + drivers/dma/qcom/qcom_adm.c | 903 ++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 915 insertions(+) + create mode 100644 drivers/dma/qcom/qcom_adm.c + +--- a/drivers/dma/qcom/Kconfig ++++ b/drivers/dma/qcom/Kconfig +@@ -1,4 +1,15 @@ + # SPDX-License-Identifier: GPL-2.0-only ++config QCOM_ADM ++ tristate "Qualcomm ADM support" ++ depends on (ARCH_QCOM || COMPILE_TEST) && !PHYS_ADDR_T_64BIT ++ select DMA_ENGINE ++ select DMA_VIRTUAL_CHANNELS ++ help ++ Enable support for the Qualcomm Application Data Mover (ADM) DMA ++ controller, as present on MSM8x60, APQ8064, and IPQ8064 devices. ++ This controller provides DMA capabilities for both general purpose ++ and on-chip peripheral devices. ++ + config QCOM_BAM_DMA + tristate "QCOM BAM DMA support" + depends on ARCH_QCOM || (COMPILE_TEST && OF && ARM) +--- a/drivers/dma/qcom/Makefile ++++ b/drivers/dma/qcom/Makefile +@@ -1,4 +1,5 @@ + # SPDX-License-Identifier: GPL-2.0 ++obj-$(CONFIG_QCOM_ADM) += qcom_adm.o + obj-$(CONFIG_QCOM_BAM_DMA) += bam_dma.o + obj-$(CONFIG_QCOM_HIDMA_MGMT) += hdma_mgmt.o + hdma_mgmt-objs := hidma_mgmt.o hidma_mgmt_sys.o +--- /dev/null ++++ b/drivers/dma/qcom/qcom_adm.c +@@ -0,0 +1,903 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "../dmaengine.h" ++#include "../virt-dma.h" ++ ++/* ADM registers - calculated from channel number and security domain */ ++#define ADM_CHAN_MULTI 0x4 ++#define ADM_CI_MULTI 0x4 ++#define ADM_CRCI_MULTI 0x4 ++#define ADM_EE_MULTI 0x800 ++#define ADM_CHAN_OFFS(chan) (ADM_CHAN_MULTI * (chan)) ++#define ADM_EE_OFFS(ee) (ADM_EE_MULTI * (ee)) ++#define ADM_CHAN_EE_OFFS(chan, ee) (ADM_CHAN_OFFS(chan) + ADM_EE_OFFS(ee)) ++#define ADM_CHAN_OFFS(chan) (ADM_CHAN_MULTI * (chan)) ++#define ADM_CI_OFFS(ci) (ADM_CHAN_OFF(ci)) ++#define ADM_CH_CMD_PTR(chan, ee) (ADM_CHAN_EE_OFFS(chan, ee)) ++#define ADM_CH_RSLT(chan, ee) (0x40 + ADM_CHAN_EE_OFFS(chan, ee)) ++#define ADM_CH_FLUSH_STATE0(chan, ee) (0x80 + ADM_CHAN_EE_OFFS(chan, ee)) ++#define ADM_CH_STATUS_SD(chan, ee) (0x200 + ADM_CHAN_EE_OFFS(chan, ee)) ++#define ADM_CH_CONF(chan) (0x240 + ADM_CHAN_OFFS(chan)) ++#define ADM_CH_RSLT_CONF(chan, ee) (0x300 + ADM_CHAN_EE_OFFS(chan, ee)) ++#define ADM_SEC_DOMAIN_IRQ_STATUS(ee) (0x380 + ADM_EE_OFFS(ee)) ++#define ADM_CI_CONF(ci) (0x390 + (ci) * ADM_CI_MULTI) ++#define ADM_GP_CTL 0x3d8 ++#define ADM_CRCI_CTL(crci, ee) (0x400 + (crci) * ADM_CRCI_MULTI + \ ++ ADM_EE_OFFS(ee)) ++ ++/* channel status */ ++#define ADM_CH_STATUS_VALID BIT(1) ++ ++/* channel result */ ++#define ADM_CH_RSLT_VALID BIT(31) ++#define ADM_CH_RSLT_ERR BIT(3) ++#define ADM_CH_RSLT_FLUSH BIT(2) ++#define ADM_CH_RSLT_TPD BIT(1) ++ ++/* channel conf */ ++#define ADM_CH_CONF_SHADOW_EN BIT(12) ++#define ADM_CH_CONF_MPU_DISABLE BIT(11) ++#define ADM_CH_CONF_PERM_MPU_CONF BIT(9) ++#define ADM_CH_CONF_FORCE_RSLT_EN BIT(7) ++#define ADM_CH_CONF_SEC_DOMAIN(ee) ((((ee) & 0x3) << 4) | (((ee) & 0x4) << 11)) ++ ++/* channel result conf */ ++#define ADM_CH_RSLT_CONF_FLUSH_EN BIT(1) ++#define ADM_CH_RSLT_CONF_IRQ_EN BIT(0) ++ ++/* CRCI CTL */ ++#define ADM_CRCI_CTL_MUX_SEL BIT(18) ++#define ADM_CRCI_CTL_RST BIT(17) ++ ++/* CI configuration */ ++#define ADM_CI_RANGE_END(x) ((x) << 24) ++#define ADM_CI_RANGE_START(x) ((x) << 16) ++#define ADM_CI_BURST_4_WORDS BIT(2) ++#define ADM_CI_BURST_8_WORDS BIT(3) ++ ++/* GP CTL */ ++#define ADM_GP_CTL_LP_EN BIT(12) ++#define ADM_GP_CTL_LP_CNT(x) ((x) << 8) ++ ++/* Command pointer list entry */ ++#define ADM_CPLE_LP BIT(31) ++#define ADM_CPLE_CMD_PTR_LIST BIT(29) ++ ++/* Command list entry */ ++#define ADM_CMD_LC BIT(31) ++#define ADM_CMD_DST_CRCI(n) (((n) & 0xf) << 7) ++#define ADM_CMD_SRC_CRCI(n) (((n) & 0xf) << 3) ++ ++#define ADM_CMD_TYPE_SINGLE 0x0 ++#define ADM_CMD_TYPE_BOX 0x3 ++ ++#define ADM_CRCI_MUX_SEL BIT(4) ++#define ADM_DESC_ALIGN 8 ++#define ADM_MAX_XFER (SZ_64K - 1) ++#define ADM_MAX_ROWS (SZ_64K - 1) ++#define ADM_MAX_CHANNELS 16 ++ ++struct adm_desc_hw_box { ++ u32 cmd; ++ u32 src_addr; ++ u32 dst_addr; ++ u32 row_len; ++ u32 num_rows; ++ u32 row_offset; ++}; ++ ++struct adm_desc_hw_single { ++ u32 cmd; ++ u32 src_addr; ++ u32 dst_addr; ++ u32 len; ++}; ++ ++struct adm_async_desc { ++ struct virt_dma_desc vd; ++ struct adm_device *adev; ++ ++ size_t length; ++ enum dma_transfer_direction dir; ++ dma_addr_t dma_addr; ++ size_t dma_len; ++ ++ void *cpl; ++ dma_addr_t cp_addr; ++ u32 crci; ++ u32 mux; ++ u32 blk_size; ++}; ++ ++struct adm_chan { ++ struct virt_dma_chan vc; ++ struct adm_device *adev; ++ ++ /* parsed from DT */ ++ u32 id; /* channel id */ ++ ++ struct adm_async_desc *curr_txd; ++ struct dma_slave_config slave; ++ struct list_head node; ++ ++ int error; ++ int initialized; ++}; ++ ++static inline struct adm_chan *to_adm_chan(struct dma_chan *common) ++{ ++ return container_of(common, struct adm_chan, vc.chan); ++} ++ ++struct adm_device { ++ void __iomem *regs; ++ struct device *dev; ++ struct dma_device common; ++ struct device_dma_parameters dma_parms; ++ struct adm_chan *channels; ++ ++ u32 ee; ++ ++ struct clk *core_clk; ++ struct clk *iface_clk; ++ ++ struct reset_control *clk_reset; ++ struct reset_control *c0_reset; ++ struct reset_control *c1_reset; ++ struct reset_control *c2_reset; ++ int irq; ++}; ++ ++/** ++ * adm_free_chan - Frees dma resources associated with the specific channel ++ * ++ * Free all allocated descriptors associated with this channel ++ * ++ */ ++static void adm_free_chan(struct dma_chan *chan) ++{ ++ /* free all queued descriptors */ ++ vchan_free_chan_resources(to_virt_chan(chan)); ++} ++ ++/** ++ * adm_get_blksize - Get block size from burst value ++ * ++ */ ++static int adm_get_blksize(unsigned int burst) ++{ ++ int ret; ++ ++ switch (burst) { ++ case 16: ++ case 32: ++ case 64: ++ case 128: ++ ret = ffs(burst >> 4) - 1; ++ break; ++ case 192: ++ ret = 4; ++ break; ++ case 256: ++ ret = 5; ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++ return ret; ++} ++ ++/** ++ * adm_process_fc_descriptors - Process descriptors for flow controlled xfers ++ * ++ * @achan: ADM channel ++ * @desc: Descriptor memory pointer ++ * @sg: Scatterlist entry ++ * @crci: CRCI value ++ * @burst: Burst size of transaction ++ * @direction: DMA transfer direction ++ */ ++static void *adm_process_fc_descriptors(struct adm_chan *achan, void *desc, ++ struct scatterlist *sg, u32 crci, ++ u32 burst, ++ enum dma_transfer_direction direction) ++{ ++ struct adm_desc_hw_box *box_desc = NULL; ++ struct adm_desc_hw_single *single_desc; ++ u32 remainder = sg_dma_len(sg); ++ u32 rows, row_offset, crci_cmd; ++ u32 mem_addr = sg_dma_address(sg); ++ u32 *incr_addr = &mem_addr; ++ u32 *src, *dst; ++ ++ if (direction == DMA_DEV_TO_MEM) { ++ crci_cmd = ADM_CMD_SRC_CRCI(crci); ++ row_offset = burst; ++ src = &achan->slave.src_addr; ++ dst = &mem_addr; ++ } else { ++ crci_cmd = ADM_CMD_DST_CRCI(crci); ++ row_offset = burst << 16; ++ src = &mem_addr; ++ dst = &achan->slave.dst_addr; ++ } ++ ++ while (remainder >= burst) { ++ box_desc = desc; ++ box_desc->cmd = ADM_CMD_TYPE_BOX | crci_cmd; ++ box_desc->row_offset = row_offset; ++ box_desc->src_addr = *src; ++ box_desc->dst_addr = *dst; ++ ++ rows = remainder / burst; ++ rows = min_t(u32, rows, ADM_MAX_ROWS); ++ box_desc->num_rows = rows << 16 | rows; ++ box_desc->row_len = burst << 16 | burst; ++ ++ *incr_addr += burst * rows; ++ remainder -= burst * rows; ++ desc += sizeof(*box_desc); ++ } ++ ++ /* if leftover bytes, do one single descriptor */ ++ if (remainder) { ++ single_desc = desc; ++ single_desc->cmd = ADM_CMD_TYPE_SINGLE | crci_cmd; ++ single_desc->len = remainder; ++ single_desc->src_addr = *src; ++ single_desc->dst_addr = *dst; ++ desc += sizeof(*single_desc); ++ ++ if (sg_is_last(sg)) ++ single_desc->cmd |= ADM_CMD_LC; ++ } else { ++ if (box_desc && sg_is_last(sg)) ++ box_desc->cmd |= ADM_CMD_LC; ++ } ++ ++ return desc; ++} ++ ++/** ++ * adm_process_non_fc_descriptors - Process descriptors for non-fc xfers ++ * ++ * @achan: ADM channel ++ * @desc: Descriptor memory pointer ++ * @sg: Scatterlist entry ++ * @direction: DMA transfer direction ++ */ ++static void *adm_process_non_fc_descriptors(struct adm_chan *achan, void *desc, ++ struct scatterlist *sg, ++ enum dma_transfer_direction direction) ++{ ++ struct adm_desc_hw_single *single_desc; ++ u32 remainder = sg_dma_len(sg); ++ u32 mem_addr = sg_dma_address(sg); ++ u32 *incr_addr = &mem_addr; ++ u32 *src, *dst; ++ ++ if (direction == DMA_DEV_TO_MEM) { ++ src = &achan->slave.src_addr; ++ dst = &mem_addr; ++ } else { ++ src = &mem_addr; ++ dst = &achan->slave.dst_addr; ++ } ++ ++ do { ++ single_desc = desc; ++ single_desc->cmd = ADM_CMD_TYPE_SINGLE; ++ single_desc->src_addr = *src; ++ single_desc->dst_addr = *dst; ++ single_desc->len = (remainder > ADM_MAX_XFER) ? ++ ADM_MAX_XFER : remainder; ++ ++ remainder -= single_desc->len; ++ *incr_addr += single_desc->len; ++ desc += sizeof(*single_desc); ++ } while (remainder); ++ ++ /* set last command if this is the end of the whole transaction */ ++ if (sg_is_last(sg)) ++ single_desc->cmd |= ADM_CMD_LC; ++ ++ return desc; ++} ++ ++/** ++ * adm_prep_slave_sg - Prep slave sg transaction ++ * ++ * @chan: dma channel ++ * @sgl: scatter gather list ++ * @sg_len: length of sg ++ * @direction: DMA transfer direction ++ * @flags: DMA flags ++ * @context: transfer context (unused) ++ */ ++static struct dma_async_tx_descriptor *adm_prep_slave_sg(struct dma_chan *chan, ++ struct scatterlist *sgl, ++ unsigned int sg_len, ++ enum dma_transfer_direction direction, ++ unsigned long flags, ++ void *context) ++{ ++ struct adm_chan *achan = to_adm_chan(chan); ++ struct adm_device *adev = achan->adev; ++ struct adm_async_desc *async_desc; ++ struct scatterlist *sg; ++ dma_addr_t cple_addr; ++ u32 i, burst; ++ u32 single_count = 0, box_count = 0, crci = 0; ++ void *desc; ++ u32 *cple; ++ int blk_size = 0; ++ ++ if (!is_slave_direction(direction)) { ++ dev_err(adev->dev, "invalid dma direction\n"); ++ return NULL; ++ } ++ ++ /* ++ * get burst value from slave configuration ++ */ ++ burst = (direction == DMA_MEM_TO_DEV) ? ++ achan->slave.dst_maxburst : ++ achan->slave.src_maxburst; ++ ++ /* if using flow control, validate burst and crci values */ ++ if (achan->slave.device_fc) { ++ blk_size = adm_get_blksize(burst); ++ if (blk_size < 0) { ++ dev_err(adev->dev, "invalid burst value: %d\n", ++ burst); ++ return ERR_PTR(-EINVAL); ++ } ++ ++ crci = achan->slave.slave_id & 0xf; ++ if (!crci || achan->slave.slave_id > 0x1f) { ++ dev_err(adev->dev, "invalid crci value\n"); ++ return ERR_PTR(-EINVAL); ++ } ++ } ++ ++ /* iterate through sgs and compute allocation size of structures */ ++ for_each_sg(sgl, sg, sg_len, i) { ++ if (achan->slave.device_fc) { ++ box_count += DIV_ROUND_UP(sg_dma_len(sg) / burst, ++ ADM_MAX_ROWS); ++ if (sg_dma_len(sg) % burst) ++ single_count++; ++ } else { ++ single_count += DIV_ROUND_UP(sg_dma_len(sg), ++ ADM_MAX_XFER); ++ } ++ } ++ ++ async_desc = kzalloc(sizeof(*async_desc), GFP_NOWAIT); ++ if (!async_desc) ++ return ERR_PTR(-ENOMEM); ++ ++ if (crci) ++ async_desc->mux = achan->slave.slave_id & ADM_CRCI_MUX_SEL ? ++ ADM_CRCI_CTL_MUX_SEL : 0; ++ async_desc->crci = crci; ++ async_desc->blk_size = blk_size; ++ async_desc->dma_len = single_count * sizeof(struct adm_desc_hw_single) + ++ box_count * sizeof(struct adm_desc_hw_box) + ++ sizeof(*cple) + 2 * ADM_DESC_ALIGN; ++ ++ async_desc->cpl = kzalloc(async_desc->dma_len, GFP_NOWAIT); ++ if (!async_desc->cpl) ++ goto free; ++ ++ async_desc->adev = adev; ++ ++ /* both command list entry and descriptors must be 8 byte aligned */ ++ cple = PTR_ALIGN(async_desc->cpl, ADM_DESC_ALIGN); ++ desc = PTR_ALIGN(cple + 1, ADM_DESC_ALIGN); ++ ++ for_each_sg(sgl, sg, sg_len, i) { ++ async_desc->length += sg_dma_len(sg); ++ ++ if (achan->slave.device_fc) ++ desc = adm_process_fc_descriptors(achan, desc, sg, crci, ++ burst, direction); ++ else ++ desc = adm_process_non_fc_descriptors(achan, desc, sg, ++ direction); ++ } ++ ++ async_desc->dma_addr = dma_map_single(adev->dev, async_desc->cpl, ++ async_desc->dma_len, ++ DMA_TO_DEVICE); ++ if (dma_mapping_error(adev->dev, async_desc->dma_addr)) ++ goto free; ++ ++ cple_addr = async_desc->dma_addr + ((void *)cple - async_desc->cpl); ++ ++ /* init cmd list */ ++ dma_sync_single_for_cpu(adev->dev, cple_addr, sizeof(*cple), ++ DMA_TO_DEVICE); ++ *cple = ADM_CPLE_LP; ++ *cple |= (async_desc->dma_addr + ADM_DESC_ALIGN) >> 3; ++ dma_sync_single_for_device(adev->dev, cple_addr, sizeof(*cple), ++ DMA_TO_DEVICE); ++ ++ return vchan_tx_prep(&achan->vc, &async_desc->vd, flags); ++ ++free: ++ kfree(async_desc); ++ return ERR_PTR(-ENOMEM); ++} ++ ++/** ++ * adm_terminate_all - terminate all transactions on a channel ++ * @achan: adm dma channel ++ * ++ * Dequeues and frees all transactions, aborts current transaction ++ * No callbacks are done ++ * ++ */ ++static int adm_terminate_all(struct dma_chan *chan) ++{ ++ struct adm_chan *achan = to_adm_chan(chan); ++ struct adm_device *adev = achan->adev; ++ unsigned long flags; ++ LIST_HEAD(head); ++ ++ spin_lock_irqsave(&achan->vc.lock, flags); ++ vchan_get_all_descriptors(&achan->vc, &head); ++ ++ /* send flush command to terminate current transaction */ ++ writel_relaxed(0x0, ++ adev->regs + ADM_CH_FLUSH_STATE0(achan->id, adev->ee)); ++ ++ spin_unlock_irqrestore(&achan->vc.lock, flags); ++ ++ vchan_dma_desc_free_list(&achan->vc, &head); ++ ++ return 0; ++} ++ ++static int adm_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg) ++{ ++ struct adm_chan *achan = to_adm_chan(chan); ++ unsigned long flag; ++ ++ spin_lock_irqsave(&achan->vc.lock, flag); ++ memcpy(&achan->slave, cfg, sizeof(struct dma_slave_config)); ++ spin_unlock_irqrestore(&achan->vc.lock, flag); ++ ++ return 0; ++} ++ ++/** ++ * adm_start_dma - start next transaction ++ * @achan - ADM dma channel ++ */ ++static void adm_start_dma(struct adm_chan *achan) ++{ ++ struct virt_dma_desc *vd = vchan_next_desc(&achan->vc); ++ struct adm_device *adev = achan->adev; ++ struct adm_async_desc *async_desc; ++ ++ lockdep_assert_held(&achan->vc.lock); ++ ++ if (!vd) ++ return; ++ ++ list_del(&vd->node); ++ ++ /* write next command list out to the CMD FIFO */ ++ async_desc = container_of(vd, struct adm_async_desc, vd); ++ achan->curr_txd = async_desc; ++ ++ /* reset channel error */ ++ achan->error = 0; ++ ++ if (!achan->initialized) { ++ /* enable interrupts */ ++ writel(ADM_CH_CONF_SHADOW_EN | ++ ADM_CH_CONF_PERM_MPU_CONF | ++ ADM_CH_CONF_MPU_DISABLE | ++ ADM_CH_CONF_SEC_DOMAIN(adev->ee), ++ adev->regs + ADM_CH_CONF(achan->id)); ++ ++ writel(ADM_CH_RSLT_CONF_IRQ_EN | ADM_CH_RSLT_CONF_FLUSH_EN, ++ adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee)); ++ ++ achan->initialized = 1; ++ } ++ ++ /* set the crci block size if this transaction requires CRCI */ ++ if (async_desc->crci) { ++ writel(async_desc->mux | async_desc->blk_size, ++ adev->regs + ADM_CRCI_CTL(async_desc->crci, adev->ee)); ++ } ++ ++ /* make sure IRQ enable doesn't get reordered */ ++ wmb(); ++ ++ /* write next command list out to the CMD FIFO */ ++ writel(ALIGN(async_desc->dma_addr, ADM_DESC_ALIGN) >> 3, ++ adev->regs + ADM_CH_CMD_PTR(achan->id, adev->ee)); ++} ++ ++/** ++ * adm_dma_irq - irq handler for ADM controller ++ * @irq: IRQ of interrupt ++ * @data: callback data ++ * ++ * IRQ handler for the bam controller ++ */ ++static irqreturn_t adm_dma_irq(int irq, void *data) ++{ ++ struct adm_device *adev = data; ++ u32 srcs, i; ++ struct adm_async_desc *async_desc; ++ unsigned long flags; ++ ++ srcs = readl_relaxed(adev->regs + ++ ADM_SEC_DOMAIN_IRQ_STATUS(adev->ee)); ++ ++ for (i = 0; i < ADM_MAX_CHANNELS; i++) { ++ struct adm_chan *achan = &adev->channels[i]; ++ u32 status, result; ++ ++ if (srcs & BIT(i)) { ++ status = readl_relaxed(adev->regs + ++ ADM_CH_STATUS_SD(i, adev->ee)); ++ ++ /* if no result present, skip */ ++ if (!(status & ADM_CH_STATUS_VALID)) ++ continue; ++ ++ result = readl_relaxed(adev->regs + ++ ADM_CH_RSLT(i, adev->ee)); ++ ++ /* no valid results, skip */ ++ if (!(result & ADM_CH_RSLT_VALID)) ++ continue; ++ ++ /* flag error if transaction was flushed or failed */ ++ if (result & (ADM_CH_RSLT_ERR | ADM_CH_RSLT_FLUSH)) ++ achan->error = 1; ++ ++ spin_lock_irqsave(&achan->vc.lock, flags); ++ async_desc = achan->curr_txd; ++ ++ achan->curr_txd = NULL; ++ ++ if (async_desc) { ++ vchan_cookie_complete(&async_desc->vd); ++ ++ /* kick off next DMA */ ++ adm_start_dma(achan); ++ } ++ ++ spin_unlock_irqrestore(&achan->vc.lock, flags); ++ } ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++/** ++ * adm_tx_status - returns status of transaction ++ * @chan: dma channel ++ * @cookie: transaction cookie ++ * @txstate: DMA transaction state ++ * ++ * Return status of dma transaction ++ */ ++static enum dma_status adm_tx_status(struct dma_chan *chan, dma_cookie_t cookie, ++ struct dma_tx_state *txstate) ++{ ++ struct adm_chan *achan = to_adm_chan(chan); ++ struct virt_dma_desc *vd; ++ enum dma_status ret; ++ unsigned long flags; ++ size_t residue = 0; ++ ++ ret = dma_cookie_status(chan, cookie, txstate); ++ if (ret == DMA_COMPLETE || !txstate) ++ return ret; ++ ++ spin_lock_irqsave(&achan->vc.lock, flags); ++ ++ vd = vchan_find_desc(&achan->vc, cookie); ++ if (vd) ++ residue = container_of(vd, struct adm_async_desc, vd)->length; ++ ++ spin_unlock_irqrestore(&achan->vc.lock, flags); ++ ++ /* ++ * residue is either the full length if it is in the issued list, or 0 ++ * if it is in progress. We have no reliable way of determining ++ * anything inbetween ++ */ ++ dma_set_residue(txstate, residue); ++ ++ if (achan->error) ++ return DMA_ERROR; ++ ++ return ret; ++} ++ ++/** ++ * adm_issue_pending - starts pending transactions ++ * @chan: dma channel ++ * ++ * Issues all pending transactions and starts DMA ++ */ ++static void adm_issue_pending(struct dma_chan *chan) ++{ ++ struct adm_chan *achan = to_adm_chan(chan); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&achan->vc.lock, flags); ++ ++ if (vchan_issue_pending(&achan->vc) && !achan->curr_txd) ++ adm_start_dma(achan); ++ spin_unlock_irqrestore(&achan->vc.lock, flags); ++} ++ ++/** ++ * adm_dma_free_desc - free descriptor memory ++ * @vd: virtual descriptor ++ * ++ */ ++static void adm_dma_free_desc(struct virt_dma_desc *vd) ++{ ++ struct adm_async_desc *async_desc = container_of(vd, ++ struct adm_async_desc, vd); ++ ++ dma_unmap_single(async_desc->adev->dev, async_desc->dma_addr, ++ async_desc->dma_len, DMA_TO_DEVICE); ++ kfree(async_desc->cpl); ++ kfree(async_desc); ++} ++ ++static void adm_channel_init(struct adm_device *adev, struct adm_chan *achan, ++ u32 index) ++{ ++ achan->id = index; ++ achan->adev = adev; ++ ++ vchan_init(&achan->vc, &adev->common); ++ achan->vc.desc_free = adm_dma_free_desc; ++} ++ ++static int adm_dma_probe(struct platform_device *pdev) ++{ ++ struct adm_device *adev; ++ int ret; ++ u32 i; ++ ++ adev = devm_kzalloc(&pdev->dev, sizeof(*adev), GFP_KERNEL); ++ if (!adev) ++ return -ENOMEM; ++ ++ adev->dev = &pdev->dev; ++ ++ adev->regs = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(adev->regs)) ++ return PTR_ERR(adev->regs); ++ ++ adev->irq = platform_get_irq(pdev, 0); ++ if (adev->irq < 0) ++ return adev->irq; ++ ++ ret = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &adev->ee); ++ if (ret) { ++ dev_err(adev->dev, "Execution environment unspecified\n"); ++ return ret; ++ } ++ ++ adev->core_clk = devm_clk_get(adev->dev, "core"); ++ if (IS_ERR(adev->core_clk)) ++ return PTR_ERR(adev->core_clk); ++ ++ adev->iface_clk = devm_clk_get(adev->dev, "iface"); ++ if (IS_ERR(adev->iface_clk)) ++ return PTR_ERR(adev->iface_clk); ++ ++ adev->clk_reset = devm_reset_control_get_exclusive(&pdev->dev, "clk"); ++ if (IS_ERR(adev->clk_reset)) { ++ dev_err(adev->dev, "failed to get ADM0 reset\n"); ++ return PTR_ERR(adev->clk_reset); ++ } ++ ++ adev->c0_reset = devm_reset_control_get_exclusive(&pdev->dev, "c0"); ++ if (IS_ERR(adev->c0_reset)) { ++ dev_err(adev->dev, "failed to get ADM0 C0 reset\n"); ++ return PTR_ERR(adev->c0_reset); ++ } ++ ++ adev->c1_reset = devm_reset_control_get_exclusive(&pdev->dev, "c1"); ++ if (IS_ERR(adev->c1_reset)) { ++ dev_err(adev->dev, "failed to get ADM0 C1 reset\n"); ++ return PTR_ERR(adev->c1_reset); ++ } ++ ++ adev->c2_reset = devm_reset_control_get_exclusive(&pdev->dev, "c2"); ++ if (IS_ERR(adev->c2_reset)) { ++ dev_err(adev->dev, "failed to get ADM0 C2 reset\n"); ++ return PTR_ERR(adev->c2_reset); ++ } ++ ++ ret = clk_prepare_enable(adev->core_clk); ++ if (ret) { ++ dev_err(adev->dev, "failed to prepare/enable core clock\n"); ++ return ret; ++ } ++ ++ ret = clk_prepare_enable(adev->iface_clk); ++ if (ret) { ++ dev_err(adev->dev, "failed to prepare/enable iface clock\n"); ++ goto err_disable_core_clk; ++ } ++ ++ reset_control_assert(adev->clk_reset); ++ reset_control_assert(adev->c0_reset); ++ reset_control_assert(adev->c1_reset); ++ reset_control_assert(adev->c2_reset); ++ ++ udelay(2); ++ ++ reset_control_deassert(adev->clk_reset); ++ reset_control_deassert(adev->c0_reset); ++ reset_control_deassert(adev->c1_reset); ++ reset_control_deassert(adev->c2_reset); ++ ++ adev->channels = devm_kcalloc(adev->dev, ADM_MAX_CHANNELS, ++ sizeof(*adev->channels), GFP_KERNEL); ++ ++ if (!adev->channels) { ++ ret = -ENOMEM; ++ goto err_disable_clks; ++ } ++ ++ /* allocate and initialize channels */ ++ INIT_LIST_HEAD(&adev->common.channels); ++ ++ for (i = 0; i < ADM_MAX_CHANNELS; i++) ++ adm_channel_init(adev, &adev->channels[i], i); ++ ++ /* reset CRCIs */ ++ for (i = 0; i < 16; i++) ++ writel(ADM_CRCI_CTL_RST, adev->regs + ++ ADM_CRCI_CTL(i, adev->ee)); ++ ++ /* configure client interfaces */ ++ writel(ADM_CI_RANGE_START(0x40) | ADM_CI_RANGE_END(0xb0) | ++ ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(0)); ++ writel(ADM_CI_RANGE_START(0x2a) | ADM_CI_RANGE_END(0x2c) | ++ ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(1)); ++ writel(ADM_CI_RANGE_START(0x12) | ADM_CI_RANGE_END(0x28) | ++ ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(2)); ++ writel(ADM_GP_CTL_LP_EN | ADM_GP_CTL_LP_CNT(0xf), ++ adev->regs + ADM_GP_CTL); ++ ++ ret = devm_request_irq(adev->dev, adev->irq, adm_dma_irq, ++ 0, "adm_dma", adev); ++ if (ret) ++ goto err_disable_clks; ++ ++ platform_set_drvdata(pdev, adev); ++ ++ adev->common.dev = adev->dev; ++ adev->common.dev->dma_parms = &adev->dma_parms; ++ ++ /* set capabilities */ ++ dma_cap_zero(adev->common.cap_mask); ++ dma_cap_set(DMA_SLAVE, adev->common.cap_mask); ++ dma_cap_set(DMA_PRIVATE, adev->common.cap_mask); ++ ++ /* initialize dmaengine apis */ ++ adev->common.directions = BIT(DMA_DEV_TO_MEM | DMA_MEM_TO_DEV); ++ adev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; ++ adev->common.src_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ adev->common.dst_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ adev->common.device_free_chan_resources = adm_free_chan; ++ adev->common.device_prep_slave_sg = adm_prep_slave_sg; ++ adev->common.device_issue_pending = adm_issue_pending; ++ adev->common.device_tx_status = adm_tx_status; ++ adev->common.device_terminate_all = adm_terminate_all; ++ adev->common.device_config = adm_slave_config; ++ ++ ret = dma_async_device_register(&adev->common); ++ if (ret) { ++ dev_err(adev->dev, "failed to register dma async device\n"); ++ goto err_disable_clks; ++ } ++ ++ ret = of_dma_controller_register(pdev->dev.of_node, ++ of_dma_xlate_by_chan_id, ++ &adev->common); ++ if (ret) ++ goto err_unregister_dma; ++ ++ return 0; ++ ++err_unregister_dma: ++ dma_async_device_unregister(&adev->common); ++err_disable_clks: ++ clk_disable_unprepare(adev->iface_clk); ++err_disable_core_clk: ++ clk_disable_unprepare(adev->core_clk); ++ ++ return ret; ++} ++ ++static int adm_dma_remove(struct platform_device *pdev) ++{ ++ struct adm_device *adev = platform_get_drvdata(pdev); ++ struct adm_chan *achan; ++ u32 i; ++ ++ of_dma_controller_free(pdev->dev.of_node); ++ dma_async_device_unregister(&adev->common); ++ ++ for (i = 0; i < ADM_MAX_CHANNELS; i++) { ++ achan = &adev->channels[i]; ++ ++ /* mask IRQs for this channel/EE pair */ ++ writel(0, adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee)); ++ ++ tasklet_kill(&adev->channels[i].vc.task); ++ adm_terminate_all(&adev->channels[i].vc.chan); ++ } ++ ++ devm_free_irq(adev->dev, adev->irq, adev); ++ ++ clk_disable_unprepare(adev->core_clk); ++ clk_disable_unprepare(adev->iface_clk); ++ ++ return 0; ++} ++ ++static const struct of_device_id adm_of_match[] = { ++ { .compatible = "qcom,adm", }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, adm_of_match); ++ ++static struct platform_driver adm_dma_driver = { ++ .probe = adm_dma_probe, ++ .remove = adm_dma_remove, ++ .driver = { ++ .name = "adm-dma-engine", ++ .of_match_table = adm_of_match, ++ }, ++}; ++ ++module_platform_driver(adm_dma_driver); ++ ++MODULE_AUTHOR("Andy Gross "); ++MODULE_DESCRIPTION("QCOM ADM DMA engine driver"); ++MODULE_LICENSE("GPL v2"); diff --git a/root/target/linux/ipq806x/patches-5.10/101-5.12-mtd-parsers-Add-Qcom-SMEM-parser.patch b/root/target/linux/ipq806x/patches-5.10/101-5.12-mtd-parsers-Add-Qcom-SMEM-parser.patch new file mode 100755 index 00000000..a78dc82a --- /dev/null +++ b/root/target/linux/ipq806x/patches-5.10/101-5.12-mtd-parsers-Add-Qcom-SMEM-parser.patch @@ -0,0 +1,217 @@ +From 803eb124e1a64e42888542c3444bfe6dac412c7f Mon Sep 17 00:00:00 2001 +From: Manivannan Sadhasivam +Date: Mon, 4 Jan 2021 09:41:35 +0530 +Subject: mtd: parsers: Add Qcom SMEM parser + +NAND based Qualcomm platforms have the partition table populated in the +Shared Memory (SMEM). Hence, add a parser for parsing the partitions +from it. + +Signed-off-by: Manivannan Sadhasivam +Signed-off-by: Miquel Raynal +Link: https://lore.kernel.org/linux-mtd/20210104041137.113075-3-manivannan.sadhasivam@linaro.org +--- + drivers/mtd/parsers/Kconfig | 8 ++ + drivers/mtd/parsers/Makefile | 1 + + drivers/mtd/parsers/qcomsmempart.c | 170 +++++++++++++++++++++++++++++++++++++ + 3 files changed, 179 insertions(+) + create mode 100644 drivers/mtd/parsers/qcomsmempart.c + +--- a/drivers/mtd/parsers/Kconfig ++++ b/drivers/mtd/parsers/Kconfig +@@ -196,6 +196,14 @@ config MTD_REDBOOT_PARTS_READONLY + + endif # MTD_REDBOOT_PARTS + ++config MTD_QCOMSMEM_PARTS ++ tristate "Qualcomm SMEM NAND flash partition parser" ++ depends on MTD_NAND_QCOM || COMPILE_TEST ++ depends on QCOM_SMEM ++ help ++ This provides support for parsing partitions from Shared Memory (SMEM) ++ for NAND flash on Qualcomm platforms. ++ + config MTD_ROUTERBOOT_PARTS + tristate "RouterBoot flash partition parser" + depends on MTD && OF +--- a/drivers/mtd/parsers/Makefile ++++ b/drivers/mtd/parsers/Makefile +@@ -13,4 +13,5 @@ obj-$(CONFIG_MTD_AFS_PARTS) += afs.o + obj-$(CONFIG_MTD_PARSER_TRX) += parser_trx.o + obj-$(CONFIG_MTD_SHARPSL_PARTS) += sharpslpart.o + obj-$(CONFIG_MTD_REDBOOT_PARTS) += redboot.o ++obj-$(CONFIG_MTD_QCOMSMEM_PARTS) += qcomsmempart.o + obj-$(CONFIG_MTD_ROUTERBOOT_PARTS) += routerbootpart.o +--- /dev/null ++++ b/drivers/mtd/parsers/qcomsmempart.c +@@ -0,0 +1,170 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Qualcomm SMEM NAND flash partition parser ++ * ++ * Copyright (C) 2020, Linaro Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define SMEM_AARM_PARTITION_TABLE 9 ++#define SMEM_APPS 0 ++ ++#define SMEM_FLASH_PART_MAGIC1 0x55ee73aa ++#define SMEM_FLASH_PART_MAGIC2 0xe35ebddb ++#define SMEM_FLASH_PTABLE_V3 3 ++#define SMEM_FLASH_PTABLE_V4 4 ++#define SMEM_FLASH_PTABLE_MAX_PARTS_V3 16 ++#define SMEM_FLASH_PTABLE_MAX_PARTS_V4 48 ++#define SMEM_FLASH_PTABLE_HDR_LEN (4 * sizeof(u32)) ++#define SMEM_FLASH_PTABLE_NAME_SIZE 16 ++ ++/** ++ * struct smem_flash_pentry - SMEM Flash partition entry ++ * @name: Name of the partition ++ * @offset: Offset in blocks ++ * @length: Length of the partition in blocks ++ * @attr: Flags for this partition ++ */ ++struct smem_flash_pentry { ++ char name[SMEM_FLASH_PTABLE_NAME_SIZE]; ++ __le32 offset; ++ __le32 length; ++ u8 attr; ++} __packed __aligned(4); ++ ++/** ++ * struct smem_flash_ptable - SMEM Flash partition table ++ * @magic1: Partition table Magic 1 ++ * @magic2: Partition table Magic 2 ++ * @version: Partition table version ++ * @numparts: Number of partitions in this ptable ++ * @pentry: Flash partition entries belonging to this ptable ++ */ ++struct smem_flash_ptable { ++ __le32 magic1; ++ __le32 magic2; ++ __le32 version; ++ __le32 numparts; ++ struct smem_flash_pentry pentry[SMEM_FLASH_PTABLE_MAX_PARTS_V4]; ++} __packed __aligned(4); ++ ++static int parse_qcomsmem_part(struct mtd_info *mtd, ++ const struct mtd_partition **pparts, ++ struct mtd_part_parser_data *data) ++{ ++ struct smem_flash_pentry *pentry; ++ struct smem_flash_ptable *ptable; ++ size_t len = SMEM_FLASH_PTABLE_HDR_LEN; ++ struct mtd_partition *parts; ++ int ret, i, numparts; ++ char *name, *c; ++ ++ pr_debug("Parsing partition table info from SMEM\n"); ++ ptable = qcom_smem_get(SMEM_APPS, SMEM_AARM_PARTITION_TABLE, &len); ++ if (IS_ERR(ptable)) { ++ pr_err("Error reading partition table header\n"); ++ return PTR_ERR(ptable); ++ } ++ ++ /* Verify ptable magic */ ++ if (le32_to_cpu(ptable->magic1) != SMEM_FLASH_PART_MAGIC1 || ++ le32_to_cpu(ptable->magic2) != SMEM_FLASH_PART_MAGIC2) { ++ pr_err("Partition table magic verification failed\n"); ++ return -EINVAL; ++ } ++ ++ /* Ensure that # of partitions is less than the max we have allocated */ ++ numparts = le32_to_cpu(ptable->numparts); ++ if (numparts > SMEM_FLASH_PTABLE_MAX_PARTS_V4) { ++ pr_err("Partition numbers exceed the max limit\n"); ++ return -EINVAL; ++ } ++ ++ /* Find out length of partition data based on table version */ ++ if (le32_to_cpu(ptable->version) <= SMEM_FLASH_PTABLE_V3) { ++ len = SMEM_FLASH_PTABLE_HDR_LEN + SMEM_FLASH_PTABLE_MAX_PARTS_V3 * ++ sizeof(struct smem_flash_pentry); ++ } else if (le32_to_cpu(ptable->version) == SMEM_FLASH_PTABLE_V4) { ++ len = SMEM_FLASH_PTABLE_HDR_LEN + SMEM_FLASH_PTABLE_MAX_PARTS_V4 * ++ sizeof(struct smem_flash_pentry); ++ } else { ++ pr_err("Unknown ptable version (%d)", le32_to_cpu(ptable->version)); ++ return -EINVAL; ++ } ++ ++ /* ++ * Now that the partition table header has been parsed, verified ++ * and the length of the partition table calculated, read the ++ * complete partition table ++ */ ++ ptable = qcom_smem_get(SMEM_APPS, SMEM_AARM_PARTITION_TABLE, &len); ++ if (IS_ERR_OR_NULL(ptable)) { ++ pr_err("Error reading partition table\n"); ++ return PTR_ERR(ptable); ++ } ++ ++ parts = kcalloc(numparts, sizeof(*parts), GFP_KERNEL); ++ if (!parts) ++ return -ENOMEM; ++ ++ for (i = 0; i < numparts; i++) { ++ pentry = &ptable->pentry[i]; ++ if (pentry->name[0] == '\0') ++ continue; ++ ++ name = kstrdup(pentry->name, GFP_KERNEL); ++ if (!name) { ++ ret = -ENOMEM; ++ goto out_free_parts; ++ } ++ ++ /* Convert name to lower case */ ++ for (c = name; *c != '\0'; c++) ++ *c = tolower(*c); ++ ++ parts[i].name = name; ++ parts[i].offset = le32_to_cpu(pentry->offset) * mtd->erasesize; ++ parts[i].mask_flags = pentry->attr; ++ parts[i].size = le32_to_cpu(pentry->length) * mtd->erasesize; ++ pr_debug("%d: %s offs=0x%08x size=0x%08x attr:0x%08x\n", ++ i, pentry->name, le32_to_cpu(pentry->offset), ++ le32_to_cpu(pentry->length), pentry->attr); ++ } ++ ++ pr_debug("SMEM partition table found: ver: %d len: %d\n", ++ le32_to_cpu(ptable->version), numparts); ++ *pparts = parts; ++ ++ return numparts; ++ ++out_free_parts: ++ while (--i >= 0) ++ kfree(parts[i].name); ++ kfree(parts); ++ *pparts = NULL; ++ ++ return ret; ++} ++ ++static const struct of_device_id qcomsmem_of_match_table[] = { ++ { .compatible = "qcom,smem-part" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, qcomsmem_of_match_table); ++ ++static struct mtd_part_parser mtd_parser_qcomsmem = { ++ .parse_fn = parse_qcomsmem_part, ++ .name = "qcomsmem", ++ .of_match_table = qcomsmem_of_match_table, ++}; ++module_mtd_part_parser(mtd_parser_qcomsmem); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_AUTHOR("Manivannan Sadhasivam "); ++MODULE_DESCRIPTION("Qualcomm SMEM NAND flash partition parser"); diff --git a/root/target/linux/ipq806x/patches-5.15/101-dwmac-ipq806x-qsgmii-pcs-all-ch-ctl.patch b/root/target/linux/ipq806x/patches-5.10/101-dwmac-ipq806x-qsgmii-pcs-all-ch-ctl.patch similarity index 97% rename from root/target/linux/ipq806x/patches-5.15/101-dwmac-ipq806x-qsgmii-pcs-all-ch-ctl.patch rename to root/target/linux/ipq806x/patches-5.10/101-dwmac-ipq806x-qsgmii-pcs-all-ch-ctl.patch index 8e9939a4..2210f4e2 100755 --- a/root/target/linux/ipq806x/patches-5.15/101-dwmac-ipq806x-qsgmii-pcs-all-ch-ctl.patch +++ b/root/target/linux/ipq806x/patches-5.10/101-dwmac-ipq806x-qsgmii-pcs-all-ch-ctl.patch @@ -63,7 +63,7 @@ val = stmmac_get_platform_resources(pdev, &stmmac_res); if (val) -@@ -346,6 +388,17 @@ static int ipq806x_gmac_probe(struct pla +@@ -339,6 +381,17 @@ static int ipq806x_gmac_probe(struct pla 0x1ul << QSGMII_PHY_RX_INPUT_EQU_OFFSET | 0x2ul << QSGMII_PHY_CDR_PI_SLEW_OFFSET | 0xCul << QSGMII_PHY_TX_DRV_AMP_OFFSET); diff --git a/root/target/linux/ipq806x/patches-5.15/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch b/root/target/linux/ipq806x/patches-5.10/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch similarity index 100% rename from root/target/linux/ipq806x/patches-5.15/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch rename to root/target/linux/ipq806x/patches-5.10/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch diff --git a/root/target/linux/ipq806x/patches-5.15/103-ARM-dts-qcom-reduce-pci-IO-size-to-64K.patch b/root/target/linux/ipq806x/patches-5.10/103-ARM-dts-qcom-reduce-pci-IO-size-to-64K.patch similarity index 96% rename from root/target/linux/ipq806x/patches-5.15/103-ARM-dts-qcom-reduce-pci-IO-size-to-64K.patch rename to root/target/linux/ipq806x/patches-5.10/103-ARM-dts-qcom-reduce-pci-IO-size-to-64K.patch index 4020d9d2..75b53234 100755 --- a/root/target/linux/ipq806x/patches-5.15/103-ARM-dts-qcom-reduce-pci-IO-size-to-64K.patch +++ b/root/target/linux/ipq806x/patches-5.10/103-ARM-dts-qcom-reduce-pci-IO-size-to-64K.patch @@ -17,7 +17,7 @@ Signed-off-by: Ansuel Smith --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -1088,7 +1088,7 @@ +@@ -1163,7 +1163,7 @@ #address-cells = <3>; #size-cells = <2>; @@ -26,7 +26,7 @@ Signed-off-by: Ansuel Smith 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */ interrupts = ; -@@ -1139,7 +1139,7 @@ +@@ -1214,7 +1214,7 @@ #address-cells = <3>; #size-cells = <2>; @@ -35,7 +35,7 @@ Signed-off-by: Ansuel Smith 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */ interrupts = ; -@@ -1190,7 +1190,7 @@ +@@ -1265,7 +1265,7 @@ #address-cells = <3>; #size-cells = <2>; diff --git a/root/target/linux/ipq806x/patches-5.10/104-1-drivers-thermal-tsens-Add-VER_0-tsens-version.patch b/root/target/linux/ipq806x/patches-5.10/104-1-drivers-thermal-tsens-Add-VER_0-tsens-version.patch new file mode 100755 index 00000000..8627244c --- /dev/null +++ b/root/target/linux/ipq806x/patches-5.10/104-1-drivers-thermal-tsens-Add-VER_0-tsens-version.patch @@ -0,0 +1,285 @@ +From 5c7d1181056feef0b58fb2f556f55e170ba5b479 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Sat, 25 Jul 2020 19:14:59 +0200 +Subject: [PATCH 01/10] drivers: thermal: tsens: Add VER_0 tsens version + +VER_0 is used to describe device based on tsens version before v0.1. +These device are devices based on msm8960 for example apq8064 or +ipq806x. + +Signed-off-by: Ansuel Smith +Reviewed-by: Thara Gopinath +Reported-by: kernel test robot +Reported-by: Dan Carpenter +--- + drivers/thermal/qcom/tsens.c | 150 ++++++++++++++++++++++++++++------- + drivers/thermal/qcom/tsens.h | 4 +- + 2 files changed, 124 insertions(+), 30 deletions(-) + +--- a/drivers/thermal/qcom/tsens.c ++++ b/drivers/thermal/qcom/tsens.c +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -515,6 +516,15 @@ static irqreturn_t tsens_irq_thread(int + dev_dbg(priv->dev, "[%u] %s: no violation: %d\n", + hw_id, __func__, temp); + } ++ ++ if (tsens_version(priv) < VER_0_1) { ++ /* Constraint: There is only 1 interrupt control register for all ++ * 11 temperature sensor. So monitoring more than 1 sensor based ++ * on interrupts will yield inconsistent result. To overcome this ++ * issue we will monitor only sensor 0 which is the master sensor. ++ */ ++ break; ++ } + } + + return IRQ_HANDLED; +@@ -530,6 +540,13 @@ static int tsens_set_trips(void *_sensor + int high_val, low_val, cl_high, cl_low; + u32 hw_id = s->hw_id; + ++ if (tsens_version(priv) < VER_0_1) { ++ /* Pre v0.1 IP had a single register for each type of interrupt ++ * and thresholds ++ */ ++ hw_id = 0; ++ } ++ + dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n", + hw_id, __func__, low, high); + +@@ -584,18 +601,21 @@ int get_temp_tsens_valid(const struct ts + u32 valid; + int ret; + +- ret = regmap_field_read(priv->rf[valid_idx], &valid); +- if (ret) +- return ret; +- while (!valid) { +- /* Valid bit is 0 for 6 AHB clock cycles. +- * At 19.2MHz, 1 AHB clock is ~60ns. +- * We should enter this loop very, very rarely. +- */ +- ndelay(400); ++ /* VER_0 doesn't have VALID bit */ ++ if (tsens_version(priv) >= VER_0_1) { + ret = regmap_field_read(priv->rf[valid_idx], &valid); + if (ret) + return ret; ++ while (!valid) { ++ /* Valid bit is 0 for 6 AHB clock cycles. ++ * At 19.2MHz, 1 AHB clock is ~60ns. ++ * We should enter this loop very, very rarely. ++ */ ++ ndelay(400); ++ ret = regmap_field_read(priv->rf[valid_idx], &valid); ++ if (ret) ++ return ret; ++ } + } + + /* Valid bit is set, OK to read the temperature */ +@@ -608,15 +628,29 @@ int get_temp_common(const struct tsens_s + { + struct tsens_priv *priv = s->priv; + int hw_id = s->hw_id; +- int last_temp = 0, ret; ++ int last_temp = 0, ret, trdy; ++ unsigned long timeout; + +- ret = regmap_field_read(priv->rf[LAST_TEMP_0 + hw_id], &last_temp); +- if (ret) +- return ret; ++ timeout = jiffies + usecs_to_jiffies(TIMEOUT_US); ++ do { ++ if (tsens_version(priv) == VER_0) { ++ ret = regmap_field_read(priv->rf[TRDY], &trdy); ++ if (ret) ++ return ret; ++ if (!trdy) ++ continue; ++ } + +- *temp = code_to_degc(last_temp, s) * 1000; ++ ret = regmap_field_read(priv->rf[LAST_TEMP_0 + hw_id], &last_temp); ++ if (ret) ++ return ret; + +- return 0; ++ *temp = code_to_degc(last_temp, s) * 1000; ++ ++ return 0; ++ } while (time_before(jiffies, timeout)); ++ ++ return -ETIMEDOUT; + } + + #ifdef CONFIG_DEBUG_FS +@@ -738,19 +772,34 @@ int __init init_common(struct tsens_priv + priv->tm_offset = 0x1000; + } + +- res = platform_get_resource(op, IORESOURCE_MEM, 0); +- tm_base = devm_ioremap_resource(dev, res); +- if (IS_ERR(tm_base)) { +- ret = PTR_ERR(tm_base); +- goto err_put_device; ++ if (tsens_version(priv) >= VER_0_1) { ++ res = platform_get_resource(op, IORESOURCE_MEM, 0); ++ tm_base = devm_ioremap_resource(dev, res); ++ if (IS_ERR(tm_base)) { ++ ret = PTR_ERR(tm_base); ++ goto err_put_device; ++ } ++ ++ priv->tm_map = devm_regmap_init_mmio(dev, tm_base, &tsens_config); ++ } else { /* VER_0 share the same gcc regs using a syscon */ ++ struct device *parent = priv->dev->parent; ++ ++ if (parent) ++ priv->tm_map = syscon_node_to_regmap(parent->of_node); + } + +- priv->tm_map = devm_regmap_init_mmio(dev, tm_base, &tsens_config); +- if (IS_ERR(priv->tm_map)) { +- ret = PTR_ERR(priv->tm_map); ++ if (IS_ERR_OR_NULL(priv->tm_map)) { ++ if (!priv->tm_map) ++ ret = -ENODEV; ++ else ++ ret = PTR_ERR(priv->tm_map); + goto err_put_device; + } + ++ /* VER_0 have only tm_map */ ++ if (!priv->srot_map) ++ priv->srot_map = priv->tm_map; ++ + if (tsens_version(priv) > VER_0_1) { + for (i = VER_MAJOR; i <= VER_STEP; i++) { + priv->rf[i] = devm_regmap_field_alloc(dev, priv->srot_map, +@@ -771,6 +820,10 @@ int __init init_common(struct tsens_priv + ret = PTR_ERR(priv->rf[TSENS_EN]); + goto err_put_device; + } ++ /* in VER_0 TSENS need to be explicitly enabled */ ++ if (tsens_version(priv) == VER_0) ++ regmap_field_write(priv->rf[TSENS_EN], 1); ++ + ret = regmap_field_read(priv->rf[TSENS_EN], &enabled); + if (ret) + goto err_put_device; +@@ -793,6 +846,19 @@ int __init init_common(struct tsens_priv + goto err_put_device; + } + ++ priv->rf[TSENS_SW_RST] = ++ devm_regmap_field_alloc(dev, priv->srot_map, priv->fields[TSENS_SW_RST]); ++ if (IS_ERR(priv->rf[TSENS_SW_RST])) { ++ ret = PTR_ERR(priv->rf[TSENS_SW_RST]); ++ goto err_put_device; ++ } ++ ++ priv->rf[TRDY] = devm_regmap_field_alloc(dev, priv->tm_map, priv->fields[TRDY]); ++ if (IS_ERR(priv->rf[TRDY])) { ++ ret = PTR_ERR(priv->rf[TRDY]); ++ goto err_put_device; ++ } ++ + /* This loop might need changes if enum regfield_ids is reordered */ + for (j = LAST_TEMP_0; j <= UP_THRESH_15; j += 16) { + for (i = 0; i < priv->feat->max_sensors; i++) { +@@ -808,7 +874,7 @@ int __init init_common(struct tsens_priv + } + } + +- if (priv->feat->crit_int) { ++ if (priv->feat->crit_int || tsens_version(priv) < VER_0_1) { + /* Loop might need changes if enum regfield_ids is reordered */ + for (j = CRITICAL_STATUS_0; j <= CRIT_THRESH_15; j += 16) { + for (i = 0; i < priv->feat->max_sensors; i++) { +@@ -846,7 +912,11 @@ int __init init_common(struct tsens_priv + } + + spin_lock_init(&priv->ul_lock); +- tsens_enable_irq(priv); ++ ++ /* VER_0 interrupt doesn't need to be enabled */ ++ if (tsens_version(priv) >= VER_0_1) ++ tsens_enable_irq(priv); ++ + tsens_debug_init(op); + + err_put_device: +@@ -945,10 +1015,19 @@ static int tsens_register_irq(struct tse + if (irq == -ENXIO) + ret = 0; + } else { +- ret = devm_request_threaded_irq(&pdev->dev, irq, +- NULL, thread_fn, +- IRQF_ONESHOT, +- dev_name(&pdev->dev), priv); ++ /* VER_0 interrupt is TRIGGER_RISING, VER_0_1 and up is ONESHOT */ ++ if (tsens_version(priv) == VER_0) ++ ret = devm_request_threaded_irq(&pdev->dev, irq, ++ thread_fn, NULL, ++ IRQF_TRIGGER_RISING, ++ dev_name(&pdev->dev), ++ priv); ++ else ++ ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, ++ thread_fn, IRQF_ONESHOT, ++ dev_name(&pdev->dev), ++ priv); ++ + if (ret) + dev_err(&pdev->dev, "%s: failed to get irq\n", + __func__); +@@ -977,6 +1056,19 @@ static int tsens_register(struct tsens_p + priv->ops->enable(priv, i); + } + ++ /* VER_0 require to set MIN and MAX THRESH ++ * These 2 regs are set using the: ++ * - CRIT_THRESH_0 for MAX THRESH hardcoded to 120°C ++ * - CRIT_THRESH_1 for MIN THRESH hardcoded to 0°C ++ */ ++ if (tsens_version(priv) < VER_0_1) { ++ regmap_field_write(priv->rf[CRIT_THRESH_0], ++ tsens_mC_to_hw(priv->sensor, 120000)); ++ ++ regmap_field_write(priv->rf[CRIT_THRESH_1], ++ tsens_mC_to_hw(priv->sensor, 0)); ++ } ++ + ret = tsens_register_irq(priv, "uplow", tsens_irq_thread); + if (ret < 0) + return ret; +--- a/drivers/thermal/qcom/tsens.h ++++ b/drivers/thermal/qcom/tsens.h +@@ -13,6 +13,7 @@ + #define CAL_DEGC_PT2 120 + #define SLOPE_FACTOR 1000 + #define SLOPE_DEFAULT 3200 ++#define TIMEOUT_US 100 + #define THRESHOLD_MAX_ADC_CODE 0x3ff + #define THRESHOLD_MIN_ADC_CODE 0x0 + +@@ -25,7 +26,8 @@ struct tsens_priv; + + /* IP version numbers in ascending order */ + enum tsens_ver { +- VER_0_1 = 0, ++ VER_0 = 0, ++ VER_0_1, + VER_1_X, + VER_2_X, + }; diff --git a/root/target/linux/ipq806x/patches-5.10/104-2-drivers-thermal-tsens-Don-t-hardcode-sensor-slope.patch b/root/target/linux/ipq806x/patches-5.10/104-2-drivers-thermal-tsens-Don-t-hardcode-sensor-slope.patch new file mode 100755 index 00000000..109f524b --- /dev/null +++ b/root/target/linux/ipq806x/patches-5.10/104-2-drivers-thermal-tsens-Don-t-hardcode-sensor-slope.patch @@ -0,0 +1,28 @@ +From efa0d50a6c5ec7619371dfe4d3e6ca54b73787d5 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Wed, 25 Nov 2020 16:47:21 +0100 +Subject: [PATCH 02/10] drivers: thermal: tsens: Don't hardcode sensor slope + +Function compute_intercept_slope hardcode the sensor slope to +SLOPE_DEFAULT. Change this and use the default value only if a slope is +not defined. This is needed for tsens VER_0 that has a hardcoded slope +table. + +Signed-off-by: Ansuel Smith +Reviewed-by: Thara Gopinath +--- + drivers/thermal/qcom/tsens.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/thermal/qcom/tsens.c ++++ b/drivers/thermal/qcom/tsens.c +@@ -86,7 +86,8 @@ void compute_intercept_slope(struct tsen + "%s: sensor%d - data_point1:%#x data_point2:%#x\n", + __func__, i, p1[i], p2[i]); + +- priv->sensor[i].slope = SLOPE_DEFAULT; ++ if (!priv->sensor[i].slope) ++ priv->sensor[i].slope = SLOPE_DEFAULT; + if (mode == TWO_PT_CALIB) { + /* + * slope (m) = adc_code2 - adc_code1 (y2 - y1)/ diff --git a/root/target/linux/ipq806x/patches-5.10/104-3-drivers-thermal-tsens-Convert-msm8960-to-reg_field.patch b/root/target/linux/ipq806x/patches-5.10/104-3-drivers-thermal-tsens-Convert-msm8960-to-reg_field.patch new file mode 100755 index 00000000..bf378107 --- /dev/null +++ b/root/target/linux/ipq806x/patches-5.10/104-3-drivers-thermal-tsens-Convert-msm8960-to-reg_field.patch @@ -0,0 +1,119 @@ +From 6bac2e2fa36c2d7c304768a689d8b73155b90aa2 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Wed, 25 Nov 2020 17:15:51 +0100 +Subject: [PATCH 03/10] drivers: thermal: tsens: Convert msm8960 to reg_field + +Convert msm9860 driver to reg_field to use the init_common +function. + +Signed-off-by: Ansuel Smith +Acked-by: Thara Gopinath +--- + drivers/thermal/qcom/tsens-8960.c | 80 ++++++++++++++++++++++++++++++- + 1 file changed, 79 insertions(+), 1 deletion(-) + +--- a/drivers/thermal/qcom/tsens-8960.c ++++ b/drivers/thermal/qcom/tsens-8960.c +@@ -51,11 +51,22 @@ + #define MIN_LIMIT_TH 0x0 + #define MAX_LIMIT_TH 0xff + +-#define S0_STATUS_ADDR 0x3628 + #define INT_STATUS_ADDR 0x363c + #define TRDY_MASK BIT(7) + #define TIMEOUT_US 100 + ++#define S0_STATUS_OFF 0x3628 ++#define S1_STATUS_OFF 0x362c ++#define S2_STATUS_OFF 0x3630 ++#define S3_STATUS_OFF 0x3634 ++#define S4_STATUS_OFF 0x3638 ++#define S5_STATUS_OFF 0x3664 /* Sensors 5-10 found on apq8064/msm8960 */ ++#define S6_STATUS_OFF 0x3668 ++#define S7_STATUS_OFF 0x366c ++#define S8_STATUS_OFF 0x3670 ++#define S9_STATUS_OFF 0x3674 ++#define S10_STATUS_OFF 0x3678 ++ + static int suspend_8960(struct tsens_priv *priv) + { + int ret; +@@ -269,6 +280,71 @@ static int get_temp_8960(const struct ts + return -ETIMEDOUT; + } + ++static struct tsens_features tsens_8960_feat = { ++ .ver_major = VER_0, ++ .crit_int = 0, ++ .adc = 1, ++ .srot_split = 0, ++ .max_sensors = 11, ++}; ++ ++static const struct reg_field tsens_8960_regfields[MAX_REGFIELDS] = { ++ /* ----- SROT ------ */ ++ /* No VERSION information */ ++ ++ /* CNTL */ ++ [TSENS_EN] = REG_FIELD(CNTL_ADDR, 0, 0), ++ [TSENS_SW_RST] = REG_FIELD(CNTL_ADDR, 1, 1), ++ /* 8960 has 5 sensors, 8660 has 11, we only handle 5 */ ++ [SENSOR_EN] = REG_FIELD(CNTL_ADDR, 3, 7), ++ ++ /* ----- TM ------ */ ++ /* INTERRUPT ENABLE */ ++ /* NO INTERRUPT ENABLE */ ++ ++ /* Single UPPER/LOWER TEMPERATURE THRESHOLD for all sensors */ ++ [LOW_THRESH_0] = REG_FIELD(THRESHOLD_ADDR, 0, 7), ++ [UP_THRESH_0] = REG_FIELD(THRESHOLD_ADDR, 8, 15), ++ /* MIN_THRESH_0 and MAX_THRESH_0 are not present in the regfield ++ * Recycle CRIT_THRESH_0 and 1 to set the required regs to hardcoded temp ++ * MIN_THRESH_0 -> CRIT_THRESH_1 ++ * MAX_THRESH_0 -> CRIT_THRESH_0 ++ */ ++ [CRIT_THRESH_1] = REG_FIELD(THRESHOLD_ADDR, 16, 23), ++ [CRIT_THRESH_0] = REG_FIELD(THRESHOLD_ADDR, 24, 31), ++ ++ /* UPPER/LOWER INTERRUPT [CLEAR/STATUS] */ ++ /* 1 == clear, 0 == normal operation */ ++ [LOW_INT_CLEAR_0] = REG_FIELD(CNTL_ADDR, 9, 9), ++ [UP_INT_CLEAR_0] = REG_FIELD(CNTL_ADDR, 10, 10), ++ ++ /* NO CRITICAL INTERRUPT SUPPORT on 8960 */ ++ ++ /* Sn_STATUS */ ++ [LAST_TEMP_0] = REG_FIELD(S0_STATUS_OFF, 0, 7), ++ [LAST_TEMP_1] = REG_FIELD(S1_STATUS_OFF, 0, 7), ++ [LAST_TEMP_2] = REG_FIELD(S2_STATUS_OFF, 0, 7), ++ [LAST_TEMP_3] = REG_FIELD(S3_STATUS_OFF, 0, 7), ++ [LAST_TEMP_4] = REG_FIELD(S4_STATUS_OFF, 0, 7), ++ [LAST_TEMP_5] = REG_FIELD(S5_STATUS_OFF, 0, 7), ++ [LAST_TEMP_6] = REG_FIELD(S6_STATUS_OFF, 0, 7), ++ [LAST_TEMP_7] = REG_FIELD(S7_STATUS_OFF, 0, 7), ++ [LAST_TEMP_8] = REG_FIELD(S8_STATUS_OFF, 0, 7), ++ [LAST_TEMP_9] = REG_FIELD(S9_STATUS_OFF, 0, 7), ++ [LAST_TEMP_10] = REG_FIELD(S10_STATUS_OFF, 0, 7), ++ ++ /* No VALID field on 8960 */ ++ /* TSENS_INT_STATUS bits: 1 == threshold violated */ ++ [MIN_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 0, 0), ++ [LOWER_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 1, 1), ++ [UPPER_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 2, 2), ++ /* No CRITICAL field on 8960 */ ++ [MAX_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 3, 3), ++ ++ /* TRDY: 1=ready, 0=in progress */ ++ [TRDY] = REG_FIELD(INT_STATUS_ADDR, 7, 7), ++}; ++ + static const struct tsens_ops ops_8960 = { + .init = init_8960, + .calibrate = calibrate_8960, +@@ -282,4 +358,6 @@ static const struct tsens_ops ops_8960 = + struct tsens_plat_data data_8960 = { + .num_sensors = 11, + .ops = &ops_8960, ++ .feat = &tsens_8960_feat, ++ .fields = tsens_8960_regfields, + }; diff --git a/root/target/linux/ipq806x/patches-5.10/104-4-drivers-thermal-tsens-Use-init_common-for-msm8960.patch b/root/target/linux/ipq806x/patches-5.10/104-4-drivers-thermal-tsens-Use-init_common-for-msm8960.patch new file mode 100755 index 00000000..ae8a52c1 --- /dev/null +++ b/root/target/linux/ipq806x/patches-5.10/104-4-drivers-thermal-tsens-Use-init_common-for-msm8960.patch @@ -0,0 +1,81 @@ +From c04f98a496929f75d75c65115d5717423c3d0634 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Wed, 25 Nov 2020 17:16:36 +0100 +Subject: [PATCH 04/10] drivers: thermal: tsens: Use init_common for msm8960 + +Use init_common and drop custom init for msm8960. + +Signed-off-by: Ansuel Smith +Reviewed-by: Thara Gopinath +--- + drivers/thermal/qcom/tsens-8960.c | 52 +------------------------------ + 1 file changed, 1 insertion(+), 51 deletions(-) + +--- a/drivers/thermal/qcom/tsens-8960.c ++++ b/drivers/thermal/qcom/tsens-8960.c +@@ -173,56 +173,6 @@ static void disable_8960(struct tsens_pr + regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl); + } + +-static int init_8960(struct tsens_priv *priv) +-{ +- int ret, i; +- u32 reg_cntl; +- +- priv->tm_map = dev_get_regmap(priv->dev, NULL); +- if (!priv->tm_map) +- return -ENODEV; +- +- /* +- * The status registers for each sensor are discontiguous +- * because some SoCs have 5 sensors while others have more +- * but the control registers stay in the same place, i.e +- * directly after the first 5 status registers. +- */ +- for (i = 0; i < priv->num_sensors; i++) { +- if (i >= 5) +- priv->sensor[i].status = S0_STATUS_ADDR + 40; +- priv->sensor[i].status += i * 4; +- } +- +- reg_cntl = SW_RST; +- ret = regmap_update_bits(priv->tm_map, CNTL_ADDR, SW_RST, reg_cntl); +- if (ret) +- return ret; +- +- if (priv->num_sensors > 1) { +- reg_cntl |= SLP_CLK_ENA | (MEASURE_PERIOD << 18); +- reg_cntl &= ~SW_RST; +- ret = regmap_update_bits(priv->tm_map, CONFIG_ADDR, +- CONFIG_MASK, CONFIG); +- } else { +- reg_cntl |= SLP_CLK_ENA_8660 | (MEASURE_PERIOD << 16); +- reg_cntl &= ~CONFIG_MASK_8660; +- reg_cntl |= CONFIG_8660 << CONFIG_SHIFT_8660; +- } +- +- reg_cntl |= GENMASK(priv->num_sensors - 1, 0) << SENSOR0_SHIFT; +- ret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl); +- if (ret) +- return ret; +- +- reg_cntl |= EN; +- ret = regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl); +- if (ret) +- return ret; +- +- return 0; +-} +- + static int calibrate_8960(struct tsens_priv *priv) + { + int i; +@@ -346,7 +296,7 @@ static const struct reg_field tsens_8960 + }; + + static const struct tsens_ops ops_8960 = { +- .init = init_8960, ++ .init = init_common, + .calibrate = calibrate_8960, + .get_temp = get_temp_8960, + .enable = enable_8960, diff --git a/root/target/linux/ipq806x/patches-5.10/104-5-drivers-thermal-tsens-Fix-bug-in-sensor-enable-for-m.patch b/root/target/linux/ipq806x/patches-5.10/104-5-drivers-thermal-tsens-Fix-bug-in-sensor-enable-for-m.patch new file mode 100755 index 00000000..7b01a67d --- /dev/null +++ b/root/target/linux/ipq806x/patches-5.10/104-5-drivers-thermal-tsens-Fix-bug-in-sensor-enable-for-m.patch @@ -0,0 +1,66 @@ +From b3e8bd33b84a6b6c863bd1733bd15b5f1483b8ab Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Wed, 25 Nov 2020 17:06:55 +0100 +Subject: [PATCH 05/10] drivers: thermal: tsens: Fix bug in sensor enable for + msm8960 + +Device based on tsens VER_0 contains a hardware bug that results in some +problem with sensor enablement. Sensor id 6-11 can't be enabled +selectively and all of them must be enabled in one step. + +Signed-off-by: Ansuel Smith +Acked-by: Thara Gopinath +--- + drivers/thermal/qcom/tsens-8960.c | 23 ++++++++++++++++++++--- + 1 file changed, 20 insertions(+), 3 deletions(-) + +--- a/drivers/thermal/qcom/tsens-8960.c ++++ b/drivers/thermal/qcom/tsens-8960.c +@@ -27,9 +27,9 @@ + #define EN BIT(0) + #define SW_RST BIT(1) + #define SENSOR0_EN BIT(3) ++#define MEASURE_PERIOD BIT(18) + #define SLP_CLK_ENA BIT(26) + #define SLP_CLK_ENA_8660 BIT(24) +-#define MEASURE_PERIOD 1 + #define SENSOR0_SHIFT 3 + + /* INT_STATUS_ADDR bitmasks */ +@@ -126,17 +126,34 @@ static int resume_8960(struct tsens_priv + static int enable_8960(struct tsens_priv *priv, int id) + { + int ret; +- u32 reg, mask; ++ u32 reg, mask = BIT(id); + + ret = regmap_read(priv->tm_map, CNTL_ADDR, ®); + if (ret) + return ret; + +- mask = BIT(id + SENSOR0_SHIFT); ++ /* HARDWARE BUG: ++ * On platforms with more than 6 sensors, all remaining sensors ++ * must be enabled together, otherwise undefined results are expected. ++ * (Sensor 6-7 disabled, Sensor 3 disabled...) In the original driver, ++ * all the sensors are enabled in one step hence this bug is not ++ * triggered. ++ */ ++ if (id > 5) ++ mask = GENMASK(10, 6); ++ ++ mask <<= SENSOR0_SHIFT; ++ ++ /* Sensors already enabled. Skip. */ ++ if ((reg & mask) == mask) ++ return 0; ++ + ret = regmap_write(priv->tm_map, CNTL_ADDR, reg | SW_RST); + if (ret) + return ret; + ++ reg |= MEASURE_PERIOD; ++ + if (priv->num_sensors > 1) + reg |= mask | SLP_CLK_ENA | EN; + else diff --git a/root/target/linux/ipq806x/patches-5.10/104-6-drivers-thermal-tsens-Replace-custom-8960-apis-with-.patch b/root/target/linux/ipq806x/patches-5.10/104-6-drivers-thermal-tsens-Replace-custom-8960-apis-with-.patch new file mode 100755 index 00000000..a82f5969 --- /dev/null +++ b/root/target/linux/ipq806x/patches-5.10/104-6-drivers-thermal-tsens-Replace-custom-8960-apis-with-.patch @@ -0,0 +1,109 @@ +From 1ff9f982051759e0387e8c7e793b49c48eae291d Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Wed, 25 Nov 2020 17:11:05 +0100 +Subject: [PATCH 06/10] drivers: thermal: tsens: Replace custom 8960 apis with + generic apis + +Rework calibrate function to use common function. Derive the offset from +a missing hardcoded slope table and the data from the nvmem calib +efuses. +Drop custom get_temp function and use generic api. + +Signed-off-by: Ansuel Smith +Acked-by: Thara Gopinath +--- + drivers/thermal/qcom/tsens-8960.c | 56 +++++++++---------------------- + 1 file changed, 15 insertions(+), 41 deletions(-) + +--- a/drivers/thermal/qcom/tsens-8960.c ++++ b/drivers/thermal/qcom/tsens-8960.c +@@ -67,6 +67,13 @@ + #define S9_STATUS_OFF 0x3674 + #define S10_STATUS_OFF 0x3678 + ++/* Original slope - 200 to compensate mC to C inaccuracy */ ++static u32 tsens_msm8960_slope[] = { ++ 976, 976, 954, 976, ++ 911, 932, 932, 999, ++ 932, 999, 932 ++ }; ++ + static int suspend_8960(struct tsens_priv *priv) + { + int ret; +@@ -194,9 +201,7 @@ static int calibrate_8960(struct tsens_p + { + int i; + char *data; +- +- ssize_t num_read = priv->num_sensors; +- struct tsens_sensor *s = priv->sensor; ++ u32 p1[11]; + + data = qfprom_read(priv->dev, "calib"); + if (IS_ERR(data)) +@@ -204,49 +209,18 @@ static int calibrate_8960(struct tsens_p + if (IS_ERR(data)) + return PTR_ERR(data); + +- for (i = 0; i < num_read; i++, s++) +- s->offset = data[i]; ++ for (i = 0; i < priv->num_sensors; i++) { ++ p1[i] = data[i]; ++ priv->sensor[i].slope = tsens_msm8960_slope[i]; ++ } ++ ++ compute_intercept_slope(priv, p1, NULL, ONE_PT_CALIB); + + kfree(data); + + return 0; + } + +-/* Temperature on y axis and ADC-code on x-axis */ +-static inline int code_to_mdegC(u32 adc_code, const struct tsens_sensor *s) +-{ +- int slope, offset; +- +- slope = thermal_zone_get_slope(s->tzd); +- offset = CAL_MDEGC - slope * s->offset; +- +- return adc_code * slope + offset; +-} +- +-static int get_temp_8960(const struct tsens_sensor *s, int *temp) +-{ +- int ret; +- u32 code, trdy; +- struct tsens_priv *priv = s->priv; +- unsigned long timeout; +- +- timeout = jiffies + usecs_to_jiffies(TIMEOUT_US); +- do { +- ret = regmap_read(priv->tm_map, INT_STATUS_ADDR, &trdy); +- if (ret) +- return ret; +- if (!(trdy & TRDY_MASK)) +- continue; +- ret = regmap_read(priv->tm_map, s->status, &code); +- if (ret) +- return ret; +- *temp = code_to_mdegC(code, s); +- return 0; +- } while (time_before(jiffies, timeout)); +- +- return -ETIMEDOUT; +-} +- + static struct tsens_features tsens_8960_feat = { + .ver_major = VER_0, + .crit_int = 0, +@@ -315,7 +289,7 @@ static const struct reg_field tsens_8960 + static const struct tsens_ops ops_8960 = { + .init = init_common, + .calibrate = calibrate_8960, +- .get_temp = get_temp_8960, ++ .get_temp = get_temp_common, + .enable = enable_8960, + .disable = disable_8960, + .suspend = suspend_8960, diff --git a/root/target/linux/ipq806x/patches-5.10/104-7-drivers-thermal-tsens-Drop-unused-define-for-msm8960.patch b/root/target/linux/ipq806x/patches-5.10/104-7-drivers-thermal-tsens-Drop-unused-define-for-msm8960.patch new file mode 100755 index 00000000..77ca3cfe --- /dev/null +++ b/root/target/linux/ipq806x/patches-5.10/104-7-drivers-thermal-tsens-Drop-unused-define-for-msm8960.patch @@ -0,0 +1,65 @@ +From 5716a61239c6ac9ceb137e825e93c3aea06c4634 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Fri, 19 Mar 2021 00:48:23 +0100 +Subject: [PATCH 07/10] drivers: thermal: tsens: Drop unused define for msm8960 + +Drop unused define for msm8960 replaced by generic api and reg_field. + +Signed-off-by: Ansuel Smith +Reviewed-by: Thara Gopinath +--- + drivers/thermal/qcom/tsens-8960.c | 24 +----------------------- + 1 file changed, 1 insertion(+), 23 deletions(-) + +--- a/drivers/thermal/qcom/tsens-8960.c ++++ b/drivers/thermal/qcom/tsens-8960.c +@@ -10,8 +10,6 @@ + #include + #include "tsens.h" + +-#define CAL_MDEGC 30000 +- + #define CONFIG_ADDR 0x3640 + #define CONFIG_ADDR_8660 0x3620 + /* CONFIG_ADDR bitmasks */ +@@ -21,39 +19,19 @@ + #define CONFIG_SHIFT_8660 28 + #define CONFIG_MASK_8660 (3 << CONFIG_SHIFT_8660) + +-#define STATUS_CNTL_ADDR_8064 0x3660 + #define CNTL_ADDR 0x3620 + /* CNTL_ADDR bitmasks */ + #define EN BIT(0) + #define SW_RST BIT(1) +-#define SENSOR0_EN BIT(3) ++ + #define MEASURE_PERIOD BIT(18) + #define SLP_CLK_ENA BIT(26) + #define SLP_CLK_ENA_8660 BIT(24) + #define SENSOR0_SHIFT 3 + +-/* INT_STATUS_ADDR bitmasks */ +-#define MIN_STATUS_MASK BIT(0) +-#define LOWER_STATUS_CLR BIT(1) +-#define UPPER_STATUS_CLR BIT(2) +-#define MAX_STATUS_MASK BIT(3) +- + #define THRESHOLD_ADDR 0x3624 +-/* THRESHOLD_ADDR bitmasks */ +-#define THRESHOLD_MAX_LIMIT_SHIFT 24 +-#define THRESHOLD_MIN_LIMIT_SHIFT 16 +-#define THRESHOLD_UPPER_LIMIT_SHIFT 8 +-#define THRESHOLD_LOWER_LIMIT_SHIFT 0 +- +-/* Initial temperature threshold values */ +-#define LOWER_LIMIT_TH 0x50 +-#define UPPER_LIMIT_TH 0xdf +-#define MIN_LIMIT_TH 0x0 +-#define MAX_LIMIT_TH 0xff + + #define INT_STATUS_ADDR 0x363c +-#define TRDY_MASK BIT(7) +-#define TIMEOUT_US 100 + + #define S0_STATUS_OFF 0x3628 + #define S1_STATUS_OFF 0x362c diff --git a/root/target/linux/ipq806x/patches-5.10/104-8-drivers-thermal-tsens-Add-support-for-ipq8064-tsens.patch b/root/target/linux/ipq806x/patches-5.10/104-8-drivers-thermal-tsens-Add-support-for-ipq8064-tsens.patch new file mode 100755 index 00000000..127abaef --- /dev/null +++ b/root/target/linux/ipq806x/patches-5.10/104-8-drivers-thermal-tsens-Add-support-for-ipq8064-tsens.patch @@ -0,0 +1,26 @@ +From 0d0c22a59bf2672b57e23da9a9ea743e91b71f54 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Sat, 25 Jul 2020 19:55:57 +0200 +Subject: [PATCH 08/10] drivers: thermal: tsens: Add support for ipq8064-tsens + +Add support for tsens present in ipq806x SoCs based on generic msm8960 +tsens driver. + +Signed-off-by: Ansuel Smith +Reviewed-by: Thara Gopinath +--- + drivers/thermal/qcom/tsens.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/thermal/qcom/tsens.c ++++ b/drivers/thermal/qcom/tsens.c +@@ -968,6 +968,9 @@ static SIMPLE_DEV_PM_OPS(tsens_pm_ops, t + + static const struct of_device_id tsens_table[] = { + { ++ .compatible = "qcom,ipq8064-tsens", ++ .data = &data_8960, ++ }, { + .compatible = "qcom,msm8916-tsens", + .data = &data_8916, + }, { diff --git a/root/target/linux/ipq806x/patches-5.10/104-9-dt-bindings-thermal-tsens-Document-ipq8064-bindings.patch b/root/target/linux/ipq806x/patches-5.10/104-9-dt-bindings-thermal-tsens-Document-ipq8064-bindings.patch new file mode 100755 index 00000000..38210686 --- /dev/null +++ b/root/target/linux/ipq806x/patches-5.10/104-9-dt-bindings-thermal-tsens-Document-ipq8064-bindings.patch @@ -0,0 +1,112 @@ +From ac369071920d427dd484cf74cddba2774bba45f5 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Thu, 9 Jul 2020 22:35:54 +0200 +Subject: [PATCH 09/10] dt-bindings: thermal: tsens: Document ipq8064 bindings + +Document the use of bindings used for msm8960 tsens based devices. +msm8960 use the same gcc regs and is set as a child of the qcom gcc. + +Signed-off-by: Ansuel Smith +Reviewed-by: Rob Herring +--- + .../bindings/thermal/qcom-tsens.yaml | 56 ++++++++++++++++--- + 1 file changed, 48 insertions(+), 8 deletions(-) + +--- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml ++++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +@@ -19,6 +19,11 @@ description: | + properties: + compatible: + oneOf: ++ - description: msm9860 TSENS based ++ items: ++ - enum: ++ - qcom,ipq8064-tsens ++ + - description: v0.1 of TSENS + items: + - enum: +@@ -73,7 +78,9 @@ properties: + maxItems: 2 + items: + - const: calib +- - const: calib_sel ++ - enum: ++ - calib_backup ++ - calib_sel + + "#qcom,sensors": + description: +@@ -88,12 +95,20 @@ properties: + Number of cells required to uniquely identify the thermal sensors. Since + we have multiple sensors this is set to 1 + ++required: ++ - compatible ++ - interrupts ++ - interrupt-names ++ - "#thermal-sensor-cells" ++ - "#qcom,sensors" ++ + allOf: + - if: + properties: + compatible: + contains: + enum: ++ - qcom,ipq8064-tsens + - qcom,msm8916-tsens + - qcom,msm8974-tsens + - qcom,msm8976-tsens +@@ -114,19 +129,44 @@ allOf: + interrupt-names: + minItems: 2 + +-required: +- - compatible +- - reg +- - "#qcom,sensors" +- - interrupts +- - interrupt-names +- - "#thermal-sensor-cells" ++ - if: ++ properties: ++ compatible: ++ contains: ++ enum: ++ - qcom,tsens-v0_1 ++ - qcom,tsens-v1 ++ - qcom,tsens-v2 ++ ++ then: ++ required: ++ - reg + + additionalProperties: false + + examples: + - | + #include ++ // Example msm9860 based SoC (ipq8064): ++ gcc: clock-controller { ++ ++ /* ... */ ++ ++ tsens: thermal-sensor { ++ compatible = "qcom,ipq8064-tsens"; ++ ++ nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; ++ nvmem-cell-names = "calib", "calib_backup"; ++ interrupts = ; ++ interrupt-names = "uplow"; ++ ++ #qcom,sensors = <11>; ++ #thermal-sensor-cells = <1>; ++ }; ++ }; ++ ++ - | ++ #include + // Example 1 (legacy: for pre v1 IP): + tsens1: thermal-sensor@900000 { + compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; diff --git a/root/target/linux/ipq806x/patches-5.10/105-10-drivers-thermal-tsens-Fix-wrong-slope-on-msm-8960.patch b/root/target/linux/ipq806x/patches-5.10/105-10-drivers-thermal-tsens-Fix-wrong-slope-on-msm-8960.patch new file mode 100755 index 00000000..6cdc0b26 --- /dev/null +++ b/root/target/linux/ipq806x/patches-5.10/105-10-drivers-thermal-tsens-Fix-wrong-slope-on-msm-8960.patch @@ -0,0 +1,32 @@ +From 68e720ed73c8f038c8c500e4c49c1e65a993a448 Mon Sep 17 00:00:00 2001 +From: Ansuel Smith +Date: Tue, 6 Apr 2021 04:45:31 +0200 +Subject: [PATCH 10/10] drivers: thermal: tsens: Fix wrong slope on msm-8960 + +Some user using some stats with the old legacy implementation and the +new implementation using the compute_intercept_slope reported an offset +of 3C. Fix the slope table to reflect the original temp. + +Signed-off-by: Ansuel Smith +--- + drivers/thermal/qcom/tsens-8960.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/thermal/qcom/tsens-8960.c ++++ b/drivers/thermal/qcom/tsens-8960.c +@@ -45,11 +45,11 @@ + #define S9_STATUS_OFF 0x3674 + #define S10_STATUS_OFF 0x3678 + +-/* Original slope - 200 to compensate mC to C inaccuracy */ ++/* Original slope - 350 to compensate mC to C inaccuracy */ + static u32 tsens_msm8960_slope[] = { +- 976, 976, 954, 976, +- 911, 932, 932, 999, +- 932, 999, 932 ++ 826, 826, 804, 826, ++ 761, 782, 782, 849, ++ 782, 849, 782 + }; + + static int suspend_8960(struct tsens_priv *priv) diff --git a/root/target/linux/ipq806x/patches-5.15/107-1-thermal-qcom-tsens-init-debugfs-only-with-successful.patch b/root/target/linux/ipq806x/patches-5.10/107-1-thermal-qcom-tsens-init-debugfs-only-with-successful.patch similarity index 100% rename from root/target/linux/ipq806x/patches-5.15/107-1-thermal-qcom-tsens-init-debugfs-only-with-successful.patch rename to root/target/linux/ipq806x/patches-5.10/107-1-thermal-qcom-tsens-init-debugfs-only-with-successful.patch diff --git a/root/target/linux/ipq806x/patches-5.15/107-2-thermal-qcom-tsens-simplify-debugfs-init-function.patch b/root/target/linux/ipq806x/patches-5.10/107-2-thermal-qcom-tsens-simplify-debugfs-init-function.patch similarity index 100% rename from root/target/linux/ipq806x/patches-5.15/107-2-thermal-qcom-tsens-simplify-debugfs-init-function.patch rename to root/target/linux/ipq806x/patches-5.10/107-2-thermal-qcom-tsens-simplify-debugfs-init-function.patch diff --git a/root/target/linux/ipq806x/patches-5.10/108-v5.14-net-stmmac-explicitly-deassert-gmac-ahb-reset.patch b/root/target/linux/ipq806x/patches-5.10/108-v5.14-net-stmmac-explicitly-deassert-gmac-ahb-reset.patch new file mode 100755 index 00000000..2bcf1775 --- /dev/null +++ b/root/target/linux/ipq806x/patches-5.10/108-v5.14-net-stmmac-explicitly-deassert-gmac-ahb-reset.patch @@ -0,0 +1,75 @@ +From e67f325e9cd67562b761e884680c0fec03a6f404 Mon Sep 17 00:00:00 2001 +From: Matthew Hagan +Date: Tue, 8 Jun 2021 19:59:06 +0100 +Subject: net: stmmac: explicitly deassert GMAC_AHB_RESET + +We are currently assuming that GMAC_AHB_RESET will already be deasserted +by the bootloader. However if this has not been done, probing of the GMAC +will fail. To remedy this we must ensure GMAC_AHB_RESET has been deasserted +prior to probing. + +v2 changes: + - remove NULL condition check for stmmac_ahb_rst in stmmac_main.c + - unwrap dev_err() message in stmmac_main.c + - add PTR_ERR() around plat->stmmac_ahb_rst in stmmac_platform.c + +v3 changes: + - add error pointer to dev_err() output + - add reset_control_assert(stmmac_ahb_rst) in stmmac_dvr_remove + - revert PTR_ERR() around plat->stmmac_ahb_rst since this is performed + on the returned value of ret by the calling function + +Signed-off-by: Matthew Hagan +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 5 +++++ + drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 6 ++++++ + include/linux/stmmac.h | 1 + + 3 files changed, 12 insertions(+) + +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +@@ -5023,6 +5023,10 @@ int stmmac_dvr_probe(struct device *devi + reset_control_reset(priv->plat->stmmac_rst); + } + ++ ret = reset_control_deassert(priv->plat->stmmac_ahb_rst); ++ if (ret == -ENOTSUPP) ++ dev_err(priv->device, "unable to bring out of ahb reset\n"); ++ + /* Init MAC and get the capabilities */ + ret = stmmac_hw_init(priv); + if (ret) +@@ -5247,6 +5251,7 @@ int stmmac_dvr_remove(struct device *dev + phylink_destroy(priv->phylink); + if (priv->plat->stmmac_rst) + reset_control_assert(priv->plat->stmmac_rst); ++ reset_control_assert(priv->plat->stmmac_ahb_rst); + pm_runtime_put(dev); + pm_runtime_disable(dev); + if (priv->hw->pcs != STMMAC_PCS_TBI && +--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c ++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +@@ -617,6 +617,12 @@ stmmac_probe_config_dt(struct platform_d + plat->stmmac_rst = NULL; + } + ++ plat->stmmac_ahb_rst = devm_reset_control_get_optional_shared( ++ &pdev->dev, "ahb"); ++ if (IS_ERR(plat->stmmac_ahb_rst)) ++ if (PTR_ERR(plat->stmmac_ahb_rst) == -EPROBE_DEFER) ++ goto error_hw_init; ++ + return plat; + + error_hw_init: +--- a/include/linux/stmmac.h ++++ b/include/linux/stmmac.h +@@ -192,6 +192,7 @@ struct plat_stmmacenet_data { + unsigned int clk_ref_rate; + s32 ptp_max_adj; + struct reset_control *stmmac_rst; ++ struct reset_control *stmmac_ahb_rst; + struct stmmac_axi *axi; + int has_gmac4; + bool has_sun8i; diff --git a/root/target/linux/ipq806x/patches-5.10/109-v5.15-arm-dts-qcom-add-ahb-reset-to-ipq806x-gmac.patch b/root/target/linux/ipq806x/patches-5.10/109-v5.15-arm-dts-qcom-add-ahb-reset-to-ipq806x-gmac.patch new file mode 100755 index 00000000..4a047ed6 --- /dev/null +++ b/root/target/linux/ipq806x/patches-5.10/109-v5.15-arm-dts-qcom-add-ahb-reset-to-ipq806x-gmac.patch @@ -0,0 +1,64 @@ +From f95c4c56d65225a537a2d88735fde7ec4d37641d Mon Sep 17 00:00:00 2001 +From: Matthew Hagan +Date: Sat, 5 Jun 2021 18:35:38 +0100 +Subject: ARM: dts: qcom: add ahb reset to ipq806x-gmac + +Add GMAC_AHB_RESET to the resets property of each gmac node. + +Signed-off-by: Matthew Hagan +Link: https://lore.kernel.org/r/20210605173546.4102455-2-mnhagan88@gmail.com +Signed-off-by: Bjorn Andersson +--- + arch/arm/boot/dts/qcom-ipq8064.dtsi | 20 ++++++++++++-------- + 1 file changed, 12 insertions(+), 8 deletions(-) + +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -1335,8 +1335,9 @@ + clocks = <&gcc GMAC_CORE1_CLK>; + clock-names = "stmmaceth"; + +- resets = <&gcc GMAC_CORE1_RESET>; +- reset-names = "stmmaceth"; ++ resets = <&gcc GMAC_CORE1_RESET>, ++ <&gcc GMAC_AHB_RESET>; ++ reset-names = "stmmaceth", "ahb"; + + status = "disabled"; + }; +@@ -1358,8 +1359,9 @@ + clocks = <&gcc GMAC_CORE2_CLK>; + clock-names = "stmmaceth"; + +- resets = <&gcc GMAC_CORE2_RESET>; +- reset-names = "stmmaceth"; ++ resets = <&gcc GMAC_CORE2_RESET>, ++ <&gcc GMAC_AHB_RESET>; ++ reset-names = "stmmaceth", "ahb"; + + status = "disabled"; + }; +@@ -1381,8 +1383,9 @@ + clocks = <&gcc GMAC_CORE3_CLK>; + clock-names = "stmmaceth"; + +- resets = <&gcc GMAC_CORE3_RESET>; +- reset-names = "stmmaceth"; ++ resets = <&gcc GMAC_CORE3_RESET>, ++ <&gcc GMAC_AHB_RESET>; ++ reset-names = "stmmaceth", "ahb"; + + status = "disabled"; + }; +@@ -1404,8 +1407,9 @@ + clocks = <&gcc GMAC_CORE4_CLK>; + clock-names = "stmmaceth"; + +- resets = <&gcc GMAC_CORE4_RESET>; +- reset-names = "stmmaceth"; ++ resets = <&gcc GMAC_CORE4_RESET>, ++ <&gcc GMAC_AHB_RESET>; ++ reset-names = "stmmaceth", "ahb"; + + status = "disabled"; + }; diff --git a/root/target/linux/ipq806x/patches-5.15/850-soc-add-qualcomm-syscon.patch b/root/target/linux/ipq806x/patches-5.10/850-soc-add-qualcomm-syscon.patch similarity index 100% rename from root/target/linux/ipq806x/patches-5.15/850-soc-add-qualcomm-syscon.patch rename to root/target/linux/ipq806x/patches-5.10/850-soc-add-qualcomm-syscon.patch diff --git a/root/target/linux/ipq806x/patches-5.15/900-arm-add-cmdline-override.patch b/root/target/linux/ipq806x/patches-5.10/900-arm-add-cmdline-override.patch similarity index 95% rename from root/target/linux/ipq806x/patches-5.15/900-arm-add-cmdline-override.patch rename to root/target/linux/ipq806x/patches-5.10/900-arm-add-cmdline-override.patch index 2459e6a2..830a1492 100755 --- a/root/target/linux/ipq806x/patches-5.15/900-arm-add-cmdline-override.patch +++ b/root/target/linux/ipq806x/patches-5.10/900-arm-add-cmdline-override.patch @@ -1,6 +1,6 @@ --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig -@@ -1793,6 +1793,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGL +@@ -1794,6 +1794,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGL endchoice diff --git a/root/target/linux/ipq806x/patches-5.15/997-device_tree_cmdline.patch b/root/target/linux/ipq806x/patches-5.10/997-device_tree_cmdline.patch similarity index 100% rename from root/target/linux/ipq806x/patches-5.15/997-device_tree_cmdline.patch rename to root/target/linux/ipq806x/patches-5.10/997-device_tree_cmdline.patch diff --git a/root/target/linux/ipq806x/patches-5.15/082-ipq8064-dtsi-tweaks.patch b/root/target/linux/ipq806x/patches-5.15/082-ipq8064-dtsi-tweaks.patch deleted file mode 100755 index 88306713..00000000 --- a/root/target/linux/ipq806x/patches-5.15/082-ipq8064-dtsi-tweaks.patch +++ /dev/null @@ -1,77 +0,0 @@ ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -128,6 +128,7 @@ - gpio-ranges = <&qcom_pinmux 0 0 69>; - #gpio-cells = <2>; - interrupt-controller; -+ #address-cells = <0>; - #interrupt-cells = <2>; - interrupts = ; - -@@ -155,6 +156,7 @@ - function = "pcie3_rst"; - drive-strength = <12>; - bias-disable; -+ output-low; - }; - }; - -@@ -190,6 +192,7 @@ - intc: interrupt-controller@2000000 { - compatible = "qcom,msm-qgic2"; - interrupt-controller; -+ #address-cells = <0>; - #interrupt-cells = <3>; - reg = <0x02000000 0x1000>, - <0x02002000 0x1000>; -@@ -630,10 +736,13 @@ - tsens_calib_backup: calib_backup@410 { - reg = <0x410 0xb>; - }; -+ speedbin_efuse: speedbin@0c0 { -+ reg = <0x0c0 0x4>; -+ }; - }; - - gcc: clock-controller@900000 { -- compatible = "qcom,gcc-ipq8064"; -+ compatible = "qcom,gcc-ipq8064", "syscon"; - reg = <0x00900000 0x4000>; - #clock-cells = <1>; - #reset-cells = <1>; -@@ -722,7 +749,7 @@ - - gmac0: ethernet@37000000 { - device_type = "network"; -- compatible = "qcom,ipq806x-gmac"; -+ compatible = "qcom,ipq806x-gmac", "snps,dwmac"; - reg = <0x37000000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; -@@ -745,7 +772,7 @@ - - gmac1: ethernet@37200000 { - device_type = "network"; -- compatible = "qcom,ipq806x-gmac"; -+ compatible = "qcom,ipq806x-gmac", "snps,dwmac"; - reg = <0x37200000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; -@@ -768,7 +795,7 @@ - - gmac2: ethernet@37400000 { - device_type = "network"; -- compatible = "qcom,ipq806x-gmac"; -+ compatible = "qcom,ipq806x-gmac", "snps,dwmac"; - reg = <0x37400000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; -@@ -791,7 +818,7 @@ - - gmac3: ethernet@37600000 { - device_type = "network"; -- compatible = "qcom,ipq806x-gmac"; -+ compatible = "qcom,ipq806x-gmac", "snps,dwmac"; - reg = <0x37600000 0x200000>; - interrupts = ; - interrupt-names = "macirq"; diff --git a/root/target/linux/ipq806x/patches-5.15/083-ipq8064-dtsi-additions.patch b/root/target/linux/ipq806x/patches-5.15/083-ipq8064-dtsi-additions.patch deleted file mode 100755 index 2231038b..00000000 --- a/root/target/linux/ipq806x/patches-5.15/083-ipq8064-dtsi-additions.patch +++ /dev/null @@ -1,355 +0,0 @@ ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -8,6 +8,8 @@ - #include - #include - #include -+#include -+#include - - / { - #address-cells = <1>; -@@ -28,6 +30,16 @@ - next-level-cache = <&L2>; - qcom,acc = <&acc0>; - qcom,saw = <&saw0>; -+ clocks = <&kraitcc 0>, <&kraitcc 4>; -+ clock-names = "cpu", "l2"; -+ clock-latency = <100000>; -+ cpu-supply = <&smb208_s2a>; -+ operating-points-v2 = <&opp_table0>; -+ voltage-tolerance = <5>; -+ cooling-min-state = <0>; -+ cooling-max-state = <10>; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_SPC>; - }; - - cpu1: cpu@1 { -@@ -38,16 +50,130 @@ - next-level-cache = <&L2>; - qcom,acc = <&acc1>; - qcom,saw = <&saw1>; -+ clocks = <&kraitcc 1>, <&kraitcc 4>; -+ clock-names = "cpu", "l2"; -+ clock-latency = <100000>; -+ cpu-supply = <&smb208_s2b>; -+ operating-points-v2 = <&opp_table0>; -+ voltage-tolerance = <5>; -+ cooling-min-state = <0>; -+ cooling-max-state = <10>; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_SPC>; -+ }; -+ -+ idle-states { -+ CPU_SPC: spc { -+ compatible = "qcom,idle-state-spc"; -+ status = "disabled"; -+ entry-latency-us = <400>; -+ exit-latency-us = <900>; -+ min-residency-us = <3000>; -+ }; - }; -+ }; - -- L2: l2-cache { -- compatible = "cache"; -- cache-level = <2>; -+ opp_table_l2: opp_table_l2 { -+ compatible = "operating-points-v2"; -+ -+ opp-384000000 { -+ opp-hz = /bits/ 64 <384000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <100000>; -+ opp-level = <0>; -+ }; -+ -+ opp-1000000000 { -+ opp-hz = /bits/ 64 <1000000000>; -+ opp-microvolt = <1100000>; -+ clock-latency-ns = <100000>; -+ opp-level = <1>; -+ }; -+ -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt = <1150000>; -+ clock-latency-ns = <100000>; -+ opp-level = <2>; - }; - }; - -+ opp_table0: opp_table0 { -+ compatible = "operating-points-v2-kryo-cpu"; -+ nvmem-cells = <&speedbin_efuse>; -+ -+ /* -+ * Voltage thresholds are -+ */ -+ opp-384000000 { -+ opp-hz = /bits/ 64 <384000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>; -+ opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>; -+ opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>; -+ opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <0>; -+ }; -+ -+ opp-600000000 { -+ opp-hz = /bits/ 64 <600000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>; -+ opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>; -+ opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>; -+ opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <1>; -+ }; -+ -+ opp-800000000 { -+ opp-hz = /bits/ 64 <800000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>; -+ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>; -+ opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>; -+ opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <1>; -+ }; -+ -+ opp-1000000000 { -+ opp-hz = /bits/ 64 <1000000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>; -+ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>; -+ opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>; -+ opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <1>; -+ }; -+ -+ opp-1200000000 { -+ opp-hz = /bits/ 64 <1200000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>; -+ opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>; -+ opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>; -+ opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <2>; -+ }; -+ -+ opp-1400000000 { -+ opp-hz = /bits/ 64 <1400000000>; -+ opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>; -+ opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>; -+ opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>; -+ opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>; -+ opp-supported-hw = <0x1>; -+ clock-latency-ns = <100000>; -+ opp-level = <2>; -+ }; -+ }; -+ - thermal-zones { - tsens_tz_sensor0 { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-sensors = <&tsens 0>; -@@ -93,6 +441,15 @@ - }; - }; - -+ fab-scaling { -+ compatible = "qcom,fab-scaling"; -+ clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>; -+ clock-names = "apps-fab-clk", "ddr-fab-clk"; -+ fab_freq_high = <533000000>; -+ fab_freq_nominal = <400000000>; -+ cpu_freq_threshold = <1000000000>; -+ }; -+ - firmware { - scm { - compatible = "qcom,scm-ipq806x", "qcom,scm"; -@@ -120,6 +477,17 @@ - reg-names = "lpass-lpaif"; - }; - -+ L2: l2-cache { -+ compatible = "qcom,krait-cache", "cache"; -+ cache-level = <2>; -+ qcom,saw = <&saw_l2>; -+ -+ clocks = <&kraitcc 4>; -+ clock-names = "l2"; -+ l2-supply = <&smb208_s1a>; -+ operating-points-v2 = <&opp_table_l2>; -+ }; -+ - qcom_pinmux: pinmux@800000 { - compatible = "qcom,ipq8064-pinctrl"; - reg = <0x800000 0x4000>; -@@ -160,6 +589,15 @@ - }; - }; - -+ i2c4_pins: i2c4_pinmux { -+ mux { -+ pins = "gpio12", "gpio13"; -+ function = "gsbi4"; -+ drive-strength = <12>; -+ bias-disable; -+ }; -+ }; -+ - spi_pins: spi_pins { - mux { - pins = "gpio18", "gpio19", "gpio21"; -@@ -169,6 +607,28 @@ - }; - }; - -+ -+ mdio0_pins: mdio0_pins { -+ mux { -+ pins = "gpio0", "gpio1"; -+ function = "mdio"; -+ drive-strength = <8>; -+ bias-disable; -+ }; -+ }; -+ -+ rgmii2_pins: rgmii2_pins { -+ mux { -+ pins = "gpio27", "gpio28", "gpio29", -+ "gpio30", "gpio31", "gpio32", -+ "gpio51", "gpio52", "gpio59", -+ "gpio60", "gpio61", "gpio62"; -+ function = "rgmii2"; -+ drive-strength = <8>; -+ bias-disable; -+ }; -+ }; -+ - leds_pins: leds_pins { - mux { - pins = "gpio7", "gpio8", "gpio9", -@@ -243,6 +739,22 @@ - regulator; - }; - -+ kraitcc: clock-controller { -+ compatible = "qcom,krait-cc-v1"; -+ #clock-cells = <1>; -+ }; -+ -+ saw_l2: regulator@02012000 { -+ compatible = "qcom,saw2", "syscon"; -+ reg = <0x02012000 0x1000>; -+ regulator; -+ }; -+ -+ sic_non_secure: sic-non-secure@12100000 { -+ compatible = "syscon"; -+ reg = <0x12100000 0x10000>; -+ }; -+ - gsbi2: gsbi@12480000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <2>; -@@ -478,6 +985,11 @@ - #reset-cells = <1>; - }; - -+ sfpb_mutex_block: syscon@1200600 { -+ compatible = "syscon"; -+ reg = <0x01200600 0x100>; -+ }; -+ - pcie0: pci@1b500000 { - compatible = "qcom,pcie-ipq8064"; - reg = <0x1b500000 0x1000 -@@ -739,6 +1335,20 @@ - status = "disabled"; - }; - -+ mdio0: mdio@37000000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ compatible = "qcom,ipq8064-mdio", "syscon"; -+ reg = <0x37000000 0x200000>; -+ resets = <&gcc GMAC_CORE1_RESET>; -+ reset-names = "stmmaceth"; -+ clocks = <&gcc GMAC_CORE1_CLK>; -+ clock-names = "stmmaceth"; -+ -+ status = "disabled"; -+ }; -+ - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; -@@ -814,4 +1463,17 @@ - }; - }; - }; -+ -+ sfpb_mutex: sfpb-mutex { -+ compatible = "qcom,sfpb-mutex"; -+ syscon = <&sfpb_mutex_block 4 4>; -+ -+ #hwlock-cells = <1>; -+ }; -+ -+ smem { -+ compatible = "qcom,smem"; -+ memory-region = <&smem>; -+ hwlocks = <&sfpb_mutex 3>; -+ }; - }; ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -1020,6 +1020,37 @@ - compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; - #clock-cells = <1>; - }; -+ regulators { -+ compatible = "qcom,rpm-smb208-regulators"; -+ -+ smb208_s1a: s1a { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s1b: s1b { -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1150000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s2a: s2a { -+ regulator-min-microvolt = < 800000>; -+ regulator-max-microvolt = <1250000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ -+ smb208_s2b: s2b { -+ regulator-min-microvolt = < 800000>; -+ regulator-max-microvolt = <1250000>; -+ -+ qcom,switch-mode-frequency = <1200000>; -+ }; -+ }; - }; - - tcsr: syscon@1a400000 { diff --git a/root/target/linux/ipq806x/patches-5.15/851-add-gsbi1-dts.patch b/root/target/linux/ipq806x/patches-5.15/851-add-gsbi1-dts.patch deleted file mode 100755 index e6ee9a93..00000000 --- a/root/target/linux/ipq806x/patches-5.15/851-add-gsbi1-dts.patch +++ /dev/null @@ -1,44 +0,0 @@ ---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi -+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi -@@ -750,6 +750,41 @@ - reg = <0x12100000 0x10000>; - }; - -+ gsbi1: gsbi@12440000 { -+ compatible = "qcom,gsbi-v1.0.0"; -+ cell-index = <1>; -+ reg = <0x12440000 0x100>; -+ clocks = <&gcc GSBI1_H_CLK>; -+ clock-names = "iface"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges; -+ status = "disabled"; -+ -+ syscon-tcsr = <&tcsr>; -+ -+ gsbi1_serial: serial@12450000 { -+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; -+ reg = <0x12450000 0x100>, -+ <0x12400000 0x03>; -+ interrupts = ; -+ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; -+ clock-names = "core", "iface"; -+ status = "disabled"; -+ }; -+ -+ gsbi1_i2c: i2c@12460000 { -+ compatible = "qcom,i2c-qup-v1.1.1"; -+ reg = <0x12460000 0x1000>; -+ interrupts = ; -+ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; -+ clock-names = "core", "iface"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ }; -+ - gsbi2: gsbi@12480000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <2>;