mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Add kernel 6.10 patches for filogic
This commit is contained in:
parent
a9809a6010
commit
7b674b3d1c
133 changed files with 13998 additions and 0 deletions
|
@ -0,0 +1,32 @@
|
||||||
|
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include <dt-bindings/gpio/gpio.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
|
||||||
|
|
||||||
|
fragment@0 {
|
||||||
|
target = <&gmac1>;
|
||||||
|
__overlay__ {
|
||||||
|
phy-mode = "2500base-x";
|
||||||
|
phy-handle = <&phy5>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
fragment@1 {
|
||||||
|
target = <&mdio_bus>;
|
||||||
|
__overlay__ {
|
||||||
|
reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
|
||||||
|
reset-delay-us = <600>;
|
||||||
|
reset-post-delay-us = <20000>;
|
||||||
|
|
||||||
|
phy5: ethernet-phy@5 {
|
||||||
|
reg = <5>;
|
||||||
|
compatible = "ethernet-phy-ieee802.3-c45";
|
||||||
|
phy-mode = "2500base-x";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
|
@ -0,0 +1,33 @@
|
||||||
|
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include <dt-bindings/gpio/gpio.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
|
||||||
|
|
||||||
|
fragment@0 {
|
||||||
|
target = <&sw_p5>;
|
||||||
|
__overlay__ {
|
||||||
|
phy-mode = "2500base-x";
|
||||||
|
phy-handle = <&phy5>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
fragment@1 {
|
||||||
|
target = <&mdio_bus>;
|
||||||
|
__overlay__ {
|
||||||
|
reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
|
||||||
|
reset-delay-us = <600>;
|
||||||
|
reset-post-delay-us = <20000>;
|
||||||
|
|
||||||
|
phy5: ethernet-phy@5 {
|
||||||
|
reg = <5>;
|
||||||
|
compatible = "ethernet-phy-ieee802.3-c45";
|
||||||
|
phy-mode = "2500base-x";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
|
@ -0,0 +1,66 @@
|
||||||
|
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
|
||||||
|
|
||||||
|
fragment@0 {
|
||||||
|
target = <&spi0>;
|
||||||
|
__overlay__ {
|
||||||
|
status = "okay";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
spi_nand: spi_nand@0 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
compatible = "spi-nand";
|
||||||
|
reg = <1>;
|
||||||
|
spi-max-frequency = <10000000>;
|
||||||
|
spi-tx-bus-width = <4>;
|
||||||
|
spi-rx-bus-width = <4>;
|
||||||
|
|
||||||
|
partitions {
|
||||||
|
compatible = "fixed-partitions";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
partition@0 {
|
||||||
|
label = "BL2";
|
||||||
|
reg = <0x00000 0x0100000>;
|
||||||
|
read-only;
|
||||||
|
};
|
||||||
|
|
||||||
|
partition@100000 {
|
||||||
|
label = "u-boot-env";
|
||||||
|
reg = <0x0100000 0x0080000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
factory: partition@180000 {
|
||||||
|
label = "Factory";
|
||||||
|
reg = <0x180000 0x0200000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
partition@380000 {
|
||||||
|
label = "FIP";
|
||||||
|
reg = <0x380000 0x0200000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
partition@580000 {
|
||||||
|
label = "ubi";
|
||||||
|
reg = <0x580000 0x4000000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
fragment@1 {
|
||||||
|
target = <&wifi>;
|
||||||
|
__overlay__ {
|
||||||
|
mediatek,mtd-eeprom = <&factory 0x0>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
|
@ -0,0 +1,188 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2022 MediaTek Inc.
|
||||||
|
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
#include "mt7981.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "MediaTek MT7981 RFB";
|
||||||
|
compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
serial0 = &uart0;
|
||||||
|
};
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
stdout-path = "serial0:115200n8";
|
||||||
|
};
|
||||||
|
|
||||||
|
memory {
|
||||||
|
reg = <0 0x40000000 0 0x20000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
reg_3p3v: regulator-3p3v {
|
||||||
|
compatible = "regulator-fixed";
|
||||||
|
regulator-name = "fixed-3.3V";
|
||||||
|
regulator-min-microvolt = <3300000>;
|
||||||
|
regulator-max-microvolt = <3300000>;
|
||||||
|
regulator-boot-on;
|
||||||
|
regulator-always-on;
|
||||||
|
};
|
||||||
|
|
||||||
|
reg_5v: regulator-5v {
|
||||||
|
compatible = "regulator-fixed";
|
||||||
|
regulator-name = "fixed-5V";
|
||||||
|
regulator-min-microvolt = <5000000>;
|
||||||
|
regulator-max-microvolt = <5000000>;
|
||||||
|
regulator-boot-on;
|
||||||
|
regulator-always-on;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpio-keys {
|
||||||
|
compatible = "gpio-keys";
|
||||||
|
reset {
|
||||||
|
label = "reset";
|
||||||
|
linux,code = <KEY_RESTART>;
|
||||||
|
gpios = <&pio 1 GPIO_ACTIVE_LOW>;
|
||||||
|
};
|
||||||
|
wps {
|
||||||
|
label = "wps";
|
||||||
|
linux,code = <KEY_WPS_BUTTON>;
|
||||||
|
gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
ð {
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
gmac0: mac@0 {
|
||||||
|
compatible = "mediatek,eth-mac";
|
||||||
|
reg = <0>;
|
||||||
|
phy-mode = "2500base-x";
|
||||||
|
|
||||||
|
fixed-link {
|
||||||
|
speed = <2500>;
|
||||||
|
full-duplex;
|
||||||
|
pause;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
gmac1: mac@1 {
|
||||||
|
compatible = "mediatek,eth-mac";
|
||||||
|
reg = <1>;
|
||||||
|
phy-mode = "gmii";
|
||||||
|
phy-handle = <&int_gbe_phy>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&mdio_bus {
|
||||||
|
switch: switch@1f {
|
||||||
|
compatible = "mediatek,mt7531";
|
||||||
|
reg = <31>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
interrupt-parent = <&pio>;
|
||||||
|
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&crypto {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&pio {
|
||||||
|
spi0_flash_pins: spi0-pins {
|
||||||
|
mux {
|
||||||
|
function = "spi";
|
||||||
|
groups = "spi0", "spi0_wp_hold";
|
||||||
|
};
|
||||||
|
conf-pu {
|
||||||
|
pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
|
||||||
|
drive-strength = <MTK_DRIVE_8mA>;
|
||||||
|
bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
|
||||||
|
};
|
||||||
|
conf-pd {
|
||||||
|
pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
|
||||||
|
drive-strength = <MTK_DRIVE_8mA>;
|
||||||
|
bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
&spi0 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&spi0_flash_pins>;
|
||||||
|
cs-gpios = <0>, <0>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
&switch {
|
||||||
|
ports {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
port@0 {
|
||||||
|
reg = <0>;
|
||||||
|
label = "lan1";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@1 {
|
||||||
|
reg = <1>;
|
||||||
|
label = "lan2";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@2 {
|
||||||
|
reg = <2>;
|
||||||
|
label = "lan3";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@3 {
|
||||||
|
reg = <3>;
|
||||||
|
label = "lan4";
|
||||||
|
};
|
||||||
|
|
||||||
|
sw_p5: port@5 {
|
||||||
|
reg = <5>;
|
||||||
|
label = "lan5";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@6 {
|
||||||
|
reg = <6>;
|
||||||
|
ethernet = <&gmac0>;
|
||||||
|
phy-mode = "2500base-x";
|
||||||
|
|
||||||
|
fixed-link {
|
||||||
|
speed = <2500>;
|
||||||
|
full-duplex;
|
||||||
|
pause;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&xhci {
|
||||||
|
vusb33-supply = <®_3p3v>;
|
||||||
|
vbus-supply = <®_5v>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&uart0 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&usb_phy {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&watchdog {
|
||||||
|
status = "okay";
|
||||||
|
};
|
|
@ -0,0 +1,822 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2020 MediaTek Inc.
|
||||||
|
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||||
|
* Author: Jianhui Zhao <zhaojh329@gmail.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <dt-bindings/interrupt-controller/irq.h>
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
#include <dt-bindings/phy/phy.h>
|
||||||
|
#include <dt-bindings/clock/mediatek,mt7981-clk.h>
|
||||||
|
#include <dt-bindings/reset/mt7986-resets.h>
|
||||||
|
#include <dt-bindings/pinctrl/mt65xx.h>
|
||||||
|
#include <dt-bindings/leds/common.h>
|
||||||
|
#include <dt-bindings/input/linux-event-codes.h>
|
||||||
|
#include <dt-bindings/gpio/gpio.h>
|
||||||
|
#include <dt-bindings/mux/mux.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "mediatek,mt7981";
|
||||||
|
interrupt-parent = <&gic>;
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
cpu@0 {
|
||||||
|
compatible = "arm,cortex-a53";
|
||||||
|
reg = <0x0>;
|
||||||
|
device_type = "cpu";
|
||||||
|
enable-method = "psci";
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu@1 {
|
||||||
|
compatible = "arm,cortex-a53";
|
||||||
|
reg = <0x1>;
|
||||||
|
device_type = "cpu";
|
||||||
|
enable-method = "psci";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
ice: ice_debug {
|
||||||
|
compatible = "mediatek,mt7981-ice_debug", "mediatek,mt2701-ice_debug";
|
||||||
|
clocks = <&infracfg CLK_INFRA_DBG_CK>;
|
||||||
|
clock-names = "ice_dbg";
|
||||||
|
};
|
||||||
|
|
||||||
|
clk40m: oscillator-40m {
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
clock-frequency = <40000000>;
|
||||||
|
clock-output-names = "clkxtal";
|
||||||
|
#clock-cells = <0>;
|
||||||
|
};
|
||||||
|
|
||||||
|
psci {
|
||||||
|
compatible = "arm,psci-0.2";
|
||||||
|
method = "smc";
|
||||||
|
};
|
||||||
|
|
||||||
|
fan: pwm-fan {
|
||||||
|
compatible = "pwm-fan";
|
||||||
|
/* cooling level (0, 1, 2, 3, 4, 5, 6, 7) : (0%/25%/37.5%/50%/62.5%/75%/87.5%/100% duty) */
|
||||||
|
cooling-levels = <0 63 95 127 159 191 223 255>;
|
||||||
|
#cooling-cells = <2>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
reg_3p3v: regulator-3p3v {
|
||||||
|
compatible = "regulator-fixed";
|
||||||
|
regulator-name = "fixed-3.3V";
|
||||||
|
regulator-min-microvolt = <3300000>;
|
||||||
|
regulator-max-microvolt = <3300000>;
|
||||||
|
regulator-boot-on;
|
||||||
|
regulator-always-on;
|
||||||
|
};
|
||||||
|
|
||||||
|
reserved-memory {
|
||||||
|
ranges;
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
|
||||||
|
/* 64 KiB reserved for ramoops/pstore */
|
||||||
|
ramoops@42ff0000 {
|
||||||
|
compatible = "ramoops";
|
||||||
|
reg = <0 0x42ff0000 0 0x10000>;
|
||||||
|
record-size = <0x1000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
|
||||||
|
secmon_reserved: secmon@43000000 {
|
||||||
|
reg = <0 0x43000000 0 0x30000>;
|
||||||
|
no-map;
|
||||||
|
};
|
||||||
|
|
||||||
|
wmcpu_emi: wmcpu-reserved@47c80000 {
|
||||||
|
reg = <0 0x47c80000 0 0x100000>;
|
||||||
|
no-map;
|
||||||
|
};
|
||||||
|
|
||||||
|
wo_emi0: wo-emi@47d80000 {
|
||||||
|
reg = <0 0x47d80000 0 0x40000>;
|
||||||
|
no-map;
|
||||||
|
};
|
||||||
|
|
||||||
|
wo_data: wo-data@47dc0000 {
|
||||||
|
reg = <0 0x47dc0000 0 0x240000>;
|
||||||
|
no-map;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
soc {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
ranges;
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
|
||||||
|
gic: interrupt-controller@c000000 {
|
||||||
|
compatible = "arm,gic-v3";
|
||||||
|
reg = <0 0x0c000000 0 0x40000>, /* GICD */
|
||||||
|
<0 0x0c080000 0 0x200000>; /* GICR */
|
||||||
|
interrupt-parent = <&gic>;
|
||||||
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
consys: consys@10000000 {
|
||||||
|
compatible = "mediatek,mt7981-consys";
|
||||||
|
reg = <0 0x10000000 0 0x8600000>;
|
||||||
|
memory-region = <&wmcpu_emi>;
|
||||||
|
};
|
||||||
|
|
||||||
|
infracfg: clock-controller@10001000 {
|
||||||
|
compatible = "mediatek,mt7981-infracfg", "syscon";
|
||||||
|
reg = <0 0x10001000 0 0x1000>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
wed_pcie: wed_pcie@10003000 {
|
||||||
|
compatible = "mediatek,wed_pcie";
|
||||||
|
reg = <0 0x10003000 0 0x10>;
|
||||||
|
};
|
||||||
|
|
||||||
|
topckgen: clock-controller@1001b000 {
|
||||||
|
compatible = "mediatek,mt7981-topckgen", "syscon";
|
||||||
|
reg = <0 0x1001b000 0 0x1000>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
watchdog: watchdog@1001c000 {
|
||||||
|
compatible = "mediatek,mt7986-wdt",
|
||||||
|
"mediatek,mt6589-wdt";
|
||||||
|
reg = <0 0x1001c000 0 0x1000>;
|
||||||
|
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
#reset-cells = <1>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
apmixedsys: clock-controller@1001e000 {
|
||||||
|
compatible = "mediatek,mt7981-apmixedsys", "syscon";
|
||||||
|
reg = <0 0x1001e000 0 0x1000>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pwm: pwm@10048000 {
|
||||||
|
compatible = "mediatek,mt7981-pwm";
|
||||||
|
reg = <0 0x10048000 0 0x1000>;
|
||||||
|
clocks = <&infracfg CLK_INFRA_PWM_STA>,
|
||||||
|
<&infracfg CLK_INFRA_PWM_HCK>,
|
||||||
|
<&infracfg CLK_INFRA_PWM1_CK>,
|
||||||
|
<&infracfg CLK_INFRA_PWM2_CK>,
|
||||||
|
<&infracfg CLK_INFRA_PWM3_CK>;
|
||||||
|
clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
|
||||||
|
#pwm-cells = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
sgmiisys0: syscon@10060000 {
|
||||||
|
compatible = "mediatek,mt7981-sgmiisys_0", "syscon";
|
||||||
|
reg = <0 0x10060000 0 0x1000>;
|
||||||
|
mediatek,pnswap;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
sgmiisys1: syscon@10070000 {
|
||||||
|
compatible = "mediatek,mt7981-sgmiisys_1", "syscon";
|
||||||
|
reg = <0 0x10070000 0 0x1000>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
crypto: crypto@10320000 {
|
||||||
|
compatible = "inside-secure,safexcel-eip97";
|
||||||
|
reg = <0 0x10320000 0 0x40000>;
|
||||||
|
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
interrupt-names = "ring0", "ring1", "ring2", "ring3";
|
||||||
|
clocks = <&topckgen CLK_TOP_EIP97B>;
|
||||||
|
clock-names = "top_eip97_ck";
|
||||||
|
assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
|
||||||
|
assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
|
||||||
|
};
|
||||||
|
|
||||||
|
uart0: serial@11002000 {
|
||||||
|
compatible = "mediatek,mt6577-uart";
|
||||||
|
reg = <0 0x11002000 0 0x400>;
|
||||||
|
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&infracfg CLK_INFRA_UART0_SEL>,
|
||||||
|
<&infracfg CLK_INFRA_UART0_CK>;
|
||||||
|
clock-names = "baud", "bus";
|
||||||
|
assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
|
||||||
|
<&infracfg CLK_INFRA_UART0_SEL>;
|
||||||
|
assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
|
||||||
|
<&topckgen CLK_TOP_UART_SEL>;
|
||||||
|
pinctrl-0 = <&uart0_pins>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
uart1: serial@11003000 {
|
||||||
|
compatible = "mediatek,mt6577-uart";
|
||||||
|
reg = <0 0x11003000 0 0x400>;
|
||||||
|
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&infracfg CLK_INFRA_UART1_SEL>,
|
||||||
|
<&infracfg CLK_INFRA_UART1_CK>;
|
||||||
|
clock-names = "baud", "bus";
|
||||||
|
assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
|
||||||
|
<&infracfg CLK_INFRA_UART1_SEL>;
|
||||||
|
assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
|
||||||
|
<&topckgen CLK_TOP_UART_SEL>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
uart2: serial@11004000 {
|
||||||
|
compatible = "mediatek,mt6577-uart";
|
||||||
|
reg = <0 0x11004000 0 0x400>;
|
||||||
|
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&infracfg CLK_INFRA_UART2_SEL>,
|
||||||
|
<&infracfg CLK_INFRA_UART2_CK>;
|
||||||
|
clock-names = "baud", "bus";
|
||||||
|
assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
|
||||||
|
<&infracfg CLK_INFRA_UART2_SEL>;
|
||||||
|
assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
|
||||||
|
<&topckgen CLK_TOP_UART_SEL>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
snand: snfi@11005000 {
|
||||||
|
compatible = "mediatek,mt7986-snand";
|
||||||
|
reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
|
||||||
|
reg-names = "nfi", "ecc";
|
||||||
|
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
|
||||||
|
<&infracfg CLK_INFRA_NFI1_CK>,
|
||||||
|
<&infracfg CLK_INFRA_NFI_HCK_CK>;
|
||||||
|
clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
|
||||||
|
assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
|
||||||
|
<&topckgen CLK_TOP_NFI1X_SEL>;
|
||||||
|
assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
|
||||||
|
<&topckgen CLK_TOP_CB_M_D8>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c0: i2c@11007000 {
|
||||||
|
compatible = "mediatek,mt7981-i2c";
|
||||||
|
reg = <0 0x11007000 0 0x1000>,
|
||||||
|
<0 0x10217080 0 0x80>;
|
||||||
|
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clock-div = <1>;
|
||||||
|
clocks = <&infracfg CLK_INFRA_I2C0_CK>,
|
||||||
|
<&infracfg CLK_INFRA_AP_DMA_CK>,
|
||||||
|
<&infracfg CLK_INFRA_I2C_MCK_CK>,
|
||||||
|
<&infracfg CLK_INFRA_I2C_PCK_CK>;
|
||||||
|
clock-names = "main", "dma", "arb", "pmic";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
spi2: spi@11009000 {
|
||||||
|
compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
|
||||||
|
reg = <0 0x11009000 0 0x100>;
|
||||||
|
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&topckgen CLK_TOP_CB_M_D2>,
|
||||||
|
<&topckgen CLK_TOP_SPI_SEL>,
|
||||||
|
<&infracfg CLK_INFRA_SPI2_CK>,
|
||||||
|
<&infracfg CLK_INFRA_SPI2_HCK_CK>;
|
||||||
|
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
spi0: spi@1100a000 {
|
||||||
|
compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
|
||||||
|
reg = <0 0x1100a000 0 0x100>;
|
||||||
|
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&topckgen CLK_TOP_CB_M_D2>,
|
||||||
|
<&topckgen CLK_TOP_SPI_SEL>,
|
||||||
|
<&infracfg CLK_INFRA_SPI0_CK>,
|
||||||
|
<&infracfg CLK_INFRA_SPI0_HCK_CK>;
|
||||||
|
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
spi1: spi@1100b000 {
|
||||||
|
compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
|
||||||
|
reg = <0 0x1100b000 0 0x100>;
|
||||||
|
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&topckgen CLK_TOP_CB_M_D2>,
|
||||||
|
<&topckgen CLK_TOP_SPIM_MST_SEL>,
|
||||||
|
<&infracfg CLK_INFRA_SPI1_CK>,
|
||||||
|
<&infracfg CLK_INFRA_SPI1_HCK_CK>;
|
||||||
|
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
thermal: thermal@1100c800 {
|
||||||
|
compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
|
||||||
|
reg = <0 0x1100c800 0 0x800>;
|
||||||
|
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&infracfg CLK_INFRA_THERM_CK>,
|
||||||
|
<&infracfg CLK_INFRA_ADC_26M_CK>;
|
||||||
|
clock-names = "therm", "auxadc";
|
||||||
|
nvmem-cells = <&thermal_calibration>;
|
||||||
|
nvmem-cell-names = "calibration-data";
|
||||||
|
#thermal-sensor-cells = <1>;
|
||||||
|
mediatek,auxadc = <&auxadc>;
|
||||||
|
mediatek,apmixedsys = <&apmixedsys>;
|
||||||
|
};
|
||||||
|
|
||||||
|
auxadc: adc@1100d000 {
|
||||||
|
compatible = "mediatek,mt7981-auxadc",
|
||||||
|
"mediatek,mt7986-auxadc",
|
||||||
|
"mediatek,mt7622-auxadc";
|
||||||
|
reg = <0 0x1100d000 0 0x1000>;
|
||||||
|
clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
|
||||||
|
<&infracfg CLK_INFRA_ADC_FRC_CK>;
|
||||||
|
clock-names = "main", "32k";
|
||||||
|
#io-channel-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
xhci: usb@11200000 {
|
||||||
|
compatible = "mediatek,mt7986-xhci",
|
||||||
|
"mediatek,mtk-xhci";
|
||||||
|
reg = <0 0x11200000 0 0x2e00>,
|
||||||
|
<0 0x11203e00 0 0x0100>;
|
||||||
|
reg-names = "mac", "ippc";
|
||||||
|
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
|
||||||
|
<&infracfg CLK_INFRA_IUSB_CK>,
|
||||||
|
<&infracfg CLK_INFRA_IUSB_133_CK>,
|
||||||
|
<&infracfg CLK_INFRA_IUSB_66M_CK>,
|
||||||
|
<&topckgen CLK_TOP_U2U3_XHCI_SEL>;
|
||||||
|
clock-names = "sys_ck",
|
||||||
|
"ref_ck",
|
||||||
|
"mcu_ck",
|
||||||
|
"dma_ck",
|
||||||
|
"xhci_ck";
|
||||||
|
phys = <&u2port0 PHY_TYPE_USB2>,
|
||||||
|
<&u3port0 PHY_TYPE_USB3>;
|
||||||
|
vusb33-supply = <®_3p3v>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
afe: audio-controller@11210000 {
|
||||||
|
compatible = "mediatek,mt79xx-audio";
|
||||||
|
reg = <0 0x11210000 0 0x9000>;
|
||||||
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
|
||||||
|
<&infracfg CLK_INFRA_AUD_26M_CK>,
|
||||||
|
<&infracfg CLK_INFRA_AUD_L_CK>,
|
||||||
|
<&infracfg CLK_INFRA_AUD_AUD_CK>,
|
||||||
|
<&infracfg CLK_INFRA_AUD_EG2_CK>,
|
||||||
|
<&topckgen CLK_TOP_AUD_SEL>;
|
||||||
|
clock-names = "aud_bus_ck",
|
||||||
|
"aud_26m_ck",
|
||||||
|
"aud_l_ck",
|
||||||
|
"aud_aud_ck",
|
||||||
|
"aud_eg2_ck",
|
||||||
|
"aud_sel";
|
||||||
|
assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
|
||||||
|
<&topckgen CLK_TOP_A1SYS_SEL>,
|
||||||
|
<&topckgen CLK_TOP_AUD_L_SEL>,
|
||||||
|
<&topckgen CLK_TOP_A_TUNER_SEL>;
|
||||||
|
assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>,
|
||||||
|
<&topckgen CLK_TOP_APLL2_D4>,
|
||||||
|
<&topckgen CLK_TOP_CB_APLL2_196M>,
|
||||||
|
<&topckgen CLK_TOP_APLL2_D4>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
mmc0: mmc@11230000 {
|
||||||
|
compatible = "mediatek,mt7986-mmc", "mediatek,mt7981-mmc";
|
||||||
|
reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>;
|
||||||
|
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <&infracfg CLK_INFRA_MSDC_CK>,
|
||||||
|
<&infracfg CLK_INFRA_MSDC_HCK_CK>,
|
||||||
|
<&infracfg CLK_INFRA_MSDC_66M_CK>,
|
||||||
|
<&infracfg CLK_INFRA_MSDC_133M_CK>;
|
||||||
|
assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
|
||||||
|
<&topckgen CLK_TOP_EMMC_400M_SEL>;
|
||||||
|
assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
|
||||||
|
<&topckgen CLK_TOP_CB_NET2_D2>;
|
||||||
|
clock-names = "source", "hclk", "axi_cg", "ahb_cg";
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
pcie: pcie@11280000 {
|
||||||
|
compatible = "mediatek,mt7981-pcie",
|
||||||
|
"mediatek,mt8192-pcie";
|
||||||
|
reg = <0 0x11280000 0 0x4000>;
|
||||||
|
reg-names = "pcie-mac";
|
||||||
|
ranges = <0x82000000 0 0x20000000
|
||||||
|
0x0 0x20000000 0 0x10000000>;
|
||||||
|
device_type = "pci";
|
||||||
|
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
bus-range = <0x00 0xff>;
|
||||||
|
clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
|
||||||
|
<&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
|
||||||
|
<&infracfg CLK_INFRA_IPCIER_CK>,
|
||||||
|
<&infracfg CLK_INFRA_IPCIEB_CK>;
|
||||||
|
phys = <&u3port0 PHY_TYPE_PCIE>;
|
||||||
|
phy-names = "pcie-phy";
|
||||||
|
interrupt-map-mask = <0 0 0 7>;
|
||||||
|
interrupt-map = <0 0 0 1 &pcie_intc 0>,
|
||||||
|
<0 0 0 2 &pcie_intc 1>,
|
||||||
|
<0 0 0 3 &pcie_intc 2>,
|
||||||
|
<0 0 0 4 &pcie_intc 3>;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
#address-cells = <3>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
pcie_intc: interrupt-controller {
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
#address-cells = <0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pio: pinctrl@11d00000 {
|
||||||
|
compatible = "mediatek,mt7981-pinctrl";
|
||||||
|
reg = <0 0x11d00000 0 0x1000>,
|
||||||
|
<0 0x11c00000 0 0x1000>,
|
||||||
|
<0 0x11c10000 0 0x1000>,
|
||||||
|
<0 0x11d20000 0 0x1000>,
|
||||||
|
<0 0x11e00000 0 0x1000>,
|
||||||
|
<0 0x11e20000 0 0x1000>,
|
||||||
|
<0 0x11f00000 0 0x1000>,
|
||||||
|
<0 0x11f10000 0 0x1000>,
|
||||||
|
<0 0x1000b000 0 0x1000>;
|
||||||
|
reg-names = "gpio", "iocfg_rt", "iocfg_rm",
|
||||||
|
"iocfg_rb", "iocfg_lb", "iocfg_bl",
|
||||||
|
"iocfg_tm", "iocfg_tl", "eint";
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
gpio-ranges = <&pio 0 0 56>;
|
||||||
|
interrupt-controller;
|
||||||
|
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
interrupt-parent = <&gic>;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
|
||||||
|
mdio_pins: mdc-mdio-pins {
|
||||||
|
mux {
|
||||||
|
function = "eth";
|
||||||
|
groups = "smi_mdc_mdio";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
uart0_pins: uart0-pins {
|
||||||
|
mux {
|
||||||
|
function = "uart";
|
||||||
|
groups = "uart0";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
wifi_dbdc_pins: wifi-dbdc-pins {
|
||||||
|
mux {
|
||||||
|
function = "eth";
|
||||||
|
groups = "wf0_mode1";
|
||||||
|
};
|
||||||
|
|
||||||
|
conf {
|
||||||
|
pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
|
||||||
|
"WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
|
||||||
|
"WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
|
||||||
|
"WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
|
||||||
|
"WF_CBA_RESETB", "WF_DIG_RESETB";
|
||||||
|
drive-strength = <4>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
gbe_led0_pins: gbe-led0-pins {
|
||||||
|
mux {
|
||||||
|
function = "led";
|
||||||
|
groups = "gbe_led0";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
gbe_led1_pins: gbe-led1-pins {
|
||||||
|
mux {
|
||||||
|
function = "led";
|
||||||
|
groups = "gbe_led1";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
topmisc: topmisc@11d10000 {
|
||||||
|
compatible = "mediatek,mt7981-topmisc", "syscon";
|
||||||
|
reg = <0 0x11d10000 0 0x10000>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
usb_phy: usb-phy@11e10000 {
|
||||||
|
compatible = "mediatek,mt7981",
|
||||||
|
"mediatek,generic-tphy-v2";
|
||||||
|
ranges = <0 0 0x11e10000 0x1700>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
u2port0: usb-phy@0 {
|
||||||
|
reg = <0x0 0x700>;
|
||||||
|
clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
|
||||||
|
clock-names = "ref";
|
||||||
|
#phy-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
u3port0: usb-phy@700 {
|
||||||
|
reg = <0x700 0x900>;
|
||||||
|
clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
|
||||||
|
clock-names = "ref";
|
||||||
|
#phy-cells = <1>;
|
||||||
|
mediatek,syscon-type = <&topmisc 0x218 0>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
efuse: efuse@11f20000 {
|
||||||
|
compatible = "mediatek,mt7981-efuse",
|
||||||
|
"mediatek,efuse";
|
||||||
|
reg = <0 0x11f20000 0 0x1000>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
thermal_calibration: thermal-calib@274 {
|
||||||
|
reg = <0x274 0xc>;
|
||||||
|
};
|
||||||
|
|
||||||
|
phy_calibration: phy-calib@8dc {
|
||||||
|
reg = <0x8dc 0x10>;
|
||||||
|
};
|
||||||
|
|
||||||
|
comb_rx_imp_p0: usb3-rx-imp@8c8 {
|
||||||
|
reg = <0x8c8 1>;
|
||||||
|
bits = <0 5>;
|
||||||
|
};
|
||||||
|
|
||||||
|
comb_tx_imp_p0: usb3-tx-imp@8c8 {
|
||||||
|
reg = <0x8c8 2>;
|
||||||
|
bits = <5 5>;
|
||||||
|
};
|
||||||
|
|
||||||
|
comb_intr_p0: usb3-intr@8c9 {
|
||||||
|
reg = <0x8c9 1>;
|
||||||
|
bits = <2 6>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
ethsys: clock-controller@15000000 {
|
||||||
|
compatible = "mediatek,mt7981-ethsys",
|
||||||
|
"syscon";
|
||||||
|
reg = <0 0x15000000 0 0x1000>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
#reset-cells = <1>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
wed: wed@15010000 {
|
||||||
|
compatible = "mediatek,mt7981-wed",
|
||||||
|
"mediatek,mt7986-wed",
|
||||||
|
"syscon";
|
||||||
|
reg = <0 0x15010000 0 0x1000>;
|
||||||
|
interrupt-parent = <&gic>;
|
||||||
|
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
memory-region = <&wo_emi0>, <&wo_data>;
|
||||||
|
memory-region-names = "wo-emi", "wo-data";
|
||||||
|
mediatek,wo-ccif = <&wo_ccif0>;
|
||||||
|
mediatek,wo-ilm = <&wo_ilm0>;
|
||||||
|
mediatek,wo-dlm = <&wo_dlm0>;
|
||||||
|
mediatek,wo-cpuboot = <&wo_cpuboot>;
|
||||||
|
};
|
||||||
|
|
||||||
|
eth: ethernet@15100000 {
|
||||||
|
compatible = "mediatek,mt7981-eth";
|
||||||
|
reg = <0 0x15100000 0 0x80000>;
|
||||||
|
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
clocks = <ðsys CLK_ETH_FE_EN>,
|
||||||
|
<ðsys CLK_ETH_GP2_EN>,
|
||||||
|
<ðsys CLK_ETH_GP1_EN>,
|
||||||
|
<ðsys CLK_ETH_WOCPU0_EN>,
|
||||||
|
<&sgmiisys0 CLK_SGM0_TX_EN>,
|
||||||
|
<&sgmiisys0 CLK_SGM0_RX_EN>,
|
||||||
|
<&sgmiisys0 CLK_SGM0_CK0_EN>,
|
||||||
|
<&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
|
||||||
|
<&sgmiisys1 CLK_SGM1_TX_EN>,
|
||||||
|
<&sgmiisys1 CLK_SGM1_RX_EN>,
|
||||||
|
<&sgmiisys1 CLK_SGM1_CK1_EN>,
|
||||||
|
<&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
|
||||||
|
<&topckgen CLK_TOP_SGM_REG>,
|
||||||
|
<&topckgen CLK_TOP_NETSYS_SEL>,
|
||||||
|
<&topckgen CLK_TOP_NETSYS_500M_SEL>;
|
||||||
|
clock-names = "fe", "gp2", "gp1", "wocpu0",
|
||||||
|
"sgmii_tx250m", "sgmii_rx250m",
|
||||||
|
"sgmii_cdr_ref", "sgmii_cdr_fb",
|
||||||
|
"sgmii2_tx250m", "sgmii2_rx250m",
|
||||||
|
"sgmii2_cdr_ref", "sgmii2_cdr_fb",
|
||||||
|
"sgmii_ck", "netsys0", "netsys1";
|
||||||
|
assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
|
||||||
|
<&topckgen CLK_TOP_SGM_325M_SEL>;
|
||||||
|
assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
|
||||||
|
<&topckgen CLK_TOP_CB_SGM_325M>;
|
||||||
|
mediatek,ethsys = <ðsys>;
|
||||||
|
mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
|
||||||
|
mediatek,infracfg = <&topmisc>;
|
||||||
|
mediatek,wed = <&wed>;
|
||||||
|
#reset-cells = <1>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
status = "disabled";
|
||||||
|
|
||||||
|
mdio_bus: mdio-bus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
int_gbe_phy: ethernet-phy@0 {
|
||||||
|
compatible = "ethernet-phy-ieee802.3-c22";
|
||||||
|
reg = <0>;
|
||||||
|
phy-mode = "gmii";
|
||||||
|
phy-is-integrated;
|
||||||
|
nvmem-cells = <&phy_calibration>;
|
||||||
|
nvmem-cell-names = "phy-cal-data";
|
||||||
|
|
||||||
|
leds {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
int_gbe_phy_led0: int-gbe-phy-led0@0 {
|
||||||
|
reg = <0>;
|
||||||
|
function = LED_FUNCTION_LAN;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
int_gbe_phy_led1: int-gbe-phy-led1@1 {
|
||||||
|
reg = <1>;
|
||||||
|
function = LED_FUNCTION_LAN;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
wdma: wdma@15104800 {
|
||||||
|
compatible = "mediatek,wed-wdma";
|
||||||
|
reg = <0 0x15104800 0 0x400>,
|
||||||
|
<0 0x15104c00 0 0x400>;
|
||||||
|
};
|
||||||
|
|
||||||
|
wo_cpuboot: syscon@15194000 {
|
||||||
|
compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
|
||||||
|
reg = <0 0x15194000 0 0x1000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ap2woccif: ap2woccif@151a5000 {
|
||||||
|
compatible = "mediatek,ap2woccif";
|
||||||
|
reg = <0 0x151a5000 0 0x1000>,
|
||||||
|
<0 0x151ad000 0 0x1000>;
|
||||||
|
interrupt-parent = <&gic>;
|
||||||
|
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
};
|
||||||
|
|
||||||
|
wo_ccif0: syscon@151a5000 {
|
||||||
|
compatible = "mediatek,mt7986-wo-ccif", "syscon";
|
||||||
|
reg = <0 0x151a5000 0 0x1000>;
|
||||||
|
interrupt-parent = <&gic>;
|
||||||
|
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
};
|
||||||
|
|
||||||
|
wo_ilm0: syscon@151e0000 {
|
||||||
|
compatible = "mediatek,mt7986-wo-ilm", "syscon";
|
||||||
|
reg = <0 0x151e0000 0 0x8000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
wo_dlm0: syscon@151e8000 {
|
||||||
|
compatible = "mediatek,mt7986-wo-dlm", "syscon";
|
||||||
|
reg = <0 0x151e8000 0 0x2000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
wifi: wifi@18000000 {
|
||||||
|
compatible = "mediatek,mt7981-wmac";
|
||||||
|
reg = <0 0x18000000 0 0x1000000>,
|
||||||
|
<0 0x10003000 0 0x1000>,
|
||||||
|
<0 0x11d10000 0 0x1000>;
|
||||||
|
resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
|
||||||
|
reset-names = "consys";
|
||||||
|
pinctrl-0 = <&wifi_dbdc_pins>;
|
||||||
|
pinctrl-names = "dbdc";
|
||||||
|
clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
|
||||||
|
<&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
|
||||||
|
clock-names = "mcu", "ap2conn";
|
||||||
|
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
|
||||||
|
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
memory-region = <&wmcpu_emi>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
thermal-zones {
|
||||||
|
cpu_thermal: cpu-thermal {
|
||||||
|
polling-delay-passive = <1000>;
|
||||||
|
polling-delay = <1000>;
|
||||||
|
thermal-sensors = <&thermal 0>;
|
||||||
|
|
||||||
|
trips {
|
||||||
|
cpu_trip_active_highest: active-highest {
|
||||||
|
temperature = <70000>;
|
||||||
|
hysteresis = <2000>;
|
||||||
|
type = "active";
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu_trip_active_high: active-high {
|
||||||
|
temperature = <60000>;
|
||||||
|
hysteresis = <2000>;
|
||||||
|
type = "active";
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu_trip_active_med: active-med {
|
||||||
|
temperature = <50000>;
|
||||||
|
hysteresis = <2000>;
|
||||||
|
type = "active";
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu_trip_active_low: active-low {
|
||||||
|
temperature = <45000>;
|
||||||
|
hysteresis = <2000>;
|
||||||
|
type = "active";
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu_trip_active_lowest: active-lowest {
|
||||||
|
temperature = <40000>;
|
||||||
|
hysteresis = <2000>;
|
||||||
|
type = "active";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
cooling-maps {
|
||||||
|
cpu-active-highest {
|
||||||
|
/* active: set fan to cooling level 7 */
|
||||||
|
cooling-device = <&fan 7 7>;
|
||||||
|
trip = <&cpu_trip_active_highest>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu-active-high {
|
||||||
|
/* active: set fan to cooling level 5 */
|
||||||
|
cooling-device = <&fan 5 5>;
|
||||||
|
trip = <&cpu_trip_active_high>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu-active-med {
|
||||||
|
/* active: set fan to cooling level 3 */
|
||||||
|
cooling-device = <&fan 3 3>;
|
||||||
|
trip = <&cpu_trip_active_med>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu-active-low {
|
||||||
|
/* active: set fan to cooling level 2 */
|
||||||
|
cooling-device = <&fan 2 2>;
|
||||||
|
trip = <&cpu_trip_active_low>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu-active-lowest {
|
||||||
|
/* active: set fan to cooling level 1 */
|
||||||
|
cooling-device = <&fan 1 1>;
|
||||||
|
trip = <&cpu_trip_active_lowest>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
timer {
|
||||||
|
compatible = "arm,armv8-timer";
|
||||||
|
interrupt-parent = <&gic>;
|
||||||
|
clock-frequency = <13000000>;
|
||||||
|
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||||
|
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
||||||
|
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||||
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
|
||||||
|
};
|
||||||
|
|
||||||
|
trng {
|
||||||
|
compatible = "mediatek,mt7981-rng";
|
||||||
|
};
|
||||||
|
};
|
|
@ -0,0 +1,52 @@
|
||||||
|
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
|
||||||
|
|
||||||
|
#include "mt7986a-rfb.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "mediatek,mt7986a-rfb-snand";
|
||||||
|
};
|
||||||
|
|
||||||
|
&spi0 {
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
spi_nand: spi_nand@0 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
compatible = "spi-nand";
|
||||||
|
reg = <1>;
|
||||||
|
spi-max-frequency = <10000000>;
|
||||||
|
spi-tx-bus-width = <4>;
|
||||||
|
spi-rx-bus-width = <4>;
|
||||||
|
|
||||||
|
partitions {
|
||||||
|
compatible = "fixed-partitions";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
partition@0 {
|
||||||
|
label = "BL2";
|
||||||
|
reg = <0x00000 0x0100000>;
|
||||||
|
read-only;
|
||||||
|
};
|
||||||
|
partition@100000 {
|
||||||
|
label = "u-boot-env";
|
||||||
|
reg = <0x0100000 0x0080000>;
|
||||||
|
};
|
||||||
|
factory: partition@180000 {
|
||||||
|
label = "Factory";
|
||||||
|
reg = <0x180000 0x0200000>;
|
||||||
|
};
|
||||||
|
partition@380000 {
|
||||||
|
label = "FIP";
|
||||||
|
reg = <0x380000 0x0200000>;
|
||||||
|
};
|
||||||
|
partition@580000 {
|
||||||
|
label = "ubi";
|
||||||
|
reg = <0x580000 0x4000000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&wifi {
|
||||||
|
mediatek,mtd-eeprom = <&factory 0>;
|
||||||
|
};
|
|
@ -0,0 +1,51 @@
|
||||||
|
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
|
||||||
|
|
||||||
|
#include "mt7986a-rfb.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "mediatek,mt7986a-rfb-snor";
|
||||||
|
};
|
||||||
|
|
||||||
|
&spi0 {
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
spi_nor: spi_nor@0 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
compatible = "jedec,spi-nor";
|
||||||
|
reg = <0>;
|
||||||
|
spi-max-frequency = <52000000>;
|
||||||
|
spi-tx-bus-width = <4>;
|
||||||
|
spi-rx-bus-width = <4>;
|
||||||
|
partitions {
|
||||||
|
compatible = "fixed-partitions";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
partition@00000 {
|
||||||
|
label = "BL2";
|
||||||
|
reg = <0x00000 0x0040000>;
|
||||||
|
};
|
||||||
|
partition@40000 {
|
||||||
|
label = "u-boot-env";
|
||||||
|
reg = <0x40000 0x0010000>;
|
||||||
|
};
|
||||||
|
factory: partition@50000 {
|
||||||
|
label = "Factory";
|
||||||
|
reg = <0x50000 0x00B0000>;
|
||||||
|
};
|
||||||
|
partition@100000 {
|
||||||
|
label = "FIP";
|
||||||
|
reg = <0x100000 0x0080000>;
|
||||||
|
};
|
||||||
|
partition@180000 {
|
||||||
|
label = "firmware";
|
||||||
|
reg = <0x180000 0xE00000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&wifi {
|
||||||
|
mediatek,mtd-eeprom = <&factory 0>;
|
||||||
|
};
|
|
@ -0,0 +1,389 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2021 MediaTek Inc.
|
||||||
|
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
#include "mt7986a.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "MediaTek MT7986a RFB";
|
||||||
|
compatible = "mediatek,mt7986a-rfb";
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
serial0 = &uart0;
|
||||||
|
};
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
stdout-path = "serial0:115200n8";
|
||||||
|
};
|
||||||
|
|
||||||
|
memory {
|
||||||
|
reg = <0 0x40000000 0 0x40000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
reg_1p8v: regulator-1p8v {
|
||||||
|
compatible = "regulator-fixed";
|
||||||
|
regulator-name = "fixed-1.8V";
|
||||||
|
regulator-min-microvolt = <1800000>;
|
||||||
|
regulator-max-microvolt = <1800000>;
|
||||||
|
regulator-boot-on;
|
||||||
|
regulator-always-on;
|
||||||
|
};
|
||||||
|
|
||||||
|
reg_3p3v: regulator-3p3v {
|
||||||
|
compatible = "regulator-fixed";
|
||||||
|
regulator-name = "fixed-3.3V";
|
||||||
|
regulator-min-microvolt = <3300000>;
|
||||||
|
regulator-max-microvolt = <3300000>;
|
||||||
|
regulator-boot-on;
|
||||||
|
regulator-always-on;
|
||||||
|
};
|
||||||
|
|
||||||
|
reg_5v: regulator-5v {
|
||||||
|
compatible = "regulator-fixed";
|
||||||
|
regulator-name = "fixed-5V";
|
||||||
|
regulator-min-microvolt = <5000000>;
|
||||||
|
regulator-max-microvolt = <5000000>;
|
||||||
|
regulator-boot-on;
|
||||||
|
regulator-always-on;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
ð {
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
gmac0: mac@0 {
|
||||||
|
compatible = "mediatek,eth-mac";
|
||||||
|
reg = <0>;
|
||||||
|
phy-mode = "2500base-x";
|
||||||
|
|
||||||
|
fixed-link {
|
||||||
|
speed = <2500>;
|
||||||
|
full-duplex;
|
||||||
|
pause;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
gmac1: mac@1 {
|
||||||
|
compatible = "mediatek,eth-mac";
|
||||||
|
reg = <1>;
|
||||||
|
phy-mode = "2500base-x";
|
||||||
|
};
|
||||||
|
|
||||||
|
mdio: mdio-bus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&wifi {
|
||||||
|
status = "okay";
|
||||||
|
pinctrl-names = "default", "dbdc";
|
||||||
|
pinctrl-0 = <&wf_2g_5g_pins>;
|
||||||
|
pinctrl-1 = <&wf_dbdc_pins>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&mdio {
|
||||||
|
phy5: phy@5 {
|
||||||
|
compatible = "ethernet-phy-id67c9.de0a";
|
||||||
|
reg = <5>;
|
||||||
|
|
||||||
|
reset-gpios = <&pio 6 1>;
|
||||||
|
reset-deassert-us = <20000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
phy6: phy@6 {
|
||||||
|
compatible = "ethernet-phy-id67c9.de0a";
|
||||||
|
reg = <6>;
|
||||||
|
};
|
||||||
|
|
||||||
|
switch: switch@1f {
|
||||||
|
compatible = "mediatek,mt7531";
|
||||||
|
reg = <31>;
|
||||||
|
reset-gpios = <&pio 5 0>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&crypto {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&mmc0 {
|
||||||
|
pinctrl-names = "default", "state_uhs";
|
||||||
|
pinctrl-0 = <&mmc0_pins_default>;
|
||||||
|
pinctrl-1 = <&mmc0_pins_uhs>;
|
||||||
|
bus-width = <8>;
|
||||||
|
max-frequency = <200000000>;
|
||||||
|
cap-mmc-highspeed;
|
||||||
|
mmc-hs200-1_8v;
|
||||||
|
mmc-hs400-1_8v;
|
||||||
|
hs400-ds-delay = <0x14014>;
|
||||||
|
vmmc-supply = <®_3p3v>;
|
||||||
|
vqmmc-supply = <®_1p8v>;
|
||||||
|
non-removable;
|
||||||
|
no-sd;
|
||||||
|
no-sdio;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&pcie {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&pcie_pins>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&pcie_phy {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&pio {
|
||||||
|
mmc0_pins_default: mmc0-pins {
|
||||||
|
mux {
|
||||||
|
function = "emmc";
|
||||||
|
groups = "emmc_51";
|
||||||
|
};
|
||||||
|
conf-cmd-dat {
|
||||||
|
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
|
||||||
|
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
|
||||||
|
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
|
||||||
|
input-enable;
|
||||||
|
drive-strength = <4>;
|
||||||
|
mediatek,pull-up-adv = <1>; /* pull-up 10K */
|
||||||
|
};
|
||||||
|
conf-clk {
|
||||||
|
pins = "EMMC_CK";
|
||||||
|
drive-strength = <6>;
|
||||||
|
mediatek,pull-down-adv = <2>; /* pull-down 50K */
|
||||||
|
};
|
||||||
|
conf-ds {
|
||||||
|
pins = "EMMC_DSL";
|
||||||
|
mediatek,pull-down-adv = <2>; /* pull-down 50K */
|
||||||
|
};
|
||||||
|
conf-rst {
|
||||||
|
pins = "EMMC_RSTB";
|
||||||
|
drive-strength = <4>;
|
||||||
|
mediatek,pull-up-adv = <1>; /* pull-up 10K */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
mmc0_pins_uhs: mmc0-uhs-pins {
|
||||||
|
mux {
|
||||||
|
function = "emmc";
|
||||||
|
groups = "emmc_51";
|
||||||
|
};
|
||||||
|
conf-cmd-dat {
|
||||||
|
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
|
||||||
|
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
|
||||||
|
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
|
||||||
|
input-enable;
|
||||||
|
drive-strength = <4>;
|
||||||
|
mediatek,pull-up-adv = <1>; /* pull-up 10K */
|
||||||
|
};
|
||||||
|
conf-clk {
|
||||||
|
pins = "EMMC_CK";
|
||||||
|
drive-strength = <6>;
|
||||||
|
mediatek,pull-down-adv = <2>; /* pull-down 50K */
|
||||||
|
};
|
||||||
|
conf-ds {
|
||||||
|
pins = "EMMC_DSL";
|
||||||
|
mediatek,pull-down-adv = <2>; /* pull-down 50K */
|
||||||
|
};
|
||||||
|
conf-rst {
|
||||||
|
pins = "EMMC_RSTB";
|
||||||
|
drive-strength = <4>;
|
||||||
|
mediatek,pull-up-adv = <1>; /* pull-up 10K */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pcie_pins: pcie-pins {
|
||||||
|
mux {
|
||||||
|
function = "pcie";
|
||||||
|
groups = "pcie_clk", "pcie_wake", "pcie_pereset";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
spic_pins_g2: spic-pins-29-to-32 {
|
||||||
|
mux {
|
||||||
|
function = "spi";
|
||||||
|
groups = "spi1_2";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
spi_flash_pins: spi-flash-pins-33-to-38 {
|
||||||
|
mux {
|
||||||
|
function = "spi";
|
||||||
|
groups = "spi0", "spi0_wp_hold";
|
||||||
|
};
|
||||||
|
conf-pu {
|
||||||
|
pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
|
||||||
|
drive-strength = <8>;
|
||||||
|
mediatek,pull-up-adv = <0>; /* bias-disable */
|
||||||
|
};
|
||||||
|
conf-pd {
|
||||||
|
pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
|
||||||
|
drive-strength = <8>;
|
||||||
|
mediatek,pull-down-adv = <0>; /* bias-disable */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
uart1_pins: uart1-pins {
|
||||||
|
mux {
|
||||||
|
function = "uart";
|
||||||
|
groups = "uart1";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
uart2_pins: uart2-pins {
|
||||||
|
mux {
|
||||||
|
function = "uart";
|
||||||
|
groups = "uart2";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
wf_2g_5g_pins: wf_2g_5g-pins {
|
||||||
|
mux {
|
||||||
|
function = "wifi";
|
||||||
|
groups = "wf_2g", "wf_5g";
|
||||||
|
};
|
||||||
|
conf {
|
||||||
|
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
|
||||||
|
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
|
||||||
|
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
|
||||||
|
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
|
||||||
|
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
|
||||||
|
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
|
||||||
|
"WF1_TOP_CLK", "WF1_TOP_DATA";
|
||||||
|
drive-strength = <4>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
wf_dbdc_pins: wf_dbdc-pins {
|
||||||
|
mux {
|
||||||
|
function = "wifi";
|
||||||
|
groups = "wf_dbdc";
|
||||||
|
};
|
||||||
|
conf {
|
||||||
|
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
|
||||||
|
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
|
||||||
|
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
|
||||||
|
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
|
||||||
|
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
|
||||||
|
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
|
||||||
|
"WF1_TOP_CLK", "WF1_TOP_DATA";
|
||||||
|
drive-strength = <4>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&spi0 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&spi_flash_pins>;
|
||||||
|
cs-gpios = <0>, <0>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
&spi1 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&spic_pins_g2>;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
proslic_spi: proslic_spi@0 {
|
||||||
|
compatible = "silabs,proslic_spi";
|
||||||
|
reg = <0>;
|
||||||
|
spi-max-frequency = <10000000>;
|
||||||
|
spi-cpha = <1>;
|
||||||
|
spi-cpol = <1>;
|
||||||
|
channel_count = <1>;
|
||||||
|
debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */
|
||||||
|
reset_gpio = <&pio 7 0>;
|
||||||
|
ig,enable-spi = <1>; /* 1: Enable, 0: Disable */
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&gmac1 {
|
||||||
|
phy-mode = "2500base-x";
|
||||||
|
phy-connection-type = "2500base-x";
|
||||||
|
phy-handle = <&phy6>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&switch {
|
||||||
|
ports {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
port@0 {
|
||||||
|
reg = <0>;
|
||||||
|
label = "lan1";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@1 {
|
||||||
|
reg = <1>;
|
||||||
|
label = "lan2";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@2 {
|
||||||
|
reg = <2>;
|
||||||
|
label = "lan3";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@3 {
|
||||||
|
reg = <3>;
|
||||||
|
label = "lan4";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@4 {
|
||||||
|
reg = <4>;
|
||||||
|
label = "wan";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@5 {
|
||||||
|
reg = <5>;
|
||||||
|
label = "lan6";
|
||||||
|
|
||||||
|
phy-mode = "2500base-x";
|
||||||
|
phy-handle = <&phy5>;
|
||||||
|
};
|
||||||
|
|
||||||
|
port@6 {
|
||||||
|
reg = <6>;
|
||||||
|
ethernet = <&gmac0>;
|
||||||
|
phy-mode = "2500base-x";
|
||||||
|
|
||||||
|
fixed-link {
|
||||||
|
speed = <2500>;
|
||||||
|
full-duplex;
|
||||||
|
pause;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&ssusb {
|
||||||
|
vusb33-supply = <®_3p3v>;
|
||||||
|
vbus-supply = <®_5v>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&uart0 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&uart1 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&uart1_pins>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&uart2 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&uart2_pins>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&usb_phy {
|
||||||
|
status = "okay";
|
||||||
|
};
|
|
@ -0,0 +1,62 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2021 MediaTek Inc.
|
||||||
|
* Author: Frank Wunderlich <frank-w@public-files.de>
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
|
||||||
|
|
||||||
|
fragment@0 {
|
||||||
|
target-path = "/soc/mmc@11230000";
|
||||||
|
__overlay__ {
|
||||||
|
pinctrl-names = "default", "state_uhs";
|
||||||
|
pinctrl-0 = <&mmc0_pins_emmc_51>;
|
||||||
|
pinctrl-1 = <&mmc0_pins_emmc_51>;
|
||||||
|
bus-width = <8>;
|
||||||
|
max-frequency = <200000000>;
|
||||||
|
cap-mmc-highspeed;
|
||||||
|
mmc-hs200-1_8v;
|
||||||
|
mmc-hs400-1_8v;
|
||||||
|
hs400-ds-delay = <0x12814>;
|
||||||
|
vqmmc-supply = <®_1p8v>;
|
||||||
|
vmmc-supply = <®_3p3v>;
|
||||||
|
non-removable;
|
||||||
|
no-sd;
|
||||||
|
no-sdio;
|
||||||
|
status = "okay";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
card@0 {
|
||||||
|
compatible = "mmc-card";
|
||||||
|
reg = <0>;
|
||||||
|
|
||||||
|
block {
|
||||||
|
compatible = "block-device";
|
||||||
|
partitions {
|
||||||
|
block-partition-env {
|
||||||
|
partname = "ubootenv";
|
||||||
|
nvmem-layout {
|
||||||
|
compatible = "u-boot,env-layout";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
emmc_rootfs: block-partition-production {
|
||||||
|
partname = "production";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
fragment@2 {
|
||||||
|
target-path = "/chosen";
|
||||||
|
__overlay__ {
|
||||||
|
rootdisk-emmc = <&emmc_rootfs>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
|
@ -0,0 +1,25 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2022 MediaTek Inc.
|
||||||
|
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "mt7988a-bananapi-bpi-r4.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Bananapi BPI-R4 2.5GE PoE";
|
||||||
|
compatible = "bananapi,bpi-r4-poe",
|
||||||
|
"mediatek,mt7988a";
|
||||||
|
};
|
||||||
|
|
||||||
|
&gmac1 {
|
||||||
|
phy-mode = "internal";
|
||||||
|
phy-connection-type = "internal";
|
||||||
|
phy = <&int_2p5g_phy>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&int_2p5g_phy {
|
||||||
|
pinctrl-names = "i2p5gbe-led";
|
||||||
|
pinctrl-0 = <&i2p5gbe_led0_pins>;
|
||||||
|
};
|
|
@ -0,0 +1,19 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2023
|
||||||
|
* Author: Daniel Golle <daniel@makrotopia.org>
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
|
||||||
|
|
||||||
|
fragment@0 {
|
||||||
|
target = <&pcf8563>;
|
||||||
|
__overlay__ {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
|
@ -0,0 +1,60 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2023 MediaTek Inc.
|
||||||
|
* Author: Frank Wunderlich <frank-w@public-files.de>
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include <dt-bindings/gpio/gpio.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
|
||||||
|
|
||||||
|
fragment@1 {
|
||||||
|
target-path = "/soc/mmc@11230000";
|
||||||
|
__overlay__ {
|
||||||
|
pinctrl-names = "default", "state_uhs";
|
||||||
|
pinctrl-0 = <&mmc0_pins_sdcard>;
|
||||||
|
pinctrl-1 = <&mmc0_pins_sdcard>;
|
||||||
|
cd-gpios = <&pio 12 GPIO_ACTIVE_LOW>;
|
||||||
|
bus-width = <4>;
|
||||||
|
max-frequency = <52000000>;
|
||||||
|
cap-sd-highspeed;
|
||||||
|
vmmc-supply = <®_3p3v>;
|
||||||
|
vqmmc-supply = <®_3p3v>;
|
||||||
|
no-mmc;
|
||||||
|
status = "okay";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
card@0 {
|
||||||
|
compatible = "mmc-card";
|
||||||
|
reg = <0>;
|
||||||
|
|
||||||
|
block {
|
||||||
|
compatible = "block-device";
|
||||||
|
partitions {
|
||||||
|
block-partition-env {
|
||||||
|
partname = "ubootenv";
|
||||||
|
nvmem-layout {
|
||||||
|
compatible = "u-boot,env-layout";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
sd_rootfs: block-partition-production {
|
||||||
|
partname = "production";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
fragment@2 {
|
||||||
|
target-path = "/chosen";
|
||||||
|
__overlay__ {
|
||||||
|
rootdisk-sd = <&sd_rootfs>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
|
@ -0,0 +1,99 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include <dt-bindings/gpio/gpio.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "bananapi,bpi-r4", "mediatek,mt7988a";
|
||||||
|
|
||||||
|
fragment@0 {
|
||||||
|
target-path = "/";
|
||||||
|
__overlay__ {
|
||||||
|
wifi_12v: regulator-wifi-12v {
|
||||||
|
compatible = "regulator-fixed";
|
||||||
|
regulator-name = "wifi";
|
||||||
|
regulator-min-microvolt = <12000000>;
|
||||||
|
regulator-max-microvolt = <12000000>;
|
||||||
|
gpios = <&pio 4 GPIO_ACTIVE_HIGH>;
|
||||||
|
enable-active-high;
|
||||||
|
regulator-always-on;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
fragment@1 {
|
||||||
|
target = <&i2c_wifi>;
|
||||||
|
__overlay__ {
|
||||||
|
// 5G WIFI MAC Address EEPROM
|
||||||
|
wifi_eeprom@51 {
|
||||||
|
compatible = "atmel,24c02";
|
||||||
|
reg = <0x51>;
|
||||||
|
address-bits = <8>;
|
||||||
|
page-size = <8>;
|
||||||
|
size = <256>;
|
||||||
|
|
||||||
|
nvmem-layout {
|
||||||
|
compatible = "fixed-layout";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
macaddr_5g: macaddr@0 {
|
||||||
|
reg = <0x0 0x6>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
// 6G WIFI MAC Address EEPROM
|
||||||
|
wifi_eeprom@52 {
|
||||||
|
compatible = "atmel,24c02";
|
||||||
|
reg = <0x52>;
|
||||||
|
address-bits = <8>;
|
||||||
|
page-size = <8>;
|
||||||
|
size = <256>;
|
||||||
|
|
||||||
|
nvmem-layout {
|
||||||
|
compatible = "fixed-layout";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
macaddr_6g: macaddr@0 {
|
||||||
|
reg = <0x0 0x6>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
fragment@2 {
|
||||||
|
target = <&pcie0>;
|
||||||
|
__overlay__ {
|
||||||
|
pcie@0,0 {
|
||||||
|
reg = <0x0000 0 0 0 0>;
|
||||||
|
|
||||||
|
wifi@0,0 {
|
||||||
|
compatible = "mediatek,mt76";
|
||||||
|
reg = <0x0000 0 0 0 0>;
|
||||||
|
nvmem-cell-names = "mac-address";
|
||||||
|
nvmem-cells = <&macaddr_5g>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
fragment@3 {
|
||||||
|
target = <&pcie1>;
|
||||||
|
__overlay__ {
|
||||||
|
pcie@0,0 {
|
||||||
|
reg = <0x0000 0 0 0 0>;
|
||||||
|
|
||||||
|
wifi@0,0 {
|
||||||
|
compatible = "mediatek,mt76";
|
||||||
|
reg = <0x0000 0 0 0 0>;
|
||||||
|
nvmem-cell-names = "mac-address";
|
||||||
|
nvmem-cells = <&macaddr_6g>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
|
@ -0,0 +1,40 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2022 MediaTek Inc.
|
||||||
|
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "mt7988a-bananapi-bpi-r4.dtsi"
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Bananapi BPI-R4";
|
||||||
|
compatible = "bananapi,bpi-r4",
|
||||||
|
"mediatek,mt7988a";
|
||||||
|
|
||||||
|
/* SFP2 cage (LAN) */
|
||||||
|
sfp2: sfp2 {
|
||||||
|
compatible = "sff,sfp";
|
||||||
|
i2c-bus = <&i2c_sfp2>;
|
||||||
|
los-gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
|
||||||
|
mod-def0-gpios = <&pio 83 GPIO_ACTIVE_LOW>;
|
||||||
|
tx-disable-gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
|
||||||
|
tx-fault-gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
|
||||||
|
rate-select0-gpios = <&pio 3 GPIO_ACTIVE_LOW>;
|
||||||
|
maximum-power-milliwatt = <3000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&gmac1 {
|
||||||
|
sfp = <&sfp2>;
|
||||||
|
managed = "in-band-status";
|
||||||
|
phy-mode = "usxgmii";
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&pca9545 {
|
||||||
|
i2c_sfp2: i2c@2 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
reg = <2>;
|
||||||
|
};
|
||||||
|
};
|
|
@ -0,0 +1,393 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2022 MediaTek Inc.
|
||||||
|
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
#include "mt7988a.dtsi"
|
||||||
|
#include <dt-bindings/gpio/gpio.h>
|
||||||
|
#include <dt-bindings/input/input.h>
|
||||||
|
#include <dt-bindings/leds/common.h>
|
||||||
|
#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "Bananapi BPI-R4";
|
||||||
|
compatible = "bananapi,bpi-r4",
|
||||||
|
"mediatek,mt7988a";
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
ethernet0 = &gmac0;
|
||||||
|
ethernet1 = &gmac1;
|
||||||
|
led-boot = &led_green;
|
||||||
|
led-failsafe = &led_green;
|
||||||
|
led-running = &led_green;
|
||||||
|
led-upgrade = &led_green;
|
||||||
|
serial0 = &uart0;
|
||||||
|
};
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
stdout-path = &uart0;
|
||||||
|
bootargs = "console=ttyS0,115200n1 loglevel=8 pci=pcie_bus_perf ubi.block=0,fit root=/dev/fit0 rootwait";
|
||||||
|
rootdisk-spim-nand = <&ubi_rootfs>;
|
||||||
|
};
|
||||||
|
|
||||||
|
memory {
|
||||||
|
reg = <0x00 0x40000000 0x00 0x10000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
/* SFP1 cage (WAN) */
|
||||||
|
sfp1: sfp1 {
|
||||||
|
compatible = "sff,sfp";
|
||||||
|
i2c-bus = <&i2c_sfp1>;
|
||||||
|
los-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
|
||||||
|
mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
|
||||||
|
tx-disable-gpios = <&pio 70 GPIO_ACTIVE_HIGH>;
|
||||||
|
tx-fault-gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
|
||||||
|
rate-select0-gpios = <&pio 21 GPIO_ACTIVE_LOW>;
|
||||||
|
maximum-power-milliwatt = <3000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gpio-keys {
|
||||||
|
compatible = "gpio-keys";
|
||||||
|
|
||||||
|
wps {
|
||||||
|
label = "WPS";
|
||||||
|
linux,code = <KEY_RESTART>;
|
||||||
|
gpios = <&pio 14 GPIO_ACTIVE_LOW>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
gpio-leds {
|
||||||
|
compatible = "gpio-leds";
|
||||||
|
|
||||||
|
led_green: led-green {
|
||||||
|
function = LED_FUNCTION_STATUS;
|
||||||
|
color = <LED_COLOR_ID_GREEN>;
|
||||||
|
gpios = <&pio 79 GPIO_ACTIVE_HIGH>;
|
||||||
|
default-state = "on";
|
||||||
|
};
|
||||||
|
|
||||||
|
led_blue: led-blue {
|
||||||
|
function = LED_FUNCTION_WPS;
|
||||||
|
color = <LED_COLOR_ID_BLUE>;
|
||||||
|
gpios = <&pio 63 GPIO_ACTIVE_HIGH>;
|
||||||
|
default-state = "off";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
ð {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&gmac0 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&gmac2 {
|
||||||
|
sfp = <&sfp1>;
|
||||||
|
managed = "in-band-status";
|
||||||
|
phy-mode = "usxgmii";
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&switch {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&gsw_phy0 {
|
||||||
|
pinctrl-names = "gbe-led";
|
||||||
|
pinctrl-0 = <&gbe0_led0_pins>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gsw_port0 {
|
||||||
|
label = "wan";
|
||||||
|
};
|
||||||
|
|
||||||
|
&gsw_phy0_led0 {
|
||||||
|
status = "okay";
|
||||||
|
color = <LED_COLOR_ID_GREEN>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gsw_phy1 {
|
||||||
|
pinctrl-names = "gbe-led";
|
||||||
|
pinctrl-0 = <&gbe1_led0_pins>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gsw_phy1_led0 {
|
||||||
|
status = "okay";
|
||||||
|
color = <LED_COLOR_ID_GREEN>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gsw_phy2 {
|
||||||
|
pinctrl-names = "gbe-led";
|
||||||
|
pinctrl-0 = <&gbe2_led0_pins>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gsw_phy2_led0 {
|
||||||
|
status = "okay";
|
||||||
|
color = <LED_COLOR_ID_GREEN>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gsw_phy3 {
|
||||||
|
pinctrl-names = "gbe-led";
|
||||||
|
pinctrl-0 = <&gbe3_led0_pins>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gsw_phy3_led0 {
|
||||||
|
status = "okay";
|
||||||
|
color = <LED_COLOR_ID_GREEN>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&cpu0 {
|
||||||
|
proc-supply = <&rt5190_buck3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&cpu1 {
|
||||||
|
proc-supply = <&rt5190_buck3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&cpu2 {
|
||||||
|
proc-supply = <&rt5190_buck3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&cpu3 {
|
||||||
|
proc-supply = <&rt5190_buck3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&cci {
|
||||||
|
proc-supply = <&rt5190_buck3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&i2c0 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&i2c0_pins>;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
rt5190a_64: rt5190a@64 {
|
||||||
|
compatible = "richtek,rt5190a";
|
||||||
|
reg = <0x64>;
|
||||||
|
vin2-supply = <&rt5190_buck1>;
|
||||||
|
vin3-supply = <&rt5190_buck1>;
|
||||||
|
vin4-supply = <&rt5190_buck1>;
|
||||||
|
|
||||||
|
regulators {
|
||||||
|
rt5190_buck1: buck1 {
|
||||||
|
regulator-name = "rt5190a-buck1";
|
||||||
|
regulator-min-microvolt = <5090000>;
|
||||||
|
regulator-max-microvolt = <5090000>;
|
||||||
|
regulator-allowed-modes =
|
||||||
|
<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
|
||||||
|
regulator-boot-on;
|
||||||
|
regulator-always-on;
|
||||||
|
};
|
||||||
|
buck2 {
|
||||||
|
regulator-name = "vcore";
|
||||||
|
regulator-min-microvolt = <600000>;
|
||||||
|
regulator-max-microvolt = <1400000>;
|
||||||
|
regulator-boot-on;
|
||||||
|
regulator-always-on;
|
||||||
|
};
|
||||||
|
rt5190_buck3: buck3 {
|
||||||
|
regulator-name = "vproc";
|
||||||
|
regulator-min-microvolt = <600000>;
|
||||||
|
regulator-max-microvolt = <1400000>;
|
||||||
|
regulator-boot-on;
|
||||||
|
};
|
||||||
|
buck4 {
|
||||||
|
regulator-name = "rt5190a-buck4";
|
||||||
|
regulator-min-microvolt = <850000>;
|
||||||
|
regulator-max-microvolt = <850000>;
|
||||||
|
regulator-allowed-modes =
|
||||||
|
<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
|
||||||
|
regulator-boot-on;
|
||||||
|
regulator-always-on;
|
||||||
|
};
|
||||||
|
ldo {
|
||||||
|
regulator-name = "rt5190a-ldo";
|
||||||
|
regulator-min-microvolt = <1200000>;
|
||||||
|
regulator-max-microvolt = <1200000>;
|
||||||
|
regulator-boot-on;
|
||||||
|
regulator-always-on;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&i2c2 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&i2c2_1_pins>;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
pca9545: i2c-switch@70 {
|
||||||
|
reg = <0x70>;
|
||||||
|
compatible = "nxp,pca9545";
|
||||||
|
reset-gpios = <&pio 5 GPIO_ACTIVE_LOW>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
i2c_rtc: i2c@0 { //eeprom,rtc,ngff
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
reg = <0>;
|
||||||
|
|
||||||
|
eeprom@50 {
|
||||||
|
compatible = "atmel,24c02";
|
||||||
|
reg = <0x50>;
|
||||||
|
address-bits = <8>;
|
||||||
|
page-size = <8>;
|
||||||
|
size = <256>;
|
||||||
|
};
|
||||||
|
|
||||||
|
eeprom@57 {
|
||||||
|
compatible = "atmel,24c02";
|
||||||
|
reg = <0x57>;
|
||||||
|
address-bits = <8>;
|
||||||
|
page-size = <8>;
|
||||||
|
size = <256>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pcf8563: rtc@51 {
|
||||||
|
compatible = "nxp,pcf8563";
|
||||||
|
reg = <0x51>;
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c_sfp1: i2c@1 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
reg = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
i2c_wifi: i2c@3 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
reg = <3>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
/* mPCIe SIM2 */
|
||||||
|
&pcie0 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&pcie0_pins>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
/* mPCIe SIM3 */
|
||||||
|
&pcie1 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&pcie1_pins>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
/* M.2 key-B SIM1 */
|
||||||
|
&pcie2 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&pcie2_pins>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
/* M.2 key-M SSD */
|
||||||
|
&pcie3 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&pcie3_pins>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&pwm {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&fan {
|
||||||
|
pwms = <&pwm 0 50000>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&ssusb1 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&tphy {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&spi0 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&spi0_flash_pins>;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
spi_nand: spi_nand@0 {
|
||||||
|
compatible = "spi-nand";
|
||||||
|
reg = <0>;
|
||||||
|
spi-max-frequency = <52000000>;
|
||||||
|
spi-tx-buswidth = <4>;
|
||||||
|
spi-rx-buswidth = <4>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&spi_nand {
|
||||||
|
partitions {
|
||||||
|
compatible = "fixed-partitions";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
partition@0 {
|
||||||
|
label = "bl2";
|
||||||
|
reg = <0x0 0x200000>;
|
||||||
|
read-only;
|
||||||
|
};
|
||||||
|
|
||||||
|
partition@200000 {
|
||||||
|
label = "ubi";
|
||||||
|
reg = <0x200000 0x7e00000>;
|
||||||
|
compatible = "linux,ubi";
|
||||||
|
|
||||||
|
volumes {
|
||||||
|
ubi-volume-ubootenv {
|
||||||
|
volname = "ubootenv";
|
||||||
|
nvmem-layout {
|
||||||
|
compatible = "u-boot,env-redundant-bool-layout";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
ubi-volume-ubootenv2 {
|
||||||
|
volname = "ubootenv2";
|
||||||
|
nvmem-layout {
|
||||||
|
compatible = "u-boot,env-redundant-bool-layout";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
ubi_rootfs: ubi-volume-fit {
|
||||||
|
volname = "fit";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&uart0 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&uart1 {
|
||||||
|
status = "okay";
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&uart1_2_lite_pins>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&uart2 {
|
||||||
|
status = "okay";
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&uart2_3_pins>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&watchdog {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&xphy {
|
||||||
|
status = "okay";
|
||||||
|
};
|
|
@ -0,0 +1,33 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2021 MediaTek Inc.
|
||||||
|
* Author: Frank Wunderlich <frank-w@public-files.de>
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
||||||
|
|
||||||
|
fragment@0 {
|
||||||
|
target = <&mmc0>;
|
||||||
|
__overlay__ {
|
||||||
|
pinctrl-names = "default", "state_uhs";
|
||||||
|
pinctrl-0 = <&mmc0_pins_emmc_51>;
|
||||||
|
pinctrl-1 = <&mmc0_pins_emmc_51>;
|
||||||
|
bus-width = <8>;
|
||||||
|
max-frequency = <200000000>;
|
||||||
|
cap-mmc-highspeed;
|
||||||
|
mmc-hs200-1_8v;
|
||||||
|
mmc-hs400-1_8v;
|
||||||
|
hs400-ds-delay = <0x12814>;
|
||||||
|
vqmmc-supply = <®_1p8v>;
|
||||||
|
vmmc-supply = <®_3p3v>;
|
||||||
|
non-removable;
|
||||||
|
no-sd;
|
||||||
|
no-sdio;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
|
@ -0,0 +1,42 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2022 MediaTek Inc.
|
||||||
|
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include <dt-bindings/gpio/gpio.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
||||||
|
|
||||||
|
fragment@0 {
|
||||||
|
target = <&mdio_bus>;
|
||||||
|
__overlay__ {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
/* external Aquantia AQR113C */
|
||||||
|
phy0: ethernet-phy@0 {
|
||||||
|
reg = <0>;
|
||||||
|
compatible = "ethernet-phy-ieee802.3-c45";
|
||||||
|
firmware-name = "AQR-G4_v5.7.0-AQR_EVB_Generic_X3410_StdCfg_MDISwap_USX_ID46316_VER2140.cld";
|
||||||
|
reset-gpios = <&pio 72 GPIO_ACTIVE_LOW>;
|
||||||
|
reset-assert-us = <100000>;
|
||||||
|
reset-deassert-us = <221000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
fragment@1 {
|
||||||
|
target = <&gmac1>;
|
||||||
|
__overlay__ {
|
||||||
|
phy-mode = "usxgmii";
|
||||||
|
phy-connection-type = "usxgmii";
|
||||||
|
phy = <&phy0>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
|
@ -0,0 +1,30 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2022 MediaTek Inc.
|
||||||
|
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
||||||
|
|
||||||
|
fragment@0 {
|
||||||
|
target = <&gmac1>;
|
||||||
|
__overlay__ {
|
||||||
|
phy-mode = "internal";
|
||||||
|
phy-connection-type = "internal";
|
||||||
|
phy = <&int_2p5g_phy>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
fragment@1 {
|
||||||
|
target = <&int_2p5g_phy>;
|
||||||
|
__overlay__ {
|
||||||
|
pinctrl-names = "i2p5gbe-led";
|
||||||
|
pinctrl-0 = <&i2p5gbe_led0_pins>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
|
@ -0,0 +1,39 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2022 MediaTek Inc.
|
||||||
|
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include <dt-bindings/gpio/gpio.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
||||||
|
|
||||||
|
fragment@0 {
|
||||||
|
target = <&mdio_bus>;
|
||||||
|
__overlay__ {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
/* external Maxlinear GPY211C */
|
||||||
|
phy13: ethernet-phy@13 {
|
||||||
|
reg = <13>;
|
||||||
|
compatible = "ethernet-phy-ieee802.3-c45";
|
||||||
|
phy-mode = "2500base-x";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
fragment@1 {
|
||||||
|
target = <&gmac1>;
|
||||||
|
__overlay__ {
|
||||||
|
phy-mode = "2500base-x";
|
||||||
|
phy-connection-type = "2500base-x";
|
||||||
|
phy = <&phy13>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
|
@ -0,0 +1,47 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2022 MediaTek Inc.
|
||||||
|
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include <dt-bindings/gpio/gpio.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
||||||
|
|
||||||
|
fragment@0 {
|
||||||
|
target = <&i2c2>;
|
||||||
|
__overlay__ {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&i2c2_0_pins>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
fragment@1 {
|
||||||
|
target-path = "/";
|
||||||
|
__overlay__ {
|
||||||
|
sfp_esp1: sfp@1 {
|
||||||
|
compatible = "sff,sfp";
|
||||||
|
i2c-bus = <&i2c2>;
|
||||||
|
mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
|
||||||
|
los-gpios = <&pio 81 GPIO_ACTIVE_HIGH>;
|
||||||
|
tx-disable-gpios = <&pio 36 GPIO_ACTIVE_HIGH>;
|
||||||
|
maximum-power-milliwatt = <3000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
fragment@2 {
|
||||||
|
target = <&gmac1>;
|
||||||
|
__overlay__ {
|
||||||
|
phy-mode = "10gbase-r";
|
||||||
|
managed = "in-band-status";
|
||||||
|
sfp = <&sfp_esp1>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
|
@ -0,0 +1,42 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2022 MediaTek Inc.
|
||||||
|
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include <dt-bindings/gpio/gpio.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
||||||
|
|
||||||
|
fragment@0 {
|
||||||
|
target = <&mdio_bus>;
|
||||||
|
__overlay__ {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
/* external Aquantia AQR113C */
|
||||||
|
phy8: ethernet-phy@8 {
|
||||||
|
reg = <8>;
|
||||||
|
compatible = "ethernet-phy-ieee802.3-c45";
|
||||||
|
firmware-name = "AQR-G4_v5.7.0-AQR_EVB_Generic_X3410_StdCfg_MDISwap_USX_ID46316_VER2140.cld";
|
||||||
|
reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>;
|
||||||
|
reset-assert-us = <100000>;
|
||||||
|
reset-deassert-us = <221000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
fragment@1 {
|
||||||
|
target = <&gmac2>;
|
||||||
|
__overlay__ {
|
||||||
|
phy-mode = "usxgmii";
|
||||||
|
phy-connection-type = "usxgmii";
|
||||||
|
phy = <&phy8>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
|
@ -0,0 +1,39 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2022 MediaTek Inc.
|
||||||
|
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include <dt-bindings/gpio/gpio.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
||||||
|
|
||||||
|
fragment@0 {
|
||||||
|
target = <&mdio_bus>;
|
||||||
|
__overlay__ {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
/* external Maxlinear GPY211C */
|
||||||
|
phy5: ethernet-phy@5 {
|
||||||
|
reg = <5>;
|
||||||
|
compatible = "ethernet-phy-ieee802.3-c45";
|
||||||
|
phy-mode = "2500base-x";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
fragment@1 {
|
||||||
|
target = <&gmac2>;
|
||||||
|
__overlay__ {
|
||||||
|
phy-mode = "2500base-x";
|
||||||
|
phy-connection-type = "2500base-x";
|
||||||
|
phy = <&phy5>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
|
@ -0,0 +1,47 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2022 MediaTek Inc.
|
||||||
|
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include <dt-bindings/gpio/gpio.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
||||||
|
|
||||||
|
fragment@0 {
|
||||||
|
target = <&i2c1>;
|
||||||
|
__overlay__ {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&i2c1_sfp_pins>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
fragment@1 {
|
||||||
|
target-path = "/";
|
||||||
|
__overlay__ {
|
||||||
|
sfp_esp0: sfp@0 {
|
||||||
|
compatible = "sff,sfp";
|
||||||
|
i2c-bus = <&i2c1>;
|
||||||
|
mod-def0-gpios = <&pio 35 GPIO_ACTIVE_LOW>;
|
||||||
|
los-gpios = <&pio 33 GPIO_ACTIVE_HIGH>;
|
||||||
|
tx-disable-gpios = <&pio 29 GPIO_ACTIVE_HIGH>;
|
||||||
|
maximum-power-milliwatt = <3000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
fragment@2 {
|
||||||
|
target = <&gmac2>;
|
||||||
|
__overlay__ {
|
||||||
|
phy-mode = "10gbase-r";
|
||||||
|
managed = "in-band-status";
|
||||||
|
sfp = <&sfp_esp0>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
|
@ -0,0 +1,31 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2023 MediaTek Inc.
|
||||||
|
* Author: Frank Wunderlich <frank-w@public-files.de>
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
#include <dt-bindings/gpio/gpio.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
||||||
|
|
||||||
|
fragment@1 {
|
||||||
|
target-path = <&mmc0>;
|
||||||
|
__overlay__ {
|
||||||
|
pinctrl-names = "default", "state_uhs";
|
||||||
|
pinctrl-0 = <&mmc0_pins_sdcard>;
|
||||||
|
pinctrl-1 = <&mmc0_pins_sdcard>;
|
||||||
|
cd-gpios = <&pio 69 GPIO_ACTIVE_LOW>;
|
||||||
|
bus-width = <4>;
|
||||||
|
max-frequency = <52000000>;
|
||||||
|
cap-sd-highspeed;
|
||||||
|
vmmc-supply = <®_3p3v>;
|
||||||
|
vqmmc-supply = <®_3p3v>;
|
||||||
|
no-mmc;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
|
@ -0,0 +1,69 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2022 MediaTek Inc.
|
||||||
|
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
||||||
|
|
||||||
|
fragment@0 {
|
||||||
|
target = <&snand>;
|
||||||
|
__overlay__ {
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
flash@0 {
|
||||||
|
compatible = "spi-nand";
|
||||||
|
reg = <0>;
|
||||||
|
spi-max-frequency = <52000000>;
|
||||||
|
spi-tx-bus-width = <4>;
|
||||||
|
spi-rx-bus-width = <4>;
|
||||||
|
mediatek,nmbm;
|
||||||
|
mediatek,bmt-max-ratio = <1>;
|
||||||
|
mediatek,bmt-max-reserved-blocks = <64>;
|
||||||
|
|
||||||
|
partitions {
|
||||||
|
compatible = "fixed-partitions";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
partition@0 {
|
||||||
|
label = "BL2";
|
||||||
|
reg = <0x00000 0x0100000>;
|
||||||
|
read-only;
|
||||||
|
};
|
||||||
|
|
||||||
|
partition@100000 {
|
||||||
|
label = "u-boot-env";
|
||||||
|
reg = <0x0100000 0x0080000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
partition@180000 {
|
||||||
|
label = "Factory";
|
||||||
|
reg = <0x180000 0x0400000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
partition@580000 {
|
||||||
|
label = "FIP";
|
||||||
|
reg = <0x580000 0x0200000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
partition@780000 {
|
||||||
|
label = "ubi";
|
||||||
|
reg = <0x780000 0x7080000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
fragment@1 {
|
||||||
|
target = <&bch>;
|
||||||
|
__overlay__ {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
|
@ -0,0 +1,82 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
||||||
|
|
||||||
|
fragment@0 {
|
||||||
|
target = <&ubi_part>;
|
||||||
|
|
||||||
|
__overlay__ {
|
||||||
|
volumes {
|
||||||
|
ubi_factory: ubi-volume-factory {
|
||||||
|
volname = "factory";
|
||||||
|
|
||||||
|
nvmem-layout {
|
||||||
|
compatible = "fixed-layout";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
eeprom_wmac: eeprom@0 {
|
||||||
|
reg = <0x0 0x1e00>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gmac2_mac: eeprom@fffee {
|
||||||
|
reg = <0xfffee 0x6>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gmac1_mac: eeprom@ffff4 {
|
||||||
|
reg = <0xffff4 0x6>;
|
||||||
|
};
|
||||||
|
|
||||||
|
gmac0_mac: eeprom@ffffa {
|
||||||
|
reg = <0xffffa 0x6>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
fragment@1 {
|
||||||
|
target = <&pcie0>;
|
||||||
|
__overlay__ {
|
||||||
|
pcie@0,0 {
|
||||||
|
reg = <0x0000 0 0 0 0>;
|
||||||
|
|
||||||
|
wifi@0,0 {
|
||||||
|
compatible = "mediatek,mt76";
|
||||||
|
reg = <0x0000 0 0 0 0>;
|
||||||
|
nvmem-cell-names = "eeprom";
|
||||||
|
nvmem-cells = <&eeprom_wmac>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
fragment@2 {
|
||||||
|
target = <&gmac0>;
|
||||||
|
__overlay__ {
|
||||||
|
nvmem-cell-names = "mac-address";
|
||||||
|
nvmem-cells = <&gmac0_mac>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
fragment@3 {
|
||||||
|
target = <&gmac1>;
|
||||||
|
__overlay__ {
|
||||||
|
nvmem-cell-names = "mac-address";
|
||||||
|
nvmem-cells = <&gmac1_mac>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
fragment@4 {
|
||||||
|
target = <&gmac2>;
|
||||||
|
__overlay__ {
|
||||||
|
nvmem-cell-names = "mac-address";
|
||||||
|
nvmem-cells = <&gmac2_mac>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
|
@ -0,0 +1,75 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2022 MediaTek Inc.
|
||||||
|
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
||||||
|
|
||||||
|
fragment@0 {
|
||||||
|
target = <&spi0>;
|
||||||
|
__overlay__ {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&spi0_flash_pins>;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
flash@0 {
|
||||||
|
compatible = "spi-nand";
|
||||||
|
reg = <0>;
|
||||||
|
spi-max-frequency = <52000000>;
|
||||||
|
spi-tx-bus-width = <4>;
|
||||||
|
spi-rx-bus-width = <4>;
|
||||||
|
|
||||||
|
partitions {
|
||||||
|
compatible = "fixed-partitions";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
partition@0 {
|
||||||
|
label = "BL2";
|
||||||
|
reg = <0x00000 0x0200000>;
|
||||||
|
read-only;
|
||||||
|
};
|
||||||
|
|
||||||
|
ubi_part: partition@200000 {
|
||||||
|
label = "ubi";
|
||||||
|
reg = <0x0200000 0x7e00000>;
|
||||||
|
compatible = "linux,ubi";
|
||||||
|
|
||||||
|
volumes {
|
||||||
|
ubi-volume-ubootenv {
|
||||||
|
volname = "ubootenv";
|
||||||
|
nvmem-layout {
|
||||||
|
compatible = "u-boot,env-redundant-bool-layout";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
ubi-volume-ubootenv2 {
|
||||||
|
volname = "ubootenv2";
|
||||||
|
nvmem-layout {
|
||||||
|
compatible = "u-boot,env-redundant-bool-layout";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
ubi_root: ubi-volume-fit {
|
||||||
|
volname = "fit";
|
||||||
|
};
|
||||||
|
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
fragment@1 {
|
||||||
|
target-path = "/chosen";
|
||||||
|
__overlay__ {
|
||||||
|
rootdisk-spim-nand = <&ubi_root>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
|
@ -0,0 +1,59 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2022 MediaTek Inc.
|
||||||
|
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
/plugin/;
|
||||||
|
|
||||||
|
/ {
|
||||||
|
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
||||||
|
|
||||||
|
fragment@0 {
|
||||||
|
target = <&spi2>;
|
||||||
|
__overlay__ {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&spi2_flash_pins>;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
flash@0 {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
compatible = "jedec,spi-nor";
|
||||||
|
spi-cal-enable;
|
||||||
|
spi-cal-mode = "read-data";
|
||||||
|
spi-cal-datalen = <7>;
|
||||||
|
spi-cal-data = /bits/ 8 <
|
||||||
|
0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; /* SF_BOOT */
|
||||||
|
spi-cal-addrlen = <1>;
|
||||||
|
spi-cal-addr = /bits/ 32 <0x0>;
|
||||||
|
reg = <0>;
|
||||||
|
spi-max-frequency = <52000000>;
|
||||||
|
spi-tx-bus-width = <4>;
|
||||||
|
spi-rx-bus-width = <4>;
|
||||||
|
|
||||||
|
partition@00000 {
|
||||||
|
label = "BL2";
|
||||||
|
reg = <0x00000 0x0040000>;
|
||||||
|
};
|
||||||
|
partition@40000 {
|
||||||
|
label = "u-boot-env";
|
||||||
|
reg = <0x40000 0x0010000>;
|
||||||
|
};
|
||||||
|
partition@50000 {
|
||||||
|
label = "Factory";
|
||||||
|
reg = <0x50000 0x0200000>;
|
||||||
|
};
|
||||||
|
partition@250000 {
|
||||||
|
label = "FIP";
|
||||||
|
reg = <0x250000 0x0080000>;
|
||||||
|
};
|
||||||
|
partition@2D0000 {
|
||||||
|
label = "firmware";
|
||||||
|
reg = <0x2D0000 0x1D30000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
|
@ -0,0 +1,200 @@
|
||||||
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2022 MediaTek Inc.
|
||||||
|
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
#include "mt7988a.dtsi"
|
||||||
|
#include <dt-bindings/pinctrl/mt65xx.h>
|
||||||
|
#include <dt-bindings/leds/common.h>
|
||||||
|
#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "MediaTek MT7988A Reference Board";
|
||||||
|
compatible = "mediatek,mt7988a-rfb",
|
||||||
|
"mediatek,mt7988a";
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
bootargs = "console=ttyS0,115200n1 loglevel=8 \
|
||||||
|
earlycon=uart8250,mmio32,0x11000000 \
|
||||||
|
pci=pcie_bus_perf";
|
||||||
|
};
|
||||||
|
|
||||||
|
memory {
|
||||||
|
reg = <0 0x40000000 0 0x40000000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
ð {
|
||||||
|
pinctrl-0 = <&mdio0_pins>;
|
||||||
|
pinctrl-names = "default";
|
||||||
|
};
|
||||||
|
|
||||||
|
&gmac0 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&cpu0 {
|
||||||
|
proc-supply = <&rt5190_buck3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&cpu1 {
|
||||||
|
proc-supply = <&rt5190_buck3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&cpu2 {
|
||||||
|
proc-supply = <&rt5190_buck3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&cpu3 {
|
||||||
|
proc-supply = <&rt5190_buck3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&cci {
|
||||||
|
proc-supply = <&rt5190_buck3>;
|
||||||
|
};
|
||||||
|
|
||||||
|
ð {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&switch {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&gsw_phy0 {
|
||||||
|
pinctrl-names = "gbe-led";
|
||||||
|
pinctrl-0 = <&gbe0_led0_pins>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gsw_phy0_led0 {
|
||||||
|
status = "okay";
|
||||||
|
color = <LED_COLOR_ID_GREEN>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gsw_phy1 {
|
||||||
|
pinctrl-names = "gbe-led";
|
||||||
|
pinctrl-0 = <&gbe1_led0_pins>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gsw_phy1_led0 {
|
||||||
|
status = "okay";
|
||||||
|
color = <LED_COLOR_ID_GREEN>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gsw_phy2 {
|
||||||
|
pinctrl-names = "gbe-led";
|
||||||
|
pinctrl-0 = <&gbe2_led0_pins>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gsw_phy2_led0 {
|
||||||
|
status = "okay";
|
||||||
|
color = <LED_COLOR_ID_GREEN>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gsw_phy3 {
|
||||||
|
pinctrl-names = "gbe-led";
|
||||||
|
pinctrl-0 = <&gbe3_led0_pins>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&gsw_phy3_led0 {
|
||||||
|
status = "okay";
|
||||||
|
color = <LED_COLOR_ID_GREEN>;
|
||||||
|
};
|
||||||
|
|
||||||
|
&i2c0 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&i2c0_pins>;
|
||||||
|
status = "okay";
|
||||||
|
|
||||||
|
rt5190a_64: rt5190a@64 {
|
||||||
|
compatible = "richtek,rt5190a";
|
||||||
|
reg = <0x64>;
|
||||||
|
/*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/
|
||||||
|
vin2-supply = <&rt5190_buck1>;
|
||||||
|
vin3-supply = <&rt5190_buck1>;
|
||||||
|
vin4-supply = <&rt5190_buck1>;
|
||||||
|
|
||||||
|
regulators {
|
||||||
|
rt5190_buck1: buck1 {
|
||||||
|
regulator-name = "rt5190a-buck1";
|
||||||
|
regulator-min-microvolt = <5090000>;
|
||||||
|
regulator-max-microvolt = <5090000>;
|
||||||
|
regulator-allowed-modes =
|
||||||
|
<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
|
||||||
|
regulator-boot-on;
|
||||||
|
regulator-always-on;
|
||||||
|
};
|
||||||
|
buck2 {
|
||||||
|
regulator-name = "vcore";
|
||||||
|
regulator-min-microvolt = <600000>;
|
||||||
|
regulator-max-microvolt = <1400000>;
|
||||||
|
regulator-boot-on;
|
||||||
|
regulator-always-on;
|
||||||
|
};
|
||||||
|
rt5190_buck3: buck3 {
|
||||||
|
regulator-name = "vproc";
|
||||||
|
regulator-min-microvolt = <600000>;
|
||||||
|
regulator-max-microvolt = <1400000>;
|
||||||
|
regulator-boot-on;
|
||||||
|
};
|
||||||
|
buck4 {
|
||||||
|
regulator-name = "rt5190a-buck4";
|
||||||
|
regulator-min-microvolt = <850000>;
|
||||||
|
regulator-max-microvolt = <850000>;
|
||||||
|
regulator-allowed-modes =
|
||||||
|
<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
|
||||||
|
regulator-boot-on;
|
||||||
|
regulator-always-on;
|
||||||
|
};
|
||||||
|
ldo {
|
||||||
|
regulator-name = "rt5190a-ldo";
|
||||||
|
regulator-min-microvolt = <1200000>;
|
||||||
|
regulator-max-microvolt = <1200000>;
|
||||||
|
regulator-boot-on;
|
||||||
|
regulator-always-on;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
&pcie0 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&pcie1 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&pcie2 {
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
&pcie3 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&ssusb0 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&ssusb1 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&tphy {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&uart0 {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&watchdog {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
&xphy {
|
||||||
|
status = "okay";
|
||||||
|
};
|
File diff suppressed because it is too large
Load diff
|
@ -0,0 +1,321 @@
|
||||||
|
// SPDX-License-Identifier: GPL-2.0+
|
||||||
|
#include <linux/bitfield.h>
|
||||||
|
#include <linux/firmware.h>
|
||||||
|
#include <linux/module.h>
|
||||||
|
#include <linux/nvmem-consumer.h>
|
||||||
|
#include <linux/of_address.h>
|
||||||
|
#include <linux/of_platform.h>
|
||||||
|
#include <linux/pinctrl/consumer.h>
|
||||||
|
#include <linux/phy.h>
|
||||||
|
#include <linux/pm_domain.h>
|
||||||
|
#include <linux/pm_runtime.h>
|
||||||
|
|
||||||
|
#define MT7988_2P5GE_PMB "mediatek/mt7988/i2p5ge-phy-pmb.bin"
|
||||||
|
|
||||||
|
#define MD32_EN BIT(0)
|
||||||
|
#define PMEM_PRIORITY BIT(8)
|
||||||
|
#define DMEM_PRIORITY BIT(16)
|
||||||
|
|
||||||
|
#define BASE100T_STATUS_EXTEND 0x10
|
||||||
|
#define BASE1000T_STATUS_EXTEND 0x11
|
||||||
|
#define EXTEND_CTRL_AND_STATUS 0x16
|
||||||
|
|
||||||
|
#define PHY_AUX_CTRL_STATUS 0x1d
|
||||||
|
#define PHY_AUX_DPX_MASK GENMASK(5, 5)
|
||||||
|
#define PHY_AUX_SPEED_MASK GENMASK(4, 2)
|
||||||
|
|
||||||
|
/* Registers on MDIO_MMD_VEND1 */
|
||||||
|
#define MTK_PHY_LINK_STATUS_MISC 0xa2
|
||||||
|
#define MTK_PHY_FDX_ENABLE BIT(5)
|
||||||
|
|
||||||
|
#define MTK_PHY_LPI_PCS_DSP_CTRL 0x121
|
||||||
|
#define MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK GENMASK(12, 8)
|
||||||
|
|
||||||
|
/* Registers on MDIO_MMD_VEND2 */
|
||||||
|
#define MTK_PHY_LED0_ON_CTRL 0x24
|
||||||
|
#define MTK_PHY_LED0_ON_LINK1000 BIT(0)
|
||||||
|
#define MTK_PHY_LED0_ON_LINK100 BIT(1)
|
||||||
|
#define MTK_PHY_LED0_ON_LINK10 BIT(2)
|
||||||
|
#define MTK_PHY_LED0_ON_LINK2500 BIT(7)
|
||||||
|
#define MTK_PHY_LED0_POLARITY BIT(14)
|
||||||
|
|
||||||
|
#define MTK_PHY_LED1_ON_CTRL 0x26
|
||||||
|
#define MTK_PHY_LED1_ON_FDX BIT(4)
|
||||||
|
#define MTK_PHY_LED1_ON_HDX BIT(5)
|
||||||
|
#define MTK_PHY_LED1_POLARITY BIT(14)
|
||||||
|
|
||||||
|
#define MTK_EXT_PAGE_ACCESS 0x1f
|
||||||
|
#define MTK_PHY_PAGE_STANDARD 0x0000
|
||||||
|
#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5
|
||||||
|
|
||||||
|
struct mtk_i2p5ge_phy_priv {
|
||||||
|
bool fw_loaded;
|
||||||
|
};
|
||||||
|
|
||||||
|
enum {
|
||||||
|
PHY_AUX_SPD_10 = 0,
|
||||||
|
PHY_AUX_SPD_100,
|
||||||
|
PHY_AUX_SPD_1000,
|
||||||
|
PHY_AUX_SPD_2500,
|
||||||
|
};
|
||||||
|
|
||||||
|
static int mtk_2p5ge_phy_read_page(struct phy_device *phydev)
|
||||||
|
{
|
||||||
|
return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mtk_2p5ge_phy_write_page(struct phy_device *phydev, int page)
|
||||||
|
{
|
||||||
|
return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mt7988_2p5ge_phy_probe(struct phy_device *phydev)
|
||||||
|
{
|
||||||
|
struct mtk_i2p5ge_phy_priv *phy_priv;
|
||||||
|
|
||||||
|
phy_priv = devm_kzalloc(&phydev->mdio.dev,
|
||||||
|
sizeof(struct mtk_i2p5ge_phy_priv), GFP_KERNEL);
|
||||||
|
if (!phy_priv)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
phydev->priv = phy_priv;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mt7988_2p5ge_phy_config_init(struct phy_device *phydev)
|
||||||
|
{
|
||||||
|
int ret, i;
|
||||||
|
const struct firmware *fw;
|
||||||
|
struct device *dev = &phydev->mdio.dev;
|
||||||
|
struct device_node *np;
|
||||||
|
void __iomem *pmb_addr;
|
||||||
|
void __iomem *md32_en_cfg_base;
|
||||||
|
struct mtk_i2p5ge_phy_priv *phy_priv = phydev->priv;
|
||||||
|
u16 reg;
|
||||||
|
struct pinctrl *pinctrl;
|
||||||
|
|
||||||
|
if (!phy_priv->fw_loaded) {
|
||||||
|
np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw");
|
||||||
|
if (!np)
|
||||||
|
return -ENOENT;
|
||||||
|
pmb_addr = of_iomap(np, 0);
|
||||||
|
if (!pmb_addr)
|
||||||
|
return -ENOMEM;
|
||||||
|
md32_en_cfg_base = of_iomap(np, 1);
|
||||||
|
if (!md32_en_cfg_base)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
ret = request_firmware(&fw, MT7988_2P5GE_PMB, dev);
|
||||||
|
if (ret) {
|
||||||
|
dev_err(dev, "failed to load firmware: %s, ret: %d\n",
|
||||||
|
MT7988_2P5GE_PMB, ret);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
reg = readw(md32_en_cfg_base);
|
||||||
|
if (reg & MD32_EN) {
|
||||||
|
phy_set_bits(phydev, 0, BIT(15));
|
||||||
|
usleep_range(10000, 11000);
|
||||||
|
}
|
||||||
|
phy_set_bits(phydev, 0, BIT(11));
|
||||||
|
|
||||||
|
/* Write magic number to safely stall MCU */
|
||||||
|
phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x800e, 0x1100);
|
||||||
|
phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x800f, 0x00df);
|
||||||
|
|
||||||
|
for (i = 0; i < fw->size - 1; i += 4)
|
||||||
|
writel(*((uint32_t *)(fw->data + i)), pmb_addr + i);
|
||||||
|
release_firmware(fw);
|
||||||
|
|
||||||
|
writew(reg & ~MD32_EN, md32_en_cfg_base);
|
||||||
|
writew(reg | MD32_EN, md32_en_cfg_base);
|
||||||
|
phy_set_bits(phydev, 0, BIT(15));
|
||||||
|
dev_info(dev, "Firmware loading/trigger ok.\n");
|
||||||
|
|
||||||
|
phy_priv->fw_loaded = true;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Setup LED */
|
||||||
|
|
||||||
|
/* Set polarity of led0 to active-high for BPI-R4 */
|
||||||
|
phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
|
||||||
|
MTK_PHY_LED0_POLARITY);
|
||||||
|
|
||||||
|
phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
|
||||||
|
MTK_PHY_LED0_ON_LINK10 |
|
||||||
|
MTK_PHY_LED0_ON_LINK100 |
|
||||||
|
MTK_PHY_LED0_ON_LINK1000 |
|
||||||
|
MTK_PHY_LED0_ON_LINK2500);
|
||||||
|
phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
|
||||||
|
MTK_PHY_LED1_ON_FDX | MTK_PHY_LED1_ON_HDX);
|
||||||
|
|
||||||
|
pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led");
|
||||||
|
if (IS_ERR(pinctrl)) {
|
||||||
|
dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n");
|
||||||
|
return PTR_ERR(pinctrl);
|
||||||
|
}
|
||||||
|
|
||||||
|
phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LPI_PCS_DSP_CTRL,
|
||||||
|
MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK, 0);
|
||||||
|
|
||||||
|
/* Enable 16-bit next page exchange bit if 1000-BT isn't advertizing */
|
||||||
|
phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
|
||||||
|
__phy_write(phydev, 0x11, 0xfbfa);
|
||||||
|
__phy_write(phydev, 0x12, 0xc3);
|
||||||
|
__phy_write(phydev, 0x10, 0x87f8);
|
||||||
|
phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mt7988_2p5ge_phy_config_aneg(struct phy_device *phydev)
|
||||||
|
{
|
||||||
|
bool changed = false;
|
||||||
|
u32 adv;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
if (phydev->autoneg == AUTONEG_DISABLE) {
|
||||||
|
/* Configure half duplex with genphy_setup_forced,
|
||||||
|
* because genphy_c45_pma_setup_forced does not support.
|
||||||
|
*/
|
||||||
|
return phydev->duplex != DUPLEX_FULL
|
||||||
|
? genphy_setup_forced(phydev)
|
||||||
|
: genphy_c45_pma_setup_forced(phydev);
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = genphy_c45_an_config_aneg(phydev);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
if (ret > 0)
|
||||||
|
changed = true;
|
||||||
|
|
||||||
|
adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
|
||||||
|
ret = phy_modify_changed(phydev, MII_CTRL1000,
|
||||||
|
ADVERTISE_1000FULL | ADVERTISE_1000HALF,
|
||||||
|
adv);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
if (ret > 0)
|
||||||
|
changed = true;
|
||||||
|
|
||||||
|
return genphy_c45_check_and_restart_aneg(phydev, changed);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mt7988_2p5ge_phy_get_features(struct phy_device *phydev)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = genphy_read_abilities(phydev);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
/* We don't support HDX at MAC layer on mt7988.
|
||||||
|
* So mask phy's HDX capabilities, too.
|
||||||
|
*/
|
||||||
|
linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
|
||||||
|
phydev->supported);
|
||||||
|
linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
|
||||||
|
phydev->supported);
|
||||||
|
linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
|
||||||
|
phydev->supported);
|
||||||
|
linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
|
||||||
|
phydev->supported);
|
||||||
|
linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mt7988_2p5ge_phy_read_status(struct phy_device *phydev)
|
||||||
|
{
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = genphy_update_link(phydev);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
phydev->speed = SPEED_UNKNOWN;
|
||||||
|
phydev->duplex = DUPLEX_UNKNOWN;
|
||||||
|
phydev->pause = 0;
|
||||||
|
phydev->asym_pause = 0;
|
||||||
|
|
||||||
|
if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
|
||||||
|
ret = genphy_c45_read_lpa(phydev);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
/* Read the link partner's 1G advertisement */
|
||||||
|
ret = phy_read(phydev, MII_STAT1000);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret);
|
||||||
|
} else if (phydev->autoneg == AUTONEG_DISABLE) {
|
||||||
|
linkmode_zero(phydev->lp_advertising);
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = phy_read(phydev, PHY_AUX_CTRL_STATUS);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
switch (FIELD_GET(PHY_AUX_SPEED_MASK, ret)) {
|
||||||
|
case PHY_AUX_SPD_10:
|
||||||
|
phydev->speed = SPEED_10;
|
||||||
|
break;
|
||||||
|
case PHY_AUX_SPD_100:
|
||||||
|
phydev->speed = SPEED_100;
|
||||||
|
break;
|
||||||
|
case PHY_AUX_SPD_1000:
|
||||||
|
phydev->speed = SPEED_1000;
|
||||||
|
break;
|
||||||
|
case PHY_AUX_SPD_2500:
|
||||||
|
phydev->speed = SPEED_2500;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LINK_STATUS_MISC);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
phydev->duplex = (ret & MTK_PHY_FDX_ENABLE) ? DUPLEX_FULL : DUPLEX_HALF;
|
||||||
|
/* FIXME: The current firmware always enables rate adaptation mode. */
|
||||||
|
phydev->rate_matching = RATE_MATCH_PAUSE;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int mt7988_2p5ge_phy_get_rate_matching(struct phy_device *phydev,
|
||||||
|
phy_interface_t iface)
|
||||||
|
{
|
||||||
|
return RATE_MATCH_PAUSE;
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct phy_driver mtk_gephy_driver[] = {
|
||||||
|
{
|
||||||
|
PHY_ID_MATCH_MODEL(0x00339c11),
|
||||||
|
.name = "MediaTek MT798x 2.5GbE PHY",
|
||||||
|
.probe = mt7988_2p5ge_phy_probe,
|
||||||
|
.config_init = mt7988_2p5ge_phy_config_init,
|
||||||
|
.config_aneg = mt7988_2p5ge_phy_config_aneg,
|
||||||
|
.get_features = mt7988_2p5ge_phy_get_features,
|
||||||
|
.read_status = mt7988_2p5ge_phy_read_status,
|
||||||
|
.get_rate_matching = mt7988_2p5ge_phy_get_rate_matching,
|
||||||
|
.suspend = genphy_suspend,
|
||||||
|
.resume = genphy_resume,
|
||||||
|
.read_page = mtk_2p5ge_phy_read_page,
|
||||||
|
.write_page = mtk_2p5ge_phy_write_page,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
module_phy_driver(mtk_gephy_driver);
|
||||||
|
|
||||||
|
static struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl[] = {
|
||||||
|
{ PHY_ID_MATCH_VENDOR(0x00339c00) },
|
||||||
|
{ }
|
||||||
|
};
|
||||||
|
|
||||||
|
MODULE_DESCRIPTION("MediaTek 2.5Gb Ethernet PHY driver");
|
||||||
|
MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
|
||||||
|
MODULE_LICENSE("GPL");
|
||||||
|
|
||||||
|
MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl);
|
||||||
|
MODULE_FIRMWARE(MT7988_2P5GE_PMB);
|
File diff suppressed because it is too large
Load diff
|
@ -0,0 +1,216 @@
|
||||||
|
From 69357074558daf6ff24c9f58714935e9e095a865 Mon Sep 17 00:00:00 2001
|
||||||
|
From: OpenWrt community <openwrt-devel@lists.openwrt.org>
|
||||||
|
Date: Wed, 13 Jul 2022 13:37:33 +0200
|
||||||
|
Subject: [PATCH] kernel: add block fit partition parser
|
||||||
|
|
||||||
|
---
|
||||||
|
block/blk.h | 2 ++
|
||||||
|
block/partitions/Kconfig | 7 +++++++
|
||||||
|
block/partitions/Makefile | 1 +
|
||||||
|
block/partitions/check.h | 3 +++
|
||||||
|
block/partitions/core.c | 17 +++++++++++++++++
|
||||||
|
block/partitions/efi.c | 8 ++++++++
|
||||||
|
block/partitions/efi.h | 3 +++
|
||||||
|
block/partitions/msdos.c | 10 ++++++++++
|
||||||
|
drivers/mtd/mtd_blkdevs.c | 2 ++
|
||||||
|
drivers/mtd/ubi/block.c | 3 +++
|
||||||
|
include/linux/msdos_partition.h | 1 +
|
||||||
|
11 files changed, 57 insertions(+)
|
||||||
|
|
||||||
|
--- a/block/blk.h
|
||||||
|
+++ b/block/blk.h
|
||||||
|
@@ -424,6 +424,8 @@ void blk_free_ext_minor(unsigned int min
|
||||||
|
#define ADDPART_FLAG_NONE 0
|
||||||
|
#define ADDPART_FLAG_RAID 1
|
||||||
|
#define ADDPART_FLAG_WHOLEDISK 2
|
||||||
|
+#define ADDPART_FLAG_READONLY 4
|
||||||
|
+#define ADDPART_FLAG_ROOTDEV 8
|
||||||
|
int bdev_add_partition(struct gendisk *disk, int partno, sector_t start,
|
||||||
|
sector_t length);
|
||||||
|
int bdev_del_partition(struct gendisk *disk, int partno);
|
||||||
|
--- a/block/partitions/Kconfig
|
||||||
|
+++ b/block/partitions/Kconfig
|
||||||
|
@@ -103,6 +103,13 @@ config ATARI_PARTITION
|
||||||
|
Say Y here if you would like to use hard disks under Linux which
|
||||||
|
were partitioned under the Atari OS.
|
||||||
|
|
||||||
|
+config FIT_PARTITION
|
||||||
|
+ bool "Flattened-Image-Tree (FIT) partition support" if PARTITION_ADVANCED
|
||||||
|
+ default n
|
||||||
|
+ help
|
||||||
|
+ Say Y here if your system needs to mount the filesystem part of
|
||||||
|
+ a Flattened-Image-Tree (FIT) image commonly used with Das U-Boot.
|
||||||
|
+
|
||||||
|
config IBM_PARTITION
|
||||||
|
bool "IBM disk label and partition support"
|
||||||
|
depends on PARTITION_ADVANCED && S390
|
||||||
|
--- a/block/partitions/Makefile
|
||||||
|
+++ b/block/partitions/Makefile
|
||||||
|
@@ -8,6 +8,7 @@ obj-$(CONFIG_ACORN_PARTITION) += acorn.o
|
||||||
|
obj-$(CONFIG_AMIGA_PARTITION) += amiga.o
|
||||||
|
obj-$(CONFIG_ATARI_PARTITION) += atari.o
|
||||||
|
obj-$(CONFIG_AIX_PARTITION) += aix.o
|
||||||
|
+obj-$(CONFIG_FIT_PARTITION) += fit.o
|
||||||
|
obj-$(CONFIG_CMDLINE_PARTITION) += cmdline.o
|
||||||
|
obj-$(CONFIG_MAC_PARTITION) += mac.o
|
||||||
|
obj-$(CONFIG_LDM_PARTITION) += ldm.o
|
||||||
|
--- a/block/partitions/check.h
|
||||||
|
+++ b/block/partitions/check.h
|
||||||
|
@@ -57,6 +57,7 @@ int amiga_partition(struct parsed_partit
|
||||||
|
int atari_partition(struct parsed_partitions *state);
|
||||||
|
int cmdline_partition(struct parsed_partitions *state);
|
||||||
|
int efi_partition(struct parsed_partitions *state);
|
||||||
|
+int fit_partition(struct parsed_partitions *state);
|
||||||
|
int ibm_partition(struct parsed_partitions *);
|
||||||
|
int karma_partition(struct parsed_partitions *state);
|
||||||
|
int ldm_partition(struct parsed_partitions *state);
|
||||||
|
@@ -67,3 +68,5 @@ int sgi_partition(struct parsed_partitio
|
||||||
|
int sun_partition(struct parsed_partitions *state);
|
||||||
|
int sysv68_partition(struct parsed_partitions *state);
|
||||||
|
int ultrix_partition(struct parsed_partitions *state);
|
||||||
|
+
|
||||||
|
+int parse_fit_partitions(struct parsed_partitions *state, u64 start_sector, u64 nr_sectors, int *slot, int add_remain);
|
||||||
|
--- a/block/partitions/core.c
|
||||||
|
+++ b/block/partitions/core.c
|
||||||
|
@@ -11,6 +11,9 @@
|
||||||
|
#include <linux/vmalloc.h>
|
||||||
|
#include <linux/raid/detect.h>
|
||||||
|
#include <linux/property.h>
|
||||||
|
+#ifdef CONFIG_FIT_PARTITION
|
||||||
|
+#include <linux/root_dev.h>
|
||||||
|
+#endif
|
||||||
|
|
||||||
|
#include "check.h"
|
||||||
|
|
||||||
|
@@ -48,6 +51,9 @@ static int (*const check_part[])(struct
|
||||||
|
#ifdef CONFIG_EFI_PARTITION
|
||||||
|
efi_partition, /* this must come before msdos */
|
||||||
|
#endif
|
||||||
|
+#ifdef CONFIG_FIT_PARTITION
|
||||||
|
+ fit_partition,
|
||||||
|
+#endif
|
||||||
|
#ifdef CONFIG_SGI_PARTITION
|
||||||
|
sgi_partition,
|
||||||
|
#endif
|
||||||
|
@@ -430,6 +436,11 @@ static struct block_device *add_partitio
|
||||||
|
goto out_del;
|
||||||
|
}
|
||||||
|
|
||||||
|
+#ifdef CONFIG_FIT_PARTITION
|
||||||
|
+ if (flags & ADDPART_FLAG_READONLY)
|
||||||
|
+ bdev->bd_read_only = true;
|
||||||
|
+#endif
|
||||||
|
+
|
||||||
|
/* everything is up and running, commence */
|
||||||
|
err = xa_insert(&disk->part_tbl, partno, bdev, GFP_KERNEL);
|
||||||
|
if (err)
|
||||||
|
@@ -622,6 +633,11 @@ static bool blk_add_partition(struct gen
|
||||||
|
(state->parts[p].flags & ADDPART_FLAG_RAID))
|
||||||
|
md_autodetect_dev(part->bd_dev);
|
||||||
|
|
||||||
|
+#ifdef CONFIG_FIT_PARTITION
|
||||||
|
+ if ((state->parts[p].flags & ADDPART_FLAG_ROOTDEV) && ROOT_DEV == 0)
|
||||||
|
+ ROOT_DEV = part->bd_dev;
|
||||||
|
+#endif
|
||||||
|
+
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
--- a/block/partitions/efi.c
|
||||||
|
+++ b/block/partitions/efi.c
|
||||||
|
@@ -716,6 +716,9 @@ int efi_partition(struct parsed_partitio
|
||||||
|
gpt_entry *ptes = NULL;
|
||||||
|
u32 i;
|
||||||
|
unsigned ssz = queue_logical_block_size(state->disk->queue) / 512;
|
||||||
|
+#ifdef CONFIG_FIT_PARTITION
|
||||||
|
+ u32 extra_slot = 64;
|
||||||
|
+#endif
|
||||||
|
|
||||||
|
if (!find_valid_gpt(state, &gpt, &ptes) || !gpt || !ptes) {
|
||||||
|
kfree(gpt);
|
||||||
|
@@ -749,6 +752,11 @@ int efi_partition(struct parsed_partitio
|
||||||
|
ARRAY_SIZE(ptes[i].partition_name));
|
||||||
|
utf16_le_to_7bit(ptes[i].partition_name, label_max, info->volname);
|
||||||
|
state->parts[i + 1].has_info = true;
|
||||||
|
+#ifdef CONFIG_FIT_PARTITION
|
||||||
|
+ /* If this is a U-Boot FIT volume it may have subpartitions */
|
||||||
|
+ if (!efi_guidcmp(ptes[i].partition_type_guid, PARTITION_LINUX_FIT_GUID))
|
||||||
|
+ (void) parse_fit_partitions(state, start * ssz, size * ssz, &extra_slot, 1);
|
||||||
|
+#endif
|
||||||
|
}
|
||||||
|
kfree(ptes);
|
||||||
|
kfree(gpt);
|
||||||
|
--- a/block/partitions/efi.h
|
||||||
|
+++ b/block/partitions/efi.h
|
||||||
|
@@ -51,6 +51,9 @@
|
||||||
|
#define PARTITION_LINUX_LVM_GUID \
|
||||||
|
EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \
|
||||||
|
0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28)
|
||||||
|
+#define PARTITION_LINUX_FIT_GUID \
|
||||||
|
+ EFI_GUID( 0xcae9be83, 0xb15f, 0x49cc, \
|
||||||
|
+ 0x86, 0x3f, 0x08, 0x1b, 0x74, 0x4a, 0x2d, 0x93)
|
||||||
|
|
||||||
|
typedef struct _gpt_header {
|
||||||
|
__le64 signature;
|
||||||
|
--- a/block/partitions/msdos.c
|
||||||
|
+++ b/block/partitions/msdos.c
|
||||||
|
@@ -564,6 +564,15 @@ static void parse_minix(struct parsed_pa
|
||||||
|
#endif /* CONFIG_MINIX_SUBPARTITION */
|
||||||
|
}
|
||||||
|
|
||||||
|
+static void parse_fit_mbr(struct parsed_partitions *state,
|
||||||
|
+ sector_t offset, sector_t size, int origin)
|
||||||
|
+{
|
||||||
|
+#ifdef CONFIG_FIT_PARTITION
|
||||||
|
+ u32 extra_slot = 64;
|
||||||
|
+ (void) parse_fit_partitions(state, offset, size, &extra_slot, 1);
|
||||||
|
+#endif /* CONFIG_FIT_PARTITION */
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
static struct {
|
||||||
|
unsigned char id;
|
||||||
|
void (*parse)(struct parsed_partitions *, sector_t, sector_t, int);
|
||||||
|
@@ -575,6 +584,7 @@ static struct {
|
||||||
|
{UNIXWARE_PARTITION, parse_unixware},
|
||||||
|
{SOLARIS_X86_PARTITION, parse_solaris_x86},
|
||||||
|
{NEW_SOLARIS_X86_PARTITION, parse_solaris_x86},
|
||||||
|
+ {FIT_PARTITION, parse_fit_mbr},
|
||||||
|
{0, NULL},
|
||||||
|
};
|
||||||
|
|
||||||
|
--- a/drivers/mtd/mtd_blkdevs.c
|
||||||
|
+++ b/drivers/mtd/mtd_blkdevs.c
|
||||||
|
@@ -359,7 +359,9 @@ int add_mtd_blktrans_dev(struct mtd_blkt
|
||||||
|
} else {
|
||||||
|
snprintf(gd->disk_name, sizeof(gd->disk_name),
|
||||||
|
"%s%d", tr->name, new->devnum);
|
||||||
|
- gd->flags |= GENHD_FL_NO_PART;
|
||||||
|
+
|
||||||
|
+ if (!IS_ENABLED(CONFIG_FIT_PARTITION) || mtd_type_is_nand(new->mtd))
|
||||||
|
+ gd->flags |= GENHD_FL_NO_PART;
|
||||||
|
}
|
||||||
|
|
||||||
|
set_capacity(gd, ((u64)new->size * tr->blksize) >> 9);
|
||||||
|
--- a/drivers/mtd/ubi/block.c
|
||||||
|
+++ b/drivers/mtd/ubi/block.c
|
||||||
|
@@ -410,7 +410,9 @@ int ubiblock_create(struct ubi_volume_in
|
||||||
|
ret = -ENODEV;
|
||||||
|
goto out_cleanup_disk;
|
||||||
|
}
|
||||||
|
- gd->flags |= GENHD_FL_NO_PART;
|
||||||
|
+ if (!IS_ENABLED(CONFIG_FIT_PARTITION))
|
||||||
|
+ gd->flags |= GENHD_FL_NO_PART;
|
||||||
|
+
|
||||||
|
gd->private_data = dev;
|
||||||
|
sprintf(gd->disk_name, "ubiblock%d_%d", dev->ubi_num, dev->vol_id);
|
||||||
|
set_capacity(gd, disk_capacity);
|
||||||
|
--- a/include/linux/msdos_partition.h
|
||||||
|
+++ b/include/linux/msdos_partition.h
|
||||||
|
@@ -31,6 +31,7 @@ enum msdos_sys_ind {
|
||||||
|
LINUX_LVM_PARTITION = 0x8e,
|
||||||
|
LINUX_RAID_PARTITION = 0xfd, /* autodetect RAID partition */
|
||||||
|
|
||||||
|
+ FIT_PARTITION = 0x2e, /* U-Boot uImage.FIT */
|
||||||
|
SOLARIS_X86_PARTITION = 0x82, /* also Linux swap partitions */
|
||||||
|
NEW_SOLARIS_X86_PARTITION = 0xbf,
|
||||||
|
|
|
@ -0,0 +1,107 @@
|
||||||
|
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
|
||||||
|
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
|
||||||
|
@@ -1,7 +1,6 @@
|
||||||
|
/*
|
||||||
|
- * Copyright (c) 2017 MediaTek Inc.
|
||||||
|
- * Author: Ming Huang <ming.huang@mediatek.com>
|
||||||
|
- * Sean Wang <sean.wang@mediatek.com>
|
||||||
|
+ * Copyright (c) 2018 MediaTek Inc.
|
||||||
|
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||||
|
*/
|
||||||
|
@@ -24,7 +23,7 @@
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
stdout-path = "serial0:115200n8";
|
||||||
|
- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
|
||||||
|
+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
|
||||||
|
};
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
@@ -45,18 +44,18 @@
|
||||||
|
key-factory {
|
||||||
|
label = "factory";
|
||||||
|
linux,code = <BTN_0>;
|
||||||
|
- gpios = <&pio 0 0>;
|
||||||
|
+ gpios = <&pio 0 GPIO_ACTIVE_LOW>;
|
||||||
|
};
|
||||||
|
|
||||||
|
key-wps {
|
||||||
|
label = "wps";
|
||||||
|
linux,code = <KEY_WPS_BUTTON>;
|
||||||
|
- gpios = <&pio 102 0>;
|
||||||
|
+ gpios = <&pio 102 GPIO_ACTIVE_LOW>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
memory@40000000 {
|
||||||
|
- reg = <0 0x40000000 0 0x20000000>;
|
||||||
|
+ reg = <0 0x40000000 0 0x40000000>;
|
||||||
|
device_type = "memory";
|
||||||
|
};
|
||||||
|
|
||||||
|
@@ -133,22 +132,22 @@
|
||||||
|
|
||||||
|
port@0 {
|
||||||
|
reg = <0>;
|
||||||
|
- label = "lan0";
|
||||||
|
+ label = "lan1";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@1 {
|
||||||
|
reg = <1>;
|
||||||
|
- label = "lan1";
|
||||||
|
+ label = "lan2";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@2 {
|
||||||
|
reg = <2>;
|
||||||
|
- label = "lan2";
|
||||||
|
+ label = "lan3";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@3 {
|
||||||
|
reg = <3>;
|
||||||
|
- label = "lan3";
|
||||||
|
+ label = "lan4";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@4 {
|
||||||
|
@@ -240,7 +239,22 @@
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
+&pcie1 {
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+ pinctrl-0 = <&pcie1_pins>;
|
||||||
|
+ status = "okay";
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
&pio {
|
||||||
|
+ /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
|
||||||
|
+ * SATA functions. i.e. output-high: PCIe, output-low: SATA
|
||||||
|
+ */
|
||||||
|
+ asm_sel {
|
||||||
|
+ gpio-hog;
|
||||||
|
+ gpios = <90 GPIO_ACTIVE_HIGH>;
|
||||||
|
+ output-high;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
/* eMMC is shared pin with parallel NAND */
|
||||||
|
emmc_pins_default: emmc-pins-default {
|
||||||
|
mux {
|
||||||
|
@@ -517,11 +531,11 @@
|
||||||
|
};
|
||||||
|
|
||||||
|
&sata {
|
||||||
|
- status = "okay";
|
||||||
|
+ status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
&sata_phy {
|
||||||
|
- status = "okay";
|
||||||
|
+ status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
&spi0 {
|
|
@ -0,0 +1,60 @@
|
||||||
|
--- a/arch/arm/boot/dts/mediatek/mt7629-rfb.dts
|
||||||
|
+++ b/arch/arm/boot/dts/mediatek/mt7629-rfb.dts
|
||||||
|
@@ -18,6 +18,7 @@
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
stdout-path = "serial0:115200n8";
|
||||||
|
+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8";
|
||||||
|
};
|
||||||
|
|
||||||
|
gpio-keys {
|
||||||
|
@@ -70,6 +71,10 @@
|
||||||
|
compatible = "mediatek,eth-mac";
|
||||||
|
reg = <0>;
|
||||||
|
phy-mode = "2500base-x";
|
||||||
|
+
|
||||||
|
+ nvmem-cells = <&macaddr_factory_2a>;
|
||||||
|
+ nvmem-cell-names = "mac-address";
|
||||||
|
+
|
||||||
|
fixed-link {
|
||||||
|
speed = <2500>;
|
||||||
|
full-duplex;
|
||||||
|
@@ -82,6 +87,9 @@
|
||||||
|
reg = <1>;
|
||||||
|
phy-mode = "gmii";
|
||||||
|
phy-handle = <&phy0>;
|
||||||
|
+
|
||||||
|
+ nvmem-cells = <&macaddr_factory_24>;
|
||||||
|
+ nvmem-cell-names = "mac-address";
|
||||||
|
};
|
||||||
|
|
||||||
|
mdio: mdio-bus {
|
||||||
|
@@ -133,8 +141,9 @@
|
||||||
|
};
|
||||||
|
|
||||||
|
partition@b0000 {
|
||||||
|
- label = "kernel";
|
||||||
|
+ label = "firmware";
|
||||||
|
reg = <0xb0000 0xb50000>;
|
||||||
|
+ compatible = "denx,fit";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
@@ -273,3 +282,17 @@
|
||||||
|
pinctrl-0 = <&watchdog_pins>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
+
|
||||||
|
+&factory {
|
||||||
|
+ compatible = "nvmem-cells";
|
||||||
|
+ #address-cells = <1>;
|
||||||
|
+ #size-cells = <1>;
|
||||||
|
+
|
||||||
|
+ macaddr_factory_24: macaddr@24 {
|
||||||
|
+ reg = <0x24 0x6>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ macaddr_factory_2a: macaddr@2a {
|
||||||
|
+ reg = <0x2a 0x6>;
|
||||||
|
+ };
|
||||||
|
+};
|
|
@ -0,0 +1,20 @@
|
||||||
|
From d6a596012150960f0f3a214d31bbac4b607dbd1e Mon Sep 17 00:00:00 2001
|
||||||
|
From: Chuanhong Guo <gch981213@gmail.com>
|
||||||
|
Date: Fri, 29 Apr 2022 10:40:56 +0800
|
||||||
|
Subject: [PATCH] arm: mediatek: select arch timer for mt7623
|
||||||
|
|
||||||
|
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
|
||||||
|
---
|
||||||
|
arch/arm/mach-mediatek/Kconfig | 1 +
|
||||||
|
1 file changed, 1 insertion(+)
|
||||||
|
|
||||||
|
--- a/arch/arm/mach-mediatek/Kconfig
|
||||||
|
+++ b/arch/arm/mach-mediatek/Kconfig
|
||||||
|
@@ -26,6 +26,7 @@ config MACH_MT6592
|
||||||
|
config MACH_MT7623
|
||||||
|
bool "MediaTek MT7623 SoCs support"
|
||||||
|
default ARCH_MEDIATEK
|
||||||
|
+ select HAVE_ARM_ARCH_TIMER
|
||||||
|
|
||||||
|
config MACH_MT7629
|
||||||
|
bool "MediaTek MT7629 SoCs support"
|
|
@ -0,0 +1,10 @@
|
||||||
|
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||||
|
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||||
|
@@ -575,6 +575,7 @@
|
||||||
|
compatible = "mediatek,mt7622-nor",
|
||||||
|
"mediatek,mt8173-nor";
|
||||||
|
reg = <0 0x11014000 0 0xe0>;
|
||||||
|
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
clocks = <&pericfg CLK_PERI_FLASH_PD>,
|
||||||
|
<&topckgen CLK_TOP_FLASH_SEL>;
|
||||||
|
clock-names = "spi", "sf";
|
|
@ -0,0 +1,16 @@
|
||||||
|
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||||
|
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||||
|
@@ -135,6 +135,13 @@
|
||||||
|
#size-cells = <2>;
|
||||||
|
ranges;
|
||||||
|
|
||||||
|
+ /* 64 KiB reserved for ramoops/pstore */
|
||||||
|
+ ramoops@42ff0000 {
|
||||||
|
+ compatible = "ramoops";
|
||||||
|
+ reg = <0 0x42ff0000 0 0x10000>;
|
||||||
|
+ record-size = <0x1000>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
|
||||||
|
secmon_reserved: secmon@43000000 {
|
||||||
|
reg = <0 0x43000000 0 0x30000>;
|
|
@ -0,0 +1,26 @@
|
||||||
|
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
|
||||||
|
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
|
||||||
|
@@ -109,10 +109,6 @@
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
-&btif {
|
||||||
|
- status = "okay";
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
&cir {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&irrx_pins>;
|
||||||
|
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
|
||||||
|
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
|
||||||
|
@@ -90,10 +90,6 @@
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
-&btif {
|
||||||
|
- status = "okay";
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
&cir {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&irrx_pins>;
|
|
@ -0,0 +1,28 @@
|
||||||
|
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
|
||||||
|
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
|
||||||
|
@@ -145,9 +145,9 @@
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
- switch@0 {
|
||||||
|
+ switch@1f {
|
||||||
|
compatible = "mediatek,mt7531";
|
||||||
|
- reg = <0>;
|
||||||
|
+ reg = <31>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
interrupt-parent = <&pio>;
|
||||||
|
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
|
||||||
|
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
|
||||||
|
@@ -117,9 +117,9 @@
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
- switch@0 {
|
||||||
|
+ switch@1f {
|
||||||
|
compatible = "mediatek,mt7531";
|
||||||
|
- reg = <0>;
|
||||||
|
+ reg = <31>;
|
||||||
|
reset-gpios = <&pio 54 0>;
|
||||||
|
|
||||||
|
ports {
|
|
@ -0,0 +1,10 @@
|
||||||
|
--- a/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts
|
||||||
|
+++ b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts
|
||||||
|
@@ -19,6 +19,7 @@
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
stdout-path = "serial2:115200n8";
|
||||||
|
+ bootargs = "console=ttyS2,115200n8 console=tty1";
|
||||||
|
};
|
||||||
|
|
||||||
|
connector {
|
|
@ -0,0 +1,11 @@
|
||||||
|
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
|
||||||
|
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
|
||||||
|
@@ -24,7 +24,7 @@
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
stdout-path = "serial0:115200n8";
|
||||||
|
- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
|
||||||
|
+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
|
||||||
|
};
|
||||||
|
|
||||||
|
cpus {
|
|
@ -0,0 +1,37 @@
|
||||||
|
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
|
||||||
|
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
|
||||||
|
@@ -20,6 +20,7 @@
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
serial0 = &uart0;
|
||||||
|
+ ethernet0 = &gmac0;
|
||||||
|
};
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
@@ -165,22 +166,22 @@
|
||||||
|
|
||||||
|
port@1 {
|
||||||
|
reg = <1>;
|
||||||
|
- label = "lan0";
|
||||||
|
+ label = "lan1";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@2 {
|
||||||
|
reg = <2>;
|
||||||
|
- label = "lan1";
|
||||||
|
+ label = "lan2";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@3 {
|
||||||
|
reg = <3>;
|
||||||
|
- label = "lan2";
|
||||||
|
+ label = "lan3";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@4 {
|
||||||
|
reg = <4>;
|
||||||
|
- label = "lan3";
|
||||||
|
+ label = "lan4";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@6 {
|
|
@ -0,0 +1,49 @@
|
||||||
|
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
|
||||||
|
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
|
||||||
|
@@ -21,6 +21,12 @@
|
||||||
|
aliases {
|
||||||
|
serial0 = &uart0;
|
||||||
|
ethernet0 = &gmac0;
|
||||||
|
+ led-boot = &led_system_green;
|
||||||
|
+ led-failsafe = &led_system_blue;
|
||||||
|
+ led-running = &led_system_green;
|
||||||
|
+ led-upgrade = &led_system_blue;
|
||||||
|
+ mmc0 = &mmc0;
|
||||||
|
+ mmc1 = &mmc1;
|
||||||
|
};
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
@@ -44,8 +50,8 @@
|
||||||
|
compatible = "gpio-keys";
|
||||||
|
|
||||||
|
factory-key {
|
||||||
|
- label = "factory";
|
||||||
|
- linux,code = <BTN_0>;
|
||||||
|
+ label = "reset";
|
||||||
|
+ linux,code = <KEY_RESTART>;
|
||||||
|
gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
|
||||||
|
};
|
||||||
|
|
||||||
|
@@ -59,17 +65,17 @@
|
||||||
|
leds {
|
||||||
|
compatible = "gpio-leds";
|
||||||
|
|
||||||
|
- led-0 {
|
||||||
|
+ led_system_green: led-0 {
|
||||||
|
label = "bpi-r64:pio:green";
|
||||||
|
color = <LED_COLOR_ID_GREEN>;
|
||||||
|
gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
|
||||||
|
default-state = "off";
|
||||||
|
};
|
||||||
|
|
||||||
|
- led-1 {
|
||||||
|
- label = "bpi-r64:pio:red";
|
||||||
|
- color = <LED_COLOR_ID_RED>;
|
||||||
|
- gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
|
||||||
|
+ led_system_blue: led-1 {
|
||||||
|
+ label = "bpi-r64:pio:blue";
|
||||||
|
+ color = <LED_COLOR_ID_BLUE>;
|
||||||
|
+ gpios = <&pio 85 GPIO_ACTIVE_HIGH>;
|
||||||
|
default-state = "off";
|
||||||
|
};
|
||||||
|
};
|
|
@ -0,0 +1,13 @@
|
||||||
|
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
|
||||||
|
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
|
||||||
|
@@ -588,6 +588,10 @@
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
+&rtc {
|
||||||
|
+ status = "disabled";
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
&sata {
|
||||||
|
status = "disabled";
|
||||||
|
};
|
|
@ -0,0 +1,20 @@
|
||||||
|
--- a/drivers/mtd/nand/spi/core.c
|
||||||
|
+++ b/drivers/mtd/nand/spi/core.c
|
||||||
|
@@ -724,7 +724,7 @@ static int spinand_mtd_write(struct mtd_
|
||||||
|
static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos)
|
||||||
|
{
|
||||||
|
struct spinand_device *spinand = nand_to_spinand(nand);
|
||||||
|
- u8 marker[2] = { };
|
||||||
|
+ u8 marker[1] = { };
|
||||||
|
struct nand_page_io_req req = {
|
||||||
|
.pos = *pos,
|
||||||
|
.ooblen = sizeof(marker),
|
||||||
|
@@ -735,7 +735,7 @@ static bool spinand_isbad(struct nand_de
|
||||||
|
|
||||||
|
spinand_select_target(spinand, pos->target);
|
||||||
|
spinand_read_page(spinand, &req);
|
||||||
|
- if (marker[0] != 0xff || marker[1] != 0xff)
|
||||||
|
+ if (marker[0] != 0xff)
|
||||||
|
return true;
|
||||||
|
|
||||||
|
return false;
|
|
@ -0,0 +1,94 @@
|
||||||
|
From c813fbe806257c574240770ef716fbee19f7dbfa Mon Sep 17 00:00:00 2001
|
||||||
|
From: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
|
||||||
|
Date: Thu, 6 Jun 2019 16:29:04 +0800
|
||||||
|
Subject: [PATCH] spi: spi-mem: Mediatek: Add SPI Nand support for MT7629
|
||||||
|
|
||||||
|
Signed-off-by: Xiangsheng Hou <xiangsheng.hou@mediatek.com>
|
||||||
|
---
|
||||||
|
arch/arm/boot/dts/mediatek/mt7629-rfb.dts | 45 ++++++++++++++++++++++++++++++++
|
||||||
|
arch/arm/boot/dts/mediatek/mt7629.dtsi | 22 ++++++++++++++++
|
||||||
|
3 files changed, 79 insertions(+)
|
||||||
|
|
||||||
|
--- a/arch/arm/boot/dts/mediatek/mt7629.dtsi
|
||||||
|
+++ b/arch/arm/boot/dts/mediatek/mt7629.dtsi
|
||||||
|
@@ -271,6 +271,27 @@
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
+ snfi: spi@1100d000 {
|
||||||
|
+ compatible = "mediatek,mt7629-snand";
|
||||||
|
+ reg = <0x1100d000 0x1000>;
|
||||||
|
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
+ clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>;
|
||||||
|
+ clock-names = "nfi_clk", "pad_clk";
|
||||||
|
+ nand-ecc-engine = <&bch>;
|
||||||
|
+ #address-cells = <1>;
|
||||||
|
+ #size-cells = <0>;
|
||||||
|
+ status = "disabled";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ bch: ecc@1100e000 {
|
||||||
|
+ compatible = "mediatek,mt7622-ecc";
|
||||||
|
+ reg = <0x1100e000 0x1000>;
|
||||||
|
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
+ clocks = <&pericfg CLK_PERI_NFIECC_PD>;
|
||||||
|
+ clock-names = "nfiecc_clk";
|
||||||
|
+ status = "disabled";
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
spi: spi@1100a000 {
|
||||||
|
compatible = "mediatek,mt7629-spi",
|
||||||
|
"mediatek,mt7622-spi";
|
||||||
|
--- a/arch/arm/boot/dts/mediatek/mt7629-rfb.dts
|
||||||
|
+++ b/arch/arm/boot/dts/mediatek/mt7629-rfb.dts
|
||||||
|
@@ -255,6 +255,50 @@
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
+&bch {
|
||||||
|
+ status = "okay";
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&snfi {
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+ pinctrl-0 = <&serial_nand_pins>;
|
||||||
|
+ status = "okay";
|
||||||
|
+ flash@0 {
|
||||||
|
+ compatible = "spi-nand";
|
||||||
|
+ reg = <0>;
|
||||||
|
+ spi-tx-bus-width = <4>;
|
||||||
|
+ spi-rx-bus-width = <4>;
|
||||||
|
+ nand-ecc-engine = <&snfi>;
|
||||||
|
+
|
||||||
|
+ partitions {
|
||||||
|
+ compatible = "fixed-partitions";
|
||||||
|
+ #address-cells = <1>;
|
||||||
|
+ #size-cells = <1>;
|
||||||
|
+
|
||||||
|
+ partition@0 {
|
||||||
|
+ label = "Bootloader";
|
||||||
|
+ reg = <0x00000 0x0100000>;
|
||||||
|
+ read-only;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ partition@100000 {
|
||||||
|
+ label = "Config";
|
||||||
|
+ reg = <0x100000 0x0040000>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ partition@140000 {
|
||||||
|
+ label = "factory";
|
||||||
|
+ reg = <0x140000 0x0080000>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ partition@1c0000 {
|
||||||
|
+ label = "firmware";
|
||||||
|
+ reg = <0x1c0000 0x1000000>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
&spi {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&spi_pins>;
|
|
@ -0,0 +1,68 @@
|
||||||
|
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
|
||||||
|
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
|
||||||
|
@@ -534,6 +534,65 @@
|
||||||
|
status = "disabled";
|
||||||
|
};
|
||||||
|
|
||||||
|
+&bch {
|
||||||
|
+ status = "okay";
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+&snfi {
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
+ pinctrl-0 = <&serial_nand_pins>;
|
||||||
|
+ status = "okay";
|
||||||
|
+ flash@0 {
|
||||||
|
+ compatible = "spi-nand";
|
||||||
|
+ reg = <0>;
|
||||||
|
+ spi-tx-bus-width = <4>;
|
||||||
|
+ spi-rx-bus-width = <4>;
|
||||||
|
+ nand-ecc-engine = <&snfi>;
|
||||||
|
+
|
||||||
|
+ partitions {
|
||||||
|
+ compatible = "fixed-partitions";
|
||||||
|
+ #address-cells = <1>;
|
||||||
|
+ #size-cells = <1>;
|
||||||
|
+
|
||||||
|
+ partition@0 {
|
||||||
|
+ label = "Preloader";
|
||||||
|
+ reg = <0x00000 0x0080000>;
|
||||||
|
+ read-only;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ partition@80000 {
|
||||||
|
+ label = "ATF";
|
||||||
|
+ reg = <0x80000 0x0040000>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ partition@c0000 {
|
||||||
|
+ label = "Bootloader";
|
||||||
|
+ reg = <0xc0000 0x0080000>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ partition@140000 {
|
||||||
|
+ label = "Config";
|
||||||
|
+ reg = <0x140000 0x0080000>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ partition@1c0000 {
|
||||||
|
+ label = "Factory";
|
||||||
|
+ reg = <0x1c0000 0x0100000>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ partition@200000 {
|
||||||
|
+ label = "firmware";
|
||||||
|
+ reg = <0x2c0000 0x2000000>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ partition@2200000 {
|
||||||
|
+ label = "User_data";
|
||||||
|
+ reg = <0x22c0000 0x4000000>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
&spi0 {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&spic0_pins>;
|
|
@ -0,0 +1,18 @@
|
||||||
|
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
|
||||||
|
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
|
||||||
|
@@ -575,7 +575,7 @@
|
||||||
|
reg = <0x140000 0x0080000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
- partition@1c0000 {
|
||||||
|
+ factory: partition@1c0000 {
|
||||||
|
label = "Factory";
|
||||||
|
reg = <0x1c0000 0x0100000>;
|
||||||
|
};
|
||||||
|
@@ -636,5 +636,6 @@
|
||||||
|
&wmac {
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&wmac_pins>;
|
||||||
|
+ mediatek,mtd-eeprom = <&factory 0x0000>;
|
||||||
|
status = "okay";
|
||||||
|
};
|
|
@ -0,0 +1,24 @@
|
||||||
|
--- a/arch/arm/boot/dts/mediatek/mt7623.dtsi
|
||||||
|
+++ b/arch/arm/boot/dts/mediatek/mt7623.dtsi
|
||||||
|
@@ -995,17 +995,15 @@
|
||||||
|
};
|
||||||
|
|
||||||
|
crypto: crypto@1b240000 {
|
||||||
|
- compatible = "mediatek,eip97-crypto";
|
||||||
|
+ compatible = "inside-secure,safexcel-eip97";
|
||||||
|
reg = <0 0x1b240000 0 0x20000>;
|
||||||
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
|
||||||
|
<GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
|
||||||
|
<GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
|
||||||
|
- <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
|
||||||
|
- <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
|
||||||
|
+ interrupt-names = "ring0", "ring1", "ring2", "ring3";
|
||||||
|
clocks = <ðsys CLK_ETHSYS_CRYPTO>;
|
||||||
|
- clock-names = "cryp";
|
||||||
|
- power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
|
||||||
|
- status = "disabled";
|
||||||
|
+ status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
|
bdpsys: syscon@1c000000 {
|
|
@ -0,0 +1,11 @@
|
||||||
|
--- a/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts
|
||||||
|
+++ b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts
|
||||||
|
@@ -19,7 +19,7 @@
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
stdout-path = "serial2:115200n8";
|
||||||
|
- bootargs = "console=ttyS2,115200n8 console=tty1";
|
||||||
|
+ bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
|
||||||
|
};
|
||||||
|
|
||||||
|
connector {
|
|
@ -0,0 +1,11 @@
|
||||||
|
--- a/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts
|
||||||
|
+++ b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts
|
||||||
|
@@ -15,6 +15,8 @@
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
serial2 = &uart2;
|
||||||
|
+ mmc0 = &mmc0;
|
||||||
|
+ mmc1 = &mmc1;
|
||||||
|
};
|
||||||
|
|
||||||
|
chosen {
|
|
@ -0,0 +1,29 @@
|
||||||
|
--- a/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts
|
||||||
|
+++ b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts
|
||||||
|
@@ -17,6 +17,10 @@
|
||||||
|
serial2 = &uart2;
|
||||||
|
mmc0 = &mmc0;
|
||||||
|
mmc1 = &mmc1;
|
||||||
|
+ led-boot = &led_system_green;
|
||||||
|
+ led-failsafe = &led_system_blue;
|
||||||
|
+ led-running = &led_system_green;
|
||||||
|
+ led-upgrade = &led_system_blue;
|
||||||
|
};
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
@@ -112,13 +116,13 @@
|
||||||
|
pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&led_pins_a>;
|
||||||
|
|
||||||
|
- blue {
|
||||||
|
+ led_system_blue: blue {
|
||||||
|
label = "bpi-r2:pio:blue";
|
||||||
|
gpios = <&pio 240 GPIO_ACTIVE_LOW>;
|
||||||
|
default-state = "off";
|
||||||
|
};
|
||||||
|
|
||||||
|
- green {
|
||||||
|
+ led_system_green: green {
|
||||||
|
label = "bpi-r2:pio:green";
|
||||||
|
gpios = <&pio 241 GPIO_ACTIVE_LOW>;
|
||||||
|
default-state = "off";
|
|
@ -0,0 +1,10 @@
|
||||||
|
--- a/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts
|
||||||
|
+++ b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts
|
||||||
|
@@ -15,6 +15,7 @@
|
||||||
|
|
||||||
|
aliases {
|
||||||
|
serial2 = &uart2;
|
||||||
|
+ ethernet0 = &gmac0;
|
||||||
|
mmc0 = &mmc0;
|
||||||
|
mmc1 = &mmc1;
|
||||||
|
led-boot = &led_system_green;
|
|
@ -0,0 +1,55 @@
|
||||||
|
--- a/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts
|
||||||
|
+++ b/arch/arm/boot/dts/mediatek/mt7623n-bananapi-bpi-r2.dts
|
||||||
|
@@ -26,7 +26,9 @@
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
stdout-path = "serial2:115200n8";
|
||||||
|
- bootargs = "earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
|
||||||
|
+ bootargs = "root=/dev/fit0 rootwait earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200n8 console=tty1";
|
||||||
|
+ rootdisk-emmc = <&emmc_rootdisk>;
|
||||||
|
+ rootdisk-sd = <&sd_rootdisk>;
|
||||||
|
};
|
||||||
|
|
||||||
|
connector {
|
||||||
|
@@ -338,6 +340,20 @@
|
||||||
|
vmmc-supply = <®_3p3v>;
|
||||||
|
vqmmc-supply = <®_1p8v>;
|
||||||
|
non-removable;
|
||||||
|
+
|
||||||
|
+ card@0 {
|
||||||
|
+ compatible = "mmc-card";
|
||||||
|
+ reg = <0>;
|
||||||
|
+
|
||||||
|
+ block {
|
||||||
|
+ compatible = "block-device";
|
||||||
|
+ partitions {
|
||||||
|
+ emmc_rootdisk: block-partition-fit {
|
||||||
|
+ partno = <3>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
};
|
||||||
|
|
||||||
|
&mmc1 {
|
||||||
|
@@ -351,6 +367,20 @@
|
||||||
|
cd-gpios = <&pio 261 GPIO_ACTIVE_LOW>;
|
||||||
|
vmmc-supply = <®_3p3v>;
|
||||||
|
vqmmc-supply = <®_3p3v>;
|
||||||
|
+
|
||||||
|
+ card@0 {
|
||||||
|
+ compatible = "mmc-card";
|
||||||
|
+ reg = <0>;
|
||||||
|
+
|
||||||
|
+ block {
|
||||||
|
+ compatible = "block-device";
|
||||||
|
+ partitions {
|
||||||
|
+ sd_rootdisk: block-partition-fit {
|
||||||
|
+ partno = <3>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
};
|
||||||
|
|
||||||
|
&mt6323keys {
|
|
@ -0,0 +1,106 @@
|
||||||
|
From patchwork Tue Apr 26 19:51:36 2022
|
||||||
|
Content-Type: text/plain; charset="utf-8"
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Transfer-Encoding: 7bit
|
||||||
|
X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
|
||||||
|
X-Patchwork-Id: 12827872
|
||||||
|
Return-Path:
|
||||||
|
<linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org>
|
||||||
|
X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on
|
||||||
|
aws-us-west-2-korg-lkml-1.web.codeaurora.org
|
||||||
|
Received: from bombadil.infradead.org (bombadil.infradead.org
|
||||||
|
[198.137.202.133])
|
||||||
|
(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))
|
||||||
|
(No client certificate requested)
|
||||||
|
by smtp.lore.kernel.org (Postfix) with ESMTPS id BACF3C433EF
|
||||||
|
for <linux-arm-kernel@archiver.kernel.org>;
|
||||||
|
Tue, 26 Apr 2022 19:53:05 +0000 (UTC)
|
||||||
|
DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;
|
||||||
|
d=lists.infradead.org; s=bombadil.20210309; h=Sender:
|
||||||
|
Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post:
|
||||||
|
List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Subject:Cc:To:
|
||||||
|
From:Date:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:
|
||||||
|
Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:
|
||||||
|
List-Owner; bh=OWGSxvlKoyPWz6b629RNINucULo6oOdFssAIiJETWRg=; b=T0HEjee0FX3hlb
|
||||||
|
x5jl7xLK5sKM0pkE2oRgwzthbFlNg8ST1j/2GkgcgT0S2Bi0vRfFxHeu/RKzS9RmiVnKJnPGL8ctg
|
||||||
|
WoBLyO5i+NcmosGoy6MmoOjGTNhj/+3q3Z1jRLBSJ4ySSP22X77YeuJTmVzySPUllQhWvDhjMVCR9
|
||||||
|
QBRmQdc6gCAg3IYGEbWwS2TG+UHveDCeZRWxMzrwI8UPadNCRFROwugmiQ3mdU41lHCTDpnlfuRJh
|
||||||
|
o1igLKfMBLz+D8rFYvDh7FfkcKkY6lNoswA2HKUun1MEzgoyQKmITPnG2maX/BvJJuj/B3ZJShh4k
|
||||||
|
AZHmXoQxq1mrsm2FxfnQ==;
|
||||||
|
Received: from localhost ([::1] helo=bombadil.infradead.org)
|
||||||
|
by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux))
|
||||||
|
id 1njRE5-00G05D-9z; Tue, 26 Apr 2022 19:51:57 +0000
|
||||||
|
Received: from fudo.makrotopia.org ([2a07:2ec0:3002::71])
|
||||||
|
by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux))
|
||||||
|
id 1njRE1-00G03h-9H; Tue, 26 Apr 2022 19:51:55 +0000
|
||||||
|
Received: from local
|
||||||
|
by fudo.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256)
|
||||||
|
(Exim 4.94.2) (envelope-from <daniel@makrotopia.org>)
|
||||||
|
id 1njRDu-0006aF-4F; Tue, 26 Apr 2022 21:51:46 +0200
|
||||||
|
Date: Tue, 26 Apr 2022 20:51:36 +0100
|
||||||
|
From: Daniel Golle <daniel@makrotopia.org>
|
||||||
|
To: devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org,
|
||||||
|
linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
|
||||||
|
Cc: Rob Herring <robh+dt@kernel.org>,
|
||||||
|
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
|
||||||
|
Matthias Brugger <matthias.bgg@gmail.com>
|
||||||
|
Subject: [PATCH] arm64: dts: mediatek: mt7622: fix GICv2 range
|
||||||
|
Message-ID: <YmhNSLgp/yg8Vr1F@makrotopia.org>
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Disposition: inline
|
||||||
|
X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3
|
||||||
|
X-CRM114-CacheID: sfid-20220426_125153_359242_EA3D452C
|
||||||
|
X-CRM114-Status: GOOD ( 12.45 )
|
||||||
|
X-BeenThere: linux-arm-kernel@lists.infradead.org
|
||||||
|
X-Mailman-Version: 2.1.34
|
||||||
|
Precedence: list
|
||||||
|
List-Id: <linux-arm-kernel.lists.infradead.org>
|
||||||
|
List-Unsubscribe:
|
||||||
|
<http://lists.infradead.org/mailman/options/linux-arm-kernel>,
|
||||||
|
<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>
|
||||||
|
List-Archive: <http://lists.infradead.org/pipermail/linux-arm-kernel/>
|
||||||
|
List-Post: <mailto:linux-arm-kernel@lists.infradead.org>
|
||||||
|
List-Help: <mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>
|
||||||
|
List-Subscribe:
|
||||||
|
<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,
|
||||||
|
<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>
|
||||||
|
Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org>
|
||||||
|
Errors-To:
|
||||||
|
linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org
|
||||||
|
|
||||||
|
With the current range specified for the CPU interface there is an
|
||||||
|
error message at boot:
|
||||||
|
|
||||||
|
GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set
|
||||||
|
|
||||||
|
Setting irqchip.gicv2_force_probe=1 in bootargs results in:
|
||||||
|
|
||||||
|
GIC: Aliased GICv2 at 0x0000000010320000, trying to find the canonical range over 128kB
|
||||||
|
GIC: Adjusting CPU interface base to 0x000000001032f000
|
||||||
|
GIC: Using split EOI/Deactivate mode
|
||||||
|
|
||||||
|
Using the adjusted CPU interface base and 8K size results in only the
|
||||||
|
final line remaining and fully working system as well as /proc/interrupts
|
||||||
|
showing additional IPI3,4,5,6:
|
||||||
|
|
||||||
|
IPI3: 0 0 CPU stop (for crash dump) interrupts
|
||||||
|
IPI4: 0 0 Timer broadcast interrupts
|
||||||
|
IPI5: 0 0 IRQ work interrupts
|
||||||
|
IPI6: 0 0 CPU wake-up interrupts
|
||||||
|
|
||||||
|
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||||
|
---
|
||||||
|
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +-
|
||||||
|
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||||
|
|
||||||
|
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||||
|
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||||
|
@@ -345,7 +345,7 @@
|
||||||
|
#interrupt-cells = <3>;
|
||||||
|
interrupt-parent = <&gic>;
|
||||||
|
reg = <0 0x10310000 0 0x1000>,
|
||||||
|
- <0 0x10320000 0 0x1000>,
|
||||||
|
+ <0 0x1032f000 0 0x2000>,
|
||||||
|
<0 0x10340000 0 0x2000>,
|
||||||
|
<0 0x10360000 0 0x2000>;
|
||||||
|
};
|
|
@ -0,0 +1,48 @@
|
||||||
|
From 824d56e753a588fcfd650db1822e34a02a48bb77 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Bruno Umuarama <anonimou_eu@hotmail.com>
|
||||||
|
Date: Thu, 13 Oct 2022 21:18:21 +0000
|
||||||
|
Subject: [PATCH] mediatek: mt7623: fix thermal zone
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Type: text/plain; charset=UTF-8
|
||||||
|
Content-Transfer-Encoding: 8bit
|
||||||
|
|
||||||
|
Raising the temperatures for passive and active trips. @VA1DER
|
||||||
|
proposed at issue 9396 to remove passive trip. This commit relates to
|
||||||
|
his suggestion.
|
||||||
|
|
||||||
|
Without this patch. the CPU will be throttled all the way down to 98MHz
|
||||||
|
if the temperature rises even a degree above the trip point, and it was
|
||||||
|
further discovered that if the internal temperature of the device is
|
||||||
|
above the first trip point temperature when it boots then it will start
|
||||||
|
in a throttled state and even
|
||||||
|
$ echo disabled > /sys/class/thermal/thermal_zone0/mode
|
||||||
|
will have no effect.
|
||||||
|
|
||||||
|
The patch increases the passive trip point and active cooling map. The
|
||||||
|
throttling temperature will then be at 77°C and 82°C, which is still a
|
||||||
|
low enough temperature for ARM devices to not be in the real danger
|
||||||
|
zone, and gives some operational headroom.
|
||||||
|
|
||||||
|
Signed-off-by: Bruno Umuarama <anonimou_eu@hotmail.com>
|
||||||
|
---
|
||||||
|
arch/arm/boot/dts/mediatek/mt7623.dtsi | 4 ++--
|
||||||
|
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||||
|
|
||||||
|
--- a/arch/arm/boot/dts/mediatek/mt7623.dtsi
|
||||||
|
+++ b/arch/arm/boot/dts/mediatek/mt7623.dtsi
|
||||||
|
@@ -160,13 +160,13 @@
|
||||||
|
|
||||||
|
trips {
|
||||||
|
cpu_passive: cpu-passive {
|
||||||
|
- temperature = <57000>;
|
||||||
|
+ temperature = <77000>;
|
||||||
|
hysteresis = <2000>;
|
||||||
|
type = "passive";
|
||||||
|
};
|
||||||
|
|
||||||
|
cpu_active: cpu-active {
|
||||||
|
- temperature = <67000>;
|
||||||
|
+ temperature = <82000>;
|
||||||
|
hysteresis = <2000>;
|
||||||
|
type = "active";
|
||||||
|
};
|
|
@ -0,0 +1,17 @@
|
||||||
|
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
|
||||||
|
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
|
||||||
|
@@ -68,6 +68,14 @@
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
ranges;
|
||||||
|
+
|
||||||
|
+ /* 64 KiB reserved for ramoops/pstore */
|
||||||
|
+ ramoops@42ff0000 {
|
||||||
|
+ compatible = "ramoops";
|
||||||
|
+ reg = <0 0x42ff0000 0 0x10000>;
|
||||||
|
+ record-size = <0x1000>;
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
|
||||||
|
secmon_reserved: secmon@43000000 {
|
||||||
|
reg = <0 0x43000000 0 0x30000>;
|
|
@ -0,0 +1,196 @@
|
||||||
|
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
|
||||||
|
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
|
||||||
|
@@ -23,6 +23,10 @@
|
||||||
|
serial0 = &uart0;
|
||||||
|
ethernet0 = &gmac0;
|
||||||
|
ethernet1 = &gmac1;
|
||||||
|
+ led-boot = &green_led;
|
||||||
|
+ led-failsafe = &green_led;
|
||||||
|
+ led-running = &green_led;
|
||||||
|
+ led-upgrade = &blue_led;
|
||||||
|
};
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
@@ -419,27 +423,27 @@
|
||||||
|
|
||||||
|
port@1 {
|
||||||
|
reg = <1>;
|
||||||
|
- label = "lan0";
|
||||||
|
+ label = "lan1";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@2 {
|
||||||
|
reg = <2>;
|
||||||
|
- label = "lan1";
|
||||||
|
+ label = "lan2";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@3 {
|
||||||
|
reg = <3>;
|
||||||
|
- label = "lan2";
|
||||||
|
+ label = "lan3";
|
||||||
|
};
|
||||||
|
|
||||||
|
port@4 {
|
||||||
|
reg = <4>;
|
||||||
|
- label = "lan3";
|
||||||
|
+ label = "lan4";
|
||||||
|
};
|
||||||
|
|
||||||
|
port5: port@5 {
|
||||||
|
reg = <5>;
|
||||||
|
- label = "lan4";
|
||||||
|
+ label = "sfp2";
|
||||||
|
phy-mode = "2500base-x";
|
||||||
|
sfp = <&sfp2>;
|
||||||
|
managed = "in-band-status";
|
||||||
|
@@ -490,9 +494,137 @@
|
||||||
|
|
||||||
|
&wifi {
|
||||||
|
status = "okay";
|
||||||
|
- pinctrl-names = "default", "dbdc";
|
||||||
|
+ pinctrl-names = "default";
|
||||||
|
pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
|
||||||
|
- pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
|
||||||
|
+
|
||||||
|
+ mediatek,eeprom-data = <0x86790900 0x000c4326 0x60000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x01000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000800 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x24649090 0x00280000 0x05100000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00021e00 0x021e0002 0x1e00021e 0x00022800 0x02280002 0x28000228 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00008080 0x8080fdf7
|
||||||
|
+ 0x0903150d 0x80808080 0x80808080 0x05050d0d 0x1313c6c6 0xc3c3c200 0x00c200c2 0x00008182
|
||||||
|
+ 0x8585c2c2 0x82828282 0x858500c2 0xc2000081 0x82858587 0x87c2c200 0x81818285 0x858787c2
|
||||||
|
+ 0xc2000081 0x82858587 0x87c2c200 0x00818285 0x858787c2 0xc2000081 0x82858587 0x87c4c4c2
|
||||||
|
+ 0xc100c300 0xc3c3c100 0x818383c3 0xc3c3c100 0x81838300 0xc2c2c2c0 0x81828484 0x000000c3
|
||||||
|
+ 0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x838686c2 0xc2c2c081 0x82848486 0x86c3c3c3
|
||||||
|
+ 0xc1008183 0x838686c3 0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x83868622 0x28002228
|
||||||
|
+ 0x00222800 0x22280000 0xdddddddd 0xdddddddd 0xddbbbbbb 0xccccccdd 0xdddddddd 0xdddddddd
|
||||||
|
+ 0xeeeeeecc 0xccccdddd 0xdddddddd 0x004a5662 0x0000004a 0x56620000 0x004a5662 0x0000004a
|
||||||
|
+ 0x56620000 0x88888888 0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600
|
||||||
|
+ 0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600 0x00000000 0xf0f0cc00
|
||||||
|
+ 0x00000000 0x0000aaaa 0xaabbbbbb 0xcccccccc 0xccccbbbb 0xbbbbbbbb 0xbbbbbbaa 0xaaaabbbb
|
||||||
|
+ 0xbbaaaaaa 0x999999aa 0xaaaabbbb 0xbbcccccc 0x00000000 0x0000aaaa 0xaa000000 0xbbbbbbbb
|
||||||
|
+ 0xbbbbaaaa 0xaa999999 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x99999999 0x9999aaaa 0xaaaaaaaa 0x999999aa 0xaaaaaaaa
|
||||||
|
+ 0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb 0x00000000 0x0000eeee 0xeeffffff 0xcccccccc
|
||||||
|
+ 0xccccdddd 0xddbbbbbb 0xccccccbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbcccc 0xccdddddd
|
||||||
|
+ 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051
|
||||||
|
+ 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200
|
||||||
|
+ 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e
|
||||||
|
+ 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051
|
||||||
|
+ 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200
|
||||||
|
+ 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e
|
||||||
|
+ 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000001 0x06000100 0x01050002 0x00ff0300
|
||||||
|
+ 0xf900fe03 0x00000000 0x00000000 0x0000009b 0x6e370000 0x00000000 0x00fc0009 0x0a00fe00
|
||||||
|
+ 0x060700fe 0x00070800 0x05000b0a 0x00000000 0x00000000 0x000000e2 0x96460000 0x00000000
|
||||||
|
+ 0x000400f7 0xf8000300 0xfcfe0003 0x00fbfc00 0xee00e3f2 0x00000000 0x00000000 0x00000011
|
||||||
|
+ 0xbb550000 0x00000000 0x000600f6 0xfc000300 0xfbfe0004 0x00fafe00 0xf600ecf2 0x00000000
|
||||||
|
+ 0x00000000 0x0000001f 0xbf580000 0x00000000 0x000600f5 0xf6000400 0xf8f90004 0x00f7f800
|
||||||
|
+ 0xf700f0f4 0x00000000 0x00000000 0x00000024 0xbe570000 0x00000000 0x000800f8 0xfe000600
|
||||||
|
+ 0xf8fd0007 0x00f9fe00 0xf500f0f4 0x00000000 0x00000000 0x0000002d 0xd6610000 0x00000000
|
||||||
|
+ 0x000400f7 0xfc000500 0xf7fc0005 0x00f7fc00 0xf900f5f8 0x00000000 0x00000000 0x00000026
|
||||||
|
+ 0xd96e0000 0x00000000 0x000400f7 0xf9000600 0xf5f70005 0x00f5f800 0xf900f4f7 0x00000000
|
||||||
|
+ 0x00000000 0x0000001b 0xce690000 0x00000000 0x000300f8 0xf8000600 0xf6f60004 0x00f6f700
|
||||||
|
+ 0xf900f4f7 0x00000000 0x00000000 0x00000018 0xd8720000 0x00000000 0x00000000 0x02404002
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0xc1c2c1c2 0x41c341c3 0x3fc13fc1 0x40c13fc2 0x3fc240c1 0x41c040c0 0x3fc23fc2 0x40c13fc2
|
||||||
|
+ 0x3fc140c0 0x41c040c0 0x3fc33fc3 0x40c23fc2 0x3fc240c1 0x41c040c0 0x3fc23fc2 0x40c23fc2
|
||||||
|
+ 0x3fc140c1 0x41c040c0 0x00000000 0x00000000 0x41c741c7 0xc1c7c1c7 0x00000000 0x00000000
|
||||||
|
+ 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0
|
||||||
|
+ 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0
|
||||||
|
+ 0x00a0ce00 0x00000000 0xb6840000 0x00000000 0x00000000 0x00000000 0x18181818 0x18181818
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x004b5763 0x0000004b 0x57630000 0x004b5763 0x0000004b 0x57630000 0x88888888 0x08474759
|
||||||
|
+ 0x69780849 0x49596d7a 0x0849495a 0x6d790848 0x48596c78 0x08484858 0x6a780848 0x48586a78
|
||||||
|
+ 0x08484858 0x6c78084a 0x4a5b6d79 0x08474759 0x697a0848 0x48596b79 0x08484859 0x6c7a0848
|
||||||
|
+ 0x48586c79 0x08484857 0x68770848 0x48576877 0x08484857 0x6a77084a 0x4a5a6a77 0x08464659
|
||||||
|
+ 0x69790848 0x48586b79 0x08484858 0x6c7a0848 0x48596c79 0x08484857 0x68770848 0x48576877
|
||||||
|
+ 0x08494958 0x6d7a084b 0x4b5c6c77 0x0847475a 0x6a7b0849 0x495a6e7c 0x0849495a 0x6e7c0849
|
||||||
|
+ 0x495b6e7c 0x08494959 0x6a7a0849 0x49596a7a 0x084a4a5a 0x6f7d084b 0x4b5c6e7b 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x85848484
|
||||||
|
+ 0xc3c4c4c5 0xc4c3c33f 0xc3c3c2c2 0xc2c2c03f 0xc3c3c3c4 0xc4c4c33f 0xc2c2c2c2 0xc1c3c1c1
|
||||||
|
+ 0xc0c08282 0x83848686 0x88880000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00001111 0x00000000
|
||||||
|
+ 0x8080f703 0x10808080 0x80050d13 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x000000a4 0xce000000 0x0000b684 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||||
|
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
|
||||||
|
|
||||||
|
led {
|
||||||
|
led-active-low;
|
||||||
|
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
|
||||||
|
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
|
||||||
|
@@ -55,6 +55,7 @@
|
||||||
|
partition@c00000 {
|
||||||
|
label = "fit";
|
||||||
|
reg = <0xc00000 0x1400000>;
|
||||||
|
+ compatible = "denx,fit";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
|
@ -0,0 +1,131 @@
|
||||||
|
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
|
||||||
|
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
|
||||||
|
@@ -23,7 +23,27 @@
|
||||||
|
no-sd;
|
||||||
|
no-sdio;
|
||||||
|
status = "okay";
|
||||||
|
+
|
||||||
|
+ card@0 {
|
||||||
|
+ compatible = "mmc-card";
|
||||||
|
+ reg = <0>;
|
||||||
|
+
|
||||||
|
+ block {
|
||||||
|
+ compatible = "block-device";
|
||||||
|
+ partitions {
|
||||||
|
+ emmc_rootdisk: block-partition-production {
|
||||||
|
+ partname = "production";
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
};
|
||||||
|
};
|
||||||
|
-};
|
||||||
|
|
||||||
|
+ fragment@1 {
|
||||||
|
+ target-path = "/chosen";
|
||||||
|
+ __overlay__ {
|
||||||
|
+ rootdisk-emmc = <&emmc_rootdisk>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+};
|
||||||
|
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
|
||||||
|
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
|
||||||
|
@@ -29,27 +29,30 @@
|
||||||
|
|
||||||
|
partition@0 {
|
||||||
|
label = "bl2";
|
||||||
|
- reg = <0x0 0x100000>;
|
||||||
|
+ reg = <0x0 0x200000>;
|
||||||
|
read-only;
|
||||||
|
};
|
||||||
|
|
||||||
|
- partition@100000 {
|
||||||
|
- label = "reserved";
|
||||||
|
- reg = <0x100000 0x280000>;
|
||||||
|
- };
|
||||||
|
-
|
||||||
|
- partition@380000 {
|
||||||
|
- label = "fip";
|
||||||
|
- reg = <0x380000 0x200000>;
|
||||||
|
- read-only;
|
||||||
|
- };
|
||||||
|
-
|
||||||
|
- partition@580000 {
|
||||||
|
+ partition@200000 {
|
||||||
|
label = "ubi";
|
||||||
|
- reg = <0x580000 0x7a80000>;
|
||||||
|
+ reg = <0x200000 0x7e00000>;
|
||||||
|
+ compatible = "linux,ubi";
|
||||||
|
+
|
||||||
|
+ volumes {
|
||||||
|
+ nand_rootdisk: ubi-volume-fit {
|
||||||
|
+ volname = "fit";
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
+
|
||||||
|
+ fragment@1 {
|
||||||
|
+ target-path = "/chosen";
|
||||||
|
+ __overlay__ {
|
||||||
|
+ rootdisk-spim-nand = <&nand_rootdisk>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
};
|
||||||
|
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
|
||||||
|
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
|
||||||
|
@@ -52,7 +52,7 @@
|
||||||
|
reg = <0x180000 0xa80000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
- partition@c00000 {
|
||||||
|
+ nor_rootdisk: partition@c00000 {
|
||||||
|
label = "fit";
|
||||||
|
reg = <0xc00000 0x1400000>;
|
||||||
|
compatible = "denx,fit";
|
||||||
|
@@ -61,4 +61,11 @@
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
+
|
||||||
|
+ fragment@1 {
|
||||||
|
+ target-path = "/chosen";
|
||||||
|
+ __overlay__ {
|
||||||
|
+ rootdisk-nor = <&nor_rootdisk>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
};
|
||||||
|
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
|
||||||
|
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
|
||||||
|
@@ -17,6 +17,27 @@
|
||||||
|
max-frequency = <52000000>;
|
||||||
|
cap-sd-highspeed;
|
||||||
|
status = "okay";
|
||||||
|
+
|
||||||
|
+ card@0 {
|
||||||
|
+ compatible = "mmc-card";
|
||||||
|
+ reg = <0>;
|
||||||
|
+
|
||||||
|
+ block {
|
||||||
|
+ compatible = "block-device";
|
||||||
|
+ partitions {
|
||||||
|
+ sd_rootdisk: block-partition-production {
|
||||||
|
+ partname = "production";
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ fragment@1 {
|
||||||
|
+ target-path = "/chosen";
|
||||||
|
+ __overlay__ {
|
||||||
|
+ rootdisk-sd = <&sd_rootdisk>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
|
@ -0,0 +1,66 @@
|
||||||
|
From 28f9a5e2a3f5441ab5594669ed82da11e32277a9 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Kristian Evensen <kristian.evensen@gmail.com>
|
||||||
|
Date: Mon, 30 Apr 2018 14:38:01 +0200
|
||||||
|
Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support
|
||||||
|
|
||||||
|
---
|
||||||
|
drivers/phy/mediatek/phy-mtk-tphy.c | 20 ++++++++++++++++++++
|
||||||
|
1 file changed, 20 insertions(+)
|
||||||
|
|
||||||
|
--- a/drivers/phy/mediatek/phy-mtk-tphy.c
|
||||||
|
+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
|
||||||
|
@@ -18,6 +18,8 @@
|
||||||
|
#include <linux/phy/phy.h>
|
||||||
|
#include <linux/platform_device.h>
|
||||||
|
#include <linux/regmap.h>
|
||||||
|
+#include <linux/mfd/syscon.h>
|
||||||
|
+#include <linux/regmap.h>
|
||||||
|
|
||||||
|
#include "phy-mtk-io.h"
|
||||||
|
|
||||||
|
@@ -267,6 +269,9 @@
|
||||||
|
|
||||||
|
#define USER_BUF_LEN(count) min_t(size_t, 8, (count))
|
||||||
|
|
||||||
|
+#define HIF_SYSCFG1 0x14
|
||||||
|
+#define HIF_SYSCFG1_PHY2_MASK (0x3 << 20)
|
||||||
|
+
|
||||||
|
enum mtk_phy_version {
|
||||||
|
MTK_PHY_V1 = 1,
|
||||||
|
MTK_PHY_V2,
|
||||||
|
@@ -334,6 +339,7 @@ struct mtk_tphy {
|
||||||
|
void __iomem *sif_base; /* only shared sif */
|
||||||
|
const struct mtk_phy_pdata *pdata;
|
||||||
|
struct mtk_phy_instance **phys;
|
||||||
|
+ struct regmap *hif;
|
||||||
|
int nphys;
|
||||||
|
int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
|
||||||
|
int src_coef; /* coefficient for slew rate calibrate */
|
||||||
|
@@ -951,6 +957,10 @@ static void pcie_phy_instance_init(struc
|
||||||
|
if (tphy->pdata->version != MTK_PHY_V1)
|
||||||
|
return;
|
||||||
|
|
||||||
|
+ if (tphy->hif)
|
||||||
|
+ regmap_update_bits(tphy->hif, HIF_SYSCFG1,
|
||||||
|
+ HIF_SYSCFG1_PHY2_MASK, 0);
|
||||||
|
+
|
||||||
|
mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG0,
|
||||||
|
P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H,
|
||||||
|
FIELD_PREP(P3A_RG_XTAL_EXT_PE1H, 0x2) |
|
||||||
|
@@ -1597,6 +1607,16 @@ static int mtk_tphy_probe(struct platfor
|
||||||
|
&tphy->src_coef);
|
||||||
|
}
|
||||||
|
|
||||||
|
+ if (of_find_property(np, "mediatek,phy-switch", NULL)) {
|
||||||
|
+ tphy->hif = syscon_regmap_lookup_by_phandle(np,
|
||||||
|
+ "mediatek,phy-switch");
|
||||||
|
+ if (IS_ERR(tphy->hif)) {
|
||||||
|
+ dev_err(&pdev->dev,
|
||||||
|
+ "missing \"mediatek,phy-switch\" phandle\n");
|
||||||
|
+ return PTR_ERR(tphy->hif);
|
||||||
|
+ }
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
port = 0;
|
||||||
|
for_each_child_of_node(np, child_np) {
|
||||||
|
struct mtk_phy_instance *instance;
|
|
@ -0,0 +1,65 @@
|
||||||
|
From 11db447f257231e08065989100311df57b7f1f1c Mon Sep 17 00:00:00 2001
|
||||||
|
From: Daniel Golle <daniel@makrotopia.org>
|
||||||
|
Date: Sat, 26 Aug 2023 21:06:14 +0100
|
||||||
|
Subject: [PATCH] pinctrl: mediatek: mt7981: add additional uart groups
|
||||||
|
|
||||||
|
Add uart2_0_tx_rx (pin 4, 5) and uart1_2 (pins 9, 10) groups.
|
||||||
|
|
||||||
|
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||||
|
---
|
||||||
|
drivers/pinctrl/mediatek/pinctrl-mt7981.c | 16 +++++++++++++---
|
||||||
|
1 file changed, 13 insertions(+), 3 deletions(-)
|
||||||
|
|
||||||
|
--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
|
||||||
|
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
|
||||||
|
@@ -611,6 +611,9 @@ static int mt7981_wo0_jtag_1_funcs[] = {
|
||||||
|
static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
|
||||||
|
static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
|
||||||
|
|
||||||
|
+static int mt7981_uart2_0_tx_rx_pins[] = { 4, 5, };
|
||||||
|
+static int mt7981_uart2_0_tx_rx_funcs[] = { 3, 3, };
|
||||||
|
+
|
||||||
|
/* GBE_LED0 */
|
||||||
|
static int mt7981_gbe_led0_pins[] = { 8, };
|
||||||
|
static int mt7981_gbe_led0_funcs[] = { 3, };
|
||||||
|
@@ -731,6 +734,9 @@ static int mt7981_uart1_0_funcs[] = { 4,
|
||||||
|
static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
|
||||||
|
static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
|
||||||
|
|
||||||
|
+static int mt7981_uart1_2_pins[] = { 9, 10, };
|
||||||
|
+static int mt7981_uart1_2_funcs[] = { 2, 2, };
|
||||||
|
+
|
||||||
|
/* UART2 */
|
||||||
|
static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
|
||||||
|
static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
|
||||||
|
@@ -805,6 +811,8 @@ static const struct group_desc mt7981_gr
|
||||||
|
PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0),
|
||||||
|
/* @GPIO(4,7) WM_JTAG(3) */
|
||||||
|
PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0),
|
||||||
|
+ /* @GPIO(4,5) WM_JTAG(4) */
|
||||||
|
+ PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7981_uart2_0_tx_rx),
|
||||||
|
/* @GPIO(8) GBE_LED0(3) */
|
||||||
|
PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0),
|
||||||
|
/* @GPIO(4,6) PTA_EXT(4) */
|
||||||
|
@@ -861,6 +869,8 @@ static const struct group_desc mt7981_gr
|
||||||
|
PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0),
|
||||||
|
/* @GPIO(26,29): UART1(2) */
|
||||||
|
PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
|
||||||
|
+ /* @GPIO(9,10): UART1(2) */
|
||||||
|
+ PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2),
|
||||||
|
/* @GPIO(22,25): UART1(3) */
|
||||||
|
PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1),
|
||||||
|
/* @GPIO(22,24) PTA_EXT(4) */
|
||||||
|
@@ -922,9 +932,9 @@ static const struct group_desc mt7981_gr
|
||||||
|
*/
|
||||||
|
static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1",
|
||||||
|
"wa_aice3", "wm_aice1_2", };
|
||||||
|
-static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0",
|
||||||
|
- "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2",
|
||||||
|
- "uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", };
|
||||||
|
+static const char *mt7981_uart_groups[] = { "net_wo0_uart_txd_0", "net_wo0_uart_txd_1",
|
||||||
|
+ "net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart2_0",
|
||||||
|
+ "uart2_0_tx_rx", "uart2_1", "wm_uart_0", "wm_aurt_1", "wm_aurt_2", };
|
||||||
|
static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
|
||||||
|
static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
|
||||||
|
static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", };
|
|
@ -0,0 +1,26 @@
|
||||||
|
--- a/drivers/pinctrl/mediatek/Kconfig
|
||||||
|
+++ b/drivers/pinctrl/mediatek/Kconfig
|
||||||
|
@@ -187,6 +187,13 @@ config PINCTRL_MT7986
|
||||||
|
default ARM64 && ARCH_MEDIATEK
|
||||||
|
select PINCTRL_MTK_MOORE
|
||||||
|
|
||||||
|
+config PINCTRL_MT7988
|
||||||
|
+ bool "Mediatek MT7988 pin control"
|
||||||
|
+ depends on OF
|
||||||
|
+ depends on ARM64 || COMPILE_TEST
|
||||||
|
+ default ARCH_MEDIATEK
|
||||||
|
+ select PINCTRL_MTK_MOORE
|
||||||
|
+
|
||||||
|
config PINCTRL_MT8167
|
||||||
|
bool "MediaTek MT8167 pin control"
|
||||||
|
depends on OF
|
||||||
|
--- a/drivers/pinctrl/mediatek/Makefile
|
||||||
|
+++ b/drivers/pinctrl/mediatek/Makefile
|
||||||
|
@@ -27,6 +27,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl
|
||||||
|
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
|
||||||
|
obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o
|
||||||
|
obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o
|
||||||
|
+obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o
|
||||||
|
obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
|
||||||
|
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
|
||||||
|
obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
|
|
@ -0,0 +1,113 @@
|
||||||
|
From 94b0f301f6ee92f79a2fe2c655dfdbdfe2aec536 Mon Sep 17 00:00:00 2001
|
||||||
|
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
|
||||||
|
Date: Sun, 19 Nov 2023 22:24:16 +0100
|
||||||
|
Subject: [PATCH] dt-bindings: arm: mediatek: move ethsys controller & convert
|
||||||
|
to DT schema
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Type: text/plain; charset=UTF-8
|
||||||
|
Content-Transfer-Encoding: 8bit
|
||||||
|
|
||||||
|
DT schema helps validating DTS files. Binding was moved to clock/ as
|
||||||
|
this hardware is a clock provider. Example required a small fix for
|
||||||
|
"reg" value (1 address cell + 1 size cell).
|
||||||
|
|
||||||
|
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||||
|
Reviewed-by: Rob Herring <robh@kernel.org>
|
||||||
|
Link: https://lore.kernel.org/r/20231119212416.2682-1-zajec5@gmail.com
|
||||||
|
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
||||||
|
---
|
||||||
|
.../bindings/arm/mediatek/mediatek,ethsys.txt | 29 ----------
|
||||||
|
.../bindings/clock/mediatek,ethsys.yaml | 54 +++++++++++++++++++
|
||||||
|
2 files changed, 54 insertions(+), 29 deletions(-)
|
||||||
|
delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
|
||||||
|
create mode 100644 Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
|
||||||
|
|
||||||
|
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
|
||||||
|
+++ /dev/null
|
||||||
|
@@ -1,29 +0,0 @@
|
||||||
|
-Mediatek ethsys controller
|
||||||
|
-============================
|
||||||
|
-
|
||||||
|
-The Mediatek ethsys controller provides various clocks to the system.
|
||||||
|
-
|
||||||
|
-Required Properties:
|
||||||
|
-
|
||||||
|
-- compatible: Should be:
|
||||||
|
- - "mediatek,mt2701-ethsys", "syscon"
|
||||||
|
- - "mediatek,mt7622-ethsys", "syscon"
|
||||||
|
- - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
|
||||||
|
- - "mediatek,mt7629-ethsys", "syscon"
|
||||||
|
- - "mediatek,mt7981-ethsys", "syscon"
|
||||||
|
- - "mediatek,mt7986-ethsys", "syscon"
|
||||||
|
-- #clock-cells: Must be 1
|
||||||
|
-- #reset-cells: Must be 1
|
||||||
|
-
|
||||||
|
-The ethsys controller uses the common clk binding from
|
||||||
|
-Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||||
|
-The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||||
|
-
|
||||||
|
-Example:
|
||||||
|
-
|
||||||
|
-ethsys: clock-controller@1b000000 {
|
||||||
|
- compatible = "mediatek,mt2701-ethsys", "syscon";
|
||||||
|
- reg = <0 0x1b000000 0 0x1000>;
|
||||||
|
- #clock-cells = <1>;
|
||||||
|
- #reset-cells = <1>;
|
||||||
|
-};
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
|
||||||
|
@@ -0,0 +1,54 @@
|
||||||
|
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||||
|
+%YAML 1.2
|
||||||
|
+---
|
||||||
|
+$id: http://devicetree.org/schemas/clock/mediatek,ethsys.yaml#
|
||||||
|
+$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||||
|
+
|
||||||
|
+title: Mediatek ethsys controller
|
||||||
|
+
|
||||||
|
+description:
|
||||||
|
+ The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||||
|
+
|
||||||
|
+maintainers:
|
||||||
|
+ - James Liao <jamesjj.liao@mediatek.com>
|
||||||
|
+
|
||||||
|
+properties:
|
||||||
|
+ compatible:
|
||||||
|
+ oneOf:
|
||||||
|
+ - items:
|
||||||
|
+ - enum:
|
||||||
|
+ - mediatek,mt2701-ethsys
|
||||||
|
+ - mediatek,mt7622-ethsys
|
||||||
|
+ - mediatek,mt7629-ethsys
|
||||||
|
+ - mediatek,mt7981-ethsys
|
||||||
|
+ - mediatek,mt7986-ethsys
|
||||||
|
+ - const: syscon
|
||||||
|
+ - items:
|
||||||
|
+ - const: mediatek,mt7623-ethsys
|
||||||
|
+ - const: mediatek,mt2701-ethsys
|
||||||
|
+ - const: syscon
|
||||||
|
+
|
||||||
|
+ reg:
|
||||||
|
+ maxItems: 1
|
||||||
|
+
|
||||||
|
+ "#clock-cells":
|
||||||
|
+ const: 1
|
||||||
|
+
|
||||||
|
+ "#reset-cells":
|
||||||
|
+ const: 1
|
||||||
|
+
|
||||||
|
+required:
|
||||||
|
+ - reg
|
||||||
|
+ - "#clock-cells"
|
||||||
|
+ - "#reset-cells"
|
||||||
|
+
|
||||||
|
+additionalProperties: false
|
||||||
|
+
|
||||||
|
+examples:
|
||||||
|
+ - |
|
||||||
|
+ clock-controller@1b000000 {
|
||||||
|
+ compatible = "mediatek,mt2701-ethsys", "syscon";
|
||||||
|
+ reg = <0x1b000000 0x1000>;
|
||||||
|
+ #clock-cells = <1>;
|
||||||
|
+ #reset-cells = <1>;
|
||||||
|
+ };
|
|
@ -0,0 +1,35 @@
|
||||||
|
From 5cfa3beb7761cb84be77225902e018d9d3f9b973 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Daniel Golle <daniel@makrotopia.org>
|
||||||
|
Date: Sun, 17 Dec 2023 21:49:45 +0000
|
||||||
|
Subject: [PATCH 1/4] dt-bindings: reset: mediatek: add MT7988 ethwarp reset
|
||||||
|
IDs
|
||||||
|
|
||||||
|
Add reset ID for ethwarp subsystem allowing to reset the built-in
|
||||||
|
Ethernet switch of the MediaTek MT7988 SoC.
|
||||||
|
|
||||||
|
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||||
|
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||||
|
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||||
|
Link: https://lore.kernel.org/r/0c14bbacf471683af67ffa7572bfa1d5c45a0b5d.1702849494.git.daniel@makrotopia.org
|
||||||
|
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
||||||
|
---
|
||||||
|
include/dt-bindings/reset/mediatek,mt7988-resets.h | 13 +++++++++++++
|
||||||
|
1 file changed, 13 insertions(+)
|
||||||
|
create mode 100644 include/dt-bindings/reset/mediatek,mt7988-resets.h
|
||||||
|
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h
|
||||||
|
@@ -0,0 +1,13 @@
|
||||||
|
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||||
|
+/*
|
||||||
|
+ * Copyright (c) 2023 Daniel Golle <daniel@makrotopia.org>
|
||||||
|
+ * Author: Daniel Golle <daniel@makrotopia.org>
|
||||||
|
+ */
|
||||||
|
+
|
||||||
|
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7988
|
||||||
|
+#define _DT_BINDINGS_RESET_CONTROLLER_MT7988
|
||||||
|
+
|
||||||
|
+/* ETHWARP resets */
|
||||||
|
+#define MT7988_ETHWARP_RST_SWITCH 0
|
||||||
|
+
|
||||||
|
+#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */
|
|
@ -0,0 +1,302 @@
|
||||||
|
From 8187e001de156e99ef95366ffd10d627ed090826 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Sam Shih <sam.shih@mediatek.com>
|
||||||
|
Date: Sun, 17 Dec 2023 21:49:33 +0000
|
||||||
|
Subject: [PATCH] dt-bindings: clock: mediatek: add MT7988 clock IDs
|
||||||
|
|
||||||
|
Add MT7988 clock dt-bindings for topckgen, apmixedsys, infracfg,
|
||||||
|
ethernet and xfipll subsystem clocks.
|
||||||
|
|
||||||
|
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
|
||||||
|
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||||
|
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||||
|
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||||
|
Link: https://lore.kernel.org/r/27f99db432e9ccc804cc5b6501d7d17d72cae879.1702849494.git.daniel@makrotopia.org
|
||||||
|
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
||||||
|
---
|
||||||
|
.../dt-bindings/clock/mediatek,mt7988-clk.h | 280 ++++++++++++++++++
|
||||||
|
1 file changed, 280 insertions(+)
|
||||||
|
create mode 100644 include/dt-bindings/clock/mediatek,mt7988-clk.h
|
||||||
|
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/include/dt-bindings/clock/mediatek,mt7988-clk.h
|
||||||
|
@@ -0,0 +1,280 @@
|
||||||
|
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||||
|
+/*
|
||||||
|
+ * Copyright (c) 2023 MediaTek Inc.
|
||||||
|
+ * Author: Sam Shih <sam.shih@mediatek.com>
|
||||||
|
+ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
|
||||||
|
+ */
|
||||||
|
+
|
||||||
|
+#ifndef _DT_BINDINGS_CLK_MT7988_H
|
||||||
|
+#define _DT_BINDINGS_CLK_MT7988_H
|
||||||
|
+
|
||||||
|
+/* APMIXEDSYS */
|
||||||
|
+
|
||||||
|
+#define CLK_APMIXED_NETSYSPLL 0
|
||||||
|
+#define CLK_APMIXED_MPLL 1
|
||||||
|
+#define CLK_APMIXED_MMPLL 2
|
||||||
|
+#define CLK_APMIXED_APLL2 3
|
||||||
|
+#define CLK_APMIXED_NET1PLL 4
|
||||||
|
+#define CLK_APMIXED_NET2PLL 5
|
||||||
|
+#define CLK_APMIXED_WEDMCUPLL 6
|
||||||
|
+#define CLK_APMIXED_SGMPLL 7
|
||||||
|
+#define CLK_APMIXED_ARM_B 8
|
||||||
|
+#define CLK_APMIXED_CCIPLL2_B 9
|
||||||
|
+#define CLK_APMIXED_USXGMIIPLL 10
|
||||||
|
+#define CLK_APMIXED_MSDCPLL 11
|
||||||
|
+
|
||||||
|
+/* TOPCKGEN */
|
||||||
|
+
|
||||||
|
+#define CLK_TOP_XTAL 0
|
||||||
|
+#define CLK_TOP_XTAL_D2 1
|
||||||
|
+#define CLK_TOP_RTC_32K 2
|
||||||
|
+#define CLK_TOP_RTC_32P7K 3
|
||||||
|
+#define CLK_TOP_MPLL_D2 4
|
||||||
|
+#define CLK_TOP_MPLL_D3_D2 5
|
||||||
|
+#define CLK_TOP_MPLL_D4 6
|
||||||
|
+#define CLK_TOP_MPLL_D8 7
|
||||||
|
+#define CLK_TOP_MPLL_D8_D2 8
|
||||||
|
+#define CLK_TOP_MMPLL_D2 9
|
||||||
|
+#define CLK_TOP_MMPLL_D3_D5 10
|
||||||
|
+#define CLK_TOP_MMPLL_D4 11
|
||||||
|
+#define CLK_TOP_MMPLL_D6_D2 12
|
||||||
|
+#define CLK_TOP_MMPLL_D8 13
|
||||||
|
+#define CLK_TOP_APLL2_D4 14
|
||||||
|
+#define CLK_TOP_NET1PLL_D4 15
|
||||||
|
+#define CLK_TOP_NET1PLL_D5 16
|
||||||
|
+#define CLK_TOP_NET1PLL_D5_D2 17
|
||||||
|
+#define CLK_TOP_NET1PLL_D5_D4 18
|
||||||
|
+#define CLK_TOP_NET1PLL_D8 19
|
||||||
|
+#define CLK_TOP_NET1PLL_D8_D2 20
|
||||||
|
+#define CLK_TOP_NET1PLL_D8_D4 21
|
||||||
|
+#define CLK_TOP_NET1PLL_D8_D8 22
|
||||||
|
+#define CLK_TOP_NET1PLL_D8_D16 23
|
||||||
|
+#define CLK_TOP_NET2PLL_D2 24
|
||||||
|
+#define CLK_TOP_NET2PLL_D4 25
|
||||||
|
+#define CLK_TOP_NET2PLL_D4_D4 26
|
||||||
|
+#define CLK_TOP_NET2PLL_D4_D8 27
|
||||||
|
+#define CLK_TOP_NET2PLL_D6 28
|
||||||
|
+#define CLK_TOP_NET2PLL_D8 29
|
||||||
|
+#define CLK_TOP_NETSYS_SEL 30
|
||||||
|
+#define CLK_TOP_NETSYS_500M_SEL 31
|
||||||
|
+#define CLK_TOP_NETSYS_2X_SEL 32
|
||||||
|
+#define CLK_TOP_NETSYS_GSW_SEL 33
|
||||||
|
+#define CLK_TOP_ETH_GMII_SEL 34
|
||||||
|
+#define CLK_TOP_NETSYS_MCU_SEL 35
|
||||||
|
+#define CLK_TOP_NETSYS_PAO_2X_SEL 36
|
||||||
|
+#define CLK_TOP_EIP197_SEL 37
|
||||||
|
+#define CLK_TOP_AXI_INFRA_SEL 38
|
||||||
|
+#define CLK_TOP_UART_SEL 39
|
||||||
|
+#define CLK_TOP_EMMC_250M_SEL 40
|
||||||
|
+#define CLK_TOP_EMMC_400M_SEL 41
|
||||||
|
+#define CLK_TOP_SPI_SEL 42
|
||||||
|
+#define CLK_TOP_SPIM_MST_SEL 43
|
||||||
|
+#define CLK_TOP_NFI1X_SEL 44
|
||||||
|
+#define CLK_TOP_SPINFI_SEL 45
|
||||||
|
+#define CLK_TOP_PWM_SEL 46
|
||||||
|
+#define CLK_TOP_I2C_SEL 47
|
||||||
|
+#define CLK_TOP_PCIE_MBIST_250M_SEL 48
|
||||||
|
+#define CLK_TOP_PEXTP_TL_SEL 49
|
||||||
|
+#define CLK_TOP_PEXTP_TL_P1_SEL 50
|
||||||
|
+#define CLK_TOP_PEXTP_TL_P2_SEL 51
|
||||||
|
+#define CLK_TOP_PEXTP_TL_P3_SEL 52
|
||||||
|
+#define CLK_TOP_USB_SYS_SEL 53
|
||||||
|
+#define CLK_TOP_USB_SYS_P1_SEL 54
|
||||||
|
+#define CLK_TOP_USB_XHCI_SEL 55
|
||||||
|
+#define CLK_TOP_USB_XHCI_P1_SEL 56
|
||||||
|
+#define CLK_TOP_USB_FRMCNT_SEL 57
|
||||||
|
+#define CLK_TOP_USB_FRMCNT_P1_SEL 58
|
||||||
|
+#define CLK_TOP_AUD_SEL 59
|
||||||
|
+#define CLK_TOP_A1SYS_SEL 60
|
||||||
|
+#define CLK_TOP_AUD_L_SEL 61
|
||||||
|
+#define CLK_TOP_A_TUNER_SEL 62
|
||||||
|
+#define CLK_TOP_SSPXTP_SEL 63
|
||||||
|
+#define CLK_TOP_USB_PHY_SEL 64
|
||||||
|
+#define CLK_TOP_USXGMII_SBUS_0_SEL 65
|
||||||
|
+#define CLK_TOP_USXGMII_SBUS_1_SEL 66
|
||||||
|
+#define CLK_TOP_SGM_0_SEL 67
|
||||||
|
+#define CLK_TOP_SGM_SBUS_0_SEL 68
|
||||||
|
+#define CLK_TOP_SGM_1_SEL 69
|
||||||
|
+#define CLK_TOP_SGM_SBUS_1_SEL 70
|
||||||
|
+#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71
|
||||||
|
+#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72
|
||||||
|
+#define CLK_TOP_SYSAXI_SEL 73
|
||||||
|
+#define CLK_TOP_SYSAPB_SEL 74
|
||||||
|
+#define CLK_TOP_ETH_REFCK_50M_SEL 75
|
||||||
|
+#define CLK_TOP_ETH_SYS_200M_SEL 76
|
||||||
|
+#define CLK_TOP_ETH_SYS_SEL 77
|
||||||
|
+#define CLK_TOP_ETH_XGMII_SEL 78
|
||||||
|
+#define CLK_TOP_BUS_TOPS_SEL 79
|
||||||
|
+#define CLK_TOP_NPU_TOPS_SEL 80
|
||||||
|
+#define CLK_TOP_DRAMC_SEL 81
|
||||||
|
+#define CLK_TOP_DRAMC_MD32_SEL 82
|
||||||
|
+#define CLK_TOP_INFRA_F26M_SEL 83
|
||||||
|
+#define CLK_TOP_PEXTP_P0_SEL 84
|
||||||
|
+#define CLK_TOP_PEXTP_P1_SEL 85
|
||||||
|
+#define CLK_TOP_PEXTP_P2_SEL 86
|
||||||
|
+#define CLK_TOP_PEXTP_P3_SEL 87
|
||||||
|
+#define CLK_TOP_DA_XTP_GLB_P0_SEL 88
|
||||||
|
+#define CLK_TOP_DA_XTP_GLB_P1_SEL 89
|
||||||
|
+#define CLK_TOP_DA_XTP_GLB_P2_SEL 90
|
||||||
|
+#define CLK_TOP_DA_XTP_GLB_P3_SEL 91
|
||||||
|
+#define CLK_TOP_CKM_SEL 92
|
||||||
|
+#define CLK_TOP_DA_SEL 93
|
||||||
|
+#define CLK_TOP_PEXTP_SEL 94
|
||||||
|
+#define CLK_TOP_TOPS_P2_26M_SEL 95
|
||||||
|
+#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96
|
||||||
|
+#define CLK_TOP_NETSYS_SYNC_250M_SEL 97
|
||||||
|
+#define CLK_TOP_MACSEC_SEL 98
|
||||||
|
+#define CLK_TOP_NETSYS_TOPS_400M_SEL 99
|
||||||
|
+#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100
|
||||||
|
+#define CLK_TOP_NETSYS_WARP_SEL 101
|
||||||
|
+#define CLK_TOP_ETH_MII_SEL 102
|
||||||
|
+#define CLK_TOP_NPU_SEL 103
|
||||||
|
+#define CLK_TOP_AUD_I2S_M 104
|
||||||
|
+
|
||||||
|
+/* MCUSYS */
|
||||||
|
+
|
||||||
|
+#define CLK_MCU_BUS_DIV_SEL 0
|
||||||
|
+#define CLK_MCU_ARM_DIV_SEL 1
|
||||||
|
+
|
||||||
|
+/* INFRACFG_AO */
|
||||||
|
+
|
||||||
|
+#define CLK_INFRA_MUX_UART0_SEL 0
|
||||||
|
+#define CLK_INFRA_MUX_UART1_SEL 1
|
||||||
|
+#define CLK_INFRA_MUX_UART2_SEL 2
|
||||||
|
+#define CLK_INFRA_MUX_SPI0_SEL 3
|
||||||
|
+#define CLK_INFRA_MUX_SPI1_SEL 4
|
||||||
|
+#define CLK_INFRA_MUX_SPI2_SEL 5
|
||||||
|
+#define CLK_INFRA_PWM_SEL 6
|
||||||
|
+#define CLK_INFRA_PWM_CK1_SEL 7
|
||||||
|
+#define CLK_INFRA_PWM_CK2_SEL 8
|
||||||
|
+#define CLK_INFRA_PWM_CK3_SEL 9
|
||||||
|
+#define CLK_INFRA_PWM_CK4_SEL 10
|
||||||
|
+#define CLK_INFRA_PWM_CK5_SEL 11
|
||||||
|
+#define CLK_INFRA_PWM_CK6_SEL 12
|
||||||
|
+#define CLK_INFRA_PWM_CK7_SEL 13
|
||||||
|
+#define CLK_INFRA_PWM_CK8_SEL 14
|
||||||
|
+#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15
|
||||||
|
+#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16
|
||||||
|
+#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17
|
||||||
|
+#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18
|
||||||
|
+
|
||||||
|
+/* INFRACFG */
|
||||||
|
+
|
||||||
|
+#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19
|
||||||
|
+#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20
|
||||||
|
+#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21
|
||||||
|
+#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22
|
||||||
|
+#define CLK_INFRA_66M_GPT_BCK 23
|
||||||
|
+#define CLK_INFRA_66M_PWM_HCK 24
|
||||||
|
+#define CLK_INFRA_66M_PWM_BCK 25
|
||||||
|
+#define CLK_INFRA_66M_PWM_CK1 26
|
||||||
|
+#define CLK_INFRA_66M_PWM_CK2 27
|
||||||
|
+#define CLK_INFRA_66M_PWM_CK3 28
|
||||||
|
+#define CLK_INFRA_66M_PWM_CK4 29
|
||||||
|
+#define CLK_INFRA_66M_PWM_CK5 30
|
||||||
|
+#define CLK_INFRA_66M_PWM_CK6 31
|
||||||
|
+#define CLK_INFRA_66M_PWM_CK7 32
|
||||||
|
+#define CLK_INFRA_66M_PWM_CK8 33
|
||||||
|
+#define CLK_INFRA_133M_CQDMA_BCK 34
|
||||||
|
+#define CLK_INFRA_66M_AUD_SLV_BCK 35
|
||||||
|
+#define CLK_INFRA_AUD_26M 36
|
||||||
|
+#define CLK_INFRA_AUD_L 37
|
||||||
|
+#define CLK_INFRA_AUD_AUD 38
|
||||||
|
+#define CLK_INFRA_AUD_EG2 39
|
||||||
|
+#define CLK_INFRA_DRAMC_F26M 40
|
||||||
|
+#define CLK_INFRA_133M_DBG_ACKM 41
|
||||||
|
+#define CLK_INFRA_66M_AP_DMA_BCK 42
|
||||||
|
+#define CLK_INFRA_66M_SEJ_BCK 43
|
||||||
|
+#define CLK_INFRA_PRE_CK_SEJ_F13M 44
|
||||||
|
+#define CLK_INFRA_26M_THERM_SYSTEM 45
|
||||||
|
+#define CLK_INFRA_I2C_BCK 46
|
||||||
|
+#define CLK_INFRA_52M_UART0_CK 47
|
||||||
|
+#define CLK_INFRA_52M_UART1_CK 48
|
||||||
|
+#define CLK_INFRA_52M_UART2_CK 49
|
||||||
|
+#define CLK_INFRA_NFI 50
|
||||||
|
+#define CLK_INFRA_SPINFI 51
|
||||||
|
+#define CLK_INFRA_66M_NFI_HCK 52
|
||||||
|
+#define CLK_INFRA_104M_SPI0 53
|
||||||
|
+#define CLK_INFRA_104M_SPI1 54
|
||||||
|
+#define CLK_INFRA_104M_SPI2_BCK 55
|
||||||
|
+#define CLK_INFRA_66M_SPI0_HCK 56
|
||||||
|
+#define CLK_INFRA_66M_SPI1_HCK 57
|
||||||
|
+#define CLK_INFRA_66M_SPI2_HCK 58
|
||||||
|
+#define CLK_INFRA_66M_FLASHIF_AXI 59
|
||||||
|
+#define CLK_INFRA_RTC 60
|
||||||
|
+#define CLK_INFRA_26M_ADC_BCK 61
|
||||||
|
+#define CLK_INFRA_RC_ADC 62
|
||||||
|
+#define CLK_INFRA_MSDC400 63
|
||||||
|
+#define CLK_INFRA_MSDC2_HCK 64
|
||||||
|
+#define CLK_INFRA_133M_MSDC_0_HCK 65
|
||||||
|
+#define CLK_INFRA_66M_MSDC_0_HCK 66
|
||||||
|
+#define CLK_INFRA_133M_CPUM_BCK 67
|
||||||
|
+#define CLK_INFRA_BIST2FPC 68
|
||||||
|
+#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69
|
||||||
|
+#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70
|
||||||
|
+#define CLK_INFRA_133M_USB_HCK 71
|
||||||
|
+#define CLK_INFRA_133M_USB_HCK_CK_P1 72
|
||||||
|
+#define CLK_INFRA_66M_USB_HCK 73
|
||||||
|
+#define CLK_INFRA_66M_USB_HCK_CK_P1 74
|
||||||
|
+#define CLK_INFRA_USB_SYS 75
|
||||||
|
+#define CLK_INFRA_USB_SYS_CK_P1 76
|
||||||
|
+#define CLK_INFRA_USB_REF 77
|
||||||
|
+#define CLK_INFRA_USB_CK_P1 78
|
||||||
|
+#define CLK_INFRA_USB_FRMCNT 79
|
||||||
|
+#define CLK_INFRA_USB_FRMCNT_CK_P1 80
|
||||||
|
+#define CLK_INFRA_USB_PIPE 81
|
||||||
|
+#define CLK_INFRA_USB_PIPE_CK_P1 82
|
||||||
|
+#define CLK_INFRA_USB_UTMI 83
|
||||||
|
+#define CLK_INFRA_USB_UTMI_CK_P1 84
|
||||||
|
+#define CLK_INFRA_USB_XHCI 85
|
||||||
|
+#define CLK_INFRA_USB_XHCI_CK_P1 86
|
||||||
|
+#define CLK_INFRA_PCIE_GFMUX_TL_P0 87
|
||||||
|
+#define CLK_INFRA_PCIE_GFMUX_TL_P1 88
|
||||||
|
+#define CLK_INFRA_PCIE_GFMUX_TL_P2 89
|
||||||
|
+#define CLK_INFRA_PCIE_GFMUX_TL_P3 90
|
||||||
|
+#define CLK_INFRA_PCIE_PIPE_P0 91
|
||||||
|
+#define CLK_INFRA_PCIE_PIPE_P1 92
|
||||||
|
+#define CLK_INFRA_PCIE_PIPE_P2 93
|
||||||
|
+#define CLK_INFRA_PCIE_PIPE_P3 94
|
||||||
|
+#define CLK_INFRA_133M_PCIE_CK_P0 95
|
||||||
|
+#define CLK_INFRA_133M_PCIE_CK_P1 96
|
||||||
|
+#define CLK_INFRA_133M_PCIE_CK_P2 97
|
||||||
|
+#define CLK_INFRA_133M_PCIE_CK_P3 98
|
||||||
|
+
|
||||||
|
+/* ETHDMA */
|
||||||
|
+
|
||||||
|
+#define CLK_ETHDMA_XGP1_EN 0
|
||||||
|
+#define CLK_ETHDMA_XGP2_EN 1
|
||||||
|
+#define CLK_ETHDMA_XGP3_EN 2
|
||||||
|
+#define CLK_ETHDMA_FE_EN 3
|
||||||
|
+#define CLK_ETHDMA_GP2_EN 4
|
||||||
|
+#define CLK_ETHDMA_GP1_EN 5
|
||||||
|
+#define CLK_ETHDMA_GP3_EN 6
|
||||||
|
+#define CLK_ETHDMA_ESW_EN 7
|
||||||
|
+#define CLK_ETHDMA_CRYPT0_EN 8
|
||||||
|
+#define CLK_ETHDMA_NR_CLK 9
|
||||||
|
+
|
||||||
|
+/* SGMIISYS_0 */
|
||||||
|
+
|
||||||
|
+#define CLK_SGM0_TX_EN 0
|
||||||
|
+#define CLK_SGM0_RX_EN 1
|
||||||
|
+#define CLK_SGMII0_NR_CLK 2
|
||||||
|
+
|
||||||
|
+/* SGMIISYS_1 */
|
||||||
|
+
|
||||||
|
+#define CLK_SGM1_TX_EN 0
|
||||||
|
+#define CLK_SGM1_RX_EN 1
|
||||||
|
+#define CLK_SGMII1_NR_CLK 2
|
||||||
|
+
|
||||||
|
+/* ETHWARP */
|
||||||
|
+
|
||||||
|
+#define CLK_ETHWARP_WOCPU2_EN 0
|
||||||
|
+#define CLK_ETHWARP_WOCPU1_EN 1
|
||||||
|
+#define CLK_ETHWARP_WOCPU0_EN 2
|
||||||
|
+#define CLK_ETHWARP_NR_CLK 3
|
||||||
|
+
|
||||||
|
+/* XFIPLL */
|
||||||
|
+#define CLK_XFIPLL_PLL 0
|
||||||
|
+#define CLK_XFIPLL_PLL_EN 1
|
||||||
|
+
|
||||||
|
+#endif /* _DT_BINDINGS_CLK_MT7988_H */
|
|
@ -0,0 +1,260 @@
|
||||||
|
From afd36e9d91b0a840983b829a9e95407d8151f7e7 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Daniel Golle <daniel@makrotopia.org>
|
||||||
|
Date: Sun, 17 Dec 2023 21:49:55 +0000
|
||||||
|
Subject: [PATCH 2/4] dt-bindings: clock: mediatek: add clock controllers of
|
||||||
|
MT7988
|
||||||
|
|
||||||
|
Add various clock controllers found in the MT7988 SoC to existing
|
||||||
|
bindings (if applicable) and add files for the new ethwarp, mcusys
|
||||||
|
and xfi-pll clock controllers not previously present in any SoC.
|
||||||
|
|
||||||
|
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||||
|
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||||
|
Link: https://lore.kernel.org/r/07e76a544ce4392bcb88e34d5480e99bb7994618.1702849494.git.daniel@makrotopia.org
|
||||||
|
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||||
|
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
||||||
|
---
|
||||||
|
.../arm/mediatek/mediatek,infracfg.yaml | 1 +
|
||||||
|
.../bindings/clock/mediatek,apmixedsys.yaml | 1 +
|
||||||
|
.../bindings/clock/mediatek,ethsys.yaml | 1 +
|
||||||
|
.../clock/mediatek,mt7988-ethwarp.yaml | 52 +++++++++++++++
|
||||||
|
.../clock/mediatek,mt7988-xfi-pll.yaml | 48 ++++++++++++++
|
||||||
|
.../bindings/clock/mediatek,topckgen.yaml | 2 +
|
||||||
|
.../bindings/net/pcs/mediatek,sgmiisys.yaml | 65 ++++++++++++++++---
|
||||||
|
7 files changed, 161 insertions(+), 9 deletions(-)
|
||||||
|
create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml
|
||||||
|
create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml
|
||||||
|
|
||||||
|
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
|
||||||
|
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
|
||||||
|
@@ -30,6 +30,7 @@ properties:
|
||||||
|
- mediatek,mt7629-infracfg
|
||||||
|
- mediatek,mt7981-infracfg
|
||||||
|
- mediatek,mt7986-infracfg
|
||||||
|
+ - mediatek,mt7988-infracfg
|
||||||
|
- mediatek,mt8135-infracfg
|
||||||
|
- mediatek,mt8167-infracfg
|
||||||
|
- mediatek,mt8173-infracfg
|
||||||
|
--- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
|
||||||
|
+++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
|
||||||
|
@@ -22,6 +22,7 @@ properties:
|
||||||
|
- mediatek,mt7622-apmixedsys
|
||||||
|
- mediatek,mt7981-apmixedsys
|
||||||
|
- mediatek,mt7986-apmixedsys
|
||||||
|
+ - mediatek,mt7988-apmixedsys
|
||||||
|
- mediatek,mt8135-apmixedsys
|
||||||
|
- mediatek,mt8173-apmixedsys
|
||||||
|
- mediatek,mt8516-apmixedsys
|
||||||
|
--- a/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
|
||||||
|
+++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
|
||||||
|
@@ -22,6 +22,7 @@ properties:
|
||||||
|
- mediatek,mt7629-ethsys
|
||||||
|
- mediatek,mt7981-ethsys
|
||||||
|
- mediatek,mt7986-ethsys
|
||||||
|
+ - mediatek,mt7988-ethsys
|
||||||
|
- const: syscon
|
||||||
|
- items:
|
||||||
|
- const: mediatek,mt7623-ethsys
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml
|
||||||
|
@@ -0,0 +1,52 @@
|
||||||
|
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||||
|
+%YAML 1.2
|
||||||
|
+---
|
||||||
|
+$id: http://devicetree.org/schemas/clock/mediatek,mt7988-ethwarp.yaml#
|
||||||
|
+$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||||
|
+
|
||||||
|
+title: MediaTek MT7988 ethwarp Controller
|
||||||
|
+
|
||||||
|
+maintainers:
|
||||||
|
+ - Daniel Golle <daniel@makrotopia.org>
|
||||||
|
+
|
||||||
|
+description:
|
||||||
|
+ The Mediatek MT7988 ethwarp controller provides clocks and resets for the
|
||||||
|
+ Ethernet related subsystems found the MT7988 SoC.
|
||||||
|
+ The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
|
||||||
|
+
|
||||||
|
+properties:
|
||||||
|
+ compatible:
|
||||||
|
+ items:
|
||||||
|
+ - const: mediatek,mt7988-ethwarp
|
||||||
|
+
|
||||||
|
+ reg:
|
||||||
|
+ maxItems: 1
|
||||||
|
+
|
||||||
|
+ '#clock-cells':
|
||||||
|
+ const: 1
|
||||||
|
+
|
||||||
|
+ '#reset-cells':
|
||||||
|
+ const: 1
|
||||||
|
+
|
||||||
|
+required:
|
||||||
|
+ - compatible
|
||||||
|
+ - reg
|
||||||
|
+ - '#clock-cells'
|
||||||
|
+ - '#reset-cells'
|
||||||
|
+
|
||||||
|
+additionalProperties: false
|
||||||
|
+
|
||||||
|
+examples:
|
||||||
|
+ - |
|
||||||
|
+ #include <dt-bindings/reset/ti-syscon.h>
|
||||||
|
+ soc {
|
||||||
|
+ #address-cells = <2>;
|
||||||
|
+ #size-cells = <2>;
|
||||||
|
+
|
||||||
|
+ clock-controller@15031000 {
|
||||||
|
+ compatible = "mediatek,mt7988-ethwarp";
|
||||||
|
+ reg = <0 0x15031000 0 0x1000>;
|
||||||
|
+ #clock-cells = <1>;
|
||||||
|
+ #reset-cells = <1>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml
|
||||||
|
@@ -0,0 +1,48 @@
|
||||||
|
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||||
|
+%YAML 1.2
|
||||||
|
+---
|
||||||
|
+$id: http://devicetree.org/schemas/clock/mediatek,mt7988-xfi-pll.yaml#
|
||||||
|
+$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||||
|
+
|
||||||
|
+title: MediaTek MT7988 XFI PLL Clock Controller
|
||||||
|
+
|
||||||
|
+maintainers:
|
||||||
|
+ - Daniel Golle <daniel@makrotopia.org>
|
||||||
|
+
|
||||||
|
+description:
|
||||||
|
+ The MediaTek XFI PLL controller provides the 156.25MHz clock for the
|
||||||
|
+ Ethernet SerDes PHY from the 40MHz top_xtal clock.
|
||||||
|
+
|
||||||
|
+properties:
|
||||||
|
+ compatible:
|
||||||
|
+ const: mediatek,mt7988-xfi-pll
|
||||||
|
+
|
||||||
|
+ reg:
|
||||||
|
+ maxItems: 1
|
||||||
|
+
|
||||||
|
+ resets:
|
||||||
|
+ maxItems: 1
|
||||||
|
+
|
||||||
|
+ '#clock-cells':
|
||||||
|
+ const: 1
|
||||||
|
+
|
||||||
|
+required:
|
||||||
|
+ - compatible
|
||||||
|
+ - reg
|
||||||
|
+ - resets
|
||||||
|
+ - '#clock-cells'
|
||||||
|
+
|
||||||
|
+additionalProperties: false
|
||||||
|
+
|
||||||
|
+examples:
|
||||||
|
+ - |
|
||||||
|
+ soc {
|
||||||
|
+ #address-cells = <2>;
|
||||||
|
+ #size-cells = <2>;
|
||||||
|
+ clock-controller@11f40000 {
|
||||||
|
+ compatible = "mediatek,mt7988-xfi-pll";
|
||||||
|
+ reg = <0 0x11f40000 0 0x1000>;
|
||||||
|
+ resets = <&watchdog 16>;
|
||||||
|
+ #clock-cells = <1>;
|
||||||
|
+ };
|
||||||
|
+ };
|
||||||
|
--- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
|
||||||
|
+++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
|
||||||
|
@@ -37,6 +37,8 @@ properties:
|
||||||
|
- mediatek,mt7629-topckgen
|
||||||
|
- mediatek,mt7981-topckgen
|
||||||
|
- mediatek,mt7986-topckgen
|
||||||
|
+ - mediatek,mt7988-mcusys
|
||||||
|
+ - mediatek,mt7988-topckgen
|
||||||
|
- mediatek,mt8167-topckgen
|
||||||
|
- mediatek,mt8183-topckgen
|
||||||
|
- const: syscon
|
||||||
|
--- a/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
|
||||||
|
+++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
|
||||||
|
@@ -15,15 +15,22 @@ description:
|
||||||
|
|
||||||
|
properties:
|
||||||
|
compatible:
|
||||||
|
- items:
|
||||||
|
- - enum:
|
||||||
|
- - mediatek,mt7622-sgmiisys
|
||||||
|
- - mediatek,mt7629-sgmiisys
|
||||||
|
- - mediatek,mt7981-sgmiisys_0
|
||||||
|
- - mediatek,mt7981-sgmiisys_1
|
||||||
|
- - mediatek,mt7986-sgmiisys_0
|
||||||
|
- - mediatek,mt7986-sgmiisys_1
|
||||||
|
- - const: syscon
|
||||||
|
+ oneOf:
|
||||||
|
+ - items:
|
||||||
|
+ - enum:
|
||||||
|
+ - mediatek,mt7622-sgmiisys
|
||||||
|
+ - mediatek,mt7629-sgmiisys
|
||||||
|
+ - mediatek,mt7981-sgmiisys_0
|
||||||
|
+ - mediatek,mt7981-sgmiisys_1
|
||||||
|
+ - mediatek,mt7986-sgmiisys_0
|
||||||
|
+ - mediatek,mt7986-sgmiisys_1
|
||||||
|
+ - const: syscon
|
||||||
|
+ - items:
|
||||||
|
+ - enum:
|
||||||
|
+ - mediatek,mt7988-sgmiisys0
|
||||||
|
+ - mediatek,mt7988-sgmiisys1
|
||||||
|
+ - const: simple-mfd
|
||||||
|
+ - const: syscon
|
||||||
|
|
||||||
|
reg:
|
||||||
|
maxItems: 1
|
||||||
|
@@ -35,11 +42,51 @@ properties:
|
||||||
|
description: Invert polarity of the SGMII data lanes
|
||||||
|
type: boolean
|
||||||
|
|
||||||
|
+ pcs:
|
||||||
|
+ type: object
|
||||||
|
+ description: MediaTek LynxI HSGMII PCS
|
||||||
|
+ properties:
|
||||||
|
+ compatible:
|
||||||
|
+ const: mediatek,mt7988-sgmii
|
||||||
|
+
|
||||||
|
+ clocks:
|
||||||
|
+ maxItems: 3
|
||||||
|
+
|
||||||
|
+ clock-names:
|
||||||
|
+ items:
|
||||||
|
+ - const: sgmii_sel
|
||||||
|
+ - const: sgmii_tx
|
||||||
|
+ - const: sgmii_rx
|
||||||
|
+
|
||||||
|
+ required:
|
||||||
|
+ - compatible
|
||||||
|
+ - clocks
|
||||||
|
+ - clock-names
|
||||||
|
+
|
||||||
|
+ additionalProperties: false
|
||||||
|
+
|
||||||
|
required:
|
||||||
|
- compatible
|
||||||
|
- reg
|
||||||
|
- '#clock-cells'
|
||||||
|
|
||||||
|
+allOf:
|
||||||
|
+ - if:
|
||||||
|
+ properties:
|
||||||
|
+ compatible:
|
||||||
|
+ contains:
|
||||||
|
+ enum:
|
||||||
|
+ - mediatek,mt7988-sgmiisys0
|
||||||
|
+ - mediatek,mt7988-sgmiisys1
|
||||||
|
+
|
||||||
|
+ then:
|
||||||
|
+ required:
|
||||||
|
+ - pcs
|
||||||
|
+
|
||||||
|
+ else:
|
||||||
|
+ properties:
|
||||||
|
+ pcs: false
|
||||||
|
+
|
||||||
|
additionalProperties: false
|
||||||
|
|
||||||
|
examples:
|
|
@ -0,0 +1,50 @@
|
||||||
|
From d9bf944beaaad1890ad3fcb755c61e1c7e4c5630 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Sam Shih <sam.shih@mediatek.com>
|
||||||
|
Date: Sun, 17 Dec 2023 21:50:07 +0000
|
||||||
|
Subject: [PATCH 3/4] clk: mediatek: add pcw_chg_bit control for PLLs of MT7988
|
||||||
|
|
||||||
|
Introduce pcw_chg_bit member to struct mtk_pll_data and use it instead
|
||||||
|
of the previously hardcoded PCW_CHG_MASK macro if set.
|
||||||
|
This will needed for clocks on the MT7988 SoC.
|
||||||
|
|
||||||
|
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
|
||||||
|
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||||
|
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||||
|
Link: https://lore.kernel.org/r/3b9c65ddb08c8bedf790aacf29871af026b6f0b7.1702849494.git.daniel@makrotopia.org
|
||||||
|
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
||||||
|
---
|
||||||
|
drivers/clk/mediatek/clk-pll.c | 5 +++--
|
||||||
|
drivers/clk/mediatek/clk-pll.h | 1 +
|
||||||
|
2 files changed, 4 insertions(+), 2 deletions(-)
|
||||||
|
|
||||||
|
--- a/drivers/clk/mediatek/clk-pll.c
|
||||||
|
+++ b/drivers/clk/mediatek/clk-pll.c
|
||||||
|
@@ -23,7 +23,7 @@
|
||||||
|
#define CON0_BASE_EN BIT(0)
|
||||||
|
#define CON0_PWR_ON BIT(0)
|
||||||
|
#define CON0_ISO_EN BIT(1)
|
||||||
|
-#define PCW_CHG_MASK BIT(31)
|
||||||
|
+#define PCW_CHG_BIT 31
|
||||||
|
|
||||||
|
#define AUDPLL_TUNER_EN BIT(31)
|
||||||
|
|
||||||
|
@@ -114,7 +114,8 @@ static void mtk_pll_set_rate_regs(struct
|
||||||
|
pll->data->pcw_shift);
|
||||||
|
val |= pcw << pll->data->pcw_shift;
|
||||||
|
writel(val, pll->pcw_addr);
|
||||||
|
- chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
|
||||||
|
+ chg = readl(pll->pcw_chg_addr) |
|
||||||
|
+ BIT(pll->data->pcw_chg_bit ? : PCW_CHG_BIT);
|
||||||
|
writel(chg, pll->pcw_chg_addr);
|
||||||
|
if (pll->tuner_addr)
|
||||||
|
writel(val + 1, pll->tuner_addr);
|
||||||
|
--- a/drivers/clk/mediatek/clk-pll.h
|
||||||
|
+++ b/drivers/clk/mediatek/clk-pll.h
|
||||||
|
@@ -48,6 +48,7 @@ struct mtk_pll_data {
|
||||||
|
const char *parent_name;
|
||||||
|
u32 en_reg;
|
||||||
|
u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
|
||||||
|
+ u8 pcw_chg_bit;
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
File diff suppressed because it is too large
Load diff
|
@ -0,0 +1,57 @@
|
||||||
|
From 26ced94177b150710d94cf365002a09cc48950e9 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Frank Wunderlich <frank-w@public-files.de>
|
||||||
|
Date: Wed, 17 Jan 2024 19:41:11 +0100
|
||||||
|
Subject: [PATCH] clk: mediatek: add infracfg reset controller for mt7988
|
||||||
|
|
||||||
|
Infracfg can also operate as reset controller, add support for it.
|
||||||
|
|
||||||
|
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
|
||||||
|
---
|
||||||
|
drivers/clk/mediatek/clk-mt7988-infracfg.c | 23 ++++++++++++++++++++++
|
||||||
|
1 file changed, 23 insertions(+)
|
||||||
|
|
||||||
|
--- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
|
||||||
|
+++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
|
||||||
|
@@ -14,6 +14,10 @@
|
||||||
|
#include "clk-gate.h"
|
||||||
|
#include "clk-mux.h"
|
||||||
|
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
|
||||||
|
+#include <dt-bindings/reset/mediatek,mt7988-resets.h>
|
||||||
|
+
|
||||||
|
+#define MT7988_INFRA_RST0_SET_OFFSET 0x70
|
||||||
|
+#define MT7988_INFRA_RST1_SET_OFFSET 0x80
|
||||||
|
|
||||||
|
static DEFINE_SPINLOCK(mt7988_clk_lock);
|
||||||
|
|
||||||
|
@@ -249,12 +253,31 @@ static const struct mtk_gate infra_clks[
|
||||||
|
GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31),
|
||||||
|
};
|
||||||
|
|
||||||
|
+static u16 infra_rst_ofs[] = {
|
||||||
|
+ MT7988_INFRA_RST0_SET_OFFSET,
|
||||||
|
+ MT7988_INFRA_RST1_SET_OFFSET,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static u16 infra_idx_map[] = {
|
||||||
|
+ [MT7988_INFRA_RST0_PEXTP_MAC_SWRST] = 0 * RST_NR_PER_BANK + 6,
|
||||||
|
+ [MT7988_INFRA_RST1_THERM_CTRL_SWRST] = 1 * RST_NR_PER_BANK + 9,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static struct mtk_clk_rst_desc infra_rst_desc = {
|
||||||
|
+ .version = MTK_RST_SET_CLR,
|
||||||
|
+ .rst_bank_ofs = infra_rst_ofs,
|
||||||
|
+ .rst_bank_nr = ARRAY_SIZE(infra_rst_ofs),
|
||||||
|
+ .rst_idx_map = infra_idx_map,
|
||||||
|
+ .rst_idx_map_nr = ARRAY_SIZE(infra_idx_map),
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
static const struct mtk_clk_desc infra_desc = {
|
||||||
|
.clks = infra_clks,
|
||||||
|
.num_clks = ARRAY_SIZE(infra_clks),
|
||||||
|
.mux_clks = infra_muxes,
|
||||||
|
.num_mux_clks = ARRAY_SIZE(infra_muxes),
|
||||||
|
.clk_lock = &mt7988_clk_lock,
|
||||||
|
+ .rst_desc = &infra_rst_desc,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct of_device_id of_match_clk_mt7988_infracfg[] = {
|
|
@ -0,0 +1,25 @@
|
||||||
|
From 3c810da3206f2e52c92f9f15a87f05db4bbba734 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Frank Wunderlich <frank-w@public-files.de>
|
||||||
|
Date: Wed, 17 Jan 2024 19:41:10 +0100
|
||||||
|
Subject: [PATCH] dt-bindings: reset: mediatek: add MT7988 reset IDs
|
||||||
|
|
||||||
|
Add reset constants for using as index in driver and dts.
|
||||||
|
|
||||||
|
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
|
||||||
|
---
|
||||||
|
include/dt-bindings/reset/mediatek,mt7988-resets.h | 6 ++++++
|
||||||
|
1 file changed, 6 insertions(+)
|
||||||
|
|
||||||
|
--- a/include/dt-bindings/reset/mediatek,mt7988-resets.h
|
||||||
|
+++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h
|
||||||
|
@@ -10,4 +10,10 @@
|
||||||
|
/* ETHWARP resets */
|
||||||
|
#define MT7988_ETHWARP_RST_SWITCH 0
|
||||||
|
|
||||||
|
+/* INFRA resets */
|
||||||
|
+#define MT7988_INFRA_RST0_PEXTP_MAC_SWRST 0
|
||||||
|
+#define MT7988_INFRA_RST1_THERM_CTRL_SWRST 1
|
||||||
|
+
|
||||||
|
+
|
||||||
|
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */
|
||||||
|
+
|
|
@ -0,0 +1,125 @@
|
||||||
|
From 137c9e08e5e542d58aa606b0bb4f0990117309a0 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Daniel Golle <daniel@makrotopia.org>
|
||||||
|
Date: Mon, 20 Nov 2023 18:22:31 +0000
|
||||||
|
Subject: [PATCH] watchdog: mediatek: mt7988: add wdt support
|
||||||
|
|
||||||
|
Add support for watchdog and reset generator unit of the MediaTek
|
||||||
|
MT7988 SoC.
|
||||||
|
|
||||||
|
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||||
|
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||||
|
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
|
||||||
|
Link: https://lore.kernel.org/r/c0cf5f701801cce60470853fa15f1d9dced78c4f.1700504385.git.daniel@makrotopia.org
|
||||||
|
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
|
||||||
|
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
|
||||||
|
---
|
||||||
|
drivers/watchdog/mtk_wdt.c | 42 ++++++++++++++++++++++++++++++++++++++
|
||||||
|
1 file changed, 42 insertions(+)
|
||||||
|
|
||||||
|
--- a/drivers/watchdog/mtk_wdt.c
|
||||||
|
+++ b/drivers/watchdog/mtk_wdt.c
|
||||||
|
@@ -58,9 +58,13 @@
|
||||||
|
#define WDT_SWSYSRST 0x18U
|
||||||
|
#define WDT_SWSYS_RST_KEY 0x88000000
|
||||||
|
|
||||||
|
+#define WDT_SWSYSRST_EN 0xfc
|
||||||
|
+
|
||||||
|
#define DRV_NAME "mtk-wdt"
|
||||||
|
#define DRV_VERSION "1.0"
|
||||||
|
|
||||||
|
+#define MT7988_TOPRGU_SW_RST_NUM 24
|
||||||
|
+
|
||||||
|
static bool nowayout = WATCHDOG_NOWAYOUT;
|
||||||
|
static unsigned int timeout;
|
||||||
|
|
||||||
|
@@ -71,10 +75,12 @@ struct mtk_wdt_dev {
|
||||||
|
struct reset_controller_dev rcdev;
|
||||||
|
bool disable_wdt_extrst;
|
||||||
|
bool reset_by_toprgu;
|
||||||
|
+ bool has_swsysrst_en;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct mtk_wdt_data {
|
||||||
|
int toprgu_sw_rst_num;
|
||||||
|
+ bool has_swsysrst_en;
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct mtk_wdt_data mt2712_data = {
|
||||||
|
@@ -89,6 +95,11 @@ static const struct mtk_wdt_data mt7986_
|
||||||
|
.toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM,
|
||||||
|
};
|
||||||
|
|
||||||
|
+static const struct mtk_wdt_data mt7988_data = {
|
||||||
|
+ .toprgu_sw_rst_num = MT7988_TOPRGU_SW_RST_NUM,
|
||||||
|
+ .has_swsysrst_en = true,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
static const struct mtk_wdt_data mt8183_data = {
|
||||||
|
.toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
|
||||||
|
};
|
||||||
|
@@ -109,6 +120,28 @@ static const struct mtk_wdt_data mt8195_
|
||||||
|
.toprgu_sw_rst_num = MT8195_TOPRGU_SW_RST_NUM,
|
||||||
|
};
|
||||||
|
|
||||||
|
+/**
|
||||||
|
+ * toprgu_reset_sw_en_unlocked() - enable/disable software control for reset bit
|
||||||
|
+ * @data: Pointer to instance of driver data.
|
||||||
|
+ * @id: Bit number identifying the reset to be enabled or disabled.
|
||||||
|
+ * @enable: If true, enable software control for that bit, disable otherwise.
|
||||||
|
+ *
|
||||||
|
+ * Context: The caller must hold lock of struct mtk_wdt_dev.
|
||||||
|
+ */
|
||||||
|
+static void toprgu_reset_sw_en_unlocked(struct mtk_wdt_dev *data,
|
||||||
|
+ unsigned long id, bool enable)
|
||||||
|
+{
|
||||||
|
+ u32 tmp;
|
||||||
|
+
|
||||||
|
+ tmp = readl(data->wdt_base + WDT_SWSYSRST_EN);
|
||||||
|
+ if (enable)
|
||||||
|
+ tmp |= BIT(id);
|
||||||
|
+ else
|
||||||
|
+ tmp &= ~BIT(id);
|
||||||
|
+
|
||||||
|
+ writel(tmp, data->wdt_base + WDT_SWSYSRST_EN);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
static int toprgu_reset_update(struct reset_controller_dev *rcdev,
|
||||||
|
unsigned long id, bool assert)
|
||||||
|
{
|
||||||
|
@@ -119,6 +152,9 @@ static int toprgu_reset_update(struct re
|
||||||
|
|
||||||
|
spin_lock_irqsave(&data->lock, flags);
|
||||||
|
|
||||||
|
+ if (assert && data->has_swsysrst_en)
|
||||||
|
+ toprgu_reset_sw_en_unlocked(data, id, true);
|
||||||
|
+
|
||||||
|
tmp = readl(data->wdt_base + WDT_SWSYSRST);
|
||||||
|
if (assert)
|
||||||
|
tmp |= BIT(id);
|
||||||
|
@@ -127,6 +163,9 @@ static int toprgu_reset_update(struct re
|
||||||
|
tmp |= WDT_SWSYS_RST_KEY;
|
||||||
|
writel(tmp, data->wdt_base + WDT_SWSYSRST);
|
||||||
|
|
||||||
|
+ if (!assert && data->has_swsysrst_en)
|
||||||
|
+ toprgu_reset_sw_en_unlocked(data, id, false);
|
||||||
|
+
|
||||||
|
spin_unlock_irqrestore(&data->lock, flags);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
@@ -406,6 +445,8 @@ static int mtk_wdt_probe(struct platform
|
||||||
|
wdt_data->toprgu_sw_rst_num);
|
||||||
|
if (err)
|
||||||
|
return err;
|
||||||
|
+
|
||||||
|
+ mtk_wdt->has_swsysrst_en = wdt_data->has_swsysrst_en;
|
||||||
|
}
|
||||||
|
|
||||||
|
mtk_wdt->disable_wdt_extrst =
|
||||||
|
@@ -444,6 +485,7 @@ static const struct of_device_id mtk_wdt
|
||||||
|
{ .compatible = "mediatek,mt6589-wdt" },
|
||||||
|
{ .compatible = "mediatek,mt6795-wdt", .data = &mt6795_data },
|
||||||
|
{ .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data },
|
||||||
|
+ { .compatible = "mediatek,mt7988-wdt", .data = &mt7988_data },
|
||||||
|
{ .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
|
||||||
|
{ .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data },
|
||||||
|
{ .compatible = "mediatek,mt8188-wdt", .data = &mt8188_data },
|
|
@ -0,0 +1,31 @@
|
||||||
|
From c202f510bbaa34ab5d65a69a61e0e72761374b17 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Daniel Golle <daniel@makrotopia.org>
|
||||||
|
Date: Mon, 11 Mar 2024 17:14:19 +0000
|
||||||
|
Subject: [PATCH] clk: mediatek: mt7988-infracfg: fix clocks for 2nd PCIe port
|
||||||
|
|
||||||
|
Due to what seems to be an undocumented oddity in MediaTek's MT7988
|
||||||
|
SoC design the CLK_INFRA_PCIE_PERI_26M_CK_P2 clock requires
|
||||||
|
CLK_INFRA_PCIE_PERI_26M_CK_P3 to be enabled.
|
||||||
|
|
||||||
|
This currently leads to PCIe port 2 not working in Linux.
|
||||||
|
|
||||||
|
Reflect the apparent relationship in the clk driver to make sure PCIe
|
||||||
|
port 2 of the MT7988 SoC works.
|
||||||
|
|
||||||
|
Suggested-by: Sam Shih <sam.shih@mediatek.com>
|
||||||
|
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||||
|
---
|
||||||
|
drivers/clk/mediatek/clk-mt7988-infracfg.c | 2 +-
|
||||||
|
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||||
|
|
||||||
|
--- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
|
||||||
|
+++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
|
||||||
|
@@ -156,7 +156,7 @@ static const struct mtk_gate infra_clks[
|
||||||
|
GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, "infra_pcie_peri_ck_26m_ck_p1",
|
||||||
|
"csw_infra_f26m_sel", 8),
|
||||||
|
GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, "infra_pcie_peri_ck_26m_ck_p2",
|
||||||
|
- "csw_infra_f26m_sel", 9),
|
||||||
|
+ "infra_pcie_peri_ck_26m_ck_p3", 9),
|
||||||
|
GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, "infra_pcie_peri_ck_26m_ck_p3",
|
||||||
|
"csw_infra_f26m_sel", 10),
|
||||||
|
/* INFRA1 */
|
|
@ -0,0 +1,63 @@
|
||||||
|
From patchwork Wed Jan 17 12:42:33 2024
|
||||||
|
Content-Type: text/plain; charset="utf-8"
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Transfer-Encoding: 7bit
|
||||||
|
X-Patchwork-Submitter: Jean Thomas <jean.thomas@wifirst.fr>
|
||||||
|
X-Patchwork-Id: 13521682
|
||||||
|
Return-Path:
|
||||||
|
<linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org>
|
||||||
|
From: Jean Thomas <jean.thomas@wifirst.fr>
|
||||||
|
To: sean.wang@kernel.org,
|
||||||
|
linus.walleij@linaro.org,
|
||||||
|
matthias.bgg@gmail.com,
|
||||||
|
angelogioacchino.delregno@collabora.com,
|
||||||
|
linux-mediatek@lists.infradead.org,
|
||||||
|
linux-gpio@vger.kernel.org,
|
||||||
|
linux-kernel@vger.kernel.org,
|
||||||
|
linux-arm-kernel@lists.infradead.org
|
||||||
|
Cc: Jean Thomas <jean.thomas@wifirst.fr>
|
||||||
|
Subject: [PATCH 1/2] pinctrl: mediatek: mt7981: add additional uart group
|
||||||
|
Date: Wed, 17 Jan 2024 13:42:33 +0100
|
||||||
|
Message-Id: <20240117124234.3137050-1-jean.thomas@wifirst.fr>
|
||||||
|
MIME-Version: 1.0
|
||||||
|
List-Id: <linux-mediatek.lists.infradead.org>
|
||||||
|
|
||||||
|
Add uart1_3 (pins 26, 27) group to the pinctrl driver for the
|
||||||
|
MediaTek MT7981 SoC.
|
||||||
|
|
||||||
|
Signed-off-by: Jean Thomas <jean.thomas@wifirst.fr>
|
||||||
|
Reviewed-by: Daniel Golle <daniel@makrotopia.org>
|
||||||
|
---
|
||||||
|
drivers/pinctrl/mediatek/pinctrl-mt7981.c | 7 ++++++-
|
||||||
|
1 file changed, 6 insertions(+), 1 deletion(-)
|
||||||
|
|
||||||
|
--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
|
||||||
|
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
|
||||||
|
@@ -737,6 +737,9 @@ static int mt7981_uart1_1_funcs[] = { 2,
|
||||||
|
static int mt7981_uart1_2_pins[] = { 9, 10, };
|
||||||
|
static int mt7981_uart1_2_funcs[] = { 2, 2, };
|
||||||
|
|
||||||
|
+static int mt7981_uart1_3_pins[] = { 26, 27, };
|
||||||
|
+static int mt7981_uart1_3_funcs[] = { 2, 2, };
|
||||||
|
+
|
||||||
|
/* UART2 */
|
||||||
|
static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
|
||||||
|
static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
|
||||||
|
@@ -871,6 +874,8 @@ static const struct group_desc mt7981_gr
|
||||||
|
PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
|
||||||
|
/* @GPIO(9,10): UART1(2) */
|
||||||
|
PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2),
|
||||||
|
+ /* @GPIO(26,27): UART1(2) */
|
||||||
|
+ PINCTRL_PIN_GROUP("uart1_3", mt7981_uart1_3),
|
||||||
|
/* @GPIO(22,25): UART1(3) */
|
||||||
|
PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1),
|
||||||
|
/* @GPIO(22,24) PTA_EXT(4) */
|
||||||
|
@@ -933,7 +938,7 @@ static const struct group_desc mt7981_gr
|
||||||
|
static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1",
|
||||||
|
"wa_aice3", "wm_aice1_2", };
|
||||||
|
static const char *mt7981_uart_groups[] = { "net_wo0_uart_txd_0", "net_wo0_uart_txd_1",
|
||||||
|
- "net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart2_0",
|
||||||
|
+ "net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart1_3", "uart2_0",
|
||||||
|
"uart2_0_tx_rx", "uart2_1", "wm_uart_0", "wm_aurt_1", "wm_aurt_2", };
|
||||||
|
static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
|
||||||
|
static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
|
|
@ -0,0 +1,82 @@
|
||||||
|
From patchwork Wed Jan 17 14:55:47 2024
|
||||||
|
Content-Type: text/plain; charset="utf-8"
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Transfer-Encoding: 7bit
|
||||||
|
X-Patchwork-Submitter: Jean Thomas <jean.thomas@wifirst.fr>
|
||||||
|
X-Patchwork-Id: 13521855
|
||||||
|
Return-Path:
|
||||||
|
<linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org>
|
||||||
|
From: Jean Thomas <jean.thomas@wifirst.fr>
|
||||||
|
To: sean.wang@kernel.org,
|
||||||
|
linus.walleij@linaro.org,
|
||||||
|
matthias.bgg@gmail.com,
|
||||||
|
angelogioacchino.delregno@collabora.com,
|
||||||
|
linux-mediatek@lists.infradead.org,
|
||||||
|
linux-gpio@vger.kernel.org,
|
||||||
|
linux-kernel@vger.kernel.org,
|
||||||
|
linux-arm-kernel@lists.infradead.org
|
||||||
|
Cc: Jean Thomas <jean.thomas@wifirst.fr>,
|
||||||
|
Daniel Golle <daniel@makrotopia.org>
|
||||||
|
Subject: [PATCH v2 2/2] pinctrl: mediatek: mt7981: add additional emmc groups
|
||||||
|
Date: Wed, 17 Jan 2024 15:55:47 +0100
|
||||||
|
Message-Id: <20240117145547.3354242-1-jean.thomas@wifirst.fr>
|
||||||
|
List-Id: <linux-mediatek.lists.infradead.org>
|
||||||
|
|
||||||
|
Add new emmc groups in the pinctrl driver for the
|
||||||
|
MediaTek MT7981 SoC:
|
||||||
|
* emmc reset, with pin 15.
|
||||||
|
* emmc 4-bit bus-width, with pins 16 to 19, and 24 to 25.
|
||||||
|
* emmc 8-bit bus-width, with pins 16 to 25.
|
||||||
|
|
||||||
|
The existing emmc_45 group is kept for legacy reasons, even
|
||||||
|
if this is the union of emmc_reset and emmc_8 groups.
|
||||||
|
|
||||||
|
Signed-off-by: Jean Thomas <jean.thomas@wifirst.fr>
|
||||||
|
Reviewed-by: Daniel Golle <daniel@makrotopia.org>
|
||||||
|
---
|
||||||
|
drivers/pinctrl/mediatek/pinctrl-mt7981.c | 17 ++++++++++++++++-
|
||||||
|
1 file changed, 16 insertions(+), 1 deletion(-)
|
||||||
|
|
||||||
|
--
|
||||||
|
2.39.2
|
||||||
|
|
||||||
|
--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
|
||||||
|
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
|
||||||
|
@@ -700,6 +700,15 @@ static int mt7981_drv_vbus_pins[] = { 14
|
||||||
|
static int mt7981_drv_vbus_funcs[] = { 1, };
|
||||||
|
|
||||||
|
/* EMMC */
|
||||||
|
+static int mt7981_emmc_reset_pins[] = { 15, };
|
||||||
|
+static int mt7981_emmc_reset_funcs[] = { 2, };
|
||||||
|
+
|
||||||
|
+static int mt7981_emmc_4_pins[] = { 16, 17, 18, 19, 24, 25, };
|
||||||
|
+static int mt7981_emmc_4_funcs[] = { 2, 2, 2, 2, 2, 2, };
|
||||||
|
+
|
||||||
|
+static int mt7981_emmc_8_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
|
||||||
|
+static int mt7981_emmc_8_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
|
||||||
|
+
|
||||||
|
static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
|
||||||
|
static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
|
||||||
|
|
||||||
|
@@ -854,6 +863,12 @@ static const struct group_desc mt7981_gr
|
||||||
|
PINCTRL_PIN_GROUP("udi", mt7981_udi),
|
||||||
|
/* @GPIO(14) DRV_VBUS(1) */
|
||||||
|
PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus),
|
||||||
|
+ /* @GPIO(15): EMMC_RSTB(2) */
|
||||||
|
+ PINCTRL_PIN_GROUP("emmc_reset", mt7981_emmc_reset),
|
||||||
|
+ /* @GPIO(16,17,18,19,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */
|
||||||
|
+ PINCTRL_PIN_GROUP("emmc_4", mt7981_emmc_4),
|
||||||
|
+ /* @GPIO(16,17,18,19,20,21,22,23,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */
|
||||||
|
+ PINCTRL_PIN_GROUP("emmc_8", mt7981_emmc_8),
|
||||||
|
/* @GPIO(15,25): EMMC(2) */
|
||||||
|
PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45),
|
||||||
|
/* @GPIO(16,21): SNFI(3) */
|
||||||
|
@@ -957,7 +972,7 @@ static const char *mt7981_i2c_groups[] =
|
||||||
|
static const char *mt7981_pcm_groups[] = { "pcm", };
|
||||||
|
static const char *mt7981_udi_groups[] = { "udi", };
|
||||||
|
static const char *mt7981_usb_groups[] = { "drv_vbus", };
|
||||||
|
-static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", };
|
||||||
|
+static const char *mt7981_flash_groups[] = { "emmc_reset", "emmc_4", "emmc_8", "emmc_45", "snfi", };
|
||||||
|
static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio",
|
||||||
|
"wf0_mode1", "wf0_mode3", "mt7531_int", };
|
||||||
|
static const char *mt7981_ant_groups[] = { "ant_sel", };
|
|
@ -0,0 +1,34 @@
|
||||||
|
--- a/drivers/mtd/nand/spi/core.c
|
||||||
|
+++ b/drivers/mtd/nand/spi/core.c
|
||||||
|
@@ -19,6 +19,7 @@
|
||||||
|
#include <linux/string.h>
|
||||||
|
#include <linux/spi/spi.h>
|
||||||
|
#include <linux/spi/spi-mem.h>
|
||||||
|
+#include <linux/mtd/mtk_bmt.h>
|
||||||
|
|
||||||
|
static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val)
|
||||||
|
{
|
||||||
|
@@ -1345,6 +1346,7 @@ static int spinand_probe(struct spi_mem
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
+ mtk_bmt_attach(mtd);
|
||||||
|
ret = mtd_device_register(mtd, NULL, 0);
|
||||||
|
if (ret)
|
||||||
|
goto err_spinand_cleanup;
|
||||||
|
@@ -1352,6 +1354,7 @@ static int spinand_probe(struct spi_mem
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
err_spinand_cleanup:
|
||||||
|
+ mtk_bmt_detach(mtd);
|
||||||
|
spinand_cleanup(spinand);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
@@ -1370,6 +1373,7 @@ static int spinand_remove(struct spi_mem
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
+ mtk_bmt_detach(mtd);
|
||||||
|
spinand_cleanup(spinand);
|
||||||
|
|
||||||
|
return 0;
|
|
@ -0,0 +1,10 @@
|
||||||
|
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
|
||||||
|
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
|
||||||
|
@@ -548,6 +548,7 @@
|
||||||
|
spi-tx-bus-width = <4>;
|
||||||
|
spi-rx-bus-width = <4>;
|
||||||
|
nand-ecc-engine = <&snfi>;
|
||||||
|
+ mediatek,bmt-v2;
|
||||||
|
|
||||||
|
partitions {
|
||||||
|
compatible = "fixed-partitions";
|
|
@ -0,0 +1,123 @@
|
||||||
|
From 5f49a5c9b16330e0df8f639310e4715dcad71947 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Davide Fioravanti <pantanastyle@gmail.com>
|
||||||
|
Date: Fri, 8 Jan 2021 15:35:24 +0100
|
||||||
|
Subject: [PATCH] mtd: spinand: Add support for the Fidelix FM35X1GA
|
||||||
|
|
||||||
|
Datasheet: http://www.hobos.com.cn/upload/datasheet/DS35X1GAXXX_100_rev00.pdf
|
||||||
|
|
||||||
|
Signed-off-by: Davide Fioravanti <pantanastyle@gmail.com>
|
||||||
|
---
|
||||||
|
drivers/mtd/nand/spi/Makefile | 2 +-
|
||||||
|
drivers/mtd/nand/spi/core.c | 1 +
|
||||||
|
drivers/mtd/nand/spi/fidelix.c | 76 ++++++++++++++++++++++++++++++++++
|
||||||
|
include/linux/mtd/spinand.h | 1 +
|
||||||
|
4 files changed, 79 insertions(+), 1 deletion(-)
|
||||||
|
create mode 100644 drivers/mtd/nand/spi/fidelix.c
|
||||||
|
|
||||||
|
--- a/drivers/mtd/nand/spi/Makefile
|
||||||
|
+++ b/drivers/mtd/nand/spi/Makefile
|
||||||
|
@@ -1,4 +1,4 @@
|
||||||
|
# SPDX-License-Identifier: GPL-2.0
|
||||||
|
-spinand-objs := core.o alliancememory.o ato.o esmt.o etron.o gigadevice.o
|
||||||
|
+spinand-objs := core.o alliancememory.o ato.o esmt.o etron.o fidelix.o gigadevice.o
|
||||||
|
spinand-objs += macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o
|
||||||
|
obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
|
||||||
|
--- a/drivers/mtd/nand/spi/core.c
|
||||||
|
+++ b/drivers/mtd/nand/spi/core.c
|
||||||
|
@@ -941,6 +941,7 @@ static const struct spinand_manufacturer
|
||||||
|
&alliancememory_spinand_manufacturer,
|
||||||
|
&ato_spinand_manufacturer,
|
||||||
|
&esmt_c8_spinand_manufacturer,
|
||||||
|
+ &fidelix_spinand_manufacturer,
|
||||||
|
&etron_spinand_manufacturer,
|
||||||
|
&gigadevice_spinand_manufacturer,
|
||||||
|
¯onix_spinand_manufacturer,
|
||||||
|
--- /dev/null
|
||||||
|
+++ b/drivers/mtd/nand/spi/fidelix.c
|
||||||
|
@@ -0,0 +1,76 @@
|
||||||
|
+// SPDX-License-Identifier: GPL-2.0
|
||||||
|
+/*
|
||||||
|
+ * Copyright (c) 2020 Davide Fioravanti <pantanastyle@gmail.com>
|
||||||
|
+ */
|
||||||
|
+
|
||||||
|
+#include <linux/device.h>
|
||||||
|
+#include <linux/kernel.h>
|
||||||
|
+#include <linux/mtd/spinand.h>
|
||||||
|
+
|
||||||
|
+#define SPINAND_MFR_FIDELIX 0xE5
|
||||||
|
+#define FIDELIX_ECCSR_MASK 0x0F
|
||||||
|
+
|
||||||
|
+static SPINAND_OP_VARIANTS(read_cache_variants,
|
||||||
|
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
|
||||||
|
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
|
||||||
|
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
|
||||||
|
+
|
||||||
|
+static SPINAND_OP_VARIANTS(write_cache_variants,
|
||||||
|
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
|
||||||
|
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
|
||||||
|
+
|
||||||
|
+static SPINAND_OP_VARIANTS(update_cache_variants,
|
||||||
|
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
|
||||||
|
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
|
||||||
|
+
|
||||||
|
+static int fm35x1ga_ooblayout_ecc(struct mtd_info *mtd, int section,
|
||||||
|
+ struct mtd_oob_region *region)
|
||||||
|
+{
|
||||||
|
+ if (section > 3)
|
||||||
|
+ return -ERANGE;
|
||||||
|
+
|
||||||
|
+ region->offset = (16 * section) + 8;
|
||||||
|
+ region->length = 8;
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int fm35x1ga_ooblayout_free(struct mtd_info *mtd, int section,
|
||||||
|
+ struct mtd_oob_region *region)
|
||||||
|
+{
|
||||||
|
+ if (section > 3)
|
||||||
|
+ return -ERANGE;
|
||||||
|
+
|
||||||
|
+ region->offset = (16 * section) + 2;
|
||||||
|
+ region->length = 6;
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static const struct mtd_ooblayout_ops fm35x1ga_ooblayout = {
|
||||||
|
+ .ecc = fm35x1ga_ooblayout_ecc,
|
||||||
|
+ .free = fm35x1ga_ooblayout_free,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static const struct spinand_info fidelix_spinand_table[] = {
|
||||||
|
+ SPINAND_INFO("FM35X1GA",
|
||||||
|
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71),
|
||||||
|
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
|
||||||
|
+ NAND_ECCREQ(4, 512),
|
||||||
|
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
|
||||||
|
+ &write_cache_variants,
|
||||||
|
+ &update_cache_variants),
|
||||||
|
+ SPINAND_HAS_QE_BIT,
|
||||||
|
+ SPINAND_ECCINFO(&fm35x1ga_ooblayout, NULL)),
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+static const struct spinand_manufacturer_ops fidelix_spinand_manuf_ops = {
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+const struct spinand_manufacturer fidelix_spinand_manufacturer = {
|
||||||
|
+ .id = SPINAND_MFR_FIDELIX,
|
||||||
|
+ .name = "Fidelix",
|
||||||
|
+ .chips = fidelix_spinand_table,
|
||||||
|
+ .nchips = ARRAY_SIZE(fidelix_spinand_table),
|
||||||
|
+ .ops = &fidelix_spinand_manuf_ops,
|
||||||
|
+};
|
||||||
|
--- a/include/linux/mtd/spinand.h
|
||||||
|
+++ b/include/linux/mtd/spinand.h
|
||||||
|
@@ -264,6 +264,7 @@ extern const struct spinand_manufacturer
|
||||||
|
extern const struct spinand_manufacturer ato_spinand_manufacturer;
|
||||||
|
extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer;
|
||||||
|
extern const struct spinand_manufacturer etron_spinand_manufacturer;
|
||||||
|
+extern const struct spinand_manufacturer fidelix_spinand_manufacturer;
|
||||||
|
extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
|
||||||
|
extern const struct spinand_manufacturer macronix_spinand_manufacturer;
|
||||||
|
extern const struct spinand_manufacturer micron_spinand_manufacturer;
|
|
@ -0,0 +1,61 @@
|
||||||
|
From patchwork Fri Apr 19 16:59:07 2024
|
||||||
|
Content-Type: text/plain; charset="utf-8"
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Transfer-Encoding: 7bit
|
||||||
|
X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
|
||||||
|
X-Patchwork-Id: 13636668
|
||||||
|
Return-Path:
|
||||||
|
<linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org>
|
||||||
|
Date: Fri, 19 Apr 2024 17:59:07 +0100
|
||||||
|
From: Daniel Golle <daniel@makrotopia.org>
|
||||||
|
To: "Rafael J. Wysocki" <rafael@kernel.org>,
|
||||||
|
Viresh Kumar <viresh.kumar@linaro.org>,
|
||||||
|
Matthias Brugger <matthias.bgg@gmail.com>,
|
||||||
|
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
|
||||||
|
linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org,
|
||||||
|
linux-arm-kernel@lists.infradead.org,
|
||||||
|
linux-mediatek@lists.infradead.org
|
||||||
|
Subject: [PATCH] cpufreq: mediatek: Add support for MT7988A
|
||||||
|
Message-ID:
|
||||||
|
<acf4fb446aacfbf6ce7b6e94bf3aad303e0ad4d1.1713545923.git.daniel@makrotopia.org>
|
||||||
|
Content-Disposition: inline
|
||||||
|
List-Id: <linux-mediatek.lists.infradead.org>
|
||||||
|
|
||||||
|
From: Sam Shih <sam.shih@mediatek.com>
|
||||||
|
|
||||||
|
This add cpufreq support for mediatek MT7988A SoC.
|
||||||
|
|
||||||
|
The platform data of MT7988A is different from previous MediaTek SoCs,
|
||||||
|
so we add a new compatible and platform data for it.
|
||||||
|
|
||||||
|
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
|
||||||
|
---
|
||||||
|
drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++++++
|
||||||
|
1 file changed, 10 insertions(+)
|
||||||
|
|
||||||
|
--- a/drivers/cpufreq/mediatek-cpufreq.c
|
||||||
|
+++ b/drivers/cpufreq/mediatek-cpufreq.c
|
||||||
|
@@ -707,6 +707,15 @@ static const struct mtk_cpufreq_platform
|
||||||
|
.ccifreq_supported = false,
|
||||||
|
};
|
||||||
|
|
||||||
|
+static const struct mtk_cpufreq_platform_data mt7988_platform_data = {
|
||||||
|
+ .min_volt_shift = 100000,
|
||||||
|
+ .max_volt_shift = 200000,
|
||||||
|
+ .proc_max_volt = 900000,
|
||||||
|
+ .sram_min_volt = 0,
|
||||||
|
+ .sram_max_volt = 1150000,
|
||||||
|
+ .ccifreq_supported = true,
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
static const struct mtk_cpufreq_platform_data mt8183_platform_data = {
|
||||||
|
.min_volt_shift = 100000,
|
||||||
|
.max_volt_shift = 200000,
|
||||||
|
@@ -740,6 +749,7 @@ static const struct of_device_id mtk_cpu
|
||||||
|
{ .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
|
||||||
|
{ .compatible = "mediatek,mt7622", .data = &mt7622_platform_data },
|
||||||
|
{ .compatible = "mediatek,mt7623", .data = &mt7623_platform_data },
|
||||||
|
+ { .compatible = "mediatek,mt7988a", .data = &mt7988_platform_data },
|
||||||
|
{ .compatible = "mediatek,mt8167", .data = &mt8516_platform_data },
|
||||||
|
{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
|
||||||
|
{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
|
|
@ -0,0 +1,99 @@
|
||||||
|
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
|
||||||
|
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
|
||||||
|
@@ -601,6 +601,30 @@ out:
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
|
+static int mtk_pinconf_bias_set_pd(struct mtk_pinctrl *hw,
|
||||||
|
+ const struct mtk_pin_desc *desc,
|
||||||
|
+ u32 pullup, u32 arg)
|
||||||
|
+{
|
||||||
|
+ int err, pd;
|
||||||
|
+
|
||||||
|
+ if (arg == MTK_DISABLE)
|
||||||
|
+ pd = 0;
|
||||||
|
+ else if ((arg == MTK_ENABLE) && pullup)
|
||||||
|
+ pd = 0;
|
||||||
|
+ else if ((arg == MTK_ENABLE) && !pullup)
|
||||||
|
+ pd = 1;
|
||||||
|
+ else {
|
||||||
|
+ err = -EINVAL;
|
||||||
|
+ goto out;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd);
|
||||||
|
+
|
||||||
|
+out:
|
||||||
|
+ return err;
|
||||||
|
+
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw,
|
||||||
|
const struct mtk_pin_desc *desc,
|
||||||
|
u32 pullup, u32 arg)
|
||||||
|
@@ -755,6 +779,12 @@ int mtk_pinconf_bias_set_combo(struct mt
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
|
+ if (try_all_type & MTK_PULL_PD_TYPE) {
|
||||||
|
+ err = mtk_pinconf_bias_set_pd(hw, desc, pullup, arg);
|
||||||
|
+ if (!err)
|
||||||
|
+ return err;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
if (try_all_type & MTK_PULL_PU_PD_TYPE) {
|
||||||
|
err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg);
|
||||||
|
if (!err)
|
||||||
|
@@ -875,6 +905,29 @@ out:
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
|
+static int mtk_pinconf_bias_get_pd(struct mtk_pinctrl *hw,
|
||||||
|
+ const struct mtk_pin_desc *desc,
|
||||||
|
+ u32 *pullup, u32 *enable)
|
||||||
|
+{
|
||||||
|
+ int err, pd;
|
||||||
|
+
|
||||||
|
+ err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd);
|
||||||
|
+ if (err)
|
||||||
|
+ goto out;
|
||||||
|
+
|
||||||
|
+ if (pd == 0) {
|
||||||
|
+ *pullup = 0;
|
||||||
|
+ *enable = MTK_DISABLE;
|
||||||
|
+ } else if (pd == 1) {
|
||||||
|
+ *pullup = 0;
|
||||||
|
+ *enable = MTK_ENABLE;
|
||||||
|
+ } else
|
||||||
|
+ err = -EINVAL;
|
||||||
|
+
|
||||||
|
+out:
|
||||||
|
+ return err;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw,
|
||||||
|
const struct mtk_pin_desc *desc,
|
||||||
|
u32 *pullup, u32 *enable)
|
||||||
|
@@ -943,6 +996,12 @@ int mtk_pinconf_bias_get_combo(struct mt
|
||||||
|
if (!err)
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
+
|
||||||
|
+ if (try_all_type & MTK_PULL_PD_TYPE) {
|
||||||
|
+ err = mtk_pinconf_bias_get_pd(hw, desc, pullup, enable);
|
||||||
|
+ if (!err)
|
||||||
|
+ return err;
|
||||||
|
+ }
|
||||||
|
|
||||||
|
if (try_all_type & MTK_PULL_PU_PD_TYPE) {
|
||||||
|
err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable);
|
||||||
|
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
|
||||||
|
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
|
||||||
|
@@ -24,6 +24,7 @@
|
||||||
|
* turned on/off itself. But it can't be selected pull up/down
|
||||||
|
*/
|
||||||
|
#define MTK_PULL_RSEL_TYPE BIT(3)
|
||||||
|
+#define MTK_PULL_PD_TYPE BIT(4)
|
||||||
|
/* MTK_PULL_PU_PD_RSEL_TYPE is a type which is controlled by
|
||||||
|
* MTK_PULL_PU_PD_TYPE and MTK_PULL_RSEL_TYPE.
|
||||||
|
*/
|
|
@ -0,0 +1,27 @@
|
||||||
|
--- a/drivers/crypto/inside-secure/safexcel.c
|
||||||
|
+++ b/drivers/crypto/inside-secure/safexcel.c
|
||||||
|
@@ -608,6 +608,14 @@ static int safexcel_hw_init(struct safex
|
||||||
|
val |= EIP197_MST_CTRL_TX_MAX_CMD(5);
|
||||||
|
writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
|
||||||
|
}
|
||||||
|
+ /*
|
||||||
|
+ * Set maximum number of TX commands to 2^4 = 16 for EIP97 HW2.1/HW2.3
|
||||||
|
+ */
|
||||||
|
+ else {
|
||||||
|
+ val = 0;
|
||||||
|
+ val |= EIP97_MST_CTRL_TX_MAX_CMD(4);
|
||||||
|
+ writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
|
||||||
|
+ }
|
||||||
|
|
||||||
|
/* Configure wr/rd cache values */
|
||||||
|
writel(EIP197_MST_CTRL_RD_CACHE(RD_CACHE_4BITS) |
|
||||||
|
--- a/drivers/crypto/inside-secure/safexcel.h
|
||||||
|
+++ b/drivers/crypto/inside-secure/safexcel.h
|
||||||
|
@@ -315,6 +315,7 @@
|
||||||
|
#define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0)
|
||||||
|
#define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4)
|
||||||
|
#define EIP197_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 20)
|
||||||
|
+#define EIP97_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 4)
|
||||||
|
#define EIP197_MST_CTRL_BYTE_SWAP BIT(24)
|
||||||
|
#define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25)
|
||||||
|
#define EIP197_MST_CTRL_BYTE_SWAP_BITS GENMASK(25, 24)
|
|
@ -0,0 +1,26 @@
|
||||||
|
--- a/drivers/crypto/inside-secure/safexcel.h
|
||||||
|
+++ b/drivers/crypto/inside-secure/safexcel.h
|
||||||
|
@@ -743,6 +743,9 @@ struct safexcel_priv_data {
|
||||||
|
/* Priority we use for advertising our algorithms */
|
||||||
|
#define SAFEXCEL_CRA_PRIORITY 300
|
||||||
|
|
||||||
|
+/* System cache line size */
|
||||||
|
+#define SYSTEM_CACHELINE_SIZE 64
|
||||||
|
+
|
||||||
|
/* SM3 digest result for zero length message */
|
||||||
|
#define EIP197_SM3_ZEROM_HASH "\x1A\xB2\x1D\x83\x55\xCF\xA1\x7F" \
|
||||||
|
"\x8E\x61\x19\x48\x31\xE8\x1A\x8F" \
|
||||||
|
--- a/drivers/crypto/inside-secure/safexcel_hash.c
|
||||||
|
+++ b/drivers/crypto/inside-secure/safexcel_hash.c
|
||||||
|
@@ -55,9 +55,9 @@ struct safexcel_ahash_req {
|
||||||
|
u8 block_sz; /* block size, only set once */
|
||||||
|
u8 digest_sz; /* output digest size, only set once */
|
||||||
|
__le32 state[SHA3_512_BLOCK_SIZE /
|
||||||
|
- sizeof(__le32)] __aligned(sizeof(__le32));
|
||||||
|
+ sizeof(__le32)] __aligned(SYSTEM_CACHELINE_SIZE);
|
||||||
|
|
||||||
|
- u64 len;
|
||||||
|
+ u64 len __aligned(SYSTEM_CACHELINE_SIZE);
|
||||||
|
u64 processed;
|
||||||
|
|
||||||
|
u8 cache[HASH_CACHE_SIZE] __aligned(sizeof(u32));
|
|
@ -0,0 +1,33 @@
|
||||||
|
--- a/drivers/tty/serial/8250/8250.h
|
||||||
|
+++ b/drivers/tty/serial/8250/8250.h
|
||||||
|
@@ -86,6 +86,7 @@ struct serial8250_config {
|
||||||
|
* STOP PARITY EPAR SPAR WLEN5 WLEN6
|
||||||
|
*/
|
||||||
|
#define UART_CAP_NOTEMT BIT(18) /* UART without interrupt on TEMT available */
|
||||||
|
+#define UART_CAP_NMOD BIT(19) /* UART doesn't do termios */
|
||||||
|
|
||||||
|
#define UART_BUG_QUOT BIT(0) /* UART has buggy quot LSB */
|
||||||
|
#define UART_BUG_TXEN BIT(1) /* UART has buggy TX IIR status */
|
||||||
|
--- a/drivers/tty/serial/8250/8250_port.c
|
||||||
|
+++ b/drivers/tty/serial/8250/8250_port.c
|
||||||
|
@@ -287,7 +287,7 @@ static const struct serial8250_config ua
|
||||||
|
.tx_loadsz = 16,
|
||||||
|
.fcr = UART_FCR_ENABLE_FIFO |
|
||||||
|
UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
|
||||||
|
- .flags = UART_CAP_FIFO,
|
||||||
|
+ .flags = UART_CAP_FIFO | UART_CAP_NMOD,
|
||||||
|
},
|
||||||
|
[PORT_NPCM] = {
|
||||||
|
.name = "Nuvoton 16550",
|
||||||
|
@@ -2774,6 +2774,11 @@ serial8250_do_set_termios(struct uart_po
|
||||||
|
unsigned long flags;
|
||||||
|
unsigned int baud, quot, frac = 0;
|
||||||
|
|
||||||
|
+ if (up->capabilities & UART_CAP_NMOD) {
|
||||||
|
+ termios->c_cflag = 0;
|
||||||
|
+ return;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
if (up->capabilities & UART_CAP_MINI) {
|
||||||
|
termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
|
||||||
|
if ((termios->c_cflag & CSIZE) == CS5 ||
|
|
@ -0,0 +1,130 @@
|
||||||
|
From bfd3acc428085742d754a6d328d1a93ebf9451df Mon Sep 17 00:00:00 2001
|
||||||
|
From: "SkyLake.Huang" <skylake.huang@mediatek.com>
|
||||||
|
Date: Thu, 23 Jun 2022 18:29:51 +0800
|
||||||
|
Subject: [PATCH 1/6] drivers: spi-mt65xx: Move chip_config to driver's private
|
||||||
|
data
|
||||||
|
|
||||||
|
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
|
||||||
|
---
|
||||||
|
drivers/spi/spi-mt65xx.c | 29 +++++++++---------------
|
||||||
|
include/linux/platform_data/spi-mt65xx.h | 17 --------------
|
||||||
|
2 files changed, 11 insertions(+), 35 deletions(-)
|
||||||
|
delete mode 100644 include/linux/platform_data/spi-mt65xx.h
|
||||||
|
|
||||||
|
--- a/drivers/spi/spi-mt65xx.c
|
||||||
|
+++ b/drivers/spi/spi-mt65xx.c
|
||||||
|
@@ -14,7 +14,6 @@
|
||||||
|
#include <linux/of.h>
|
||||||
|
#include <linux/gpio/consumer.h>
|
||||||
|
#include <linux/platform_device.h>
|
||||||
|
-#include <linux/platform_data/spi-mt65xx.h>
|
||||||
|
#include <linux/pm_runtime.h>
|
||||||
|
#include <linux/spi/spi.h>
|
||||||
|
#include <linux/spi/spi-mem.h>
|
||||||
|
@@ -171,6 +170,8 @@ struct mtk_spi {
|
||||||
|
struct device *dev;
|
||||||
|
dma_addr_t tx_dma;
|
||||||
|
dma_addr_t rx_dma;
|
||||||
|
+ u32 sample_sel;
|
||||||
|
+ u32 get_tick_dly;
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct mtk_spi_compatible mtk_common_compat;
|
||||||
|
@@ -216,15 +217,6 @@ static const struct mtk_spi_compatible m
|
||||||
|
.no_need_unprepare = true,
|
||||||
|
};
|
||||||
|
|
||||||
|
-/*
|
||||||
|
- * A piece of default chip info unless the platform
|
||||||
|
- * supplies it.
|
||||||
|
- */
|
||||||
|
-static const struct mtk_chip_config mtk_default_chip_info = {
|
||||||
|
- .sample_sel = 0,
|
||||||
|
- .tick_delay = 0,
|
||||||
|
-};
|
||||||
|
-
|
||||||
|
static const struct of_device_id mtk_spi_of_match[] = {
|
||||||
|
{ .compatible = "mediatek,spi-ipm",
|
||||||
|
.data = (void *)&mtk_ipm_compat,
|
||||||
|
@@ -352,7 +344,6 @@ static int mtk_spi_hw_init(struct spi_ma
|
||||||
|
{
|
||||||
|
u16 cpha, cpol;
|
||||||
|
u32 reg_val;
|
||||||
|
- struct mtk_chip_config *chip_config = spi->controller_data;
|
||||||
|
struct mtk_spi *mdata = spi_master_get_devdata(master);
|
||||||
|
|
||||||
|
cpha = spi->mode & SPI_CPHA ? 1 : 0;
|
||||||
|
@@ -402,7 +393,7 @@ static int mtk_spi_hw_init(struct spi_ma
|
||||||
|
else
|
||||||
|
reg_val &= ~SPI_CMD_CS_POL;
|
||||||
|
|
||||||
|
- if (chip_config->sample_sel)
|
||||||
|
+ if (mdata->sample_sel)
|
||||||
|
reg_val |= SPI_CMD_SAMPLE_SEL;
|
||||||
|
else
|
||||||
|
reg_val &= ~SPI_CMD_SAMPLE_SEL;
|
||||||
|
@@ -429,20 +420,20 @@ static int mtk_spi_hw_init(struct spi_ma
|
||||||
|
if (mdata->dev_comp->ipm_design) {
|
||||||
|
reg_val = readl(mdata->base + SPI_CMD_REG);
|
||||||
|
reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK;
|
||||||
|
- reg_val |= ((chip_config->tick_delay & 0x7)
|
||||||
|
+ reg_val |= ((mdata->get_tick_dly & 0x7)
|
||||||
|
<< SPI_CMD_IPM_GET_TICKDLY_OFFSET);
|
||||||
|
writel(reg_val, mdata->base + SPI_CMD_REG);
|
||||||
|
} else {
|
||||||
|
reg_val = readl(mdata->base + SPI_CFG1_REG);
|
||||||
|
reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
|
||||||
|
- reg_val |= ((chip_config->tick_delay & 0x7)
|
||||||
|
+ reg_val |= ((mdata->get_tick_dly & 0x7)
|
||||||
|
<< SPI_CFG1_GET_TICK_DLY_OFFSET);
|
||||||
|
writel(reg_val, mdata->base + SPI_CFG1_REG);
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
reg_val = readl(mdata->base + SPI_CFG1_REG);
|
||||||
|
reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1;
|
||||||
|
- reg_val |= ((chip_config->tick_delay & 0x3)
|
||||||
|
+ reg_val |= ((mdata->get_tick_dly & 0x3)
|
||||||
|
<< SPI_CFG1_GET_TICK_DLY_OFFSET_V1);
|
||||||
|
writel(reg_val, mdata->base + SPI_CFG1_REG);
|
||||||
|
}
|
||||||
|
@@ -732,9 +723,6 @@ static int mtk_spi_setup(struct spi_devi
|
||||||
|
{
|
||||||
|
struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
|
||||||
|
|
||||||
|
- if (!spi->controller_data)
|
||||||
|
- spi->controller_data = (void *)&mtk_default_chip_info;
|
||||||
|
-
|
||||||
|
if (mdata->dev_comp->need_pad_sel && spi_get_csgpiod(spi, 0))
|
||||||
|
/* CS de-asserted, gpiolib will handle inversion */
|
||||||
|
gpiod_direction_output(spi_get_csgpiod(spi, 0), 0);
|
||||||
|
@@ -1140,6 +1128,10 @@ static int mtk_spi_probe(struct platform
|
||||||
|
mdata = spi_master_get_devdata(master);
|
||||||
|
mdata->dev_comp = device_get_match_data(dev);
|
||||||
|
|
||||||
|
+ /* Set device configs to default first. Calibrate it later. */
|
||||||
|
+ mdata->sample_sel = 0;
|
||||||
|
+ mdata->get_tick_dly = 2;
|
||||||
|
+
|
||||||
|
if (mdata->dev_comp->enhance_timing)
|
||||||
|
master->mode_bits |= SPI_CS_HIGH;
|
||||||
|
|
||||||
|
--- a/include/linux/platform_data/spi-mt65xx.h
|
||||||
|
+++ /dev/null
|
||||||
|
@@ -1,17 +0,0 @@
|
||||||
|
-/* SPDX-License-Identifier: GPL-2.0-only */
|
||||||
|
-/*
|
||||||
|
- * MTK SPI bus driver definitions
|
||||||
|
- *
|
||||||
|
- * Copyright (c) 2015 MediaTek Inc.
|
||||||
|
- * Author: Leilk Liu <leilk.liu@mediatek.com>
|
||||||
|
- */
|
||||||
|
-
|
||||||
|
-#ifndef ____LINUX_PLATFORM_DATA_SPI_MTK_H
|
||||||
|
-#define ____LINUX_PLATFORM_DATA_SPI_MTK_H
|
||||||
|
-
|
||||||
|
-/* Board specific platform_data */
|
||||||
|
-struct mtk_chip_config {
|
||||||
|
- u32 sample_sel;
|
||||||
|
- u32 tick_delay;
|
||||||
|
-};
|
||||||
|
-#endif
|
|
@ -0,0 +1,236 @@
|
||||||
|
From 2ade0172154e50c8a2bfd8634c6eff943cffea29 Mon Sep 17 00:00:00 2001
|
||||||
|
From: "SkyLake.Huang" <skylake.huang@mediatek.com>
|
||||||
|
Date: Thu, 23 Jun 2022 18:35:52 +0800
|
||||||
|
Subject: [PATCH 2/6] drivers: spi: Add support for dynamic calibration
|
||||||
|
|
||||||
|
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
|
||||||
|
---
|
||||||
|
drivers/spi/spi.c | 137 ++++++++++++++++++++++++++++++++++++++++
|
||||||
|
include/linux/spi/spi.h | 42 ++++++++++++
|
||||||
|
2 files changed, 179 insertions(+)
|
||||||
|
|
||||||
|
--- a/drivers/spi/spi.c
|
||||||
|
+++ b/drivers/spi/spi.c
|
||||||
|
@@ -1370,6 +1370,70 @@ static int spi_transfer_wait(struct spi_
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
+int spi_do_calibration(struct spi_controller *ctlr, struct spi_device *spi,
|
||||||
|
+ int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen), void *drv_priv)
|
||||||
|
+{
|
||||||
|
+ int datalen = ctlr->cal_rule->datalen;
|
||||||
|
+ int addrlen = ctlr->cal_rule->addrlen;
|
||||||
|
+ u8 *buf;
|
||||||
|
+ int ret;
|
||||||
|
+ int i;
|
||||||
|
+ struct list_head *cal_head, *listptr;
|
||||||
|
+ struct spi_cal_target *target;
|
||||||
|
+
|
||||||
|
+ /* Calculate calibration result */
|
||||||
|
+ int hit_val, total_hit, origin;
|
||||||
|
+ bool hit;
|
||||||
|
+
|
||||||
|
+ /* Make sure we can start calibration */
|
||||||
|
+ if(!ctlr->cal_target || !ctlr->cal_rule || !ctlr->append_caldata)
|
||||||
|
+ return 0;
|
||||||
|
+
|
||||||
|
+ buf = kzalloc(datalen * sizeof(u8), GFP_KERNEL);
|
||||||
|
+ if(!buf)
|
||||||
|
+ return -ENOMEM;
|
||||||
|
+
|
||||||
|
+ ret = ctlr->append_caldata(ctlr);
|
||||||
|
+ if (ret)
|
||||||
|
+ goto cal_end;
|
||||||
|
+
|
||||||
|
+ cal_head = ctlr->cal_target;
|
||||||
|
+ list_for_each(listptr, cal_head) {
|
||||||
|
+ target = list_entry(listptr, struct spi_cal_target, list);
|
||||||
|
+
|
||||||
|
+ hit = false;
|
||||||
|
+ hit_val = 0;
|
||||||
|
+ total_hit = 0;
|
||||||
|
+ origin = *target->cal_item;
|
||||||
|
+
|
||||||
|
+ for(i=target->cal_min; i<=target->cal_max; i+=target->step) {
|
||||||
|
+ *target->cal_item = i;
|
||||||
|
+ ret = (*cal_read)(drv_priv, ctlr->cal_rule->addr, addrlen, buf, datalen);
|
||||||
|
+ if(ret)
|
||||||
|
+ break;
|
||||||
|
+ dev_dbg(&spi->dev, "controller cal item value: 0x%x\n", i);
|
||||||
|
+ if(memcmp(ctlr->cal_rule->match_data, buf, datalen * sizeof(u8)) == 0) {
|
||||||
|
+ hit = true;
|
||||||
|
+ hit_val += i;
|
||||||
|
+ total_hit++;
|
||||||
|
+ dev_dbg(&spi->dev, "golden data matches data read!\n");
|
||||||
|
+ }
|
||||||
|
+ }
|
||||||
|
+ if(hit) {
|
||||||
|
+ *target->cal_item = DIV_ROUND_CLOSEST(hit_val, total_hit);
|
||||||
|
+ dev_info(&spi->dev, "calibration result: 0x%x", *target->cal_item);
|
||||||
|
+ } else {
|
||||||
|
+ *target->cal_item = origin;
|
||||||
|
+ dev_warn(&spi->dev, "calibration failed, fallback to default: 0x%x", origin);
|
||||||
|
+ }
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+cal_end:
|
||||||
|
+ kfree(buf);
|
||||||
|
+ return ret? ret: 0;
|
||||||
|
+}
|
||||||
|
+EXPORT_SYMBOL_GPL(spi_do_calibration);
|
||||||
|
+
|
||||||
|
static void _spi_transfer_delay_ns(u32 ns)
|
||||||
|
{
|
||||||
|
if (!ns)
|
||||||
|
@@ -2215,6 +2279,75 @@ void spi_flush_queue(struct spi_controll
|
||||||
|
/*-------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
#if defined(CONFIG_OF)
|
||||||
|
+static inline void alloc_cal_data(struct list_head **cal_target,
|
||||||
|
+ struct spi_cal_rule **cal_rule, bool enable)
|
||||||
|
+{
|
||||||
|
+ if(enable) {
|
||||||
|
+ *cal_target = kmalloc(sizeof(struct list_head), GFP_KERNEL);
|
||||||
|
+ INIT_LIST_HEAD(*cal_target);
|
||||||
|
+ *cal_rule = kmalloc(sizeof(struct spi_cal_rule), GFP_KERNEL);
|
||||||
|
+ } else {
|
||||||
|
+ kfree(*cal_target);
|
||||||
|
+ kfree(*cal_rule);
|
||||||
|
+ }
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int of_spi_parse_cal_dt(struct spi_controller *ctlr, struct spi_device *spi,
|
||||||
|
+ struct device_node *nc)
|
||||||
|
+{
|
||||||
|
+ u32 value;
|
||||||
|
+ int rc;
|
||||||
|
+ const char *cal_mode;
|
||||||
|
+
|
||||||
|
+ rc = of_property_read_bool(nc, "spi-cal-enable");
|
||||||
|
+ if (rc)
|
||||||
|
+ alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, true);
|
||||||
|
+ else
|
||||||
|
+ return 0;
|
||||||
|
+
|
||||||
|
+ rc = of_property_read_string(nc, "spi-cal-mode", &cal_mode);
|
||||||
|
+ if(!rc) {
|
||||||
|
+ if(strcmp("read-data", cal_mode) == 0){
|
||||||
|
+ ctlr->cal_rule->mode = SPI_CAL_READ_DATA;
|
||||||
|
+ } else if(strcmp("read-pp", cal_mode) == 0) {
|
||||||
|
+ ctlr->cal_rule->mode = SPI_CAL_READ_PP;
|
||||||
|
+ return 0;
|
||||||
|
+ } else if(strcmp("read-sfdp", cal_mode) == 0){
|
||||||
|
+ ctlr->cal_rule->mode = SPI_CAL_READ_SFDP;
|
||||||
|
+ return 0;
|
||||||
|
+ }
|
||||||
|
+ } else
|
||||||
|
+ goto err;
|
||||||
|
+
|
||||||
|
+ ctlr->cal_rule->datalen = 0;
|
||||||
|
+ rc = of_property_read_u32(nc, "spi-cal-datalen", &value);
|
||||||
|
+ if(!rc && value > 0) {
|
||||||
|
+ ctlr->cal_rule->datalen = value;
|
||||||
|
+
|
||||||
|
+ ctlr->cal_rule->match_data = kzalloc(value * sizeof(u8), GFP_KERNEL);
|
||||||
|
+ rc = of_property_read_u8_array(nc, "spi-cal-data",
|
||||||
|
+ ctlr->cal_rule->match_data, value);
|
||||||
|
+ if(rc)
|
||||||
|
+ kfree(ctlr->cal_rule->match_data);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ rc = of_property_read_u32(nc, "spi-cal-addrlen", &value);
|
||||||
|
+ if(!rc && value > 0) {
|
||||||
|
+ ctlr->cal_rule->addrlen = value;
|
||||||
|
+
|
||||||
|
+ ctlr->cal_rule->addr = kzalloc(value * sizeof(u32), GFP_KERNEL);
|
||||||
|
+ rc = of_property_read_u32_array(nc, "spi-cal-addr",
|
||||||
|
+ ctlr->cal_rule->addr, value);
|
||||||
|
+ if(rc)
|
||||||
|
+ kfree(ctlr->cal_rule->addr);
|
||||||
|
+ }
|
||||||
|
+ return 0;
|
||||||
|
+
|
||||||
|
+err:
|
||||||
|
+ alloc_cal_data(&ctlr->cal_target, &ctlr->cal_rule, false);
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
static void of_spi_parse_dt_cs_delay(struct device_node *nc,
|
||||||
|
struct spi_delay *delay, const char *prop)
|
||||||
|
{
|
||||||
|
@@ -2354,6 +2487,10 @@ of_register_spi_device(struct spi_contro
|
||||||
|
if (rc)
|
||||||
|
goto err_out;
|
||||||
|
|
||||||
|
+ rc = of_spi_parse_cal_dt(ctlr, spi, nc);
|
||||||
|
+ if (rc)
|
||||||
|
+ goto err_out;
|
||||||
|
+
|
||||||
|
/* Store a pointer to the node in the device structure */
|
||||||
|
of_node_get(nc);
|
||||||
|
|
||||||
|
--- a/include/linux/spi/spi.h
|
||||||
|
+++ b/include/linux/spi/spi.h
|
||||||
|
@@ -330,6 +330,40 @@ struct spi_driver {
|
||||||
|
struct device_driver driver;
|
||||||
|
};
|
||||||
|
|
||||||
|
+enum {
|
||||||
|
+ SPI_CAL_READ_DATA = 0,
|
||||||
|
+ SPI_CAL_READ_PP = 1, /* only for SPI-NAND */
|
||||||
|
+ SPI_CAL_READ_SFDP = 2, /* only for SPI-NOR */
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+struct nand_addr {
|
||||||
|
+ unsigned int lun;
|
||||||
|
+ unsigned int plane;
|
||||||
|
+ unsigned int eraseblock;
|
||||||
|
+ unsigned int page;
|
||||||
|
+ unsigned int dataoffs;
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+/**
|
||||||
|
+ * Read calibration rule from device dts node.
|
||||||
|
+ * Once calibration result matches the rule, we regard is as success.
|
||||||
|
+ */
|
||||||
|
+struct spi_cal_rule {
|
||||||
|
+ int datalen;
|
||||||
|
+ u8 *match_data;
|
||||||
|
+ int addrlen;
|
||||||
|
+ u32 *addr;
|
||||||
|
+ int mode;
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
+struct spi_cal_target {
|
||||||
|
+ u32 *cal_item;
|
||||||
|
+ int cal_min; /* min of cal_item */
|
||||||
|
+ int cal_max; /* max of cal_item */
|
||||||
|
+ int step; /* Increase/decrease cal_item */
|
||||||
|
+ struct list_head list;
|
||||||
|
+};
|
||||||
|
+
|
||||||
|
static inline struct spi_driver *to_spi_driver(struct device_driver *drv)
|
||||||
|
{
|
||||||
|
return drv ? container_of(drv, struct spi_driver, driver) : NULL;
|
||||||
|
@@ -727,6 +761,11 @@ struct spi_controller {
|
||||||
|
void *dummy_rx;
|
||||||
|
void *dummy_tx;
|
||||||
|
|
||||||
|
+ /* For calibration */
|
||||||
|
+ int (*append_caldata)(struct spi_controller *ctlr);
|
||||||
|
+ struct list_head *cal_target;
|
||||||
|
+ struct spi_cal_rule *cal_rule;
|
||||||
|
+
|
||||||
|
int (*fw_translate_cs)(struct spi_controller *ctlr, unsigned cs);
|
||||||
|
|
||||||
|
/*
|
||||||
|
@@ -1600,6 +1639,9 @@ spi_register_board_info(struct spi_board
|
||||||
|
{ return 0; }
|
||||||
|
#endif
|
||||||
|
|
||||||
|
+extern int spi_do_calibration(struct spi_controller *ctlr,
|
||||||
|
+ struct spi_device *spi, int (*cal_read)(void *, u32 *, int, u8 *, int), void *drv_priv);
|
||||||
|
+
|
||||||
|
/*
|
||||||
|
* If you're hotplugging an adapter with devices (parport, USB, etc)
|
||||||
|
* use spi_new_device() to describe each device. You can also call
|
|
@ -0,0 +1,41 @@
|
||||||
|
From 06640a5da2973318c06e516da16a5b579622e7c5 Mon Sep 17 00:00:00 2001
|
||||||
|
From: "SkyLake.Huang" <skylake.huang@mediatek.com>
|
||||||
|
Date: Thu, 23 Jun 2022 18:37:55 +0800
|
||||||
|
Subject: [PATCH 3/6] drivers: spi-mem: Add spi calibration hook
|
||||||
|
|
||||||
|
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
|
||||||
|
---
|
||||||
|
drivers/spi/spi-mem.c | 8 ++++++++
|
||||||
|
include/linux/spi/spi-mem.h | 4 ++++
|
||||||
|
2 files changed, 12 insertions(+)
|
||||||
|
|
||||||
|
--- a/drivers/spi/spi-mem.c
|
||||||
|
+++ b/drivers/spi/spi-mem.c
|
||||||
|
@@ -419,6 +419,14 @@ int spi_mem_exec_op(struct spi_mem *mem,
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL_GPL(spi_mem_exec_op);
|
||||||
|
|
||||||
|
+int spi_mem_do_calibration(struct spi_mem *mem,
|
||||||
|
+ int (*cal_read)(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen),
|
||||||
|
+ void *priv)
|
||||||
|
+{
|
||||||
|
+ return spi_do_calibration(mem->spi->controller, mem->spi, cal_read, priv);
|
||||||
|
+}
|
||||||
|
+EXPORT_SYMBOL_GPL(spi_mem_do_calibration);
|
||||||
|
+
|
||||||
|
/**
|
||||||
|
* spi_mem_get_name() - Return the SPI mem device name to be used by the
|
||||||
|
* upper layer if necessary
|
||||||
|
--- a/include/linux/spi/spi-mem.h
|
||||||
|
+++ b/include/linux/spi/spi-mem.h
|
||||||
|
@@ -370,6 +370,10 @@ bool spi_mem_supports_op(struct spi_mem
|
||||||
|
int spi_mem_exec_op(struct spi_mem *mem,
|
||||||
|
const struct spi_mem_op *op);
|
||||||
|
|
||||||
|
+int spi_mem_do_calibration(struct spi_mem *mem,
|
||||||
|
+ int (*cal_read)(void *, u32 *, int, u8 *, int),
|
||||||
|
+ void *priv);
|
||||||
|
+
|
||||||
|
const char *spi_mem_get_name(struct spi_mem *mem);
|
||||||
|
|
||||||
|
struct spi_mem_dirmap_desc *
|
|
@ -0,0 +1,43 @@
|
||||||
|
From d278c7a0bf730318a7ccf8d0a8b434c813e23fd0 Mon Sep 17 00:00:00 2001
|
||||||
|
From: "SkyLake.Huang" <skylake.huang@mediatek.com>
|
||||||
|
Date: Thu, 23 Jun 2022 18:39:03 +0800
|
||||||
|
Subject: [PATCH 4/6] drivers: spi-mt65xx: Add controller's calibration
|
||||||
|
paramter
|
||||||
|
|
||||||
|
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
|
||||||
|
---
|
||||||
|
drivers/spi/spi-mt65xx.c | 16 ++++++++++++++++
|
||||||
|
1 file changed, 16 insertions(+)
|
||||||
|
|
||||||
|
--- a/drivers/spi/spi-mt65xx.c
|
||||||
|
+++ b/drivers/spi/spi-mt65xx.c
|
||||||
|
@@ -834,6 +834,21 @@ static irqreturn_t mtk_spi_interrupt(int
|
||||||
|
return IRQ_HANDLED;
|
||||||
|
}
|
||||||
|
|
||||||
|
+static int mtk_spi_append_caldata(struct spi_controller *ctlr)
|
||||||
|
+{
|
||||||
|
+ struct spi_cal_target *cal_target = kmalloc(sizeof(*cal_target), GFP_KERNEL);
|
||||||
|
+ struct mtk_spi *mdata = spi_master_get_devdata(ctlr);
|
||||||
|
+
|
||||||
|
+ cal_target->cal_item = &mdata->get_tick_dly;
|
||||||
|
+ cal_target->cal_min = 0;
|
||||||
|
+ cal_target->cal_max = 7;
|
||||||
|
+ cal_target->step = 1;
|
||||||
|
+
|
||||||
|
+ list_add(&cal_target->list, ctlr->cal_target);
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem,
|
||||||
|
struct spi_mem_op *op)
|
||||||
|
{
|
||||||
|
@@ -1124,6 +1139,7 @@ static int mtk_spi_probe(struct platform
|
||||||
|
master->setup = mtk_spi_setup;
|
||||||
|
master->set_cs_timing = mtk_spi_set_hw_cs_timing;
|
||||||
|
master->use_gpio_descriptors = true;
|
||||||
|
+ master->append_caldata = mtk_spi_append_caldata;
|
||||||
|
|
||||||
|
mdata = spi_master_get_devdata(master);
|
||||||
|
mdata->dev_comp = device_get_match_data(dev);
|
|
@ -0,0 +1,81 @@
|
||||||
|
From 7670ec4a14891a1a182b98a9c403ffbf6b49e4b1 Mon Sep 17 00:00:00 2001
|
||||||
|
From: "SkyLake.Huang" <skylake.huang@mediatek.com>
|
||||||
|
Date: Thu, 23 Jun 2022 18:39:56 +0800
|
||||||
|
Subject: [PATCH 5/6] drivers: mtd: spinand: Add calibration support for
|
||||||
|
spinand
|
||||||
|
|
||||||
|
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
|
||||||
|
---
|
||||||
|
drivers/mtd/nand/spi/core.c | 54 +++++++++++++++++++++++++++++++++++++
|
||||||
|
1 file changed, 54 insertions(+)
|
||||||
|
|
||||||
|
--- a/drivers/mtd/nand/spi/core.c
|
||||||
|
+++ b/drivers/mtd/nand/spi/core.c
|
||||||
|
@@ -979,6 +979,56 @@ static int spinand_manufacturer_match(st
|
||||||
|
return -ENOTSUPP;
|
||||||
|
}
|
||||||
|
|
||||||
|
+int spinand_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen) {
|
||||||
|
+ struct spinand_device *spinand = (struct spinand_device *)priv;
|
||||||
|
+ struct device *dev = &spinand->spimem->spi->dev;
|
||||||
|
+ struct spi_mem_op op = SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, buf, readlen);
|
||||||
|
+ struct nand_pos pos;
|
||||||
|
+ struct nand_page_io_req req;
|
||||||
|
+ u8 status;
|
||||||
|
+ int ret;
|
||||||
|
+
|
||||||
|
+ if(addrlen != sizeof(struct nand_addr)/sizeof(unsigned int)) {
|
||||||
|
+ dev_err(dev, "Must provide correct addr(length) for spinand calibration\n");
|
||||||
|
+ return -EINVAL;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ ret = spinand_reset_op(spinand);
|
||||||
|
+ if (ret)
|
||||||
|
+ return ret;
|
||||||
|
+
|
||||||
|
+ /* We should store our golden data in first target because
|
||||||
|
+ * we can't switch target at this moment.
|
||||||
|
+ */
|
||||||
|
+ pos = (struct nand_pos){
|
||||||
|
+ .target = 0,
|
||||||
|
+ .lun = *addr,
|
||||||
|
+ .plane = *(addr+1),
|
||||||
|
+ .eraseblock = *(addr+2),
|
||||||
|
+ .page = *(addr+3),
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ req = (struct nand_page_io_req){
|
||||||
|
+ .pos = pos,
|
||||||
|
+ .dataoffs = *(addr+4),
|
||||||
|
+ .datalen = readlen,
|
||||||
|
+ .databuf.in = buf,
|
||||||
|
+ .mode = MTD_OPS_AUTO_OOB,
|
||||||
|
+ };
|
||||||
|
+
|
||||||
|
+ ret = spinand_load_page_op(spinand, &req);
|
||||||
|
+ if (ret)
|
||||||
|
+ return ret;
|
||||||
|
+
|
||||||
|
+ ret = spinand_wait(spinand, &status);
|
||||||
|
+ if (ret < 0)
|
||||||
|
+ return ret;
|
||||||
|
+
|
||||||
|
+ ret = spi_mem_exec_op(spinand->spimem, &op);
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
static int spinand_id_detect(struct spinand_device *spinand)
|
||||||
|
{
|
||||||
|
u8 *id = spinand->id.data;
|
||||||
|
@@ -1229,6 +1279,10 @@ static int spinand_init(struct spinand_d
|
||||||
|
if (!spinand->scratchbuf)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
+ ret = spi_mem_do_calibration(spinand->spimem, spinand_cal_read, spinand);
|
||||||
|
+ if (ret)
|
||||||
|
+ dev_err(dev, "Failed to calibrate SPI-NAND (err = %d)\n", ret);
|
||||||
|
+
|
||||||
|
ret = spinand_detect(spinand);
|
||||||
|
if (ret)
|
||||||
|
goto err_free_bufs;
|
|
@ -0,0 +1,57 @@
|
||||||
|
From f3fe3b15eca7908eaac57f9b8387a5dbc45ec5b2 Mon Sep 17 00:00:00 2001
|
||||||
|
From: "SkyLake.Huang" <skylake.huang@mediatek.com>
|
||||||
|
Date: Thu, 23 Jun 2022 18:40:59 +0800
|
||||||
|
Subject: [PATCH 6/6] drivers: mtd: spi-nor: Add calibration support for
|
||||||
|
spi-nor
|
||||||
|
|
||||||
|
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
|
||||||
|
---
|
||||||
|
drivers/mtd/nand/spi/core.c | 5 ++++-
|
||||||
|
drivers/mtd/spi-nor/core.c | 15 +++++++++++++++
|
||||||
|
2 files changed, 19 insertions(+), 1 deletion(-)
|
||||||
|
|
||||||
|
--- a/drivers/mtd/nand/spi/core.c
|
||||||
|
+++ b/drivers/mtd/nand/spi/core.c
|
||||||
|
@@ -1020,7 +1020,10 @@ int spinand_cal_read(void *priv, u32 *ad
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
- ret = spinand_wait(spinand, &status);
|
||||||
|
+ ret = spinand_wait(spinand,
|
||||||
|
+ SPINAND_READ_INITIAL_DELAY_US,
|
||||||
|
+ SPINAND_READ_POLL_DELAY_US,
|
||||||
|
+ &status);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
--- a/drivers/mtd/spi-nor/core.c
|
||||||
|
+++ b/drivers/mtd/spi-nor/core.c
|
||||||
|
@@ -3378,6 +3378,18 @@ static const struct flash_info *spi_nor_
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
+static int spi_nor_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen)
|
||||||
|
+{
|
||||||
|
+ struct spi_nor *nor = (struct spi_nor *)priv;
|
||||||
|
+
|
||||||
|
+ nor->reg_proto = SNOR_PROTO_1_1_1;
|
||||||
|
+ nor->read_proto = SNOR_PROTO_1_1_1;
|
||||||
|
+ nor->read_opcode = SPINOR_OP_READ;
|
||||||
|
+ nor->read_dummy = 0;
|
||||||
|
+
|
||||||
|
+ return nor->controller_ops->read(nor, *addr, readlen, buf);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor,
|
||||||
|
const char *name)
|
||||||
|
{
|
||||||
|
@@ -3506,6 +3518,9 @@ int spi_nor_scan(struct spi_nor *nor, co
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
+ if(nor->spimem)
|
||||||
|
+ spi_mem_do_calibration(nor->spimem, spi_nor_cal_read, nor);
|
||||||
|
+
|
||||||
|
info = spi_nor_get_flash_info(nor, name);
|
||||||
|
if (IS_ERR(info))
|
||||||
|
return PTR_ERR(info);
|
|
@ -0,0 +1,25 @@
|
||||||
|
--- a/drivers/net/phy/Kconfig
|
||||||
|
+++ b/drivers/net/phy/Kconfig
|
||||||
|
@@ -419,6 +419,12 @@ config ROCKCHIP_PHY
|
||||||
|
help
|
||||||
|
Currently supports the integrated Ethernet PHY.
|
||||||
|
|
||||||
|
+config RTL8367S_GSW
|
||||||
|
+ tristate "rtl8367 Gigabit Switch support for mt7622"
|
||||||
|
+ depends on NET_VENDOR_MEDIATEK
|
||||||
|
+ help
|
||||||
|
+ This driver supports rtl8367s in mt7622
|
||||||
|
+
|
||||||
|
config SMSC_PHY
|
||||||
|
tristate "SMSC PHYs"
|
||||||
|
select CRC16
|
||||||
|
--- a/drivers/net/phy/Makefile
|
||||||
|
+++ b/drivers/net/phy/Makefile
|
||||||
|
@@ -102,6 +102,7 @@ obj-$(CONFIG_QSEMI_PHY) += qsemi.o
|
||||||
|
obj-$(CONFIG_REALTEK_PHY) += realtek.o
|
||||||
|
obj-$(CONFIG_RENESAS_PHY) += uPD60620.o
|
||||||
|
obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o
|
||||||
|
+obj-$(CONFIG_RTL8367S_GSW) += rtk/
|
||||||
|
obj-$(CONFIG_SMSC_PHY) += smsc.o
|
||||||
|
obj-$(CONFIG_STE10XP) += ste10Xp.o
|
||||||
|
obj-$(CONFIG_TERANETICS_PHY) += teranetics.o
|
|
@ -0,0 +1,34 @@
|
||||||
|
From: qizhong cheng <qizhong.cheng@mediatek.com>
|
||||||
|
Date: Mon, 27 Dec 2021 21:31:10 +0800
|
||||||
|
Subject: [PATCH] PCI: mediatek: Assert PERST# for 100ms for power and clock to
|
||||||
|
stabilize
|
||||||
|
MIME-Version: 1.0
|
||||||
|
Content-Type: text/plain; charset=UTF-8
|
||||||
|
Content-Transfer-Encoding: 8bit
|
||||||
|
|
||||||
|
Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
|
||||||
|
2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
|
||||||
|
be delayed 100ms (TPVPERL) for the power and clock to become stable.
|
||||||
|
|
||||||
|
Link: https://lore.kernel.org/r/20211227133110.14500-1-qizhong.cheng@mediatek.com
|
||||||
|
Signed-off-by: qizhong cheng <qizhong.cheng@mediatek.com>
|
||||||
|
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
|
||||||
|
Acked-by: Pali Rohár <pali@kernel.org>
|
||||||
|
---
|
||||||
|
|
||||||
|
--- a/drivers/pci/controller/pcie-mediatek.c
|
||||||
|
+++ b/drivers/pci/controller/pcie-mediatek.c
|
||||||
|
@@ -708,6 +708,13 @@ static int mtk_pcie_startup_port_v2(stru
|
||||||
|
*/
|
||||||
|
msleep(100);
|
||||||
|
|
||||||
|
+ /*
|
||||||
|
+ * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
|
||||||
|
+ * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
|
||||||
|
+ * be delayed 100ms (TPVPERL) for the power and clock to become stable.
|
||||||
|
+ */
|
||||||
|
+ msleep(100);
|
||||||
|
+
|
||||||
|
/* De-assert PHY, PE, PIPE, MAC and configuration reset */
|
||||||
|
val = readl(port->base + PCIE_RST_CTRL);
|
||||||
|
val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
|
|
@ -0,0 +1,28 @@
|
||||||
|
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||||
|
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||||
|
@@ -844,6 +844,12 @@
|
||||||
|
#address-cells = <0>;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
};
|
||||||
|
+
|
||||||
|
+ slot0: pcie@0,0 {
|
||||||
|
+ reg = <0x0000 0 0 0 0>;
|
||||||
|
+ #address-cells = <3>;
|
||||||
|
+ #size-cells = <2>;
|
||||||
|
+ };
|
||||||
|
};
|
||||||
|
|
||||||
|
pcie1: pcie@1a145000 {
|
||||||
|
@@ -882,6 +888,12 @@
|
||||||
|
#address-cells = <0>;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
};
|
||||||
|
+
|
||||||
|
+ slot1: pcie@1,0 {
|
||||||
|
+ reg = <0x0800 0 0 0 0>;
|
||||||
|
+ #address-cells = <3>;
|
||||||
|
+ #size-cells = <2>;
|
||||||
|
+ };
|
||||||
|
};
|
||||||
|
|
||||||
|
sata: sata@1a200000 {
|
|
@ -0,0 +1,23 @@
|
||||||
|
From: Felix Fietkau <nbd@nbd.name>
|
||||||
|
Date: Fri, 4 Sep 2020 18:33:27 +0200
|
||||||
|
Subject: [PATCH] pcie-mediatek: fix clearing interrupt status
|
||||||
|
|
||||||
|
Clearing the status needs to happen after running the handler, otherwise
|
||||||
|
we will get an extra spurious interrupt after the cause has been cleared
|
||||||
|
|
||||||
|
Signed-off-by: Felix Fietkau <nbd@nbd.name>
|
||||||
|
---
|
||||||
|
|
||||||
|
--- a/drivers/pci/controller/pcie-mediatek.c
|
||||||
|
+++ b/drivers/pci/controller/pcie-mediatek.c
|
||||||
|
@@ -607,9 +607,9 @@ static void mtk_pcie_intr_handler(struct
|
||||||
|
if (status & INTX_MASK) {
|
||||||
|
for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
|
||||||
|
/* Clear the INTx */
|
||||||
|
- writel(1 << bit, port->base + PCIE_INT_STATUS);
|
||||||
|
generic_handle_domain_irq(port->irq_domain,
|
||||||
|
bit - INTX_SHIFT);
|
||||||
|
+ writel(1 << bit, port->base + PCIE_INT_STATUS);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
|
@ -0,0 +1,17 @@
|
||||||
|
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
|
||||||
|
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
|
||||||
|
@@ -375,7 +375,13 @@ static int mtk_pcie_startup_port(struct
|
||||||
|
msleep(100);
|
||||||
|
|
||||||
|
/* De-assert reset signals */
|
||||||
|
- val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
|
||||||
|
+ val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB);
|
||||||
|
+ writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
|
||||||
|
+
|
||||||
|
+ msleep(100);
|
||||||
|
+
|
||||||
|
+ /* De-assert PERST# signals */
|
||||||
|
+ val &= ~(PCIE_PE_RSTB);
|
||||||
|
writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
|
||||||
|
|
||||||
|
/* Check if the link is up or not */
|
|
@ -0,0 +1,167 @@
|
||||||
|
From 50cefacc6c001eea1d9b1c78ba27304566f304f1 Mon Sep 17 00:00:00 2001
|
||||||
|
From: Daniel Golle <daniel@makrotopia.org>
|
||||||
|
Date: Fri, 2 Jun 2023 13:06:26 +0800
|
||||||
|
Subject: [PATCH] phy: mediatek: xsphy: support type switch by pericfg
|
||||||
|
|
||||||
|
Patch from Sam Shih <sam.shih@mediatek.com> found in MediaTek SDK
|
||||||
|
released under GPL.
|
||||||
|
|
||||||
|
Get syscon and use it to set the PHY type.
|
||||||
|
Extend support to PCIe and SGMII mode in addition to USB2 and USB3.
|
||||||
|
|
||||||
|
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||||
|
---
|
||||||
|
drivers/phy/mediatek/phy-mtk-xsphy.c | 81 +++++++++++++++++++++++++++-
|
||||||
|
1 file changed, 80 insertions(+), 1 deletion(-)
|
||||||
|
|
||||||
|
--- a/drivers/phy/mediatek/phy-mtk-xsphy.c
|
||||||
|
+++ b/drivers/phy/mediatek/phy-mtk-xsphy.c
|
||||||
|
@@ -11,10 +11,12 @@
|
||||||
|
#include <linux/clk.h>
|
||||||
|
#include <linux/delay.h>
|
||||||
|
#include <linux/iopoll.h>
|
||||||
|
+#include <linux/mfd/syscon.h>
|
||||||
|
#include <linux/module.h>
|
||||||
|
#include <linux/of_address.h>
|
||||||
|
#include <linux/phy/phy.h>
|
||||||
|
#include <linux/platform_device.h>
|
||||||
|
+#include <linux/regmap.h>
|
||||||
|
|
||||||
|
#include "phy-mtk-io.h"
|
||||||
|
|
||||||
|
@@ -81,12 +83,22 @@
|
||||||
|
#define XSP_SR_COEF_DIVISOR 1000
|
||||||
|
#define XSP_FM_DET_CYCLE_CNT 1024
|
||||||
|
|
||||||
|
+/* PHY switch between pcie/usb3/sgmii */
|
||||||
|
+#define USB_PHY_SWITCH_CTRL 0x0
|
||||||
|
+#define RG_PHY_SW_TYPE GENMASK(3, 0)
|
||||||
|
+#define RG_PHY_SW_PCIE 0x0
|
||||||
|
+#define RG_PHY_SW_USB3 0x1
|
||||||
|
+#define RG_PHY_SW_SGMII 0x2
|
||||||
|
+
|
||||||
|
struct xsphy_instance {
|
||||||
|
struct phy *phy;
|
||||||
|
void __iomem *port_base;
|
||||||
|
struct clk *ref_clk; /* reference clock of anolog phy */
|
||||||
|
u32 index;
|
||||||
|
u32 type;
|
||||||
|
+ struct regmap *type_sw;
|
||||||
|
+ u32 type_sw_reg;
|
||||||
|
+ u32 type_sw_index;
|
||||||
|
/* only for HQA test */
|
||||||
|
int efuse_intr;
|
||||||
|
int efuse_tx_imp;
|
||||||
|
@@ -259,6 +271,10 @@ static void phy_parse_property(struct mt
|
||||||
|
inst->efuse_intr, inst->efuse_tx_imp,
|
||||||
|
inst->efuse_rx_imp);
|
||||||
|
break;
|
||||||
|
+ case PHY_TYPE_PCIE:
|
||||||
|
+ case PHY_TYPE_SGMII:
|
||||||
|
+ /* nothing to do */
|
||||||
|
+ break;
|
||||||
|
default:
|
||||||
|
dev_err(xsphy->dev, "incompatible phy type\n");
|
||||||
|
return;
|
||||||
|
@@ -305,6 +321,62 @@ static void u3_phy_props_set(struct mtk_
|
||||||
|
RG_XTP_LN0_RX_IMPSEL, inst->efuse_rx_imp);
|
||||||
|
}
|
||||||
|
|
||||||
|
+/* type switch for usb3/pcie/sgmii */
|
||||||
|
+static int phy_type_syscon_get(struct xsphy_instance *instance,
|
||||||
|
+ struct device_node *dn)
|
||||||
|
+{
|
||||||
|
+ struct of_phandle_args args;
|
||||||
|
+ int ret;
|
||||||
|
+
|
||||||
|
+ /* type switch function is optional */
|
||||||
|
+ if (!of_property_read_bool(dn, "mediatek,syscon-type"))
|
||||||
|
+ return 0;
|
||||||
|
+
|
||||||
|
+ ret = of_parse_phandle_with_fixed_args(dn, "mediatek,syscon-type",
|
||||||
|
+ 2, 0, &args);
|
||||||
|
+ if (ret)
|
||||||
|
+ return ret;
|
||||||
|
+
|
||||||
|
+ instance->type_sw_reg = args.args[0];
|
||||||
|
+ instance->type_sw_index = args.args[1] & 0x3; /* <=3 */
|
||||||
|
+ instance->type_sw = syscon_node_to_regmap(args.np);
|
||||||
|
+ of_node_put(args.np);
|
||||||
|
+ dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n",
|
||||||
|
+ instance->type_sw_reg, instance->type_sw_index);
|
||||||
|
+
|
||||||
|
+ return PTR_ERR_OR_ZERO(instance->type_sw);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static int phy_type_set(struct xsphy_instance *instance)
|
||||||
|
+{
|
||||||
|
+ int type;
|
||||||
|
+ u32 offset;
|
||||||
|
+
|
||||||
|
+ if (!instance->type_sw)
|
||||||
|
+ return 0;
|
||||||
|
+
|
||||||
|
+ switch (instance->type) {
|
||||||
|
+ case PHY_TYPE_USB3:
|
||||||
|
+ type = RG_PHY_SW_USB3;
|
||||||
|
+ break;
|
||||||
|
+ case PHY_TYPE_PCIE:
|
||||||
|
+ type = RG_PHY_SW_PCIE;
|
||||||
|
+ break;
|
||||||
|
+ case PHY_TYPE_SGMII:
|
||||||
|
+ type = RG_PHY_SW_SGMII;
|
||||||
|
+ break;
|
||||||
|
+ case PHY_TYPE_USB2:
|
||||||
|
+ default:
|
||||||
|
+ return 0;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ offset = instance->type_sw_index * BITS_PER_BYTE;
|
||||||
|
+ regmap_update_bits(instance->type_sw, instance->type_sw_reg,
|
||||||
|
+ RG_PHY_SW_TYPE << offset, type << offset);
|
||||||
|
+
|
||||||
|
+ return 0;
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
static int mtk_phy_init(struct phy *phy)
|
||||||
|
{
|
||||||
|
struct xsphy_instance *inst = phy_get_drvdata(phy);
|
||||||
|
@@ -325,6 +397,10 @@ static int mtk_phy_init(struct phy *phy)
|
||||||
|
case PHY_TYPE_USB3:
|
||||||
|
u3_phy_props_set(xsphy, inst);
|
||||||
|
break;
|
||||||
|
+ case PHY_TYPE_PCIE:
|
||||||
|
+ case PHY_TYPE_SGMII:
|
||||||
|
+ /* nothing to do, only used to set type */
|
||||||
|
+ break;
|
||||||
|
default:
|
||||||
|
dev_err(xsphy->dev, "incompatible phy type\n");
|
||||||
|
clk_disable_unprepare(inst->ref_clk);
|
||||||
|
@@ -403,12 +479,15 @@ static struct phy *mtk_phy_xlate(struct
|
||||||
|
|
||||||
|
inst->type = args->args[0];
|
||||||
|
if (!(inst->type == PHY_TYPE_USB2 ||
|
||||||
|
- inst->type == PHY_TYPE_USB3)) {
|
||||||
|
+ inst->type == PHY_TYPE_USB3 ||
|
||||||
|
+ inst->type == PHY_TYPE_PCIE ||
|
||||||
|
+ inst->type == PHY_TYPE_SGMII)) {
|
||||||
|
dev_err(dev, "unsupported phy type: %d\n", inst->type);
|
||||||
|
return ERR_PTR(-EINVAL);
|
||||||
|
}
|
||||||
|
|
||||||
|
phy_parse_property(xsphy, inst);
|
||||||
|
+ phy_type_set(inst);
|
||||||
|
|
||||||
|
return inst->phy;
|
||||||
|
}
|
||||||
|
@@ -515,6 +594,10 @@ static int mtk_xsphy_probe(struct platfo
|
||||||
|
retval = PTR_ERR(inst->ref_clk);
|
||||||
|
goto put_child;
|
||||||
|
}
|
||||||
|
+
|
||||||
|
+ retval = phy_type_syscon_get(inst, child_np);
|
||||||
|
+ if (retval)
|
||||||
|
+ goto put_child;
|
||||||
|
}
|
||||||
|
|
||||||
|
provider = devm_of_phy_provider_register(dev, mtk_phy_xlate);
|
|
@ -0,0 +1,91 @@
|
||||||
|
From: Felix Fietkau <nbd@nbd.name>
|
||||||
|
Date: Fri, 4 Sep 2020 18:42:42 +0200
|
||||||
|
Subject: [PATCH] pci: pcie-mediatek: add support for coherent DMA
|
||||||
|
|
||||||
|
It improves performance by eliminating the need for a cache flush for DMA on
|
||||||
|
attached devices
|
||||||
|
|
||||||
|
Signed-off-by: Felix Fietkau <nbd@nbd.name>
|
||||||
|
---
|
||||||
|
|
||||||
|
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||||
|
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||||
|
@@ -832,6 +832,9 @@
|
||||||
|
bus-range = <0x00 0xff>;
|
||||||
|
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
|
||||||
|
status = "disabled";
|
||||||
|
+ dma-coherent;
|
||||||
|
+ mediatek,hifsys = <&hifsys>;
|
||||||
|
+ mediatek,cci-control = <&cci_control2>;
|
||||||
|
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
interrupt-map-mask = <0 0 0 7>;
|
||||||
|
@@ -876,6 +879,9 @@
|
||||||
|
bus-range = <0x00 0xff>;
|
||||||
|
ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
|
||||||
|
status = "disabled";
|
||||||
|
+ dma-coherent;
|
||||||
|
+ mediatek,hifsys = <&hifsys>;
|
||||||
|
+ mediatek,cci-control = <&cci_control2>;
|
||||||
|
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
interrupt-map-mask = <0 0 0 7>;
|
||||||
|
@@ -937,7 +943,7 @@
|
||||||
|
};
|
||||||
|
|
||||||
|
hifsys: clock-controller@1af00000 {
|
||||||
|
- compatible = "mediatek,mt7622-hifsys";
|
||||||
|
+ compatible = "mediatek,mt7622-hifsys", "syscon";
|
||||||
|
reg = <0 0x1af00000 0 0x70>;
|
||||||
|
#clock-cells = <1>;
|
||||||
|
};
|
||||||
|
--- a/drivers/pci/controller/pcie-mediatek.c
|
||||||
|
+++ b/drivers/pci/controller/pcie-mediatek.c
|
||||||
|
@@ -20,6 +20,7 @@
|
||||||
|
#include <linux/of_address.h>
|
||||||
|
#include <linux/of_pci.h>
|
||||||
|
#include <linux/of_platform.h>
|
||||||
|
+#include <linux/of_address.h>
|
||||||
|
#include <linux/pci.h>
|
||||||
|
#include <linux/phy/phy.h>
|
||||||
|
#include <linux/platform_device.h>
|
||||||
|
@@ -139,6 +140,11 @@
|
||||||
|
#define PCIE_LINK_STATUS_V2 0x804
|
||||||
|
#define PCIE_PORT_LINKUP_V2 BIT(10)
|
||||||
|
|
||||||
|
+/* DMA channel mapping */
|
||||||
|
+#define HIFSYS_DMA_AG_MAP 0x008
|
||||||
|
+#define HIFSYS_DMA_AG_MAP_PCIE0 BIT(0)
|
||||||
|
+#define HIFSYS_DMA_AG_MAP_PCIE1 BIT(1)
|
||||||
|
+
|
||||||
|
struct mtk_pcie_port;
|
||||||
|
|
||||||
|
/**
|
||||||
|
@@ -1060,6 +1066,27 @@ static int mtk_pcie_setup(struct mtk_pci
|
||||||
|
struct mtk_pcie_port *port, *tmp;
|
||||||
|
int err, slot;
|
||||||
|
|
||||||
|
+ if (of_dma_is_coherent(node)) {
|
||||||
|
+ struct regmap *con;
|
||||||
|
+ u32 mask;
|
||||||
|
+
|
||||||
|
+ con = syscon_regmap_lookup_by_phandle(node,
|
||||||
|
+ "mediatek,cci-control");
|
||||||
|
+ /* enable CPU/bus coherency */
|
||||||
|
+ if (!IS_ERR(con))
|
||||||
|
+ regmap_write(con, 0, 3);
|
||||||
|
+
|
||||||
|
+ con = syscon_regmap_lookup_by_phandle(node,
|
||||||
|
+ "mediatek,hifsys");
|
||||||
|
+ if (IS_ERR(con)) {
|
||||||
|
+ dev_err(dev, "missing hifsys node\n");
|
||||||
|
+ return PTR_ERR(con);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
+ mask = HIFSYS_DMA_AG_MAP_PCIE0 | HIFSYS_DMA_AG_MAP_PCIE1;
|
||||||
|
+ regmap_update_bits(con, HIFSYS_DMA_AG_MAP, mask, mask);
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
slot = of_get_pci_domain_nr(dev->of_node);
|
||||||
|
if (slot < 0) {
|
||||||
|
for_each_available_child_of_node(node, child) {
|
|
@ -0,0 +1,27 @@
|
||||||
|
From: Jip de Beer <gpk6x3591g0l@opayq.com>
|
||||||
|
Date: Sun, 9 Jan 2022 13:14:04 +0100
|
||||||
|
Subject: [PATCH] mediatek mt7622: fix 300mhz typo in dts
|
||||||
|
|
||||||
|
The lowest frequency should be 300MHz, since that is the label
|
||||||
|
assigned to the OPP in the mt7622.dtsi device tree, while there is one
|
||||||
|
missing zero in the actual value.
|
||||||
|
|
||||||
|
To be clear, the lowest frequency should be 300MHz instead of 30MHz.
|
||||||
|
|
||||||
|
As mentioned @dangowrt on the OpenWrt forum there is no benefit in
|
||||||
|
leaving 30MHz as the lowest frequency.
|
||||||
|
|
||||||
|
Signed-off-by: Jip de Beer <gpk6x3591g0l@opayq.com>
|
||||||
|
Signed-off-by: Fritz D. Ansel <fdansel@yandex.ru>
|
||||||
|
---
|
||||||
|
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||||
|
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||||
|
@@ -24,7 +24,7 @@
|
||||||
|
compatible = "operating-points-v2";
|
||||||
|
opp-shared;
|
||||||
|
opp-300000000 {
|
||||||
|
- opp-hz = /bits/ 64 <30000000>;
|
||||||
|
+ opp-hz = /bits/ 64 <300000000>;
|
||||||
|
opp-microvolt = <950000>;
|
||||||
|
};
|
||||||
|
|
|
@ -0,0 +1,25 @@
|
||||||
|
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||||
|
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||||
|
@@ -23,11 +23,17 @@
|
||||||
|
cpu_opp_table: opp-table {
|
||||||
|
compatible = "operating-points-v2";
|
||||||
|
opp-shared;
|
||||||
|
- opp-300000000 {
|
||||||
|
- opp-hz = /bits/ 64 <300000000>;
|
||||||
|
- opp-microvolt = <950000>;
|
||||||
|
- };
|
||||||
|
-
|
||||||
|
+ /* Due to the bug described at the link below, remove the 300 MHz clock to avoid a low
|
||||||
|
+ * voltage condition that can cause a hang when rebooting the RT3200/E8450.
|
||||||
|
+ *
|
||||||
|
+ * https://forum.openwrt.org/t/belkin-rt3200-linksys-e8450-wifi-ax-discussion/94302/1490
|
||||||
|
+ *
|
||||||
|
+ * opp-300000000 {
|
||||||
|
+ * opp-hz = /bits/ 64 <300000000>;
|
||||||
|
+ * opp-microvolt = <950000>;
|
||||||
|
+ * };
|
||||||
|
+ *
|
||||||
|
+ */
|
||||||
|
opp-437500000 {
|
||||||
|
opp-hz = /bits/ 64 <437500000>;
|
||||||
|
opp-microvolt = <1000000>;
|
|
@ -0,0 +1,63 @@
|
||||||
|
From a969b663c866129ed9eb217785a6574fbe826f1d Mon Sep 17 00:00:00 2001
|
||||||
|
From: Daniel Golle <daniel@makrotopia.org>
|
||||||
|
Date: Thu, 6 Apr 2023 23:36:50 +0100
|
||||||
|
Subject: [PATCH] net: phy: mxl-gpy: don't use SGMII AN if using phylink
|
||||||
|
|
||||||
|
MAC drivers using phylink expect SGMII in-band-status to be switched off
|
||||||
|
when attached to a PHY. Make sure this is the case also for mxl-gpy which
|
||||||
|
keeps SGMII in-band-status in case of SGMII interface mode is used.
|
||||||
|
|
||||||
|
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||||
|
---
|
||||||
|
drivers/net/phy/mxl-gpy.c | 19 ++++++++++++++++---
|
||||||
|
1 file changed, 16 insertions(+), 3 deletions(-)
|
||||||
|
|
||||||
|
--- a/drivers/net/phy/mxl-gpy.c
|
||||||
|
+++ b/drivers/net/phy/mxl-gpy.c
|
||||||
|
@@ -386,8 +386,11 @@ static bool gpy_2500basex_chk(struct phy
|
||||||
|
|
||||||
|
phydev->speed = SPEED_2500;
|
||||||
|
phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
|
||||||
|
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
|
||||||
|
- VSPEC1_SGMII_CTRL_ANEN, 0);
|
||||||
|
+
|
||||||
|
+ if (!phydev->phylink)
|
||||||
|
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
|
||||||
|
+ VSPEC1_SGMII_CTRL_ANEN, 0);
|
||||||
|
+
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
@@ -438,6 +441,14 @@ static int gpy_config_aneg(struct phy_de
|
||||||
|
u32 adv;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
+ /* Disable SGMII auto-negotiation if using phylink */
|
||||||
|
+ if (phydev->phylink) {
|
||||||
|
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
|
||||||
|
+ VSPEC1_SGMII_CTRL_ANEN, 0);
|
||||||
|
+ if (ret < 0)
|
||||||
|
+ return ret;
|
||||||
|
+ }
|
||||||
|
+
|
||||||
|
if (phydev->autoneg == AUTONEG_DISABLE) {
|
||||||
|
/* Configure half duplex with genphy_setup_forced,
|
||||||
|
* because genphy_c45_pma_setup_forced does not support.
|
||||||
|
@@ -560,6 +571,8 @@ static int gpy_update_interface(struct p
|
||||||
|
switch (phydev->speed) {
|
||||||
|
case SPEED_2500:
|
||||||
|
phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
|
||||||
|
+ if (phydev->phylink)
|
||||||
|
+ break;
|
||||||
|
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
|
||||||
|
VSPEC1_SGMII_CTRL_ANEN, 0);
|
||||||
|
if (ret < 0) {
|
||||||
|
@@ -573,7 +586,7 @@ static int gpy_update_interface(struct p
|
||||||
|
case SPEED_100:
|
||||||
|
case SPEED_10:
|
||||||
|
phydev->interface = PHY_INTERFACE_MODE_SGMII;
|
||||||
|
- if (gpy_sgmii_aneg_en(phydev))
|
||||||
|
+ if (phydev->phylink || gpy_sgmii_aneg_en(phydev))
|
||||||
|
break;
|
||||||
|
/* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed
|
||||||
|
* if ANEG is disabled (in 2500-BaseX mode).
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Add table
Add a link
Reference in a new issue