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https://github.com/Ysurac/openmptcprouter.git
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Add not yet tested code for RPI5 support
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
501a471507
commit
7f3388ed3b
214 changed files with 58823 additions and 0 deletions
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@ -0,0 +1,249 @@
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From bb05ccd66342643b1cd9a0a48cec3ebdc3eed511 Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Tue, 21 Feb 2023 14:38:32 +0100
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Subject: [PATCH 0975/1016] drm/vc4: Add additional warn_on
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Some code path in vc4 are conditional to a generation and cannot be
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executed on others. Let's put a WARN_ON if that ever happens.
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/gpu/drm/vc4/vc4_hvs.c | 32 ++++++++++++++++++++++++++++++--
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drivers/gpu/drm/vc4/vc4_kms.c | 6 ++++++
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drivers/gpu/drm/vc4/vc4_plane.c | 19 +++++++++++++++++++
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3 files changed, 55 insertions(+), 2 deletions(-)
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diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c
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index 24b1630f56e8..e3ed0c27a71c 100644
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--- a/drivers/gpu/drm/vc4/vc4_hvs.c
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+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
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@@ -417,12 +417,15 @@ static int vc4_hvs_upload_linear_kernel(struct vc4_hvs *hvs,
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static void vc4_hvs_lut_load(struct vc4_hvs *hvs,
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struct vc4_crtc *vc4_crtc)
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{
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- struct drm_device *drm = &hvs->vc4->base;
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+ struct vc4_dev *vc4 = hvs->vc4;
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+ struct drm_device *drm = &vc4->base;
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struct drm_crtc *crtc = &vc4_crtc->base;
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struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
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int idx;
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u32 i;
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+ WARN_ON_ONCE(vc4->gen > VC4_GEN_5);
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+
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if (!drm_dev_enter(drm, &idx))
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return;
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@@ -758,6 +761,8 @@ u8 vc4_hvs_get_fifo_frame_count(struct vc4_hvs *hvs, unsigned int fifo)
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u8 field = 0;
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int idx;
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+ WARN_ON_ONCE(vc4->gen > VC4_GEN_6);
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+
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if (!drm_dev_enter(drm, &idx))
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return 0;
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@@ -791,6 +796,8 @@ int vc4_hvs_get_fifo_from_output(struct vc4_hvs *hvs, unsigned int output)
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u32 reg;
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int ret;
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+ WARN_ON_ONCE(vc4->gen > VC4_GEN_6);
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+
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switch (vc4->gen) {
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case VC4_GEN_4:
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return output;
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@@ -880,6 +887,8 @@ static int vc4_hvs_init_channel(struct vc4_hvs *hvs, struct drm_crtc *crtc,
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u32 dispctrl;
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int idx;
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+ WARN_ON_ONCE(vc4->gen > VC4_GEN_5);
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+
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if (!drm_dev_enter(drm, &idx))
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return -ENODEV;
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@@ -947,6 +956,8 @@ static int vc6_hvs_init_channel(struct vc4_hvs *hvs, struct drm_crtc *crtc,
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u32 disp_ctrl1;
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int idx;
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+ WARN_ON_ONCE(vc4->gen != VC4_GEN_6);
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+
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if (!drm_dev_enter(drm, &idx))
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return -ENODEV;
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@@ -972,9 +983,12 @@ static int vc6_hvs_init_channel(struct vc4_hvs *hvs, struct drm_crtc *crtc,
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static void __vc4_hvs_stop_channel(struct vc4_hvs *hvs, unsigned int chan)
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{
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- struct drm_device *drm = &hvs->vc4->base;
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+ struct vc4_dev *vc4 = hvs->vc4;
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+ struct drm_device *drm = &vc4->base;
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int idx;
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+ WARN_ON_ONCE(vc4->gen > VC4_GEN_5);
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+
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if (!drm_dev_enter(drm, &idx))
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return;
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@@ -1007,6 +1021,8 @@ static void __vc6_hvs_stop_channel(struct vc4_hvs *hvs, unsigned int chan)
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struct drm_device *drm = &vc4->base;
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int idx;
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+ WARN_ON_ONCE(vc4->gen != VC4_GEN_6);
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+
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if (!drm_dev_enter(drm, &idx))
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return;
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@@ -1234,6 +1250,8 @@ void vc4_hvs_atomic_flush(struct drm_crtc *crtc,
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bool found = false;
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int idx;
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+ WARN_ON_ONCE(vc4->gen > VC4_GEN_6);
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+
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if (!drm_dev_enter(dev, &idx)) {
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vc4_crtc_send_vblank(crtc);
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return;
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@@ -1324,6 +1342,8 @@ void vc4_hvs_atomic_flush(struct drm_crtc *crtc,
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if (crtc->state->color_mgmt_changed) {
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u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(channel));
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+ WARN_ON_ONCE(vc4->gen > VC4_GEN_5);
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+
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if (crtc->state->gamma_lut) {
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if (vc4->gen == VC4_GEN_4) {
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vc4_hvs_update_gamma_lut(hvs, vc4_crtc);
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@@ -1363,6 +1383,8 @@ void vc4_hvs_mask_underrun(struct vc4_hvs *hvs, int channel)
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u32 dispctrl;
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int idx;
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+ WARN_ON(vc4->gen > VC4_GEN_5);
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+
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if (!drm_dev_enter(drm, &idx))
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return;
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@@ -1383,6 +1405,8 @@ void vc4_hvs_unmask_underrun(struct vc4_hvs *hvs, int channel)
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u32 dispctrl;
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int idx;
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+ WARN_ON(vc4->gen > VC4_GEN_5);
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+
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if (!drm_dev_enter(drm, &idx))
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return;
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@@ -1417,6 +1441,8 @@ static irqreturn_t vc4_hvs_irq_handler(int irq, void *data)
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u32 status;
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u32 dspeislur;
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+ WARN_ON(vc4->gen > VC4_GEN_5);
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+
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/*
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* NOTE: We don't need to protect the register access using
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* drm_dev_enter() there because the interrupt handler lifetime
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@@ -1466,6 +1492,8 @@ static irqreturn_t vc6_hvs_eof_irq_handler(int irq, void *data)
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struct vc4_hvs *hvs = vc4->hvs;
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unsigned int i;
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+ WARN_ON(vc4->gen < VC4_GEN_6);
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+
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for (i = 0; i < HVS_NUM_CHANNELS; i++) {
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if (!hvs->eof_irq[i].enabled)
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continue;
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diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
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index 00efc5b9f906..3aeab0c26aff 100644
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--- a/drivers/gpu/drm/vc4/vc4_kms.c
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+++ b/drivers/gpu/drm/vc4/vc4_kms.c
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@@ -147,6 +147,8 @@ vc4_ctm_commit(struct vc4_dev *vc4, struct drm_atomic_state *state)
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if (vc4->firmware_kms)
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return;
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+ WARN_ON_ONCE(vc4->gen > VC4_GEN_5);
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+
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if (ctm_state->fifo) {
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HVS_WRITE(SCALER_OLEDCOEF2,
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VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]),
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@@ -222,6 +224,8 @@ static void vc4_hvs_pv_muxing_commit(struct vc4_dev *vc4,
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struct drm_crtc *crtc;
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unsigned int i;
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+ WARN_ON_ONCE(vc4->gen != VC4_GEN_4);
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+
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for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
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struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
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@@ -265,6 +269,8 @@ static void vc5_hvs_pv_muxing_commit(struct vc4_dev *vc4,
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unsigned int i;
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u32 reg;
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+ WARN_ON_ONCE(vc4->gen != VC4_GEN_5);
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+
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for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
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struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
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struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
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index 1e205749812a..314bc56cbae6 100644
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--- a/drivers/gpu/drm/vc4/vc4_plane.c
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+++ b/drivers/gpu/drm/vc4/vc4_plane.c
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@@ -555,8 +555,11 @@ static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state)
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static void vc4_write_tpz(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
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{
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+ struct vc4_dev *vc4 = to_vc4_dev(vc4_state->base.plane->dev);
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u32 scale, recip;
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+ WARN_ON_ONCE(vc4->gen > VC4_GEN_6);
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+
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scale = src / dst;
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/* The specs note that while the reciprocal would be defined
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@@ -581,10 +584,13 @@ static void vc4_write_tpz(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
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static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst, u32 xy, int channel, int chroma_offset)
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{
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+ struct vc4_dev *vc4 = to_vc4_dev(vc4_state->base.plane->dev);
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u32 scale = src / dst;
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s32 offset, offset2;
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s32 phase;
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+ WARN_ON_ONCE(vc4->gen > VC4_GEN_6);
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+
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/* Start the phase at 1/2 pixel from the 1st pixel at src_x.
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1/4 pixel for YUV, plus the offset for chroma siting */
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if (channel) {
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@@ -801,8 +807,11 @@ static size_t vc6_upm_size(const struct drm_plane_state *state,
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static void vc4_write_scaling_parameters(struct drm_plane_state *state,
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int channel)
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{
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+ struct vc4_dev *vc4 = to_vc4_dev(state->plane->dev);
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struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
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+ WARN_ON_ONCE(vc4->gen > VC4_GEN_6);
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+
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/* Ch0 H-PPF Word 0: Scaling Parameters */
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if (vc4_state->x_scaling[channel] == VC4_SCALING_PPF) {
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vc4_write_ppf(vc4_state,
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@@ -1040,6 +1049,11 @@ static const u32 colorspace_coeffs[2][DRM_COLOR_ENCODING_MAX][3] = {
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static u32 vc4_hvs4_get_alpha_blend_mode(struct drm_plane_state *state)
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{
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+ struct drm_device *dev = state->state->dev;
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+ struct vc4_dev *vc4 = to_vc4_dev(dev);
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+
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+ WARN_ON_ONCE(vc4->gen != VC4_GEN_4);
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+
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if (!state->fb->format->has_alpha)
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return VC4_SET_FIELD(SCALER_POS2_ALPHA_MODE_FIXED,
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SCALER_POS2_ALPHA_MODE);
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@@ -1061,6 +1075,11 @@ static u32 vc4_hvs4_get_alpha_blend_mode(struct drm_plane_state *state)
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static u32 vc4_hvs5_get_alpha_blend_mode(struct drm_plane_state *state)
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{
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+ struct drm_device *dev = state->state->dev;
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+ struct vc4_dev *vc4 = to_vc4_dev(dev);
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+
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+ WARN_ON_ONCE(vc4->gen != VC4_GEN_5 && vc4->gen != VC4_GEN_6);
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+
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if (!state->fb->format->has_alpha)
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return VC4_SET_FIELD(SCALER5_CTL2_ALPHA_MODE_FIXED,
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SCALER5_CTL2_ALPHA_MODE);
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--
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2.42.0
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