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Use teltonika uboot for RUTX
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Ycarus (Yannick Chabanois)
parent
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commit
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7338 changed files with 1833685 additions and 0 deletions
379
6.1/package/boot/uboot-ipq40xx/src/post/board/lwmon5/gdc.c
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379
6.1/package/boot/uboot-ipq40xx/src/post/board/lwmon5/gdc.c
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@ -0,0 +1,379 @@
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/*
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* (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com
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*
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* Developed for DENX Software Engineering GmbH
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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/* This test attempts to verify board GDC. A scratch register tested, then
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* simple memory test (get_ram_size()) run over GDC memory.
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*/
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#include <post.h>
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#include <watchdog.h>
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#include <asm/io.h>
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#include <video.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define GDC_SCRATCH_REG 0xC1FF8044
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#define GDC_VERSION_REG 0xC1FF8084
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#define GDC_HOST_BASE 0xC1FC0000
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#define GDC_RAM_START 0xC0000000
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#define GDC_RAM_END (GDC_HOST_BASE - 1)
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#define GDC_RAM_SIZE (GDC_RAM_END - GDC_RAM_START)
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#if CONFIG_POST & CONFIG_SYS_POST_BSPEC4
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const static unsigned long pattern[] = {
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0xffffffff,
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0xaaaaaaaa,
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0xcccccccc,
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0xf0f0f0f0,
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0xff00ff00,
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0xffff0000,
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0x0000ffff,
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0x00ff00ff,
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0x0f0f0f0f,
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0x33333333,
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0x55555555,
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0x00000000
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};
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const static unsigned long otherpattern = 0x01234567;
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/* test write/read og a given LIME Register */
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static int gdc_test_reg_one(uint value)
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{
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uint read_value;
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/* write test pattern */
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out_be32((void *)GDC_SCRATCH_REG, value);
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/* read other location (protect against data lines capacity) */
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in_be32((void *)GDC_RAM_START);
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/* verify test pattern */
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read_value = in_be32((void *)GDC_SCRATCH_REG);
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if (read_value != value) {
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post_log("GDC SCRATCH test failed write %08X, read %08X\n",
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value, read_value);
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}
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return (read_value != value);
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}
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/* test with a given static 32 bit pattern in a given memory addressrange */
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static int gdc_post_test1(ulong *start, ulong size, ulong val)
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{
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int ret = 0;
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ulong i = 0;
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ulong *mem = start;
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ulong readback;
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for (i = 0; i < size / sizeof(ulong); i++) {
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mem[i] = val;
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if (i % 1024 == 0)
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WATCHDOG_RESET();
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}
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for (i = 0; i < size / sizeof(ulong); i++) {
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readback = mem[i];
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if (readback != val) {
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post_log("GDC Memory error at %08x, "
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"wrote %08x, read %08x !\n",
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mem + i, val, readback);
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ret = -1;
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break;
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}
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if (i % 1024 == 0)
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WATCHDOG_RESET();
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}
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return ret;
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}
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/* test with dynamic 32 bit pattern in a given memory addressrange */
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static int gdc_post_test2(ulong *start, ulong size)
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{
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int ret = 0;
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ulong i = 0;
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ulong *mem = start;
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ulong readback;
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for (i = 0; i < size / sizeof(ulong); i++) {
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mem[i] = 1 << (i % 32);
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if (i % 1024 == 0)
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WATCHDOG_RESET();
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}
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for (i = 0; i < size / sizeof(ulong); i++) {
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readback = mem[i];
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if (readback != 1 << (i % 32)) {
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post_log("GDC Memory error at %08x, "
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"wrote %08x, read %08x !\n",
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mem + i, 1 << (i % 32), readback);
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ret = -1;
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break;
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}
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if (i % 1024 == 0)
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WATCHDOG_RESET();
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}
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return ret;
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}
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/* test with dynamic 32 bit pattern in a given memory addressrange */
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static int gdc_post_test3(ulong *start, ulong size)
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{
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int ret = 0;
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ulong i = 0;
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ulong *mem = start;
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ulong readback;
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for (i = 0; i < size / sizeof(ulong); i++) {
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mem[i] = i;
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if (i % 1024 == 0)
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WATCHDOG_RESET();
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}
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for (i = 0; i < size / sizeof(ulong); i++) {
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readback = mem[i];
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if (readback != i) {
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post_log("GDC Memory error at %08x, "
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"wrote %08x, read %08x !\n",
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mem + i, i, readback);
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ret = -1;
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break;
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}
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if (i % 1024 == 0)
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WATCHDOG_RESET();
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}
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return ret;
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}
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/* test with dynamic 32 bit pattern in a given memory addressrange */
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static int gdc_post_test4(ulong *start, ulong size)
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{
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int ret = 0;
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ulong i = 0;
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ulong *mem = start;
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ulong readback;
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for (i = 0; i < size / sizeof(ulong); i++) {
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mem[i] = ~i;
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if (i % 1024 == 0)
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WATCHDOG_RESET();
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}
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for (i = 0; i < size / sizeof(ulong); i++) {
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readback = mem[i];
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if (readback != ~i) {
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post_log("GDC Memory error at %08x, "
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"wrote %08x, read %08x !\n",
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mem + i, ~i, readback);
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ret = -1;
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break;
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}
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if (i % 1024 == 0)
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WATCHDOG_RESET();
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}
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return ret;
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}
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/* do some patterntests in a given addressrange */
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int gdc_mem_test(ulong *start, ulong size)
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{
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int ret = 0;
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/*
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* check addressrange and do different static and dynamic
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* pattern tests with it.
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*/
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if (((void *)start) + size <= (void *)GDC_RAM_END) {
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if (ret == 0)
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ret = gdc_post_test1(start, size, 0x00000000);
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if (ret == 0)
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ret = gdc_post_test1(start, size, 0xffffffff);
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if (ret == 0)
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ret = gdc_post_test1(start, size, 0x55555555);
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if (ret == 0)
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ret = gdc_post_test1(start, size, 0xaaaaaaaa);
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if (ret == 0)
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ret = gdc_post_test2(start, size);
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if (ret == 0)
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ret = gdc_post_test3(start, size);
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if (ret == 0)
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ret = gdc_post_test4(start, size);
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}
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return ret;
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}
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/* test function of gdc memory addresslines*/
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static int gdc_post_addrline(ulong *address, ulong *base, ulong size)
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{
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ulong *target;
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ulong *end;
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ulong readback = 0;
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ulong xor = 0;
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int ret = 0;
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end = (ulong *)((ulong)base + size);
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for (xor = sizeof(long); xor > 0; xor <<= 1) {
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target = (ulong *)((ulong)address ^ xor);
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if ((target >= base) && (target < end)) {
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*address = ~*target;
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readback = *target;
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}
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if (readback == *address) {
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post_log("GDC Memory (address line) error at %08x"
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"XOR value %08x !\n",
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address, target , xor);
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ret = -1;
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break;
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}
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}
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return ret;
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}
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static int gdc_post_dataline(ulong *address)
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{
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unsigned long temp32 = 0;
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int i = 0;
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int ret = 0;
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for (i = 0; i < ARRAY_SIZE(pattern); i++) {
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*address = pattern[i];
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/*
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* Put a different pattern on the data lines: otherwise they
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* may float long enough to read back what we wrote.
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*/
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*(address + 1) = otherpattern;
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temp32 = *address;
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if (temp32 != pattern[i]){
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post_log("GDC Memory (date line) error at %08x, "
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"wrote %08x, read %08x !\n",
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address, pattern[i], temp32);
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ret = 1;
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}
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}
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return ret;
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}
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/* Verify GDC, get memory size, verify GDC memory */
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int gdc_post_test(int flags)
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{
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uint old_value;
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int i = 0;
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int ret = 0;
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post_log("\n");
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old_value = in_be32((void *)GDC_SCRATCH_REG);
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/*
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* GPIOC2 register behaviour: the LIME graphics processor has a
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* maximum of 5 GPIO ports that can be used in this hardware
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* configuration. Thus only the bits for these 5 GPIOs can be
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* activated in the GPIOC2 register. All other bits will always be
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* read as zero.
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*/
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if (gdc_test_reg_one(0x00150015))
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ret = 1;
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if (gdc_test_reg_one(0x000A000A))
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ret = 1;
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out_be32((void *)GDC_SCRATCH_REG, old_value);
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old_value = in_be32((void *)GDC_VERSION_REG);
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post_log("GDC chip version %u.%u, year %04X\n",
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(old_value >> 8) & 0xFF, old_value & 0xFF,
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(old_value >> 16) & 0xFFFF);
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old_value = get_ram_size((void *)GDC_RAM_START,
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0x02000000);
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debug("GDC RAM size (ist): %d bytes\n", old_value);
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debug("GDC RAM size (soll): %d bytes\n", GDC_RAM_SIZE);
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post_log("GDC RAM size: %d bytes\n", old_value);
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/* Test SDRAM datalines */
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if (gdc_post_dataline((ulong *)GDC_RAM_START)) {
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ret = 1;
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goto out;
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}
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WATCHDOG_RESET();
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/* Test SDRAM adresslines */
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if (gdc_post_addrline((ulong *)GDC_RAM_START,
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(ulong *)GDC_RAM_START, GDC_RAM_SIZE)) {
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ret = 1;
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goto out;
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}
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WATCHDOG_RESET();
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if (gdc_post_addrline((ulong *)GDC_RAM_END - sizeof(long),
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(ulong *)GDC_RAM_START, GDC_RAM_SIZE)) {
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ret = 1;
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goto out;
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}
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WATCHDOG_RESET();
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/* memory pattern test */
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debug("GDC Memory test (flags %8x:%8x)\n", flags,
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POST_SLOWTEST | POST_MANUAL);
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if (flags & POST_MANUAL) {
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debug("Full memory test\n");
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if (gdc_mem_test((ulong *)GDC_RAM_START, GDC_RAM_SIZE)) {
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ret = 1;
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goto out;
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}
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/* load splashscreen again */
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} else {
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debug("smart memory test\n");
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for (i = 0; i < (GDC_RAM_SIZE >> 20) && ret == 0; i++) {
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if (ret == 0)
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ret = gdc_mem_test((ulong *)(GDC_RAM_START +
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(i << 20)),
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0x800);
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if (ret == 0)
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ret = gdc_mem_test((ulong *)(GDC_RAM_START +
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(i << 20) + 0xff800),
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0x800);
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}
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}
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WATCHDOG_RESET();
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out:
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return ret;
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}
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#endif /* CONFIG_POST & CONFIG_SYS_POST_BSPEC4 */
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