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Add patches for BPI-R2

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Ycarus (Yannick Chabanois) 2020-04-20 09:45:14 +02:00
parent b1be088d7f
commit 8b04e8ac65
23 changed files with 2179 additions and 15 deletions
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77
root/target/linux/mediatek/patches-5.4/0171-dts-mt7623-add-mali450.patch Normal file
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@ -0,0 +1,77 @@
From 6468d187f12604f38f0a3acde430fdc5c5390771 Mon Sep 17 00:00:00 2001
From: Ryder Lee <ryder.lee@mediatek.com>
Date: Tue, 23 Jul 2019 11:32:50 +0800
Subject: [PATCH] arm: dts: mt7623: add Mali-450 device nodes
Add nodes for Mali-450 and iommu larb3.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
---
arch/arm/boot/dts/mt7623.dtsi | 39 ++++++++++++++++++++++++++++++++++-
1 file changed, 38 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index 8d0807fd9460..f7905561b30e 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -3,6 +3,7 @@
* Copyright (c) 2017-2018 MediaTek Inc.
* Author: John Crispin <john@phrozen.org>
* Sean Wang <sean.wang@mediatek.com>
+ * Ryder Lee <ryder.lee@mediatek.com>
*
*/
@@ -371,7 +372,7 @@
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_M4U>;
clock-names = "bclk";
- mediatek,larbs = <&larb0 &larb1 &larb2>;
+ mediatek,larbs = <&larb0 &larb1 &larb2 &larb3>;
#iommu-cells = <1>;
};
@@ -794,6 +795,42 @@
#reset-cells = <1>;
};
+ larb3: larb@13010000 {
+ compatible = "mediatek,mt7623-smi-larb",
+ "mediatek,mt2701-smi-larb";
+ reg = <0 0x13010000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ mediatek,larb-id = <3>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "apb", "smi";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;
+ };
+
+ mali: gpu@13040000 {
+ compatible = "mediatek,mt7623-mali", "arm,mali-450";
+ reg = <0 0x13040000 0 0x30000>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 178 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
+ "ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3",
+ "pp";
+ clocks = <&topckgen CLK_TOP_MMPLL>,
+ <&g3dsys CLK_G3DSYS_CORE>;
+ clock-names = "bus", "core";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;
+ mediatek,larb = <&larb3>;
+ resets = <&g3dsys MT2701_G3DSYS_CORE_RST>;
+ };
+
mmsys: syscon@14000000 {
compatible = "mediatek,mt7623-mmsys",
"mediatek,mt2701-mmsys",