mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-02-14 12:21:53 +00:00
Fix z8102ax kernel 6.10 compilation
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
aa572cfc21
commit
c84e4b5ef4
49 changed files with 328 additions and 10899 deletions
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@ -8376,5 +8376,22 @@ CONFIG_USB_DEFAULT_AUTHORIZATION_MODE=1
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# CONFIG_LEDS_KTD202X is not set
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# CONFIG_LEDS_NCP5623 is not set
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# CONFIG_AF8133J is not set
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# CONFIG_PHY_MTK_MIPI_CSI_0_5 is not set
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# CONFIG_FSCACHE is not set
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# CONFIG_TEST_FPU is not set
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# CONFIG_NET_DSA_TAG_VSC73XX_8021Q is not set
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# CONFIG_PCI_PWRCTL_PWRSEQ is not set
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# CONFIG_NET_AIROHA is not set
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# CONFIG_NET_VENDOR_META is not set
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# CONFIG_SPI_CH341 is not set
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# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set
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# CONFIG_GPIO_VIRTUSER is not set
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# CONFIG_POWER_SEQUENCING is not set
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# CONFIG_SENSORS_MP2891 is not set
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# CONFIG_SENSORS_MP2993 is not set
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# CONFIG_SENSORS_MP5920 is not set
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# CONFIG_SENSORS_MP9941 is not set
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# CONFIG_SENSORS_SPD5118 is not set
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# CONFIG_CZNIC_PLATFORMS is not set
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# CONFIG_QCOM_PD_MAPPER is not set
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# CONFIG_PWM_GPIO is not set
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# CONFIG_FSCACHE is not set
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@ -1,64 +0,0 @@
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From 880d1311335120f64447ca9d11933872d734e19a Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Mon, 27 Mar 2023 18:41:54 +0100
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Subject: [PATCH] generic: pcs-mtk-lynxi: add hack to use 2500Base-X without AN
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Using 2500Base-T SFP modules e.g. on the BananaPi R3 requires manually
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disabling auto-negotiation, e.g. using ethtool. While a proper fix
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using SFP quirks is being discussed upstream, bring a work-around to
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restore user experience to what it was before the switch to the
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dedicated SGMII PCS driver.
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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--- a/drivers/net/pcs/pcs-mtk-lynxi.c
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+++ b/drivers/net/pcs/pcs-mtk-lynxi.c
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@@ -114,14 +114,23 @@ static void mtk_pcs_lynxi_get_state(stru
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struct phylink_link_state *state)
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{
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struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
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- unsigned int bm, adv;
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+ unsigned int bm, bmsr, adv;
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/* Read the BMSR and LPA */
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regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &bm);
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- regmap_read(mpcs->regmap, SGMSYS_PCS_ADVERTISE, &adv);
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+ bmsr = FIELD_GET(SGMII_BMSR, bm);
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+
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+ if (state->interface == PHY_INTERFACE_MODE_2500BASEX) {
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+ state->link = !!(bmsr & BMSR_LSTATUS);
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+ state->an_complete = !!(bmsr & BMSR_ANEGCOMPLETE);
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+ state->speed = SPEED_2500;
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+ state->duplex = DUPLEX_FULL;
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+
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+ return;
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+ }
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- phylink_mii_c22_pcs_decode_state(state, FIELD_GET(SGMII_BMSR, bm),
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- FIELD_GET(SGMII_LPA, adv));
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+ regmap_read(mpcs->regmap, SGMSYS_PCS_ADVERTISE, &adv);
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+ phylink_mii_c22_pcs_decode_state(state, bmsr, FIELD_GET(SGMII_LPA, adv));
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}
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static void mtk_sgmii_reset(struct mtk_pcs_lynxi *mpcs)
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@@ -142,7 +151,7 @@ static int mtk_pcs_lynxi_config(struct p
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{
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struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
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bool mode_changed = false, changed;
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- unsigned int rgc3, sgm_mode, bmcr;
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+ unsigned int rgc3, sgm_mode, bmcr = 0;
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int advertise, link_timer;
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advertise = phylink_mii_c22_pcs_encode_advertisement(interface,
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@@ -165,9 +174,8 @@ static int mtk_pcs_lynxi_config(struct p
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if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
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if (interface == PHY_INTERFACE_MODE_SGMII)
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sgm_mode |= SGMII_SPEED_DUPLEX_AN;
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- bmcr = BMCR_ANENABLE;
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- } else {
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- bmcr = 0;
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+ if (interface != PHY_INTERFACE_MODE_2500BASEX)
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+ bmcr = BMCR_ANENABLE;
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}
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if (mpcs->interface != interface) {
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@ -1,81 +0,0 @@
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From patchwork Thu Feb 6 17:19:41 2020
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Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
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X-Patchwork-Id: 1234465
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Date: Thu, 6 Feb 2020 19:19:41 +0200
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From: Daniel Golle <daniel@makrotopia.org>
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To: linux-mtd@lists.infradead.org
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Subject: [PATCH v2] mtd: spi-nor: Add support for xt25f128b chip
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Message-ID: <20200206171941.GA2398@makrotopia.org>
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MIME-Version: 1.0
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Content-Disposition: inline
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List-Subscribe: <http://lists.infradead.org/mailman/listinfo/linux-mtd>,
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<mailto:linux-mtd-request@lists.infradead.org?subject=subscribe>
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Cc: Eitan Cohen <eitan@neot-semadar.com>, Piotr Dymacz <pepe2k@gmail.com>,
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Tudor Ambarus <tudor.ambarus@microchip.com>
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Sender: "linux-mtd" <linux-mtd-bounces@lists.infradead.org>
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Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org
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Add XT25F128B made by XTX Technology (Shenzhen) Limited.
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This chip supports dual and quad read and uniform 4K-byte erase.
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Verified on Teltonika RUT955 which comes with XT25F128B in recent
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versions of the device.
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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---
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drivers/mtd/spi-nor/spi-nor.c | 4 ++++
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1 file changed, 4 insertions(+)
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--- a/drivers/mtd/spi-nor/Makefile
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+++ b/drivers/mtd/spi-nor/Makefile
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@@ -17,6 +17,7 @@ spi-nor-objs += sst.o
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spi-nor-objs += winbond.o
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spi-nor-objs += xilinx.o
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spi-nor-objs += xmc.o
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+spi-nor-objs += xtx.o
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spi-nor-$(CONFIG_DEBUG_FS) += debugfs.o
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obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o
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--- /dev/null
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+++ b/drivers/mtd/spi-nor/xtx.c
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@@ -0,0 +1,17 @@
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+// SPDX-License-Identifier: GPL-2.0
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+#include <linux/mtd/spi-nor.h>
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+
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+#include "core.h"
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+
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+static const struct flash_info xtx_parts[] = {
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+ /* XTX Technology (Shenzhen) Limited */
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+ { "xt25f128b", INFO(0x0B4018, 0, 64 * 1024, 256)
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+ NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
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+ SPI_NOR_QUAD_READ) },
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+};
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+
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+const struct spi_nor_manufacturer spi_nor_xtx = {
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+ .name = "xtx",
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+ .parts = xtx_parts,
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+ .nparts = ARRAY_SIZE(xtx_parts),
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+};
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--- a/drivers/mtd/spi-nor/core.c
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+++ b/drivers/mtd/spi-nor/core.c
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@@ -2017,6 +2017,7 @@ static const struct spi_nor_manufacturer
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&spi_nor_winbond,
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&spi_nor_xilinx,
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&spi_nor_xmc,
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+ &spi_nor_xtx,
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};
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static const struct flash_info spi_nor_generic_flash = {
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--- a/drivers/mtd/spi-nor/core.h
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+++ b/drivers/mtd/spi-nor/core.h
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@@ -647,6 +647,7 @@ extern const struct spi_nor_manufacturer
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extern const struct spi_nor_manufacturer spi_nor_winbond;
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extern const struct spi_nor_manufacturer spi_nor_xilinx;
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extern const struct spi_nor_manufacturer spi_nor_xmc;
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+extern const struct spi_nor_manufacturer spi_nor_xtx;
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extern const struct attribute_group *spi_nor_sysfs_groups[];
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@ -1,98 +0,0 @@
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From: Daniel Golle <daniel@makrotopia.org>
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Subject: ubi: auto-attach mtd device named "ubi" or "data" on boot
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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drivers/mtd/ubi/build.c | 36 ++++++++++++++++++++++++++++++++++++
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1 file changed, 36 insertions(+)
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--- a/drivers/mtd/ubi/build.c
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+++ b/drivers/mtd/ubi/build.c
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@@ -1258,6 +1258,74 @@ static struct mtd_notifier ubi_mtd_notif
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.remove = ubi_notify_remove,
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};
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+
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+/*
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+ * This function tries attaching mtd partitions named either "ubi" or "data"
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+ * during boot.
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+ */
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+static void __init ubi_auto_attach(void)
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+{
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+ int err;
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+ struct mtd_info *mtd;
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+ loff_t offset = 0;
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+ size_t len;
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+ char magic[4];
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+
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+ /* try attaching mtd device named "ubi" or "data" */
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+ mtd = open_mtd_device("ubi");
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+ if (IS_ERR(mtd))
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+ mtd = open_mtd_device("data");
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+
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+ if (IS_ERR(mtd))
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+ return;
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+
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+ /* get the first not bad block */
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+ if (mtd_can_have_bb(mtd))
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+ while (mtd_block_isbad(mtd, offset)) {
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+ offset += mtd->erasesize;
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+
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+ if (offset > mtd->size) {
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+ pr_err("UBI error: Failed to find a non-bad "
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+ "block on mtd%d\n", mtd->index);
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+ goto cleanup;
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+ }
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+ }
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+
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+ /* check if the read from flash was successful */
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+ err = mtd_read(mtd, offset, 4, &len, (void *) magic);
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+ if ((err && !mtd_is_bitflip(err)) || len != 4) {
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+ pr_err("UBI error: unable to read from mtd%d\n", mtd->index);
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+ goto cleanup;
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+ }
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+
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+ /* check for a valid ubi magic */
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+ if (strncmp(magic, "UBI#", 4)) {
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+ pr_err("UBI error: no valid UBI magic found inside mtd%d\n", mtd->index);
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+ goto cleanup;
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+ }
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+
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+ /* don't auto-add media types where UBI doesn't makes sense */
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+ if (mtd->type != MTD_NANDFLASH &&
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+ mtd->type != MTD_NORFLASH &&
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+ mtd->type != MTD_DATAFLASH &&
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+ mtd->type != MTD_MLCNANDFLASH)
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+ goto cleanup;
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+
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+ mutex_lock(&ubi_devices_mutex);
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+ pr_notice("UBI: auto-attach mtd%d\n", mtd->index);
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+ err = ubi_attach_mtd_dev(mtd, UBI_DEV_NUM_AUTO, 0, 0, false);
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+ mutex_unlock(&ubi_devices_mutex);
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+ if (err < 0) {
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+ pr_err("UBI error: cannot attach mtd%d\n", mtd->index);
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+ goto cleanup;
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+ }
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+
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+ return;
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+
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+cleanup:
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+ put_mtd_device(mtd);
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+}
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+
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static int __init ubi_init_attach(void)
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{
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int err, i, k;
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@@ -1308,6 +1376,12 @@ static int __init ubi_init_attach(void)
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}
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}
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+ /* auto-attach mtd devices only if built-in to the kernel and no ubi.mtd
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+ * parameter was given */
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+ if (IS_ENABLED(CONFIG_MTD_ROOTFS_ROOT_DEV) &&
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+ !ubi_is_module() && !mtd_devs)
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+ ubi_auto_attach();
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+
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return 0;
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out_detach:
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File diff suppressed because it is too large
Load diff
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@ -1,936 +0,0 @@
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From d5e337e7aecc2e1cc9e96768062610adb95f8f72 Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Tue, 12 Dec 2023 03:51:14 +0000
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Subject: [PATCH] net: ethernet: mtk_eth_soc: add paths and SerDes modes for
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MT7988
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MT7988 comes with a built-in 2.5G PHY as well as SerDes lanes to
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connect external PHYs or transceivers in USXGMII, 10GBase-R, 5GBase-R,
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2500Base-X, 1000Base-X and Cisco SGMII interface modes.
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Implement support for configuring for the new paths to SerDes interfaces
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and the internal 2.5G PHY.
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|
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Add USXGMII PCS driver for 10GBase-R, 5GBase-R and USXGMII mode, and
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setup the new PHYA on MT7988 to access the also still existing old
|
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LynxI PCS for 1000Base-X, 2500Base-X and Cisco SGMII PCS interface
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modes.
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||||
|
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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drivers/net/ethernet/mediatek/mtk_eth_path.c | 122 +++++++-
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drivers/net/ethernet/mediatek/mtk_eth_soc.c | 292 +++++++++++++++++--
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drivers/net/ethernet/mediatek/mtk_eth_soc.h | 107 ++++++-
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3 files changed, 470 insertions(+), 51 deletions(-)
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|
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--- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
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@@ -31,10 +31,20 @@ static const char *mtk_eth_path_name(u64
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return "gmac2_rgmii";
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case MTK_ETH_PATH_GMAC2_SGMII:
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return "gmac2_sgmii";
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+ case MTK_ETH_PATH_GMAC2_2P5GPHY:
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+ return "gmac2_2p5gphy";
|
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case MTK_ETH_PATH_GMAC2_GEPHY:
|
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return "gmac2_gephy";
|
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+ case MTK_ETH_PATH_GMAC3_SGMII:
|
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+ return "gmac3_sgmii";
|
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case MTK_ETH_PATH_GDM1_ESW:
|
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return "gdm1_esw";
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+ case MTK_ETH_PATH_GMAC1_USXGMII:
|
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+ return "gmac1_usxgmii";
|
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+ case MTK_ETH_PATH_GMAC2_USXGMII:
|
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+ return "gmac2_usxgmii";
|
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+ case MTK_ETH_PATH_GMAC3_USXGMII:
|
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+ return "gmac3_usxgmii";
|
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default:
|
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return "unknown path";
|
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}
|
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@@ -127,6 +137,27 @@ static int set_mux_u3_gmac2_to_qphy(stru
|
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return 0;
|
||||
}
|
||||
|
||||
+static int set_mux_gmac2_to_2p5gphy(struct mtk_eth *eth, u64 path)
|
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+{
|
||||
+ int ret;
|
||||
+
|
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+ if (path == MTK_ETH_PATH_GMAC2_2P5GPHY) {
|
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+ ret = regmap_clear_bits(eth->ethsys, ETHSYS_SYSCFG0, SYSCFG0_SGMII_GMAC2_V2);
|
||||
+ if (ret)
|
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+ return ret;
|
||||
+
|
||||
+ /* Setup mux to 2p5g PHY */
|
||||
+ ret = regmap_clear_bits(eth->infra, TOP_MISC_NETSYS_PCS_MUX, MUX_G2_USXGMII_SEL);
|
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+ if (ret)
|
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+ return ret;
|
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+
|
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+ dev_dbg(eth->dev, "path %s in %s updated\n",
|
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+ mtk_eth_path_name(path), __func__);
|
||||
+ }
|
||||
+
|
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+ return 0;
|
||||
+}
|
||||
+
|
||||
static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, u64 path)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
@@ -165,7 +196,48 @@ static int set_mux_gmac1_gmac2_to_sgmii_
|
||||
return 0;
|
||||
}
|
||||
|
||||
-static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, u64 path)
|
||||
+static int set_mux_gmac123_to_usxgmii(struct mtk_eth *eth, u64 path)
|
||||
+{
|
||||
+ unsigned int val = 0;
|
||||
+ bool updated = true;
|
||||
+ int mac_id = 0;
|
||||
+
|
||||
+ /* Disable SYSCFG1 SGMII */
|
||||
+ regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
|
||||
+
|
||||
+ switch (path) {
|
||||
+ case MTK_ETH_PATH_GMAC1_USXGMII:
|
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+ val &= ~(u32)SYSCFG0_SGMII_GMAC1_V2;
|
||||
+ mac_id = MTK_GMAC1_ID;
|
||||
+ break;
|
||||
+ case MTK_ETH_PATH_GMAC2_USXGMII:
|
||||
+ val &= ~(u32)SYSCFG0_SGMII_GMAC2_V2;
|
||||
+ mac_id = MTK_GMAC2_ID;
|
||||
+ break;
|
||||
+ case MTK_ETH_PATH_GMAC3_USXGMII:
|
||||
+ val &= ~(u32)SYSCFG0_SGMII_GMAC3_V2;
|
||||
+ mac_id = MTK_GMAC3_ID;
|
||||
+ break;
|
||||
+ default:
|
||||
+ updated = false;
|
||||
+ };
|
||||
+
|
||||
+ if (updated) {
|
||||
+ regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0,
|
||||
+ SYSCFG0_SGMII_MASK, val);
|
||||
+
|
||||
+ if (mac_id == MTK_GMAC2_ID)
|
||||
+ regmap_set_bits(eth->infra, TOP_MISC_NETSYS_PCS_MUX,
|
||||
+ MUX_G2_USXGMII_SEL);
|
||||
+ }
|
||||
+
|
||||
+ dev_dbg(eth->dev, "path %s in %s updated = %d\n",
|
||||
+ mtk_eth_path_name(path), __func__, updated);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int set_mux_gmac123_to_gephy_sgmii(struct mtk_eth *eth, u64 path)
|
||||
{
|
||||
unsigned int val = 0;
|
||||
bool updated = true;
|
||||
@@ -182,6 +254,9 @@ static int set_mux_gmac12_to_gephy_sgmii
|
||||
case MTK_ETH_PATH_GMAC2_SGMII:
|
||||
val |= SYSCFG0_SGMII_GMAC2_V2;
|
||||
break;
|
||||
+ case MTK_ETH_PATH_GMAC3_SGMII:
|
||||
+ val |= SYSCFG0_SGMII_GMAC3_V2;
|
||||
+ break;
|
||||
default:
|
||||
updated = false;
|
||||
}
|
||||
@@ -210,13 +285,25 @@ static const struct mtk_eth_muxc mtk_eth
|
||||
.cap_bit = MTK_ETH_MUX_U3_GMAC2_TO_QPHY,
|
||||
.set_path = set_mux_u3_gmac2_to_qphy,
|
||||
}, {
|
||||
+ .name = "mux_gmac2_to_2p5gphy",
|
||||
+ .cap_bit = MTK_ETH_MUX_GMAC2_TO_2P5GPHY,
|
||||
+ .set_path = set_mux_gmac2_to_2p5gphy,
|
||||
+ }, {
|
||||
.name = "mux_gmac1_gmac2_to_sgmii_rgmii",
|
||||
.cap_bit = MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII,
|
||||
.set_path = set_mux_gmac1_gmac2_to_sgmii_rgmii,
|
||||
}, {
|
||||
.name = "mux_gmac12_to_gephy_sgmii",
|
||||
.cap_bit = MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII,
|
||||
- .set_path = set_mux_gmac12_to_gephy_sgmii,
|
||||
+ .set_path = set_mux_gmac123_to_gephy_sgmii,
|
||||
+ }, {
|
||||
+ .name = "mux_gmac123_to_gephy_sgmii",
|
||||
+ .cap_bit = MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII,
|
||||
+ .set_path = set_mux_gmac123_to_gephy_sgmii,
|
||||
+ }, {
|
||||
+ .name = "mux_gmac123_to_usxgmii",
|
||||
+ .cap_bit = MTK_ETH_MUX_GMAC123_TO_USXGMII,
|
||||
+ .set_path = set_mux_gmac123_to_usxgmii,
|
||||
},
|
||||
};
|
||||
|
||||
@@ -249,12 +336,39 @@ out:
|
||||
return err;
|
||||
}
|
||||
|
||||
+int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id)
|
||||
+{
|
||||
+ u64 path;
|
||||
+
|
||||
+ path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_USXGMII :
|
||||
+ (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_USXGMII :
|
||||
+ MTK_ETH_PATH_GMAC3_USXGMII;
|
||||
+
|
||||
+ /* Setup proper MUXes along the path */
|
||||
+ return mtk_eth_mux_setup(eth, path);
|
||||
+}
|
||||
+
|
||||
int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id)
|
||||
{
|
||||
u64 path;
|
||||
|
||||
- path = (mac_id == 0) ? MTK_ETH_PATH_GMAC1_SGMII :
|
||||
- MTK_ETH_PATH_GMAC2_SGMII;
|
||||
+ path = (mac_id == MTK_GMAC1_ID) ? MTK_ETH_PATH_GMAC1_SGMII :
|
||||
+ (mac_id == MTK_GMAC2_ID) ? MTK_ETH_PATH_GMAC2_SGMII :
|
||||
+ MTK_ETH_PATH_GMAC3_SGMII;
|
||||
+
|
||||
+ /* Setup proper MUXes along the path */
|
||||
+ return mtk_eth_mux_setup(eth, path);
|
||||
+}
|
||||
+
|
||||
+int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id)
|
||||
+{
|
||||
+ u64 path = 0;
|
||||
+
|
||||
+ if (mac_id == MTK_GMAC2_ID)
|
||||
+ path = MTK_ETH_PATH_GMAC2_2P5GPHY;
|
||||
+
|
||||
+ if (!path)
|
||||
+ return -EINVAL;
|
||||
|
||||
/* Setup proper MUXes along the path */
|
||||
return mtk_eth_mux_setup(eth, path);
|
||||
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
|
||||
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
|
||||
@@ -22,6 +22,8 @@
|
||||
#include <linux/pinctrl/devinfo.h>
|
||||
#include <linux/phylink.h>
|
||||
#include <linux/pcs/pcs-mtk-lynxi.h>
|
||||
+#include <linux/pcs/pcs-mtk-usxgmii.h>
|
||||
+#include <linux/phy/phy.h>
|
||||
#include <linux/jhash.h>
|
||||
#include <linux/bitfield.h>
|
||||
#include <net/dsa.h>
|
||||
@@ -261,12 +263,8 @@ static const char * const mtk_clks_sourc
|
||||
"ethwarp_wocpu2",
|
||||
"ethwarp_wocpu1",
|
||||
"ethwarp_wocpu0",
|
||||
- "top_usxgmii0_sel",
|
||||
- "top_usxgmii1_sel",
|
||||
"top_sgm0_sel",
|
||||
"top_sgm1_sel",
|
||||
- "top_xfi_phy0_xtal_sel",
|
||||
- "top_xfi_phy1_xtal_sel",
|
||||
"top_eth_gmii_sel",
|
||||
"top_eth_refck_50m_sel",
|
||||
"top_eth_sys_200m_sel",
|
||||
@@ -509,6 +507,30 @@ static void mtk_setup_bridge_switch(stru
|
||||
MTK_GSW_CFG);
|
||||
}
|
||||
|
||||
+static bool mtk_check_gmac23_idle(struct mtk_mac *mac)
|
||||
+{
|
||||
+ u32 mac_fsm, gdm_fsm;
|
||||
+
|
||||
+ mac_fsm = mtk_r32(mac->hw, MTK_MAC_FSM(mac->id));
|
||||
+
|
||||
+ switch (mac->id) {
|
||||
+ case MTK_GMAC2_ID:
|
||||
+ gdm_fsm = mtk_r32(mac->hw, MTK_FE_GDM2_FSM);
|
||||
+ break;
|
||||
+ case MTK_GMAC3_ID:
|
||||
+ gdm_fsm = mtk_r32(mac->hw, MTK_FE_GDM3_FSM);
|
||||
+ break;
|
||||
+ default:
|
||||
+ return true;
|
||||
+ };
|
||||
+
|
||||
+ if ((mac_fsm & 0xFFFF0000) == 0x01010000 &&
|
||||
+ (gdm_fsm & 0xFFFF0000) == 0x00000000)
|
||||
+ return true;
|
||||
+
|
||||
+ return false;
|
||||
+}
|
||||
+
|
||||
static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
|
||||
phy_interface_t interface)
|
||||
{
|
||||
@@ -517,6 +539,21 @@ static struct phylink_pcs *mtk_mac_selec
|
||||
struct mtk_eth *eth = mac->hw;
|
||||
unsigned int sid;
|
||||
|
||||
+ if (mtk_is_netsys_v3_or_greater(eth)) {
|
||||
+ switch (interface) {
|
||||
+ case PHY_INTERFACE_MODE_1000BASEX:
|
||||
+ case PHY_INTERFACE_MODE_2500BASEX:
|
||||
+ case PHY_INTERFACE_MODE_SGMII:
|
||||
+ return mac->sgmii_pcs;
|
||||
+ case PHY_INTERFACE_MODE_5GBASER:
|
||||
+ case PHY_INTERFACE_MODE_10GBASER:
|
||||
+ case PHY_INTERFACE_MODE_USXGMII:
|
||||
+ return mac->usxgmii_pcs;
|
||||
+ default:
|
||||
+ return NULL;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
if (interface == PHY_INTERFACE_MODE_SGMII ||
|
||||
phy_interface_mode_is_8023z(interface)) {
|
||||
sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
|
||||
@@ -568,7 +605,22 @@ static void mtk_mac_config(struct phylin
|
||||
goto init_err;
|
||||
}
|
||||
break;
|
||||
+ case PHY_INTERFACE_MODE_USXGMII:
|
||||
+ case PHY_INTERFACE_MODE_10GBASER:
|
||||
+ case PHY_INTERFACE_MODE_5GBASER:
|
||||
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) {
|
||||
+ err = mtk_gmac_usxgmii_path_setup(eth, mac->id);
|
||||
+ if (err)
|
||||
+ goto init_err;
|
||||
+ }
|
||||
+ break;
|
||||
case PHY_INTERFACE_MODE_INTERNAL:
|
||||
+ if (mac->id == MTK_GMAC2_ID &&
|
||||
+ MTK_HAS_CAPS(eth->soc->caps, MTK_2P5GPHY)) {
|
||||
+ err = mtk_gmac_2p5gphy_path_setup(eth, mac->id);
|
||||
+ if (err)
|
||||
+ goto init_err;
|
||||
+ }
|
||||
break;
|
||||
default:
|
||||
goto err_phy;
|
||||
@@ -615,8 +667,6 @@ static void mtk_mac_config(struct phylin
|
||||
val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
|
||||
val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
|
||||
regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
|
||||
-
|
||||
- mac->interface = state->interface;
|
||||
}
|
||||
|
||||
/* SGMII */
|
||||
@@ -633,21 +683,40 @@ static void mtk_mac_config(struct phylin
|
||||
|
||||
/* Save the syscfg0 value for mac_finish */
|
||||
mac->syscfg0 = val;
|
||||
- } else if (phylink_autoneg_inband(mode)) {
|
||||
+ } else if (state->interface != PHY_INTERFACE_MODE_USXGMII &&
|
||||
+ state->interface != PHY_INTERFACE_MODE_10GBASER &&
|
||||
+ state->interface != PHY_INTERFACE_MODE_5GBASER &&
|
||||
+ phylink_autoneg_inband(mode)) {
|
||||
dev_err(eth->dev,
|
||||
- "In-band mode not supported in non SGMII mode!\n");
|
||||
+ "In-band mode not supported in non-SerDes modes!\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Setup gmac */
|
||||
- if (mtk_is_netsys_v3_or_greater(eth) &&
|
||||
- mac->interface == PHY_INTERFACE_MODE_INTERNAL) {
|
||||
- mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id));
|
||||
- mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));
|
||||
+ if (mtk_is_netsys_v3_or_greater(eth)) {
|
||||
+ if (mtk_interface_mode_is_xgmii(state->interface)) {
|
||||
+ mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id));
|
||||
+ mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id));
|
||||
+
|
||||
+ if (mac->id == MTK_GMAC1_ID)
|
||||
+ mtk_setup_bridge_switch(eth);
|
||||
+ } else {
|
||||
+ mtk_w32(eth, 0, MTK_GDMA_EG_CTRL(mac->id));
|
||||
|
||||
- mtk_setup_bridge_switch(eth);
|
||||
+ /* FIXME: In current hardware design, we have to reset FE
|
||||
+ * when swtiching XGDM to GDM. Therefore, here trigger an SER
|
||||
+ * to let GDM go back to the initial state.
|
||||
+ */
|
||||
+ if ((mtk_interface_mode_is_xgmii(mac->interface) ||
|
||||
+ mac->interface == PHY_INTERFACE_MODE_NA) &&
|
||||
+ !mtk_check_gmac23_idle(mac) &&
|
||||
+ !test_bit(MTK_RESETTING, ð->state))
|
||||
+ schedule_work(ð->pending_work);
|
||||
+ }
|
||||
}
|
||||
|
||||
+ mac->interface = state->interface;
|
||||
+
|
||||
return;
|
||||
|
||||
err_phy:
|
||||
@@ -660,6 +729,18 @@ init_err:
|
||||
mac->id, phy_modes(state->interface), err);
|
||||
}
|
||||
|
||||
+static int mtk_mac_prepare(struct phylink_config *config, unsigned int mode,
|
||||
+ phy_interface_t interface)
|
||||
+{
|
||||
+ struct mtk_mac *mac = container_of(config, struct mtk_mac,
|
||||
+ phylink_config);
|
||||
+
|
||||
+ if (mac->pextp && mac->interface != interface)
|
||||
+ phy_reset(mac->pextp);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int mtk_mac_finish(struct phylink_config *config, unsigned int mode,
|
||||
phy_interface_t interface)
|
||||
{
|
||||
@@ -668,6 +749,10 @@ static int mtk_mac_finish(struct phylink
|
||||
struct mtk_eth *eth = mac->hw;
|
||||
u32 mcr_cur, mcr_new;
|
||||
|
||||
+ /* Setup PMA/PMD */
|
||||
+ if (mac->pextp)
|
||||
+ phy_set_mode_ext(mac->pextp, PHY_MODE_ETHERNET, interface);
|
||||
+
|
||||
/* Enable SGMII */
|
||||
if (interface == PHY_INTERFACE_MODE_SGMII ||
|
||||
phy_interface_mode_is_8023z(interface))
|
||||
@@ -692,10 +777,14 @@ static void mtk_mac_link_down(struct phy
|
||||
{
|
||||
struct mtk_mac *mac = container_of(config, struct mtk_mac,
|
||||
phylink_config);
|
||||
- u32 mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
|
||||
|
||||
- mcr &= ~(MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK);
|
||||
- mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
|
||||
+ if (!mtk_interface_mode_is_xgmii(interface)) {
|
||||
+ mtk_m32(mac->hw, MAC_MCR_TX_EN | MAC_MCR_RX_EN | MAC_MCR_FORCE_LINK, 0, MTK_MAC_MCR(mac->id));
|
||||
+ if (mtk_is_netsys_v3_or_greater(mac->hw))
|
||||
+ mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), 0, MTK_XGMAC_STS(mac->id));
|
||||
+ } else if (mtk_is_netsys_v3_or_greater(mac->hw) && mac->id != MTK_GMAC1_ID) {
|
||||
+ mtk_m32(mac->hw, XMAC_MCR_TRX_DISABLE, XMAC_MCR_TRX_DISABLE, MTK_XMAC_MCR(mac->id));
|
||||
+ }
|
||||
}
|
||||
|
||||
static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx,
|
||||
@@ -767,13 +856,11 @@ static void mtk_set_queue_speed(struct m
|
||||
mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
|
||||
}
|
||||
|
||||
-static void mtk_mac_link_up(struct phylink_config *config,
|
||||
- struct phy_device *phy,
|
||||
- unsigned int mode, phy_interface_t interface,
|
||||
- int speed, int duplex, bool tx_pause, bool rx_pause)
|
||||
+static void mtk_gdm_mac_link_up(struct mtk_mac *mac,
|
||||
+ struct phy_device *phy,
|
||||
+ unsigned int mode, phy_interface_t interface,
|
||||
+ int speed, int duplex, bool tx_pause, bool rx_pause)
|
||||
{
|
||||
- struct mtk_mac *mac = container_of(config, struct mtk_mac,
|
||||
- phylink_config);
|
||||
u32 mcr;
|
||||
|
||||
mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
|
||||
@@ -807,9 +894,63 @@ static void mtk_mac_link_up(struct phyli
|
||||
mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
|
||||
}
|
||||
|
||||
+static void mtk_xgdm_mac_link_up(struct mtk_mac *mac,
|
||||
+ struct phy_device *phy,
|
||||
+ unsigned int mode, phy_interface_t interface,
|
||||
+ int speed, int duplex, bool tx_pause, bool rx_pause)
|
||||
+{
|
||||
+ u32 mcr, force_link = 0;
|
||||
+
|
||||
+ if (mac->id == MTK_GMAC1_ID)
|
||||
+ return;
|
||||
+
|
||||
+ /* Eliminate the interference(before link-up) caused by PHY noise */
|
||||
+ mtk_m32(mac->hw, XMAC_LOGIC_RST, 0, MTK_XMAC_LOGIC_RST(mac->id));
|
||||
+ mdelay(20);
|
||||
+ mtk_m32(mac->hw, XMAC_GLB_CNTCLR, XMAC_GLB_CNTCLR, MTK_XMAC_CNT_CTRL(mac->id));
|
||||
+
|
||||
+ if (mac->interface == PHY_INTERFACE_MODE_INTERNAL || mac->id == MTK_GMAC3_ID)
|
||||
+ force_link = MTK_XGMAC_FORCE_LINK(mac->id);
|
||||
+
|
||||
+ mtk_m32(mac->hw, MTK_XGMAC_FORCE_LINK(mac->id), force_link, MTK_XGMAC_STS(mac->id));
|
||||
+
|
||||
+ mcr = mtk_r32(mac->hw, MTK_XMAC_MCR(mac->id));
|
||||
+ mcr &= ~(XMAC_MCR_FORCE_TX_FC | XMAC_MCR_FORCE_RX_FC | XMAC_MCR_TRX_DISABLE);
|
||||
+ /* Configure pause modes -
|
||||
+ * phylink will avoid these for half duplex
|
||||
+ */
|
||||
+ if (tx_pause)
|
||||
+ mcr |= XMAC_MCR_FORCE_TX_FC;
|
||||
+ if (rx_pause)
|
||||
+ mcr |= XMAC_MCR_FORCE_RX_FC;
|
||||
+
|
||||
+ mtk_w32(mac->hw, mcr, MTK_XMAC_MCR(mac->id));
|
||||
+}
|
||||
+
|
||||
+static void mtk_mac_link_up(struct phylink_config *config,
|
||||
+ struct phy_device *phy,
|
||||
+ unsigned int mode, phy_interface_t interface,
|
||||
+ int speed, int duplex, bool tx_pause, bool rx_pause)
|
||||
+{
|
||||
+ struct mtk_mac *mac = container_of(config, struct mtk_mac,
|
||||
+ phylink_config);
|
||||
+
|
||||
+ if (mtk_is_netsys_v3_or_greater(mac->hw) && mtk_interface_mode_is_xgmii(interface))
|
||||
+ mtk_xgdm_mac_link_up(mac, phy, mode, interface, speed, duplex,
|
||||
+ tx_pause, rx_pause);
|
||||
+ else
|
||||
+ mtk_gdm_mac_link_up(mac, phy, mode, interface, speed, duplex,
|
||||
+ tx_pause, rx_pause);
|
||||
+
|
||||
+ /* Repeat pextp setup to tune link */
|
||||
+ if (mac->pextp)
|
||||
+ phy_set_mode_ext(mac->pextp, PHY_MODE_ETHERNET, interface);
|
||||
+}
|
||||
+
|
||||
static const struct phylink_mac_ops mtk_phylink_ops = {
|
||||
.mac_select_pcs = mtk_mac_select_pcs,
|
||||
.mac_config = mtk_mac_config,
|
||||
+ .mac_prepare = mtk_mac_prepare,
|
||||
.mac_finish = mtk_mac_finish,
|
||||
.mac_link_down = mtk_mac_link_down,
|
||||
.mac_link_up = mtk_mac_link_up,
|
||||
@@ -3403,6 +3544,9 @@ static int mtk_open(struct net_device *d
|
||||
struct mtk_eth *eth = mac->hw;
|
||||
int i, err;
|
||||
|
||||
+ if (mac->pextp)
|
||||
+ phy_power_on(mac->pextp);
|
||||
+
|
||||
err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
|
||||
if (err) {
|
||||
netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
|
||||
@@ -3532,6 +3676,9 @@ static int mtk_stop(struct net_device *d
|
||||
for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
|
||||
mtk_ppe_stop(eth->ppe[i]);
|
||||
|
||||
+ if (mac->pextp)
|
||||
+ phy_power_off(mac->pextp);
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -4529,6 +4676,7 @@ static const struct net_device_ops mtk_n
|
||||
static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
|
||||
{
|
||||
const __be32 *_id = of_get_property(np, "reg", NULL);
|
||||
+ struct device_node *pcs_np;
|
||||
phy_interface_t phy_mode;
|
||||
struct phylink *phylink;
|
||||
struct mtk_mac *mac;
|
||||
@@ -4565,16 +4713,41 @@ static int mtk_add_mac(struct mtk_eth *e
|
||||
mac->id = id;
|
||||
mac->hw = eth;
|
||||
mac->of_node = np;
|
||||
+ pcs_np = of_parse_phandle(mac->of_node, "pcs-handle", 0);
|
||||
+ if (pcs_np) {
|
||||
+ mac->sgmii_pcs = mtk_pcs_lynxi_get(eth->dev, pcs_np);
|
||||
+ if (IS_ERR(mac->sgmii_pcs)) {
|
||||
+ if (PTR_ERR(mac->sgmii_pcs) == -EPROBE_DEFER)
|
||||
+ return -EPROBE_DEFER;
|
||||
|
||||
- err = of_get_ethdev_address(mac->of_node, eth->netdev[id]);
|
||||
- if (err == -EPROBE_DEFER)
|
||||
- return err;
|
||||
+ dev_err(eth->dev, "cannot select SGMII PCS, error %ld\n",
|
||||
+ PTR_ERR(mac->sgmii_pcs));
|
||||
+ return PTR_ERR(mac->sgmii_pcs);
|
||||
+ }
|
||||
+ }
|
||||
|
||||
- if (err) {
|
||||
- /* If the mac address is invalid, use random mac address */
|
||||
- eth_hw_addr_random(eth->netdev[id]);
|
||||
- dev_err(eth->dev, "generated random MAC address %pM\n",
|
||||
- eth->netdev[id]->dev_addr);
|
||||
+ pcs_np = of_parse_phandle(mac->of_node, "pcs-handle", 1);
|
||||
+ if (pcs_np) {
|
||||
+ mac->usxgmii_pcs = mtk_usxgmii_pcs_get(eth->dev, pcs_np);
|
||||
+ if (IS_ERR(mac->usxgmii_pcs)) {
|
||||
+ if (PTR_ERR(mac->usxgmii_pcs) == -EPROBE_DEFER)
|
||||
+ return -EPROBE_DEFER;
|
||||
+
|
||||
+ dev_err(eth->dev, "cannot select USXGMII PCS, error %ld\n",
|
||||
+ PTR_ERR(mac->usxgmii_pcs));
|
||||
+ return PTR_ERR(mac->usxgmii_pcs);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ if (mtk_is_netsys_v3_or_greater(eth) && (mac->sgmii_pcs || mac->usxgmii_pcs)) {
|
||||
+ mac->pextp = devm_of_phy_get(eth->dev, mac->of_node, NULL);
|
||||
+ if (IS_ERR(mac->pextp)) {
|
||||
+ if (PTR_ERR(mac->pextp) != -EPROBE_DEFER)
|
||||
+ dev_err(eth->dev, "cannot get PHY, error %ld\n",
|
||||
+ PTR_ERR(mac->pextp));
|
||||
+
|
||||
+ return PTR_ERR(mac->pextp);
|
||||
+ }
|
||||
}
|
||||
|
||||
memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
|
||||
@@ -4657,8 +4830,21 @@ static int mtk_add_mac(struct mtk_eth *e
|
||||
phy_interface_zero(mac->phylink_config.supported_interfaces);
|
||||
__set_bit(PHY_INTERFACE_MODE_INTERNAL,
|
||||
mac->phylink_config.supported_interfaces);
|
||||
+ } else if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_USXGMII)) {
|
||||
+ mac->phylink_config.mac_capabilities |= MAC_5000FD | MAC_10000FD;
|
||||
+ __set_bit(PHY_INTERFACE_MODE_5GBASER,
|
||||
+ mac->phylink_config.supported_interfaces);
|
||||
+ __set_bit(PHY_INTERFACE_MODE_10GBASER,
|
||||
+ mac->phylink_config.supported_interfaces);
|
||||
+ __set_bit(PHY_INTERFACE_MODE_USXGMII,
|
||||
+ mac->phylink_config.supported_interfaces);
|
||||
}
|
||||
|
||||
+ if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_2P5GPHY) &&
|
||||
+ id == MTK_GMAC2_ID)
|
||||
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
|
||||
+ mac->phylink_config.supported_interfaces);
|
||||
+
|
||||
phylink = phylink_create(&mac->phylink_config,
|
||||
of_fwnode_handle(mac->of_node),
|
||||
phy_mode, &mtk_phylink_ops);
|
||||
@@ -4709,6 +4895,26 @@ free_netdev:
|
||||
return err;
|
||||
}
|
||||
|
||||
+static int mtk_mac_assign_address(struct mtk_eth *eth, int i, bool test_defer_only)
|
||||
+{
|
||||
+ int err = of_get_ethdev_address(eth->mac[i]->of_node, eth->netdev[i]);
|
||||
+
|
||||
+ if (err == -EPROBE_DEFER)
|
||||
+ return err;
|
||||
+
|
||||
+ if (test_defer_only)
|
||||
+ return 0;
|
||||
+
|
||||
+ if (err) {
|
||||
+ /* If the mac address is invalid, use random mac address */
|
||||
+ eth_hw_addr_random(eth->netdev[i]);
|
||||
+ dev_err(eth->dev, "generated random MAC address %pM\n",
|
||||
+ eth->netdev[i]);
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev)
|
||||
{
|
||||
struct net_device *dev, *tmp;
|
||||
@@ -4855,7 +5061,8 @@ static int mtk_probe(struct platform_dev
|
||||
regmap_write(cci, 0, 3);
|
||||
}
|
||||
|
||||
- if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
|
||||
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII) &&
|
||||
+ !mtk_is_netsys_v3_or_greater(eth)) {
|
||||
err = mtk_sgmii_init(eth);
|
||||
|
||||
if (err)
|
||||
@@ -4966,6 +5173,24 @@ static int mtk_probe(struct platform_dev
|
||||
}
|
||||
}
|
||||
|
||||
+ for (i = 0; i < MTK_MAX_DEVS; i++) {
|
||||
+ if (!eth->netdev[i])
|
||||
+ continue;
|
||||
+
|
||||
+ err = mtk_mac_assign_address(eth, i, true);
|
||||
+ if (err)
|
||||
+ goto err_deinit_hw;
|
||||
+ }
|
||||
+
|
||||
+ for (i = 0; i < MTK_MAX_DEVS; i++) {
|
||||
+ if (!eth->netdev[i])
|
||||
+ continue;
|
||||
+
|
||||
+ err = mtk_mac_assign_address(eth, i, false);
|
||||
+ if (err)
|
||||
+ goto err_deinit_hw;
|
||||
+ }
|
||||
+
|
||||
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
|
||||
err = devm_request_irq(eth->dev, eth->irq[0],
|
||||
mtk_handle_irq, 0,
|
||||
@@ -5068,6 +5293,11 @@ static int mtk_remove(struct platform_de
|
||||
mtk_stop(eth->netdev[i]);
|
||||
mac = netdev_priv(eth->netdev[i]);
|
||||
phylink_disconnect_phy(mac->phylink);
|
||||
+ if (mac->sgmii_pcs)
|
||||
+ mtk_pcs_lynxi_put(mac->sgmii_pcs);
|
||||
+
|
||||
+ if (mac->usxgmii_pcs)
|
||||
+ mtk_usxgmii_pcs_put(mac->usxgmii_pcs);
|
||||
}
|
||||
|
||||
mtk_wed_exit();
|
||||
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
|
||||
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
|
||||
@@ -15,6 +15,7 @@
|
||||
#include <linux/u64_stats_sync.h>
|
||||
#include <linux/refcount.h>
|
||||
#include <linux/phylink.h>
|
||||
+#include <linux/reset.h>
|
||||
#include <linux/rhashtable.h>
|
||||
#include <linux/dim.h>
|
||||
#include <linux/bitfield.h>
|
||||
@@ -504,6 +505,21 @@
|
||||
#define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
|
||||
#define INTF_MODE_RGMII_10_100 0
|
||||
|
||||
+/* XFI Mac control registers */
|
||||
+#define MTK_XMAC_BASE(x) (0x12000 + (((x) - 1) * 0x1000))
|
||||
+#define MTK_XMAC_MCR(x) (MTK_XMAC_BASE(x))
|
||||
+#define XMAC_MCR_TRX_DISABLE 0xf
|
||||
+#define XMAC_MCR_FORCE_TX_FC BIT(5)
|
||||
+#define XMAC_MCR_FORCE_RX_FC BIT(4)
|
||||
+
|
||||
+/* XFI Mac logic reset registers */
|
||||
+#define MTK_XMAC_LOGIC_RST(x) (MTK_XMAC_BASE(x) + 0x10)
|
||||
+#define XMAC_LOGIC_RST BIT(0)
|
||||
+
|
||||
+/* XFI Mac count global control */
|
||||
+#define MTK_XMAC_CNT_CTRL(x) (MTK_XMAC_BASE(x) + 0x100)
|
||||
+#define XMAC_GLB_CNTCLR BIT(0)
|
||||
+
|
||||
/* GPIO port control registers for GMAC 2*/
|
||||
#define GPIO_OD33_CTRL8 0x4c0
|
||||
#define GPIO_BIAS_CTRL 0xed0
|
||||
@@ -529,6 +545,7 @@
|
||||
#define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK)
|
||||
#define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
|
||||
#define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
|
||||
+#define SYSCFG0_SGMII_GMAC3_V2 BIT(7)
|
||||
|
||||
|
||||
/* ethernet subsystem clock register */
|
||||
@@ -567,6 +584,11 @@
|
||||
#define GEPHY_MAC_SEL BIT(1)
|
||||
|
||||
/* Top misc registers */
|
||||
+#define TOP_MISC_NETSYS_PCS_MUX 0x84
|
||||
+#define NETSYS_PCS_MUX_MASK GENMASK(1, 0)
|
||||
+#define MUX_G2_USXGMII_SEL BIT(1)
|
||||
+#define MUX_HSGMII1_G1_SEL BIT(0)
|
||||
+
|
||||
#define USB_PHY_SWITCH_REG 0x218
|
||||
#define QPHY_SEL_MASK GENMASK(1, 0)
|
||||
#define SGMII_QPHY_SEL 0x2
|
||||
@@ -591,6 +613,8 @@
|
||||
#define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c)
|
||||
#define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110)
|
||||
|
||||
+/* Debug Purpose Register */
|
||||
+#define MTK_PSE_FQFC_CFG 0x100
|
||||
#define MTK_FE_CDM1_FSM 0x220
|
||||
#define MTK_FE_CDM2_FSM 0x224
|
||||
#define MTK_FE_CDM3_FSM 0x238
|
||||
@@ -599,6 +623,11 @@
|
||||
#define MTK_FE_CDM6_FSM 0x328
|
||||
#define MTK_FE_GDM1_FSM 0x228
|
||||
#define MTK_FE_GDM2_FSM 0x22C
|
||||
+#define MTK_FE_GDM3_FSM 0x23C
|
||||
+#define MTK_FE_PSE_FREE 0x240
|
||||
+#define MTK_FE_DROP_FQ 0x244
|
||||
+#define MTK_FE_DROP_FC 0x248
|
||||
+#define MTK_FE_DROP_PPE 0x24C
|
||||
|
||||
#define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100))
|
||||
|
||||
@@ -723,12 +752,8 @@ enum mtk_clks_map {
|
||||
MTK_CLK_ETHWARP_WOCPU2,
|
||||
MTK_CLK_ETHWARP_WOCPU1,
|
||||
MTK_CLK_ETHWARP_WOCPU0,
|
||||
- MTK_CLK_TOP_USXGMII_SBUS_0_SEL,
|
||||
- MTK_CLK_TOP_USXGMII_SBUS_1_SEL,
|
||||
MTK_CLK_TOP_SGM_0_SEL,
|
||||
MTK_CLK_TOP_SGM_1_SEL,
|
||||
- MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL,
|
||||
- MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL,
|
||||
MTK_CLK_TOP_ETH_GMII_SEL,
|
||||
MTK_CLK_TOP_ETH_REFCK_50M_SEL,
|
||||
MTK_CLK_TOP_ETH_SYS_200M_SEL,
|
||||
@@ -799,19 +824,9 @@ enum mtk_clks_map {
|
||||
BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \
|
||||
BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \
|
||||
BIT_ULL(MTK_CLK_CRYPTO) | \
|
||||
- BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
|
||||
- BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
|
||||
- BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
|
||||
- BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
|
||||
BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \
|
||||
BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \
|
||||
BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \
|
||||
- BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \
|
||||
- BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \
|
||||
- BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \
|
||||
- BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \
|
||||
- BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \
|
||||
- BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \
|
||||
BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \
|
||||
BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \
|
||||
BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \
|
||||
@@ -945,6 +960,8 @@ enum mkt_eth_capabilities {
|
||||
MTK_RGMII_BIT = 0,
|
||||
MTK_TRGMII_BIT,
|
||||
MTK_SGMII_BIT,
|
||||
+ MTK_USXGMII_BIT,
|
||||
+ MTK_2P5GPHY_BIT,
|
||||
MTK_ESW_BIT,
|
||||
MTK_GEPHY_BIT,
|
||||
MTK_MUX_BIT,
|
||||
@@ -965,8 +982,11 @@ enum mkt_eth_capabilities {
|
||||
MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
|
||||
MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
|
||||
MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
|
||||
+ MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT,
|
||||
MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT,
|
||||
MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT,
|
||||
+ MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT,
|
||||
+ MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT,
|
||||
|
||||
/* PATH BITS */
|
||||
MTK_ETH_PATH_GMAC1_RGMII_BIT,
|
||||
@@ -974,14 +994,21 @@ enum mkt_eth_capabilities {
|
||||
MTK_ETH_PATH_GMAC1_SGMII_BIT,
|
||||
MTK_ETH_PATH_GMAC2_RGMII_BIT,
|
||||
MTK_ETH_PATH_GMAC2_SGMII_BIT,
|
||||
+ MTK_ETH_PATH_GMAC2_2P5GPHY_BIT,
|
||||
MTK_ETH_PATH_GMAC2_GEPHY_BIT,
|
||||
+ MTK_ETH_PATH_GMAC3_SGMII_BIT,
|
||||
MTK_ETH_PATH_GDM1_ESW_BIT,
|
||||
+ MTK_ETH_PATH_GMAC1_USXGMII_BIT,
|
||||
+ MTK_ETH_PATH_GMAC2_USXGMII_BIT,
|
||||
+ MTK_ETH_PATH_GMAC3_USXGMII_BIT,
|
||||
};
|
||||
|
||||
/* Supported hardware group on SoCs */
|
||||
#define MTK_RGMII BIT_ULL(MTK_RGMII_BIT)
|
||||
#define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT)
|
||||
#define MTK_SGMII BIT_ULL(MTK_SGMII_BIT)
|
||||
+#define MTK_USXGMII BIT_ULL(MTK_USXGMII_BIT)
|
||||
+#define MTK_2P5GPHY BIT_ULL(MTK_2P5GPHY_BIT)
|
||||
#define MTK_ESW BIT_ULL(MTK_ESW_BIT)
|
||||
#define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT)
|
||||
#define MTK_MUX BIT_ULL(MTK_MUX_BIT)
|
||||
@@ -1004,10 +1031,16 @@ enum mkt_eth_capabilities {
|
||||
BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
|
||||
#define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \
|
||||
BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
|
||||
+#define MTK_ETH_MUX_GMAC2_TO_2P5GPHY \
|
||||
+ BIT_ULL(MTK_ETH_MUX_GMAC2_TO_2P5GPHY_BIT)
|
||||
#define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \
|
||||
BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT)
|
||||
#define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \
|
||||
BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT)
|
||||
+#define MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII \
|
||||
+ BIT_ULL(MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII_BIT)
|
||||
+#define MTK_ETH_MUX_GMAC123_TO_USXGMII \
|
||||
+ BIT_ULL(MTK_ETH_MUX_GMAC123_TO_USXGMII_BIT)
|
||||
|
||||
/* Supported path present on SoCs */
|
||||
#define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT)
|
||||
@@ -1015,8 +1048,13 @@ enum mkt_eth_capabilities {
|
||||
#define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT)
|
||||
#define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT)
|
||||
#define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)
|
||||
+#define MTK_ETH_PATH_GMAC2_2P5GPHY BIT_ULL(MTK_ETH_PATH_GMAC2_2P5GPHY_BIT)
|
||||
#define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT)
|
||||
+#define MTK_ETH_PATH_GMAC3_SGMII BIT_ULL(MTK_ETH_PATH_GMAC3_SGMII_BIT)
|
||||
#define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT)
|
||||
+#define MTK_ETH_PATH_GMAC1_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC1_USXGMII_BIT)
|
||||
+#define MTK_ETH_PATH_GMAC2_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC2_USXGMII_BIT)
|
||||
+#define MTK_ETH_PATH_GMAC3_USXGMII BIT_ULL(MTK_ETH_PATH_GMAC3_USXGMII_BIT)
|
||||
|
||||
#define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
|
||||
#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
|
||||
@@ -1024,7 +1062,12 @@ enum mkt_eth_capabilities {
|
||||
#define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
|
||||
#define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
|
||||
#define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
|
||||
+#define MTK_GMAC2_2P5GPHY (MTK_ETH_PATH_GMAC2_2P5GPHY | MTK_2P5GPHY)
|
||||
+#define MTK_GMAC3_SGMII (MTK_ETH_PATH_GMAC3_SGMII | MTK_SGMII)
|
||||
#define MTK_GDM1_ESW (MTK_ETH_PATH_GDM1_ESW | MTK_ESW)
|
||||
+#define MTK_GMAC1_USXGMII (MTK_ETH_PATH_GMAC1_USXGMII | MTK_USXGMII)
|
||||
+#define MTK_GMAC2_USXGMII (MTK_ETH_PATH_GMAC2_USXGMII | MTK_USXGMII)
|
||||
+#define MTK_GMAC3_USXGMII (MTK_ETH_PATH_GMAC3_USXGMII | MTK_USXGMII)
|
||||
|
||||
/* MUXes present on SoCs */
|
||||
/* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
|
||||
@@ -1043,10 +1086,20 @@ enum mkt_eth_capabilities {
|
||||
(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \
|
||||
MTK_SHARED_SGMII)
|
||||
|
||||
+/* 2: GMAC2 -> XGMII */
|
||||
+#define MTK_MUX_GMAC2_TO_2P5GPHY \
|
||||
+ (MTK_ETH_MUX_GMAC2_TO_2P5GPHY | MTK_MUX | MTK_INFRA)
|
||||
+
|
||||
/* 0: GMACx -> GEPHY, 1: GMACx -> SGMII where x is 1 or 2 */
|
||||
#define MTK_MUX_GMAC12_TO_GEPHY_SGMII \
|
||||
(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII | MTK_MUX)
|
||||
|
||||
+#define MTK_MUX_GMAC123_TO_GEPHY_SGMII \
|
||||
+ (MTK_ETH_MUX_GMAC123_TO_GEPHY_SGMII | MTK_MUX)
|
||||
+
|
||||
+#define MTK_MUX_GMAC123_TO_USXGMII \
|
||||
+ (MTK_ETH_MUX_GMAC123_TO_USXGMII | MTK_MUX | MTK_INFRA)
|
||||
+
|
||||
#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
|
||||
|
||||
#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
|
||||
@@ -1078,8 +1131,12 @@ enum mkt_eth_capabilities {
|
||||
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
|
||||
MTK_RSTCTRL_PPE1 | MTK_SRAM)
|
||||
|
||||
-#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_QDMA | \
|
||||
- MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | MTK_SRAM)
|
||||
+#define MT7988_CAPS (MTK_36BIT_DMA | MTK_GDM1_ESW | MTK_GMAC1_SGMII | \
|
||||
+ MTK_GMAC2_2P5GPHY | MTK_GMAC2_SGMII | MTK_GMAC2_USXGMII | \
|
||||
+ MTK_GMAC3_SGMII | MTK_GMAC3_USXGMII | \
|
||||
+ MTK_MUX_GMAC123_TO_GEPHY_SGMII | \
|
||||
+ MTK_MUX_GMAC123_TO_USXGMII | MTK_MUX_GMAC2_TO_2P5GPHY | \
|
||||
+ MTK_QDMA | MTK_RSTCTRL_PPE1 | MTK_RSTCTRL_PPE2 | MTK_SRAM)
|
||||
|
||||
struct mtk_tx_dma_desc_info {
|
||||
dma_addr_t addr;
|
||||
@@ -1322,6 +1379,9 @@ struct mtk_mac {
|
||||
struct device_node *of_node;
|
||||
struct phylink *phylink;
|
||||
struct phylink_config phylink_config;
|
||||
+ struct phylink_pcs *sgmii_pcs;
|
||||
+ struct phylink_pcs *usxgmii_pcs;
|
||||
+ struct phy *pextp;
|
||||
struct mtk_eth *hw;
|
||||
struct mtk_hw_stats *hw_stats;
|
||||
__be32 hwlro_ip[MTK_MAX_LRO_IP_CNT];
|
||||
@@ -1445,6 +1505,19 @@ static inline u32 mtk_get_ib2_multicast_
|
||||
return MTK_FOE_IB2_MULTICAST;
|
||||
}
|
||||
|
||||
+static inline bool mtk_interface_mode_is_xgmii(phy_interface_t interface)
|
||||
+{
|
||||
+ switch (interface) {
|
||||
+ case PHY_INTERFACE_MODE_INTERNAL:
|
||||
+ case PHY_INTERFACE_MODE_USXGMII:
|
||||
+ case PHY_INTERFACE_MODE_10GBASER:
|
||||
+ case PHY_INTERFACE_MODE_5GBASER:
|
||||
+ return true;
|
||||
+ default:
|
||||
+ return false;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
/* read the hardware status register */
|
||||
void mtk_stats_update_mac(struct mtk_mac *mac);
|
||||
|
||||
@@ -1453,8 +1526,10 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne
|
||||
u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg);
|
||||
|
||||
int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
|
||||
+int mtk_gmac_2p5gphy_path_setup(struct mtk_eth *eth, int mac_id);
|
||||
int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
|
||||
int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
|
||||
+int mtk_gmac_usxgmii_path_setup(struct mtk_eth *eth, int mac_id);
|
||||
|
||||
int mtk_eth_offload_init(struct mtk_eth *eth);
|
||||
int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,
|
||||
|
|
@ -1,147 +0,0 @@
|
|||
From: Daniel Golle <daniel@makrotopia.org>
|
||||
Subject: libata: add ledtrig support
|
||||
|
||||
This adds a LED trigger for each ATA port indicating disk activity.
|
||||
|
||||
As this is needed only on specific platforms (NAS SoCs and such),
|
||||
these platforms should define ARCH_WANTS_LIBATA_LEDS if there
|
||||
are boards with LED(s) intended to indicate ATA disk activity and
|
||||
need the OS to take care of that.
|
||||
In that way, if not selected, LED trigger support not will be
|
||||
included in libata-core and both, codepaths and structures remain
|
||||
untouched.
|
||||
|
||||
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||
---
|
||||
drivers/ata/Kconfig | 16 ++++++++++++++++
|
||||
drivers/ata/libata-core.c | 41 +++++++++++++++++++++++++++++++++++++++++
|
||||
include/linux/libata.h | 9 +++++++++
|
||||
3 files changed, 66 insertions(+)
|
||||
|
||||
--- a/drivers/ata/Kconfig
|
||||
+++ b/drivers/ata/Kconfig
|
||||
@@ -67,6 +67,22 @@ config ATA_FORCE
|
||||
|
||||
If unsure, say Y.
|
||||
|
||||
+config ARCH_WANT_LIBATA_LEDS
|
||||
+ bool
|
||||
+
|
||||
+config ATA_LEDS
|
||||
+ bool "support ATA port LED triggers"
|
||||
+ depends on ARCH_WANT_LIBATA_LEDS
|
||||
+ select NEW_LEDS
|
||||
+ select LEDS_CLASS
|
||||
+ select LEDS_TRIGGERS
|
||||
+ default y
|
||||
+ help
|
||||
+ This option adds a LED trigger for each registered ATA port.
|
||||
+ It is used to drive disk activity leds connected via GPIO.
|
||||
+
|
||||
+ If unsure, say N.
|
||||
+
|
||||
config ATA_ACPI
|
||||
bool "ATA ACPI Support"
|
||||
depends on ACPI
|
||||
--- a/drivers/ata/libata-core.c
|
||||
+++ b/drivers/ata/libata-core.c
|
||||
@@ -685,6 +685,17 @@ static inline void ata_set_tf_cdl(struct
|
||||
qc->flags |= ATA_QCFLAG_HAS_CDL | ATA_QCFLAG_RESULT_TF;
|
||||
}
|
||||
|
||||
+#ifdef CONFIG_ATA_LEDS
|
||||
+#define LIBATA_BLINK_DELAY 20 /* ms */
|
||||
+static inline void ata_led_act(struct ata_port *ap)
|
||||
+{
|
||||
+ if (unlikely(!ap->ledtrig))
|
||||
+ return;
|
||||
+
|
||||
+ led_trigger_blink_oneshot(ap->ledtrig, LIBATA_BLINK_DELAY, LIBATA_BLINK_DELAY, 0);
|
||||
+}
|
||||
+#endif
|
||||
+
|
||||
/**
|
||||
* ata_build_rw_tf - Build ATA taskfile for given read/write request
|
||||
* @qc: Metadata associated with the taskfile to build
|
||||
@@ -4771,6 +4782,9 @@ void __ata_qc_complete(struct ata_queued
|
||||
link->active_tag = ATA_TAG_POISON;
|
||||
ap->nr_active_links--;
|
||||
}
|
||||
+#ifdef CONFIG_ATA_LEDS
|
||||
+ ata_led_act(ap);
|
||||
+#endif
|
||||
|
||||
/* clear exclusive status */
|
||||
if (unlikely(qc->flags & ATA_QCFLAG_CLEAR_EXCL &&
|
||||
@@ -5494,6 +5508,9 @@ struct ata_port *ata_port_alloc(struct a
|
||||
ap->stats.unhandled_irq = 1;
|
||||
ap->stats.idle_irq = 1;
|
||||
#endif
|
||||
+#ifdef CONFIG_ATA_LEDS
|
||||
+ ap->ledtrig = kzalloc(sizeof(struct led_trigger), GFP_KERNEL);
|
||||
+#endif
|
||||
ata_sff_port_init(ap);
|
||||
|
||||
return ap;
|
||||
@@ -5530,6 +5547,12 @@ static void ata_host_release(struct kref
|
||||
kfree(ap->pmp_link);
|
||||
kfree(ap->slave_link);
|
||||
kfree(ap->ncq_sense_buf);
|
||||
+#ifdef CONFIG_ATA_LEDS
|
||||
+ if (ap->ledtrig) {
|
||||
+ led_trigger_unregister(ap->ledtrig);
|
||||
+ kfree(ap->ledtrig);
|
||||
+ };
|
||||
+#endif
|
||||
kfree(ap);
|
||||
host->ports[i] = NULL;
|
||||
}
|
||||
@@ -5920,7 +5943,23 @@ int ata_host_register(struct ata_host *h
|
||||
host->ports[i]->print_id = atomic_inc_return(&ata_print_id);
|
||||
host->ports[i]->local_port_no = i + 1;
|
||||
}
|
||||
+#ifdef CONFIG_ATA_LEDS
|
||||
+ for (i = 0; i < host->n_ports; i++) {
|
||||
+ if (unlikely(!host->ports[i]->ledtrig))
|
||||
+ continue;
|
||||
|
||||
+ snprintf(host->ports[i]->ledtrig_name,
|
||||
+ sizeof(host->ports[i]->ledtrig_name), "ata%u",
|
||||
+ host->ports[i]->print_id);
|
||||
+
|
||||
+ host->ports[i]->ledtrig->name = host->ports[i]->ledtrig_name;
|
||||
+
|
||||
+ if (led_trigger_register(host->ports[i]->ledtrig)) {
|
||||
+ kfree(host->ports[i]->ledtrig);
|
||||
+ host->ports[i]->ledtrig = NULL;
|
||||
+ }
|
||||
+ }
|
||||
+#endif
|
||||
/* Create associated sysfs transport objects */
|
||||
for (i = 0; i < host->n_ports; i++) {
|
||||
rc = ata_tport_add(host->dev,host->ports[i]);
|
||||
--- a/include/linux/libata.h
|
||||
+++ b/include/linux/libata.h
|
||||
@@ -23,6 +23,9 @@
|
||||
#include <linux/cdrom.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/async.h>
|
||||
+#ifdef CONFIG_ATA_LEDS
|
||||
+#include <linux/leds.h>
|
||||
+#endif
|
||||
|
||||
/*
|
||||
* Define if arch has non-standard setup. This is a _PCI_ standard
|
||||
@@ -875,6 +878,12 @@ struct ata_port {
|
||||
#ifdef CONFIG_ATA_ACPI
|
||||
struct ata_acpi_gtm __acpi_init_gtm; /* use ata_acpi_init_gtm() */
|
||||
#endif
|
||||
+
|
||||
+#ifdef CONFIG_ATA_LEDS
|
||||
+ struct led_trigger *ledtrig;
|
||||
+ char ledtrig_name[8];
|
||||
+#endif
|
||||
+
|
||||
/* owned by EH */
|
||||
u8 *ncq_sense_buf;
|
||||
u8 sector_buf[ATA_SECT_SIZE] ____cacheline_aligned;
|
||||
307
6.10/target/linux/mediatek/files-6.10/block/partitions/fit.c
Normal file
307
6.10/target/linux/mediatek/files-6.10/block/partitions/fit.c
Normal file
|
|
@ -0,0 +1,307 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* fs/partitions/fit.c
|
||||
* Copyright (C) 2021 Daniel Golle
|
||||
*
|
||||
* headers extracted from U-Boot mkimage sources
|
||||
* (C) Copyright 2008 Semihalf
|
||||
* (C) Copyright 2000-2005
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* based on existing partition parsers
|
||||
* Copyright (C) 1991-1998 Linus Torvalds
|
||||
* Re-organised Feb 1998 Russell King
|
||||
*/
|
||||
|
||||
#define pr_fmt(fmt) fmt
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/libfdt.h>
|
||||
#include <linux/version.h>
|
||||
|
||||
#include "check.h"
|
||||
|
||||
#define FIT_IMAGES_PATH "/images"
|
||||
#define FIT_CONFS_PATH "/configurations"
|
||||
|
||||
/* hash/signature/key node */
|
||||
#define FIT_HASH_NODENAME "hash"
|
||||
#define FIT_ALGO_PROP "algo"
|
||||
#define FIT_VALUE_PROP "value"
|
||||
#define FIT_IGNORE_PROP "uboot-ignore"
|
||||
#define FIT_SIG_NODENAME "signature"
|
||||
#define FIT_KEY_REQUIRED "required"
|
||||
#define FIT_KEY_HINT "key-name-hint"
|
||||
|
||||
/* cipher node */
|
||||
#define FIT_CIPHER_NODENAME "cipher"
|
||||
#define FIT_ALGO_PROP "algo"
|
||||
|
||||
/* image node */
|
||||
#define FIT_DATA_PROP "data"
|
||||
#define FIT_DATA_POSITION_PROP "data-position"
|
||||
#define FIT_DATA_OFFSET_PROP "data-offset"
|
||||
#define FIT_DATA_SIZE_PROP "data-size"
|
||||
#define FIT_TIMESTAMP_PROP "timestamp"
|
||||
#define FIT_DESC_PROP "description"
|
||||
#define FIT_ARCH_PROP "arch"
|
||||
#define FIT_TYPE_PROP "type"
|
||||
#define FIT_OS_PROP "os"
|
||||
#define FIT_COMP_PROP "compression"
|
||||
#define FIT_ENTRY_PROP "entry"
|
||||
#define FIT_LOAD_PROP "load"
|
||||
|
||||
/* configuration node */
|
||||
#define FIT_KERNEL_PROP "kernel"
|
||||
#define FIT_FILESYSTEM_PROP "filesystem"
|
||||
#define FIT_RAMDISK_PROP "ramdisk"
|
||||
#define FIT_FDT_PROP "fdt"
|
||||
#define FIT_LOADABLE_PROP "loadables"
|
||||
#define FIT_DEFAULT_PROP "default"
|
||||
#define FIT_SETUP_PROP "setup"
|
||||
#define FIT_FPGA_PROP "fpga"
|
||||
#define FIT_FIRMWARE_PROP "firmware"
|
||||
#define FIT_STANDALONE_PROP "standalone"
|
||||
|
||||
#define FIT_MAX_HASH_LEN HASH_MAX_DIGEST_SIZE
|
||||
|
||||
#define MIN_FREE_SECT 16
|
||||
#define REMAIN_VOLNAME "rootfs_data"
|
||||
|
||||
int parse_fit_partitions(struct parsed_partitions *state, u64 fit_start_sector, u64 sectors, int *slot, int add_remain)
|
||||
{
|
||||
struct block_device *bdev = state->disk->part0;
|
||||
struct address_space *mapping = bdev->bd_inode->i_mapping;
|
||||
struct page *page;
|
||||
void *fit, *init_fit;
|
||||
struct partition_meta_info *info;
|
||||
char tmp[sizeof(info->volname)];
|
||||
u64 dsize, dsectors, imgmaxsect = 0;
|
||||
u32 size, image_pos, image_len;
|
||||
const u32 *image_offset_be, *image_len_be, *image_pos_be;
|
||||
int ret = 1, node, images, config;
|
||||
const char *image_name, *image_type, *image_description, *config_default,
|
||||
*config_description, *config_loadables, *bootconf_c;
|
||||
int image_name_len, image_type_len, image_description_len, config_default_len,
|
||||
config_description_len, config_loadables_len, bootconf_len;
|
||||
sector_t start_sect, nr_sects;
|
||||
size_t label_min;
|
||||
struct device_node *np = NULL;
|
||||
char *bootconf = NULL, *bootconf_term;
|
||||
const char *loadable;
|
||||
const char *select_rootfs = NULL;
|
||||
bool found;
|
||||
int loadables_rem_len, loadable_len;
|
||||
|
||||
if (fit_start_sector % (1<<(PAGE_SHIFT - SECTOR_SHIFT)))
|
||||
return -ERANGE;
|
||||
|
||||
page = read_mapping_page(mapping, fit_start_sector >> (PAGE_SHIFT - SECTOR_SHIFT), NULL);
|
||||
if (IS_ERR(page))
|
||||
return -EFAULT;
|
||||
|
||||
if (PageError(page))
|
||||
return -EFAULT;
|
||||
|
||||
init_fit = page_address(page);
|
||||
|
||||
if (!init_fit) {
|
||||
put_page(page);
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
if (fdt_check_header(init_fit)) {
|
||||
put_page(page);
|
||||
return 0;
|
||||
}
|
||||
|
||||
dsectors = get_capacity(bdev->bd_disk);
|
||||
if (sectors)
|
||||
dsectors = (dsectors>sectors)?sectors:dsectors;
|
||||
|
||||
dsize = dsectors << SECTOR_SHIFT;
|
||||
size = fdt_totalsize(init_fit);
|
||||
|
||||
/* silently skip non-external-data legacy FIT images */
|
||||
if (size > PAGE_SIZE) {
|
||||
put_page(page);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (size >= dsize) {
|
||||
state->access_beyond_eod = 1;
|
||||
put_page(page);
|
||||
return -EFBIG;
|
||||
}
|
||||
|
||||
fit = kmemdup(init_fit, size, GFP_KERNEL);
|
||||
put_page(page);
|
||||
if (!fit)
|
||||
return -ENOMEM;
|
||||
|
||||
np = of_find_node_by_path("/chosen");
|
||||
if (np) {
|
||||
/* new fitblk driver should take over if /chosen/rootdisk is defined */
|
||||
if (of_get_property(np, "rootdisk", NULL))
|
||||
return 0;
|
||||
|
||||
bootconf_c = of_get_property(np, "u-boot,bootconf", &bootconf_len);
|
||||
if (bootconf_c && bootconf_len)
|
||||
bootconf = kmemdup_nul(bootconf_c, bootconf_len, GFP_KERNEL);
|
||||
}
|
||||
|
||||
if (bootconf) {
|
||||
bootconf_term = strchr(bootconf, '#');
|
||||
if (bootconf_term)
|
||||
*bootconf_term = '\0';
|
||||
}
|
||||
|
||||
config = fdt_path_offset(fit, FIT_CONFS_PATH);
|
||||
if (config < 0) {
|
||||
printk(KERN_ERR "FIT: Cannot find %s node: %d\n", FIT_CONFS_PATH, images);
|
||||
ret = -ENOENT;
|
||||
goto ret_out;
|
||||
}
|
||||
|
||||
config_default = fdt_getprop(fit, config, FIT_DEFAULT_PROP, &config_default_len);
|
||||
|
||||
if (!config_default && !bootconf) {
|
||||
printk(KERN_ERR "FIT: Cannot find default configuration\n");
|
||||
ret = -ENOENT;
|
||||
goto ret_out;
|
||||
}
|
||||
|
||||
node = fdt_subnode_offset(fit, config, bootconf?:config_default);
|
||||
if (node < 0) {
|
||||
printk(KERN_ERR "FIT: Cannot find %s node: %d\n", bootconf?:config_default, node);
|
||||
ret = -ENOENT;
|
||||
goto ret_out;
|
||||
}
|
||||
|
||||
config_description = fdt_getprop(fit, node, FIT_DESC_PROP, &config_description_len);
|
||||
config_loadables = fdt_getprop(fit, node, FIT_LOADABLE_PROP, &config_loadables_len);
|
||||
|
||||
printk(KERN_DEBUG "FIT: %s configuration: \"%s\"%s%s%s\n",
|
||||
bootconf?"Selected":"Default", bootconf?:config_default,
|
||||
config_description?" (":"", config_description?:"", config_description?")":"");
|
||||
|
||||
if (!config_loadables || !config_loadables_len) {
|
||||
printk(KERN_ERR "FIT: No loadables configured in \"%s\"\n", bootconf?:config_default);
|
||||
ret = -ENOENT;
|
||||
goto ret_out;
|
||||
}
|
||||
|
||||
images = fdt_path_offset(fit, FIT_IMAGES_PATH);
|
||||
if (images < 0) {
|
||||
printk(KERN_ERR "FIT: Cannot find %s node: %d\n", FIT_IMAGES_PATH, images);
|
||||
ret = -EINVAL;
|
||||
goto ret_out;
|
||||
}
|
||||
|
||||
fdt_for_each_subnode(node, fit, images) {
|
||||
image_name = fdt_get_name(fit, node, &image_name_len);
|
||||
image_type = fdt_getprop(fit, node, FIT_TYPE_PROP, &image_type_len);
|
||||
image_offset_be = fdt_getprop(fit, node, FIT_DATA_OFFSET_PROP, NULL);
|
||||
image_pos_be = fdt_getprop(fit, node, FIT_DATA_POSITION_PROP, NULL);
|
||||
image_len_be = fdt_getprop(fit, node, FIT_DATA_SIZE_PROP, NULL);
|
||||
if (!image_name || !image_type || !image_len_be)
|
||||
continue;
|
||||
|
||||
image_len = be32_to_cpu(*image_len_be);
|
||||
if (!image_len)
|
||||
continue;
|
||||
|
||||
if (image_offset_be)
|
||||
image_pos = be32_to_cpu(*image_offset_be) + size;
|
||||
else if (image_pos_be)
|
||||
image_pos = be32_to_cpu(*image_pos_be);
|
||||
else
|
||||
continue;
|
||||
|
||||
image_description = fdt_getprop(fit, node, FIT_DESC_PROP, &image_description_len);
|
||||
|
||||
printk(KERN_DEBUG "FIT: %16s sub-image 0x%08x..0x%08x \"%s\" %s%s%s\n",
|
||||
image_type, image_pos, image_pos + image_len - 1, image_name,
|
||||
image_description?"(":"", image_description?:"", image_description?") ":"");
|
||||
|
||||
if (strcmp(image_type, FIT_FILESYSTEM_PROP))
|
||||
continue;
|
||||
|
||||
/* check if sub-image is part of configured loadables */
|
||||
found = false;
|
||||
loadable = config_loadables;
|
||||
loadables_rem_len = config_loadables_len;
|
||||
while (loadables_rem_len > 1) {
|
||||
loadable_len = strnlen(loadable, loadables_rem_len - 1) + 1;
|
||||
loadables_rem_len -= loadable_len;
|
||||
if (!strncmp(image_name, loadable, loadable_len)) {
|
||||
found = true;
|
||||
break;
|
||||
}
|
||||
loadable += loadable_len;
|
||||
}
|
||||
if (!found)
|
||||
continue;
|
||||
|
||||
if (image_pos & ((1 << PAGE_SHIFT)-1)) {
|
||||
printk(KERN_ERR "FIT: image %s start not aligned to page boundaries, skipping\n", image_name);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (image_len & ((1 << PAGE_SHIFT)-1)) {
|
||||
printk(KERN_ERR "FIT: sub-image %s end not aligned to page boundaries, skipping\n", image_name);
|
||||
continue;
|
||||
}
|
||||
|
||||
start_sect = image_pos >> SECTOR_SHIFT;
|
||||
nr_sects = image_len >> SECTOR_SHIFT;
|
||||
imgmaxsect = (imgmaxsect < (start_sect + nr_sects))?(start_sect + nr_sects):imgmaxsect;
|
||||
|
||||
if (start_sect + nr_sects > dsectors) {
|
||||
state->access_beyond_eod = 1;
|
||||
continue;
|
||||
}
|
||||
|
||||
put_partition(state, ++(*slot), fit_start_sector + start_sect, nr_sects);
|
||||
state->parts[*slot].flags = ADDPART_FLAG_READONLY;
|
||||
state->parts[*slot].has_info = true;
|
||||
info = &state->parts[*slot].info;
|
||||
|
||||
label_min = min_t(int, sizeof(info->volname) - 1, image_name_len);
|
||||
strncpy(info->volname, image_name, label_min);
|
||||
info->volname[label_min] = '\0';
|
||||
|
||||
snprintf(tmp, sizeof(tmp), "(%s)", info->volname);
|
||||
strlcat(state->pp_buf, tmp, PAGE_SIZE);
|
||||
|
||||
/* Mark first loadable listed to be mounted as rootfs */
|
||||
if (!strcmp(image_name, config_loadables)) {
|
||||
select_rootfs = image_name;
|
||||
state->parts[*slot].flags |= ADDPART_FLAG_ROOTDEV;
|
||||
}
|
||||
}
|
||||
|
||||
if (select_rootfs)
|
||||
printk(KERN_DEBUG "FIT: selecting configured loadable \"%s\" to be root filesystem\n", select_rootfs);
|
||||
|
||||
if (add_remain && (imgmaxsect + MIN_FREE_SECT) < dsectors) {
|
||||
put_partition(state, ++(*slot), fit_start_sector + imgmaxsect, dsectors - imgmaxsect);
|
||||
state->parts[*slot].flags = 0;
|
||||
info = &state->parts[*slot].info;
|
||||
strcpy(info->volname, REMAIN_VOLNAME);
|
||||
snprintf(tmp, sizeof(tmp), "(%s)", REMAIN_VOLNAME);
|
||||
strlcat(state->pp_buf, tmp, PAGE_SIZE);
|
||||
}
|
||||
ret_out:
|
||||
kfree(bootconf);
|
||||
kfree(fit);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int fit_partition(struct parsed_partitions *state) {
|
||||
int slot = 0;
|
||||
return parse_fit_partitions(state, 0, 0, &slot, 0);
|
||||
}
|
||||
|
|
@ -500,3 +500,4 @@ CONFIG_ZSTD_DECOMPRESS=y
|
|||
# CONFIG_MTD_SPLIT_SEIL_FW is not set
|
||||
CONFIG_ARM64_PLATFORM_DEVICES=y
|
||||
CONFIG_MTK_SOCINFO=y
|
||||
# CONFIG_PHY_MTK_MIPI_CSI_0_5 is not set
|
||||
|
|
|
|||
|
|
@ -1,216 +0,0 @@
|
|||
From 69357074558daf6ff24c9f58714935e9e095a865 Mon Sep 17 00:00:00 2001
|
||||
From: OpenWrt community <openwrt-devel@lists.openwrt.org>
|
||||
Date: Wed, 13 Jul 2022 13:37:33 +0200
|
||||
Subject: [PATCH] kernel: add block fit partition parser
|
||||
|
||||
---
|
||||
block/blk.h | 2 ++
|
||||
block/partitions/Kconfig | 7 +++++++
|
||||
block/partitions/Makefile | 1 +
|
||||
block/partitions/check.h | 3 +++
|
||||
block/partitions/core.c | 17 +++++++++++++++++
|
||||
block/partitions/efi.c | 8 ++++++++
|
||||
block/partitions/efi.h | 3 +++
|
||||
block/partitions/msdos.c | 10 ++++++++++
|
||||
drivers/mtd/mtd_blkdevs.c | 2 ++
|
||||
drivers/mtd/ubi/block.c | 3 +++
|
||||
include/linux/msdos_partition.h | 1 +
|
||||
11 files changed, 57 insertions(+)
|
||||
|
||||
--- a/block/blk.h
|
||||
+++ b/block/blk.h
|
||||
@@ -424,6 +424,8 @@ void blk_free_ext_minor(unsigned int min
|
||||
#define ADDPART_FLAG_NONE 0
|
||||
#define ADDPART_FLAG_RAID 1
|
||||
#define ADDPART_FLAG_WHOLEDISK 2
|
||||
+#define ADDPART_FLAG_READONLY 4
|
||||
+#define ADDPART_FLAG_ROOTDEV 8
|
||||
int bdev_add_partition(struct gendisk *disk, int partno, sector_t start,
|
||||
sector_t length);
|
||||
int bdev_del_partition(struct gendisk *disk, int partno);
|
||||
--- a/block/partitions/Kconfig
|
||||
+++ b/block/partitions/Kconfig
|
||||
@@ -103,6 +103,13 @@ config ATARI_PARTITION
|
||||
Say Y here if you would like to use hard disks under Linux which
|
||||
were partitioned under the Atari OS.
|
||||
|
||||
+config FIT_PARTITION
|
||||
+ bool "Flattened-Image-Tree (FIT) partition support" if PARTITION_ADVANCED
|
||||
+ default n
|
||||
+ help
|
||||
+ Say Y here if your system needs to mount the filesystem part of
|
||||
+ a Flattened-Image-Tree (FIT) image commonly used with Das U-Boot.
|
||||
+
|
||||
config IBM_PARTITION
|
||||
bool "IBM disk label and partition support"
|
||||
depends on PARTITION_ADVANCED && S390
|
||||
--- a/block/partitions/Makefile
|
||||
+++ b/block/partitions/Makefile
|
||||
@@ -8,6 +8,7 @@ obj-$(CONFIG_ACORN_PARTITION) += acorn.o
|
||||
obj-$(CONFIG_AMIGA_PARTITION) += amiga.o
|
||||
obj-$(CONFIG_ATARI_PARTITION) += atari.o
|
||||
obj-$(CONFIG_AIX_PARTITION) += aix.o
|
||||
+obj-$(CONFIG_FIT_PARTITION) += fit.o
|
||||
obj-$(CONFIG_CMDLINE_PARTITION) += cmdline.o
|
||||
obj-$(CONFIG_MAC_PARTITION) += mac.o
|
||||
obj-$(CONFIG_LDM_PARTITION) += ldm.o
|
||||
--- a/block/partitions/check.h
|
||||
+++ b/block/partitions/check.h
|
||||
@@ -57,6 +57,7 @@ int amiga_partition(struct parsed_partit
|
||||
int atari_partition(struct parsed_partitions *state);
|
||||
int cmdline_partition(struct parsed_partitions *state);
|
||||
int efi_partition(struct parsed_partitions *state);
|
||||
+int fit_partition(struct parsed_partitions *state);
|
||||
int ibm_partition(struct parsed_partitions *);
|
||||
int karma_partition(struct parsed_partitions *state);
|
||||
int ldm_partition(struct parsed_partitions *state);
|
||||
@@ -67,3 +68,5 @@ int sgi_partition(struct parsed_partitio
|
||||
int sun_partition(struct parsed_partitions *state);
|
||||
int sysv68_partition(struct parsed_partitions *state);
|
||||
int ultrix_partition(struct parsed_partitions *state);
|
||||
+
|
||||
+int parse_fit_partitions(struct parsed_partitions *state, u64 start_sector, u64 nr_sectors, int *slot, int add_remain);
|
||||
--- a/block/partitions/core.c
|
||||
+++ b/block/partitions/core.c
|
||||
@@ -11,6 +11,9 @@
|
||||
#include <linux/vmalloc.h>
|
||||
#include <linux/raid/detect.h>
|
||||
#include <linux/property.h>
|
||||
+#ifdef CONFIG_FIT_PARTITION
|
||||
+#include <linux/root_dev.h>
|
||||
+#endif
|
||||
|
||||
#include "check.h"
|
||||
|
||||
@@ -48,6 +51,9 @@ static int (*const check_part[])(struct
|
||||
#ifdef CONFIG_EFI_PARTITION
|
||||
efi_partition, /* this must come before msdos */
|
||||
#endif
|
||||
+#ifdef CONFIG_FIT_PARTITION
|
||||
+ fit_partition,
|
||||
+#endif
|
||||
#ifdef CONFIG_SGI_PARTITION
|
||||
sgi_partition,
|
||||
#endif
|
||||
@@ -430,6 +436,11 @@ static struct block_device *add_partitio
|
||||
goto out_del;
|
||||
}
|
||||
|
||||
+#ifdef CONFIG_FIT_PARTITION
|
||||
+ if (flags & ADDPART_FLAG_READONLY)
|
||||
+ bdev->bd_read_only = true;
|
||||
+#endif
|
||||
+
|
||||
/* everything is up and running, commence */
|
||||
err = xa_insert(&disk->part_tbl, partno, bdev, GFP_KERNEL);
|
||||
if (err)
|
||||
@@ -622,6 +633,11 @@ static bool blk_add_partition(struct gen
|
||||
(state->parts[p].flags & ADDPART_FLAG_RAID))
|
||||
md_autodetect_dev(part->bd_dev);
|
||||
|
||||
+#ifdef CONFIG_FIT_PARTITION
|
||||
+ if ((state->parts[p].flags & ADDPART_FLAG_ROOTDEV) && ROOT_DEV == 0)
|
||||
+ ROOT_DEV = part->bd_dev;
|
||||
+#endif
|
||||
+
|
||||
return true;
|
||||
}
|
||||
|
||||
--- a/block/partitions/efi.c
|
||||
+++ b/block/partitions/efi.c
|
||||
@@ -716,6 +716,9 @@ int efi_partition(struct parsed_partitio
|
||||
gpt_entry *ptes = NULL;
|
||||
u32 i;
|
||||
unsigned ssz = queue_logical_block_size(state->disk->queue) / 512;
|
||||
+#ifdef CONFIG_FIT_PARTITION
|
||||
+ u32 extra_slot = 64;
|
||||
+#endif
|
||||
|
||||
if (!find_valid_gpt(state, &gpt, &ptes) || !gpt || !ptes) {
|
||||
kfree(gpt);
|
||||
@@ -749,6 +752,11 @@ int efi_partition(struct parsed_partitio
|
||||
ARRAY_SIZE(ptes[i].partition_name));
|
||||
utf16_le_to_7bit(ptes[i].partition_name, label_max, info->volname);
|
||||
state->parts[i + 1].has_info = true;
|
||||
+#ifdef CONFIG_FIT_PARTITION
|
||||
+ /* If this is a U-Boot FIT volume it may have subpartitions */
|
||||
+ if (!efi_guidcmp(ptes[i].partition_type_guid, PARTITION_LINUX_FIT_GUID))
|
||||
+ (void) parse_fit_partitions(state, start * ssz, size * ssz, &extra_slot, 1);
|
||||
+#endif
|
||||
}
|
||||
kfree(ptes);
|
||||
kfree(gpt);
|
||||
--- a/block/partitions/efi.h
|
||||
+++ b/block/partitions/efi.h
|
||||
@@ -51,6 +51,9 @@
|
||||
#define PARTITION_LINUX_LVM_GUID \
|
||||
EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \
|
||||
0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28)
|
||||
+#define PARTITION_LINUX_FIT_GUID \
|
||||
+ EFI_GUID( 0xcae9be83, 0xb15f, 0x49cc, \
|
||||
+ 0x86, 0x3f, 0x08, 0x1b, 0x74, 0x4a, 0x2d, 0x93)
|
||||
|
||||
typedef struct _gpt_header {
|
||||
__le64 signature;
|
||||
--- a/block/partitions/msdos.c
|
||||
+++ b/block/partitions/msdos.c
|
||||
@@ -564,6 +564,15 @@ static void parse_minix(struct parsed_pa
|
||||
#endif /* CONFIG_MINIX_SUBPARTITION */
|
||||
}
|
||||
|
||||
+static void parse_fit_mbr(struct parsed_partitions *state,
|
||||
+ sector_t offset, sector_t size, int origin)
|
||||
+{
|
||||
+#ifdef CONFIG_FIT_PARTITION
|
||||
+ u32 extra_slot = 64;
|
||||
+ (void) parse_fit_partitions(state, offset, size, &extra_slot, 1);
|
||||
+#endif /* CONFIG_FIT_PARTITION */
|
||||
+}
|
||||
+
|
||||
static struct {
|
||||
unsigned char id;
|
||||
void (*parse)(struct parsed_partitions *, sector_t, sector_t, int);
|
||||
@@ -575,6 +584,7 @@ static struct {
|
||||
{UNIXWARE_PARTITION, parse_unixware},
|
||||
{SOLARIS_X86_PARTITION, parse_solaris_x86},
|
||||
{NEW_SOLARIS_X86_PARTITION, parse_solaris_x86},
|
||||
+ {FIT_PARTITION, parse_fit_mbr},
|
||||
{0, NULL},
|
||||
};
|
||||
|
||||
--- a/drivers/mtd/mtd_blkdevs.c
|
||||
+++ b/drivers/mtd/mtd_blkdevs.c
|
||||
@@ -359,7 +359,9 @@ int add_mtd_blktrans_dev(struct mtd_blkt
|
||||
} else {
|
||||
snprintf(gd->disk_name, sizeof(gd->disk_name),
|
||||
"%s%d", tr->name, new->devnum);
|
||||
- gd->flags |= GENHD_FL_NO_PART;
|
||||
+
|
||||
+ if (!IS_ENABLED(CONFIG_FIT_PARTITION) || mtd_type_is_nand(new->mtd))
|
||||
+ gd->flags |= GENHD_FL_NO_PART;
|
||||
}
|
||||
|
||||
set_capacity(gd, ((u64)new->size * tr->blksize) >> 9);
|
||||
--- a/drivers/mtd/ubi/block.c
|
||||
+++ b/drivers/mtd/ubi/block.c
|
||||
@@ -410,7 +410,9 @@ int ubiblock_create(struct ubi_volume_in
|
||||
ret = -ENODEV;
|
||||
goto out_cleanup_disk;
|
||||
}
|
||||
- gd->flags |= GENHD_FL_NO_PART;
|
||||
+ if (!IS_ENABLED(CONFIG_FIT_PARTITION))
|
||||
+ gd->flags |= GENHD_FL_NO_PART;
|
||||
+
|
||||
gd->private_data = dev;
|
||||
sprintf(gd->disk_name, "ubiblock%d_%d", dev->ubi_num, dev->vol_id);
|
||||
set_capacity(gd, disk_capacity);
|
||||
--- a/include/linux/msdos_partition.h
|
||||
+++ b/include/linux/msdos_partition.h
|
||||
@@ -31,6 +31,7 @@ enum msdos_sys_ind {
|
||||
LINUX_LVM_PARTITION = 0x8e,
|
||||
LINUX_RAID_PARTITION = 0xfd, /* autodetect RAID partition */
|
||||
|
||||
+ FIT_PARTITION = 0x2e, /* U-Boot uImage.FIT */
|
||||
SOLARIS_X86_PARTITION = 0x82, /* also Linux swap partitions */
|
||||
NEW_SOLARIS_X86_PARTITION = 0xbf,
|
||||
|
||||
|
|
@ -1,28 +0,0 @@
|
|||
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
|
||||
@@ -145,9 +145,9 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
- switch@0 {
|
||||
+ switch@1f {
|
||||
compatible = "mediatek,mt7531";
|
||||
- reg = <0>;
|
||||
+ reg = <31>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&pio>;
|
||||
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
|
||||
@@ -117,9 +117,9 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
- switch@0 {
|
||||
+ switch@1f {
|
||||
compatible = "mediatek,mt7531";
|
||||
- reg = <0>;
|
||||
+ reg = <31>;
|
||||
reset-gpios = <&pio 54 0>;
|
||||
|
||||
ports {
|
||||
|
|
@ -1,196 +0,0 @@
|
|||
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
|
||||
@@ -23,6 +23,10 @@
|
||||
serial0 = &uart0;
|
||||
ethernet0 = &gmac0;
|
||||
ethernet1 = &gmac1;
|
||||
+ led-boot = &green_led;
|
||||
+ led-failsafe = &green_led;
|
||||
+ led-running = &green_led;
|
||||
+ led-upgrade = &blue_led;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@@ -419,27 +423,27 @@
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
- label = "lan0";
|
||||
+ label = "lan1";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
- label = "lan1";
|
||||
+ label = "lan2";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
- label = "lan2";
|
||||
+ label = "lan3";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
- label = "lan3";
|
||||
+ label = "lan4";
|
||||
};
|
||||
|
||||
port5: port@5 {
|
||||
reg = <5>;
|
||||
- label = "lan4";
|
||||
+ label = "sfp2";
|
||||
phy-mode = "2500base-x";
|
||||
sfp = <&sfp2>;
|
||||
managed = "in-band-status";
|
||||
@@ -490,9 +494,137 @@
|
||||
|
||||
&wifi {
|
||||
status = "okay";
|
||||
- pinctrl-names = "default", "dbdc";
|
||||
+ pinctrl-names = "default";
|
||||
pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
|
||||
- pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
|
||||
+
|
||||
+ mediatek,eeprom-data = <0x86790900 0x000c4326 0x60000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x01000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000800 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x24649090 0x00280000 0x05100000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00021e00 0x021e0002 0x1e00021e 0x00022800 0x02280002 0x28000228 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00008080 0x8080fdf7
|
||||
+ 0x0903150d 0x80808080 0x80808080 0x05050d0d 0x1313c6c6 0xc3c3c200 0x00c200c2 0x00008182
|
||||
+ 0x8585c2c2 0x82828282 0x858500c2 0xc2000081 0x82858587 0x87c2c200 0x81818285 0x858787c2
|
||||
+ 0xc2000081 0x82858587 0x87c2c200 0x00818285 0x858787c2 0xc2000081 0x82858587 0x87c4c4c2
|
||||
+ 0xc100c300 0xc3c3c100 0x818383c3 0xc3c3c100 0x81838300 0xc2c2c2c0 0x81828484 0x000000c3
|
||||
+ 0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x838686c2 0xc2c2c081 0x82848486 0x86c3c3c3
|
||||
+ 0xc1008183 0x838686c3 0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x83868622 0x28002228
|
||||
+ 0x00222800 0x22280000 0xdddddddd 0xdddddddd 0xddbbbbbb 0xccccccdd 0xdddddddd 0xdddddddd
|
||||
+ 0xeeeeeecc 0xccccdddd 0xdddddddd 0x004a5662 0x0000004a 0x56620000 0x004a5662 0x0000004a
|
||||
+ 0x56620000 0x88888888 0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600
|
||||
+ 0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600 0x00000000 0xf0f0cc00
|
||||
+ 0x00000000 0x0000aaaa 0xaabbbbbb 0xcccccccc 0xccccbbbb 0xbbbbbbbb 0xbbbbbbaa 0xaaaabbbb
|
||||
+ 0xbbaaaaaa 0x999999aa 0xaaaabbbb 0xbbcccccc 0x00000000 0x0000aaaa 0xaa000000 0xbbbbbbbb
|
||||
+ 0xbbbbaaaa 0xaa999999 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb
|
||||
+ 0x00000000 0x00000000 0x00000000 0x99999999 0x9999aaaa 0xaaaaaaaa 0x999999aa 0xaaaaaaaa
|
||||
+ 0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb 0x00000000 0x0000eeee 0xeeffffff 0xcccccccc
|
||||
+ 0xccccdddd 0xddbbbbbb 0xccccccbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbcccc 0xccdddddd
|
||||
+ 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051
|
||||
+ 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200
|
||||
+ 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e
|
||||
+ 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051
|
||||
+ 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200
|
||||
+ 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e
|
||||
+ 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000001 0x06000100 0x01050002 0x00ff0300
|
||||
+ 0xf900fe03 0x00000000 0x00000000 0x0000009b 0x6e370000 0x00000000 0x00fc0009 0x0a00fe00
|
||||
+ 0x060700fe 0x00070800 0x05000b0a 0x00000000 0x00000000 0x000000e2 0x96460000 0x00000000
|
||||
+ 0x000400f7 0xf8000300 0xfcfe0003 0x00fbfc00 0xee00e3f2 0x00000000 0x00000000 0x00000011
|
||||
+ 0xbb550000 0x00000000 0x000600f6 0xfc000300 0xfbfe0004 0x00fafe00 0xf600ecf2 0x00000000
|
||||
+ 0x00000000 0x0000001f 0xbf580000 0x00000000 0x000600f5 0xf6000400 0xf8f90004 0x00f7f800
|
||||
+ 0xf700f0f4 0x00000000 0x00000000 0x00000024 0xbe570000 0x00000000 0x000800f8 0xfe000600
|
||||
+ 0xf8fd0007 0x00f9fe00 0xf500f0f4 0x00000000 0x00000000 0x0000002d 0xd6610000 0x00000000
|
||||
+ 0x000400f7 0xfc000500 0xf7fc0005 0x00f7fc00 0xf900f5f8 0x00000000 0x00000000 0x00000026
|
||||
+ 0xd96e0000 0x00000000 0x000400f7 0xf9000600 0xf5f70005 0x00f5f800 0xf900f4f7 0x00000000
|
||||
+ 0x00000000 0x0000001b 0xce690000 0x00000000 0x000300f8 0xf8000600 0xf6f60004 0x00f6f700
|
||||
+ 0xf900f4f7 0x00000000 0x00000000 0x00000018 0xd8720000 0x00000000 0x00000000 0x02404002
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0xc1c2c1c2 0x41c341c3 0x3fc13fc1 0x40c13fc2 0x3fc240c1 0x41c040c0 0x3fc23fc2 0x40c13fc2
|
||||
+ 0x3fc140c0 0x41c040c0 0x3fc33fc3 0x40c23fc2 0x3fc240c1 0x41c040c0 0x3fc23fc2 0x40c23fc2
|
||||
+ 0x3fc140c1 0x41c040c0 0x00000000 0x00000000 0x41c741c7 0xc1c7c1c7 0x00000000 0x00000000
|
||||
+ 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0
|
||||
+ 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0
|
||||
+ 0x00a0ce00 0x00000000 0xb6840000 0x00000000 0x00000000 0x00000000 0x18181818 0x18181818
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x004b5763 0x0000004b 0x57630000 0x004b5763 0x0000004b 0x57630000 0x88888888 0x08474759
|
||||
+ 0x69780849 0x49596d7a 0x0849495a 0x6d790848 0x48596c78 0x08484858 0x6a780848 0x48586a78
|
||||
+ 0x08484858 0x6c78084a 0x4a5b6d79 0x08474759 0x697a0848 0x48596b79 0x08484859 0x6c7a0848
|
||||
+ 0x48586c79 0x08484857 0x68770848 0x48576877 0x08484857 0x6a77084a 0x4a5a6a77 0x08464659
|
||||
+ 0x69790848 0x48586b79 0x08484858 0x6c7a0848 0x48596c79 0x08484857 0x68770848 0x48576877
|
||||
+ 0x08494958 0x6d7a084b 0x4b5c6c77 0x0847475a 0x6a7b0849 0x495a6e7c 0x0849495a 0x6e7c0849
|
||||
+ 0x495b6e7c 0x08494959 0x6a7a0849 0x49596a7a 0x084a4a5a 0x6f7d084b 0x4b5c6e7b 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x85848484
|
||||
+ 0xc3c4c4c5 0xc4c3c33f 0xc3c3c2c2 0xc2c2c03f 0xc3c3c3c4 0xc4c4c33f 0xc2c2c2c2 0xc1c3c1c1
|
||||
+ 0xc0c08282 0x83848686 0x88880000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00001111 0x00000000
|
||||
+ 0x8080f703 0x10808080 0x80050d13 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x000000a4 0xce000000 0x0000b684 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
|
||||
|
||||
led {
|
||||
led-active-low;
|
||||
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
|
||||
@@ -55,6 +55,7 @@
|
||||
partition@c00000 {
|
||||
label = "fit";
|
||||
reg = <0xc00000 0x1400000>;
|
||||
+ compatible = "denx,fit";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,131 +0,0 @@
|
|||
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso
|
||||
@@ -23,7 +23,27 @@
|
||||
no-sd;
|
||||
no-sdio;
|
||||
status = "okay";
|
||||
+
|
||||
+ card@0 {
|
||||
+ compatible = "mmc-card";
|
||||
+ reg = <0>;
|
||||
+
|
||||
+ block {
|
||||
+ compatible = "block-device";
|
||||
+ partitions {
|
||||
+ emmc_rootdisk: block-partition-production {
|
||||
+ partname = "production";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
};
|
||||
-};
|
||||
|
||||
+ fragment@1 {
|
||||
+ target-path = "/chosen";
|
||||
+ __overlay__ {
|
||||
+ rootdisk-emmc = <&emmc_rootdisk>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso
|
||||
@@ -29,27 +29,30 @@
|
||||
|
||||
partition@0 {
|
||||
label = "bl2";
|
||||
- reg = <0x0 0x100000>;
|
||||
+ reg = <0x0 0x200000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
- partition@100000 {
|
||||
- label = "reserved";
|
||||
- reg = <0x100000 0x280000>;
|
||||
- };
|
||||
-
|
||||
- partition@380000 {
|
||||
- label = "fip";
|
||||
- reg = <0x380000 0x200000>;
|
||||
- read-only;
|
||||
- };
|
||||
-
|
||||
- partition@580000 {
|
||||
+ partition@200000 {
|
||||
label = "ubi";
|
||||
- reg = <0x580000 0x7a80000>;
|
||||
+ reg = <0x200000 0x7e00000>;
|
||||
+ compatible = "linux,ubi";
|
||||
+
|
||||
+ volumes {
|
||||
+ nand_rootdisk: ubi-volume-fit {
|
||||
+ volname = "fit";
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
+
|
||||
+ fragment@1 {
|
||||
+ target-path = "/chosen";
|
||||
+ __overlay__ {
|
||||
+ rootdisk-spim-nand = <&nand_rootdisk>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
|
||||
@@ -52,7 +52,7 @@
|
||||
reg = <0x180000 0xa80000>;
|
||||
};
|
||||
|
||||
- partition@c00000 {
|
||||
+ nor_rootdisk: partition@c00000 {
|
||||
label = "fit";
|
||||
reg = <0xc00000 0x1400000>;
|
||||
compatible = "denx,fit";
|
||||
@@ -61,4 +61,11 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
+
|
||||
+ fragment@1 {
|
||||
+ target-path = "/chosen";
|
||||
+ __overlay__ {
|
||||
+ rootdisk-nor = <&nor_rootdisk>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso
|
||||
@@ -17,6 +17,27 @@
|
||||
max-frequency = <52000000>;
|
||||
cap-sd-highspeed;
|
||||
status = "okay";
|
||||
+
|
||||
+ card@0 {
|
||||
+ compatible = "mmc-card";
|
||||
+ reg = <0>;
|
||||
+
|
||||
+ block {
|
||||
+ compatible = "block-device";
|
||||
+ partitions {
|
||||
+ sd_rootdisk: block-partition-production {
|
||||
+ partname = "production";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ fragment@1 {
|
||||
+ target-path = "/chosen";
|
||||
+ __overlay__ {
|
||||
+ rootdisk-sd = <&sd_rootdisk>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,65 +0,0 @@
|
|||
From 11db447f257231e08065989100311df57b7f1f1c Mon Sep 17 00:00:00 2001
|
||||
From: Daniel Golle <daniel@makrotopia.org>
|
||||
Date: Sat, 26 Aug 2023 21:06:14 +0100
|
||||
Subject: [PATCH] pinctrl: mediatek: mt7981: add additional uart groups
|
||||
|
||||
Add uart2_0_tx_rx (pin 4, 5) and uart1_2 (pins 9, 10) groups.
|
||||
|
||||
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||
---
|
||||
drivers/pinctrl/mediatek/pinctrl-mt7981.c | 16 +++++++++++++---
|
||||
1 file changed, 13 insertions(+), 3 deletions(-)
|
||||
|
||||
--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
|
||||
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
|
||||
@@ -611,6 +611,9 @@ static int mt7981_wo0_jtag_1_funcs[] = {
|
||||
static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
|
||||
static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
|
||||
|
||||
+static int mt7981_uart2_0_tx_rx_pins[] = { 4, 5, };
|
||||
+static int mt7981_uart2_0_tx_rx_funcs[] = { 3, 3, };
|
||||
+
|
||||
/* GBE_LED0 */
|
||||
static int mt7981_gbe_led0_pins[] = { 8, };
|
||||
static int mt7981_gbe_led0_funcs[] = { 3, };
|
||||
@@ -731,6 +734,9 @@ static int mt7981_uart1_0_funcs[] = { 4,
|
||||
static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
|
||||
static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
|
||||
|
||||
+static int mt7981_uart1_2_pins[] = { 9, 10, };
|
||||
+static int mt7981_uart1_2_funcs[] = { 2, 2, };
|
||||
+
|
||||
/* UART2 */
|
||||
static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
|
||||
static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
|
||||
@@ -805,6 +811,8 @@ static const struct group_desc mt7981_gr
|
||||
PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0),
|
||||
/* @GPIO(4,7) WM_JTAG(3) */
|
||||
PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0),
|
||||
+ /* @GPIO(4,5) WM_JTAG(4) */
|
||||
+ PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7981_uart2_0_tx_rx),
|
||||
/* @GPIO(8) GBE_LED0(3) */
|
||||
PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0),
|
||||
/* @GPIO(4,6) PTA_EXT(4) */
|
||||
@@ -861,6 +869,8 @@ static const struct group_desc mt7981_gr
|
||||
PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0),
|
||||
/* @GPIO(26,29): UART1(2) */
|
||||
PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
|
||||
+ /* @GPIO(9,10): UART1(2) */
|
||||
+ PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2),
|
||||
/* @GPIO(22,25): UART1(3) */
|
||||
PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1),
|
||||
/* @GPIO(22,24) PTA_EXT(4) */
|
||||
@@ -922,9 +932,9 @@ static const struct group_desc mt7981_gr
|
||||
*/
|
||||
static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1",
|
||||
"wa_aice3", "wm_aice1_2", };
|
||||
-static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0",
|
||||
- "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2",
|
||||
- "uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", };
|
||||
+static const char *mt7981_uart_groups[] = { "net_wo0_uart_txd_0", "net_wo0_uart_txd_1",
|
||||
+ "net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart2_0",
|
||||
+ "uart2_0_tx_rx", "uart2_1", "wm_uart_0", "wm_aurt_1", "wm_aurt_2", };
|
||||
static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
|
||||
static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
|
||||
static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", };
|
||||
|
|
@ -1,113 +0,0 @@
|
|||
From 94b0f301f6ee92f79a2fe2c655dfdbdfe2aec536 Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
|
||||
Date: Sun, 19 Nov 2023 22:24:16 +0100
|
||||
Subject: [PATCH] dt-bindings: arm: mediatek: move ethsys controller & convert
|
||||
to DT schema
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
DT schema helps validating DTS files. Binding was moved to clock/ as
|
||||
this hardware is a clock provider. Example required a small fix for
|
||||
"reg" value (1 address cell + 1 size cell).
|
||||
|
||||
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
Reviewed-by: Rob Herring <robh@kernel.org>
|
||||
Link: https://lore.kernel.org/r/20231119212416.2682-1-zajec5@gmail.com
|
||||
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
||||
---
|
||||
.../bindings/arm/mediatek/mediatek,ethsys.txt | 29 ----------
|
||||
.../bindings/clock/mediatek,ethsys.yaml | 54 +++++++++++++++++++
|
||||
2 files changed, 54 insertions(+), 29 deletions(-)
|
||||
delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
|
||||
create mode 100644 Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
|
||||
|
||||
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
|
||||
+++ /dev/null
|
||||
@@ -1,29 +0,0 @@
|
||||
-Mediatek ethsys controller
|
||||
-============================
|
||||
-
|
||||
-The Mediatek ethsys controller provides various clocks to the system.
|
||||
-
|
||||
-Required Properties:
|
||||
-
|
||||
-- compatible: Should be:
|
||||
- - "mediatek,mt2701-ethsys", "syscon"
|
||||
- - "mediatek,mt7622-ethsys", "syscon"
|
||||
- - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
|
||||
- - "mediatek,mt7629-ethsys", "syscon"
|
||||
- - "mediatek,mt7981-ethsys", "syscon"
|
||||
- - "mediatek,mt7986-ethsys", "syscon"
|
||||
-- #clock-cells: Must be 1
|
||||
-- #reset-cells: Must be 1
|
||||
-
|
||||
-The ethsys controller uses the common clk binding from
|
||||
-Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
-The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
-
|
||||
-Example:
|
||||
-
|
||||
-ethsys: clock-controller@1b000000 {
|
||||
- compatible = "mediatek,mt2701-ethsys", "syscon";
|
||||
- reg = <0 0x1b000000 0 0x1000>;
|
||||
- #clock-cells = <1>;
|
||||
- #reset-cells = <1>;
|
||||
-};
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
|
||||
@@ -0,0 +1,54 @@
|
||||
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
+%YAML 1.2
|
||||
+---
|
||||
+$id: http://devicetree.org/schemas/clock/mediatek,ethsys.yaml#
|
||||
+$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
+
|
||||
+title: Mediatek ethsys controller
|
||||
+
|
||||
+description:
|
||||
+ The available clocks are defined in dt-bindings/clock/mt*-clk.h.
|
||||
+
|
||||
+maintainers:
|
||||
+ - James Liao <jamesjj.liao@mediatek.com>
|
||||
+
|
||||
+properties:
|
||||
+ compatible:
|
||||
+ oneOf:
|
||||
+ - items:
|
||||
+ - enum:
|
||||
+ - mediatek,mt2701-ethsys
|
||||
+ - mediatek,mt7622-ethsys
|
||||
+ - mediatek,mt7629-ethsys
|
||||
+ - mediatek,mt7981-ethsys
|
||||
+ - mediatek,mt7986-ethsys
|
||||
+ - const: syscon
|
||||
+ - items:
|
||||
+ - const: mediatek,mt7623-ethsys
|
||||
+ - const: mediatek,mt2701-ethsys
|
||||
+ - const: syscon
|
||||
+
|
||||
+ reg:
|
||||
+ maxItems: 1
|
||||
+
|
||||
+ "#clock-cells":
|
||||
+ const: 1
|
||||
+
|
||||
+ "#reset-cells":
|
||||
+ const: 1
|
||||
+
|
||||
+required:
|
||||
+ - reg
|
||||
+ - "#clock-cells"
|
||||
+ - "#reset-cells"
|
||||
+
|
||||
+additionalProperties: false
|
||||
+
|
||||
+examples:
|
||||
+ - |
|
||||
+ clock-controller@1b000000 {
|
||||
+ compatible = "mediatek,mt2701-ethsys", "syscon";
|
||||
+ reg = <0x1b000000 0x1000>;
|
||||
+ #clock-cells = <1>;
|
||||
+ #reset-cells = <1>;
|
||||
+ };
|
||||
|
|
@ -1,35 +0,0 @@
|
|||
From 5cfa3beb7761cb84be77225902e018d9d3f9b973 Mon Sep 17 00:00:00 2001
|
||||
From: Daniel Golle <daniel@makrotopia.org>
|
||||
Date: Sun, 17 Dec 2023 21:49:45 +0000
|
||||
Subject: [PATCH 1/4] dt-bindings: reset: mediatek: add MT7988 ethwarp reset
|
||||
IDs
|
||||
|
||||
Add reset ID for ethwarp subsystem allowing to reset the built-in
|
||||
Ethernet switch of the MediaTek MT7988 SoC.
|
||||
|
||||
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
Link: https://lore.kernel.org/r/0c14bbacf471683af67ffa7572bfa1d5c45a0b5d.1702849494.git.daniel@makrotopia.org
|
||||
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
||||
---
|
||||
include/dt-bindings/reset/mediatek,mt7988-resets.h | 13 +++++++++++++
|
||||
1 file changed, 13 insertions(+)
|
||||
create mode 100644 include/dt-bindings/reset/mediatek,mt7988-resets.h
|
||||
|
||||
--- /dev/null
|
||||
+++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h
|
||||
@@ -0,0 +1,13 @@
|
||||
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
+/*
|
||||
+ * Copyright (c) 2023 Daniel Golle <daniel@makrotopia.org>
|
||||
+ * Author: Daniel Golle <daniel@makrotopia.org>
|
||||
+ */
|
||||
+
|
||||
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7988
|
||||
+#define _DT_BINDINGS_RESET_CONTROLLER_MT7988
|
||||
+
|
||||
+/* ETHWARP resets */
|
||||
+#define MT7988_ETHWARP_RST_SWITCH 0
|
||||
+
|
||||
+#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */
|
||||
|
|
@ -1,302 +0,0 @@
|
|||
From 8187e001de156e99ef95366ffd10d627ed090826 Mon Sep 17 00:00:00 2001
|
||||
From: Sam Shih <sam.shih@mediatek.com>
|
||||
Date: Sun, 17 Dec 2023 21:49:33 +0000
|
||||
Subject: [PATCH] dt-bindings: clock: mediatek: add MT7988 clock IDs
|
||||
|
||||
Add MT7988 clock dt-bindings for topckgen, apmixedsys, infracfg,
|
||||
ethernet and xfipll subsystem clocks.
|
||||
|
||||
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
|
||||
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
Link: https://lore.kernel.org/r/27f99db432e9ccc804cc5b6501d7d17d72cae879.1702849494.git.daniel@makrotopia.org
|
||||
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
||||
---
|
||||
.../dt-bindings/clock/mediatek,mt7988-clk.h | 280 ++++++++++++++++++
|
||||
1 file changed, 280 insertions(+)
|
||||
create mode 100644 include/dt-bindings/clock/mediatek,mt7988-clk.h
|
||||
|
||||
--- /dev/null
|
||||
+++ b/include/dt-bindings/clock/mediatek,mt7988-clk.h
|
||||
@@ -0,0 +1,280 @@
|
||||
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
+/*
|
||||
+ * Copyright (c) 2023 MediaTek Inc.
|
||||
+ * Author: Sam Shih <sam.shih@mediatek.com>
|
||||
+ * Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
|
||||
+ */
|
||||
+
|
||||
+#ifndef _DT_BINDINGS_CLK_MT7988_H
|
||||
+#define _DT_BINDINGS_CLK_MT7988_H
|
||||
+
|
||||
+/* APMIXEDSYS */
|
||||
+
|
||||
+#define CLK_APMIXED_NETSYSPLL 0
|
||||
+#define CLK_APMIXED_MPLL 1
|
||||
+#define CLK_APMIXED_MMPLL 2
|
||||
+#define CLK_APMIXED_APLL2 3
|
||||
+#define CLK_APMIXED_NET1PLL 4
|
||||
+#define CLK_APMIXED_NET2PLL 5
|
||||
+#define CLK_APMIXED_WEDMCUPLL 6
|
||||
+#define CLK_APMIXED_SGMPLL 7
|
||||
+#define CLK_APMIXED_ARM_B 8
|
||||
+#define CLK_APMIXED_CCIPLL2_B 9
|
||||
+#define CLK_APMIXED_USXGMIIPLL 10
|
||||
+#define CLK_APMIXED_MSDCPLL 11
|
||||
+
|
||||
+/* TOPCKGEN */
|
||||
+
|
||||
+#define CLK_TOP_XTAL 0
|
||||
+#define CLK_TOP_XTAL_D2 1
|
||||
+#define CLK_TOP_RTC_32K 2
|
||||
+#define CLK_TOP_RTC_32P7K 3
|
||||
+#define CLK_TOP_MPLL_D2 4
|
||||
+#define CLK_TOP_MPLL_D3_D2 5
|
||||
+#define CLK_TOP_MPLL_D4 6
|
||||
+#define CLK_TOP_MPLL_D8 7
|
||||
+#define CLK_TOP_MPLL_D8_D2 8
|
||||
+#define CLK_TOP_MMPLL_D2 9
|
||||
+#define CLK_TOP_MMPLL_D3_D5 10
|
||||
+#define CLK_TOP_MMPLL_D4 11
|
||||
+#define CLK_TOP_MMPLL_D6_D2 12
|
||||
+#define CLK_TOP_MMPLL_D8 13
|
||||
+#define CLK_TOP_APLL2_D4 14
|
||||
+#define CLK_TOP_NET1PLL_D4 15
|
||||
+#define CLK_TOP_NET1PLL_D5 16
|
||||
+#define CLK_TOP_NET1PLL_D5_D2 17
|
||||
+#define CLK_TOP_NET1PLL_D5_D4 18
|
||||
+#define CLK_TOP_NET1PLL_D8 19
|
||||
+#define CLK_TOP_NET1PLL_D8_D2 20
|
||||
+#define CLK_TOP_NET1PLL_D8_D4 21
|
||||
+#define CLK_TOP_NET1PLL_D8_D8 22
|
||||
+#define CLK_TOP_NET1PLL_D8_D16 23
|
||||
+#define CLK_TOP_NET2PLL_D2 24
|
||||
+#define CLK_TOP_NET2PLL_D4 25
|
||||
+#define CLK_TOP_NET2PLL_D4_D4 26
|
||||
+#define CLK_TOP_NET2PLL_D4_D8 27
|
||||
+#define CLK_TOP_NET2PLL_D6 28
|
||||
+#define CLK_TOP_NET2PLL_D8 29
|
||||
+#define CLK_TOP_NETSYS_SEL 30
|
||||
+#define CLK_TOP_NETSYS_500M_SEL 31
|
||||
+#define CLK_TOP_NETSYS_2X_SEL 32
|
||||
+#define CLK_TOP_NETSYS_GSW_SEL 33
|
||||
+#define CLK_TOP_ETH_GMII_SEL 34
|
||||
+#define CLK_TOP_NETSYS_MCU_SEL 35
|
||||
+#define CLK_TOP_NETSYS_PAO_2X_SEL 36
|
||||
+#define CLK_TOP_EIP197_SEL 37
|
||||
+#define CLK_TOP_AXI_INFRA_SEL 38
|
||||
+#define CLK_TOP_UART_SEL 39
|
||||
+#define CLK_TOP_EMMC_250M_SEL 40
|
||||
+#define CLK_TOP_EMMC_400M_SEL 41
|
||||
+#define CLK_TOP_SPI_SEL 42
|
||||
+#define CLK_TOP_SPIM_MST_SEL 43
|
||||
+#define CLK_TOP_NFI1X_SEL 44
|
||||
+#define CLK_TOP_SPINFI_SEL 45
|
||||
+#define CLK_TOP_PWM_SEL 46
|
||||
+#define CLK_TOP_I2C_SEL 47
|
||||
+#define CLK_TOP_PCIE_MBIST_250M_SEL 48
|
||||
+#define CLK_TOP_PEXTP_TL_SEL 49
|
||||
+#define CLK_TOP_PEXTP_TL_P1_SEL 50
|
||||
+#define CLK_TOP_PEXTP_TL_P2_SEL 51
|
||||
+#define CLK_TOP_PEXTP_TL_P3_SEL 52
|
||||
+#define CLK_TOP_USB_SYS_SEL 53
|
||||
+#define CLK_TOP_USB_SYS_P1_SEL 54
|
||||
+#define CLK_TOP_USB_XHCI_SEL 55
|
||||
+#define CLK_TOP_USB_XHCI_P1_SEL 56
|
||||
+#define CLK_TOP_USB_FRMCNT_SEL 57
|
||||
+#define CLK_TOP_USB_FRMCNT_P1_SEL 58
|
||||
+#define CLK_TOP_AUD_SEL 59
|
||||
+#define CLK_TOP_A1SYS_SEL 60
|
||||
+#define CLK_TOP_AUD_L_SEL 61
|
||||
+#define CLK_TOP_A_TUNER_SEL 62
|
||||
+#define CLK_TOP_SSPXTP_SEL 63
|
||||
+#define CLK_TOP_USB_PHY_SEL 64
|
||||
+#define CLK_TOP_USXGMII_SBUS_0_SEL 65
|
||||
+#define CLK_TOP_USXGMII_SBUS_1_SEL 66
|
||||
+#define CLK_TOP_SGM_0_SEL 67
|
||||
+#define CLK_TOP_SGM_SBUS_0_SEL 68
|
||||
+#define CLK_TOP_SGM_1_SEL 69
|
||||
+#define CLK_TOP_SGM_SBUS_1_SEL 70
|
||||
+#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71
|
||||
+#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72
|
||||
+#define CLK_TOP_SYSAXI_SEL 73
|
||||
+#define CLK_TOP_SYSAPB_SEL 74
|
||||
+#define CLK_TOP_ETH_REFCK_50M_SEL 75
|
||||
+#define CLK_TOP_ETH_SYS_200M_SEL 76
|
||||
+#define CLK_TOP_ETH_SYS_SEL 77
|
||||
+#define CLK_TOP_ETH_XGMII_SEL 78
|
||||
+#define CLK_TOP_BUS_TOPS_SEL 79
|
||||
+#define CLK_TOP_NPU_TOPS_SEL 80
|
||||
+#define CLK_TOP_DRAMC_SEL 81
|
||||
+#define CLK_TOP_DRAMC_MD32_SEL 82
|
||||
+#define CLK_TOP_INFRA_F26M_SEL 83
|
||||
+#define CLK_TOP_PEXTP_P0_SEL 84
|
||||
+#define CLK_TOP_PEXTP_P1_SEL 85
|
||||
+#define CLK_TOP_PEXTP_P2_SEL 86
|
||||
+#define CLK_TOP_PEXTP_P3_SEL 87
|
||||
+#define CLK_TOP_DA_XTP_GLB_P0_SEL 88
|
||||
+#define CLK_TOP_DA_XTP_GLB_P1_SEL 89
|
||||
+#define CLK_TOP_DA_XTP_GLB_P2_SEL 90
|
||||
+#define CLK_TOP_DA_XTP_GLB_P3_SEL 91
|
||||
+#define CLK_TOP_CKM_SEL 92
|
||||
+#define CLK_TOP_DA_SEL 93
|
||||
+#define CLK_TOP_PEXTP_SEL 94
|
||||
+#define CLK_TOP_TOPS_P2_26M_SEL 95
|
||||
+#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96
|
||||
+#define CLK_TOP_NETSYS_SYNC_250M_SEL 97
|
||||
+#define CLK_TOP_MACSEC_SEL 98
|
||||
+#define CLK_TOP_NETSYS_TOPS_400M_SEL 99
|
||||
+#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100
|
||||
+#define CLK_TOP_NETSYS_WARP_SEL 101
|
||||
+#define CLK_TOP_ETH_MII_SEL 102
|
||||
+#define CLK_TOP_NPU_SEL 103
|
||||
+#define CLK_TOP_AUD_I2S_M 104
|
||||
+
|
||||
+/* MCUSYS */
|
||||
+
|
||||
+#define CLK_MCU_BUS_DIV_SEL 0
|
||||
+#define CLK_MCU_ARM_DIV_SEL 1
|
||||
+
|
||||
+/* INFRACFG_AO */
|
||||
+
|
||||
+#define CLK_INFRA_MUX_UART0_SEL 0
|
||||
+#define CLK_INFRA_MUX_UART1_SEL 1
|
||||
+#define CLK_INFRA_MUX_UART2_SEL 2
|
||||
+#define CLK_INFRA_MUX_SPI0_SEL 3
|
||||
+#define CLK_INFRA_MUX_SPI1_SEL 4
|
||||
+#define CLK_INFRA_MUX_SPI2_SEL 5
|
||||
+#define CLK_INFRA_PWM_SEL 6
|
||||
+#define CLK_INFRA_PWM_CK1_SEL 7
|
||||
+#define CLK_INFRA_PWM_CK2_SEL 8
|
||||
+#define CLK_INFRA_PWM_CK3_SEL 9
|
||||
+#define CLK_INFRA_PWM_CK4_SEL 10
|
||||
+#define CLK_INFRA_PWM_CK5_SEL 11
|
||||
+#define CLK_INFRA_PWM_CK6_SEL 12
|
||||
+#define CLK_INFRA_PWM_CK7_SEL 13
|
||||
+#define CLK_INFRA_PWM_CK8_SEL 14
|
||||
+#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15
|
||||
+#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16
|
||||
+#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17
|
||||
+#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18
|
||||
+
|
||||
+/* INFRACFG */
|
||||
+
|
||||
+#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19
|
||||
+#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20
|
||||
+#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21
|
||||
+#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22
|
||||
+#define CLK_INFRA_66M_GPT_BCK 23
|
||||
+#define CLK_INFRA_66M_PWM_HCK 24
|
||||
+#define CLK_INFRA_66M_PWM_BCK 25
|
||||
+#define CLK_INFRA_66M_PWM_CK1 26
|
||||
+#define CLK_INFRA_66M_PWM_CK2 27
|
||||
+#define CLK_INFRA_66M_PWM_CK3 28
|
||||
+#define CLK_INFRA_66M_PWM_CK4 29
|
||||
+#define CLK_INFRA_66M_PWM_CK5 30
|
||||
+#define CLK_INFRA_66M_PWM_CK6 31
|
||||
+#define CLK_INFRA_66M_PWM_CK7 32
|
||||
+#define CLK_INFRA_66M_PWM_CK8 33
|
||||
+#define CLK_INFRA_133M_CQDMA_BCK 34
|
||||
+#define CLK_INFRA_66M_AUD_SLV_BCK 35
|
||||
+#define CLK_INFRA_AUD_26M 36
|
||||
+#define CLK_INFRA_AUD_L 37
|
||||
+#define CLK_INFRA_AUD_AUD 38
|
||||
+#define CLK_INFRA_AUD_EG2 39
|
||||
+#define CLK_INFRA_DRAMC_F26M 40
|
||||
+#define CLK_INFRA_133M_DBG_ACKM 41
|
||||
+#define CLK_INFRA_66M_AP_DMA_BCK 42
|
||||
+#define CLK_INFRA_66M_SEJ_BCK 43
|
||||
+#define CLK_INFRA_PRE_CK_SEJ_F13M 44
|
||||
+#define CLK_INFRA_26M_THERM_SYSTEM 45
|
||||
+#define CLK_INFRA_I2C_BCK 46
|
||||
+#define CLK_INFRA_52M_UART0_CK 47
|
||||
+#define CLK_INFRA_52M_UART1_CK 48
|
||||
+#define CLK_INFRA_52M_UART2_CK 49
|
||||
+#define CLK_INFRA_NFI 50
|
||||
+#define CLK_INFRA_SPINFI 51
|
||||
+#define CLK_INFRA_66M_NFI_HCK 52
|
||||
+#define CLK_INFRA_104M_SPI0 53
|
||||
+#define CLK_INFRA_104M_SPI1 54
|
||||
+#define CLK_INFRA_104M_SPI2_BCK 55
|
||||
+#define CLK_INFRA_66M_SPI0_HCK 56
|
||||
+#define CLK_INFRA_66M_SPI1_HCK 57
|
||||
+#define CLK_INFRA_66M_SPI2_HCK 58
|
||||
+#define CLK_INFRA_66M_FLASHIF_AXI 59
|
||||
+#define CLK_INFRA_RTC 60
|
||||
+#define CLK_INFRA_26M_ADC_BCK 61
|
||||
+#define CLK_INFRA_RC_ADC 62
|
||||
+#define CLK_INFRA_MSDC400 63
|
||||
+#define CLK_INFRA_MSDC2_HCK 64
|
||||
+#define CLK_INFRA_133M_MSDC_0_HCK 65
|
||||
+#define CLK_INFRA_66M_MSDC_0_HCK 66
|
||||
+#define CLK_INFRA_133M_CPUM_BCK 67
|
||||
+#define CLK_INFRA_BIST2FPC 68
|
||||
+#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69
|
||||
+#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70
|
||||
+#define CLK_INFRA_133M_USB_HCK 71
|
||||
+#define CLK_INFRA_133M_USB_HCK_CK_P1 72
|
||||
+#define CLK_INFRA_66M_USB_HCK 73
|
||||
+#define CLK_INFRA_66M_USB_HCK_CK_P1 74
|
||||
+#define CLK_INFRA_USB_SYS 75
|
||||
+#define CLK_INFRA_USB_SYS_CK_P1 76
|
||||
+#define CLK_INFRA_USB_REF 77
|
||||
+#define CLK_INFRA_USB_CK_P1 78
|
||||
+#define CLK_INFRA_USB_FRMCNT 79
|
||||
+#define CLK_INFRA_USB_FRMCNT_CK_P1 80
|
||||
+#define CLK_INFRA_USB_PIPE 81
|
||||
+#define CLK_INFRA_USB_PIPE_CK_P1 82
|
||||
+#define CLK_INFRA_USB_UTMI 83
|
||||
+#define CLK_INFRA_USB_UTMI_CK_P1 84
|
||||
+#define CLK_INFRA_USB_XHCI 85
|
||||
+#define CLK_INFRA_USB_XHCI_CK_P1 86
|
||||
+#define CLK_INFRA_PCIE_GFMUX_TL_P0 87
|
||||
+#define CLK_INFRA_PCIE_GFMUX_TL_P1 88
|
||||
+#define CLK_INFRA_PCIE_GFMUX_TL_P2 89
|
||||
+#define CLK_INFRA_PCIE_GFMUX_TL_P3 90
|
||||
+#define CLK_INFRA_PCIE_PIPE_P0 91
|
||||
+#define CLK_INFRA_PCIE_PIPE_P1 92
|
||||
+#define CLK_INFRA_PCIE_PIPE_P2 93
|
||||
+#define CLK_INFRA_PCIE_PIPE_P3 94
|
||||
+#define CLK_INFRA_133M_PCIE_CK_P0 95
|
||||
+#define CLK_INFRA_133M_PCIE_CK_P1 96
|
||||
+#define CLK_INFRA_133M_PCIE_CK_P2 97
|
||||
+#define CLK_INFRA_133M_PCIE_CK_P3 98
|
||||
+
|
||||
+/* ETHDMA */
|
||||
+
|
||||
+#define CLK_ETHDMA_XGP1_EN 0
|
||||
+#define CLK_ETHDMA_XGP2_EN 1
|
||||
+#define CLK_ETHDMA_XGP3_EN 2
|
||||
+#define CLK_ETHDMA_FE_EN 3
|
||||
+#define CLK_ETHDMA_GP2_EN 4
|
||||
+#define CLK_ETHDMA_GP1_EN 5
|
||||
+#define CLK_ETHDMA_GP3_EN 6
|
||||
+#define CLK_ETHDMA_ESW_EN 7
|
||||
+#define CLK_ETHDMA_CRYPT0_EN 8
|
||||
+#define CLK_ETHDMA_NR_CLK 9
|
||||
+
|
||||
+/* SGMIISYS_0 */
|
||||
+
|
||||
+#define CLK_SGM0_TX_EN 0
|
||||
+#define CLK_SGM0_RX_EN 1
|
||||
+#define CLK_SGMII0_NR_CLK 2
|
||||
+
|
||||
+/* SGMIISYS_1 */
|
||||
+
|
||||
+#define CLK_SGM1_TX_EN 0
|
||||
+#define CLK_SGM1_RX_EN 1
|
||||
+#define CLK_SGMII1_NR_CLK 2
|
||||
+
|
||||
+/* ETHWARP */
|
||||
+
|
||||
+#define CLK_ETHWARP_WOCPU2_EN 0
|
||||
+#define CLK_ETHWARP_WOCPU1_EN 1
|
||||
+#define CLK_ETHWARP_WOCPU0_EN 2
|
||||
+#define CLK_ETHWARP_NR_CLK 3
|
||||
+
|
||||
+/* XFIPLL */
|
||||
+#define CLK_XFIPLL_PLL 0
|
||||
+#define CLK_XFIPLL_PLL_EN 1
|
||||
+
|
||||
+#endif /* _DT_BINDINGS_CLK_MT7988_H */
|
||||
|
|
@ -1,260 +0,0 @@
|
|||
From afd36e9d91b0a840983b829a9e95407d8151f7e7 Mon Sep 17 00:00:00 2001
|
||||
From: Daniel Golle <daniel@makrotopia.org>
|
||||
Date: Sun, 17 Dec 2023 21:49:55 +0000
|
||||
Subject: [PATCH 2/4] dt-bindings: clock: mediatek: add clock controllers of
|
||||
MT7988
|
||||
|
||||
Add various clock controllers found in the MT7988 SoC to existing
|
||||
bindings (if applicable) and add files for the new ethwarp, mcusys
|
||||
and xfi-pll clock controllers not previously present in any SoC.
|
||||
|
||||
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
Link: https://lore.kernel.org/r/07e76a544ce4392bcb88e34d5480e99bb7994618.1702849494.git.daniel@makrotopia.org
|
||||
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
||||
---
|
||||
.../arm/mediatek/mediatek,infracfg.yaml | 1 +
|
||||
.../bindings/clock/mediatek,apmixedsys.yaml | 1 +
|
||||
.../bindings/clock/mediatek,ethsys.yaml | 1 +
|
||||
.../clock/mediatek,mt7988-ethwarp.yaml | 52 +++++++++++++++
|
||||
.../clock/mediatek,mt7988-xfi-pll.yaml | 48 ++++++++++++++
|
||||
.../bindings/clock/mediatek,topckgen.yaml | 2 +
|
||||
.../bindings/net/pcs/mediatek,sgmiisys.yaml | 65 ++++++++++++++++---
|
||||
7 files changed, 161 insertions(+), 9 deletions(-)
|
||||
create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml
|
||||
create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml
|
||||
|
||||
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
|
||||
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
|
||||
@@ -30,6 +30,7 @@ properties:
|
||||
- mediatek,mt7629-infracfg
|
||||
- mediatek,mt7981-infracfg
|
||||
- mediatek,mt7986-infracfg
|
||||
+ - mediatek,mt7988-infracfg
|
||||
- mediatek,mt8135-infracfg
|
||||
- mediatek,mt8167-infracfg
|
||||
- mediatek,mt8173-infracfg
|
||||
--- a/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
|
||||
+++ b/Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
|
||||
@@ -22,6 +22,7 @@ properties:
|
||||
- mediatek,mt7622-apmixedsys
|
||||
- mediatek,mt7981-apmixedsys
|
||||
- mediatek,mt7986-apmixedsys
|
||||
+ - mediatek,mt7988-apmixedsys
|
||||
- mediatek,mt8135-apmixedsys
|
||||
- mediatek,mt8173-apmixedsys
|
||||
- mediatek,mt8516-apmixedsys
|
||||
--- a/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
|
||||
+++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
|
||||
@@ -22,6 +22,7 @@ properties:
|
||||
- mediatek,mt7629-ethsys
|
||||
- mediatek,mt7981-ethsys
|
||||
- mediatek,mt7986-ethsys
|
||||
+ - mediatek,mt7988-ethsys
|
||||
- const: syscon
|
||||
- items:
|
||||
- const: mediatek,mt7623-ethsys
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-ethwarp.yaml
|
||||
@@ -0,0 +1,52 @@
|
||||
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
+%YAML 1.2
|
||||
+---
|
||||
+$id: http://devicetree.org/schemas/clock/mediatek,mt7988-ethwarp.yaml#
|
||||
+$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
+
|
||||
+title: MediaTek MT7988 ethwarp Controller
|
||||
+
|
||||
+maintainers:
|
||||
+ - Daniel Golle <daniel@makrotopia.org>
|
||||
+
|
||||
+description:
|
||||
+ The Mediatek MT7988 ethwarp controller provides clocks and resets for the
|
||||
+ Ethernet related subsystems found the MT7988 SoC.
|
||||
+ The clock values can be found in <dt-bindings/clock/mt*-clk.h>.
|
||||
+
|
||||
+properties:
|
||||
+ compatible:
|
||||
+ items:
|
||||
+ - const: mediatek,mt7988-ethwarp
|
||||
+
|
||||
+ reg:
|
||||
+ maxItems: 1
|
||||
+
|
||||
+ '#clock-cells':
|
||||
+ const: 1
|
||||
+
|
||||
+ '#reset-cells':
|
||||
+ const: 1
|
||||
+
|
||||
+required:
|
||||
+ - compatible
|
||||
+ - reg
|
||||
+ - '#clock-cells'
|
||||
+ - '#reset-cells'
|
||||
+
|
||||
+additionalProperties: false
|
||||
+
|
||||
+examples:
|
||||
+ - |
|
||||
+ #include <dt-bindings/reset/ti-syscon.h>
|
||||
+ soc {
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <2>;
|
||||
+
|
||||
+ clock-controller@15031000 {
|
||||
+ compatible = "mediatek,mt7988-ethwarp";
|
||||
+ reg = <0 0x15031000 0 0x1000>;
|
||||
+ #clock-cells = <1>;
|
||||
+ #reset-cells = <1>;
|
||||
+ };
|
||||
+ };
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7988-xfi-pll.yaml
|
||||
@@ -0,0 +1,48 @@
|
||||
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
+%YAML 1.2
|
||||
+---
|
||||
+$id: http://devicetree.org/schemas/clock/mediatek,mt7988-xfi-pll.yaml#
|
||||
+$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
+
|
||||
+title: MediaTek MT7988 XFI PLL Clock Controller
|
||||
+
|
||||
+maintainers:
|
||||
+ - Daniel Golle <daniel@makrotopia.org>
|
||||
+
|
||||
+description:
|
||||
+ The MediaTek XFI PLL controller provides the 156.25MHz clock for the
|
||||
+ Ethernet SerDes PHY from the 40MHz top_xtal clock.
|
||||
+
|
||||
+properties:
|
||||
+ compatible:
|
||||
+ const: mediatek,mt7988-xfi-pll
|
||||
+
|
||||
+ reg:
|
||||
+ maxItems: 1
|
||||
+
|
||||
+ resets:
|
||||
+ maxItems: 1
|
||||
+
|
||||
+ '#clock-cells':
|
||||
+ const: 1
|
||||
+
|
||||
+required:
|
||||
+ - compatible
|
||||
+ - reg
|
||||
+ - resets
|
||||
+ - '#clock-cells'
|
||||
+
|
||||
+additionalProperties: false
|
||||
+
|
||||
+examples:
|
||||
+ - |
|
||||
+ soc {
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <2>;
|
||||
+ clock-controller@11f40000 {
|
||||
+ compatible = "mediatek,mt7988-xfi-pll";
|
||||
+ reg = <0 0x11f40000 0 0x1000>;
|
||||
+ resets = <&watchdog 16>;
|
||||
+ #clock-cells = <1>;
|
||||
+ };
|
||||
+ };
|
||||
--- a/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
|
||||
+++ b/Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
|
||||
@@ -37,6 +37,8 @@ properties:
|
||||
- mediatek,mt7629-topckgen
|
||||
- mediatek,mt7981-topckgen
|
||||
- mediatek,mt7986-topckgen
|
||||
+ - mediatek,mt7988-mcusys
|
||||
+ - mediatek,mt7988-topckgen
|
||||
- mediatek,mt8167-topckgen
|
||||
- mediatek,mt8183-topckgen
|
||||
- const: syscon
|
||||
--- a/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
|
||||
+++ b/Documentation/devicetree/bindings/net/pcs/mediatek,sgmiisys.yaml
|
||||
@@ -15,15 +15,22 @@ description:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
- items:
|
||||
- - enum:
|
||||
- - mediatek,mt7622-sgmiisys
|
||||
- - mediatek,mt7629-sgmiisys
|
||||
- - mediatek,mt7981-sgmiisys_0
|
||||
- - mediatek,mt7981-sgmiisys_1
|
||||
- - mediatek,mt7986-sgmiisys_0
|
||||
- - mediatek,mt7986-sgmiisys_1
|
||||
- - const: syscon
|
||||
+ oneOf:
|
||||
+ - items:
|
||||
+ - enum:
|
||||
+ - mediatek,mt7622-sgmiisys
|
||||
+ - mediatek,mt7629-sgmiisys
|
||||
+ - mediatek,mt7981-sgmiisys_0
|
||||
+ - mediatek,mt7981-sgmiisys_1
|
||||
+ - mediatek,mt7986-sgmiisys_0
|
||||
+ - mediatek,mt7986-sgmiisys_1
|
||||
+ - const: syscon
|
||||
+ - items:
|
||||
+ - enum:
|
||||
+ - mediatek,mt7988-sgmiisys0
|
||||
+ - mediatek,mt7988-sgmiisys1
|
||||
+ - const: simple-mfd
|
||||
+ - const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@@ -35,11 +42,51 @@ properties:
|
||||
description: Invert polarity of the SGMII data lanes
|
||||
type: boolean
|
||||
|
||||
+ pcs:
|
||||
+ type: object
|
||||
+ description: MediaTek LynxI HSGMII PCS
|
||||
+ properties:
|
||||
+ compatible:
|
||||
+ const: mediatek,mt7988-sgmii
|
||||
+
|
||||
+ clocks:
|
||||
+ maxItems: 3
|
||||
+
|
||||
+ clock-names:
|
||||
+ items:
|
||||
+ - const: sgmii_sel
|
||||
+ - const: sgmii_tx
|
||||
+ - const: sgmii_rx
|
||||
+
|
||||
+ required:
|
||||
+ - compatible
|
||||
+ - clocks
|
||||
+ - clock-names
|
||||
+
|
||||
+ additionalProperties: false
|
||||
+
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
+allOf:
|
||||
+ - if:
|
||||
+ properties:
|
||||
+ compatible:
|
||||
+ contains:
|
||||
+ enum:
|
||||
+ - mediatek,mt7988-sgmiisys0
|
||||
+ - mediatek,mt7988-sgmiisys1
|
||||
+
|
||||
+ then:
|
||||
+ required:
|
||||
+ - pcs
|
||||
+
|
||||
+ else:
|
||||
+ properties:
|
||||
+ pcs: false
|
||||
+
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
|
@ -1,50 +0,0 @@
|
|||
From d9bf944beaaad1890ad3fcb755c61e1c7e4c5630 Mon Sep 17 00:00:00 2001
|
||||
From: Sam Shih <sam.shih@mediatek.com>
|
||||
Date: Sun, 17 Dec 2023 21:50:07 +0000
|
||||
Subject: [PATCH 3/4] clk: mediatek: add pcw_chg_bit control for PLLs of MT7988
|
||||
|
||||
Introduce pcw_chg_bit member to struct mtk_pll_data and use it instead
|
||||
of the previously hardcoded PCW_CHG_MASK macro if set.
|
||||
This will needed for clocks on the MT7988 SoC.
|
||||
|
||||
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
|
||||
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
Link: https://lore.kernel.org/r/3b9c65ddb08c8bedf790aacf29871af026b6f0b7.1702849494.git.daniel@makrotopia.org
|
||||
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
||||
---
|
||||
drivers/clk/mediatek/clk-pll.c | 5 +++--
|
||||
drivers/clk/mediatek/clk-pll.h | 1 +
|
||||
2 files changed, 4 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/clk/mediatek/clk-pll.c
|
||||
+++ b/drivers/clk/mediatek/clk-pll.c
|
||||
@@ -23,7 +23,7 @@
|
||||
#define CON0_BASE_EN BIT(0)
|
||||
#define CON0_PWR_ON BIT(0)
|
||||
#define CON0_ISO_EN BIT(1)
|
||||
-#define PCW_CHG_MASK BIT(31)
|
||||
+#define PCW_CHG_BIT 31
|
||||
|
||||
#define AUDPLL_TUNER_EN BIT(31)
|
||||
|
||||
@@ -114,7 +114,8 @@ static void mtk_pll_set_rate_regs(struct
|
||||
pll->data->pcw_shift);
|
||||
val |= pcw << pll->data->pcw_shift;
|
||||
writel(val, pll->pcw_addr);
|
||||
- chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
|
||||
+ chg = readl(pll->pcw_chg_addr) |
|
||||
+ BIT(pll->data->pcw_chg_bit ? : PCW_CHG_BIT);
|
||||
writel(chg, pll->pcw_chg_addr);
|
||||
if (pll->tuner_addr)
|
||||
writel(val + 1, pll->tuner_addr);
|
||||
--- a/drivers/clk/mediatek/clk-pll.h
|
||||
+++ b/drivers/clk/mediatek/clk-pll.h
|
||||
@@ -48,6 +48,7 @@ struct mtk_pll_data {
|
||||
const char *parent_name;
|
||||
u32 en_reg;
|
||||
u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
|
||||
+ u8 pcw_chg_bit;
|
||||
};
|
||||
|
||||
/*
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,57 +0,0 @@
|
|||
From 26ced94177b150710d94cf365002a09cc48950e9 Mon Sep 17 00:00:00 2001
|
||||
From: Frank Wunderlich <frank-w@public-files.de>
|
||||
Date: Wed, 17 Jan 2024 19:41:11 +0100
|
||||
Subject: [PATCH] clk: mediatek: add infracfg reset controller for mt7988
|
||||
|
||||
Infracfg can also operate as reset controller, add support for it.
|
||||
|
||||
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
|
||||
---
|
||||
drivers/clk/mediatek/clk-mt7988-infracfg.c | 23 ++++++++++++++++++++++
|
||||
1 file changed, 23 insertions(+)
|
||||
|
||||
--- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
|
||||
+++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
|
||||
@@ -14,6 +14,10 @@
|
||||
#include "clk-gate.h"
|
||||
#include "clk-mux.h"
|
||||
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
|
||||
+#include <dt-bindings/reset/mediatek,mt7988-resets.h>
|
||||
+
|
||||
+#define MT7988_INFRA_RST0_SET_OFFSET 0x70
|
||||
+#define MT7988_INFRA_RST1_SET_OFFSET 0x80
|
||||
|
||||
static DEFINE_SPINLOCK(mt7988_clk_lock);
|
||||
|
||||
@@ -249,12 +253,31 @@ static const struct mtk_gate infra_clks[
|
||||
GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31),
|
||||
};
|
||||
|
||||
+static u16 infra_rst_ofs[] = {
|
||||
+ MT7988_INFRA_RST0_SET_OFFSET,
|
||||
+ MT7988_INFRA_RST1_SET_OFFSET,
|
||||
+};
|
||||
+
|
||||
+static u16 infra_idx_map[] = {
|
||||
+ [MT7988_INFRA_RST0_PEXTP_MAC_SWRST] = 0 * RST_NR_PER_BANK + 6,
|
||||
+ [MT7988_INFRA_RST1_THERM_CTRL_SWRST] = 1 * RST_NR_PER_BANK + 9,
|
||||
+};
|
||||
+
|
||||
+static struct mtk_clk_rst_desc infra_rst_desc = {
|
||||
+ .version = MTK_RST_SET_CLR,
|
||||
+ .rst_bank_ofs = infra_rst_ofs,
|
||||
+ .rst_bank_nr = ARRAY_SIZE(infra_rst_ofs),
|
||||
+ .rst_idx_map = infra_idx_map,
|
||||
+ .rst_idx_map_nr = ARRAY_SIZE(infra_idx_map),
|
||||
+};
|
||||
+
|
||||
static const struct mtk_clk_desc infra_desc = {
|
||||
.clks = infra_clks,
|
||||
.num_clks = ARRAY_SIZE(infra_clks),
|
||||
.mux_clks = infra_muxes,
|
||||
.num_mux_clks = ARRAY_SIZE(infra_muxes),
|
||||
.clk_lock = &mt7988_clk_lock,
|
||||
+ .rst_desc = &infra_rst_desc,
|
||||
};
|
||||
|
||||
static const struct of_device_id of_match_clk_mt7988_infracfg[] = {
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
From 3c810da3206f2e52c92f9f15a87f05db4bbba734 Mon Sep 17 00:00:00 2001
|
||||
From: Frank Wunderlich <frank-w@public-files.de>
|
||||
Date: Wed, 17 Jan 2024 19:41:10 +0100
|
||||
Subject: [PATCH] dt-bindings: reset: mediatek: add MT7988 reset IDs
|
||||
|
||||
Add reset constants for using as index in driver and dts.
|
||||
|
||||
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
|
||||
---
|
||||
include/dt-bindings/reset/mediatek,mt7988-resets.h | 6 ++++++
|
||||
1 file changed, 6 insertions(+)
|
||||
|
||||
--- a/include/dt-bindings/reset/mediatek,mt7988-resets.h
|
||||
+++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h
|
||||
@@ -10,4 +10,10 @@
|
||||
/* ETHWARP resets */
|
||||
#define MT7988_ETHWARP_RST_SWITCH 0
|
||||
|
||||
+/* INFRA resets */
|
||||
+#define MT7988_INFRA_RST0_PEXTP_MAC_SWRST 0
|
||||
+#define MT7988_INFRA_RST1_THERM_CTRL_SWRST 1
|
||||
+
|
||||
+
|
||||
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */
|
||||
+
|
||||
|
|
@ -1,125 +0,0 @@
|
|||
From 137c9e08e5e542d58aa606b0bb4f0990117309a0 Mon Sep 17 00:00:00 2001
|
||||
From: Daniel Golle <daniel@makrotopia.org>
|
||||
Date: Mon, 20 Nov 2023 18:22:31 +0000
|
||||
Subject: [PATCH] watchdog: mediatek: mt7988: add wdt support
|
||||
|
||||
Add support for watchdog and reset generator unit of the MediaTek
|
||||
MT7988 SoC.
|
||||
|
||||
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
|
||||
Link: https://lore.kernel.org/r/c0cf5f701801cce60470853fa15f1d9dced78c4f.1700504385.git.daniel@makrotopia.org
|
||||
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
|
||||
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
|
||||
---
|
||||
drivers/watchdog/mtk_wdt.c | 42 ++++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 42 insertions(+)
|
||||
|
||||
--- a/drivers/watchdog/mtk_wdt.c
|
||||
+++ b/drivers/watchdog/mtk_wdt.c
|
||||
@@ -58,9 +58,13 @@
|
||||
#define WDT_SWSYSRST 0x18U
|
||||
#define WDT_SWSYS_RST_KEY 0x88000000
|
||||
|
||||
+#define WDT_SWSYSRST_EN 0xfc
|
||||
+
|
||||
#define DRV_NAME "mtk-wdt"
|
||||
#define DRV_VERSION "1.0"
|
||||
|
||||
+#define MT7988_TOPRGU_SW_RST_NUM 24
|
||||
+
|
||||
static bool nowayout = WATCHDOG_NOWAYOUT;
|
||||
static unsigned int timeout;
|
||||
|
||||
@@ -71,10 +75,12 @@ struct mtk_wdt_dev {
|
||||
struct reset_controller_dev rcdev;
|
||||
bool disable_wdt_extrst;
|
||||
bool reset_by_toprgu;
|
||||
+ bool has_swsysrst_en;
|
||||
};
|
||||
|
||||
struct mtk_wdt_data {
|
||||
int toprgu_sw_rst_num;
|
||||
+ bool has_swsysrst_en;
|
||||
};
|
||||
|
||||
static const struct mtk_wdt_data mt2712_data = {
|
||||
@@ -89,6 +95,11 @@ static const struct mtk_wdt_data mt7986_
|
||||
.toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM,
|
||||
};
|
||||
|
||||
+static const struct mtk_wdt_data mt7988_data = {
|
||||
+ .toprgu_sw_rst_num = MT7988_TOPRGU_SW_RST_NUM,
|
||||
+ .has_swsysrst_en = true,
|
||||
+};
|
||||
+
|
||||
static const struct mtk_wdt_data mt8183_data = {
|
||||
.toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
|
||||
};
|
||||
@@ -109,6 +120,28 @@ static const struct mtk_wdt_data mt8195_
|
||||
.toprgu_sw_rst_num = MT8195_TOPRGU_SW_RST_NUM,
|
||||
};
|
||||
|
||||
+/**
|
||||
+ * toprgu_reset_sw_en_unlocked() - enable/disable software control for reset bit
|
||||
+ * @data: Pointer to instance of driver data.
|
||||
+ * @id: Bit number identifying the reset to be enabled or disabled.
|
||||
+ * @enable: If true, enable software control for that bit, disable otherwise.
|
||||
+ *
|
||||
+ * Context: The caller must hold lock of struct mtk_wdt_dev.
|
||||
+ */
|
||||
+static void toprgu_reset_sw_en_unlocked(struct mtk_wdt_dev *data,
|
||||
+ unsigned long id, bool enable)
|
||||
+{
|
||||
+ u32 tmp;
|
||||
+
|
||||
+ tmp = readl(data->wdt_base + WDT_SWSYSRST_EN);
|
||||
+ if (enable)
|
||||
+ tmp |= BIT(id);
|
||||
+ else
|
||||
+ tmp &= ~BIT(id);
|
||||
+
|
||||
+ writel(tmp, data->wdt_base + WDT_SWSYSRST_EN);
|
||||
+}
|
||||
+
|
||||
static int toprgu_reset_update(struct reset_controller_dev *rcdev,
|
||||
unsigned long id, bool assert)
|
||||
{
|
||||
@@ -119,6 +152,9 @@ static int toprgu_reset_update(struct re
|
||||
|
||||
spin_lock_irqsave(&data->lock, flags);
|
||||
|
||||
+ if (assert && data->has_swsysrst_en)
|
||||
+ toprgu_reset_sw_en_unlocked(data, id, true);
|
||||
+
|
||||
tmp = readl(data->wdt_base + WDT_SWSYSRST);
|
||||
if (assert)
|
||||
tmp |= BIT(id);
|
||||
@@ -127,6 +163,9 @@ static int toprgu_reset_update(struct re
|
||||
tmp |= WDT_SWSYS_RST_KEY;
|
||||
writel(tmp, data->wdt_base + WDT_SWSYSRST);
|
||||
|
||||
+ if (!assert && data->has_swsysrst_en)
|
||||
+ toprgu_reset_sw_en_unlocked(data, id, false);
|
||||
+
|
||||
spin_unlock_irqrestore(&data->lock, flags);
|
||||
|
||||
return 0;
|
||||
@@ -406,6 +445,8 @@ static int mtk_wdt_probe(struct platform
|
||||
wdt_data->toprgu_sw_rst_num);
|
||||
if (err)
|
||||
return err;
|
||||
+
|
||||
+ mtk_wdt->has_swsysrst_en = wdt_data->has_swsysrst_en;
|
||||
}
|
||||
|
||||
mtk_wdt->disable_wdt_extrst =
|
||||
@@ -444,6 +485,7 @@ static const struct of_device_id mtk_wdt
|
||||
{ .compatible = "mediatek,mt6589-wdt" },
|
||||
{ .compatible = "mediatek,mt6795-wdt", .data = &mt6795_data },
|
||||
{ .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data },
|
||||
+ { .compatible = "mediatek,mt7988-wdt", .data = &mt7988_data },
|
||||
{ .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
|
||||
{ .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data },
|
||||
{ .compatible = "mediatek,mt8188-wdt", .data = &mt8188_data },
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
From c202f510bbaa34ab5d65a69a61e0e72761374b17 Mon Sep 17 00:00:00 2001
|
||||
From: Daniel Golle <daniel@makrotopia.org>
|
||||
Date: Mon, 11 Mar 2024 17:14:19 +0000
|
||||
Subject: [PATCH] clk: mediatek: mt7988-infracfg: fix clocks for 2nd PCIe port
|
||||
|
||||
Due to what seems to be an undocumented oddity in MediaTek's MT7988
|
||||
SoC design the CLK_INFRA_PCIE_PERI_26M_CK_P2 clock requires
|
||||
CLK_INFRA_PCIE_PERI_26M_CK_P3 to be enabled.
|
||||
|
||||
This currently leads to PCIe port 2 not working in Linux.
|
||||
|
||||
Reflect the apparent relationship in the clk driver to make sure PCIe
|
||||
port 2 of the MT7988 SoC works.
|
||||
|
||||
Suggested-by: Sam Shih <sam.shih@mediatek.com>
|
||||
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||
---
|
||||
drivers/clk/mediatek/clk-mt7988-infracfg.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/clk/mediatek/clk-mt7988-infracfg.c
|
||||
+++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c
|
||||
@@ -156,7 +156,7 @@ static const struct mtk_gate infra_clks[
|
||||
GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1, "infra_pcie_peri_ck_26m_ck_p1",
|
||||
"csw_infra_f26m_sel", 8),
|
||||
GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2, "infra_pcie_peri_ck_26m_ck_p2",
|
||||
- "csw_infra_f26m_sel", 9),
|
||||
+ "infra_pcie_peri_ck_26m_ck_p3", 9),
|
||||
GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3, "infra_pcie_peri_ck_26m_ck_p3",
|
||||
"csw_infra_f26m_sel", 10),
|
||||
/* INFRA1 */
|
||||
|
|
@ -1,63 +0,0 @@
|
|||
From patchwork Wed Jan 17 12:42:33 2024
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
X-Patchwork-Submitter: Jean Thomas <jean.thomas@wifirst.fr>
|
||||
X-Patchwork-Id: 13521682
|
||||
Return-Path:
|
||||
<linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org>
|
||||
From: Jean Thomas <jean.thomas@wifirst.fr>
|
||||
To: sean.wang@kernel.org,
|
||||
linus.walleij@linaro.org,
|
||||
matthias.bgg@gmail.com,
|
||||
angelogioacchino.delregno@collabora.com,
|
||||
linux-mediatek@lists.infradead.org,
|
||||
linux-gpio@vger.kernel.org,
|
||||
linux-kernel@vger.kernel.org,
|
||||
linux-arm-kernel@lists.infradead.org
|
||||
Cc: Jean Thomas <jean.thomas@wifirst.fr>
|
||||
Subject: [PATCH 1/2] pinctrl: mediatek: mt7981: add additional uart group
|
||||
Date: Wed, 17 Jan 2024 13:42:33 +0100
|
||||
Message-Id: <20240117124234.3137050-1-jean.thomas@wifirst.fr>
|
||||
MIME-Version: 1.0
|
||||
List-Id: <linux-mediatek.lists.infradead.org>
|
||||
|
||||
Add uart1_3 (pins 26, 27) group to the pinctrl driver for the
|
||||
MediaTek MT7981 SoC.
|
||||
|
||||
Signed-off-by: Jean Thomas <jean.thomas@wifirst.fr>
|
||||
Reviewed-by: Daniel Golle <daniel@makrotopia.org>
|
||||
---
|
||||
drivers/pinctrl/mediatek/pinctrl-mt7981.c | 7 ++++++-
|
||||
1 file changed, 6 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
|
||||
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
|
||||
@@ -737,6 +737,9 @@ static int mt7981_uart1_1_funcs[] = { 2,
|
||||
static int mt7981_uart1_2_pins[] = { 9, 10, };
|
||||
static int mt7981_uart1_2_funcs[] = { 2, 2, };
|
||||
|
||||
+static int mt7981_uart1_3_pins[] = { 26, 27, };
|
||||
+static int mt7981_uart1_3_funcs[] = { 2, 2, };
|
||||
+
|
||||
/* UART2 */
|
||||
static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
|
||||
static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
|
||||
@@ -871,6 +874,8 @@ static const struct group_desc mt7981_gr
|
||||
PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
|
||||
/* @GPIO(9,10): UART1(2) */
|
||||
PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2),
|
||||
+ /* @GPIO(26,27): UART1(2) */
|
||||
+ PINCTRL_PIN_GROUP("uart1_3", mt7981_uart1_3),
|
||||
/* @GPIO(22,25): UART1(3) */
|
||||
PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1),
|
||||
/* @GPIO(22,24) PTA_EXT(4) */
|
||||
@@ -933,7 +938,7 @@ static const struct group_desc mt7981_gr
|
||||
static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1",
|
||||
"wa_aice3", "wm_aice1_2", };
|
||||
static const char *mt7981_uart_groups[] = { "net_wo0_uart_txd_0", "net_wo0_uart_txd_1",
|
||||
- "net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart2_0",
|
||||
+ "net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart1_3", "uart2_0",
|
||||
"uart2_0_tx_rx", "uart2_1", "wm_uart_0", "wm_aurt_1", "wm_aurt_2", };
|
||||
static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
|
||||
static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
|
||||
|
|
@ -1,82 +0,0 @@
|
|||
From patchwork Wed Jan 17 14:55:47 2024
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
X-Patchwork-Submitter: Jean Thomas <jean.thomas@wifirst.fr>
|
||||
X-Patchwork-Id: 13521855
|
||||
Return-Path:
|
||||
<linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org>
|
||||
From: Jean Thomas <jean.thomas@wifirst.fr>
|
||||
To: sean.wang@kernel.org,
|
||||
linus.walleij@linaro.org,
|
||||
matthias.bgg@gmail.com,
|
||||
angelogioacchino.delregno@collabora.com,
|
||||
linux-mediatek@lists.infradead.org,
|
||||
linux-gpio@vger.kernel.org,
|
||||
linux-kernel@vger.kernel.org,
|
||||
linux-arm-kernel@lists.infradead.org
|
||||
Cc: Jean Thomas <jean.thomas@wifirst.fr>,
|
||||
Daniel Golle <daniel@makrotopia.org>
|
||||
Subject: [PATCH v2 2/2] pinctrl: mediatek: mt7981: add additional emmc groups
|
||||
Date: Wed, 17 Jan 2024 15:55:47 +0100
|
||||
Message-Id: <20240117145547.3354242-1-jean.thomas@wifirst.fr>
|
||||
List-Id: <linux-mediatek.lists.infradead.org>
|
||||
|
||||
Add new emmc groups in the pinctrl driver for the
|
||||
MediaTek MT7981 SoC:
|
||||
* emmc reset, with pin 15.
|
||||
* emmc 4-bit bus-width, with pins 16 to 19, and 24 to 25.
|
||||
* emmc 8-bit bus-width, with pins 16 to 25.
|
||||
|
||||
The existing emmc_45 group is kept for legacy reasons, even
|
||||
if this is the union of emmc_reset and emmc_8 groups.
|
||||
|
||||
Signed-off-by: Jean Thomas <jean.thomas@wifirst.fr>
|
||||
Reviewed-by: Daniel Golle <daniel@makrotopia.org>
|
||||
---
|
||||
drivers/pinctrl/mediatek/pinctrl-mt7981.c | 17 ++++++++++++++++-
|
||||
1 file changed, 16 insertions(+), 1 deletion(-)
|
||||
|
||||
--
|
||||
2.39.2
|
||||
|
||||
--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
|
||||
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
|
||||
@@ -700,6 +700,15 @@ static int mt7981_drv_vbus_pins[] = { 14
|
||||
static int mt7981_drv_vbus_funcs[] = { 1, };
|
||||
|
||||
/* EMMC */
|
||||
+static int mt7981_emmc_reset_pins[] = { 15, };
|
||||
+static int mt7981_emmc_reset_funcs[] = { 2, };
|
||||
+
|
||||
+static int mt7981_emmc_4_pins[] = { 16, 17, 18, 19, 24, 25, };
|
||||
+static int mt7981_emmc_4_funcs[] = { 2, 2, 2, 2, 2, 2, };
|
||||
+
|
||||
+static int mt7981_emmc_8_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
|
||||
+static int mt7981_emmc_8_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
|
||||
+
|
||||
static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, };
|
||||
static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
|
||||
|
||||
@@ -854,6 +863,12 @@ static const struct group_desc mt7981_gr
|
||||
PINCTRL_PIN_GROUP("udi", mt7981_udi),
|
||||
/* @GPIO(14) DRV_VBUS(1) */
|
||||
PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus),
|
||||
+ /* @GPIO(15): EMMC_RSTB(2) */
|
||||
+ PINCTRL_PIN_GROUP("emmc_reset", mt7981_emmc_reset),
|
||||
+ /* @GPIO(16,17,18,19,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */
|
||||
+ PINCTRL_PIN_GROUP("emmc_4", mt7981_emmc_4),
|
||||
+ /* @GPIO(16,17,18,19,20,21,22,23,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */
|
||||
+ PINCTRL_PIN_GROUP("emmc_8", mt7981_emmc_8),
|
||||
/* @GPIO(15,25): EMMC(2) */
|
||||
PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45),
|
||||
/* @GPIO(16,21): SNFI(3) */
|
||||
@@ -957,7 +972,7 @@ static const char *mt7981_i2c_groups[] =
|
||||
static const char *mt7981_pcm_groups[] = { "pcm", };
|
||||
static const char *mt7981_udi_groups[] = { "udi", };
|
||||
static const char *mt7981_usb_groups[] = { "drv_vbus", };
|
||||
-static const char *mt7981_flash_groups[] = { "emmc_45", "snfi", };
|
||||
+static const char *mt7981_flash_groups[] = { "emmc_reset", "emmc_4", "emmc_8", "emmc_45", "snfi", };
|
||||
static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio",
|
||||
"wf0_mode1", "wf0_mode3", "mt7531_int", };
|
||||
static const char *mt7981_ant_groups[] = { "ant_sel", };
|
||||
|
|
@ -1,123 +0,0 @@
|
|||
From 5f49a5c9b16330e0df8f639310e4715dcad71947 Mon Sep 17 00:00:00 2001
|
||||
From: Davide Fioravanti <pantanastyle@gmail.com>
|
||||
Date: Fri, 8 Jan 2021 15:35:24 +0100
|
||||
Subject: [PATCH] mtd: spinand: Add support for the Fidelix FM35X1GA
|
||||
|
||||
Datasheet: http://www.hobos.com.cn/upload/datasheet/DS35X1GAXXX_100_rev00.pdf
|
||||
|
||||
Signed-off-by: Davide Fioravanti <pantanastyle@gmail.com>
|
||||
---
|
||||
drivers/mtd/nand/spi/Makefile | 2 +-
|
||||
drivers/mtd/nand/spi/core.c | 1 +
|
||||
drivers/mtd/nand/spi/fidelix.c | 76 ++++++++++++++++++++++++++++++++++
|
||||
include/linux/mtd/spinand.h | 1 +
|
||||
4 files changed, 79 insertions(+), 1 deletion(-)
|
||||
create mode 100644 drivers/mtd/nand/spi/fidelix.c
|
||||
|
||||
--- a/drivers/mtd/nand/spi/Makefile
|
||||
+++ b/drivers/mtd/nand/spi/Makefile
|
||||
@@ -1,4 +1,4 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
-spinand-objs := core.o alliancememory.o ato.o esmt.o etron.o gigadevice.o
|
||||
+spinand-objs := core.o alliancememory.o ato.o esmt.o etron.o fidelix.o gigadevice.o
|
||||
spinand-objs += macronix.o micron.o paragon.o toshiba.o winbond.o xtx.o
|
||||
obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
|
||||
--- a/drivers/mtd/nand/spi/core.c
|
||||
+++ b/drivers/mtd/nand/spi/core.c
|
||||
@@ -941,6 +941,7 @@ static const struct spinand_manufacturer
|
||||
&alliancememory_spinand_manufacturer,
|
||||
&ato_spinand_manufacturer,
|
||||
&esmt_c8_spinand_manufacturer,
|
||||
+ &fidelix_spinand_manufacturer,
|
||||
&etron_spinand_manufacturer,
|
||||
&gigadevice_spinand_manufacturer,
|
||||
¯onix_spinand_manufacturer,
|
||||
--- /dev/null
|
||||
+++ b/drivers/mtd/nand/spi/fidelix.c
|
||||
@@ -0,0 +1,76 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0
|
||||
+/*
|
||||
+ * Copyright (c) 2020 Davide Fioravanti <pantanastyle@gmail.com>
|
||||
+ */
|
||||
+
|
||||
+#include <linux/device.h>
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/mtd/spinand.h>
|
||||
+
|
||||
+#define SPINAND_MFR_FIDELIX 0xE5
|
||||
+#define FIDELIX_ECCSR_MASK 0x0F
|
||||
+
|
||||
+static SPINAND_OP_VARIANTS(read_cache_variants,
|
||||
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
|
||||
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
|
||||
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
|
||||
+
|
||||
+static SPINAND_OP_VARIANTS(write_cache_variants,
|
||||
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
|
||||
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
|
||||
+
|
||||
+static SPINAND_OP_VARIANTS(update_cache_variants,
|
||||
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
|
||||
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
|
||||
+
|
||||
+static int fm35x1ga_ooblayout_ecc(struct mtd_info *mtd, int section,
|
||||
+ struct mtd_oob_region *region)
|
||||
+{
|
||||
+ if (section > 3)
|
||||
+ return -ERANGE;
|
||||
+
|
||||
+ region->offset = (16 * section) + 8;
|
||||
+ region->length = 8;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int fm35x1ga_ooblayout_free(struct mtd_info *mtd, int section,
|
||||
+ struct mtd_oob_region *region)
|
||||
+{
|
||||
+ if (section > 3)
|
||||
+ return -ERANGE;
|
||||
+
|
||||
+ region->offset = (16 * section) + 2;
|
||||
+ region->length = 6;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct mtd_ooblayout_ops fm35x1ga_ooblayout = {
|
||||
+ .ecc = fm35x1ga_ooblayout_ecc,
|
||||
+ .free = fm35x1ga_ooblayout_free,
|
||||
+};
|
||||
+
|
||||
+static const struct spinand_info fidelix_spinand_table[] = {
|
||||
+ SPINAND_INFO("FM35X1GA",
|
||||
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x71),
|
||||
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
|
||||
+ NAND_ECCREQ(4, 512),
|
||||
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
|
||||
+ &write_cache_variants,
|
||||
+ &update_cache_variants),
|
||||
+ SPINAND_HAS_QE_BIT,
|
||||
+ SPINAND_ECCINFO(&fm35x1ga_ooblayout, NULL)),
|
||||
+};
|
||||
+
|
||||
+static const struct spinand_manufacturer_ops fidelix_spinand_manuf_ops = {
|
||||
+};
|
||||
+
|
||||
+const struct spinand_manufacturer fidelix_spinand_manufacturer = {
|
||||
+ .id = SPINAND_MFR_FIDELIX,
|
||||
+ .name = "Fidelix",
|
||||
+ .chips = fidelix_spinand_table,
|
||||
+ .nchips = ARRAY_SIZE(fidelix_spinand_table),
|
||||
+ .ops = &fidelix_spinand_manuf_ops,
|
||||
+};
|
||||
--- a/include/linux/mtd/spinand.h
|
||||
+++ b/include/linux/mtd/spinand.h
|
||||
@@ -264,6 +264,7 @@ extern const struct spinand_manufacturer
|
||||
extern const struct spinand_manufacturer ato_spinand_manufacturer;
|
||||
extern const struct spinand_manufacturer esmt_c8_spinand_manufacturer;
|
||||
extern const struct spinand_manufacturer etron_spinand_manufacturer;
|
||||
+extern const struct spinand_manufacturer fidelix_spinand_manufacturer;
|
||||
extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
|
||||
extern const struct spinand_manufacturer macronix_spinand_manufacturer;
|
||||
extern const struct spinand_manufacturer micron_spinand_manufacturer;
|
||||
|
|
@ -1,61 +0,0 @@
|
|||
From patchwork Fri Apr 19 16:59:07 2024
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
|
||||
X-Patchwork-Id: 13636668
|
||||
Return-Path:
|
||||
<linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org>
|
||||
Date: Fri, 19 Apr 2024 17:59:07 +0100
|
||||
From: Daniel Golle <daniel@makrotopia.org>
|
||||
To: "Rafael J. Wysocki" <rafael@kernel.org>,
|
||||
Viresh Kumar <viresh.kumar@linaro.org>,
|
||||
Matthias Brugger <matthias.bgg@gmail.com>,
|
||||
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
|
||||
linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org,
|
||||
linux-arm-kernel@lists.infradead.org,
|
||||
linux-mediatek@lists.infradead.org
|
||||
Subject: [PATCH] cpufreq: mediatek: Add support for MT7988A
|
||||
Message-ID:
|
||||
<acf4fb446aacfbf6ce7b6e94bf3aad303e0ad4d1.1713545923.git.daniel@makrotopia.org>
|
||||
Content-Disposition: inline
|
||||
List-Id: <linux-mediatek.lists.infradead.org>
|
||||
|
||||
From: Sam Shih <sam.shih@mediatek.com>
|
||||
|
||||
This add cpufreq support for mediatek MT7988A SoC.
|
||||
|
||||
The platform data of MT7988A is different from previous MediaTek SoCs,
|
||||
so we add a new compatible and platform data for it.
|
||||
|
||||
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
|
||||
---
|
||||
drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++++++
|
||||
1 file changed, 10 insertions(+)
|
||||
|
||||
--- a/drivers/cpufreq/mediatek-cpufreq.c
|
||||
+++ b/drivers/cpufreq/mediatek-cpufreq.c
|
||||
@@ -707,6 +707,15 @@ static const struct mtk_cpufreq_platform
|
||||
.ccifreq_supported = false,
|
||||
};
|
||||
|
||||
+static const struct mtk_cpufreq_platform_data mt7988_platform_data = {
|
||||
+ .min_volt_shift = 100000,
|
||||
+ .max_volt_shift = 200000,
|
||||
+ .proc_max_volt = 900000,
|
||||
+ .sram_min_volt = 0,
|
||||
+ .sram_max_volt = 1150000,
|
||||
+ .ccifreq_supported = true,
|
||||
+};
|
||||
+
|
||||
static const struct mtk_cpufreq_platform_data mt8183_platform_data = {
|
||||
.min_volt_shift = 100000,
|
||||
.max_volt_shift = 200000,
|
||||
@@ -740,6 +749,7 @@ static const struct of_device_id mtk_cpu
|
||||
{ .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
|
||||
{ .compatible = "mediatek,mt7622", .data = &mt7622_platform_data },
|
||||
{ .compatible = "mediatek,mt7623", .data = &mt7623_platform_data },
|
||||
+ { .compatible = "mediatek,mt7988a", .data = &mt7988_platform_data },
|
||||
{ .compatible = "mediatek,mt8167", .data = &mt8516_platform_data },
|
||||
{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
|
||||
{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
|
||||
|
|
@ -1,130 +0,0 @@
|
|||
From bfd3acc428085742d754a6d328d1a93ebf9451df Mon Sep 17 00:00:00 2001
|
||||
From: "SkyLake.Huang" <skylake.huang@mediatek.com>
|
||||
Date: Thu, 23 Jun 2022 18:29:51 +0800
|
||||
Subject: [PATCH 1/6] drivers: spi-mt65xx: Move chip_config to driver's private
|
||||
data
|
||||
|
||||
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
|
||||
---
|
||||
drivers/spi/spi-mt65xx.c | 29 +++++++++---------------
|
||||
include/linux/platform_data/spi-mt65xx.h | 17 --------------
|
||||
2 files changed, 11 insertions(+), 35 deletions(-)
|
||||
delete mode 100644 include/linux/platform_data/spi-mt65xx.h
|
||||
|
||||
--- a/drivers/spi/spi-mt65xx.c
|
||||
+++ b/drivers/spi/spi-mt65xx.c
|
||||
@@ -14,7 +14,6 @@
|
||||
#include <linux/of.h>
|
||||
#include <linux/gpio/consumer.h>
|
||||
#include <linux/platform_device.h>
|
||||
-#include <linux/platform_data/spi-mt65xx.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/spi/spi-mem.h>
|
||||
@@ -171,6 +170,8 @@ struct mtk_spi {
|
||||
struct device *dev;
|
||||
dma_addr_t tx_dma;
|
||||
dma_addr_t rx_dma;
|
||||
+ u32 sample_sel;
|
||||
+ u32 get_tick_dly;
|
||||
};
|
||||
|
||||
static const struct mtk_spi_compatible mtk_common_compat;
|
||||
@@ -216,15 +217,6 @@ static const struct mtk_spi_compatible m
|
||||
.no_need_unprepare = true,
|
||||
};
|
||||
|
||||
-/*
|
||||
- * A piece of default chip info unless the platform
|
||||
- * supplies it.
|
||||
- */
|
||||
-static const struct mtk_chip_config mtk_default_chip_info = {
|
||||
- .sample_sel = 0,
|
||||
- .tick_delay = 0,
|
||||
-};
|
||||
-
|
||||
static const struct of_device_id mtk_spi_of_match[] = {
|
||||
{ .compatible = "mediatek,spi-ipm",
|
||||
.data = (void *)&mtk_ipm_compat,
|
||||
@@ -352,7 +344,6 @@ static int mtk_spi_hw_init(struct spi_ma
|
||||
{
|
||||
u16 cpha, cpol;
|
||||
u32 reg_val;
|
||||
- struct mtk_chip_config *chip_config = spi->controller_data;
|
||||
struct mtk_spi *mdata = spi_master_get_devdata(master);
|
||||
|
||||
cpha = spi->mode & SPI_CPHA ? 1 : 0;
|
||||
@@ -402,7 +393,7 @@ static int mtk_spi_hw_init(struct spi_ma
|
||||
else
|
||||
reg_val &= ~SPI_CMD_CS_POL;
|
||||
|
||||
- if (chip_config->sample_sel)
|
||||
+ if (mdata->sample_sel)
|
||||
reg_val |= SPI_CMD_SAMPLE_SEL;
|
||||
else
|
||||
reg_val &= ~SPI_CMD_SAMPLE_SEL;
|
||||
@@ -429,20 +420,20 @@ static int mtk_spi_hw_init(struct spi_ma
|
||||
if (mdata->dev_comp->ipm_design) {
|
||||
reg_val = readl(mdata->base + SPI_CMD_REG);
|
||||
reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK;
|
||||
- reg_val |= ((chip_config->tick_delay & 0x7)
|
||||
+ reg_val |= ((mdata->get_tick_dly & 0x7)
|
||||
<< SPI_CMD_IPM_GET_TICKDLY_OFFSET);
|
||||
writel(reg_val, mdata->base + SPI_CMD_REG);
|
||||
} else {
|
||||
reg_val = readl(mdata->base + SPI_CFG1_REG);
|
||||
reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
|
||||
- reg_val |= ((chip_config->tick_delay & 0x7)
|
||||
+ reg_val |= ((mdata->get_tick_dly & 0x7)
|
||||
<< SPI_CFG1_GET_TICK_DLY_OFFSET);
|
||||
writel(reg_val, mdata->base + SPI_CFG1_REG);
|
||||
}
|
||||
} else {
|
||||
reg_val = readl(mdata->base + SPI_CFG1_REG);
|
||||
reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1;
|
||||
- reg_val |= ((chip_config->tick_delay & 0x3)
|
||||
+ reg_val |= ((mdata->get_tick_dly & 0x3)
|
||||
<< SPI_CFG1_GET_TICK_DLY_OFFSET_V1);
|
||||
writel(reg_val, mdata->base + SPI_CFG1_REG);
|
||||
}
|
||||
@@ -732,9 +723,6 @@ static int mtk_spi_setup(struct spi_devi
|
||||
{
|
||||
struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
|
||||
|
||||
- if (!spi->controller_data)
|
||||
- spi->controller_data = (void *)&mtk_default_chip_info;
|
||||
-
|
||||
if (mdata->dev_comp->need_pad_sel && spi_get_csgpiod(spi, 0))
|
||||
/* CS de-asserted, gpiolib will handle inversion */
|
||||
gpiod_direction_output(spi_get_csgpiod(spi, 0), 0);
|
||||
@@ -1140,6 +1128,10 @@ static int mtk_spi_probe(struct platform
|
||||
mdata = spi_master_get_devdata(master);
|
||||
mdata->dev_comp = device_get_match_data(dev);
|
||||
|
||||
+ /* Set device configs to default first. Calibrate it later. */
|
||||
+ mdata->sample_sel = 0;
|
||||
+ mdata->get_tick_dly = 2;
|
||||
+
|
||||
if (mdata->dev_comp->enhance_timing)
|
||||
master->mode_bits |= SPI_CS_HIGH;
|
||||
|
||||
--- a/include/linux/platform_data/spi-mt65xx.h
|
||||
+++ /dev/null
|
||||
@@ -1,17 +0,0 @@
|
||||
-/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
-/*
|
||||
- * MTK SPI bus driver definitions
|
||||
- *
|
||||
- * Copyright (c) 2015 MediaTek Inc.
|
||||
- * Author: Leilk Liu <leilk.liu@mediatek.com>
|
||||
- */
|
||||
-
|
||||
-#ifndef ____LINUX_PLATFORM_DATA_SPI_MTK_H
|
||||
-#define ____LINUX_PLATFORM_DATA_SPI_MTK_H
|
||||
-
|
||||
-/* Board specific platform_data */
|
||||
-struct mtk_chip_config {
|
||||
- u32 sample_sel;
|
||||
- u32 tick_delay;
|
||||
-};
|
||||
-#endif
|
||||
|
|
@ -1,43 +0,0 @@
|
|||
From d278c7a0bf730318a7ccf8d0a8b434c813e23fd0 Mon Sep 17 00:00:00 2001
|
||||
From: "SkyLake.Huang" <skylake.huang@mediatek.com>
|
||||
Date: Thu, 23 Jun 2022 18:39:03 +0800
|
||||
Subject: [PATCH 4/6] drivers: spi-mt65xx: Add controller's calibration
|
||||
paramter
|
||||
|
||||
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
|
||||
---
|
||||
drivers/spi/spi-mt65xx.c | 16 ++++++++++++++++
|
||||
1 file changed, 16 insertions(+)
|
||||
|
||||
--- a/drivers/spi/spi-mt65xx.c
|
||||
+++ b/drivers/spi/spi-mt65xx.c
|
||||
@@ -834,6 +834,21 @@ static irqreturn_t mtk_spi_interrupt(int
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
+static int mtk_spi_append_caldata(struct spi_controller *ctlr)
|
||||
+{
|
||||
+ struct spi_cal_target *cal_target = kmalloc(sizeof(*cal_target), GFP_KERNEL);
|
||||
+ struct mtk_spi *mdata = spi_master_get_devdata(ctlr);
|
||||
+
|
||||
+ cal_target->cal_item = &mdata->get_tick_dly;
|
||||
+ cal_target->cal_min = 0;
|
||||
+ cal_target->cal_max = 7;
|
||||
+ cal_target->step = 1;
|
||||
+
|
||||
+ list_add(&cal_target->list, ctlr->cal_target);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem,
|
||||
struct spi_mem_op *op)
|
||||
{
|
||||
@@ -1124,6 +1139,7 @@ static int mtk_spi_probe(struct platform
|
||||
master->setup = mtk_spi_setup;
|
||||
master->set_cs_timing = mtk_spi_set_hw_cs_timing;
|
||||
master->use_gpio_descriptors = true;
|
||||
+ master->append_caldata = mtk_spi_append_caldata;
|
||||
|
||||
mdata = spi_master_get_devdata(master);
|
||||
mdata->dev_comp = device_get_match_data(dev);
|
||||
|
|
@ -1,81 +0,0 @@
|
|||
From 7670ec4a14891a1a182b98a9c403ffbf6b49e4b1 Mon Sep 17 00:00:00 2001
|
||||
From: "SkyLake.Huang" <skylake.huang@mediatek.com>
|
||||
Date: Thu, 23 Jun 2022 18:39:56 +0800
|
||||
Subject: [PATCH 5/6] drivers: mtd: spinand: Add calibration support for
|
||||
spinand
|
||||
|
||||
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
|
||||
---
|
||||
drivers/mtd/nand/spi/core.c | 54 +++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 54 insertions(+)
|
||||
|
||||
--- a/drivers/mtd/nand/spi/core.c
|
||||
+++ b/drivers/mtd/nand/spi/core.c
|
||||
@@ -979,6 +979,56 @@ static int spinand_manufacturer_match(st
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
+int spinand_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen) {
|
||||
+ struct spinand_device *spinand = (struct spinand_device *)priv;
|
||||
+ struct device *dev = &spinand->spimem->spi->dev;
|
||||
+ struct spi_mem_op op = SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, buf, readlen);
|
||||
+ struct nand_pos pos;
|
||||
+ struct nand_page_io_req req;
|
||||
+ u8 status;
|
||||
+ int ret;
|
||||
+
|
||||
+ if(addrlen != sizeof(struct nand_addr)/sizeof(unsigned int)) {
|
||||
+ dev_err(dev, "Must provide correct addr(length) for spinand calibration\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ ret = spinand_reset_op(spinand);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ /* We should store our golden data in first target because
|
||||
+ * we can't switch target at this moment.
|
||||
+ */
|
||||
+ pos = (struct nand_pos){
|
||||
+ .target = 0,
|
||||
+ .lun = *addr,
|
||||
+ .plane = *(addr+1),
|
||||
+ .eraseblock = *(addr+2),
|
||||
+ .page = *(addr+3),
|
||||
+ };
|
||||
+
|
||||
+ req = (struct nand_page_io_req){
|
||||
+ .pos = pos,
|
||||
+ .dataoffs = *(addr+4),
|
||||
+ .datalen = readlen,
|
||||
+ .databuf.in = buf,
|
||||
+ .mode = MTD_OPS_AUTO_OOB,
|
||||
+ };
|
||||
+
|
||||
+ ret = spinand_load_page_op(spinand, &req);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = spinand_wait(spinand, &status);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = spi_mem_exec_op(spinand->spimem, &op);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int spinand_id_detect(struct spinand_device *spinand)
|
||||
{
|
||||
u8 *id = spinand->id.data;
|
||||
@@ -1229,6 +1279,10 @@ static int spinand_init(struct spinand_d
|
||||
if (!spinand->scratchbuf)
|
||||
return -ENOMEM;
|
||||
|
||||
+ ret = spi_mem_do_calibration(spinand->spimem, spinand_cal_read, spinand);
|
||||
+ if (ret)
|
||||
+ dev_err(dev, "Failed to calibrate SPI-NAND (err = %d)\n", ret);
|
||||
+
|
||||
ret = spinand_detect(spinand);
|
||||
if (ret)
|
||||
goto err_free_bufs;
|
||||
|
|
@ -1,57 +0,0 @@
|
|||
From f3fe3b15eca7908eaac57f9b8387a5dbc45ec5b2 Mon Sep 17 00:00:00 2001
|
||||
From: "SkyLake.Huang" <skylake.huang@mediatek.com>
|
||||
Date: Thu, 23 Jun 2022 18:40:59 +0800
|
||||
Subject: [PATCH 6/6] drivers: mtd: spi-nor: Add calibration support for
|
||||
spi-nor
|
||||
|
||||
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
|
||||
---
|
||||
drivers/mtd/nand/spi/core.c | 5 ++++-
|
||||
drivers/mtd/spi-nor/core.c | 15 +++++++++++++++
|
||||
2 files changed, 19 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/mtd/nand/spi/core.c
|
||||
+++ b/drivers/mtd/nand/spi/core.c
|
||||
@@ -1020,7 +1020,10 @@ int spinand_cal_read(void *priv, u32 *ad
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
- ret = spinand_wait(spinand, &status);
|
||||
+ ret = spinand_wait(spinand,
|
||||
+ SPINAND_READ_INITIAL_DELAY_US,
|
||||
+ SPINAND_READ_POLL_DELAY_US,
|
||||
+ &status);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
--- a/drivers/mtd/spi-nor/core.c
|
||||
+++ b/drivers/mtd/spi-nor/core.c
|
||||
@@ -3378,6 +3378,18 @@ static const struct flash_info *spi_nor_
|
||||
return NULL;
|
||||
}
|
||||
|
||||
+static int spi_nor_cal_read(void *priv, u32 *addr, int addrlen, u8 *buf, int readlen)
|
||||
+{
|
||||
+ struct spi_nor *nor = (struct spi_nor *)priv;
|
||||
+
|
||||
+ nor->reg_proto = SNOR_PROTO_1_1_1;
|
||||
+ nor->read_proto = SNOR_PROTO_1_1_1;
|
||||
+ nor->read_opcode = SPINOR_OP_READ;
|
||||
+ nor->read_dummy = 0;
|
||||
+
|
||||
+ return nor->controller_ops->read(nor, *addr, readlen, buf);
|
||||
+}
|
||||
+
|
||||
static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor,
|
||||
const char *name)
|
||||
{
|
||||
@@ -3506,6 +3518,9 @@ int spi_nor_scan(struct spi_nor *nor, co
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
+ if(nor->spimem)
|
||||
+ spi_mem_do_calibration(nor->spimem, spi_nor_cal_read, nor);
|
||||
+
|
||||
info = spi_nor_get_flash_info(nor, name);
|
||||
if (IS_ERR(info))
|
||||
return PTR_ERR(info);
|
||||
|
|
@ -1,44 +0,0 @@
|
|||
From eb58bf4afd708eb3c64c7b9b2c5fbfacdcdee3e5 Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
|
||||
Date: Wed, 14 Feb 2024 15:04:54 +0100
|
||||
Subject: [PATCH] pwm: mediatek: add support for MT7988
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
MT7988 uses new registers layout just like MT7981 but it supports 8 PWM
|
||||
interfaces.
|
||||
|
||||
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
Reviewed-by: Daniel Golle <daniel@makrotopia.org>
|
||||
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20240214140454.6438-2-zajec5@gmail.com
|
||||
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
|
||||
---
|
||||
drivers/pwm/pwm-mediatek.c | 8 ++++++++
|
||||
1 file changed, 8 insertions(+)
|
||||
|
||||
--- a/drivers/pwm/pwm-mediatek.c
|
||||
+++ b/drivers/pwm/pwm-mediatek.c
|
||||
@@ -341,6 +341,13 @@ static const struct pwm_mediatek_of_data
|
||||
.reg_offset = mtk_pwm_reg_offset_v1,
|
||||
};
|
||||
|
||||
+static const struct pwm_mediatek_of_data mt7988_pwm_data = {
|
||||
+ .num_pwms = 8,
|
||||
+ .pwm45_fixup = false,
|
||||
+ .has_ck_26m_sel = false,
|
||||
+ .reg_offset = mtk_pwm_reg_offset_v2,
|
||||
+};
|
||||
+
|
||||
static const struct pwm_mediatek_of_data mt8183_pwm_data = {
|
||||
.num_pwms = 4,
|
||||
.pwm45_fixup = false,
|
||||
@@ -371,6 +378,7 @@ static const struct of_device_id pwm_med
|
||||
{ .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
|
||||
{ .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
|
||||
{ .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
|
||||
+ { .compatible = "mediatek,mt7988-pwm", .data = &mt7988_pwm_data },
|
||||
{ .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
|
||||
{ .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },
|
||||
{ .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
|
||||
|
|
@ -1,58 +0,0 @@
|
|||
From 6cf96078969ec00b873db99bae4e47001290685e Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
|
||||
Date: Wed, 27 Sep 2023 21:37:23 +0200
|
||||
Subject: [PATCH 35/42] thermal: lvts: Convert to platform remove callback
|
||||
returning void
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
The .remove() callback for a platform driver returns an int which makes
|
||||
many driver authors wrongly assume it's possible to do error handling by
|
||||
returning an error code. However the value returned is ignored (apart
|
||||
from emitting a warning) and this typically results in resource leaks.
|
||||
|
||||
To improve here there is a quest to make the remove callback return
|
||||
void. In the first step of this quest all drivers are converted to
|
||||
.remove_new(), which already returns void. Eventually after all drivers
|
||||
are converted, .remove_new() will be renamed to .remove().
|
||||
|
||||
Trivially convert this driver from always returning zero in the remove
|
||||
callback to the void returning variant.
|
||||
|
||||
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
|
||||
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
|
||||
---
|
||||
drivers/thermal/mediatek/lvts_thermal.c | 6 ++----
|
||||
1 file changed, 2 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/drivers/thermal/mediatek/lvts_thermal.c
|
||||
+++ b/drivers/thermal/mediatek/lvts_thermal.c
|
||||
@@ -1243,7 +1243,7 @@ static int lvts_probe(struct platform_de
|
||||
return 0;
|
||||
}
|
||||
|
||||
-static int lvts_remove(struct platform_device *pdev)
|
||||
+static void lvts_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct lvts_domain *lvts_td;
|
||||
int i;
|
||||
@@ -1254,8 +1254,6 @@ static int lvts_remove(struct platform_d
|
||||
lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
|
||||
|
||||
lvts_debugfs_exit(lvts_td);
|
||||
-
|
||||
- return 0;
|
||||
}
|
||||
|
||||
static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
|
||||
@@ -1356,7 +1354,7 @@ MODULE_DEVICE_TABLE(of, lvts_of_match);
|
||||
|
||||
static struct platform_driver lvts_driver = {
|
||||
.probe = lvts_probe,
|
||||
- .remove = lvts_remove,
|
||||
+ .remove_new = lvts_remove,
|
||||
.driver = {
|
||||
.name = "mtk-lvts-thermal",
|
||||
.of_match_table = lvts_of_match,
|
||||
|
|
@ -1,198 +0,0 @@
|
|||
From 26cc18a3d6d9eac21c4f4b4bb96147b2c6617c86 Mon Sep 17 00:00:00 2001
|
||||
From: Frank Wunderlich <frank-w@public-files.de>
|
||||
Date: Fri, 22 Sep 2023 07:50:19 +0200
|
||||
Subject: [PATCH 36/42] thermal/drivers/mediatek/lvts_thermal: Make coeff
|
||||
configurable
|
||||
|
||||
The upcoming mt7988 has different temperature coefficients so we
|
||||
cannot use constants in the functions lvts_golden_temp_init,
|
||||
lvts_golden_temp_init and lvts_raw_to_temp anymore.
|
||||
|
||||
Add a field in the lvts_ctrl pointing to the lvts_data which now
|
||||
contains the soc-specific temperature coefficents.
|
||||
|
||||
To make the code better readable, rename static int coeff_b to
|
||||
golden_temp_offset, COEFF_A to temp_factor and COEFF_B to temp_offset.
|
||||
|
||||
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
|
||||
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
Tested-by: Daniel Golle <daniel@makrotopia.org>
|
||||
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
Link: https://lore.kernel.org/r/20230922055020.6436-4-linux@fw-web.de
|
||||
---
|
||||
drivers/thermal/mediatek/lvts_thermal.c | 51 ++++++++++++++++---------
|
||||
1 file changed, 34 insertions(+), 17 deletions(-)
|
||||
|
||||
--- a/drivers/thermal/mediatek/lvts_thermal.c
|
||||
+++ b/drivers/thermal/mediatek/lvts_thermal.c
|
||||
@@ -80,8 +80,8 @@
|
||||
#define LVTS_SENSOR_MAX 4
|
||||
#define LVTS_GOLDEN_TEMP_MAX 62
|
||||
#define LVTS_GOLDEN_TEMP_DEFAULT 50
|
||||
-#define LVTS_COEFF_A -250460
|
||||
-#define LVTS_COEFF_B 250460
|
||||
+#define LVTS_COEFF_A_MT8195 -250460
|
||||
+#define LVTS_COEFF_B_MT8195 250460
|
||||
|
||||
#define LVTS_MSR_IMMEDIATE_MODE 0
|
||||
#define LVTS_MSR_FILTERED_MODE 1
|
||||
@@ -94,7 +94,7 @@
|
||||
#define LVTS_MINIMUM_THRESHOLD 20000
|
||||
|
||||
static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
|
||||
-static int coeff_b = LVTS_COEFF_B;
|
||||
+static int golden_temp_offset;
|
||||
|
||||
struct lvts_sensor_data {
|
||||
int dt_id;
|
||||
@@ -112,6 +112,8 @@ struct lvts_ctrl_data {
|
||||
struct lvts_data {
|
||||
const struct lvts_ctrl_data *lvts_ctrl;
|
||||
int num_lvts_ctrl;
|
||||
+ int temp_factor;
|
||||
+ int temp_offset;
|
||||
};
|
||||
|
||||
struct lvts_sensor {
|
||||
@@ -126,6 +128,7 @@ struct lvts_sensor {
|
||||
|
||||
struct lvts_ctrl {
|
||||
struct lvts_sensor sensors[LVTS_SENSOR_MAX];
|
||||
+ const struct lvts_data *lvts_data;
|
||||
u32 calibration[LVTS_SENSOR_MAX];
|
||||
u32 hw_tshut_raw_temp;
|
||||
int num_lvts_sensor;
|
||||
@@ -247,21 +250,21 @@ static void lvts_debugfs_exit(struct lvt
|
||||
|
||||
#endif
|
||||
|
||||
-static int lvts_raw_to_temp(u32 raw_temp)
|
||||
+static int lvts_raw_to_temp(u32 raw_temp, int temp_factor)
|
||||
{
|
||||
int temperature;
|
||||
|
||||
- temperature = ((s64)(raw_temp & 0xFFFF) * LVTS_COEFF_A) >> 14;
|
||||
- temperature += coeff_b;
|
||||
+ temperature = ((s64)(raw_temp & 0xFFFF) * temp_factor) >> 14;
|
||||
+ temperature += golden_temp_offset;
|
||||
|
||||
return temperature;
|
||||
}
|
||||
|
||||
-static u32 lvts_temp_to_raw(int temperature)
|
||||
+static u32 lvts_temp_to_raw(int temperature, int temp_factor)
|
||||
{
|
||||
- u32 raw_temp = ((s64)(coeff_b - temperature)) << 14;
|
||||
+ u32 raw_temp = ((s64)(golden_temp_offset - temperature)) << 14;
|
||||
|
||||
- raw_temp = div_s64(raw_temp, -LVTS_COEFF_A);
|
||||
+ raw_temp = div_s64(raw_temp, -temp_factor);
|
||||
|
||||
return raw_temp;
|
||||
}
|
||||
@@ -269,6 +272,9 @@ static u32 lvts_temp_to_raw(int temperat
|
||||
static int lvts_get_temp(struct thermal_zone_device *tz, int *temp)
|
||||
{
|
||||
struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
|
||||
+ struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl,
|
||||
+ sensors[lvts_sensor->id]);
|
||||
+ const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
|
||||
void __iomem *msr = lvts_sensor->msr;
|
||||
u32 value;
|
||||
int rc;
|
||||
@@ -301,7 +307,7 @@ static int lvts_get_temp(struct thermal_
|
||||
if (rc)
|
||||
return -EAGAIN;
|
||||
|
||||
- *temp = lvts_raw_to_temp(value & 0xFFFF);
|
||||
+ *temp = lvts_raw_to_temp(value & 0xFFFF, lvts_data->temp_factor);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -348,10 +354,13 @@ static bool lvts_should_update_thresh(st
|
||||
static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high)
|
||||
{
|
||||
struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
|
||||
- struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, sensors[lvts_sensor->id]);
|
||||
+ struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl,
|
||||
+ sensors[lvts_sensor->id]);
|
||||
+ const struct lvts_data *lvts_data = lvts_ctrl->lvts_data;
|
||||
void __iomem *base = lvts_sensor->base;
|
||||
- u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD);
|
||||
- u32 raw_high = lvts_temp_to_raw(high);
|
||||
+ u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD,
|
||||
+ lvts_data->temp_factor);
|
||||
+ u32 raw_high = lvts_temp_to_raw(high, lvts_data->temp_factor);
|
||||
bool should_update_thresh;
|
||||
|
||||
lvts_sensor->low_thresh = low;
|
||||
@@ -694,7 +703,7 @@ static int lvts_calibration_read(struct
|
||||
return 0;
|
||||
}
|
||||
|
||||
-static int lvts_golden_temp_init(struct device *dev, u32 *value)
|
||||
+static int lvts_golden_temp_init(struct device *dev, u32 *value, int temp_offset)
|
||||
{
|
||||
u32 gt;
|
||||
|
||||
@@ -703,7 +712,7 @@ static int lvts_golden_temp_init(struct
|
||||
if (gt && gt < LVTS_GOLDEN_TEMP_MAX)
|
||||
golden_temp = gt;
|
||||
|
||||
- coeff_b = golden_temp * 500 + LVTS_COEFF_B;
|
||||
+ golden_temp_offset = golden_temp * 500 + temp_offset;
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -726,7 +735,7 @@ static int lvts_ctrl_init(struct device
|
||||
* The golden temp information is contained in the first chunk
|
||||
* of efuse data.
|
||||
*/
|
||||
- ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib);
|
||||
+ ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib, lvts_data->temp_offset);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
@@ -737,6 +746,7 @@ static int lvts_ctrl_init(struct device
|
||||
for (i = 0; i < lvts_data->num_lvts_ctrl; i++) {
|
||||
|
||||
lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset;
|
||||
+ lvts_ctrl[i].lvts_data = lvts_data;
|
||||
|
||||
ret = lvts_sensor_init(dev, &lvts_ctrl[i],
|
||||
&lvts_data->lvts_ctrl[i]);
|
||||
@@ -760,7 +770,8 @@ static int lvts_ctrl_init(struct device
|
||||
* after initializing the calibration.
|
||||
*/
|
||||
lvts_ctrl[i].hw_tshut_raw_temp =
|
||||
- lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp);
|
||||
+ lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp,
|
||||
+ lvts_data->temp_factor);
|
||||
|
||||
lvts_ctrl[i].low_thresh = INT_MIN;
|
||||
lvts_ctrl[i].high_thresh = INT_MIN;
|
||||
@@ -1225,6 +1236,8 @@ static int lvts_probe(struct platform_de
|
||||
if (irq < 0)
|
||||
return irq;
|
||||
|
||||
+ golden_temp_offset = lvts_data->temp_offset;
|
||||
+
|
||||
ret = lvts_domain_init(dev, lvts_td, lvts_data);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n");
|
||||
@@ -1338,11 +1351,15 @@ static const struct lvts_ctrl_data mt819
|
||||
static const struct lvts_data mt8195_lvts_mcu_data = {
|
||||
.lvts_ctrl = mt8195_lvts_mcu_data_ctrl,
|
||||
.num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
|
||||
+ .temp_factor = LVTS_COEFF_A_MT8195,
|
||||
+ .temp_offset = LVTS_COEFF_B_MT8195,
|
||||
};
|
||||
|
||||
static const struct lvts_data mt8195_lvts_ap_data = {
|
||||
.lvts_ctrl = mt8195_lvts_ap_data_ctrl,
|
||||
.num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl),
|
||||
+ .temp_factor = LVTS_COEFF_A_MT8195,
|
||||
+ .temp_offset = LVTS_COEFF_B_MT8195,
|
||||
};
|
||||
|
||||
static const struct of_device_id lvts_of_match[] = {
|
||||
|
|
@ -1,91 +0,0 @@
|
|||
From 9924e9b91b43aaa1610a1d59c4caa43785948cf6 Mon Sep 17 00:00:00 2001
|
||||
From: Frank Wunderlich <frank-w@public-files.de>
|
||||
Date: Fri, 22 Sep 2023 07:50:20 +0200
|
||||
Subject: [PATCH 37/42] thermal/drivers/mediatek/lvts_thermal: Add mt7988
|
||||
support
|
||||
|
||||
Add Support for Mediatek Filogic 880/MT7988 LVTS.
|
||||
|
||||
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
|
||||
Tested-by: Daniel Golle <daniel@makrotopia.org>
|
||||
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
Link: https://lore.kernel.org/r/20230922055020.6436-5-linux@fw-web.de
|
||||
---
|
||||
drivers/thermal/mediatek/lvts_thermal.c | 38 +++++++++++++++++++++++++
|
||||
1 file changed, 38 insertions(+)
|
||||
|
||||
--- a/drivers/thermal/mediatek/lvts_thermal.c
|
||||
+++ b/drivers/thermal/mediatek/lvts_thermal.c
|
||||
@@ -82,6 +82,8 @@
|
||||
#define LVTS_GOLDEN_TEMP_DEFAULT 50
|
||||
#define LVTS_COEFF_A_MT8195 -250460
|
||||
#define LVTS_COEFF_B_MT8195 250460
|
||||
+#define LVTS_COEFF_A_MT7988 -204650
|
||||
+#define LVTS_COEFF_B_MT7988 204650
|
||||
|
||||
#define LVTS_MSR_IMMEDIATE_MODE 0
|
||||
#define LVTS_MSR_FILTERED_MODE 1
|
||||
@@ -89,6 +91,7 @@
|
||||
#define LVTS_MSR_READ_TIMEOUT_US 400
|
||||
#define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2)
|
||||
|
||||
+#define LVTS_HW_SHUTDOWN_MT7988 105000
|
||||
#define LVTS_HW_SHUTDOWN_MT8195 105000
|
||||
|
||||
#define LVTS_MINIMUM_THRESHOLD 20000
|
||||
@@ -1269,6 +1272,33 @@ static void lvts_remove(struct platform_
|
||||
lvts_debugfs_exit(lvts_td);
|
||||
}
|
||||
|
||||
+static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] = {
|
||||
+ {
|
||||
+ .cal_offset = { 0x00, 0x04, 0x08, 0x0c },
|
||||
+ .lvts_sensor = {
|
||||
+ { .dt_id = MT7988_CPU_0 },
|
||||
+ { .dt_id = MT7988_CPU_1 },
|
||||
+ { .dt_id = MT7988_ETH2P5G_0 },
|
||||
+ { .dt_id = MT7988_ETH2P5G_1 }
|
||||
+ },
|
||||
+ .num_lvts_sensor = 4,
|
||||
+ .offset = 0x0,
|
||||
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988,
|
||||
+ },
|
||||
+ {
|
||||
+ .cal_offset = { 0x14, 0x18, 0x1c, 0x20 },
|
||||
+ .lvts_sensor = {
|
||||
+ { .dt_id = MT7988_TOPS_0},
|
||||
+ { .dt_id = MT7988_TOPS_1},
|
||||
+ { .dt_id = MT7988_ETHWARP_0},
|
||||
+ { .dt_id = MT7988_ETHWARP_1}
|
||||
+ },
|
||||
+ .num_lvts_sensor = 4,
|
||||
+ .offset = 0x100,
|
||||
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988,
|
||||
+ }
|
||||
+};
|
||||
+
|
||||
static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
|
||||
{
|
||||
.cal_offset = { 0x04, 0x07 },
|
||||
@@ -1348,6 +1378,13 @@ static const struct lvts_ctrl_data mt819
|
||||
}
|
||||
};
|
||||
|
||||
+static const struct lvts_data mt7988_lvts_ap_data = {
|
||||
+ .lvts_ctrl = mt7988_lvts_ap_data_ctrl,
|
||||
+ .num_lvts_ctrl = ARRAY_SIZE(mt7988_lvts_ap_data_ctrl),
|
||||
+ .temp_factor = LVTS_COEFF_A_MT7988,
|
||||
+ .temp_offset = LVTS_COEFF_B_MT7988,
|
||||
+};
|
||||
+
|
||||
static const struct lvts_data mt8195_lvts_mcu_data = {
|
||||
.lvts_ctrl = mt8195_lvts_mcu_data_ctrl,
|
||||
.num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
|
||||
@@ -1363,6 +1400,7 @@ static const struct lvts_data mt8195_lvt
|
||||
};
|
||||
|
||||
static const struct of_device_id lvts_of_match[] = {
|
||||
+ { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data },
|
||||
{ .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
|
||||
{ .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
|
||||
{},
|
||||
|
|
@ -1,30 +0,0 @@
|
|||
From fb1bbb5b63e4e3c788a978724749ced57d208054 Mon Sep 17 00:00:00 2001
|
||||
From: Minjie Du <duminjie@vivo.com>
|
||||
Date: Thu, 21 Sep 2023 17:10:50 +0800
|
||||
Subject: [PATCH 38/42] thermal/drivers/mediatek/lvts_thermal: Fix error check
|
||||
in lvts_debugfs_init()
|
||||
|
||||
debugfs_create_dir() function returns an error value embedded in
|
||||
the pointer (PTR_ERR). Evaluate the return value using IS_ERR
|
||||
rather than checking for NULL.
|
||||
|
||||
Signed-off-by: Minjie Du <duminjie@vivo.com>
|
||||
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
|
||||
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
|
||||
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
Link: https://lore.kernel.org/r/20230921091057.3812-1-duminjie@vivo.com
|
||||
---
|
||||
drivers/thermal/mediatek/lvts_thermal.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/thermal/mediatek/lvts_thermal.c
|
||||
+++ b/drivers/thermal/mediatek/lvts_thermal.c
|
||||
@@ -219,7 +219,7 @@ static int lvts_debugfs_init(struct devi
|
||||
|
||||
sprintf(name, "controller%d", i);
|
||||
dentry = debugfs_create_dir(name, lvts_td->dom_dentry);
|
||||
- if (!dentry)
|
||||
+ if (IS_ERR(dentry))
|
||||
continue;
|
||||
|
||||
regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
|
||||
|
|
@ -1,83 +0,0 @@
|
|||
From a1d874ef3376295ee8ed89b3b5315f4c840ff00b Mon Sep 17 00:00:00 2001
|
||||
From: Balsam CHIHI <bchihi@baylibre.com>
|
||||
Date: Tue, 17 Oct 2023 21:05:42 +0200
|
||||
Subject: [PATCH 40/42] thermal/drivers/mediatek/lvts_thermal: Add suspend and
|
||||
resume
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
Add suspend and resume support to LVTS driver.
|
||||
|
||||
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
|
||||
[bero@baylibre.com: suspend/resume in noirq phase]
|
||||
Co-developed-by: Bernhard Rosenkränzer <bero@baylibre.com>
|
||||
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
|
||||
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
|
||||
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
|
||||
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
Link: https://lore.kernel.org/r/20231017190545.157282-3-bero@baylibre.com
|
||||
---
|
||||
drivers/thermal/mediatek/lvts_thermal.c | 37 +++++++++++++++++++++++++
|
||||
1 file changed, 37 insertions(+)
|
||||
|
||||
--- a/drivers/thermal/mediatek/lvts_thermal.c
|
||||
+++ b/drivers/thermal/mediatek/lvts_thermal.c
|
||||
@@ -1299,6 +1299,38 @@ static const struct lvts_ctrl_data mt798
|
||||
}
|
||||
};
|
||||
|
||||
+static int lvts_suspend(struct device *dev)
|
||||
+{
|
||||
+ struct lvts_domain *lvts_td;
|
||||
+ int i;
|
||||
+
|
||||
+ lvts_td = dev_get_drvdata(dev);
|
||||
+
|
||||
+ for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
|
||||
+ lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
|
||||
+
|
||||
+ clk_disable_unprepare(lvts_td->clk);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int lvts_resume(struct device *dev)
|
||||
+{
|
||||
+ struct lvts_domain *lvts_td;
|
||||
+ int i, ret;
|
||||
+
|
||||
+ lvts_td = dev_get_drvdata(dev);
|
||||
+
|
||||
+ ret = clk_prepare_enable(lvts_td->clk);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
|
||||
+ lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
|
||||
{
|
||||
.cal_offset = { 0x04, 0x07 },
|
||||
@@ -1407,12 +1439,17 @@ static const struct of_device_id lvts_of
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, lvts_of_match);
|
||||
|
||||
+static const struct dev_pm_ops lvts_pm_ops = {
|
||||
+ NOIRQ_SYSTEM_SLEEP_PM_OPS(lvts_suspend, lvts_resume)
|
||||
+};
|
||||
+
|
||||
static struct platform_driver lvts_driver = {
|
||||
.probe = lvts_probe,
|
||||
.remove_new = lvts_remove,
|
||||
.driver = {
|
||||
.name = "mtk-lvts-thermal",
|
||||
.of_match_table = lvts_of_match,
|
||||
+ .pm = &lvts_pm_ops,
|
||||
},
|
||||
};
|
||||
module_platform_driver(lvts_driver);
|
||||
|
|
@ -1,151 +0,0 @@
|
|||
From 7d8b3864b38d881cf105328ff8569f47446811ad Mon Sep 17 00:00:00 2001
|
||||
From: Balsam CHIHI <bchihi@baylibre.com>
|
||||
Date: Tue, 17 Oct 2023 21:05:43 +0200
|
||||
Subject: [PATCH 41/42] thermal/drivers/mediatek/lvts_thermal: Add mt8192
|
||||
support
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
Add LVTS Driver support for MT8192.
|
||||
|
||||
Co-developed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
|
||||
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
|
||||
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
|
||||
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
|
||||
[bero@baylibre.com: cosmetic changes, rebase]
|
||||
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
|
||||
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
|
||||
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
|
||||
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
Link: https://lore.kernel.org/r/20231017190545.157282-4-bero@baylibre.com
|
||||
---
|
||||
drivers/thermal/mediatek/lvts_thermal.c | 95 +++++++++++++++++++++++++
|
||||
1 file changed, 95 insertions(+)
|
||||
|
||||
--- a/drivers/thermal/mediatek/lvts_thermal.c
|
||||
+++ b/drivers/thermal/mediatek/lvts_thermal.c
|
||||
@@ -92,6 +92,7 @@
|
||||
#define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2)
|
||||
|
||||
#define LVTS_HW_SHUTDOWN_MT7988 105000
|
||||
+#define LVTS_HW_SHUTDOWN_MT8192 105000
|
||||
#define LVTS_HW_SHUTDOWN_MT8195 105000
|
||||
|
||||
#define LVTS_MINIMUM_THRESHOLD 20000
|
||||
@@ -1331,6 +1332,88 @@ static int lvts_resume(struct device *de
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = {
|
||||
+ {
|
||||
+ .cal_offset = { 0x04, 0x08 },
|
||||
+ .lvts_sensor = {
|
||||
+ { .dt_id = MT8192_MCU_BIG_CPU0 },
|
||||
+ { .dt_id = MT8192_MCU_BIG_CPU1 }
|
||||
+ },
|
||||
+ .num_lvts_sensor = 2,
|
||||
+ .offset = 0x0,
|
||||
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
|
||||
+ .mode = LVTS_MSR_FILTERED_MODE,
|
||||
+ },
|
||||
+ {
|
||||
+ .cal_offset = { 0x0c, 0x10 },
|
||||
+ .lvts_sensor = {
|
||||
+ { .dt_id = MT8192_MCU_BIG_CPU2 },
|
||||
+ { .dt_id = MT8192_MCU_BIG_CPU3 }
|
||||
+ },
|
||||
+ .num_lvts_sensor = 2,
|
||||
+ .offset = 0x100,
|
||||
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
|
||||
+ .mode = LVTS_MSR_FILTERED_MODE,
|
||||
+ },
|
||||
+ {
|
||||
+ .cal_offset = { 0x14, 0x18, 0x1c, 0x20 },
|
||||
+ .lvts_sensor = {
|
||||
+ { .dt_id = MT8192_MCU_LITTLE_CPU0 },
|
||||
+ { .dt_id = MT8192_MCU_LITTLE_CPU1 },
|
||||
+ { .dt_id = MT8192_MCU_LITTLE_CPU2 },
|
||||
+ { .dt_id = MT8192_MCU_LITTLE_CPU3 }
|
||||
+ },
|
||||
+ .num_lvts_sensor = 4,
|
||||
+ .offset = 0x200,
|
||||
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
|
||||
+ .mode = LVTS_MSR_FILTERED_MODE,
|
||||
+ }
|
||||
+};
|
||||
+
|
||||
+static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = {
|
||||
+ {
|
||||
+ .cal_offset = { 0x24, 0x28 },
|
||||
+ .lvts_sensor = {
|
||||
+ { .dt_id = MT8192_AP_VPU0 },
|
||||
+ { .dt_id = MT8192_AP_VPU1 }
|
||||
+ },
|
||||
+ .num_lvts_sensor = 2,
|
||||
+ .offset = 0x0,
|
||||
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
|
||||
+ },
|
||||
+ {
|
||||
+ .cal_offset = { 0x2c, 0x30 },
|
||||
+ .lvts_sensor = {
|
||||
+ { .dt_id = MT8192_AP_GPU0 },
|
||||
+ { .dt_id = MT8192_AP_GPU1 }
|
||||
+ },
|
||||
+ .num_lvts_sensor = 2,
|
||||
+ .offset = 0x100,
|
||||
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
|
||||
+ },
|
||||
+ {
|
||||
+ .cal_offset = { 0x34, 0x38 },
|
||||
+ .lvts_sensor = {
|
||||
+ { .dt_id = MT8192_AP_INFRA },
|
||||
+ { .dt_id = MT8192_AP_CAM },
|
||||
+ },
|
||||
+ .num_lvts_sensor = 2,
|
||||
+ .offset = 0x200,
|
||||
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
|
||||
+ },
|
||||
+ {
|
||||
+ .cal_offset = { 0x3c, 0x40, 0x44 },
|
||||
+ .lvts_sensor = {
|
||||
+ { .dt_id = MT8192_AP_MD0 },
|
||||
+ { .dt_id = MT8192_AP_MD1 },
|
||||
+ { .dt_id = MT8192_AP_MD2 }
|
||||
+ },
|
||||
+ .num_lvts_sensor = 3,
|
||||
+ .offset = 0x300,
|
||||
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
|
||||
+ }
|
||||
+};
|
||||
+
|
||||
static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
|
||||
{
|
||||
.cal_offset = { 0x04, 0x07 },
|
||||
@@ -1417,6 +1500,16 @@ static const struct lvts_data mt7988_lvt
|
||||
.temp_offset = LVTS_COEFF_B_MT7988,
|
||||
};
|
||||
|
||||
+static const struct lvts_data mt8192_lvts_mcu_data = {
|
||||
+ .lvts_ctrl = mt8192_lvts_mcu_data_ctrl,
|
||||
+ .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl),
|
||||
+};
|
||||
+
|
||||
+static const struct lvts_data mt8192_lvts_ap_data = {
|
||||
+ .lvts_ctrl = mt8192_lvts_ap_data_ctrl,
|
||||
+ .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl),
|
||||
+};
|
||||
+
|
||||
static const struct lvts_data mt8195_lvts_mcu_data = {
|
||||
.lvts_ctrl = mt8195_lvts_mcu_data_ctrl,
|
||||
.num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
|
||||
@@ -1433,6 +1526,8 @@ static const struct lvts_data mt8195_lvt
|
||||
|
||||
static const struct of_device_id lvts_of_match[] = {
|
||||
{ .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data },
|
||||
+ { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data },
|
||||
+ { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data },
|
||||
{ .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
|
||||
{ .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
|
||||
{},
|
||||
|
|
@ -1,70 +0,0 @@
|
|||
From 5d126a3c87cf7964b28bacf3826eea4266265bce Mon Sep 17 00:00:00 2001
|
||||
From: Balsam CHIHI <bchihi@baylibre.com>
|
||||
Date: Tue, 17 Oct 2023 21:05:45 +0200
|
||||
Subject: [PATCH 42/42] thermal/drivers/mediatek/lvts_thermal: Update
|
||||
calibration data documentation
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
Update LVTS calibration data documentation for mt8192 and mt8195.
|
||||
|
||||
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
|
||||
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
|
||||
[bero@baylibre.com: Fix issues pointed out by Nícolas F. R. A. Prado <nfraprado@collabora.com>]
|
||||
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
|
||||
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com>
|
||||
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
Link: https://lore.kernel.org/r/20231017190545.157282-6-bero@baylibre.com
|
||||
---
|
||||
drivers/thermal/mediatek/lvts_thermal.c | 31 +++++++++++++++++++++++--
|
||||
1 file changed, 29 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/thermal/mediatek/lvts_thermal.c
|
||||
+++ b/drivers/thermal/mediatek/lvts_thermal.c
|
||||
@@ -616,7 +616,34 @@ static int lvts_sensor_init(struct devic
|
||||
* The efuse blob values follows the sensor enumeration per thermal
|
||||
* controller. The decoding of the stream is as follow:
|
||||
*
|
||||
- * stream index map for MCU Domain :
|
||||
+ * MT8192 :
|
||||
+ * Stream index map for MCU Domain mt8192 :
|
||||
+ *
|
||||
+ * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
|
||||
+ * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B
|
||||
+ *
|
||||
+ * <-----sensor#2-----> <-----sensor#3----->
|
||||
+ * 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13
|
||||
+ *
|
||||
+ * <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
|
||||
+ * 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23
|
||||
+ *
|
||||
+ * Stream index map for AP Domain mt8192 :
|
||||
+ *
|
||||
+ * <-----sensor#0-----> <-----sensor#1----->
|
||||
+ * 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B
|
||||
+ *
|
||||
+ * <-----sensor#2-----> <-----sensor#3----->
|
||||
+ * 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33
|
||||
+ *
|
||||
+ * <-----sensor#4-----> <-----sensor#5----->
|
||||
+ * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B
|
||||
+ *
|
||||
+ * <-----sensor#6-----> <-----sensor#7-----> <-----sensor#8----->
|
||||
+ * 0x3C | 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47
|
||||
+ *
|
||||
+ * MT8195 :
|
||||
+ * Stream index map for MCU Domain mt8195 :
|
||||
*
|
||||
* <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
|
||||
* 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09
|
||||
@@ -627,7 +654,7 @@ static int lvts_sensor_init(struct devic
|
||||
* <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
|
||||
* 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21
|
||||
*
|
||||
- * stream index map for AP Domain :
|
||||
+ * Stream index map for AP Domain mt8195 :
|
||||
*
|
||||
* <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1----->
|
||||
* 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A
|
||||
|
|
@ -1,45 +0,0 @@
|
|||
From 3bf827929a44c17bfb1bf1000b143c02ce26a929 Mon Sep 17 00:00:00 2001
|
||||
From: Daniel Golle <daniel@makrotopia.org>
|
||||
Date: Sat, 26 Aug 2023 21:56:51 +0100
|
||||
Subject: [PATCH] i2c: mt65xx: allow optional pmic clock
|
||||
|
||||
Using the I2C host controller on the MT7981 SoC requires 4 clocks to
|
||||
be enabled. One of them, the pmic clk, is only enabled in case
|
||||
'mediatek,have-pmic' is also set which has other consequences which
|
||||
are not desired in this case.
|
||||
|
||||
Allow defining a pmic clk even in case the 'mediatek,have-pmic' propterty
|
||||
is not present and the bus is not used to connect to a pmic, but may
|
||||
still require to enable the pmic clock.
|
||||
|
||||
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||
---
|
||||
drivers/i2c/busses/i2c-mt65xx.c | 12 ++++++++----
|
||||
1 file changed, 8 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/drivers/i2c/busses/i2c-mt65xx.c
|
||||
+++ b/drivers/i2c/busses/i2c-mt65xx.c
|
||||
@@ -1442,15 +1442,19 @@ static int mtk_i2c_probe(struct platform
|
||||
if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk))
|
||||
return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk);
|
||||
|
||||
+ i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get_optional(&pdev->dev, "pmic");
|
||||
+ if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) {
|
||||
+ dev_err(&pdev->dev, "cannot get pmic clock\n");
|
||||
+ return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk);
|
||||
+ }
|
||||
+
|
||||
if (i2c->have_pmic) {
|
||||
- i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get(&pdev->dev, "pmic");
|
||||
- if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) {
|
||||
+ if (!i2c->clocks[I2C_MT65XX_CLK_PMIC].clk) {
|
||||
dev_err(&pdev->dev, "cannot get pmic clock\n");
|
||||
- return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk);
|
||||
+ return -ENODEV;
|
||||
}
|
||||
speed_clk = I2C_MT65XX_CLK_PMIC;
|
||||
} else {
|
||||
- i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = NULL;
|
||||
speed_clk = I2C_MT65XX_CLK_MAIN;
|
||||
}
|
||||
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
From f3f0934e5c7b9c16e0cb2435be3555382e6293ad Mon Sep 17 00:00:00 2001
|
||||
From: Maso Huang <maso.huang@mediatek.com>
|
||||
Date: Tue, 24 Oct 2023 11:50:17 +0800
|
||||
Subject: [PATCH 7/9] ASoC: mediatek: mt7986: drop the remove callback of
|
||||
mt7986_wm8960
|
||||
|
||||
Drop the remove callback of mt7986_wm8960.
|
||||
|
||||
Signed-off-by: Maso Huang <maso.huang@mediatek.com>
|
||||
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20231024035019.11732-2-maso.huang@mediatek.com
|
||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
||||
---
|
||||
sound/soc/mediatek/mt7986/mt7986-wm8960.c | 10 ----------
|
||||
1 file changed, 10 deletions(-)
|
||||
|
||||
--- a/sound/soc/mediatek/mt7986/mt7986-wm8960.c
|
||||
+++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c
|
||||
@@ -163,15 +163,6 @@ err_of_node_put:
|
||||
return ret;
|
||||
}
|
||||
|
||||
-static void mt7986_wm8960_machine_remove(struct platform_device *pdev)
|
||||
-{
|
||||
- struct snd_soc_card *card = platform_get_drvdata(pdev);
|
||||
- struct mt7986_wm8960_priv *priv = snd_soc_card_get_drvdata(card);
|
||||
-
|
||||
- of_node_put(priv->codec_node);
|
||||
- of_node_put(priv->platform_node);
|
||||
-}
|
||||
-
|
||||
static const struct of_device_id mt7986_wm8960_machine_dt_match[] = {
|
||||
{.compatible = "mediatek,mt7986-wm8960-sound"},
|
||||
{ /* sentinel */ }
|
||||
@@ -184,7 +175,6 @@ static struct platform_driver mt7986_wm8
|
||||
.of_match_table = mt7986_wm8960_machine_dt_match,
|
||||
},
|
||||
.probe = mt7986_wm8960_machine_probe,
|
||||
- .remove_new = mt7986_wm8960_machine_remove,
|
||||
};
|
||||
|
||||
module_platform_driver(mt7986_wm8960_machine);
|
||||
|
|
@ -1,105 +0,0 @@
|
|||
From 98b8fb2cb4fcab1903d0baf611bf0c3f822a08dc Mon Sep 17 00:00:00 2001
|
||||
From: Maso Huang <maso.huang@mediatek.com>
|
||||
Date: Tue, 24 Oct 2023 11:50:18 +0800
|
||||
Subject: [PATCH 8/9] ASoC: mediatek: mt7986: remove the mt7986_wm8960_priv
|
||||
structure
|
||||
|
||||
Remove the mt7986_wm8960_priv structure.
|
||||
|
||||
Signed-off-by: Maso Huang <maso.huang@mediatek.com>
|
||||
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20231024035019.11732-3-maso.huang@mediatek.com
|
||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
||||
---
|
||||
sound/soc/mediatek/mt7986/mt7986-wm8960.c | 33 +++++++++--------------
|
||||
1 file changed, 12 insertions(+), 21 deletions(-)
|
||||
|
||||
--- a/sound/soc/mediatek/mt7986/mt7986-wm8960.c
|
||||
+++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c
|
||||
@@ -12,11 +12,6 @@
|
||||
|
||||
#include "mt7986-afe-common.h"
|
||||
|
||||
-struct mt7986_wm8960_priv {
|
||||
- struct device_node *platform_node;
|
||||
- struct device_node *codec_node;
|
||||
-};
|
||||
-
|
||||
static const struct snd_soc_dapm_widget mt7986_wm8960_widgets[] = {
|
||||
SND_SOC_DAPM_HP("Headphone", NULL),
|
||||
SND_SOC_DAPM_MIC("AMIC", NULL),
|
||||
@@ -92,20 +87,18 @@ static int mt7986_wm8960_machine_probe(s
|
||||
struct snd_soc_card *card = &mt7986_wm8960_card;
|
||||
struct snd_soc_dai_link *dai_link;
|
||||
struct device_node *platform, *codec;
|
||||
- struct mt7986_wm8960_priv *priv;
|
||||
+ struct device_node *platform_dai_node, *codec_dai_node;
|
||||
int ret, i;
|
||||
|
||||
- priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
|
||||
- if (!priv)
|
||||
- return -ENOMEM;
|
||||
+ card->dev = &pdev->dev;
|
||||
|
||||
platform = of_get_child_by_name(pdev->dev.of_node, "platform");
|
||||
|
||||
if (platform) {
|
||||
- priv->platform_node = of_parse_phandle(platform, "sound-dai", 0);
|
||||
+ platform_dai_node = of_parse_phandle(platform, "sound-dai", 0);
|
||||
of_node_put(platform);
|
||||
|
||||
- if (!priv->platform_node) {
|
||||
+ if (!platform_dai_node) {
|
||||
dev_err(&pdev->dev, "Failed to parse platform/sound-dai property\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
@@ -117,24 +110,22 @@ static int mt7986_wm8960_machine_probe(s
|
||||
for_each_card_prelinks(card, i, dai_link) {
|
||||
if (dai_link->platforms->name)
|
||||
continue;
|
||||
- dai_link->platforms->of_node = priv->platform_node;
|
||||
+ dai_link->platforms->of_node = platform_dai_node;
|
||||
}
|
||||
|
||||
- card->dev = &pdev->dev;
|
||||
-
|
||||
codec = of_get_child_by_name(pdev->dev.of_node, "codec");
|
||||
|
||||
if (codec) {
|
||||
- priv->codec_node = of_parse_phandle(codec, "sound-dai", 0);
|
||||
+ codec_dai_node = of_parse_phandle(codec, "sound-dai", 0);
|
||||
of_node_put(codec);
|
||||
|
||||
- if (!priv->codec_node) {
|
||||
- of_node_put(priv->platform_node);
|
||||
+ if (!codec_dai_node) {
|
||||
+ of_node_put(platform_dai_node);
|
||||
dev_err(&pdev->dev, "Failed to parse codec/sound-dai property\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
} else {
|
||||
- of_node_put(priv->platform_node);
|
||||
+ of_node_put(platform_dai_node);
|
||||
dev_err(&pdev->dev, "Property 'codec' missing or invalid\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
@@ -142,7 +133,7 @@ static int mt7986_wm8960_machine_probe(s
|
||||
for_each_card_prelinks(card, i, dai_link) {
|
||||
if (dai_link->codecs->name)
|
||||
continue;
|
||||
- dai_link->codecs->of_node = priv->codec_node;
|
||||
+ dai_link->codecs->of_node = codec_dai_node;
|
||||
}
|
||||
|
||||
ret = snd_soc_of_parse_audio_routing(card, "audio-routing");
|
||||
@@ -158,8 +149,8 @@ static int mt7986_wm8960_machine_probe(s
|
||||
}
|
||||
|
||||
err_of_node_put:
|
||||
- of_node_put(priv->codec_node);
|
||||
- of_node_put(priv->platform_node);
|
||||
+ of_node_put(platform_dai_node);
|
||||
+ of_node_put(codec_dai_node);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -1,49 +0,0 @@
|
|||
From 4e229f4264f4be7a6a554487714c0913ef59cf7f Mon Sep 17 00:00:00 2001
|
||||
From: Maso Huang <maso.huang@mediatek.com>
|
||||
Date: Tue, 24 Oct 2023 11:50:19 +0800
|
||||
Subject: [PATCH 9/9] ASoC: mediatek: mt7986: add sample rate checker
|
||||
|
||||
mt7986 only supports 8/12/16/24/32/48/96/192 kHz
|
||||
|
||||
Signed-off-by: Maso Huang <maso.huang@mediatek.com>
|
||||
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20231024035019.11732-4-maso.huang@mediatek.com
|
||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
||||
---
|
||||
sound/soc/mediatek/mt7986/mt7986-dai-etdm.c | 23 +++++++++++++++++----
|
||||
1 file changed, 19 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/sound/soc/mediatek/mt7986/mt7986-dai-etdm.c
|
||||
+++ b/sound/soc/mediatek/mt7986/mt7986-dai-etdm.c
|
||||
@@ -237,12 +237,27 @@ static int mtk_dai_etdm_hw_params(struct
|
||||
struct snd_pcm_hw_params *params,
|
||||
struct snd_soc_dai *dai)
|
||||
{
|
||||
+ unsigned int rate = params_rate(params);
|
||||
struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
|
||||
|
||||
- mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_PLAYBACK);
|
||||
- mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_CAPTURE);
|
||||
-
|
||||
- return 0;
|
||||
+ switch (rate) {
|
||||
+ case 8000:
|
||||
+ case 12000:
|
||||
+ case 16000:
|
||||
+ case 24000:
|
||||
+ case 32000:
|
||||
+ case 48000:
|
||||
+ case 96000:
|
||||
+ case 192000:
|
||||
+ mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_PLAYBACK);
|
||||
+ mtk_dai_etdm_config(afe, params, dai, SNDRV_PCM_STREAM_CAPTURE);
|
||||
+ return 0;
|
||||
+ default:
|
||||
+ dev_err(afe->dev,
|
||||
+ "Sample rate %d invalid. Supported rates: 8/12/16/24/32/48/96/192 kHz\n",
|
||||
+ rate);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
}
|
||||
|
||||
static int mtk_dai_etdm_trigger(struct snd_pcm_substream *substream, int cmd,
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
From e4cde335d1771863a60b6931e51357b8470e85c4 Mon Sep 17 00:00:00 2001
|
||||
From: Daniel Golle <daniel@makrotopia.org>
|
||||
Date: Sun, 10 Dec 2023 22:41:39 +0000
|
||||
Subject: [PATCH] ASoC: mediatek: mt7986: silence error in case of
|
||||
-EPROBE_DEFER
|
||||
|
||||
If probe is defered no error should be printed. Mute it.
|
||||
|
||||
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||
---
|
||||
sound/soc/mediatek/mt7986/mt7986-wm8960.c | 4 +++-
|
||||
1 file changed, 3 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/sound/soc/mediatek/mt7986/mt7986-wm8960.c
|
||||
+++ b/sound/soc/mediatek/mt7986/mt7986-wm8960.c
|
||||
@@ -144,7 +144,9 @@ static int mt7986_wm8960_machine_probe(s
|
||||
|
||||
ret = devm_snd_soc_register_card(&pdev->dev, card);
|
||||
if (ret) {
|
||||
- dev_err(&pdev->dev, "%s snd_soc_register_card fail: %d\n", __func__, ret);
|
||||
+ if (ret != -EPROBE_DEFER)
|
||||
+ dev_err(&pdev->dev, "%s snd_soc_register_card fail: %d\n", __func__, ret);
|
||||
+
|
||||
goto err_of_node_put;
|
||||
}
|
||||
|
||||
|
|
@ -1,54 +0,0 @@
|
|||
--- a/arch/arm/Kconfig
|
||||
+++ b/arch/arm/Kconfig
|
||||
@@ -1568,6 +1568,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
|
||||
|
||||
endchoice
|
||||
|
||||
+config CMDLINE_OVERRIDE
|
||||
+ bool "Use alternative cmdline from device tree"
|
||||
+ help
|
||||
+ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can
|
||||
+ be used, this is not a good option for kernels that are shared across
|
||||
+ devices. This setting enables using "chosen/cmdline-override" as the
|
||||
+ cmdline if it exists in the device tree.
|
||||
+
|
||||
config CMDLINE
|
||||
string "Default kernel command string"
|
||||
default ""
|
||||
--- a/drivers/of/fdt.c
|
||||
+++ b/drivers/of/fdt.c
|
||||
@@ -1189,6 +1189,17 @@ int __init early_init_dt_scan_chosen(cha
|
||||
if (p != NULL && l > 0)
|
||||
strlcat(cmdline, p, min_t(int, strlen(cmdline) + (int)l, COMMAND_LINE_SIZE));
|
||||
|
||||
+ /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different
|
||||
+ * device tree option of chosen/bootargs-override. This is
|
||||
+ * helpful on boards where u-boot sets bootargs, and is unable
|
||||
+ * to be modified.
|
||||
+ */
|
||||
+#ifdef CONFIG_CMDLINE_OVERRIDE
|
||||
+ p = of_get_flat_dt_prop(node, "bootargs-override", &l);
|
||||
+ if (p != NULL && l > 0)
|
||||
+ strlcpy(cmdline, p, min((int)l, COMMAND_LINE_SIZE));
|
||||
+#endif
|
||||
+
|
||||
handle_cmdline:
|
||||
/*
|
||||
* CONFIG_CMDLINE is meant to be a default in case nothing else
|
||||
--- a/arch/arm64/Kconfig
|
||||
+++ b/arch/arm64/Kconfig
|
||||
@@ -2269,6 +2269,14 @@ config CMDLINE_FORCE
|
||||
|
||||
endchoice
|
||||
|
||||
+config CMDLINE_OVERRIDE
|
||||
+ bool "Use alternative cmdline from device tree"
|
||||
+ help
|
||||
+ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can
|
||||
+ be used, this is not a good option for kernels that are shared across
|
||||
+ devices. This setting enables using "chosen/cmdline-override" as the
|
||||
+ cmdline if it exists in the device tree.
|
||||
+
|
||||
config EFI_STUB
|
||||
bool
|
||||
|
||||
|
|
@ -1,34 +0,0 @@
|
|||
---
|
||||
drivers/leds/Kconfig | 10 ++++++++++
|
||||
drivers/leds/Makefile | 1 +
|
||||
2 files changed, 11 insertions(+)
|
||||
|
||||
--- a/drivers/leds/Kconfig
|
||||
+++ b/drivers/leds/Kconfig
|
||||
@@ -901,6 +901,16 @@ source "drivers/leds/flash/Kconfig"
|
||||
comment "RGB LED drivers"
|
||||
source "drivers/leds/rgb/Kconfig"
|
||||
|
||||
+config LEDS_SMARTRG_LED
|
||||
+ tristate "LED support for Adtran SmartRG"
|
||||
+ depends on LEDS_CLASS && I2C && OF
|
||||
+ help
|
||||
+ This option enables support for the Adtran SmartRG platform
|
||||
+ system LED driver.
|
||||
+
|
||||
+ To compile this driver as a module, choose M here: the module
|
||||
+ will be called leds-smartrg-system.
|
||||
+
|
||||
comment "LED Triggers"
|
||||
source "drivers/leds/trigger/Kconfig"
|
||||
|
||||
--- a/drivers/leds/Makefile
|
||||
+++ b/drivers/leds/Makefile
|
||||
@@ -78,6 +78,7 @@ obj-$(CONFIG_LEDS_POWERNV) += leds-powe
|
||||
obj-$(CONFIG_LEDS_PWM) += leds-pwm.o
|
||||
obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o
|
||||
obj-$(CONFIG_LEDS_SC27XX_BLTC) += leds-sc27xx-bltc.o
|
||||
+obj-$(CONFIG_LEDS_SMARTRG_LED) += leds-smartrg-system.o
|
||||
obj-$(CONFIG_LEDS_SUNFIRE) += leds-sunfire.o
|
||||
obj-$(CONFIG_LEDS_SYSCON) += leds-syscon.o
|
||||
obj-$(CONFIG_LEDS_TCA6507) += leds-tca6507.o
|
||||
3
build.sh
3
build.sh
|
|
@ -902,8 +902,7 @@ if [ "$OMR_KERNEL" = "6.10" ]; then
|
|||
rm -f package/kernel/rtl8812au-ct/patches/099-cut-linkid-linux-version-code-conditionals.patch
|
||||
rm -f package/kernel/rtl8812au-ct/patches/100-api_update.patch
|
||||
echo 'CONFIG_KERNEL_GIT_CLONE_URI="https://github.com/multipath-tcp/mptcp_net-next.git"' >> ".config"
|
||||
#echo 'CONFIG_KERNEL_GIT_REF="7377151edddb46e11f664e5709e594551a414fe3"' >> ".config"
|
||||
echo 'CONFIG_KERNEL_GIT_REF="9c4a82ff89bb16e8ca3cc993345c0122b7d4bfa0"' >> ".config"
|
||||
echo 'CONFIG_KERNEL_GIT_REF="30be9e34452a634aab77a15634890e9c7637812a"' >> ".config"
|
||||
fi
|
||||
|
||||
#rm -rf feeds/packages/libs/libwebp
|
||||
|
|
|
|||
1
config
1
config
|
|
@ -268,6 +268,7 @@ CONFIG_OPENSSL_WITH_CHACHA_POLY1305=y
|
|||
# CONFIG_LUCI_CSSTIDY is not set
|
||||
CONFIG_LIBCURL_OPENSSL=y
|
||||
CONFIG_LIBCURL_ZLIB=y
|
||||
CONFIG_LIBCURL_LIBIDN2=y
|
||||
# CONFIG_LIBCURL_MBEDTLS is not set
|
||||
# CONFIG_LIBCURL_WOLFSSL is not set
|
||||
# CONFIG_PACKAGE_libustream-wolfssl is not set
|
||||
|
|
|
|||
Loading…
Reference in a new issue