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Kernel 5.4 RUTX support

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Ycarus (Yannick Chabanois) 2023-08-14 17:47:02 +02:00
parent 839fcf1cab
commit cfce9f52b2
7376 changed files with 3902 additions and 546 deletions
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234
common/package/boot/uboot-ipq40xx/src/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c Normal file
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/*
* (C) Copyright 2005-2009
* BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include "asm/m5282.h"
#include <bmp_layout.h>
#include <status_led.h>
#include <bus_vcxk.h>
/*---------------------------------------------------------------------------*/
DECLARE_GLOBAL_DATA_PTR;
unsigned long display_width;
unsigned long display_height;
/*---------------------------------------------------------------------------*/
int checkboard (void)
{
puts ("Board: MCF-EV1 + MCF-EV23 (BuS Elektronik GmbH & Co. KG)\n");
#if (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
puts (" Boot from Internal FLASH\n");
#endif
return 0;
}
phys_size_t initdram (int board_type)
{
int size, i;
size = 0;
MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6
| MCFSDRAMC_DCR_RC ((15 * CONFIG_SYS_CLK) >> 4);
#ifdef CONFIG_SYS_SDRAM_BASE0
MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE0)
| MCFSDRAMC_DACR_CASL (1)
| MCFSDRAMC_DACR_CBM (3)
| MCFSDRAMC_DACR_PS_16;
MCFSDRAMC_DMR0 = MCFSDRAMC_DMR_BAM_16M | MCFSDRAMC_DMR_V;
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
*(unsigned short *) (CONFIG_SYS_SDRAM_BASE0) = 0xA5A5;
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
for (i = 0; i < 2000; i++)
asm (" nop");
mbar_writeLong (MCFSDRAMC_DACR0,
mbar_readLong (MCFSDRAMC_DACR0) | MCFSDRAMC_DACR_IMRS);
*(unsigned int *) (CONFIG_SYS_SDRAM_BASE0 + 0x220) = 0xA5A5;
size += CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
#endif
#ifdef CONFIG_SYS_SDRAM_BASE1
MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE1)
| MCFSDRAMC_DACR_CASL (1)
| MCFSDRAMC_DACR_CBM (3)
| MCFSDRAMC_DACR_PS_16;
MCFSDRAMC_DMR1 = MCFSDRAMC_DMR_BAM_16M | MCFSDRAMC_DMR_V;
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP;
*(unsigned short *) (CONFIG_SYS_SDRAM_BASE1) = 0xA5A5;
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE;
for (i = 0; i < 2000; i++)
asm (" nop");
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS;
*(unsigned int *) (CONFIG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5;
size += CONFIG_SYS_SDRAM_SIZE1 * 1024 * 1024;
#endif
return size;
}
#if defined(CONFIG_SYS_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
uint *p;
printf("SDRAM test phase 1:\n");
for (p = pstart; p < pend; p++)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("SDRAM test phase 2:\n");
for (p = pstart; p < pend; p++)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p);
return 1;
}
}
printf("SDRAM test passed.\n");
return 0;
}
#endif
int misc_init_r(void)
{
#ifdef CONFIG_HW_WATCHDOG
hw_watchdog_init();
#endif
#ifndef CONFIG_VIDEO
vcxk_init(16, 16);
#endif
return 1;
}
#if defined(CONFIG_VIDEO)
/*
****h* EB+CPU5282-T1/drv_video_init
* FUNCTION
***
*/
int drv_video_init(void)
{
char *s;
unsigned long splash;
printf("Init Video as ");
if ((s = getenv("displaywidth")) != NULL)
display_width = simple_strtoul(s, NULL, 10);
else
display_width = 256;
if ((s = getenv("displayheight")) != NULL)
display_height = simple_strtoul(s, NULL, 10);
else
display_height = 256;
printf("%lu x %lu pixel matrix\n", display_width, display_height);
MCFCCM_CCR &= ~MCFCCM_CCR_SZEN;
MCFGPIO_PEPAR &= ~MCFGPIO_PEPAR_PEPA2;
vcxk_init(display_width, display_height);
#ifdef CONFIG_SPLASH_SCREEN
if ((s = getenv("splashimage")) != NULL) {
debug("use splashimage: %s\n", s);
splash = simple_strtoul(s, NULL, 16);
debug("use splashimage: %x\n", splash);
vcxk_acknowledge_wait();
video_display_bitmap(splash, 0, 0);
}
#endif
return 0;
}
#endif
/*---------------------------------------------------------------------------*/
#ifdef CONFIG_VIDEO
int do_brightness(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int rcode = 0;
ulong side;
ulong bright;
switch (argc) {
case 3:
side = simple_strtoul(argv[1], NULL, 10);
bright = simple_strtoul(argv[2], NULL, 10);
if ((side >= 0) && (side <= 3) &&
(bright >= 0) && (bright <= 1000)) {
vcxk_setbrightness(side, bright);
rcode = 0;
} else {
printf("parameters out of range\n");
printf("Usage:\n%s\n", cmdtp->usage);
rcode = 1;
}
break;
default:
printf("Usage:\n%s\n", cmdtp->usage);
rcode = 1;
break;
}
return rcode;
}
/*---------------------------------------------------------------------------*/
U_BOOT_CMD(
bright, 3, 0, do_brightness,
"sets the display brightness\n",
" <side> <0..1000>\n side: 0/3=both; 1=first; 2=second\n"
);
#endif
/* EOF EB+MCF-EV123.c */

44
common/package/boot/uboot-ipq40xx/src/board/BuS/EB+MCF-EV123/Makefile Normal file
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#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o cfm_flash.o flash.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

212
common/package/boot/uboot-ipq40xx/src/board/BuS/EB+MCF-EV123/cfm_flash.c Normal file
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/*
* Basic Flash Driver for Freescale MCF 5281/5282 internal FLASH
*
* (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/m5282.h>
#include "cfm_flash.h"
#if defined(CONFIG_M5281) || defined(CONFIG_M5282)
#if (CONFIG_SYS_CLK>20000000)
#define CFM_CLK (((long) CONFIG_SYS_CLK / (400000 * 8) + 1) | 0x40)
#else
#define CFM_CLK ((long) CONFIG_SYS_CLK / 400000 + 1)
#endif
#define cmf_backdoor_address(addr) (((addr) & 0x0007FFFF) | 0x04000000 | \
(CONFIG_SYS_MBAR & 0xC0000000))
void cfm_flash_print_info (flash_info_t * info)
{
printf ("Freescale: ");
switch (info->flash_id & FLASH_TYPEMASK) {
case FREESCALE_ID_MCF5281 & FLASH_TYPEMASK:
printf ("MCF5281 internal FLASH\n");
break;
case FREESCALE_ID_MCF5282 & FLASH_TYPEMASK:
printf ("MCF5282 internal FLASH\n");
break;
default:
printf ("Unknown Chip Type\n");
break;
}
}
void cfm_flash_init (flash_info_t * info)
{
int sector;
ulong protection;
MCFCFM_MCR = 0;
MCFCFM_CLKD = CFM_CLK;
debug ("CFM Clock divider: %ld (%d Hz @ %ld Hz)\n",CFM_CLK,\
CONFIG_SYS_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\
CONFIG_SYS_CLK);
MCFCFM_SACC = 0;
MCFCFM_DACC = 0;
if (MCFCFM_SEC & MCFCFM_SEC_KEYEN)
puts("CFM backdoor access is enabled\n");
if (MCFCFM_SEC & MCFCFM_SEC_SECSTAT)
puts("CFM securety is enabled\n");
#ifdef CONFIG_M5281
info->flash_id = (FREESCALE_MANUFACT & FLASH_VENDMASK) |
(FREESCALE_ID_MCF5281 & FLASH_TYPEMASK);
info->size = 256*1024;
info->sector_count = 16;
#else
info->flash_id = (FREESCALE_MANUFACT & FLASH_VENDMASK) |
(FREESCALE_ID_MCF5282 & FLASH_TYPEMASK);
info->size = 512*1024;
info->sector_count = 32;
#endif
protection = MCFCFM_PROT;
for (sector = 0; sector < info->sector_count; sector++)
{
if (sector == 0)
{
info->start[sector] = CONFIG_SYS_INT_FLASH_BASE;
}
else
{
info->start[sector] = info->start[sector-1] + 0x04000;
}
info->protect[sector] = protection & 1;
protection >>= 1;
}
}
int cfm_flash_readycheck(int checkblank)
{
int rc;
unsigned char state;
rc = ERR_OK;
while (!(MCFCFM_USTAT & MCFCFM_USTAT_CCIF));
state = MCFCFM_USTAT;
if (state & MCFCFM_USTAT_ACCERR)
{
debug ("%s(): CFM access error",__FUNCTION__);
rc = ERR_PROG_ERROR;
}
if (state & MCFCFM_USTAT_PVIOL)
{
debug ("%s(): CFM protection violation",__FUNCTION__);
rc = ERR_PROTECTED;
}
if (checkblank)
{
if (!(state & MCFCFM_USTAT_BLANK))
{
debug ("%s(): CFM erras error",__FUNCTION__);
rc = ERR_NOT_ERASED;
}
}
MCFCFM_USTAT = state & 0x34; /* reset state */
return rc;
}
/* Erase 16KiB = 8 2KiB pages */
int cfm_flash_erase_sector (flash_info_t * info, int sector)
{
ulong address;
int page;
int rc;
rc= ERR_OK;
address = cmf_backdoor_address(info->start[sector]);
for (page=0; (page<8) && (rc==ERR_OK); page++)
{
*(volatile __u32*) address = 0;
MCFCFM_CMD = MCFCFM_CMD_PGERS;
MCFCFM_USTAT = MCFCFM_USTAT_CBEIF;
rc = cfm_flash_readycheck(0);
if (rc==ERR_OK)
{
*(volatile __u32*) address = 0;
MCFCFM_CMD = MCFCFM_CMD_PGERSVER;
MCFCFM_USTAT = MCFCFM_USTAT_CBEIF;
rc = cfm_flash_readycheck(1);
}
address += 0x800;
}
return rc;
}
int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
int rc;
ulong dest, data;
rc = ERR_OK;
if (addr & 3)
{
debug ("Byte and Word alignment not supported\n");
rc = ERR_ALIGN;
}
if (cnt & 3)
{
debug ("Byte and Word transfer not supported\n");
rc = ERR_ALIGN;
}
dest = cmf_backdoor_address(addr);
while ((cnt>=4) && (rc == ERR_OK))
{
data = *((volatile u32 *) src);
*(volatile u32*) dest = data;
MCFCFM_CMD = MCFCFM_CMD_PGM;
MCFCFM_USTAT = MCFCFM_USTAT_CBEIF;
rc = cfm_flash_readycheck(0);
if (*(volatile u32*) addr != data) rc = ERR_PROG_ERROR;
src +=4;
dest +=4;
addr +=4;
cnt -=4;
}
return rc;
}
#ifdef CONFIG_SYS_FLASH_PROTECTION
int cfm_flash_protect(flash_info_t * info,long sector,int prot)
{
int rc;
rc= ERR_OK;
if (prot)
{
MCFCFM_PROT |= (1<<sector);
info->protect[sector]=1;
}
else
{
MCFCFM_PROT &= ~(1<<sector);
info->protect[sector]=0;
}
return rc;
}
#endif
#endif

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common/package/boot/uboot-ipq40xx/src/board/BuS/EB+MCF-EV123/cfm_flash.h Normal file
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/*
* Basic Flash Driver for Freescale MCF 5282 internal FLASH
*
* (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CFM_FLASH_H_
#define __CFM_FLASH_H_
#define FREESCALE_MANUFACT 0xFACFFACF
#define FREESCALE_ID_MCF5281 0x5281
#define FREESCALE_ID_MCF5282 0x5282
extern void cfm_flash_print_info (flash_info_t * info);
extern int cfm_flash_erase_sector (flash_info_t * info, int sector);
extern void cfm_flash_init (flash_info_t * info);
extern int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
#ifdef CONFIG_SYS_FLASH_PROTECTION
extern int cfm_flash_protect(flash_info_t * info,long sector,int prot);
#endif
#endif

27
common/package/boot/uboot-ipq40xx/src/board/BuS/EB+MCF-EV123/config.mk Normal file
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#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
ifndef CONFIG_SYS_TEXT_BASE
CONFIG_SYS_TEXT_BASE = 0xFE000000
endif

415
common/package/boot/uboot-ipq40xx/src/board/BuS/EB+MCF-EV123/flash.c Normal file
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/*
* (C) Copyright 2005
* BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
*
* Based On
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include "cfm_flash.h"
#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
#define FLASH_BANK_SIZE 0x200000
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
void flash_print_info (flash_info_t * info)
{
int i;
switch (info->flash_id & FLASH_VENDMASK) {
case (AMD_MANUFACT & FLASH_VENDMASK):
printf ("AMD: ");
switch (info->flash_id & FLASH_TYPEMASK) {
case (AMD_ID_LV160B & FLASH_TYPEMASK):
printf ("AM29LV160B (16Bit)\n");
break;
default:
printf ("Unknown Chip Type\n");
break;
}
break;
case FREESCALE_MANUFACT & FLASH_VENDMASK:
cfm_flash_print_info (info);
break;
default:
printf ("Unknown Vendor ");
break;
}
puts (" Size: ");
if ((info->size >> 20) > 0)
{
printf ("%ld MiB",info->size >> 20);
}
else
{
printf ("%ld KiB",info->size >> 10);
}
printf (" in %d Sectors\n", info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; i++) {
if ((i % 4) == 0) {
printf ("\n ");
}
printf ("%02d: %08lX%s ", i,info->start[i],
info->protect[i] ? " P" : " ");
}
printf ("\n\n");
}
unsigned long flash_init (void)
{
int i, j;
ulong size = 0;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
ulong flashbase = 0;
switch (i)
{
case 1:
flash_info[i].flash_id =
(AMD_MANUFACT & FLASH_VENDMASK) |
(AMD_ID_LV160B & FLASH_TYPEMASK);
flash_info[i].size = FLASH_BANK_SIZE;
flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
flashbase = PHYS_FLASH_1;
for (j = 0; j < flash_info[i].sector_count; j++) {
if (j == 0) {
/* 1st is 16 KiB */
flash_info[i].start[j] = flashbase;
}
if ((j >= 1) && (j <= 2)) {
/* 2nd and 3rd are 8 KiB */
flash_info[i].start[j] =
flashbase + 0x4000 + 0x2000 * (j - 1);
}
if (j == 3) {
/* 4th is 32 KiB */
flash_info[i].start[j] = flashbase + 0x8000;
}
if ((j >= 4) && (j <= 34)) {
/* rest is 256 KiB */
flash_info[i].start[j] =
flashbase + 0x10000 + 0x10000 * (j - 4);
}
}
break;
case 0:
cfm_flash_init (&flash_info[i]);
break;
default:
panic ("configured to many flash banks!\n");
}
size += flash_info[i].size;
}
flash_protect (FLAG_PROTECT_SET,
CONFIG_SYS_FLASH_BASE,
CONFIG_SYS_FLASH_BASE + 0xffff, &flash_info[0]);
return size;
}
#define CMD_READ_ARRAY 0x00F0
#define CMD_UNLOCK1 0x00AA
#define CMD_UNLOCK2 0x0055
#define CMD_ERASE_SETUP 0x0080
#define CMD_ERASE_CONFIRM 0x0030
#define CMD_PROGRAM 0x00A0
#define CMD_UNLOCK_BYPASS 0x0020
#define MEM_FLASH_ADDR1 (*(volatile u16 *)(info->start[0] + (0x00000555<<1)))
#define MEM_FLASH_ADDR2 (*(volatile u16 *)(info->start[0] + (0x000002AA<<1)))
#define BIT_ERASE_DONE 0x0080
#define BIT_RDY_MASK 0x0080
#define BIT_PROGRAM_ERROR 0x0020
#define BIT_TIMEOUT 0x80000000 /* our flag */
#define ERR_READY -1
int amd_flash_erase_sector(flash_info_t * info, int sector)
{
int state;
ulong result;
ulong start;
volatile u16 *addr =
(volatile u16 *) (info->start[sector]);
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
*addr = CMD_ERASE_CONFIRM;
/* wait until flash is ready */
state = 0;
start = get_timer(0);
do {
result = *addr;
/* check timeout */
if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
state = ERR_TIMOUT;
}
if (!state && (result & 0xFFFF) & BIT_ERASE_DONE)
state = ERR_READY;
}
while (!state);
if (state == ERR_READY)
state = ERR_OK;
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
return state;
}
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
int iflag, cflag;
int sector;
int rc;
rc = ERR_OK;
if (info->flash_id == FLASH_UNKNOWN)
{
rc = ERR_UNKNOWN_FLASH_TYPE;
} /* (info->flash_id == FLASH_UNKNOWN) */
if ((s_first < 0) || (s_first > s_last) || s_last >= info->sector_count)
{
rc = ERR_INVAL;
}
cflag = icache_status ();
icache_disable ();
iflag = disable_interrupts ();
for (sector = s_first; (sector <= s_last) && (rc == ERR_OK); sector++) {
if (info->protect[sector])
{
putc('P'); /* protected sector will not erase */
}
else
{
/* erase on unprotected sector */
puts("E\b");
switch (info->flash_id & FLASH_VENDMASK)
{
case (AMD_MANUFACT & FLASH_VENDMASK):
rc = amd_flash_erase_sector(info,sector);
break;
case (FREESCALE_MANUFACT & FLASH_VENDMASK):
rc = cfm_flash_erase_sector(info,sector);
break;
default:
return ERR_UNKNOWN_FLASH_VENDOR;
}
putc('.');
}
}
if (rc!=ERR_OK)
{
printf ("\n ");
flash_perror (rc);
}
else
{
printf (" done\n");
}
udelay (10000); /* allow flash to settle - wait 10 ms */
if (iflag)
enable_interrupts ();
if (cflag)
icache_enable ();
return rc;
}
volatile static int amd_write_word (flash_info_t * info, ulong dest, u16 data)
{
volatile u16 *addr;
ulong result;
int cflag, iflag;
int state;
ulong start;
/*
* Check if Flash is (sufficiently) erased
*/
addr = (volatile u16 *) dest;
result = *addr;
if ((result & data) != data)
return ERR_NOT_ERASED;
/*
* Disable interrupts which might cause a timeout
* here. Remember that our exception vectors are
* at address 0 in the flash, and we don't want a
* (ticker) exception to happen while the flash
* chip is in programming mode.
*/
cflag = icache_status ();
icache_disable ();
iflag = disable_interrupts ();
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
MEM_FLASH_ADDR1 = CMD_PROGRAM;
*addr = data;
/* arm simple, non interrupt dependent timer */
start = get_timer(0);
/* wait until flash is ready */
state = 0;
do {
result = *addr;
/* check timeout */
if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
state = ERR_TIMOUT;
}
if (!state && ((result & BIT_RDY_MASK) == (data & BIT_RDY_MASK)))
state = ERR_READY;
} while (!state);
*addr = CMD_READ_ARRAY;
if (state == ERR_READY)
state = ERR_OK;
if ((*addr != data) && (state != ERR_TIMOUT))
state = ERR_PROG_ERROR;
if (iflag)
enable_interrupts ();
if (cflag)
icache_enable ();
return state;
}
int amd_flash_write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
int rc;
ulong dest;
u16 data;
rc = ERR_OK;
if (addr & 1)
{
debug ("Byte alignment not supported\n");
rc = ERR_ALIGN;
}
if (cnt & 1)
{
debug ("Byte transfer not supported\n");
rc = ERR_ALIGN;
}
dest = addr;
while ((cnt>=2) && (rc == ERR_OK))
{
data = *((volatile u16 *) src);
rc=amd_write_word (info,dest,data);
src +=2;
dest +=2;
cnt -=2;
}
return rc;
}
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
int rc;
switch (info->flash_id & FLASH_VENDMASK)
{
case (AMD_MANUFACT & FLASH_VENDMASK):
rc = amd_flash_write_buff(info,src,addr,cnt);
break;
case (FREESCALE_MANUFACT & FLASH_VENDMASK):
rc = cfm_flash_write_buff(info,src,addr,cnt);
break;
default:
rc = ERR_UNKNOWN_FLASH_VENDOR;
}
return rc;
}
int amd_flash_protect(flash_info_t * info,long sector,int prot)
{
int rc;
rc= ERR_OK;
if (prot)
{
info->protect[sector]=1;
}
else
{
info->protect[sector]=0;
}
return rc;
}
#ifdef CONFIG_SYS_FLASH_PROTECTION
int flash_real_protect(flash_info_t * info,long sector,int prot)
{
int rc;
switch (info->flash_id & FLASH_VENDMASK)
{
case (AMD_MANUFACT & FLASH_VENDMASK):
rc = amd_flash_protect(info,sector,prot);
break;
case (FREESCALE_MANUFACT & FLASH_VENDMASK):
rc = cfm_flash_protect(info,sector,prot);
break;
default:
rc = ERR_UNKNOWN_FLASH_VENDOR;
}
return rc;
}
#endif

96
common/package/boot/uboot-ipq40xx/src/board/BuS/EB+MCF-EV123/u-boot.lds Normal file
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/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(m68k)
SECTIONS
{
.text :
{
arch/m68k/cpu/mcf52x2/start.o (.text*)
*(.text*)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
__got_start = .;
KEEP(*(.got))
__got_end = .;
_GOT2_TABLE_ = .;
KEEP(*(.got2))
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data*)
*(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
_sbss = .;
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
}
__bss_end__ = . ;
PROVIDE (end = .);
}

44
common/package/boot/uboot-ipq40xx/src/board/BuS/eb_cpux9k2/Makefile Normal file
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@ -0,0 +1,44 @@
#
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS := cpux9k2.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

391
common/package/boot/uboot-ipq40xx/src/board/BuS/eb_cpux9k2/cpux9k2.c Normal file
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/*
* (C) Copyright 2008-2009
* BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
* Jens Scharsig <esw@bus-elektronik.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <exports.h>
#include <net.h>
#include <netdev.h>
#include <nand.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_mc.h>
#include <asm/arch/at91_common.h>
#ifdef CONFIG_STATUS_LED
#include <status_led.h>
#endif
#ifdef CONFIG_VIDEO
#include <bus_vcxk.h>
extern unsigned long display_width;
extern unsigned long display_height;
#endif
#ifdef CONFIG_CMD_NAND
void cpux9k2_nand_hw_init(void);
#endif
DECLARE_GLOBAL_DATA_PTR;
/*
* Miscelaneous platform dependent initialisations
*/
int board_init(void)
{
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
/* Enable Ctrlc */
console_init_f();
/* Correct IRDA resistor problem / Set PA23_TXD in Output */
writel(ATMEL_PMX_AA_TXD2, &pio->pioa.oer);
gd->bd->bi_arch_number = MACH_TYPE_EB_CPUX9K2;
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_STATUS_LED
status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
#endif
#ifdef CONFIG_CMD_NAND
cpux9k2_nand_hw_init();
#endif
return 0;
}
int board_early_init_f(void)
{
at91_seriald_hw_init();
return 0;
}
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
uchar mac[8];
uchar tm;
uchar midx;
uchar macn6, macn7;
if (getenv("ethaddr") == NULL) {
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x00,
CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
(uchar *) &mac, sizeof(mac)) != 0) {
puts("Error reading MAC from EEPROM\n");
} else {
tm = 0;
macn6 = 0;
macn7 = 0xFF;
for (midx = 0; midx < 6; midx++) {
if ((mac[midx] != 0) && (mac[midx] != 0xFF))
tm++;
macn6 += mac[midx];
macn7 ^= mac[midx];
}
if ((macn6 != mac[6]) || (macn7 != mac[7]))
tm = 0;
if (tm)
eth_setenv_enetaddr("ethaddr", mac);
else
puts("Error: invalid MAC at EEPROM\n");
}
}
gd->jt[XF_do_reset] = (void *) do_reset;
#ifdef CONFIG_STATUS_LED
status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);
#endif
return 0;
}
#endif
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
udelay(10000);
eth_init(gd->bd);
}
#endif
/*
* DRAM initialisations
*/
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
/*
* Ethernet initialisations
*/
#ifdef CONFIG_DRIVER_AT91EMAC
int board_eth_init(bd_t *bis)
{
int rc = 0;
rc = at91emac_register(bis, (u32) ATMEL_BASE_EMAC);
return rc;
}
#endif
/*
* Disk On Chip (NAND) Millenium initialization.
* The NAND lives in the CS2* space
*/
#if defined(CONFIG_CMD_NAND)
#define MASK_ALE (1 << 22) /* our ALE is AD22 */
#define MASK_CLE (1 << 21) /* our CLE is AD21 */
void cpux9k2_nand_hw_init(void)
{
unsigned long csr;
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_mc_t *mc = (at91_mc_t *) ATMEL_BASE_MC;
/* Setup Smart Media, fitst enable the address range of CS3 */
writel(readl(&mc->ebi.csa) | AT91_EBI_CSA_CS3A, &mc->ebi.csa);
/* RWH = 1 | RWS = 0 | TDF = 1 | NWS = 3 */
csr = AT91_SMC_CSR_RWHOLD(1) | AT91_SMC_CSR_TDF(1) |
AT91_SMC_CSR_NWS(3) |
AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_8 |
AT91_SMC_CSR_WSEN;
writel(csr, &mc->smc.csr[3]);
writel(ATMEL_PMX_CA_SMOE | ATMEL_PMX_CA_SMWE, &pio->pioc.asr);
writel(ATMEL_PMX_CA_BFCK | ATMEL_PMX_CA_SMOE | ATMEL_PMX_CA_SMWE,
&pio->pioc.pdr);
/* Configure PC2 as input (signal Nand READY ) */
writel(ATMEL_PMX_CA_BFAVD, &pio->pioc.per);
writel(ATMEL_PMX_CA_BFAVD, &pio->pioc.odr); /* disable output */
writel(ATMEL_PMX_CA_BFCK, &pio->pioc.codr);
/* PIOC clock enabling */
writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
}
static void board_nand_hwcontrol(struct mtd_info *mtd,
int cmd, unsigned int ctrl)
{
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
struct nand_chip *this = mtd->priv;
ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
if (ctrl & NAND_CTRL_CHANGE) {
IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
if (ctrl & NAND_CLE)
IO_ADDR_W |= MASK_CLE;
if (ctrl & NAND_ALE)
IO_ADDR_W |= MASK_ALE;
if ((ctrl & NAND_NCE))
writel(1, &pio->pioc.codr);
else
writel(1, &pio->pioc.sodr);
this->IO_ADDR_W = (void *) IO_ADDR_W;
}
if (cmd != NAND_CMD_NONE)
writeb(cmd, this->IO_ADDR_W);
}
static int board_nand_dev_ready(struct mtd_info *mtd)
{
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
return ((readl(&pio->pioc.pdsr) & (1 << 2)) != 0);
}
int board_nand_init(struct nand_chip *nand)
{
cpux9k2_nand_hw_init();
nand->ecc.mode = NAND_ECC_SOFT;
nand->cmd_ctrl = board_nand_hwcontrol;
nand->dev_ready = board_nand_dev_ready;
nand->chip_delay = 20;
return 0;
}
#endif
#if defined(CONFIG_VIDEO)
/*
* drv_video_init
* FUNCTION: initialize VCxK device
*/
int drv_video_init(void)
{
#ifdef CONFIG_SPLASH_SCREEN
unsigned long splash;
#endif
char *s;
unsigned long csr;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_mc_t *mc = (at91_mc_t *) ATMEL_BASE_MC;
printf("Init Video as ");
s = getenv("displaywidth");
if (s != NULL)
display_width = simple_strtoul(s, NULL, 10);
else
display_width = 256;
s = getenv("displayheight");
if (s != NULL)
display_height = simple_strtoul(s, NULL, 10);
else
display_height = 256;
printf("%ld x %ld pixel matrix\n", display_width, display_height);
/* RWH = 7 | RWS =7 | TDF = 15 | NWS = 0x7F */
csr = AT91_SMC_CSR_RWHOLD(7) | AT91_SMC_CSR_RWSETUP(7) |
AT91_SMC_CSR_TDF(15) | AT91_SMC_CSR_NWS(127) |
AT91_SMC_CSR_ACSS_STANDARD | AT91_SMC_CSR_DBW_16 |
AT91_SMC_CSR_BAT_16 | AT91_SMC_CSR_WSEN;
writel(csr, &mc->smc.csr[2]);
writel(1 << ATMEL_ID_PIOB, &pmc->pcer);
vcxk_init(display_width, display_height);
#ifdef CONFIG_SPLASH_SCREEN
s = getenv("splashimage");
if (s != NULL) {
splash = simple_strtoul(s, NULL, 16);
printf("use splashimage: %lx\n", splash);
video_display_bitmap(splash, 0, 0);
}
#endif
return 0;
}
#endif
#ifdef CONFIG_SOFT_I2C
void i2c_init_board(void)
{
u32 pin;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
writel(1 << ATMEL_ID_PIOA, &pmc->pcer);
pin = ATMEL_PMX_AA_TWD | ATMEL_PMX_AA_TWCK;
writel(pin, &pio->pioa.idr);
writel(pin, &pio->pioa.pudr);
writel(pin, &pio->pioa.per);
writel(pin, &pio->pioa.oer);
writel(pin, &pio->pioa.sodr);
}
#endif
/*--------------------------------------------------------------------------*/
#ifdef CONFIG_STATUS_LED
void __led_toggle(led_id_t mask)
{
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
if (readl(&pio->piod.odsr) & mask)
writel(mask, &pio->piod.codr);
else
writel(mask, &pio->piod.codr);
}
void __led_init(led_id_t mask, int state)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
writel(1 << ATMEL_ID_PIOD, &pmc->pcer); /* Enable PIOB clock */
/* Disable peripherals on LEDs */
writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.per);
/* Enable pins as outputs */
writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.oer);
/* Turn all LEDs OFF */
writel(STATUS_LED_BIT | STATUS_LED_BIT1, &pio->piod.sodr);
__led_set(mask, state);
}
void __led_set(led_id_t mask, int state)
{
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
if (state == STATUS_LED_ON)
writel(mask, &pio->piod.codr);
else
writel(mask, &pio->piod.sodr);
}
#endif
/*---------------------------------------------------------------------------*/
int do_brightness(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int rcode = 0;
ulong side;
ulong bright;
switch (argc) {
case 3:
side = simple_strtoul(argv[1], NULL, 10);
bright = simple_strtoul(argv[2], NULL, 10);
if ((side >= 0) && (side <= 3) &&
(bright >= 0) && (bright <= 1000)) {
vcxk_setbrightness(side, bright);
rcode = 0;
} else {
printf("parameters out of range\n");
printf("Usage:\n%s\n", cmdtp->usage);
rcode = 1;
}
break;
default:
printf("Usage:\n%s\n", cmdtp->usage);
rcode = 1;
break;
}
return rcode;
}
/*---------------------------------------------------------------------------*/
U_BOOT_CMD(
bright, 3, 0, do_brightness,
"bright - sets the display brightness\n",
" <side> <0..1000>\n side: 0/3=both; 1=first; 2=second\n"
);
/* EOF cpu9k2.c */

48
common/package/boot/uboot-ipq40xx/src/board/BuS/vl_ma2sc/Makefile Normal file
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#
# (C) Copyright 2003-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2009-2012
# Jens Scharsig <esw@bus-elekronik.de>
# BuS Elektronik GmbH & Co. KG
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS += vl_ma2sc.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

551
common/package/boot/uboot-ipq40xx/src/board/BuS/vl_ma2sc/vl_ma2sc.c Normal file
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/*
* (C) Copyright 2009-2012
* Jens Scharsig <esw@bus-elekronik.de>
* BuS Elektronik GmbH & Co. KG
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <common.h>
#include <asm/sizes.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clk.h>
#include <asm/arch/at91_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91sam9263.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91_common.h>
#include <lcd.h>
#include <i2c.h>
#include <atmel_lcdc.h>
#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
#include <net.h>
#endif
#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_CMD_NAND
static void vl_ma2sc_nand_hw_init(void)
{
unsigned long csa;
at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */
at91_set_pio_output(AT91_PIO_PORTA, 12, 1); /* CAN_STB -> H */
at91_set_pio_output(AT91_PIO_PORTA, 11, 1); /* CAN_EN -> H */
/* Enable CS3 */
csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
writel(csa, &matrix->csa[0]);
/* Configure SMC CS3 for NAND/SmartMedia */
writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
&smc->cs[3].setup);
writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
&smc->cs[3].pulse);
writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
&smc->cs[3].cycle);
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
AT91_SMC_MODE_DBW_8 |
AT91_SMC_MODE_TDF_CYCLE(2),
&smc->cs[3].mode);
writel((1 << ATMEL_ID_PIOB) | (1 << ATMEL_ID_PIOCDE),
&pmc->pcer);
/* Configure RDY/BSY */
#ifdef CONFIG_SYS_NAND_READY_PIN
at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
#endif
/* Enable NandFlash */
at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
#ifdef CONFIG_MACB
static void vl_ma2sc_macb_hw_init(void)
{
unsigned long erstl;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC;
/* Enable clock */
writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
/* Need to reset PHY -> 500ms reset */
writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
AT91_RSTC_MR_URSTEN, &rstc->mr);
writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
/* Wait for end hardware reset */
while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
;
/* Restore NRST value */
writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
at91_macb_hw_init();
}
#endif
#ifdef CONFIG_LCD
vidinfo_t panel_info = {
.vl_col = 320,
.vl_row = 240,
.vl_clk = 6500000,
.vl_sync = ATMEL_LCDC_INVDVAL_INVERTED |
ATMEL_LCDC_INVLINE_INVERTED |
ATMEL_LCDC_INVVD_INVERTED |
ATMEL_LCDC_INVFRAME_INVERTED,
.vl_bpix = (ATMEL_LCDC_PIXELSIZE_8 >> 5),
.vl_tft = 1,
.vl_hsync_len = 5, /* Horiz Sync Pulse Width */
.vl_left_margin = 68, /* horiz back porch */
.vl_right_margin = 20, /* horiz front porch */
.vl_vsync_len = 2, /* vert Sync Pulse Width */
.vl_upper_margin = 18, /* vert back porch */
.vl_lower_margin = 4, /* vert front porch */
.mmio = ATMEL_BASE_LCDC,
};
void lcd_enable(void)
{
}
void lcd_disable(void)
{
}
static void vl_ma2sc_lcd_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD0 */
at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD1 */
at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD9 */
at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD26 */
at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD17 */
at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
at91_set_pio_output(AT91_PIO_PORTE, 0, 0); /* LCD QXH */
at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* LCD SHUT */
at91_set_pio_output(AT91_PIO_PORTE, 3, 1); /* LCD TopBottom */
at91_set_pio_output(AT91_PIO_PORTE, 4, 0); /* LCD REV */
at91_set_pio_output(AT91_PIO_PORTE, 5, 1); /* LCD RightLeft */
at91_set_pio_output(AT91_PIO_PORTE, 6, 0); /* LCD Color Mode CM */
at91_set_pio_output(AT91_PIO_PORTE, 7, 0); /* LCD BGR */
at91_set_pio_output(AT91_PIO_PORTB, 9, 0); /* LCD CC */
writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
gd->fb_base = ATMEL_BASE_SRAM0;
}
#endif /* Config LCD */
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
/* Enable clocks for all PIOs */
writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
(1 << ATMEL_ID_PIOCDE),
&pmc->pcer);
at91_seriald_hw_init();
return 0;
}
#endif
int board_init(void)
{
at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
u32 pin;
pin = 0x1F000001;
writel(pin, &pio->pioa.idr);
writel(pin, &pio->pioa.pudr);
writel(pin, &pio->pioa.per);
writel(pin, &pio->pioa.oer);
writel(pin, &pio->pioa.sodr);
writel((1 << 25), &pio->pioa.codr);
pin = 0x1F000100;
writel(pin, &pio->piob.idr);
writel(pin, &pio->piob.pudr);
writel(pin, &pio->piob.per);
writel(pin, &pio->piob.oer);
writel(pin, &pio->piob.codr);
writel((1 << 24), &pio->piob.sodr);
pin = 0x40000000; /* Pullup DRxD enbable */
writel(pin, &pio->pioc.puer);
pin = 0x0000000F; /* HWversion als Input */
writel(pin, &pio->piod.idr);
writel(pin, &pio->piod.puer);
writel(pin, &pio->piod.per);
writel(pin, &pio->piod.odr);
writel(pin, &pio->piod.owdr);
/* Enable Ctrlc */
console_init_f();
gd->bd->bi_arch_number = MACH_TYPE_VL_MA2SC;
/* adress of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
writel(CONFIG_SYS_SMC0_MODE0_VAL, &smc->cs[0].setup);
writel(CONFIG_SYS_SMC0_CYCLE0_VAL, &smc->cs[0].cycle);
writel(CONFIG_SYS_SMC0_PULSE0_VAL, &smc->cs[0].pulse);
writel(CONFIG_SYS_SMC0_SETUP0_VAL, &smc->cs[0].setup);
#ifdef CONFIG_CMD_NAND
vl_ma2sc_nand_hw_init();
#endif
#ifdef CONFIG_MACB
vl_ma2sc_macb_hw_init();
#endif
#ifdef CONFIG_USB_OHCI_NEW
at91_uhp_hw_init();
#endif
#ifdef CONFIG_LCD
vl_ma2sc_lcd_hw_init();
#endif
return 0;
}
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
uchar buffer[8];
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
u32 pin;
buffer[0] = 0x04;
buffer[1] = 0x00;
if (i2c_write(0x68, 0x0E, 1, buffer, 2) != 0)
puts("error reseting rtc clock\n\0");
/* read hardware version */
pin = (readl(&pio->piod.pdsr) & 0x0F) + 0x44;
printf("Board: revision %c\n", pin);
buffer[0] = pin;
buffer[1] = 0;
setenv("revision", (char *) buffer);
pin = 0x40000000; /* Pullup DRxD enbable */
writel(pin, &pio->pioc.puer);
return 0;
}
#endif
int dram_init(void)
{
gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
#ifdef CONFIG_RESET_PHY_R
void reset_phy(void)
{
#ifdef CONFIG_MACB
/*
* Initialize ethernet HW addr prior to starting Linux,
* needed for nfsroot
*/
eth_init(gd->bd);
#endif
}
#endif
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_MACB
rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x01);
#endif
return rc;
}
#ifdef CONFIG_SOFT_I2C
void i2c_init_board(void)
{
u32 pin;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
u8 sda = (1<<4);
u8 scl = (1<<5);
writel(1 << ATMEL_ID_PIOB, &pmc->pcer);
pin = sda | scl;
writel(pin, &pio->piob.idr); /* Disable Interupt */
writel(pin, &pio->piob.pudr);
writel(pin, &pio->piob.per);
writel(pin, &pio->piob.oer);
writel(pin, &pio->piob.sodr);
}
#endif
void watchdog_reset(void)
{
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
u32 pin = 0x1; /* PA0 */
if ((readl(&pio->pioa.odsr) & pin) > 0)
writel(pin, &pio->pioa.codr);
else
writel(pin, &pio->pioa.sodr);
}
void enable_caches(void)
{
#ifndef CONFIG_SYS_DCACHE_OFF
dcache_enable();
#endif
}
/*---------------------------------------------------------------------------*/
int do_ledtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int rcode = 1;
int row;
int col;
u32 pinz;
u32 pins;
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
at91_set_pio_output(AT91_PIO_PORTB, 8, 0); /* LCD DIM */
pins = 0x1F000000;
writel(pins, &pio->pioa.idr);
writel(pins, &pio->pioa.pudr);
writel(pins, &pio->pioa.per);
writel(pins, &pio->pioa.oer);
writel(pins, &pio->pioa.sodr);
pinz = 0x1F000000;
writel(pinz, &pio->piob.idr);
writel(pinz, &pio->piob.pudr);
writel(pinz, &pio->piob.per);
writel(pinz, &pio->piob.oer);
writel(pinz, &pio->piob.sodr);
for (row = 0; row < 5; row++) {
for (col = 0; col < 5; col++) {
writel((0x01000000 << col), &pio->piob.sodr);
writel((0x01000000 << row), &pio->pioa.codr);
printf("LED Test %d x %d\n", row, col);
udelay(1000000);
writel(pinz, &pio->piob.codr);
writel(pins, &pio->pioa.sodr);
}
}
return rcode;
}
void poweroff(void)
{
watchdog_reset();
at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */
udelay(100);
at91_set_pio_output(AT91_PIO_PORTA, 12, 0); /* CAN_STB -> L */
udelay(100);
at91_set_pio_output(AT91_PIO_PORTA, 11, 0); /* CAN_EN -> L */
udelay(100);
while (1)
watchdog_reset();
}
int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int rcode = 1;
poweroff();
return rcode;
}
int do_beep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int i;
u32 freq;
u32 durate;
int rcode = 1;
freq = 1000;
durate = 2;
switch (argc) {
case 3:
durate = simple_strtoul(argv[2], NULL, 10);
case 2:
freq = simple_strtoul(argv[1], NULL, 10);
case 1:
break;
default:
cmd_usage(cmdtp);
rcode = 1;
break;
}
durate = durate * freq;
freq = 500000 / freq;
for (i = 0; i < durate; i++) {
at91_set_pio_output(AT91_PIO_PORTB, 29, 1); /* Sound On*/
udelay(freq);
at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/
udelay(freq);
}
at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/
return rcode;
}
int do_keytest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int rcode = 1;
int row;
u32 col;
u32 pinz;
u32 pins;
at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
writel((1 << ATMEL_ID_PIOA), &pmc->pcer);
pins = 0x001F0000;
writel(pins, &pio->pioa.idr);
writel(pins, &pio->pioa.pudr);
writel(pins, &pio->pioa.per);
writel(pins, &pio->pioa.odr);
pinz = 0x000F0000;
writel(pinz, &pio->piob.idr);
writel(pinz, &pio->piob.pudr);
writel(pinz, &pio->piob.per);
writel(pinz, &pio->piob.oer);
writel(pinz, &pio->piob.codr);
while (1) {
col = 0;
for (row = 0; row < 4; row++) {
writel((0x00010000 << row), &pio->piob.sodr);
udelay(10000);
col <<= 4;
col |= ((readl(&pio->pioa.pdsr) >> 16) & 0xF) ^ 0xF ;
writel(pinz, &pio->piob.codr);
}
printf("Matix: ");
for (row = 0; row < 16; row++) {
printf("%1.1d", col & 1);
col >>= 1;
}
printf(" SP %d\r ",
1 ^ (1 & (readl(&pio->piob.pdsr) >> 20)));
if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0) {
/* SHUTDOWN */
row = 0;
while (row < 1000) {
if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0)
row++;
udelay(100);
}
udelay(100000);
row = 0;
while (row < 1000) {
if ((1 & (readl(&pio->pioa.pdsr) >> 1)) > 0) {
row++;
udelay(1000);
}
}
poweroff();
while (1)
;
}
}
return rcode;
}
/*****************************************************************************/
U_BOOT_CMD(
ledtest, 1, 0, do_ledtest,
"test ledmatrix",
"\n"
);
U_BOOT_CMD(
keytest, 1, 0, do_keytest,
"test keymatix and special keys, poweroff on pressing ON key",
"\n"
);
U_BOOT_CMD(
poweroff, 1, 0, do_poweroff,
"power off",
"\n"
);
U_BOOT_CMD(
beep, 3, 0, do_beep,
"[freq [duration]]",
"freq frequence of beep\nduration duration of beep\n"
);
/*****************************************************************************/