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	Add missing 6.1 kernel config
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					 2 changed files with 2 additions and 40 deletions
				
			
		|  | @ -1,40 +0,0 @@ | |||
| From 0cdf37b755feda3aaceb749750613b5e563e7284 Mon Sep 17 00:00:00 2001 | ||||
| From: Andrew Powers-Holmes <aholmes@omnom.net> | ||||
| Date: Sat, 12 Nov 2022 22:41:26 +1100 | ||||
| Subject: [PATCH] arm64: dts: rockchip: rk356x: Fix PCIe register and | ||||
|  range mappings | ||||
| 
 | ||||
| The register and range mappings for the PCIe controller in Rockchip's | ||||
| RK356x SoCs are incorrect. Replace them with corrected values from the | ||||
| vendor BSP sources, updated to match current DT schema. | ||||
| 
 | ||||
| Tested-by: Ondrej Jirman <megi@xff.cz> | ||||
| Signed-off-by: Andrew Powers-Holmes <aholmes@omnom.net> | ||||
| ---
 | ||||
|  arch/arm64/boot/dts/rockchip/rk3568.dtsi | 14 ++++++++------ | ||||
|  arch/arm64/boot/dts/rockchip/rk356x.dtsi |  7 ++++--- | ||||
|  2 files changed, 12 insertions(+), 9 deletions(-) | ||||
| 
 | ||||
| --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
 | ||||
| +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
 | ||||
| @@ -952,7 +952,7 @@
 | ||||
|  		compatible = "rockchip,rk3568-pcie"; | ||||
|  		reg = <0x3 0xc0000000 0x0 0x00400000>, | ||||
|  		      <0x0 0xfe260000 0x0 0x00010000>, | ||||
| -		      <0x3 0x3f000000 0x0 0x01000000>;
 | ||||
| +		      <0x0 0xf4000000 0x0 0x00100000>;
 | ||||
|  		reg-names = "dbi", "apb", "config"; | ||||
|  		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, | ||||
|  			     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, | ||||
| @@ -982,8 +982,9 @@
 | ||||
|  		phys = <&combphy2 PHY_TYPE_PCIE>; | ||||
|  		phy-names = "pcie-phy"; | ||||
|  		power-domains = <&power RK3568_PD_PIPE>; | ||||
| -		ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000
 | ||||
| -			  0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>;
 | ||||
| +		ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
 | ||||
| +			 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
 | ||||
| +			 <0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
 | ||||
|  		resets = <&cru SRST_PCIE20_POWERUP>; | ||||
|  		reset-names = "pipe"; | ||||
|  		#address-cells = <3>; | ||||
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