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Add kernel 5.15 for RPI4 support
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
e961d478cd
commit
df88a19bbd
638 changed files with 239907 additions and 0 deletions
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@ -0,0 +1,155 @@
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From 4e4edf458c458663de9989d4c101842fbc05c9ae Mon Sep 17 00:00:00 2001
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From: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com>
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Date: Thu, 15 Jul 2021 01:07:30 +0200
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Subject: [PATCH 470/634] drm/vc4: Fix timings for VEC modes
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This commit fixes vertical timings of the VEC (composite output) modes
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to accurately represent the 525-line ("NTSC") and 625-line ("PAL") ITU-R
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standards.
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Previous timings were actually defined as 502 and 601 lines, resulting
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in non-standard 62.69 Hz and 52 Hz signals being generated,
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respectively.
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Changes to vc4_crtc.c have also been made, to make the PixelValve
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vertical timings accurately correspond to the DRM modeline in interlaced
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modes. The resulting VERTA/VERTB register values have been verified
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against the reference values set by the Raspberry Pi firmware.
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Signed-off-by: Mateusz Kwiatkowski <kfyatek+publicgit@gmail.com>
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---
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drivers/gpu/drm/vc4/vc4_crtc.c | 70 +++++++++++++++++++++-------------
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drivers/gpu/drm/vc4/vc4_vec.c | 4 +-
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2 files changed, 45 insertions(+), 29 deletions(-)
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diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
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index e21119f32552..23be68a8ecec 100644
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--- a/drivers/gpu/drm/vc4/vc4_crtc.c
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+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
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@@ -318,8 +318,14 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encode
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bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
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vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
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bool is_dsi1 = vc4_encoder->type == VC4_ENCODER_TYPE_DSI1;
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+ bool is_vec = vc4_encoder->type == VC4_ENCODER_TYPE_VEC;
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u32 format = is_dsi1 ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
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u8 ppc = pv_data->pixels_per_clock;
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+
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+ u16 vert_bp = mode->crtc_vtotal - mode->crtc_vsync_end;
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+ u16 vert_sync = mode->crtc_vsync_end - mode->crtc_vsync_start;
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+ u16 vert_fp = mode->crtc_vsync_start - mode->crtc_vdisplay;
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+
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bool debug_dump_regs = false;
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if (debug_dump_regs) {
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@@ -343,49 +349,59 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encode
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VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc,
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PV_HORZB_HACTIVE));
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- CRTC_WRITE(PV_VERTA,
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- VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
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- interlace,
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- PV_VERTA_VBP) |
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- VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
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- PV_VERTA_VSYNC));
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- CRTC_WRITE(PV_VERTB,
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- VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
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- PV_VERTB_VFP) |
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- VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
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-
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if (interlace) {
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+ bool odd_field_first = false;
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+ u32 field_delay = mode->htotal * pixel_rep / (2 * ppc);
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+ u16 vert_bp_even = vert_bp;
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+ u16 vert_fp_even = vert_fp;
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+
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+ if (is_vec) {
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+ /* VEC (composite output) */
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+ ++field_delay;
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+ if (mode->htotal == 858) {
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+ /* 525-line mode (NTSC or PAL-M) */
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+ odd_field_first = true;
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+ }
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+ }
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+
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+ if (odd_field_first)
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+ ++vert_fp_even;
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+ else
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+ ++vert_bp;
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+
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CRTC_WRITE(PV_VERTA_EVEN,
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- VC4_SET_FIELD(mode->crtc_vtotal -
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- mode->crtc_vsync_end,
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- PV_VERTA_VBP) |
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- VC4_SET_FIELD(mode->crtc_vsync_end -
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- mode->crtc_vsync_start,
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- PV_VERTA_VSYNC));
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+ VC4_SET_FIELD(vert_bp_even, PV_VERTA_VBP) |
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+ VC4_SET_FIELD(vert_sync, PV_VERTA_VSYNC));
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CRTC_WRITE(PV_VERTB_EVEN,
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- VC4_SET_FIELD(mode->crtc_vsync_start -
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- mode->crtc_vdisplay,
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- PV_VERTB_VFP) |
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+ VC4_SET_FIELD(vert_fp_even, PV_VERTB_VFP) |
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VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
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- /* We set up first field even mode for HDMI. VEC's
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- * NTSC mode would want first field odd instead, once
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- * we support it (to do so, set ODD_FIRST and put the
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- * delay in VSYNCD_EVEN instead).
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+ /* We set up first field even mode for HDMI and VEC's PAL.
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+ * For NTSC, we need first field odd.
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*/
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CRTC_WRITE(PV_V_CONTROL,
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PV_VCONTROL_CONTINUOUS |
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(is_dsi ? PV_VCONTROL_DSI : 0) |
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PV_VCONTROL_INTERLACE |
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- VC4_SET_FIELD(mode->htotal * pixel_rep / (2 * ppc),
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- PV_VCONTROL_ODD_DELAY));
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- CRTC_WRITE(PV_VSYNCD_EVEN, 0);
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+ (odd_field_first
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+ ? PV_VCONTROL_ODD_FIRST
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+ : VC4_SET_FIELD(field_delay,
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+ PV_VCONTROL_ODD_DELAY)));
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+ CRTC_WRITE(PV_VSYNCD_EVEN,
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+ (odd_field_first ? field_delay : 0));
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} else {
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CRTC_WRITE(PV_V_CONTROL,
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PV_VCONTROL_CONTINUOUS |
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(is_dsi ? PV_VCONTROL_DSI : 0));
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}
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+ CRTC_WRITE(PV_VERTA,
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+ VC4_SET_FIELD(vert_bp, PV_VERTA_VBP) |
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+ VC4_SET_FIELD(vert_sync, PV_VERTA_VSYNC));
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+ CRTC_WRITE(PV_VERTB,
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+ VC4_SET_FIELD(vert_fp, PV_VERTB_VFP) |
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+ VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
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+
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if (is_dsi)
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CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
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diff --git a/drivers/gpu/drm/vc4/vc4_vec.c b/drivers/gpu/drm/vc4/vc4_vec.c
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index 11fc3d6f66b1..4e2250b8fa23 100644
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--- a/drivers/gpu/drm/vc4/vc4_vec.c
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+++ b/drivers/gpu/drm/vc4/vc4_vec.c
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@@ -256,7 +256,7 @@ static void vc4_vec_ntsc_j_mode_set(struct vc4_vec *vec)
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static const struct drm_display_mode ntsc_mode = {
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DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 13500,
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720, 720 + 14, 720 + 14 + 64, 720 + 14 + 64 + 60, 0,
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- 480, 480 + 3, 480 + 3 + 3, 480 + 3 + 3 + 16, 0,
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+ 480, 480 + 7, 480 + 7 + 6, 525, 0,
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DRM_MODE_FLAG_INTERLACE)
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};
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@@ -278,7 +278,7 @@ static void vc4_vec_pal_m_mode_set(struct vc4_vec *vec)
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static const struct drm_display_mode pal_mode = {
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DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 13500,
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720, 720 + 20, 720 + 20 + 64, 720 + 20 + 64 + 60, 0,
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- 576, 576 + 2, 576 + 2 + 3, 576 + 2 + 3 + 20, 0,
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+ 576, 576 + 4, 576 + 4 + 6, 625, 0,
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DRM_MODE_FLAG_INTERLACE)
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};
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--
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2.33.1
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