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Update uboot-rockchip with support for nanopi R4S 1Gb (#2611)

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Anael Orlinski 2022-10-17 19:07:18 +02:00 committed by GitHub
parent e120659ff7
commit e47b0e22dd
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GPG key ID: 4AEE18F83AFDEB23
10 changed files with 1105 additions and 311 deletions
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9
contributors/anaelorlinski.md Normal file
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@ -0,0 +1,9 @@
2022-10-13
I hereby agree to the terms of the "OpenMPTCProuter Individual Contributor License Agreement", with MD5 checksum bc827a07eb93611d793ddb7c75083c00.
I furthermore declare that I am authorized and able to make this agreement and sign this declaration.
Signed,
Anael Orlinski https://github.com/anaelorlinski

7
root/package/boot/uboot-rockchip/Makefile
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@ -5,10 +5,10 @@
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_VERSION:=2021.04
PKG_VERSION:=2021.07
PKG_RELEASE:=1
PKG_HASH:=0d438b1bb5cceb57a18ea2de4a0d51f7be5b05b98717df05938636e0aadfe11a
PKG_HASH:=312b7eeae44581d1362c3a3f02c28d806647756c82ba8c72241c7cdbe68ba77e
PKG_MAINTAINER:=Tobias Maedel <openwrt@tbspace.de>
@ -52,7 +52,7 @@ define U-Boot/rock-pi-4-rk3399
BUILD_SUBTARGET:=armv8
NAME:=Rock Pi 4
BUILD_DEVICES:= \
radxa_rock-pi-4
radxa_rock-pi-4a
DEPENDS:=+PACKAGE_u-boot-rock-pi-4-rk3399:arm-trusted-firmware-rockchip
PKG_BUILD_DEPENDS:=arm-trusted-firmware-rockchip
ATF:=rk3399_bl31.elf
@ -88,6 +88,7 @@ ifneq ($(OF_PLATDATA),)
$(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-plat.c $(PKG_BUILD_DIR)/tpl/dts/dt-plat.c
$(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-structs-gen.h $(PKG_BUILD_DIR)/include/generated/dt-structs-gen.h
$(CP) $(PKG_BUILD_DIR)/of-platdata/$(OF_PLATDATA)/dt-decl.h $(PKG_BUILD_DIR)/include/generated/dt-decl.h
endif
$(SED) 's#CONFIG_MKIMAGE_DTC_PATH=.*#CONFIG_MKIMAGE_DTC_PATH="$(PKG_BUILD_DIR)/scripts/dtc/dtc"#g' $(PKG_BUILD_DIR)/.config

24
root/package/boot/uboot-rockchip/patches/001-scripts-remove-dependency-on-swig.patch Normal file
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@ -0,0 +1,24 @@
From b137ca16b54c67d76714ea5a0138741959b0dc29 Mon Sep 17 00:00:00 2001
From: David Bauer <mail@david-bauer.net>
Date: Mon, 13 Jul 2020 23:37:37 +0200
Subject: [PATCH] scripts: remove dependency on swig
Don't build the libfdt tool, as it has a dependency on swig (which
OpenWrt does not ship).
This requires more hacks, as of-platdata generation does not work
without it.
Signed-off-by: David Bauer <mail@david-bauer.net>
---
scripts/dtc/Makefile | 2 --
1 file changed, 2 deletions(-)
--- a/scripts/dtc/Makefile
+++ b/scripts/dtc/Makefile
@@ -18,5 +18,3 @@ HOSTCFLAGS_dtc-parser.tab.o := -I$(src)
# dependencies on generated files need to be listed explicitly
$(obj)/dtc-lexer.lex.o: $(obj)/dtc-parser.tab.h
-# Added for U-Boot
-subdir-$(CONFIG_PYLIBFDT) += pylibfdt

14
root/package/boot/uboot-rockchip/patches/002-spl-remove-dtoc-of-pdata-generation.patch
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@ -17,14 +17,12 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -329,10 +329,6 @@ PHONY += dts_dir
dts_dir:
$(shell [ -d $(obj)/dts ] || mkdir -p $(obj)/dts)
-include/generated/dt-structs-gen.h $(u-boot-spl-platdata_c) &: \
- $(obj)/$(SPL_BIN).dtb dts_dir FORCE
@@ -354,8 +354,6 @@ $(platdata-hdr) $(u-boot-spl-platdata_c)
@# of OF_PLATDATA_INST and this might change between builds. Leaving old
@# ones around is confusing and it is possible that switching the
@# setting again will use the old one instead of regenerating it.
- @rm -f $(u-boot-spl-all-platdata_c) $(u-boot-spl-all-platdata)
- $(call if_changed,dtoc)
-
ifdef CONFIG_SAMSUNG
ifdef CONFIG_VAR_SIZE_SPL
VAR_SIZE_PARAM = --vs

290
root/package/boot/uboot-rockchip/patches/102-arm64-rk3399-Add-support-NanoPi-R4s.patch
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@ -1,290 +0,0 @@
From b69b9f3f54732c303939eb748aad97cd4cf60168 Mon Sep 17 00:00:00 2001
From: Xiaobo Tian <peterwillcn@gmail.com>
Date: Sat, 27 Feb 2021 22:39:11 +0800
Subject: [PATCH] arm64: rk3399: Add support NanoPi R4s
NanoPi R4s is SBC base on Rockchip RK3399 hexa-core processor with
dual-Core Cortex-A72 and Mali-T864 GPU with 4GiB(LPDDR4) of RAM, SD card support,
including 2 gigabit ethernet(RTL8211E 1Gbps - RTL8111H 1Gbps) and 2 USB 3.0 port.
port.It also has two GPIO headers which allows further peripherals to be used.
The devicetree file is taken of the rk3399 nanopi4 Linux kernel [1].
[1] https://github.com/torvalds/linux/commit/e7a095908227fb3ccc86d001d9e13c9ae2bef8e6
Signed-off-by: xiaobo <peterwillcn@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi | 16 +++
arch/arm/dts/rk3399-nanopi-r4s.dts | 138 +++++++++++++++++++++
board/rockchip/evb_rk3399/MAINTAINERS | 6 +
configs/nanopi-r4s-rk3399_defconfig | 62 +++++++++
5 files changed, 223 insertions(+)
create mode 100644 arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3399-nanopi-r4s.dts
create mode 100644 configs/nanopi-r4s-rk3399_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index dd4d4efed31..0a139473811 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -132,6 +132,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-nanopi-m4.dtb \
rk3399-nanopi-m4-2gb.dtb \
rk3399-nanopi-neo4.dtb \
+ rk3399-nanopi-r4s.dtb \
rk3399-orangepi.dtb \
rk3399-pinebook-pro.dtb \
rk3399-puma-haikou.dtb \
diff --git a/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi
new file mode 100644
index 00000000000..cd1642527ba
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * RK3399-based FriendlyElec boards device tree source
+ *
+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2018 Collabora Ltd.
+ * Copyright (c) 2019 Arm Ltd.
+ * Copyright (C) 2020 Xiaobo <peterwillcn@gmail.com>
+ */
+
+#include "rk3399-nanopi4-u-boot.dtsi"
+#include "rk3399-sdram-lpddr4-100.dtsi"
diff --git a/arch/arm/dts/rk3399-nanopi-r4s.dts b/arch/arm/dts/rk3399-nanopi-r4s.dts
new file mode 100644
index 00000000000..6f2cf17bf1b
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopi-r4s.dts
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (c) 2018 Collabora Ltd.
+ * Copyright (c) 2019 Arm Ltd.
+ * Copyright (C) 2020 Xiaobo <peterwillcn@gmail.com>
+ */
+
+/dts-v1/;
+#include "rk3399-nanopi4.dtsi"
+
+/ {
+ model = "FriendlyElec NanoPi R4S";
+ compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399";
+
+ aliases {
+ ethernet1 = &r8169;
+ };
+
+ vdd_5v: vdd-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ cooling-levels = <0 12 18 255>;
+ #cooling-cells = <2>;
+ fan-supply = <&vdd_5v>;
+ pwms = <&pwm1 0 50000 0>;
+ };
+};
+
+&cpu_thermal {
+ trips {
+ cpu_warm: cpu_warm {
+ temperature = <55000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_hot: cpu_hot {
+ temperature = <65000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map2 {
+ trip = <&cpu_warm>;
+ cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+ };
+
+ map3 {
+ trip = <&cpu_hot>;
+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
+&emmc_phy {
+ status = "disabled";
+};
+
+&fusb0 {
+ status = "disabled";
+};
+
+&leds {
+ lan_led: led-1 {
+ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
+ label = "nanopi-r4s:green:lan";
+ };
+
+ wan_led: led-2 {
+ gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
+ label = "nanopi-r4s:green:wan";
+ };
+};
+
+&leds_gpio {
+ rockchip,pins =
+ <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>,
+ <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>,
+ <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+};
+
+&pcie0 {
+ max-link-speed = <1>;
+ num-lanes = <1>;
+ vpcie3v3-supply = <&vcc3v3_sys>;
+
+ pcie@0 {
+ reg = <0x00000000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ r8169: pcie@0,0 {
+ reg = <0x000000 0 0 0 0>;
+ local-mac-address = [ 00 00 00 00 00 00 ];
+ };
+ };
+};
+
+&sdhci {
+ status = "disabled";
+};
+
+&sdio0 {
+ status = "disabled";
+};
+
+&sdmmc {
+ host-index-min = <1>;
+};
+
+&u2phy0_host {
+ phy-supply = <&vdd_5v>;
+};
+
+&u2phy1_host {
+ status = "disabled";
+};
+
+&usbdrd_dwc3_0 {
+ dr_mode = "host";
+};
+
+&vcc3v3_sys {
+ vin-supply = <&vcc5v0_sys>;
+};
diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS
index 4c889e06a63..3b9d60eccd4 100644
--- a/board/rockchip/evb_rk3399/MAINTAINERS
+++ b/board/rockchip/evb_rk3399/MAINTAINERS
@@ -55,6 +55,12 @@ S: Maintained
F: configs/nanopi-neo4-rk3399_defconfig
F: arch/arm/dts/rk3399-nanopi-neo4-u-boot.dtsi
+NANOPI-R4S
+M: Xiaobo Tian <peterwillcn@gmail.com>
+S: Maintained
+F: configs/nanopi-r4s-rk3399_defconfig
+F: arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi
+
ORANGEPI-RK3399
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig
new file mode 100644
index 00000000000..0a3c28b0126
--- /dev/null
+++ b/configs/nanopi-r4s-rk3399_defconfig
@@ -0,0 +1,62 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_TARGET_EVB_RK3399=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb"
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
+CONFIG_TPL=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM_RK3399_LPDDR4=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_ERRNO_STR=y

637
root/package/boot/uboot-rockchip/patches/202-rockchip-rk3399-split-nanopi-r4s-out-of-evb_rk3399.patch Normal file
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@ -0,0 +1,637 @@
From 244492a7a5451eca042d3ec7ccff8de6e23dd288 Mon Sep 17 00:00:00 2001
From: hmz007 <hmz007@gmail.com>
Date: Fri, 18 Dec 2020 17:10:35 +0800
Subject: [PATCH 2/4] rockchip: rk3399: split nanopi-r4s out of evb_rk3399
Signed-off-by: hmz007 <hmz007@gmail.com>
---
arch/arm/mach-rockchip/rk3399/Kconfig | 6 +
board/friendlyarm/nanopi4/Kconfig | 15 +++
board/friendlyarm/nanopi4/MAINTAINERS | 6 +
board/friendlyarm/nanopi4/Makefile | 8 ++
board/friendlyarm/nanopi4/README | 122 +++++++++++++++++++
board/friendlyarm/nanopi4/hwrev.c | 149 ++++++++++++++++++++++++
board/friendlyarm/nanopi4/hwrev.h | 27 +++++
board/friendlyarm/nanopi4/nanopi4.c | 148 +++++++++++++++++++++++
configs/nanopi-r4s-4gb-rk3399_defconfig | 4 +-
configs/nanopi-r4s-rk3399_defconfig | 4 +-
drivers/clk/rockchip/clk_rk3399.c | 2 +
include/configs/nanopi4.h | 24 ++++
12 files changed, 511 insertions(+), 4 deletions(-)
create mode 100644 board/friendlyarm/nanopi4/Kconfig
create mode 100644 board/friendlyarm/nanopi4/MAINTAINERS
create mode 100644 board/friendlyarm/nanopi4/Makefile
create mode 100644 board/friendlyarm/nanopi4/README
create mode 100644 board/friendlyarm/nanopi4/hwrev.c
create mode 100644 board/friendlyarm/nanopi4/hwrev.h
create mode 100644 board/friendlyarm/nanopi4/nanopi4.c
create mode 100644 include/configs/nanopi4.h
diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig
index 17628f9171..2a44aae43c 100644
--- a/arch/arm/mach-rockchip/rk3399/Kconfig
+++ b/arch/arm/mach-rockchip/rk3399/Kconfig
@@ -109,6 +109,11 @@ config TARGET_ROC_PC_RK3399
* wide voltage input(5V-15V), dual cell battery
* Wifi/BT accessible via expansion board M.2
+config TARGET_NANOPI4
+ bool "FriendlyElec NanoPi 4 Series"
+ help
+ Support for FriendlyElec boards based on RK3399.
+
endchoice
config ROCKCHIP_BOOT_MODE_REG
@@ -152,6 +157,7 @@ config SYS_BOOTCOUNT_ADDR
endif # BOOTCOUNT_LIMIT
source "board/firefly/roc-pc-rk3399/Kconfig"
+source "board/friendlyarm/nanopi4/Kconfig"
source "board/google/gru/Kconfig"
source "board/pine64/pinebook-pro-rk3399/Kconfig"
source "board/pine64/rockpro64_rk3399/Kconfig"
diff --git a/board/friendlyarm/nanopi4/Kconfig b/board/friendlyarm/nanopi4/Kconfig
new file mode 100644
index 0000000000..f3f9dd7b56
--- /dev/null
+++ b/board/friendlyarm/nanopi4/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_NANOPI4
+
+config SYS_BOARD
+ default "nanopi4"
+
+config SYS_VENDOR
+ default "friendlyarm"
+
+config SYS_CONFIG_NAME
+ default "nanopi4"
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+
+endif
diff --git a/board/friendlyarm/nanopi4/MAINTAINERS b/board/friendlyarm/nanopi4/MAINTAINERS
new file mode 100644
index 0000000000..b4c35701d6
--- /dev/null
+++ b/board/friendlyarm/nanopi4/MAINTAINERS
@@ -0,0 +1,6 @@
+NanoPi 4 Series
+M: <support@friendlyarm.com>
+S: Maintained
+F: board/friendlyarm/nanopi4/
+F: include/configs/nanopi4.h
+F: configs/nanopi4_defconfig
diff --git a/board/friendlyarm/nanopi4/Makefile b/board/friendlyarm/nanopi4/Makefile
new file mode 100644
index 0000000000..33a1466567
--- /dev/null
+++ b/board/friendlyarm/nanopi4/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) Guangzhou FriendlyELEC Computer Tech. Co., Ltd.
+# (http://www.friendlyarm.com)
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += nanopi4.o hwrev.o
diff --git a/board/friendlyarm/nanopi4/README b/board/friendlyarm/nanopi4/README
new file mode 100644
index 0000000000..c6f58203eb
--- /dev/null
+++ b/board/friendlyarm/nanopi4/README
@@ -0,0 +1,122 @@
+Introduction
+============
+
+RK3399 key features we might use in U-Boot:
+* CPU: ARMv8 64bit Big-Little architecture,
+* Big: dual-core Cortex-A72
+* Little: quad-core Cortex-A53
+* IRAM: 200KB
+* DRAM: 4GB-128MB dual-channel
+* eMMC: support eMMC 5.0/5.1, suport HS400, HS200, DDR50
+* SD/MMC: support SD 3.0, MMC 4.51
+* USB: USB3.0 type-C port *2 with dwc3 controller
+* USB2.0 EHCI host port *2
+* Display: RGB/HDMI/DP/MIPI/EDP
+
+evb key features:
+* regulator: pwm regulator for CPU B/L
+* PMIC: rk808
+* debug console: UART2
+
+In order to support Arm Trust Firmware(ATF), we can use either SPL or
+miniloader from rockchip to do:
+* do DRAM init
+* load and verify ATF image
+* load and verify U-Boot image
+
+Here is the step-by-step to boot to U-Boot on rk3399.
+
+Get the Source and prebuild binary
+==================================
+
+ > mkdir ~/evb_rk3399
+ > cd ~/evb_rk3399
+ > git clone https://github.com/ARM-software/arm-trusted-firmware.git
+ > git clone https://github.com/rockchip-linux/rkbin.git
+ > git clone https://github.com/rockchip-linux/rkdeveloptool.git
+
+
+Compile ATF
+===========
+
+ > cd arm-trusted-firmware
+ > make realclean
+ > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31
+
+ Get bl31.elf in this step, copy it to U-Boot root dir:
+ > cp build/rk3399/release/bl31/bl31.elf ../u-boot/
+
+ Or you can get the bl31.elf directly from Rockchip:
+ > cp rkbin/rk33/rk3399_bl31_v1.00.elf ../u-boot/bl31.elf
+
+
+Compile U-Boot
+==============
+
+ > cd ../u-boot
+ > export CROSS_COMPILE=aarch64-linux-gnu-
+ > make evb-rk3399_defconfig
+ for firefly-rk3399, use below instead:
+ > make firefly-rk3399_defconfig
+ > make
+ > make u-boot.itb
+
+ Get spl/u-boot-spl.bin and u-boot.itb in this step.
+
+Compile rkdeveloptool
+=====================
+
+Get rkdeveloptool installed on your Host in this step.
+
+Follow instructions in latest README, example:
+ > cd ../rkdeveloptool
+ > autoreconf -i
+ > ./configure
+ > make
+ > sudo make install
+
+Both origin binaries and Tool are ready now, choose either option 1 or
+option 2 to deploy U-Boot.
+
+Package the image
+=================
+
+Package the image for U-Boot SPL(option 1)
+--------------------------------
+ > cd ..
+ > tools/mkimage -n rk3399 -T rksd -d spl/u-boot-spl.bin idbspl.img
+
+ Get idbspl.img in this step.
+
+Package the image for Rockchip miniloader(option 2)
+------------------------------------------
+ > cd ..
+ > cp arm-trusted-firmware/build/rk3399/release/bl31.elf rkbin/rk33
+ > ./rkbin/tools/trust_merger rkbin/tools/RK3399TRUST.ini
+ > ./rkbin/tools/loaderimage --pack --uboot u-boot/u-boot-dtb.bin uboot.img
+
+ Get trust.img and uboot.img in this step.
+
+Flash the image to eMMC
+=======================
+
+Flash the image with U-Boot SPL(option 1)
+-------------------------------
+Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
+ > rkdeveloptool db rkbin/rk33/rk3399_loader_v1.08.106.bin
+ > rkdeveloptool wl 64 u-boot/idbspl.img
+ > rkdeveloptool wl 0x4000 u-boot/u-boot.itb
+ > rkdeveloptool rd
+
+Flash the image with Rockchip miniloader(option 2)
+----------------------------------------
+Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then:
+ > rkdeveloptool db rkbin/rk33/rk3399_loader_v1.08.106.bin
+ > rkdeveloptool ul rkbin/rk33/rk3399_loader_v1.08.106.bin
+ > rkdeveloptool wl 0x4000 u-boot/uboot.img
+ > rkdeveloptool wl 0x6000 u-boot/trust.img
+ > rkdeveloptool rd
+
+You should be able to get U-Boot log in console/UART2(baurdrate 1500000)
+For more detail, please reference to:
+http://opensource.rock-chips.com/wiki_Boot_option
diff --git a/board/friendlyarm/nanopi4/hwrev.c b/board/friendlyarm/nanopi4/hwrev.c
new file mode 100644
index 0000000000..9199a927ee
--- /dev/null
+++ b/board/friendlyarm/nanopi4/hwrev.c
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <linux/delay.h>
+#include <log.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch-rockchip/gpio.h>
+
+/*
+ * ID info:
+ * ID : Volts : ADC value : Bucket
+ * == ===== ========= ===========
+ * 0 : 0.102V: 58 : 0 - 81
+ * 1 : 0.211V: 120 : 82 - 150
+ * 2 : 0.319V: 181 : 151 - 211
+ * 3 : 0.427V: 242 : 212 - 274
+ * 4 : 0.542V: 307 : 275 - 342
+ * 5 : 0.666V: 378 : 343 - 411
+ * 6 : 0.781V: 444 : 412 - 477
+ * 7 : 0.900V: 511 : 478 - 545
+ * 8 : 1.023V: 581 : 546 - 613
+ * 9 : 1.137V: 646 : 614 - 675
+ * 10 : 1.240V: 704 : 676 - 733
+ * 11 : 1.343V: 763 : 734 - 795
+ * 12 : 1.457V: 828 : 796 - 861
+ * 13 : 1.576V: 895 : 862 - 925
+ * 14 : 1.684V: 956 : 926 - 989
+ * 15 : 1.800V: 1023 : 990 - 1023
+ */
+static const int id_readings[] = {
+ 81, 150, 211, 274, 342, 411, 477, 545,
+ 613, 675, 733, 795, 861, 925, 989, 1023
+};
+
+static int cached_board_id = -1;
+
+#define SARADC_BASE 0xFF100000
+#define SARADC_DATA (SARADC_BASE + 0)
+#define SARADC_CTRL (SARADC_BASE + 8)
+
+static u32 get_saradc_value(int chn)
+{
+ int timeout = 0;
+ u32 adc_value = 0;
+
+ writel(0, SARADC_CTRL);
+ udelay(2);
+
+ writel(0x28 | chn, SARADC_CTRL);
+ udelay(50);
+
+ timeout = 0;
+ do {
+ if (readl(SARADC_CTRL) & 0x40) {
+ adc_value = readl(SARADC_DATA) & 0x3FF;
+ goto stop_adc;
+ }
+
+ udelay(10);
+ } while (timeout++ < 100);
+
+stop_adc:
+ writel(0, SARADC_CTRL);
+
+ return adc_value;
+}
+
+static uint32_t get_adc_index(int chn)
+{
+ int i;
+ int adc_reading;
+
+ if (cached_board_id != -1)
+ return cached_board_id;
+
+ adc_reading = get_saradc_value(chn);
+ for (i = 0; i < ARRAY_SIZE(id_readings); i++) {
+ if (adc_reading <= id_readings[i]) {
+ debug("ADC reading %d, ID %d\n", adc_reading, i);
+ cached_board_id = i;
+ return i;
+ }
+ }
+
+ /* should die for impossible value */
+ return 0;
+}
+
+/*
+ * Board revision list: <GPIO4_D1 | GPIO4_D0>
+ * 0b00 - NanoPC-T4
+ * 0b01 - NanoPi M4
+ *
+ * Extended by ADC_IN4
+ * Group A:
+ * 0x04 - NanoPi NEO4
+ * 0x06 - SOC-RK3399
+ *
+ * Group B:
+ * 0x21 - NanoPi M4 Ver2.0
+ */
+static int pcb_rev = -1;
+
+void bd_hwrev_init(void)
+{
+#define GPIO4_BASE 0xff790000
+ struct rockchip_gpio_regs *regs = (void *)GPIO4_BASE;
+
+#ifdef CONFIG_SPL_BUILD
+ struct udevice *dev;
+
+ if (uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(clk_rk3399), &dev))
+ return;
+#endif
+
+ if (pcb_rev >= 0)
+ return;
+
+ /* D1, D0: input mode */
+ clrbits_le32(&regs->swport_ddr, (0x3 << 24));
+ pcb_rev = (readl(&regs->ext_port) >> 24) & 0x3;
+
+ if (pcb_rev == 0x3) {
+ /* Revision group A: 0x04 ~ 0x13 */
+ pcb_rev = 0x4 + get_adc_index(4);
+
+ } else if (pcb_rev == 0x1) {
+ int idx = get_adc_index(4);
+
+ /* Revision group B: 0x21 ~ 0x2f */
+ if (idx > 0) {
+ pcb_rev = 0x20 + idx;
+ }
+ }
+}
+
+/* To override __weak symbols */
+u32 get_board_rev(void)
+{
+ return pcb_rev;
+}
+
diff --git a/board/friendlyarm/nanopi4/hwrev.h b/board/friendlyarm/nanopi4/hwrev.h
new file mode 100644
index 0000000000..23b3c7a557
--- /dev/null
+++ b/board/friendlyarm/nanopi4/hwrev.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) Guangzhou FriendlyARM Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, you can access it online at
+ * http://www.gnu.org/licenses/gpl-2.0.html.
+ */
+
+#ifndef __BD_HW_REV_H__
+#define __BD_HW_REV_H__
+
+extern void bd_hwrev_config_gpio(void);
+extern void bd_hwrev_init(void);
+extern u32 get_board_rev(void);
+
+#endif /* __BD_HW_REV_H__ */
diff --git a/board/friendlyarm/nanopi4/nanopi4.c b/board/friendlyarm/nanopi4/nanopi4.c
new file mode 100644
index 0000000000..a140370ca2
--- /dev/null
+++ b/board/friendlyarm/nanopi4/nanopi4.c
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <env.h>
+#include <hash.h>
+#include <linux/bitops.h>
+#include <i2c.h>
+#include <init.h>
+#include <net.h>
+#include <netdev.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rk3399.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/misc.h>
+#include <asm/io.h>
+#include <asm/setup.h>
+#include <u-boot/sha256.h>
+
+#ifdef CONFIG_MISC_INIT_R
+static void setup_iodomain(void)
+{
+ struct rk3399_grf_regs *grf =
+ syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ /* BT565 and AUDIO is in 1.8v domain */
+ rk_setreg(&grf->io_vsel, BIT(0) | BIT(1));
+}
+
+static int __maybe_unused mac_read_from_generic_eeprom(u8 *addr)
+{
+ struct udevice *i2c_dev;
+ int ret;
+
+ /* Microchip 24AA02xxx EEPROMs with EUI-48 Node Identity */
+ ret = i2c_get_chip_for_busnum(2, 0x51, 1, &i2c_dev);
+ if (!ret)
+ ret = dm_i2c_read(i2c_dev, 0xfa, addr, 6);
+
+ return ret;
+}
+
+static void setup_macaddr(void)
+{
+#if CONFIG_IS_ENABLED(CMD_NET)
+ int ret;
+ const char *cpuid = env_get("cpuid#");
+ u8 hash[SHA256_SUM_LEN];
+ int size = sizeof(hash);
+ u8 mac_addr[6];
+ int from_eeprom = 0;
+ int lockdown = 0;
+
+#ifndef CONFIG_ENV_IS_NOWHERE
+ lockdown = env_get_yesno("lockdown") == 1;
+#endif
+ if (lockdown && env_get("ethaddr"))
+ return;
+
+ ret = mac_read_from_generic_eeprom(mac_addr);
+ if (!ret && is_valid_ethaddr(mac_addr)) {
+ eth_env_set_enetaddr("ethaddr", mac_addr);
+ from_eeprom = 1;
+ }
+
+ if (!cpuid) {
+ debug("%s: could not retrieve 'cpuid#'\n", __func__);
+ return;
+ }
+
+ ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size);
+ if (ret) {
+ debug("%s: failed to calculate SHA256\n", __func__);
+ return;
+ }
+
+ /* Copy 6 bytes of the hash to base the MAC address on */
+ memcpy(mac_addr, hash, 6);
+
+ /* Make this a valid MAC address and set it */
+ mac_addr[0] &= 0xfe; /* clear multicast bit */
+ mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
+
+ if (from_eeprom) {
+ eth_env_set_enetaddr("eth1addr", mac_addr);
+ } else {
+ eth_env_set_enetaddr("ethaddr", mac_addr);
+
+ if (lockdown && env_get("eth1addr"))
+ return;
+
+ /* Ugly, copy another 4 bytes to generate a similar address */
+ memcpy(mac_addr + 2, hash + 8, 4);
+ if (!memcmp(hash + 2, hash + 8, 4))
+ mac_addr[5] ^= 0xff;
+
+ eth_env_set_enetaddr("eth1addr", mac_addr);
+ }
+#endif
+
+ return;
+}
+
+int misc_init_r(void)
+{
+ const u32 cpuid_offset = 0x7;
+ const u32 cpuid_length = 0x10;
+ u8 cpuid[cpuid_length];
+ int ret;
+
+ setup_iodomain();
+
+ ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
+ if (ret)
+ return ret;
+
+ ret = rockchip_cpuid_set(cpuid, cpuid_length);
+ if (ret)
+ return ret;
+
+ setup_macaddr();
+ bd_hwrev_init();
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ char *serial_string;
+ u64 serial = 0;
+
+ serial_string = env_get("serial#");
+
+ if (serial_string)
+ serial = simple_strtoull(serial_string, NULL, 16);
+
+ serialnr->high = (u32)(serial >> 32);
+ serialnr->low = (u32)(serial & 0xffffffff);
+}
+#endif
diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig
index 034241f209..b67f7c0dc9 100644
--- a/configs/nanopi-r4s-rk3399_defconfig
+++ b/configs/nanopi-r4s-rk3399_defconfig
@@ -4,13 +4,13 @@ CONFIG_SYS_TEXT_BASE=0x00200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x3F8000
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s"
CONFIG_ROCKCHIP_RK3399=y
-CONFIG_TARGET_EVB_RK3399=y
+CONFIG_TARGET_NANOPI4=y
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s"
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb"
-CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_MISC_INIT_R=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_STACK_R=y
CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 22c373a623..38975c0c65 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1351,6 +1351,8 @@ static void rkclk_init(struct rockchip_cru *cru)
pclk_div << PCLK_PERILP1_DIV_CON_SHIFT |
hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
+
+ rk3399_saradc_set_clk(cru, 1000000);
}
#endif
diff --git a/include/configs/nanopi4.h b/include/configs/nanopi4.h
new file mode 100644
index 0000000000..a86d38976a
--- /dev/null
+++ b/include/configs/nanopi4.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) Guangzhou FriendlyELEC Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __CONFIG_NANOPI4_H__
+#define __CONFIG_NANOPI4_H__
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdin=serial,usbkbd\0" \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#include <configs/rk3399_common.h>
+
+#define SDRAM_BANK_SIZE (2UL << 30)
+
+#define CONFIG_SERIAL_TAG
+#define CONFIG_REVISION_TAG
+
+#endif
--
2.25.1

275
root/package/boot/uboot-rockchip/patches/203-ram-rk3399-Add-support-for-multiple-DDR-types.patch Normal file
View file

@ -0,0 +1,275 @@
From 1bc90230df5cd55513268f2f7a43abdbad1161b5 Mon Sep 17 00:00:00 2001
From: hmz007 <hmz007@gmail.com>
Date: Sat, 19 Dec 2020 19:39:14 +0800
Subject: [PATCH 3/4] ram: rk3399: Add support for multiple DDR types
Move rockchip,sdram-params to named subnode to include
multiple sdram parameters, and then read the parameters
(by subnode name, first subnode or current node) before
rk3399_dmc_init().
Signed-off-by: hmz007 <hmz007@gmail.com>
---
arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi | 6 ++-
arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi | 5 +-
arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi | 6 ++-
.../arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi | 3 ++
.../arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi | 3 ++
.../rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi | 3 ++
arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi | 3 ++
drivers/ram/rockchip/sdram_rk3399.c | 49 +++++++++++++++----
8 files changed, 64 insertions(+), 14 deletions(-)
diff --git a/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi b/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi
index 7fae249536..dad5b7fbd4 100644
--- a/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi
+++ b/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi
@@ -4,7 +4,9 @@
*/
&dmc {
- rockchip,sdram-params = <
+ ddr3-1333 {
+ u-boot,dm-pre-reloc;
+ rockchip,sdram-params = <
0x1
0xa
0x3
@@ -1536,5 +1538,5 @@
0x01010000
0x00000000
>;
+ };
};
-
diff --git a/arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi b/arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi
index 23c7c34a9a..238f667a76 100644
--- a/arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi
+++ b/arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi
@@ -4,7 +4,9 @@
*/
&dmc {
- rockchip,sdram-params = <
+ ddr3-1600 {
+ u-boot,dm-pre-reloc;
+ rockchip,sdram-params = <
0x1
0xa
0x3
@@ -1536,4 +1538,5 @@
0x01010000
0x00000000
>;
+ };
};
diff --git a/arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi b/arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi
index ea029ca90a..7f6b95fe42 100644
--- a/arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi
+++ b/arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi
@@ -4,7 +4,9 @@
*/
&dmc {
- rockchip,sdram-params = <
+ ddr3-1866 {
+ u-boot,dm-pre-reloc;
+ rockchip,sdram-params = <
0x1
0xa
0x3
@@ -1536,5 +1538,5 @@
0x01010000
0x00000000
>;
+ };
};
-
diff --git a/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi b/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi
index 7296dbb80e..a83564794e 100644
--- a/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi
+++ b/arch/arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi
@@ -5,6 +5,8 @@
*/
&dmc {
+ lpddr3-2GB-1600 {
+ u-boot,dm-pre-reloc;
rockchip,sdram-params = <
0x1
0xa
@@ -1537,4 +1539,5 @@
0x01010000
0x00000000
>;
+ };
};
diff --git a/arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi b/arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi
index bf429c21e4..537936c6fb 100644
--- a/arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi
+++ b/arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi
@@ -4,6 +4,8 @@
*/
&dmc {
+ lpddr3-4GB-1600 {
+ u-boot,dm-pre-reloc;
rockchip,sdram-params = <
0x2
0xa
@@ -1536,4 +1538,5 @@
0x01010000
0x00000000
>;
+ };
};
diff --git a/arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi b/arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi
index 96f459fd0b..a0acdb5add 100644
--- a/arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi
+++ b/arch/arm/dts/rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi
@@ -4,6 +4,8 @@
*/
&dmc {
+ lpddr3-samsung-4GB-1866 {
+ u-boot,dm-pre-reloc;
rockchip,sdram-params = <
0x2
0xa
@@ -1543,4 +1545,5 @@
0x01010000 /* DENALI_PHY_957_DATA */
0x00000000 /* DENALI_PHY_958_DATA */
>;
+ };
};
diff --git a/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
index f0c478d189..21d212236f 100644
--- a/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
+++ b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
@@ -6,6 +6,8 @@
*/
&dmc {
+ lpddr4-100 {
+ u-boot,dm-pre-reloc;
rockchip,sdram-params = <
0x2
0xa
@@ -1538,4 +1540,5 @@
0x01010000
0x00000000
>;
+ };
};
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 530c8a2f40..db30105989 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1625,7 +1625,6 @@ static void set_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf, u32 stride)
rk_clrsetreg(&pmusgrf->soc_con4, 0x1f << 10, stride << 10);
}
-#if !defined(CONFIG_RAM_RK3399_LPDDR4)
static int data_training_first(struct dram_info *dram, u32 channel, u8 rank,
struct rk3399_sdram_params *params)
{
@@ -1715,8 +1714,8 @@ void modify_param(const struct chan_info *chan,
clrsetbits_le32(&denali_pi_params[76], 0x1 << 24, 0x1 << 24);
clrsetbits_le32(&denali_pi_params[77], 0x1, 0x1);
}
-#else
+#if defined(CONFIG_RAM_RK3399_LPDDR4)
struct rk3399_sdram_params dfs_cfgs_lpddr4[] = {
#include "sdram-rk3399-lpddr4-400.inc"
#include "sdram-rk3399-lpddr4-800.inc"
@@ -3011,20 +3010,40 @@ static int sdram_init(struct dram_info *dram,
return 0;
}
+__weak const char *rk3399_get_ddrtype(void)
+{
+ return NULL;
+}
+
static int rk3399_dmc_of_to_plat(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rockchip_dmc_plat *plat = dev_get_plat(dev);
+ ofnode node = { .np = NULL };
+ const char *name;
int ret;
- ret = dev_read_u32_array(dev, "rockchip,sdram-params",
- (u32 *)&plat->sdram_params,
- sizeof(plat->sdram_params) / sizeof(u32));
+ name = rk3399_get_ddrtype();
+ if (name)
+ node = dev_read_subnode(dev, name);
+ if (!ofnode_valid(node)) {
+ debug("Failed to read subnode %s\n", name);
+ node = dev_read_first_subnode(dev);
+ }
+
+ /* fallback to current node */
+ if (!ofnode_valid(node))
+ node = dev_ofnode(dev);
+
+ ret = ofnode_read_u32_array(node, "rockchip,sdram-params",
+ (u32 *)&plat->sdram_params,
+ sizeof(plat->sdram_params) / sizeof(u32));
if (ret) {
printf("%s: Cannot read rockchip,sdram-params %d\n",
__func__, ret);
return ret;
}
+
ret = regmap_init_mem(dev_ofnode(dev), &plat->map);
if (ret)
printf("%s: regmap failed %d\n", __func__, ret);
@@ -3051,18 +3070,20 @@ static int conv_of_platdata(struct udevice *dev)
#endif
static const struct sdram_rk3399_ops rk3399_ops = {
-#if !defined(CONFIG_RAM_RK3399_LPDDR4)
.data_training_first = data_training_first,
.set_rate_index = switch_to_phy_index1,
.modify_param = modify_param,
.get_phy_index_params = get_phy_index_params,
-#else
+};
+
+#if defined(CONFIG_RAM_RK3399_LPDDR4)
+static const struct sdram_rk3399_ops lpddr4_ops = {
.data_training_first = lpddr4_mr_detect,
.set_rate_index = lpddr4_set_rate,
.modify_param = lpddr4_modify_param,
.get_phy_index_params = lpddr4_get_phy_index_params,
-#endif
};
+#endif
static int rk3399_dmc_init(struct udevice *dev)
{
@@ -3081,7 +3102,17 @@ static int rk3399_dmc_init(struct udevice *dev)
return ret;
#endif
- priv->ops = &rk3399_ops;
+ if (params->base.dramtype == LPDDR4) {
+#if defined(CONFIG_RAM_RK3399_LPDDR4)
+ priv->ops = &lpddr4_ops;
+#else
+ printf("LPDDR4 support is disable\n");
+ return -EINVAL;
+#endif
+ } else {
+ priv->ops = &rk3399_ops;
+ }
+
priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
--
2.25.1

89
root/package/boot/uboot-rockchip/patches/204-board-nanopi4-unify-1GB-4GB-variants-of-R4S.patch Normal file
View file

@ -0,0 +1,89 @@
From 317331b3d7ddcf2a5e7b5a9002ac559627000032 Mon Sep 17 00:00:00 2001
From: hmz007 <hmz007@gmail.com>
Date: Sat, 19 Dec 2020 20:39:29 +0800
Subject: [PATCH 4/4] board: nanopi4: unify 1GB/4GB variants of R4S
Signed-off-by: hmz007 <hmz007@gmail.com>
---
.../arm/dts/rk3399-nanopi-r4s-4gb-u-boot.dtsi | 8 --
arch/arm/dts/rk3399-nanopi-r4s-4gb.dts | 114 ------------------
arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi | 2 +
board/friendlyarm/nanopi4/hwrev.c | 36 ++++++
configs/nanopi-r4s-4gb-rk3399_defconfig | 63 ----------
configs/nanopi-r4s-rk3399_defconfig | 1 +
6 files changed, 39 insertions(+), 185 deletions(-)
delete mode 100644 arch/arm/dts/rk3399-nanopi-r4s-4gb-u-boot.dtsi
delete mode 100644 arch/arm/dts/rk3399-nanopi-r4s-4gb.dts
delete mode 100644 configs/nanopi-r4s-4gb-rk3399_defconfig
diff --git a/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi b/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi
index eb0aca4758..9369a7022a 100644
--- a/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi
@@ -4,4 +4,6 @@
*/
#include "rk3399-nanopi4-u-boot.dtsi"
#include "rk3399-sdram-lpddr4-100.dtsi"
+#include "rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi"
+#include "rk3399-sdram-ddr3-1866.dtsi"
diff --git a/board/friendlyarm/nanopi4/hwrev.c b/board/friendlyarm/nanopi4/hwrev.c
index 9199a927ee..812fcef9c7 100644
--- a/board/friendlyarm/nanopi4/hwrev.c
+++ b/board/friendlyarm/nanopi4/hwrev.c
@@ -101,9 +101,13 @@ static uint32_t get_adc_index(int chn)
* Group A:
* 0x04 - NanoPi NEO4
* 0x06 - SOC-RK3399
+ * 0x07 - SOC-RK3399 V2
+ * 0x09 - NanoPi R4S 1GB
+ * 0x0A - NanoPi R4S 4GB
*
* Group B:
* 0x21 - NanoPi M4 Ver2.0
+ * 0x22 - NanoPi M4B
*/
static int pcb_rev = -1;
@@ -141,6 +145,38 @@ void bd_hwrev_init(void)
}
}
+#ifdef CONFIG_SPL_BUILD
+static struct board_ddrtype {
+ int rev;
+ const char *type;
+} ddrtypes[] = {
+ { 0x00, "lpddr3-samsung-4GB-1866" },
+ { 0x01, "lpddr3-samsung-4GB-1866" },
+ { 0x04, "ddr3-1866" },
+ { 0x06, "ddr3-1866" },
+ { 0x07, "lpddr4-100" },
+ { 0x09, "ddr3-1866" },
+ { 0x0a, "lpddr4-100" },
+ { 0x21, "lpddr4-100" },
+ { 0x22, "ddr3-1866" },
+};
+
+const char *rk3399_get_ddrtype(void) {
+ int i;
+
+ bd_hwrev_init();
+ printf("Board: rev%02x\n", pcb_rev);
+
+ for (i = 0; i < ARRAY_SIZE(ddrtypes); i++) {
+ if (ddrtypes[i].rev == pcb_rev)
+ return ddrtypes[i].type;
+ }
+
+ /* fallback to first subnode (ie, first included dtsi) */
+ return NULL;
+}
+#endif
+
/* To override __weak symbols */
u32 get_board_rev(void)
{
--
2.25.1

23
root/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-decl.h Normal file
View file

@ -0,0 +1,23 @@
/*
* DO NOT MODIFY
*
* Declares externs for all device/uclass instances.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
/* driver declarations - these allow DM_DRIVER_GET() to be used */
extern U_BOOT_DRIVER(rockchip_rk3328_cru);
extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
extern U_BOOT_DRIVER(ns16550_serial);
extern U_BOOT_DRIVER(rockchip_rk3328_grf);
/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
extern UCLASS_DRIVER(clk);
extern UCLASS_DRIVER(mmc);
extern UCLASS_DRIVER(ram);
extern UCLASS_DRIVER(serial);
extern UCLASS_DRIVER(syscon);

48
root/package/boot/uboot-rockchip/src/of-platdata/nanopi-r2s-rk3328/dt-plat.c
View file

@ -12,19 +12,38 @@
#include <dm.h>
#include <dt-structs.h>
/* Node /clock-controller@ff440000 index 0 */
/*
* driver_info declarations, ordered by 'struct driver_info' linker_list idx:
*
* idx driver_info driver
* --- -------------------- --------------------
* 0: clock_controller_at_ff440000 rockchip_rk3328_cru
* 1: dmc rockchip_rk3328_dmc
* 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc
* 3: serial_at_ff130000 ns16550_serial
* 4: syscon_at_ff100000 rockchip_rk3328_grf
* --- -------------------- --------------------
*/
/*
* Node /clock-controller@ff440000 index 0
* driver rockchip_rk3328_cru parent None
*/
static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
.reg = {0xff440000, 0x1000},
.rockchip_grf = 0x3a,
};
U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
.name = "rockchip_rk3328_cru",
.plat = &dtv_clock_controller_at_ff440000,
.plat = &dtv_clock_controller_at_ff440000,
.plat_size = sizeof(dtv_clock_controller_at_ff440000),
.parent_idx = -1,
};
/* Node /dmc index 1 */
/*
* Node /dmc index 1
* driver rockchip_rk3328_dmc parent None
*/
static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
.reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
0xff720000, 0x1000, 0xff798000, 0x1000},
@ -56,12 +75,15 @@ static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
};
U_BOOT_DRVINFO(dmc) = {
.name = "rockchip_rk3328_dmc",
.plat = &dtv_dmc,
.plat = &dtv_dmc,
.plat_size = sizeof(dtv_dmc),
.parent_idx = -1,
};
/* Node /mmc@ff500000 index 2 */
/*
* Node /mmc@ff500000 index 2
* driver rockchip_rk3288_dw_mshc parent None
*/
static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
.bus_width = 0x4,
.cap_sd_highspeed = true,
@ -87,12 +109,15 @@ static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
};
U_BOOT_DRVINFO(mmc_at_ff500000) = {
.name = "rockchip_rk3288_dw_mshc",
.plat = &dtv_mmc_at_ff500000,
.plat = &dtv_mmc_at_ff500000,
.plat_size = sizeof(dtv_mmc_at_ff500000),
.parent_idx = -1,
};
/* Node /serial@ff130000 index 3 */
/*
* Node /serial@ff130000 index 3
* driver ns16550_serial parent None
*/
static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
.clock_frequency = 0x16e3600,
.clocks = {
@ -109,18 +134,21 @@ static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
};
U_BOOT_DRVINFO(serial_at_ff130000) = {
.name = "ns16550_serial",
.plat = &dtv_serial_at_ff130000,
.plat = &dtv_serial_at_ff130000,
.plat_size = sizeof(dtv_serial_at_ff130000),
.parent_idx = -1,
};
/* Node /syscon@ff100000 index 4 */
/*
* Node /syscon@ff100000 index 4
* driver rockchip_rk3328_grf parent None
*/
static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
.reg = {0xff100000, 0x1000},
};
U_BOOT_DRVINFO(syscon_at_ff100000) = {
.name = "rockchip_rk3328_grf",
.plat = &dtv_syscon_at_ff100000,
.plat = &dtv_syscon_at_ff100000,
.plat_size = sizeof(dtv_syscon_at_ff100000),
.parent_idx = -1,
};