mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Add test z8102ax kernel 6.6 support
This commit is contained in:
parent
65865c9314
commit
f70b1a24cc
82 changed files with 10630 additions and 94 deletions
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@ -6824,6 +6824,7 @@ CONFIG_TEXTSEARCH=y
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# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
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# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set
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# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
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# CONFIG_THERMAL_DEFAULT_GOV_BANG_BANG is not set
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# CONFIG_THERMAL_EMULATION is not set
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# CONFIG_THERMAL_GOV_BANG_BANG is not set
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# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
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@ -8126,3 +8127,24 @@ CONFIG_DEBUG_INFO_COMPRESSED_NONE=y
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# CONFIG_TEST_DHRY is not set
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# CONFIG_DEBUG_CGROUP_REF is not set
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# CONFIG_USER_EVENTS is not set
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# CONFIG_CHARGER_RT9467 is not set
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# CONFIG_CHARGER_RT9471 is not set
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# CONFIG_XILINX_WINDOW_WATCHDOG is not set
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# CONFIG_MFD_MAX5970 is not set
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# CONFIG_MFD_TPS65219 is not set
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# CONFIG_REGULATOR_AW37503 is not set
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# CONFIG_REGULATOR_MAX77857 is not set
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# CONFIG_REGULATOR_MAX20411 is not set
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# CONFIG_REGULATOR_RAA215300 is not set
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# CONFIG_REGULATOR_RT4803 is not set
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# CONFIG_REGULATOR_RT5739 is not set
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# CONFIG_REGULATOR_RT6190 is not set
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# CONFIG_REGULATOR_RTQ2208 is not set
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# CONFIG_REGULATOR_TPS6287X is not set
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# CONFIG_LEDS_LM3697 is not set
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# CONFIG_LEDS_GROUP_MULTICOLOR is not set
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# CONFIG_COMMON_CLK_SI521XX is not set
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# CONFIG_COMMON_CLK_VC3 is not set
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# CONFIG_CDX_BUS is not set
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# CONFIG_CRYPTO_SM4_ARM64_CE_CCM is not set
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# CONFIG_CRYPTO_SM4_ARM64_CE_GCM is not set
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@ -1,94 +0,0 @@
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From: Felix Fietkau <nbd@nbd.name>
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Date: Thu, 3 Nov 2022 12:38:49 +0100
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Subject: [PATCH] net: ethernet: mtk_eth_soc: work around issue with sending
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small fragments
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When lots of frames are sent with a number of very small fragments, an
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internal FIFO can overflow, causing the DMA engine to lock up lock up and
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transmit attempts time out.
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Fix this on MT7986 by increasing the reserved FIFO space.
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Fix this on older chips by detecting the presence of small fragments and use
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skb_gso_segment + skb_linearize to deal with them.
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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---
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -1562,12 +1562,28 @@ static void mtk_wake_queue(struct mtk_et
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}
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}
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+static bool mtk_skb_has_small_frag(struct sk_buff *skb)
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+{
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+ int min_size = 16;
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+ int i;
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+
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+ if (skb_headlen(skb) < min_size)
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+ return true;
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+
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+ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
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+ if (skb_frag_size(&skb_shinfo(skb)->frags[i]) < min_size)
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+ return true;
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+
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+ return false;
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+}
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+
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static netdev_tx_t mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
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{
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struct mtk_mac *mac = netdev_priv(dev);
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struct mtk_eth *eth = mac->hw;
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struct mtk_tx_ring *ring = ð->tx_ring;
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struct net_device_stats *stats = &dev->stats;
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+ struct sk_buff *segs, *next;
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bool gso = false;
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int tx_num;
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@@ -1589,6 +1605,18 @@ static netdev_tx_t mtk_start_xmit(struct
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return NETDEV_TX_BUSY;
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}
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+ if (mtk_is_netsys_v1(eth) &&
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+ skb_is_gso(skb) && mtk_skb_has_small_frag(skb)) {
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+ segs = skb_gso_segment(skb, dev->features & ~NETIF_F_ALL_TSO);
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+ if (IS_ERR(segs))
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+ goto drop;
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+
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+ if (segs) {
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+ consume_skb(skb);
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+ skb = segs;
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+ }
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+ }
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+
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/* TSO: fill MSS info in tcp checksum field */
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if (skb_is_gso(skb)) {
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if (skb_cow_head(skb, 0)) {
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@@ -1604,8 +1632,14 @@ static netdev_tx_t mtk_start_xmit(struct
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}
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}
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- if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
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- goto drop;
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+ skb_list_walk_safe(skb, skb, next) {
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+ if ((mtk_is_netsys_v1(eth) &&
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+ mtk_skb_has_small_frag(skb) && skb_linearize(skb)) ||
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+ mtk_tx_map(skb, dev, tx_num, ring, gso) < 0) {
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+ stats->tx_dropped++;
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+ dev_kfree_skb_any(skb);
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+ }
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+ }
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if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
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netif_tx_stop_all_queues(dev);
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -268,7 +268,7 @@
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#define MTK_CHK_DDONE_EN BIT(28)
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#define MTK_DMAD_WR_WDONE BIT(26)
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#define MTK_WCOMP_EN BIT(24)
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-#define MTK_RESV_BUF (0x40 << 16)
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+#define MTK_RESV_BUF (0x80 << 16)
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#define MTK_MUTLI_CNT (0x4 << 12)
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#define MTK_LEAKY_BUCKET_EN BIT(11)
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275
6.6/target/linux/mediatek/dts/mt7981b-zbt-z8102ax.dts
Normal file
275
6.6/target/linux/mediatek/dts/mt7981b-zbt-z8102ax.dts
Normal file
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@ -0,0 +1,275 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include "mt7981.dtsi"
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/ {
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model = "ZBT Z8102AX";
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compatible = "z8102ax", "mediatek,mt7981";
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aliases {
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serial0 = &uart0;
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led-boot = &led_status_red;
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led-failsafe = &led_status_red;
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led-running = &led_status_green;
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led-upgrade = &led_status_green;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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gpio-keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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linux,code = <KEY_RESTART>;
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gpios = <&pio 1 GPIO_ACTIVE_LOW>;
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};
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wps {
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label = "wps";
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linux,code = <KEY_WPS_BUTTON>;
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gpios = <&pio 0 GPIO_ACTIVE_LOW>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led_status_red: red {
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label = "red:status";
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gpios = <&pio 9 GPIO_ACTIVE_LOW>;
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};
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led_status_green: green {
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label = "green:status";
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gpios = <&pio 10 GPIO_ACTIVE_LOW>;
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};
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led_status_blue: blue {
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label = "blue:status";
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gpios = <&pio 11 GPIO_ACTIVE_LOW>;
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};
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led_status_4g: 4g {
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label = "4g:status";
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gpios = <&pio 8 GPIO_ACTIVE_LOW>;
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};
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led_status_4g2: 4g2 {
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label = "4g2:status";
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gpios = <&pio 13 GPIO_ACTIVE_LOW>;
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};
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};
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usb_vbus: regulator-usb-vbus {
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compatible = "regulator-fixed";
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regulator-name = "usb_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&pio 12 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-boot-on;
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};
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};
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ð {
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status = "okay";
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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reg = <0>;
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phy-mode = "2500base-x";
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nvmem-cell-names = "mac-address";
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nvmem-cells = <&macaddr_factory_004>;
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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gmac1: mac@1 {
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compatible = "mediatek,eth-mac";
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reg = <1>;
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phy-mode = "gmii";
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phy-handle = <&int_gbe_phy>;
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};
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};
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&mdio_bus {
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switch: switch@0 {
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compatible = "mediatek,mt7531";
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reg = <31>;
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reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&pio>;
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interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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&spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_flash_pins>;
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status = "okay";
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spi_nand@0 {
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compatible = "spi-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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spi-max-frequency = <52000000>;
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spi-tx-buswidth = <4>;
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spi-rx-buswidth = <4>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "bl2";
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reg = <0x0000000 0x0100000>;
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read-only;
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};
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partition@100000 {
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label = "u-boot-env";
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reg = <0x0100000 0x0080000>;
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};
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factory: partition@180000 {
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label = "Factory";
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reg = <0x0180000 0x0200000>;
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read-only;
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};
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partition@380000 {
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label = "fip";
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reg = <0x0380000 0x0200000>;
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read-only;
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};
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partition@580000 {
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label = "ubi";
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reg = <0x0580000 0x4000000>;
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};
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};
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};
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};
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&switch {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan1";
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nvmem-cell-names = "mac-address";
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nvmem-cells = <&macaddr_factory_004>;
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mac-address-increment = <2>;
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};
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port@1 {
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reg = <1>;
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label = "lan2";
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nvmem-cell-names = "mac-address";
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nvmem-cells = <&macaddr_factory_004>;
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mac-address-increment = <2>;
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};
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port@2 {
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reg = <2>;
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label = "lan3";
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nvmem-cell-names = "mac-address";
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nvmem-cells = <&macaddr_factory_004>;
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mac-address-increment = <2>;
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};
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port@3 {
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reg = <3>;
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label = "lan4";
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nvmem-cell-names = "mac-address";
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nvmem-cells = <&macaddr_factory_004>;
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mac-address-increment = <2>;
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};
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port@6 {
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reg = <6>;
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ethernet = <&gmac0>;
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phy-mode = "2500base-x";
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fixed-link {
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speed = <2500>;
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full-duplex;
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pause;
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};
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};
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};
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};
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&pio {
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spi0_flash_pins: spi0-pins {
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mux {
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function = "spi";
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groups = "spi0", "spi0_wp_hold";
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};
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conf-pu {
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pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
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drive-strength = <8>;
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mediatek,pull-up-adv = <0>; /* bias-disable */
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};
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conf-pd {
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pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
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drive-strength = <8>;
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mediatek,pull-up-adv = <0>; /* bias-disable */
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};
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};
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};
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&uart0 {
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status = "okay";
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};
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&watchdog {
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status = "okay";
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};
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&wifi {
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status = "okay";
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mediatek,mtd-eeprom = <&factory 0x0>;
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};
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&usb_phy {
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status = "okay";
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};
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&xhci {
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vbus-supply = <&usb_vbus>;
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status = "okay";
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};
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&factory {
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compatible = "nvmem-cells";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_factory_004: macaddr@004 {
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reg = <0x004 0x6>;
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};
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};
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@ -0,0 +1,32 @@
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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/gpio/gpio.h>
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/ {
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compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
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fragment@0 {
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target = <&gmac1>;
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__overlay__ {
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phy-mode = "2500base-x";
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phy-handle = <&phy5>;
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};
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};
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fragment@1 {
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target = <&mdio_bus>;
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__overlay__ {
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reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
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reset-delay-us = <600>;
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reset-post-delay-us = <20000>;
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phy5: ethernet-phy@5 {
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reg = <5>;
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compatible = "ethernet-phy-ieee802.3-c45";
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phy-mode = "2500base-x";
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};
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};
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};
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};
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@ -0,0 +1,33 @@
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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/gpio/gpio.h>
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/ {
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compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
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fragment@0 {
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target = <&sw_p5>;
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__overlay__ {
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phy-mode = "2500base-x";
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phy-handle = <&phy5>;
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status = "okay";
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};
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};
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fragment@1 {
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target = <&mdio_bus>;
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__overlay__ {
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reset-gpios = <&pio 14 GPIO_ACTIVE_LOW>;
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reset-delay-us = <600>;
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reset-post-delay-us = <20000>;
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phy5: ethernet-phy@5 {
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reg = <5>;
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compatible = "ethernet-phy-ieee802.3-c45";
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phy-mode = "2500base-x";
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};
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};
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};
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};
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@ -0,0 +1,66 @@
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/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
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/dts-v1/;
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/plugin/;
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/ {
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compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
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fragment@0 {
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target = <&spi0>;
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__overlay__ {
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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spi_nand: spi_nand@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-nand";
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reg = <1>;
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spi-max-frequency = <10000000>;
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spi-tx-bus-width = <4>;
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||||
spi-rx-bus-width = <4>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "BL2";
|
||||
reg = <0x00000 0x0100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x0100000 0x0080000>;
|
||||
};
|
||||
|
||||
factory: partition@180000 {
|
||||
label = "Factory";
|
||||
reg = <0x180000 0x0200000>;
|
||||
};
|
||||
|
||||
partition@380000 {
|
||||
label = "FIP";
|
||||
reg = <0x380000 0x0200000>;
|
||||
};
|
||||
|
||||
partition@580000 {
|
||||
label = "ubi";
|
||||
reg = <0x580000 0x4000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@1 {
|
||||
target = <&wifi>;
|
||||
__overlay__ {
|
||||
mediatek,mtd-eeprom = <&factory 0x0>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,188 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2022 MediaTek Inc.
|
||||
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "mt7981.dtsi"
|
||||
|
||||
/ {
|
||||
model = "MediaTek MT7981 RFB";
|
||||
compatible = "mediatek,mt7981-rfb", "mediatek,mt7981";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0 0x40000000 0 0x20000000>;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator-3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_5v: regulator-5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-5V";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
reset {
|
||||
label = "reset";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&pio 1 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
wps {
|
||||
label = "wps";
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ð {
|
||||
status = "okay";
|
||||
|
||||
gmac0: mac@0 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <0>;
|
||||
phy-mode = "2500base-x";
|
||||
|
||||
fixed-link {
|
||||
speed = <2500>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
|
||||
gmac1: mac@1 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <1>;
|
||||
phy-mode = "gmii";
|
||||
phy-handle = <&int_gbe_phy>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio_bus {
|
||||
switch: switch@1f {
|
||||
compatible = "mediatek,mt7531";
|
||||
reg = <31>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&pio>;
|
||||
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&crypto {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pio {
|
||||
spi0_flash_pins: spi0-pins {
|
||||
mux {
|
||||
function = "spi";
|
||||
groups = "spi0", "spi0_wp_hold";
|
||||
};
|
||||
conf-pu {
|
||||
pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
|
||||
drive-strength = <MTK_DRIVE_8mA>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
|
||||
};
|
||||
conf-pd {
|
||||
pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
|
||||
drive-strength = <MTK_DRIVE_8mA>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_flash_pins>;
|
||||
cs-gpios = <0>, <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&switch {
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
sw_p5: port@5 {
|
||||
reg = <5>;
|
||||
label = "lan5";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
port@6 {
|
||||
reg = <6>;
|
||||
ethernet = <&gmac0>;
|
||||
phy-mode = "2500base-x";
|
||||
|
||||
fixed-link {
|
||||
speed = <2500>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&xhci {
|
||||
vusb33-supply = <®_3p3v>;
|
||||
vbus-supply = <®_5v>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog {
|
||||
status = "okay";
|
||||
};
|
|
@ -0,0 +1,808 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2020 MediaTek Inc.
|
||||
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||
* Author: Jianhui Zhao <zhaojh329@gmail.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/clock/mediatek,mt7981-clk.h>
|
||||
#include <dt-bindings/reset/mt7986-resets.h>
|
||||
#include <dt-bindings/pinctrl/mt65xx.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/input/linux-event-codes.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/mux/mux.h>
|
||||
|
||||
/ {
|
||||
compatible = "mediatek,mt7981";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
enable-method = "psci";
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
enable-method = "psci";
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm: pwm@10048000 {
|
||||
compatible = "mediatek,mt7981-pwm";
|
||||
reg = <0 0x10048000 0 0x1000>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&infracfg CLK_INFRA_PWM_STA>,
|
||||
<&infracfg CLK_INFRA_PWM_HCK>,
|
||||
<&infracfg CLK_INFRA_PWM1_CK>,
|
||||
<&infracfg CLK_INFRA_PWM2_CK>,
|
||||
<&infracfg CLK_INFRA_PWM3_CK>;
|
||||
clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
|
||||
};
|
||||
|
||||
fan: pwm-fan {
|
||||
compatible = "pwm-fan";
|
||||
/* cooling level (0, 1, 2, 3) : (0% duty, 50% duty, 75% duty, 100% duty) */
|
||||
cooling-levels = <0 128 192 255>;
|
||||
#cooling-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu_thermal: cpu-thermal {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&thermal 0>;
|
||||
trips {
|
||||
cpu_trip_crit: crit {
|
||||
temperature = <125000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
|
||||
cpu_trip_hot: hot {
|
||||
temperature = <120000>;
|
||||
hysteresis = <2000>;
|
||||
type = "hot";
|
||||
};
|
||||
|
||||
cpu_trip_active_high: active-high {
|
||||
temperature = <115000>;
|
||||
hysteresis = <2000>;
|
||||
type = "active";
|
||||
};
|
||||
|
||||
cpu_trip_active_med: active-med {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "active";
|
||||
};
|
||||
|
||||
cpu_trip_active_low: active-low {
|
||||
temperature = <60000>;
|
||||
hysteresis = <2000>;
|
||||
type = "active";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
cpu-active-high {
|
||||
/* active: set fan to cooling level 3 */
|
||||
cooling-device = <&fan 3 3>;
|
||||
trip = <&cpu_trip_active_high>;
|
||||
};
|
||||
|
||||
cpu-active-med {
|
||||
/* active: set fan to cooling level 2 */
|
||||
cooling-device = <&fan 2 2>;
|
||||
trip = <&cpu_trip_active_med>;
|
||||
};
|
||||
|
||||
cpu-active-low {
|
||||
/* passive: set fan to cooling level 1 */
|
||||
cooling-device = <&fan 1 1>;
|
||||
trip = <&cpu_trip_active_low>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal: thermal@1100c800 {
|
||||
#thermal-sensor-cells = <1>;
|
||||
compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
|
||||
reg = <0 0x1100c800 0 0x800>;
|
||||
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&infracfg CLK_INFRA_THERM_CK>,
|
||||
<&infracfg CLK_INFRA_ADC_26M_CK>;
|
||||
clock-names = "therm", "auxadc";
|
||||
mediatek,auxadc = <&auxadc>;
|
||||
mediatek,apmixedsys = <&apmixedsys>;
|
||||
nvmem-cells = <&thermal_calibration>;
|
||||
nvmem-cell-names = "calibration-data";
|
||||
};
|
||||
|
||||
auxadc: adc@1100d000 {
|
||||
compatible = "mediatek,mt7981-auxadc",
|
||||
"mediatek,mt7986-auxadc",
|
||||
"mediatek,mt7622-auxadc";
|
||||
reg = <0 0x1100d000 0 0x1000>;
|
||||
clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
|
||||
<&infracfg CLK_INFRA_ADC_FRC_CK>;
|
||||
clock-names = "main", "32k";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
||||
wdma: wdma@15104800 {
|
||||
compatible = "mediatek,wed-wdma";
|
||||
reg = <0 0x15104800 0 0x400>,
|
||||
<0 0x15104c00 0 0x400>;
|
||||
};
|
||||
|
||||
ap2woccif: ap2woccif@151a5000 {
|
||||
compatible = "mediatek,ap2woccif";
|
||||
reg = <0 0x151a5000 0 0x1000>,
|
||||
<0 0x151ad000 0 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
/* 64 KiB reserved for ramoops/pstore */
|
||||
ramoops@42ff0000 {
|
||||
compatible = "ramoops";
|
||||
reg = <0 0x42ff0000 0 0x10000>;
|
||||
record-size = <0x1000>;
|
||||
};
|
||||
|
||||
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
|
||||
secmon_reserved: secmon@43000000 {
|
||||
reg = <0 0x43000000 0 0x30000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wmcpu_emi: wmcpu-reserved@47c80000 {
|
||||
reg = <0 0x47c80000 0 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wo_emi0: wo-emi@47d80000 {
|
||||
reg = <0 0x47d80000 0 0x40000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wo_data: wo-data@47dc0000 {
|
||||
reg = <0 0x47dc0000 0 0x240000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
trng {
|
||||
compatible = "mediatek,mt7981-rng";
|
||||
};
|
||||
|
||||
clk40m: oscillator@0 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <40000000>;
|
||||
clock-output-names = "clkxtal";
|
||||
};
|
||||
|
||||
infracfg: infracfg@10001000 {
|
||||
compatible = "mediatek,mt7981-infracfg", "syscon";
|
||||
reg = <0 0x10001000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
topckgen: topckgen@1001B000 {
|
||||
compatible = "mediatek,mt7981-topckgen", "syscon";
|
||||
reg = <0 0x1001B000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
apmixedsys: apmixedsys@1001E000 {
|
||||
compatible = "mediatek,mt7981-apmixedsys", "mediatek,mt7986-apmixedsys", "syscon";
|
||||
reg = <0 0x1001E000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupt-parent = <&gic>;
|
||||
clock-frequency = <13000000>;
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
};
|
||||
|
||||
watchdog: watchdog@1001c000 {
|
||||
compatible = "mediatek,mt7986-wdt",
|
||||
"mediatek,mt6589-wdt";
|
||||
reg = <0 0x1001c000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#reset-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@c000000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupt-controller;
|
||||
reg = <0 0x0c000000 0 0x40000>, /* GICD */
|
||||
<0 0x0c080000 0 0x200000>; /* GICR */
|
||||
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
uart0: serial@11002000 {
|
||||
compatible = "mediatek,mt6577-uart";
|
||||
reg = <0 0x11002000 0 0x400>;
|
||||
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&infracfg CLK_INFRA_UART0_SEL>,
|
||||
<&infracfg CLK_INFRA_UART0_CK>;
|
||||
clock-names = "baud", "bus";
|
||||
assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
|
||||
<&infracfg CLK_INFRA_UART0_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
|
||||
<&topckgen CLK_TOP_UART_SEL>;
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@11003000 {
|
||||
compatible = "mediatek,mt6577-uart";
|
||||
reg = <0 0x11003000 0 0x400>;
|
||||
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&infracfg CLK_INFRA_UART1_SEL>,
|
||||
<&infracfg CLK_INFRA_UART1_CK>;
|
||||
clock-names = "baud", "bus";
|
||||
assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
|
||||
<&infracfg CLK_INFRA_UART1_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
|
||||
<&topckgen CLK_TOP_UART_SEL>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@11004000 {
|
||||
compatible = "mediatek,mt6577-uart";
|
||||
reg = <0 0x11004000 0 0x400>;
|
||||
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&infracfg CLK_INFRA_UART2_SEL>,
|
||||
<&infracfg CLK_INFRA_UART2_CK>;
|
||||
clock-names = "baud", "bus";
|
||||
assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
|
||||
<&infracfg CLK_INFRA_UART2_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_CB_CKSQ_40M>,
|
||||
<&topckgen CLK_TOP_UART_SEL>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@11007000 {
|
||||
compatible = "mediatek,mt7981-i2c";
|
||||
reg = <0 0x11007000 0 0x1000>,
|
||||
<0 0x10217080 0 0x80>;
|
||||
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-div = <1>;
|
||||
clocks = <&infracfg CLK_INFRA_I2C0_CK>,
|
||||
<&infracfg CLK_INFRA_AP_DMA_CK>,
|
||||
<&infracfg CLK_INFRA_I2C_MCK_CK>,
|
||||
<&infracfg CLK_INFRA_I2C_PCK_CK>;
|
||||
clock-names = "main", "dma", "arb", "pmic";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie: pcie@11280000 {
|
||||
compatible = "mediatek,mt7981-pcie",
|
||||
"mediatek,mt7986-pcie";
|
||||
device_type = "pci";
|
||||
reg = <0 0x11280000 0 0x4000>;
|
||||
reg-names = "pcie-mac";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x82000000 0 0x20000000
|
||||
0x0 0x20000000 0 0x10000000>;
|
||||
status = "disabled";
|
||||
|
||||
clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
|
||||
<&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
|
||||
<&infracfg CLK_INFRA_IPCIER_CK>,
|
||||
<&infracfg CLK_INFRA_IPCIEB_CK>;
|
||||
|
||||
phys = <&u3port0 PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc 0>,
|
||||
<0 0 0 2 &pcie_intc 1>,
|
||||
<0 0 0 3 &pcie_intc 2>,
|
||||
<0 0 0 4 &pcie_intc 3>;
|
||||
pcie_intc: interrupt-controller {
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
crypto: crypto@10320000 {
|
||||
compatible = "inside-secure,safexcel-eip97";
|
||||
reg = <0 0x10320000 0 0x40000>;
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ring0", "ring1", "ring2", "ring3";
|
||||
clocks = <&topckgen CLK_TOP_EIP97B>;
|
||||
clock-names = "top_eip97_ck";
|
||||
assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
|
||||
};
|
||||
|
||||
pio: pinctrl@11d00000 {
|
||||
compatible = "mediatek,mt7981-pinctrl";
|
||||
reg = <0 0x11d00000 0 0x1000>,
|
||||
<0 0x11c00000 0 0x1000>,
|
||||
<0 0x11c10000 0 0x1000>,
|
||||
<0 0x11d20000 0 0x1000>,
|
||||
<0 0x11e00000 0 0x1000>,
|
||||
<0 0x11e20000 0 0x1000>,
|
||||
<0 0x11f00000 0 0x1000>,
|
||||
<0 0x11f10000 0 0x1000>,
|
||||
<0 0x1000b000 0 0x1000>;
|
||||
reg-names = "gpio", "iocfg_rt", "iocfg_rm",
|
||||
"iocfg_rb", "iocfg_lb", "iocfg_bl",
|
||||
"iocfg_tm", "iocfg_tl", "eint";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pio 0 0 56>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&gic>;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
mdio_pins: mdc-mdio-pins {
|
||||
mux {
|
||||
function = "eth";
|
||||
groups = "smi_mdc_mdio";
|
||||
};
|
||||
};
|
||||
|
||||
uart0_pins: uart0-pins {
|
||||
mux {
|
||||
function = "uart";
|
||||
groups = "uart0";
|
||||
};
|
||||
};
|
||||
|
||||
wifi_dbdc_pins: wifi-dbdc-pins {
|
||||
mux {
|
||||
function = "eth";
|
||||
groups = "wf0_mode1";
|
||||
};
|
||||
conf {
|
||||
pins = "WF_HB1", "WF_HB2", "WF_HB3", "WF_HB4",
|
||||
"WF_HB0", "WF_HB0_B", "WF_HB5", "WF_HB6",
|
||||
"WF_HB7", "WF_HB8", "WF_HB9", "WF_HB10",
|
||||
"WF_TOP_CLK", "WF_TOP_DATA", "WF_XO_REQ",
|
||||
"WF_CBA_RESETB", "WF_DIG_RESETB";
|
||||
drive-strength = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
gbe_led0_pins: gbe-led0-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "gbe_led0";
|
||||
};
|
||||
};
|
||||
|
||||
gbe_led1_pins: gbe-led1-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "gbe_led1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ethsys: syscon@15000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "mediatek,mt7981-ethsys",
|
||||
"mediatek,mt7986-ethsys",
|
||||
"syscon";
|
||||
reg = <0 0x15000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
wed: wed@15010000 {
|
||||
compatible = "mediatek,mt7981-wed",
|
||||
"mediatek,mt7986-wed",
|
||||
"syscon";
|
||||
reg = <0 0x15010000 0 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
|
||||
memory-region = <&wo_emi0>, <&wo_data>;
|
||||
memory-region-names = "wo-emi", "wo-data";
|
||||
mediatek,wo-ccif = <&wo_ccif0>;
|
||||
mediatek,wo-ilm = <&wo_ilm0>;
|
||||
mediatek,wo-dlm = <&wo_dlm0>;
|
||||
mediatek,wo-cpuboot = <&wo_cpuboot>;
|
||||
};
|
||||
|
||||
eth: ethernet@15100000 {
|
||||
compatible = "mediatek,mt7981-eth";
|
||||
reg = <0 0x15100000 0 0x80000>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <ðsys CLK_ETH_FE_EN>,
|
||||
<ðsys CLK_ETH_GP2_EN>,
|
||||
<ðsys CLK_ETH_GP1_EN>,
|
||||
<ðsys CLK_ETH_WOCPU0_EN>,
|
||||
<&sgmiisys0 CLK_SGM0_TX_EN>,
|
||||
<&sgmiisys0 CLK_SGM0_RX_EN>,
|
||||
<&sgmiisys0 CLK_SGM0_CK0_EN>,
|
||||
<&sgmiisys0 CLK_SGM0_CDR_CK0_EN>,
|
||||
<&sgmiisys1 CLK_SGM1_TX_EN>,
|
||||
<&sgmiisys1 CLK_SGM1_RX_EN>,
|
||||
<&sgmiisys1 CLK_SGM1_CK1_EN>,
|
||||
<&sgmiisys1 CLK_SGM1_CDR_CK1_EN>,
|
||||
<&topckgen CLK_TOP_SGM_REG>,
|
||||
<&topckgen CLK_TOP_NETSYS_SEL>,
|
||||
<&topckgen CLK_TOP_NETSYS_500M_SEL>;
|
||||
clock-names = "fe", "gp2", "gp1", "wocpu0",
|
||||
"sgmii_tx250m", "sgmii_rx250m",
|
||||
"sgmii_cdr_ref", "sgmii_cdr_fb",
|
||||
"sgmii2_tx250m", "sgmii2_rx250m",
|
||||
"sgmii2_cdr_ref", "sgmii2_cdr_fb",
|
||||
"sgmii_ck", "netsys0", "netsys1";
|
||||
assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
|
||||
<&topckgen CLK_TOP_SGM_325M_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_CB_NET2_800M>,
|
||||
<&topckgen CLK_TOP_CB_SGM_325M>;
|
||||
mediatek,ethsys = <ðsys>;
|
||||
mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
|
||||
mediatek,infracfg = <&topmisc>;
|
||||
mediatek,wed = <&wed>;
|
||||
#reset-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
mdio_bus: mdio-bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
int_gbe_phy: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
phy-mode = "gmii";
|
||||
phy-is-integrated;
|
||||
nvmem-cells = <&phy_calibration>;
|
||||
nvmem-cell-names = "phy-cal-data";
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
int_gbe_phy_led0: int-gbe-phy-led0@0 {
|
||||
reg = <0>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
int_gbe_phy_led1: int-gbe-phy-led1@1 {
|
||||
reg = <1>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
wo_dlm0: syscon@151e8000 {
|
||||
compatible = "mediatek,mt7986-wo-dlm", "syscon";
|
||||
reg = <0 0x151e8000 0 0x2000>;
|
||||
};
|
||||
|
||||
wo_ilm0: syscon@151e0000 {
|
||||
compatible = "mediatek,mt7986-wo-ilm", "syscon";
|
||||
reg = <0 0x151e0000 0 0x8000>;
|
||||
};
|
||||
|
||||
wo_cpuboot: syscon@15194000 {
|
||||
compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
|
||||
reg = <0 0x15194000 0 0x1000>;
|
||||
};
|
||||
|
||||
wo_ccif0: syscon@151a5000 {
|
||||
compatible = "mediatek,mt7986-wo-ccif", "syscon";
|
||||
reg = <0 0x151a5000 0 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sgmiisys0: syscon@10060000 {
|
||||
compatible = "mediatek,mt7981-sgmiisys_0", "mediatek,mt7986-sgmiisys_0", "syscon";
|
||||
reg = <0 0x10060000 0 0x1000>;
|
||||
mediatek,pnswap;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
sgmiisys1: syscon@10070000 {
|
||||
compatible = "mediatek,mt7981-sgmiisys_1", "mediatek,mt7986-sgmiisys_1", "syscon";
|
||||
reg = <0 0x10070000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
topmisc: topmisc@11d10000 {
|
||||
compatible = "mediatek,mt7981-topmisc", "syscon";
|
||||
reg = <0 0x11d10000 0 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
snand: snfi@11005000 {
|
||||
compatible = "mediatek,mt7986-snand";
|
||||
reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
|
||||
reg-names = "nfi", "ecc";
|
||||
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
|
||||
<&infracfg CLK_INFRA_NFI1_CK>,
|
||||
<&infracfg CLK_INFRA_NFI_HCK_CK>;
|
||||
clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
|
||||
assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
|
||||
<&topckgen CLK_TOP_NFI1X_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
|
||||
<&topckgen CLK_TOP_CB_M_D8>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc0: mmc@11230000 {
|
||||
compatible = "mediatek,mt7986-mmc",
|
||||
"mediatek,mt7981-mmc";
|
||||
reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&infracfg CLK_INFRA_MSDC_CK>,
|
||||
<&infracfg CLK_INFRA_MSDC_HCK_CK>,
|
||||
<&infracfg CLK_INFRA_MSDC_66M_CK>,
|
||||
<&infracfg CLK_INFRA_MSDC_133M_CK>;
|
||||
assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
|
||||
<&topckgen CLK_TOP_EMMC_400M_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
|
||||
<&topckgen CLK_TOP_CB_NET2_D2>;
|
||||
clock-names = "source", "hclk", "axi_cg", "ahb_cg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wed_pcie: wed_pcie@10003000 {
|
||||
compatible = "mediatek,wed_pcie";
|
||||
reg = <0 0x10003000 0 0x10>;
|
||||
};
|
||||
|
||||
spi0: spi@1100a000 {
|
||||
compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0 0x1100a000 0 0x100>;
|
||||
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&topckgen CLK_TOP_CB_M_D2>,
|
||||
<&topckgen CLK_TOP_SPI_SEL>,
|
||||
<&infracfg CLK_INFRA_SPI0_CK>,
|
||||
<&infracfg CLK_INFRA_SPI0_HCK_CK>;
|
||||
|
||||
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@1100b000 {
|
||||
compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0 0x1100b000 0 0x100>;
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&topckgen CLK_TOP_CB_M_D2>,
|
||||
<&topckgen CLK_TOP_SPIM_MST_SEL>,
|
||||
<&infracfg CLK_INFRA_SPI1_CK>,
|
||||
<&infracfg CLK_INFRA_SPI1_HCK_CK>;
|
||||
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi2: spi@11009000 {
|
||||
compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0 0x11009000 0 0x100>;
|
||||
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&topckgen CLK_TOP_CB_M_D2>,
|
||||
<&topckgen CLK_TOP_SPI_SEL>,
|
||||
<&infracfg CLK_INFRA_SPI2_CK>,
|
||||
<&infracfg CLK_INFRA_SPI2_HCK_CK>;
|
||||
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
consys: consys@10000000 {
|
||||
compatible = "mediatek,mt7981-consys";
|
||||
reg = <0 0x10000000 0 0x8600000>;
|
||||
memory-region = <&wmcpu_emi>;
|
||||
};
|
||||
|
||||
xhci: usb@11200000 {
|
||||
compatible = "mediatek,mt7986-xhci",
|
||||
"mediatek,mtk-xhci";
|
||||
reg = <0 0x11200000 0 0x2e00>,
|
||||
<0 0x11203e00 0 0x0100>;
|
||||
reg-names = "mac", "ippc";
|
||||
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
|
||||
<&infracfg CLK_INFRA_IUSB_CK>,
|
||||
<&infracfg CLK_INFRA_IUSB_133_CK>,
|
||||
<&infracfg CLK_INFRA_IUSB_66M_CK>,
|
||||
<&topckgen CLK_TOP_U2U3_XHCI_SEL>;
|
||||
clock-names = "sys_ck",
|
||||
"ref_ck",
|
||||
"mcu_ck",
|
||||
"dma_ck",
|
||||
"xhci_ck";
|
||||
phys = <&u2port0 PHY_TYPE_USB2>,
|
||||
<&u3port0 PHY_TYPE_USB3>;
|
||||
vusb33-supply = <®_3p3v>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_phy: usb-phy@11e10000 {
|
||||
compatible = "mediatek,mt7981",
|
||||
"mediatek,generic-tphy-v2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x11e10000 0x1700>;
|
||||
status = "disabled";
|
||||
|
||||
u2port0: usb-phy@0 {
|
||||
reg = <0x0 0x700>;
|
||||
clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
|
||||
clock-names = "ref";
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
u3port0: usb-phy@700 {
|
||||
reg = <0x700 0x900>;
|
||||
clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
|
||||
clock-names = "ref";
|
||||
#phy-cells = <1>;
|
||||
mediatek,syscon-type = <&topmisc 0x218 0>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
reg_3p3v: regulator-3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
efuse: efuse@11f20000 {
|
||||
compatible = "mediatek,mt7981-efuse",
|
||||
"mediatek,efuse";
|
||||
reg = <0 0x11f20000 0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
status = "okay";
|
||||
|
||||
thermal_calibration: thermal-calib@274 {
|
||||
reg = <0x274 0xc>;
|
||||
};
|
||||
|
||||
phy_calibration: phy-calib@8dc {
|
||||
reg = <0x8dc 0x10>;
|
||||
};
|
||||
|
||||
comb_rx_imp_p0: usb3-rx-imp@8c8 {
|
||||
reg = <0x8c8 1>;
|
||||
bits = <0 5>;
|
||||
};
|
||||
|
||||
comb_tx_imp_p0: usb3-tx-imp@8c8 {
|
||||
reg = <0x8c8 2>;
|
||||
bits = <5 5>;
|
||||
};
|
||||
|
||||
comb_intr_p0: usb3-intr@8c9 {
|
||||
reg = <0x8c9 1>;
|
||||
bits = <2 6>;
|
||||
};
|
||||
};
|
||||
|
||||
afe: audio-controller@11210000 {
|
||||
compatible = "mediatek,mt79xx-audio";
|
||||
reg = <0 0x11210000 0 0x9000>;
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
|
||||
<&infracfg CLK_INFRA_AUD_26M_CK>,
|
||||
<&infracfg CLK_INFRA_AUD_L_CK>,
|
||||
<&infracfg CLK_INFRA_AUD_AUD_CK>,
|
||||
<&infracfg CLK_INFRA_AUD_EG2_CK>,
|
||||
<&topckgen CLK_TOP_AUD_SEL>;
|
||||
clock-names = "aud_bus_ck",
|
||||
"aud_26m_ck",
|
||||
"aud_l_ck",
|
||||
"aud_aud_ck",
|
||||
"aud_eg2_ck",
|
||||
"aud_sel";
|
||||
assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
|
||||
<&topckgen CLK_TOP_A1SYS_SEL>,
|
||||
<&topckgen CLK_TOP_AUD_L_SEL>,
|
||||
<&topckgen CLK_TOP_A_TUNER_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>,
|
||||
<&topckgen CLK_TOP_APLL2_D4>,
|
||||
<&topckgen CLK_TOP_CB_APLL2_196M>,
|
||||
<&topckgen CLK_TOP_APLL2_D4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ice: ice_debug {
|
||||
compatible = "mediatek,mt7981-ice_debug",
|
||||
"mediatek,mt2701-ice_debug";
|
||||
clocks = <&infracfg CLK_INFRA_DBG_CK>;
|
||||
clock-names = "ice_dbg";
|
||||
};
|
||||
|
||||
wifi: wifi@18000000 {
|
||||
compatible = "mediatek,mt7981-wmac";
|
||||
resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
|
||||
reset-names = "consys";
|
||||
pinctrl-0 = <&wifi_dbdc_pins>;
|
||||
pinctrl-names = "dbdc";
|
||||
clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
|
||||
<&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
|
||||
clock-names = "mcu", "ap2conn";
|
||||
reg = <0 0x18000000 0 0x1000000>,
|
||||
<0 0x10003000 0 0x1000>,
|
||||
<0 0x11d10000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
|
||||
memory-region = <&wmcpu_emi>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
|
@ -0,0 +1,52 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
|
||||
|
||||
#include "mt7986a-rfb.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "mediatek,mt7986a-rfb-snand";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi_nand: spi_nand@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spi-nand";
|
||||
reg = <1>;
|
||||
spi-max-frequency = <10000000>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "BL2";
|
||||
reg = <0x00000 0x0100000>;
|
||||
read-only;
|
||||
};
|
||||
partition@100000 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x0100000 0x0080000>;
|
||||
};
|
||||
factory: partition@180000 {
|
||||
label = "Factory";
|
||||
reg = <0x180000 0x0200000>;
|
||||
};
|
||||
partition@380000 {
|
||||
label = "FIP";
|
||||
reg = <0x380000 0x0200000>;
|
||||
};
|
||||
partition@580000 {
|
||||
label = "ubi";
|
||||
reg = <0x580000 0x4000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&wifi {
|
||||
mediatek,mtd-eeprom = <&factory 0>;
|
||||
};
|
|
@ -0,0 +1,51 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
|
||||
|
||||
#include "mt7986a-rfb.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "mediatek,mt7986a-rfb-snor";
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
|
||||
spi_nor: spi_nor@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <52000000>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@00000 {
|
||||
label = "BL2";
|
||||
reg = <0x00000 0x0040000>;
|
||||
};
|
||||
partition@40000 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x40000 0x0010000>;
|
||||
};
|
||||
factory: partition@50000 {
|
||||
label = "Factory";
|
||||
reg = <0x50000 0x00B0000>;
|
||||
};
|
||||
partition@100000 {
|
||||
label = "FIP";
|
||||
reg = <0x100000 0x0080000>;
|
||||
};
|
||||
partition@180000 {
|
||||
label = "firmware";
|
||||
reg = <0x180000 0xE00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&wifi {
|
||||
mediatek,mtd-eeprom = <&factory 0>;
|
||||
};
|
|
@ -0,0 +1,389 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2021 MediaTek Inc.
|
||||
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "mt7986a.dtsi"
|
||||
|
||||
/ {
|
||||
model = "MediaTek MT7986a RFB";
|
||||
compatible = "mediatek,mt7986a-rfb";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0 0x40000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
reg_1p8v: regulator-1p8v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-1.8V";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator-3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_5v: regulator-5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-5V";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
ð {
|
||||
status = "okay";
|
||||
|
||||
gmac0: mac@0 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <0>;
|
||||
phy-mode = "2500base-x";
|
||||
|
||||
fixed-link {
|
||||
speed = <2500>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
|
||||
gmac1: mac@1 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <1>;
|
||||
phy-mode = "2500base-x";
|
||||
};
|
||||
|
||||
mdio: mdio-bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&wifi {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "dbdc";
|
||||
pinctrl-0 = <&wf_2g_5g_pins>;
|
||||
pinctrl-1 = <&wf_dbdc_pins>;
|
||||
};
|
||||
|
||||
&mdio {
|
||||
phy5: phy@5 {
|
||||
compatible = "ethernet-phy-id67c9.de0a";
|
||||
reg = <5>;
|
||||
|
||||
reset-gpios = <&pio 6 1>;
|
||||
reset-deassert-us = <20000>;
|
||||
};
|
||||
|
||||
phy6: phy@6 {
|
||||
compatible = "ethernet-phy-id67c9.de0a";
|
||||
reg = <6>;
|
||||
};
|
||||
|
||||
switch: switch@0 {
|
||||
compatible = "mediatek,mt7531";
|
||||
reg = <31>;
|
||||
reset-gpios = <&pio 5 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&crypto {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
pinctrl-0 = <&mmc0_pins_default>;
|
||||
pinctrl-1 = <&mmc0_pins_uhs>;
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
cap-mmc-highspeed;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
hs400-ds-delay = <0x14014>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <®_1p8v>;
|
||||
non-removable;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pio {
|
||||
mmc0_pins_default: mmc0-pins {
|
||||
mux {
|
||||
function = "emmc";
|
||||
groups = "emmc_51";
|
||||
};
|
||||
conf-cmd-dat {
|
||||
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
|
||||
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
|
||||
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
|
||||
input-enable;
|
||||
drive-strength = <4>;
|
||||
mediatek,pull-up-adv = <1>; /* pull-up 10K */
|
||||
};
|
||||
conf-clk {
|
||||
pins = "EMMC_CK";
|
||||
drive-strength = <6>;
|
||||
mediatek,pull-down-adv = <2>; /* pull-down 50K */
|
||||
};
|
||||
conf-ds {
|
||||
pins = "EMMC_DSL";
|
||||
mediatek,pull-down-adv = <2>; /* pull-down 50K */
|
||||
};
|
||||
conf-rst {
|
||||
pins = "EMMC_RSTB";
|
||||
drive-strength = <4>;
|
||||
mediatek,pull-up-adv = <1>; /* pull-up 10K */
|
||||
};
|
||||
};
|
||||
|
||||
mmc0_pins_uhs: mmc0-uhs-pins {
|
||||
mux {
|
||||
function = "emmc";
|
||||
groups = "emmc_51";
|
||||
};
|
||||
conf-cmd-dat {
|
||||
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
|
||||
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
|
||||
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
|
||||
input-enable;
|
||||
drive-strength = <4>;
|
||||
mediatek,pull-up-adv = <1>; /* pull-up 10K */
|
||||
};
|
||||
conf-clk {
|
||||
pins = "EMMC_CK";
|
||||
drive-strength = <6>;
|
||||
mediatek,pull-down-adv = <2>; /* pull-down 50K */
|
||||
};
|
||||
conf-ds {
|
||||
pins = "EMMC_DSL";
|
||||
mediatek,pull-down-adv = <2>; /* pull-down 50K */
|
||||
};
|
||||
conf-rst {
|
||||
pins = "EMMC_RSTB";
|
||||
drive-strength = <4>;
|
||||
mediatek,pull-up-adv = <1>; /* pull-up 10K */
|
||||
};
|
||||
};
|
||||
|
||||
pcie_pins: pcie-pins {
|
||||
mux {
|
||||
function = "pcie";
|
||||
groups = "pcie_clk", "pcie_wake", "pcie_pereset";
|
||||
};
|
||||
};
|
||||
|
||||
spic_pins_g2: spic-pins-29-to-32 {
|
||||
mux {
|
||||
function = "spi";
|
||||
groups = "spi1_2";
|
||||
};
|
||||
};
|
||||
|
||||
spi_flash_pins: spi-flash-pins-33-to-38 {
|
||||
mux {
|
||||
function = "spi";
|
||||
groups = "spi0", "spi0_wp_hold";
|
||||
};
|
||||
conf-pu {
|
||||
pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
|
||||
drive-strength = <8>;
|
||||
mediatek,pull-up-adv = <0>; /* bias-disable */
|
||||
};
|
||||
conf-pd {
|
||||
pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
|
||||
drive-strength = <8>;
|
||||
mediatek,pull-down-adv = <0>; /* bias-disable */
|
||||
};
|
||||
};
|
||||
|
||||
uart1_pins: uart1-pins {
|
||||
mux {
|
||||
function = "uart";
|
||||
groups = "uart1";
|
||||
};
|
||||
};
|
||||
|
||||
uart2_pins: uart2-pins {
|
||||
mux {
|
||||
function = "uart";
|
||||
groups = "uart2";
|
||||
};
|
||||
};
|
||||
|
||||
wf_2g_5g_pins: wf_2g_5g-pins {
|
||||
mux {
|
||||
function = "wifi";
|
||||
groups = "wf_2g", "wf_5g";
|
||||
};
|
||||
conf {
|
||||
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
|
||||
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
|
||||
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
|
||||
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
|
||||
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
|
||||
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
|
||||
"WF1_TOP_CLK", "WF1_TOP_DATA";
|
||||
drive-strength = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
wf_dbdc_pins: wf_dbdc-pins {
|
||||
mux {
|
||||
function = "wifi";
|
||||
groups = "wf_dbdc";
|
||||
};
|
||||
conf {
|
||||
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
|
||||
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
|
||||
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
|
||||
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
|
||||
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
|
||||
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
|
||||
"WF1_TOP_CLK", "WF1_TOP_DATA";
|
||||
drive-strength = <4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi_flash_pins>;
|
||||
cs-gpios = <0>, <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spic_pins_g2>;
|
||||
status = "okay";
|
||||
|
||||
proslic_spi: proslic_spi@0 {
|
||||
compatible = "silabs,proslic_spi";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <10000000>;
|
||||
spi-cpha = <1>;
|
||||
spi-cpol = <1>;
|
||||
channel_count = <1>;
|
||||
debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */
|
||||
reset_gpio = <&pio 7 0>;
|
||||
ig,enable-spi = <1>; /* 1: Enable, 0: Disable */
|
||||
};
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
phy-mode = "2500base-x";
|
||||
phy-connection-type = "2500base-x";
|
||||
phy-handle = <&phy6>;
|
||||
};
|
||||
|
||||
&switch {
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "wan";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
label = "lan6";
|
||||
|
||||
phy-mode = "2500base-x";
|
||||
phy-handle = <&phy5>;
|
||||
};
|
||||
|
||||
port@6 {
|
||||
reg = <6>;
|
||||
ethernet = <&gmac0>;
|
||||
phy-mode = "2500base-x";
|
||||
|
||||
fixed-link {
|
||||
speed = <2500>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ssusb {
|
||||
vusb33-supply = <®_3p3v>;
|
||||
vbus-supply = <®_5v>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_phy {
|
||||
status = "okay";
|
||||
};
|
|
@ -0,0 +1,33 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2021 MediaTek Inc.
|
||||
* Author: Frank Wunderlich <frank-w@public-files.de>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/ {
|
||||
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
||||
|
||||
fragment@0 {
|
||||
target = <&mmc0>;
|
||||
__overlay__ {
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
pinctrl-0 = <&mmc0_pins_emmc_51>;
|
||||
pinctrl-1 = <&mmc0_pins_emmc_51>;
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
cap-mmc-highspeed;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
hs400-ds-delay = <0x12814>;
|
||||
vqmmc-supply = <®_1p8v>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
non-removable;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,41 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2022 MediaTek Inc.
|
||||
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
||||
|
||||
fragment@0 {
|
||||
target = <&mdio_bus>;
|
||||
__overlay__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* external Aquantia AQR113C */
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reset-gpios = <&pio 72 GPIO_ACTIVE_LOW>;
|
||||
reset-assert-us = <100000>;
|
||||
reset-deassert-us = <221000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@1 {
|
||||
target = <&gmac1>;
|
||||
__overlay__ {
|
||||
phy-mode = "usxgmii";
|
||||
phy-connection-type = "usxgmii";
|
||||
phy = <&phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,30 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2022 MediaTek Inc.
|
||||
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/ {
|
||||
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
||||
|
||||
fragment@0 {
|
||||
target = <&gmac1>;
|
||||
__overlay__ {
|
||||
phy-mode = "internal";
|
||||
phy-connection-type = "internal";
|
||||
phy = <&int_2p5g_phy>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@1 {
|
||||
target = <&int_2p5g_phy>;
|
||||
__overlay__ {
|
||||
pinctrl-names = "i2p5gbe-led";
|
||||
pinctrl-0 = <&i2p5gbe_led0_pins>;
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,39 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2022 MediaTek Inc.
|
||||
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
||||
|
||||
fragment@0 {
|
||||
target = <&mdio_bus>;
|
||||
__overlay__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* external Maxlinear GPY211C */
|
||||
phy13: ethernet-phy@13 {
|
||||
reg = <13>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
phy-mode = "2500base-x";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@1 {
|
||||
target = <&gmac1>;
|
||||
__overlay__ {
|
||||
phy-mode = "2500base-x";
|
||||
phy-connection-type = "2500base-x";
|
||||
phy = <&phy13>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,47 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2022 MediaTek Inc.
|
||||
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
||||
|
||||
fragment@0 {
|
||||
target = <&i2c2>;
|
||||
__overlay__ {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_0_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@1 {
|
||||
target-path = "/";
|
||||
__overlay__ {
|
||||
sfp_esp1: sfp@1 {
|
||||
compatible = "sff,sfp";
|
||||
i2c-bus = <&i2c2>;
|
||||
mod-def0-gpios = <&pio 82 GPIO_ACTIVE_LOW>;
|
||||
los-gpios = <&pio 81 GPIO_ACTIVE_HIGH>;
|
||||
tx-disable-gpios = <&pio 36 GPIO_ACTIVE_HIGH>;
|
||||
maximum-power-milliwatt = <3000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@2 {
|
||||
target = <&gmac1>;
|
||||
__overlay__ {
|
||||
phy-mode = "10gbase-r";
|
||||
managed = "in-band-status";
|
||||
sfp = <&sfp_esp1>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,41 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2022 MediaTek Inc.
|
||||
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
||||
|
||||
fragment@0 {
|
||||
target = <&mdio_bus>;
|
||||
__overlay__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* external Aquantia AQR113C */
|
||||
phy8: ethernet-phy@8 {
|
||||
reg = <8>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>;
|
||||
reset-assert-us = <100000>;
|
||||
reset-deassert-us = <221000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@1 {
|
||||
target = <&gmac2>;
|
||||
__overlay__ {
|
||||
phy-mode = "usxgmii";
|
||||
phy-connection-type = "usxgmii";
|
||||
phy = <&phy8>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,39 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2022 MediaTek Inc.
|
||||
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
||||
|
||||
fragment@0 {
|
||||
target = <&mdio_bus>;
|
||||
__overlay__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* external Maxlinear GPY211C */
|
||||
phy5: ethernet-phy@5 {
|
||||
reg = <5>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
phy-mode = "2500base-x";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@1 {
|
||||
target = <&gmac2>;
|
||||
__overlay__ {
|
||||
phy-mode = "2500base-x";
|
||||
phy-connection-type = "2500base-x";
|
||||
phy = <&phy5>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,47 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2022 MediaTek Inc.
|
||||
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
||||
|
||||
fragment@0 {
|
||||
target = <&i2c1>;
|
||||
__overlay__ {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_sfp_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@1 {
|
||||
target-path = "/";
|
||||
__overlay__ {
|
||||
sfp_esp0: sfp@0 {
|
||||
compatible = "sff,sfp";
|
||||
i2c-bus = <&i2c1>;
|
||||
mod-def0-gpios = <&pio 35 GPIO_ACTIVE_LOW>;
|
||||
los-gpios = <&pio 33 GPIO_ACTIVE_HIGH>;
|
||||
tx-disable-gpios = <&pio 29 GPIO_ACTIVE_HIGH>;
|
||||
maximum-power-milliwatt = <3000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@2 {
|
||||
target = <&gmac2>;
|
||||
__overlay__ {
|
||||
phy-mode = "10gbase-r";
|
||||
managed = "in-band-status";
|
||||
sfp = <&sfp_esp0>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,31 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2023 MediaTek Inc.
|
||||
* Author: Frank Wunderlich <frank-w@public-files.de>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
||||
|
||||
fragment@1 {
|
||||
target-path = <&mmc0>;
|
||||
__overlay__ {
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
pinctrl-0 = <&mmc0_pins_sdcard>;
|
||||
pinctrl-1 = <&mmc0_pins_sdcard>;
|
||||
cd-gpios = <&pio 69 GPIO_ACTIVE_LOW>;
|
||||
bus-width = <4>;
|
||||
max-frequency = <52000000>;
|
||||
cap-sd-highspeed;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <®_3p3v>;
|
||||
no-mmc;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,69 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2022 MediaTek Inc.
|
||||
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/ {
|
||||
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
||||
|
||||
fragment@0 {
|
||||
target = <&snand>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "spi-nand";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <52000000>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
mediatek,nmbm;
|
||||
mediatek,bmt-max-ratio = <1>;
|
||||
mediatek,bmt-max-reserved-blocks = <64>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "BL2";
|
||||
reg = <0x00000 0x0100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x0100000 0x0080000>;
|
||||
};
|
||||
|
||||
partition@180000 {
|
||||
label = "Factory";
|
||||
reg = <0x180000 0x0400000>;
|
||||
};
|
||||
|
||||
partition@580000 {
|
||||
label = "FIP";
|
||||
reg = <0x580000 0x0200000>;
|
||||
};
|
||||
|
||||
partition@780000 {
|
||||
label = "ubi";
|
||||
reg = <0x780000 0x7080000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@1 {
|
||||
target = <&bch>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,64 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2022 MediaTek Inc.
|
||||
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/ {
|
||||
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
||||
|
||||
fragment@0 {
|
||||
target = <&spi0>;
|
||||
__overlay__ {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_flash_pins>;
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "spi-nand";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <52000000>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
mediatek,nmbm;
|
||||
mediatek,bmt-max-ratio = <1>;
|
||||
mediatek,bmt-max-reserved-blocks = <64>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "BL2";
|
||||
reg = <0x00000 0x0100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x0100000 0x0080000>;
|
||||
};
|
||||
|
||||
partition@180000 {
|
||||
label = "Factory";
|
||||
reg = <0x180000 0x0400000>;
|
||||
};
|
||||
|
||||
partition@580000 {
|
||||
label = "FIP";
|
||||
reg = <0x580000 0x0200000>;
|
||||
};
|
||||
|
||||
partition@780000 {
|
||||
label = "ubi";
|
||||
reg = <0x780000 0x7080000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,59 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2022 MediaTek Inc.
|
||||
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/ {
|
||||
compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
|
||||
|
||||
fragment@0 {
|
||||
target = <&spi2>;
|
||||
__overlay__ {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi2_flash_pins>;
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-cal-enable;
|
||||
spi-cal-mode = "read-data";
|
||||
spi-cal-datalen = <7>;
|
||||
spi-cal-data = /bits/ 8 <
|
||||
0x53 0x46 0x5F 0x42 0x4F 0x4F 0x54>; /* SF_BOOT */
|
||||
spi-cal-addrlen = <1>;
|
||||
spi-cal-addr = /bits/ 32 <0x0>;
|
||||
reg = <0>;
|
||||
spi-max-frequency = <52000000>;
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
|
||||
partition@00000 {
|
||||
label = "BL2";
|
||||
reg = <0x00000 0x0040000>;
|
||||
};
|
||||
partition@40000 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x40000 0x0010000>;
|
||||
};
|
||||
partition@50000 {
|
||||
label = "Factory";
|
||||
reg = <0x50000 0x0200000>;
|
||||
};
|
||||
partition@250000 {
|
||||
label = "FIP";
|
||||
reg = <0x250000 0x0080000>;
|
||||
};
|
||||
partition@2D0000 {
|
||||
label = "firmware";
|
||||
reg = <0x2D0000 0x1D30000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,200 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2022 MediaTek Inc.
|
||||
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "mt7988a.dtsi"
|
||||
#include <dt-bindings/pinctrl/mt65xx.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
|
||||
|
||||
/ {
|
||||
model = "MediaTek MT7988A Reference Board";
|
||||
compatible = "mediatek,mt7988a-rfb",
|
||||
"mediatek,mt7988";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200n1 loglevel=8 \
|
||||
earlycon=uart8250,mmio32,0x11000000 \
|
||||
pci=pcie_bus_perf";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0 0x40000000 0 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
ð {
|
||||
pinctrl-0 = <&mdio0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
proc-supply = <&rt5190_buck3>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
proc-supply = <&rt5190_buck3>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
proc-supply = <&rt5190_buck3>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
proc-supply = <&rt5190_buck3>;
|
||||
};
|
||||
|
||||
&cci {
|
||||
proc-supply = <&rt5190_buck3>;
|
||||
};
|
||||
|
||||
ð {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&switch {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gsw_phy0 {
|
||||
pinctrl-names = "gbe-led";
|
||||
pinctrl-0 = <&gbe0_led0_pins>;
|
||||
};
|
||||
|
||||
&gsw_phy0_led0 {
|
||||
status = "okay";
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
&gsw_phy1 {
|
||||
pinctrl-names = "gbe-led";
|
||||
pinctrl-0 = <&gbe1_led0_pins>;
|
||||
};
|
||||
|
||||
&gsw_phy1_led0 {
|
||||
status = "okay";
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
&gsw_phy2 {
|
||||
pinctrl-names = "gbe-led";
|
||||
pinctrl-0 = <&gbe2_led0_pins>;
|
||||
};
|
||||
|
||||
&gsw_phy2_led0 {
|
||||
status = "okay";
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
&gsw_phy3 {
|
||||
pinctrl-names = "gbe-led";
|
||||
pinctrl-0 = <&gbe3_led0_pins>;
|
||||
};
|
||||
|
||||
&gsw_phy3_led0 {
|
||||
status = "okay";
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
status = "okay";
|
||||
|
||||
rt5190a_64: rt5190a@64 {
|
||||
compatible = "richtek,rt5190a";
|
||||
reg = <0x64>;
|
||||
/*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/
|
||||
vin2-supply = <&rt5190_buck1>;
|
||||
vin3-supply = <&rt5190_buck1>;
|
||||
vin4-supply = <&rt5190_buck1>;
|
||||
|
||||
regulators {
|
||||
rt5190_buck1: buck1 {
|
||||
regulator-name = "rt5190a-buck1";
|
||||
regulator-min-microvolt = <5090000>;
|
||||
regulator-max-microvolt = <5090000>;
|
||||
regulator-allowed-modes =
|
||||
<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
buck2 {
|
||||
regulator-name = "vcore";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
rt5190_buck3: buck3 {
|
||||
regulator-name = "vproc";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
buck4 {
|
||||
regulator-name = "rt5190a-buck4";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <850000>;
|
||||
regulator-allowed-modes =
|
||||
<RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
ldo {
|
||||
regulator-name = "rt5190a-ldo";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssusb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssusb1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tphy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&xphy {
|
||||
status = "okay";
|
||||
};
|
File diff suppressed because it is too large
Load diff
|
@ -0,0 +1,113 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2023 MediaTek Inc.
|
||||
* Author: Sam Shih <sam.shih@mediatek.com>
|
||||
* Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
#include "clk-mux.h"
|
||||
#include "clk-pll.h"
|
||||
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
|
||||
|
||||
#define MT7988_PLL_FMAX (2500UL * MHZ)
|
||||
#define MT7988_PCW_CHG_SHIFT 2
|
||||
|
||||
#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
|
||||
_pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
|
||||
_tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, \
|
||||
_div_table) \
|
||||
{ \
|
||||
.id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \
|
||||
.en_mask = _en_mask, .flags = _flags, \
|
||||
.rst_bar_mask = BIT(_rst_bar_mask), .fmax = MT7988_PLL_FMAX, \
|
||||
.pcwbits = _pcwbits, .pd_reg = _pd_reg, \
|
||||
.pd_shift = _pd_shift, .tuner_reg = _tuner_reg, \
|
||||
.tuner_en_reg = _tuner_en_reg, .tuner_en_bit = _tuner_en_bit, \
|
||||
.pcw_reg = _pcw_reg, .pcw_shift = _pcw_shift, \
|
||||
.pcw_chg_reg = _pcw_chg_reg, \
|
||||
.pcw_chg_shift = MT7988_PCW_CHG_SHIFT, \
|
||||
.div_table = _div_table, .parent_name = "clkxtal", \
|
||||
}
|
||||
|
||||
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
|
||||
_pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
|
||||
_tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg) \
|
||||
PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, \
|
||||
_pcwbits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
|
||||
_tuner_en_bit, _pcw_reg, _pcw_shift, _pcw_chg_reg, NULL)
|
||||
|
||||
static const struct mtk_pll_data plls[] = {
|
||||
PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0,
|
||||
0, 32, 0x0104, 4, 0, 0, 0, 0x0108, 0, 0x0104),
|
||||
PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR,
|
||||
23, 32, 0x0114, 4, 0, 0, 0, 0x0118, 0, 0x0114),
|
||||
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001,
|
||||
HAVE_RST_BAR, 23, 32, 0x0124, 4, 0, 0, 0, 0x0128, 0, 0x0124),
|
||||
PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32,
|
||||
0x0134, 4, 0x0704, 0x0700, 1, 0x0138, 0, 0x0134),
|
||||
PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001,
|
||||
HAVE_RST_BAR, 23, 32, 0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144),
|
||||
PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001,
|
||||
(HAVE_RST_BAR | PLL_AO), 23, 32, 0x0154, 4, 0, 0, 0, 0x0158, 0,
|
||||
0x0154),
|
||||
PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0,
|
||||
0, 32, 0x0164, 4, 0, 0, 0, 0x0168, 0, 0x0164),
|
||||
PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32,
|
||||
0x0174, 4, 0, 0, 0, 0x0178, 0, 0x0174),
|
||||
PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001,
|
||||
(HAVE_RST_BAR | PLL_AO), 23, 32, 0x0204, 4, 0, 0, 0, 0x0208, 0,
|
||||
0x0204),
|
||||
PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001,
|
||||
HAVE_RST_BAR, 23, 32, 0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214),
|
||||
PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001,
|
||||
HAVE_RST_BAR, 23, 32, 0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304),
|
||||
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0,
|
||||
32, 0x0314, 4, 0, 0, 0, 0x0318, 0, 0x0314),
|
||||
};
|
||||
|
||||
static const struct of_device_id of_match_clk_mt7988_apmixed[] = {
|
||||
{ .compatible = "mediatek,mt7988-apmixedsys", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int clk_mt7988_apmixed_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
|
||||
if (!clk_data)
|
||||
return -ENOMEM;
|
||||
|
||||
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
|
||||
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r) {
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
goto free_apmixed_data;
|
||||
}
|
||||
return r;
|
||||
|
||||
free_apmixed_data:
|
||||
mtk_free_clk_data(clk_data);
|
||||
return r;
|
||||
}
|
||||
|
||||
static struct platform_driver clk_mt7988_apmixed_drv = {
|
||||
.probe = clk_mt7988_apmixed_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt7988-apmixed",
|
||||
.of_match_table = of_match_clk_mt7988_apmixed,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(clk_mt7988_apmixed_drv);
|
||||
MODULE_LICENSE("GPL");
|
|
@ -0,0 +1,141 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2023 MediaTek Inc.
|
||||
* Author: Sam Shih <sam.shih@mediatek.com>
|
||||
* Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs ethdma_cg_regs = {
|
||||
.set_ofs = 0x30,
|
||||
.clr_ofs = 0x30,
|
||||
.sta_ofs = 0x30,
|
||||
};
|
||||
|
||||
#define GATE_ETHDMA(_id, _name, _parent, _shift) \
|
||||
{ \
|
||||
.id = _id, .name = _name, .parent_name = _parent, \
|
||||
.regs = ðdma_cg_regs, .shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate ethdma_clks[] = {
|
||||
GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0),
|
||||
GATE_ETHDMA(CLK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "top_xtal", 1),
|
||||
GATE_ETHDMA(CLK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "top_xtal", 2),
|
||||
GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6),
|
||||
GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "top_xtal", 7),
|
||||
GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "top_xtal", 8),
|
||||
GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "top_xtal", 10),
|
||||
GATE_ETHDMA(CLK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw_sel", 16),
|
||||
GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197_sel",
|
||||
29),
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc ethdma_desc = {
|
||||
.clks = ethdma_clks,
|
||||
.num_clks = ARRAY_SIZE(ethdma_clks),
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs sgmii0_cg_regs = {
|
||||
.set_ofs = 0xe4,
|
||||
.clr_ofs = 0xe4,
|
||||
.sta_ofs = 0xe4,
|
||||
};
|
||||
|
||||
#define GATE_SGMII0(_id, _name, _parent, _shift) \
|
||||
{ \
|
||||
.id = _id, .name = _name, .parent_name = _parent, \
|
||||
.regs = &sgmii0_cg_regs, .shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate sgmii0_clks[] = {
|
||||
GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "top_xtal", 2),
|
||||
GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3),
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc sgmii0_desc = {
|
||||
.clks = sgmii0_clks,
|
||||
.num_clks = ARRAY_SIZE(sgmii0_clks),
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs sgmii1_cg_regs = {
|
||||
.set_ofs = 0xe4,
|
||||
.clr_ofs = 0xe4,
|
||||
.sta_ofs = 0xe4,
|
||||
};
|
||||
|
||||
#define GATE_SGMII1(_id, _name, _parent, _shift) \
|
||||
{ \
|
||||
.id = _id, .name = _name, .parent_name = _parent, \
|
||||
.regs = &sgmii1_cg_regs, .shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate sgmii1_clks[] = {
|
||||
GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "top_xtal", 2),
|
||||
GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3),
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc sgmii1_desc = {
|
||||
.clks = sgmii1_clks,
|
||||
.num_clks = ARRAY_SIZE(sgmii1_clks),
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs ethwarp_cg_regs = {
|
||||
.set_ofs = 0x14,
|
||||
.clr_ofs = 0x14,
|
||||
.sta_ofs = 0x14,
|
||||
};
|
||||
|
||||
#define GATE_ETHWARP(_id, _name, _parent, _shift) \
|
||||
{ \
|
||||
.id = _id, .name = _name, .parent_name = _parent, \
|
||||
.regs = ðwarp_cg_regs, .shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate ethwarp_clks[] = {
|
||||
GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en",
|
||||
"netsys_mcu_sel", 13),
|
||||
GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en",
|
||||
"netsys_mcu_sel", 14),
|
||||
GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en",
|
||||
"netsys_mcu_sel", 15),
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc ethwarp_desc = {
|
||||
.clks = ethwarp_clks,
|
||||
.num_clks = ARRAY_SIZE(ethwarp_clks),
|
||||
};
|
||||
|
||||
static const struct of_device_id of_match_clk_mt7986_eth[] = {
|
||||
{ .compatible = "mediatek,mt7988-ethsys", .data = ðdma_desc },
|
||||
{ .compatible = "mediatek,mt7988-sgmiisys_0", .data = &sgmii0_desc },
|
||||
{ .compatible = "mediatek,mt7988-sgmiisys_1", .data = &sgmii1_desc },
|
||||
{ .compatible = "mediatek,mt7988-ethwarp", .data = ðwarp_desc },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_eth);
|
||||
|
||||
static struct platform_driver clk_mt7988_eth_drv = {
|
||||
.driver = {
|
||||
.name = "clk-mt7988-eth",
|
||||
.of_match_table = of_match_clk_mt7986_eth,
|
||||
},
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
};
|
||||
module_platform_driver(clk_mt7988_eth_drv);
|
||||
|
||||
MODULE_DESCRIPTION("MediaTek MT7988 Ethernet clocks driver");
|
||||
MODULE_LICENSE("GPL");
|
|
@ -0,0 +1,376 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2023 MediaTek Inc.
|
||||
* Author: Sam Shih <sam.shih@mediatek.com>
|
||||
* Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
#include "clk-mux.h"
|
||||
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
|
||||
|
||||
static DEFINE_SPINLOCK(mt7988_clk_lock);
|
||||
|
||||
static const char *const infra_mux_uart0_parents[] __initconst = {
|
||||
"csw_infra_f26m_sel", "uart_sel"
|
||||
};
|
||||
|
||||
static const char *const infra_mux_uart1_parents[] __initconst = {
|
||||
"csw_infra_f26m_sel", "uart_sel"
|
||||
};
|
||||
|
||||
static const char *const infra_mux_uart2_parents[] __initconst = {
|
||||
"csw_infra_f26m_sel", "uart_sel"
|
||||
};
|
||||
|
||||
static const char *const infra_mux_spi0_parents[] __initconst = { "i2c_sel",
|
||||
"spi_sel" };
|
||||
|
||||
static const char *const infra_mux_spi1_parents[] __initconst = {
|
||||
"i2c_sel", "spim_mst_sel"
|
||||
};
|
||||
|
||||
static const char *const infra_pwm_bck_parents[] __initconst = {
|
||||
"top_rtc_32p7k", "csw_infra_f26m_sel", "sysaxi_sel", "pwm_sel"
|
||||
};
|
||||
|
||||
static const char *const infra_pcie_gfmux_tl_ck_o_p0_parents[] __initconst = {
|
||||
"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
|
||||
"pextp_tl_sel"
|
||||
};
|
||||
|
||||
static const char *const infra_pcie_gfmux_tl_ck_o_p1_parents[] __initconst = {
|
||||
"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
|
||||
"pextp_tl_p1_sel"
|
||||
};
|
||||
|
||||
static const char *const infra_pcie_gfmux_tl_ck_o_p2_parents[] __initconst = {
|
||||
"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
|
||||
"pextp_tl_p2_sel"
|
||||
};
|
||||
|
||||
static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = {
|
||||
"top_rtc_32p7k", "csw_infra_f26m_sel", "csw_infra_f26m_sel",
|
||||
"pextp_tl_p3_sel"
|
||||
};
|
||||
|
||||
static const struct mtk_mux infra_muxes[] = {
|
||||
/* MODULE_CLK_SEL_0 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
|
||||
infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014,
|
||||
0, 1, -1, -1, -1),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
|
||||
infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014,
|
||||
1, 1, -1, -1, -1),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
|
||||
infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014,
|
||||
2, 1, -1, -1, -1),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
|
||||
infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 4,
|
||||
1, -1, -1, -1),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
|
||||
infra_mux_spi1_parents, 0x0018, 0x0010, 0x0014, 5,
|
||||
1, -1, -1, -1),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel",
|
||||
infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 6,
|
||||
1, -1, -1, -1),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel",
|
||||
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 14,
|
||||
2, -1, -1, -1),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel",
|
||||
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 16,
|
||||
2, -1, -1, -1),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel",
|
||||
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 18,
|
||||
2, -1, -1, -1),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel",
|
||||
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 20,
|
||||
2, -1, -1, -1),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel",
|
||||
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 22,
|
||||
2, -1, -1, -1),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel",
|
||||
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 24,
|
||||
2, -1, -1, -1),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel",
|
||||
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 26,
|
||||
2, -1, -1, -1),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel",
|
||||
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 28,
|
||||
2, -1, -1, -1),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel",
|
||||
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 30,
|
||||
2, -1, -1, -1),
|
||||
/* MODULE_CLK_SEL_1 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL,
|
||||
"infra_pcie_gfmux_tl_o_p0_sel",
|
||||
infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028,
|
||||
0x0020, 0x0024, 0, 2, -1, -1, -1),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL,
|
||||
"infra_pcie_gfmux_tl_o_p1_sel",
|
||||
infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028,
|
||||
0x0020, 0x0024, 2, 2, -1, -1, -1),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL,
|
||||
"infra_pcie_gfmux_tl_o_p2_sel",
|
||||
infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028,
|
||||
0x0020, 0x0024, 4, 2, -1, -1, -1),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL,
|
||||
"infra_pcie_gfmux_tl_o_p3_sel",
|
||||
infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028,
|
||||
0x0020, 0x0024, 6, 2, -1, -1, -1),
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs infra0_cg_regs = {
|
||||
.set_ofs = 0x10,
|
||||
.clr_ofs = 0x14,
|
||||
.sta_ofs = 0x18,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs infra1_cg_regs = {
|
||||
.set_ofs = 0x40,
|
||||
.clr_ofs = 0x44,
|
||||
.sta_ofs = 0x48,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs infra2_cg_regs = {
|
||||
.set_ofs = 0x50,
|
||||
.clr_ofs = 0x54,
|
||||
.sta_ofs = 0x58,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs infra3_cg_regs = {
|
||||
.set_ofs = 0x60,
|
||||
.clr_ofs = 0x64,
|
||||
.sta_ofs = 0x68,
|
||||
};
|
||||
|
||||
#define GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, _flags) \
|
||||
{ \
|
||||
.id = _id, .name = _name, .parent_name = _parent, \
|
||||
.regs = &infra0_cg_regs, .shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \
|
||||
}
|
||||
|
||||
#define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flags) \
|
||||
{ \
|
||||
.id = _id, .name = _name, .parent_name = _parent, \
|
||||
.regs = &infra1_cg_regs, .shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \
|
||||
}
|
||||
|
||||
#define GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, _flags) \
|
||||
{ \
|
||||
.id = _id, .name = _name, .parent_name = _parent, \
|
||||
.regs = &infra2_cg_regs, .shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \
|
||||
}
|
||||
|
||||
#define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flags) \
|
||||
{ \
|
||||
.id = _id, .name = _name, .parent_name = _parent, \
|
||||
.regs = &infra3_cg_regs, .shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr, .flags = _flags, \
|
||||
}
|
||||
|
||||
#define GATE_INFRA0(_id, _name, _parent, _shift) \
|
||||
GATE_INFRA0_FLAGS(_id, _name, _parent, _shift, 0)
|
||||
|
||||
#define GATE_INFRA1(_id, _name, _parent, _shift) \
|
||||
GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
|
||||
|
||||
#define GATE_INFRA2(_id, _name, _parent, _shift) \
|
||||
GATE_INFRA2_FLAGS(_id, _name, _parent, _shift, 0)
|
||||
|
||||
#define GATE_INFRA3(_id, _name, _parent, _shift) \
|
||||
GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
|
||||
|
||||
#define GATE_CRITICAL(_id, _name, _parent, _regs, _shift) { \
|
||||
.id = _id, .name = _name, .parent_name = _parent, \
|
||||
.regs = _regs, .shift = _shift, \
|
||||
.flags = CLK_IS_CRITICAL, \
|
||||
.ops = &mtk_clk_gate_ops_setclr, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate infra_clks[] = {
|
||||
/* INFRA0 */
|
||||
GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P0,
|
||||
"infra_pcie_peri_ck_26m_ck_p0", "csw_infra_f26m_sel", 7),
|
||||
GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P1,
|
||||
"infra_pcie_peri_ck_26m_ck_p1", "csw_infra_f26m_sel", 8),
|
||||
GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P2,
|
||||
"infra_pcie_peri_ck_26m_ck_p2", "csw_infra_f26m_sel", 9),
|
||||
GATE_INFRA0(CLK_INFRA_PCIE_PERI_26M_CK_P3,
|
||||
"infra_pcie_peri_ck_26m_ck_p3", "csw_infra_f26m_sel", 10),
|
||||
/* INFRA1 */
|
||||
GATE_INFRA1(CLK_INFRA_66M_GPT_BCK, "infra_hf_66m_gpt_bck",
|
||||
"sysaxi_sel", 0),
|
||||
GATE_INFRA1(CLK_INFRA_66M_PWM_HCK, "infra_hf_66m_pwm_hck",
|
||||
"sysaxi_sel", 1),
|
||||
GATE_INFRA1(CLK_INFRA_66M_PWM_BCK, "infra_hf_66m_pwm_bck",
|
||||
"infra_pwm_sel", 2),
|
||||
GATE_INFRA1(CLK_INFRA_66M_PWM_CK1, "infra_hf_66m_pwm_ck1",
|
||||
"infra_pwm_ck1_sel", 3),
|
||||
GATE_INFRA1(CLK_INFRA_66M_PWM_CK2, "infra_hf_66m_pwm_ck2",
|
||||
"infra_pwm_ck2_sel", 4),
|
||||
GATE_INFRA1(CLK_INFRA_66M_PWM_CK3, "infra_hf_66m_pwm_ck3",
|
||||
"infra_pwm_ck3_sel", 5),
|
||||
GATE_INFRA1(CLK_INFRA_66M_PWM_CK4, "infra_hf_66m_pwm_ck4",
|
||||
"infra_pwm_ck4_sel", 6),
|
||||
GATE_INFRA1(CLK_INFRA_66M_PWM_CK5, "infra_hf_66m_pwm_ck5",
|
||||
"infra_pwm_ck5_sel", 7),
|
||||
GATE_INFRA1(CLK_INFRA_66M_PWM_CK6, "infra_hf_66m_pwm_ck6",
|
||||
"infra_pwm_ck6_sel", 8),
|
||||
GATE_INFRA1(CLK_INFRA_66M_PWM_CK7, "infra_hf_66m_pwm_ck7",
|
||||
"infra_pwm_ck7_sel", 9),
|
||||
GATE_INFRA1(CLK_INFRA_66M_PWM_CK8, "infra_hf_66m_pwm_ck8",
|
||||
"infra_pwm_ck8_sel", 10),
|
||||
GATE_INFRA1(CLK_INFRA_133M_CQDMA_BCK, "infra_hf_133m_cqdma_bck",
|
||||
"sysaxi_sel", 12),
|
||||
GATE_INFRA1(CLK_INFRA_66M_AUD_SLV_BCK, "infra_66m_aud_slv_bck",
|
||||
"sysaxi_sel", 13),
|
||||
GATE_INFRA1(CLK_INFRA_AUD_26M, "infra_f_faud_26m",
|
||||
"csw_infra_f26m_sel", 14),
|
||||
GATE_INFRA1(CLK_INFRA_AUD_L, "infra_f_faud_l", "aud_l_sel", 15),
|
||||
GATE_INFRA1(CLK_INFRA_AUD_AUD, "infra_f_aud_aud", "a1sys_sel", 16),
|
||||
GATE_INFRA1(CLK_INFRA_AUD_EG2, "infra_f_faud_eg2", "a_tuner_sel", 18),
|
||||
GATE_INFRA1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
|
||||
"csw_infra_f26m_sel", 19, CLK_IS_CRITICAL),
|
||||
// JTAG
|
||||
GATE_INFRA1_FLAGS(CLK_INFRA_133M_DBG_ACKM, "infra_hf_133m_dbg_ackm",
|
||||
"sysaxi_sel", 20, CLK_IS_CRITICAL),
|
||||
GATE_INFRA1(CLK_INFRA_66M_AP_DMA_BCK, "infra_66m_ap_dma_bck",
|
||||
"sysaxi_sel", 21),
|
||||
GATE_INFRA1(CLK_INFRA_66M_SEJ_BCK, "infra_hf_66m_sej_bck",
|
||||
"sysaxi_sel", 29),
|
||||
GATE_INFRA1(CLK_INFRA_PRE_CK_SEJ_F13M, "infra_pre_ck_sej_f13m",
|
||||
"csw_infra_f26m_sel", 30),
|
||||
/* INFRA2 */
|
||||
GATE_INFRA2(CLK_INFRA_26M_THERM_SYSTEM, "infra_hf_26m_therm_system",
|
||||
"csw_infra_f26m_sel", 0),
|
||||
GATE_INFRA2(CLK_INFRA_I2C_BCK, "infra_i2c_bck", "i2c_sel", 1),
|
||||
GATE_INFRA2(CLK_INFRA_52M_UART0_CK, "infra_f_52m_uart0",
|
||||
"infra_mux_uart0_sel", 3),
|
||||
GATE_INFRA2(CLK_INFRA_52M_UART1_CK, "infra_f_52m_uart1",
|
||||
"infra_mux_uart1_sel", 4),
|
||||
GATE_INFRA2(CLK_INFRA_52M_UART2_CK, "infra_f_52m_uart2",
|
||||
"infra_mux_uart2_sel", 5),
|
||||
GATE_INFRA2(CLK_INFRA_NFI, "infra_f_fnfi", "nfi1x_sel", 9),
|
||||
GATE_INFRA2(CLK_INFRA_SPINFI, "infra_f_fspinfi", "spinfi_sel", 10),
|
||||
GATE_INFRA2_FLAGS(CLK_INFRA_66M_NFI_HCK, "infra_hf_66m_nfi_hck",
|
||||
"sysaxi_sel", 11, CLK_IS_CRITICAL),
|
||||
GATE_INFRA2_FLAGS(CLK_INFRA_104M_SPI0, "infra_hf_104m_spi0",
|
||||
"infra_mux_spi0_sel", 12, CLK_IS_CRITICAL),
|
||||
GATE_INFRA2(CLK_INFRA_104M_SPI1, "infra_hf_104m_spi1",
|
||||
"infra_mux_spi1_sel", 13),
|
||||
GATE_INFRA2(CLK_INFRA_104M_SPI2_BCK, "infra_hf_104m_spi2_bck",
|
||||
"infra_mux_spi2_sel", 14),
|
||||
GATE_INFRA2_FLAGS(CLK_INFRA_66M_SPI0_HCK, "infra_hf_66m_spi0_hck",
|
||||
"sysaxi_sel", 15, CLK_IS_CRITICAL),
|
||||
GATE_INFRA2(CLK_INFRA_66M_SPI1_HCK, "infra_hf_66m_spi1_hck",
|
||||
"sysaxi_sel", 16),
|
||||
GATE_INFRA2(CLK_INFRA_66M_SPI2_HCK, "infra_hf_66m_spi2_hck",
|
||||
"sysaxi_sel", 17),
|
||||
GATE_INFRA2(CLK_INFRA_66M_FLASHIF_AXI, "infra_hf_66m_flashif_axi",
|
||||
"sysaxi_sel", 18),
|
||||
GATE_CRITICAL(CLK_INFRA_RTC, "infra_f_frtc", "top_rtc_32k", &infra2_cg_regs, 19),
|
||||
GATE_INFRA2(CLK_INFRA_26M_ADC_BCK, "infra_f_26m_adc_bck",
|
||||
"csw_infra_f26m_sel", 20),
|
||||
GATE_INFRA2(CLK_INFRA_RC_ADC, "infra_f_frc_adc", "infra_f_26m_adc_bck",
|
||||
21),
|
||||
GATE_INFRA2(CLK_INFRA_MSDC400, "infra_f_fmsdc400", "emmc_400m_sel",
|
||||
22),
|
||||
GATE_INFRA2(CLK_INFRA_MSDC2_HCK, "infra_f_fmsdc2_hck", "emmc_250m_sel",
|
||||
23),
|
||||
GATE_INFRA2(CLK_INFRA_133M_MSDC_0_HCK, "infra_hf_133m_msdc_0_hck",
|
||||
"sysaxi_sel", 24),
|
||||
GATE_INFRA2(CLK_INFRA_66M_MSDC_0_HCK, "infra_66m_msdc_0_hck",
|
||||
"sysaxi_sel", 25),
|
||||
GATE_INFRA2(CLK_INFRA_133M_CPUM_BCK, "infra_hf_133m_cpum_bck",
|
||||
"sysaxi_sel", 26),
|
||||
GATE_INFRA2(CLK_INFRA_BIST2FPC, "infra_hf_fbist2fpc", "nfi1x_sel", 27),
|
||||
GATE_INFRA2(CLK_INFRA_I2C_X16W_MCK_CK_P1,
|
||||
"infra_hf_i2c_x16w_mck_ck_p1", "sysaxi_sel", 29),
|
||||
GATE_INFRA2(CLK_INFRA_I2C_X16W_PCK_CK_P1,
|
||||
"infra_hf_i2c_x16w_pck_ck_p1", "sysaxi_sel", 31),
|
||||
/* INFRA3 */
|
||||
GATE_INFRA3(CLK_INFRA_133M_USB_HCK, "infra_133m_usb_hck", "sysaxi_sel",
|
||||
0),
|
||||
GATE_INFRA3(CLK_INFRA_133M_USB_HCK_CK_P1, "infra_133m_usb_hck_ck_p1",
|
||||
"sysaxi_sel", 1),
|
||||
GATE_INFRA3(CLK_INFRA_66M_USB_HCK, "infra_66m_usb_hck", "sysaxi_sel",
|
||||
2),
|
||||
GATE_INFRA3(CLK_INFRA_66M_USB_HCK_CK_P1, "infra_66m_usb_hck_ck_p1",
|
||||
"sysaxi_sel", 3),
|
||||
GATE_INFRA3(CLK_INFRA_USB_SYS, "infra_usb_sys", "usb_sys_sel", 4),
|
||||
GATE_INFRA3(CLK_INFRA_USB_SYS_CK_P1, "infra_usb_sys_ck_p1",
|
||||
"usb_sys_p1_sel", 5),
|
||||
GATE_INFRA3(CLK_INFRA_USB_REF, "infra_usb_ref", "top_xtal", 6),
|
||||
GATE_INFRA3(CLK_INFRA_USB_CK_P1, "infra_usb_ck_p1", "top_xtal", 7),
|
||||
GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT, "infra_usb_frmcnt",
|
||||
"usb_frmcnt_sel", 8, CLK_IS_CRITICAL),
|
||||
GATE_INFRA3_FLAGS(CLK_INFRA_USB_FRMCNT_CK_P1, "infra_usb_frmcnt_ck_p1",
|
||||
"usb_frmcnt_p1_sel", 9, CLK_IS_CRITICAL),
|
||||
GATE_INFRA3(CLK_INFRA_USB_PIPE, "infra_usb_pipe", "sspxtp_sel", 10),
|
||||
GATE_INFRA3(CLK_INFRA_USB_PIPE_CK_P1, "infra_usb_pipe_ck_p1",
|
||||
"usb_phy_sel", 11),
|
||||
GATE_INFRA3(CLK_INFRA_USB_UTMI, "infra_usb_utmi", "top_xtal", 12),
|
||||
GATE_INFRA3(CLK_INFRA_USB_UTMI_CK_P1, "infra_usb_utmi_ck_p1",
|
||||
"top_xtal", 13),
|
||||
GATE_INFRA3(CLK_INFRA_USB_XHCI, "infra_usb_xhci", "usb_xhci_sel", 14),
|
||||
GATE_INFRA3(CLK_INFRA_USB_XHCI_CK_P1, "infra_usb_xhci_ck_p1",
|
||||
"usb_xhci_p1_sel", 15),
|
||||
GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P0, "infra_pcie_gfmux_tl_ck_p0",
|
||||
"infra_pcie_gfmux_tl_o_p0_sel", 20),
|
||||
GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P1, "infra_pcie_gfmux_tl_ck_p1",
|
||||
"infra_pcie_gfmux_tl_o_p1_sel", 21),
|
||||
GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P2, "infra_pcie_gfmux_tl_ck_p2",
|
||||
"infra_pcie_gfmux_tl_o_p2_sel", 22),
|
||||
GATE_INFRA3(CLK_INFRA_PCIE_GFMUX_TL_P3, "infra_pcie_gfmux_tl_ck_p3",
|
||||
"infra_pcie_gfmux_tl_o_p3_sel", 23),
|
||||
GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P0, "infra_pcie_pipe_ck_p0",
|
||||
"top_xtal", 24),
|
||||
GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P1, "infra_pcie_pipe_ck_p1",
|
||||
"top_xtal", 25),
|
||||
GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P2, "infra_pcie_pipe_ck_p2",
|
||||
"top_xtal", 26),
|
||||
GATE_INFRA3(CLK_INFRA_PCIE_PIPE_P3, "infra_pcie_pipe_ck_p3",
|
||||
"top_xtal", 27),
|
||||
GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P0, "infra_133m_pcie_ck_p0",
|
||||
"sysaxi_sel", 28),
|
||||
GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P1, "infra_133m_pcie_ck_p1",
|
||||
"sysaxi_sel", 29),
|
||||
GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P2, "infra_133m_pcie_ck_p2",
|
||||
"sysaxi_sel", 30),
|
||||
GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3",
|
||||
"sysaxi_sel", 31),
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc infra_desc = {
|
||||
.clks = infra_clks,
|
||||
.num_clks = ARRAY_SIZE(infra_clks),
|
||||
.mux_clks = infra_muxes,
|
||||
.num_mux_clks = ARRAY_SIZE(infra_muxes),
|
||||
.clk_lock = &mt7988_clk_lock,
|
||||
};
|
||||
|
||||
static const struct of_device_id of_match_clk_mt7988_infracfg[] = {
|
||||
{ .compatible = "mediatek,mt7988-infracfg", .data = &infra_desc },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_infracfg);
|
||||
|
||||
static struct platform_driver clk_mt7988_infracfg_drv = {
|
||||
.driver = {
|
||||
.name = "clk-mt7988-infracfg",
|
||||
.of_match_table = of_match_clk_mt7988_infracfg,
|
||||
},
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
};
|
||||
module_platform_driver(clk_mt7988_infracfg_drv);
|
|
@ -0,0 +1,446 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2023 MediaTek Inc.
|
||||
* Author: Sam Shih <sam.shih@mediatek.com>
|
||||
* Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
#include "clk-mux.h"
|
||||
#include <dt-bindings/clock/mediatek,mt7988-clk.h>
|
||||
|
||||
static DEFINE_SPINLOCK(mt7988_clk_lock);
|
||||
|
||||
static const struct mtk_fixed_clk top_fixed_clks[] = {
|
||||
FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),
|
||||
};
|
||||
|
||||
static const struct mtk_fixed_factor top_divs[] = {
|
||||
FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
|
||||
FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
|
||||
FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
|
||||
FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2),
|
||||
FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2),
|
||||
FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4),
|
||||
FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8),
|
||||
FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16),
|
||||
FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
|
||||
FACTOR(CLK_TOP_MMPLL_D3_D5, "mmpll_d3_d5", "mmpll", 1, 15),
|
||||
FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
|
||||
FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12),
|
||||
FACTOR(CLK_TOP_MMPLL_D8, "mmpll_d8", "mmpll", 1, 8),
|
||||
FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
|
||||
FACTOR(CLK_TOP_NET1PLL_D4, "net1pll_d4", "net1pll", 1, 4),
|
||||
FACTOR(CLK_TOP_NET1PLL_D5, "net1pll_d5", "net1pll", 1, 5),
|
||||
FACTOR(CLK_TOP_NET1PLL_D5_D2, "net1pll_d5_d2", "net1pll", 1, 10),
|
||||
FACTOR(CLK_TOP_NET1PLL_D5_D4, "net1pll_d5_d4", "net1pll", 1, 20),
|
||||
FACTOR(CLK_TOP_NET1PLL_D8, "net1pll_d8", "net1pll", 1, 8),
|
||||
FACTOR(CLK_TOP_NET1PLL_D8_D2, "net1pll_d8_d2", "net1pll", 1, 16),
|
||||
FACTOR(CLK_TOP_NET1PLL_D8_D4, "net1pll_d8_d4", "net1pll", 1, 32),
|
||||
FACTOR(CLK_TOP_NET1PLL_D8_D8, "net1pll_d8_d8", "net1pll", 1, 64),
|
||||
FACTOR(CLK_TOP_NET1PLL_D8_D16, "net1pll_d8_d16", "net1pll", 1, 128),
|
||||
FACTOR(CLK_TOP_NET2PLL_D2, "net2pll_d2", "net2pll", 1, 2),
|
||||
FACTOR(CLK_TOP_NET2PLL_D4, "net2pll_d4", "net2pll", 1, 4),
|
||||
FACTOR(CLK_TOP_NET2PLL_D4_D4, "net2pll_d4_d4", "net2pll", 1, 16),
|
||||
FACTOR(CLK_TOP_NET2PLL_D4_D8, "net2pll_d4_d8", "net2pll", 1, 32),
|
||||
FACTOR(CLK_TOP_NET2PLL_D6, "net2pll_d6", "net2pll", 1, 6),
|
||||
FACTOR(CLK_TOP_NET2PLL_D8, "net2pll_d8", "net2pll", 1, 8),
|
||||
};
|
||||
|
||||
static const char *const netsys_parents[] = { "top_xtal", "net2pll_d2",
|
||||
"mmpll_d2" };
|
||||
|
||||
static const char *const netsys_500m_parents[] = { "top_xtal", "net1pll_d5",
|
||||
"net1pll_d5_d2" };
|
||||
|
||||
static const char *const netsys_2x_parents[] = { "top_xtal", "net2pll",
|
||||
"mmpll" };
|
||||
|
||||
static const char *const netsys_gsw_parents[] = { "top_xtal", "net1pll_d4",
|
||||
"net1pll_d5" };
|
||||
|
||||
static const char *const eth_gmii_parents[] = { "top_xtal", "net1pll_d5_d4" };
|
||||
|
||||
static const char *const netsys_mcu_parents[] = { "top_xtal", "net2pll",
|
||||
"mmpll", "net1pll_d4",
|
||||
"net1pll_d5", "mpll" };
|
||||
|
||||
static const char *const eip197_parents[] = { "top_xtal", "netsyspll",
|
||||
"net2pll", "mmpll",
|
||||
"net1pll_d4", "net1pll_d5" };
|
||||
|
||||
static const char *const axi_infra_parents[] = { "top_xtal", "net1pll_d8_d2" };
|
||||
|
||||
static const char *const uart_parents[] = { "top_xtal", "mpll_d8",
|
||||
"mpll_d8_d2" };
|
||||
|
||||
static const char *const emmc_250m_parents[] = { "top_xtal", "net1pll_d5_d2",
|
||||
"mmpll_d4" };
|
||||
|
||||
static const char *const emmc_400m_parents[] = { "top_xtal", "msdcpll",
|
||||
"mmpll_d2", "mpll_d2",
|
||||
"mmpll_d4", "net1pll_d8_d2" };
|
||||
|
||||
static const char *const spi_parents[] = { "top_xtal", "mpll_d2",
|
||||
"mmpll_d4", "net1pll_d8_d2",
|
||||
"net2pll_d6", "net1pll_d5_d4",
|
||||
"mpll_d4", "net1pll_d8_d4" };
|
||||
|
||||
static const char *const nfi1x_parents[] = { "top_xtal", "mmpll_d4",
|
||||
"net1pll_d8_d2", "net2pll_d6",
|
||||
"mpll_d4", "mmpll_d8",
|
||||
"net1pll_d8_d4", "mpll_d8" };
|
||||
|
||||
static const char *const spinfi_parents[] = { "top_xtal_d2", "top_xtal",
|
||||
"net1pll_d5_d4", "mpll_d4",
|
||||
"mmpll_d8", "net1pll_d8_d4",
|
||||
"mmpll_d6_d2", "mpll_d8" };
|
||||
|
||||
static const char *const pwm_parents[] = { "top_xtal", "net1pll_d8_d2",
|
||||
"net1pll_d5_d4", "mpll_d4",
|
||||
"mpll_d8_d2", "top_rtc_32k" };
|
||||
|
||||
static const char *const i2c_parents[] = { "top_xtal", "net1pll_d5_d4",
|
||||
"mpll_d4", "net1pll_d8_d4" };
|
||||
|
||||
static const char *const pcie_mbist_250m_parents[] = { "top_xtal",
|
||||
"net1pll_d5_d2" };
|
||||
|
||||
static const char *const pextp_tl_ck_parents[] = { "top_xtal", "net2pll_d6",
|
||||
"mmpll_d8", "mpll_d8_d2",
|
||||
"top_rtc_32k" };
|
||||
|
||||
static const char *const usb_frmcnt_parents[] = { "top_xtal", "mmpll_d3_d5" };
|
||||
|
||||
static const char *const aud_parents[] = { "top_xtal", "apll2" };
|
||||
|
||||
static const char *const a1sys_parents[] = { "top_xtal", "apll2_d4" };
|
||||
|
||||
static const char *const aud_l_parents[] = { "top_xtal", "apll2",
|
||||
"mpll_d8_d2" };
|
||||
|
||||
static const char *const sspxtp_parents[] = { "top_xtal_d2", "mpll_d8_d2" };
|
||||
|
||||
static const char *const usxgmii_sbus_0_parents[] = { "top_xtal",
|
||||
"net1pll_d8_d4" };
|
||||
|
||||
static const char *const sgm_0_parents[] = { "top_xtal", "sgmpll" };
|
||||
|
||||
static const char *const sysapb_parents[] = { "top_xtal", "mpll_d3_d2" };
|
||||
|
||||
static const char *const eth_refck_50m_parents[] = { "top_xtal",
|
||||
"net2pll_d4_d4" };
|
||||
|
||||
static const char *const eth_sys_200m_parents[] = { "top_xtal", "net2pll_d4" };
|
||||
|
||||
static const char *const eth_xgmii_parents[] = { "top_xtal_d2",
|
||||
"net1pll_d8_d8",
|
||||
"net1pll_d8_d16" };
|
||||
|
||||
static const char *const bus_tops_parents[] = { "top_xtal", "net1pll_d5",
|
||||
"net2pll_d2" };
|
||||
|
||||
static const char *const npu_tops_parents[] = { "top_xtal", "net2pll" };
|
||||
|
||||
static const char *const dramc_md32_parents[] = { "top_xtal", "mpll_d2",
|
||||
"wedmcupll" };
|
||||
|
||||
static const char *const da_xtp_glb_p0_parents[] = { "top_xtal",
|
||||
"net2pll_d8" };
|
||||
|
||||
static const char *const mcusys_backup_625m_parents[] = { "top_xtal",
|
||||
"net1pll_d4" };
|
||||
|
||||
static const char *const macsec_parents[] = { "top_xtal", "sgmpll",
|
||||
"net1pll_d8" };
|
||||
|
||||
static const char *const netsys_tops_400m_parents[] = { "top_xtal",
|
||||
"net2pll_d2" };
|
||||
|
||||
static const char *const eth_mii_parents[] = { "top_xtal_d2",
|
||||
"net2pll_d4_d8" };
|
||||
|
||||
static const struct mtk_mux top_muxes[] = {
|
||||
/* CLK_CFG_0 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
|
||||
0x000, 0x004, 0x008, 0, 2, 7, 0x1c0, 0),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
|
||||
netsys_500m_parents, 0x000, 0x004, 0x008, 8, 2,
|
||||
15, 0x1C0, 1),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
|
||||
netsys_2x_parents, 0x000, 0x004, 0x008, 16, 2, 23,
|
||||
0x1C0, 2),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel",
|
||||
netsys_gsw_parents, 0x000, 0x004, 0x008, 24, 2,
|
||||
31, 0x1C0, 3),
|
||||
/* CLK_CFG_1 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel",
|
||||
eth_gmii_parents, 0x010, 0x014, 0x018, 0, 1, 7,
|
||||
0x1C0, 4),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
|
||||
netsys_mcu_parents, 0x010, 0x014, 0x018, 8, 3, 15,
|
||||
0x1C0, 5),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PAO_2X_SEL, "netsys_pao_2x_sel",
|
||||
netsys_mcu_parents, 0x010, 0x014, 0x018, 16, 3,
|
||||
23, 0x1C0, 6),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP197_SEL, "eip197_sel", eip197_parents,
|
||||
0x010, 0x014, 0x018, 24, 3, 31, 0x1c0, 7),
|
||||
/* CLK_CFG_2 */
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_INFRA_SEL, "axi_infra_sel",
|
||||
axi_infra_parents, 0x020, 0x024, 0x028, 0,
|
||||
1, 7, 0x1C0, 8, CLK_IS_CRITICAL),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x020,
|
||||
0x024, 0x028, 8, 2, 15, 0x1c0, 9),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel",
|
||||
emmc_250m_parents, 0x020, 0x024, 0x028, 16, 2, 23,
|
||||
0x1C0, 10),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_400M_SEL, "emmc_400m_sel",
|
||||
emmc_400m_parents, 0x020, 0x024, 0x028, 24, 3, 31,
|
||||
0x1C0, 11),
|
||||
/* CLK_CFG_3 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x030,
|
||||
0x034, 0x038, 0, 3, 7, 0x1c0, 12),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
|
||||
0x030, 0x034, 0x038, 8, 3, 15, 0x1c0, 13),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
|
||||
0x030, 0x034, 0x038, 16, 3, 23, 0x1c0, 14),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
|
||||
0x030, 0x034, 0x038, 24, 3, 31, 0x1c0, 15),
|
||||
/* CLK_CFG_4 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x040,
|
||||
0x044, 0x048, 0, 3, 7, 0x1c0, 16),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x040,
|
||||
0x044, 0x048, 8, 2, 15, 0x1c0, 17),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_MBIST_250M_SEL,
|
||||
"pcie_mbist_250m_sel", pcie_mbist_250m_parents,
|
||||
0x040, 0x044, 0x048, 16, 1, 23, 0x1C0, 18),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_sel",
|
||||
pextp_tl_ck_parents, 0x040, 0x044, 0x048, 24, 3,
|
||||
31, 0x1C0, 19),
|
||||
/* CLK_CFG_5 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P1_SEL, "pextp_tl_p1_sel",
|
||||
pextp_tl_ck_parents, 0x050, 0x054, 0x058, 0, 3, 7,
|
||||
0x1C0, 20),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P2_SEL, "pextp_tl_p2_sel",
|
||||
pextp_tl_ck_parents, 0x050, 0x054, 0x058, 8, 3,
|
||||
15, 0x1C0, 21),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_P3_SEL, "pextp_tl_p3_sel",
|
||||
pextp_tl_ck_parents, 0x050, 0x054, 0x058, 16, 3,
|
||||
23, 0x1C0, 22),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_SEL, "usb_sys_sel",
|
||||
eth_gmii_parents, 0x050, 0x054, 0x058, 24, 1, 31,
|
||||
0x1C0, 23),
|
||||
/* CLK_CFG_6 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_SYS_P1_SEL, "usb_sys_p1_sel",
|
||||
eth_gmii_parents, 0x060, 0x064, 0x068, 0, 1, 7,
|
||||
0x1C0, 24),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_SEL, "usb_xhci_sel",
|
||||
eth_gmii_parents, 0x060, 0x064, 0x068, 8, 1, 15,
|
||||
0x1C0, 25),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "usb_xhci_p1_sel",
|
||||
eth_gmii_parents, 0x060, 0x064, 0x068, 16, 1, 23,
|
||||
0x1C0, 26),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel",
|
||||
usb_frmcnt_parents, 0x060, 0x064, 0x068, 24, 1,
|
||||
31, 0x1C0, 27),
|
||||
/* CLK_CFG_7 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_FRMCNT_P1_SEL, "usb_frmcnt_p1_sel",
|
||||
usb_frmcnt_parents, 0x070, 0x074, 0x078, 0, 1, 7,
|
||||
0x1C0, 28),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x070,
|
||||
0x074, 0x078, 8, 1, 15, 0x1c0, 29),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
|
||||
0x070, 0x074, 0x078, 16, 1, 23, 0x1c0, 30),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
|
||||
0x070, 0x074, 0x078, 24, 2, 31, 0x1c4, 0),
|
||||
/* CLK_CFG_8 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel", a1sys_parents,
|
||||
0x080, 0x084, 0x088, 0, 1, 7, 0x1c4, 1),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPXTP_SEL, "sspxtp_sel", sspxtp_parents,
|
||||
0x080, 0x084, 0x088, 8, 1, 15, 0x1c4, 2),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_PHY_SEL, "usb_phy_sel",
|
||||
sspxtp_parents, 0x080, 0x084, 0x088, 16, 1, 23,
|
||||
0x1c4, 3),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_0_SEL, "usxgmii_sbus_0_sel",
|
||||
usxgmii_sbus_0_parents, 0x080, 0x084, 0x088, 24,
|
||||
1, 31, 0x1C4, 4),
|
||||
/* CLK_CFG_9 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_USXGMII_SBUS_1_SEL, "usxgmii_sbus_1_sel",
|
||||
usxgmii_sbus_0_parents, 0x090, 0x094, 0x098, 0, 1,
|
||||
7, 0x1C4, 5),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_0_SEL, "sgm_0_sel", sgm_0_parents,
|
||||
0x090, 0x094, 0x098, 8, 1, 15, 0x1c4, 6),
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_0_SEL, "sgm_sbus_0_sel",
|
||||
usxgmii_sbus_0_parents, 0x090, 0x094, 0x098,
|
||||
16, 1, 23, 0x1C4, 7, CLK_IS_CRITICAL),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_1_SEL, "sgm_1_sel", sgm_0_parents,
|
||||
0x090, 0x094, 0x098, 24, 1, 31, 0x1c4, 8),
|
||||
/* CLK_CFG_10 */
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_SBUS_1_SEL, "sgm_sbus_1_sel",
|
||||
usxgmii_sbus_0_parents, 0x0a0, 0x0a4, 0x0a8,
|
||||
0, 1, 7, 0x1C4, 9, CLK_IS_CRITICAL),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_0_XTAL_SEL, "xfi_phy_0_xtal_sel",
|
||||
sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 8, 1, 15,
|
||||
0x1C4, 10),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_XFI_PHY_1_XTAL_SEL, "xfi_phy_1_xtal_sel",
|
||||
sspxtp_parents, 0x0a0, 0x0a4, 0x0a8, 16, 1, 23,
|
||||
0x1C4, 11),
|
||||
/* CLK_CFG_11 */
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
|
||||
axi_infra_parents, 0x0a0, 0x0a4, 0x0a8, 24,
|
||||
1, 31, 0x1C4, 12, CLK_IS_CRITICAL),
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
|
||||
sysapb_parents, 0x0b0, 0x0b4, 0x0b8, 0, 1,
|
||||
7, 0x1c4, 13, CLK_IS_CRITICAL),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_REFCK_50M_SEL, "eth_refck_50m_sel",
|
||||
eth_refck_50m_parents, 0x0b0, 0x0b4, 0x0b8, 8, 1,
|
||||
15, 0x1C4, 14),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_200M_SEL, "eth_sys_200m_sel",
|
||||
eth_sys_200m_parents, 0x0b0, 0x0b4, 0x0b8, 16, 1,
|
||||
23, 0x1C4, 15),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_SYS_SEL, "eth_sys_sel",
|
||||
pcie_mbist_250m_parents, 0x0b0, 0x0b4, 0x0b8, 24,
|
||||
1, 31, 0x1C4, 16),
|
||||
/* CLK_CFG_12 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_XGMII_SEL, "eth_xgmii_sel",
|
||||
eth_xgmii_parents, 0x0c0, 0x0c4, 0x0c8, 0, 2, 7,
|
||||
0x1C4, 17),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_BUS_TOPS_SEL, "bus_tops_sel",
|
||||
bus_tops_parents, 0x0c0, 0x0c4, 0x0c8, 8, 2, 15,
|
||||
0x1C4, 18),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_TOPS_SEL, "npu_tops_sel",
|
||||
npu_tops_parents, 0x0c0, 0x0c4, 0x0c8, 16, 1, 23,
|
||||
0x1C4, 19),
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
|
||||
sspxtp_parents, 0x0c0, 0x0c4, 0x0c8, 24, 1,
|
||||
31, 0x1C4, 20, CLK_IS_CRITICAL),
|
||||
/* CLK_CFG_13 */
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
|
||||
dramc_md32_parents, 0x0d0, 0x0d4, 0x0d8, 0,
|
||||
2, 7, 0x1C4, 21, CLK_IS_CRITICAL),
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(
|
||||
CLK_TOP_INFRA_F26M_SEL, "csw_infra_f26m_sel", sspxtp_parents,
|
||||
0x0d0, 0x0d4, 0x0d8, 8, 1, 15, 0x1C4, 22, CLK_IS_CRITICAL),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P0_SEL, "pextp_p0_sel",
|
||||
sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 16, 1, 23,
|
||||
0x1C4, 23),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P1_SEL, "pextp_p1_sel",
|
||||
sspxtp_parents, 0x0d0, 0x0d4, 0x0d8, 24, 1, 31,
|
||||
0x1C4, 24),
|
||||
/* CLK_CFG_14 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P2_SEL, "pextp_p2_sel",
|
||||
sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 0, 1, 7,
|
||||
0x1C4, 25),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_P3_SEL, "pextp_p3_sel",
|
||||
sspxtp_parents, 0x0e0, 0x0e4, 0x0e8, 8, 1, 15,
|
||||
0x1C4, 26),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P0_SEL, "da_xtp_glb_p0_sel",
|
||||
da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 16, 1,
|
||||
23, 0x1C4, 27),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P1_SEL, "da_xtp_glb_p1_sel",
|
||||
da_xtp_glb_p0_parents, 0x0e0, 0x0e4, 0x0e8, 24, 1,
|
||||
31, 0x1C4, 28),
|
||||
/* CLK_CFG_15 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P2_SEL, "da_xtp_glb_p2_sel",
|
||||
da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 0, 1,
|
||||
7, 0x1C4, 29),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_XTP_GLB_P3_SEL, "da_xtp_glb_p3_sel",
|
||||
da_xtp_glb_p0_parents, 0x0f0, 0x0f4, 0x0f8, 8, 1,
|
||||
15, 0x1C4, 30),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_CKM_SEL, "ckm_sel", sspxtp_parents, 0x0F0,
|
||||
0x0f4, 0x0f8, 16, 1, 23, 0x1c8, 0),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_SEL, "da_sel", sspxtp_parents, 0x0f0,
|
||||
0x0f4, 0x0f8, 24, 1, 31, 0x1C8, 1),
|
||||
/* CLK_CFG_16 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_SEL, "pextp_sel", sspxtp_parents,
|
||||
0x0100, 0x104, 0x108, 0, 1, 7, 0x1c8, 2),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_TOPS_P2_26M_SEL, "tops_p2_26m_sel",
|
||||
sspxtp_parents, 0x0100, 0x104, 0x108, 8, 1, 15,
|
||||
0x1C8, 3),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MCUSYS_BACKUP_625M_SEL,
|
||||
"mcusys_backup_625m_sel",
|
||||
mcusys_backup_625m_parents, 0x0100, 0x104, 0x108,
|
||||
16, 1, 23, 0x1C8, 4),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SYNC_250M_SEL,
|
||||
"netsys_sync_250m_sel", pcie_mbist_250m_parents,
|
||||
0x0100, 0x104, 0x108, 24, 1, 31, 0x1c8, 5),
|
||||
/* CLK_CFG_17 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MACSEC_SEL, "macsec_sel", macsec_parents,
|
||||
0x0110, 0x114, 0x118, 0, 2, 7, 0x1c8, 6),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_TOPS_400M_SEL,
|
||||
"netsys_tops_400m_sel", netsys_tops_400m_parents,
|
||||
0x0110, 0x114, 0x118, 8, 1, 15, 0x1c8, 7),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_PPEFB_250M_SEL,
|
||||
"netsys_ppefb_250m_sel", pcie_mbist_250m_parents,
|
||||
0x0110, 0x114, 0x118, 16, 1, 23, 0x1c8, 8),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_WARP_SEL, "netsys_warp_sel",
|
||||
netsys_parents, 0x0110, 0x114, 0x118, 24, 2, 31,
|
||||
0x1C8, 9),
|
||||
/* CLK_CFG_18 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_MII_SEL, "eth_mii_sel",
|
||||
eth_mii_parents, 0x0120, 0x124, 0x128, 0, 1, 7,
|
||||
0x1c8, 10),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_NPU_SEL, "ck_npu_sel", netsys_2x_parents,
|
||||
0x0120, 0x124, 0x128, 8, 2, 15, 0x1c8, 11),
|
||||
};
|
||||
|
||||
static const struct mtk_composite top_aud_divs[] = {
|
||||
DIV_GATE(CLK_TOP_AUD_I2S_M, "aud_i2s_m", "aud_sel", 0x0420, 0, 0x0420,
|
||||
8, 8),
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc topck_desc = {
|
||||
.fixed_clks = top_fixed_clks,
|
||||
.num_fixed_clks = ARRAY_SIZE(top_fixed_clks),
|
||||
.factor_clks = top_divs,
|
||||
.num_factor_clks = ARRAY_SIZE(top_divs),
|
||||
.mux_clks = top_muxes,
|
||||
.num_mux_clks = ARRAY_SIZE(top_muxes),
|
||||
.composite_clks = top_aud_divs,
|
||||
.num_composite_clks = ARRAY_SIZE(top_aud_divs),
|
||||
.clk_lock = &mt7988_clk_lock,
|
||||
};
|
||||
|
||||
static const char *const mcu_bus_div_parents[] = { "top_xtal", "ccipll2_b",
|
||||
"net1pll_d4" };
|
||||
|
||||
static const char *const mcu_arm_div_parents[] = { "top_xtal", "arm_b",
|
||||
"net1pll_d4" };
|
||||
|
||||
static struct mtk_composite mcu_muxes[] = {
|
||||
/* bus_pll_divider_cfg */
|
||||
MUX_GATE_FLAGS(CLK_MCU_BUS_DIV_SEL, "mcu_bus_div_sel",
|
||||
mcu_bus_div_parents, 0x7C0, 9, 2, -1, CLK_IS_CRITICAL),
|
||||
/* mp2_pll_divider_cfg */
|
||||
MUX_GATE_FLAGS(CLK_MCU_ARM_DIV_SEL, "mcu_arm_div_sel",
|
||||
mcu_arm_div_parents, 0x7A8, 9, 2, -1, CLK_IS_CRITICAL),
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc mcusys_desc = {
|
||||
.composite_clks = mcu_muxes,
|
||||
.num_composite_clks = ARRAY_SIZE(mcu_muxes),
|
||||
};
|
||||
|
||||
static const struct of_device_id of_match_clk_mt7988_topckgen[] = {
|
||||
{ .compatible = "mediatek,mt7988-topckgen", .data = &topck_desc },
|
||||
{ .compatible = "mediatek,mt7988-mcusys", .data = &mcusys_desc },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_topckgen);
|
||||
|
||||
static struct platform_driver clk_mt7988_topckgen_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt7988-topckgen",
|
||||
.of_match_table = of_match_clk_mt7988_topckgen,
|
||||
},
|
||||
};
|
||||
module_platform_driver(clk_mt7988_topckgen_drv);
|
||||
MODULE_LICENSE("GPL");
|
|
@ -0,0 +1,262 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
#include <linux/bitfield.h>
|
||||
#include <linux/firmware.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/nvmem-consumer.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
#include <linux/phy.h>
|
||||
|
||||
#define MEDAITEK_2P5GE_PHY_DMB_FW "mediatek/mediatek-2p5ge-phy-dmb.bin"
|
||||
#define MEDIATEK_2P5GE_PHY_PMB_FW "mediatek/mediatek-2p5ge-phy-pmb.bin"
|
||||
|
||||
#define MD32_EN_CFG 0x18
|
||||
#define MD32_EN BIT(0)
|
||||
|
||||
#define BASE100T_STATUS_EXTEND 0x10
|
||||
#define BASE1000T_STATUS_EXTEND 0x11
|
||||
#define EXTEND_CTRL_AND_STATUS 0x16
|
||||
|
||||
#define PHY_AUX_CTRL_STATUS 0x1d
|
||||
#define PHY_AUX_DPX_MASK GENMASK(5, 5)
|
||||
#define PHY_AUX_SPEED_MASK GENMASK(4, 2)
|
||||
|
||||
/* Registers on MDIO_MMD_VEND1 */
|
||||
#define MTK_PHY_LINK_STATUS_MISC 0xa2
|
||||
#define MTK_PHY_FDX_ENABLE BIT(5)
|
||||
|
||||
/* Registers on MDIO_MMD_VEND2 */
|
||||
#define MTK_PHY_LED0_ON_CTRL 0x24
|
||||
#define MTK_PHY_LED0_ON_LINK1000 BIT(0)
|
||||
#define MTK_PHY_LED0_ON_LINK100 BIT(1)
|
||||
#define MTK_PHY_LED0_ON_LINK10 BIT(2)
|
||||
#define MTK_PHY_LED0_ON_LINK2500 BIT(7)
|
||||
#define MTK_PHY_LED0_POLARITY BIT(14)
|
||||
|
||||
#define MTK_PHY_LED1_ON_CTRL 0x26
|
||||
#define MTK_PHY_LED1_ON_FDX BIT(4)
|
||||
#define MTK_PHY_LED1_ON_HDX BIT(5)
|
||||
#define MTK_PHY_LED1_POLARITY BIT(14)
|
||||
|
||||
enum {
|
||||
PHY_AUX_SPD_10 = 0,
|
||||
PHY_AUX_SPD_100,
|
||||
PHY_AUX_SPD_1000,
|
||||
PHY_AUX_SPD_2500,
|
||||
};
|
||||
|
||||
static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev)
|
||||
{
|
||||
int ret;
|
||||
int i;
|
||||
const struct firmware *fw;
|
||||
struct device *dev = &phydev->mdio.dev;
|
||||
struct device_node *np;
|
||||
void __iomem *dmb_addr;
|
||||
void __iomem *pmb_addr;
|
||||
void __iomem *mcucsr_base;
|
||||
u16 reg;
|
||||
struct pinctrl *pinctrl;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw");
|
||||
if (!np)
|
||||
return -ENOENT;
|
||||
|
||||
dmb_addr = of_iomap(np, 0);
|
||||
if (!dmb_addr)
|
||||
return -ENOMEM;
|
||||
pmb_addr = of_iomap(np, 1);
|
||||
if (!pmb_addr)
|
||||
return -ENOMEM;
|
||||
mcucsr_base = of_iomap(np, 2);
|
||||
if (!mcucsr_base)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = request_firmware(&fw, MEDAITEK_2P5GE_PHY_DMB_FW, dev);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to load firmware: %s, ret: %d\n",
|
||||
MEDAITEK_2P5GE_PHY_DMB_FW, ret);
|
||||
return ret;
|
||||
}
|
||||
for (i = 0; i < fw->size - 1; i += 4)
|
||||
writel(*((uint32_t *)(fw->data + i)), dmb_addr + i);
|
||||
release_firmware(fw);
|
||||
|
||||
ret = request_firmware(&fw, MEDIATEK_2P5GE_PHY_PMB_FW, dev);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to load firmware: %s, ret: %d\n",
|
||||
MEDIATEK_2P5GE_PHY_PMB_FW, ret);
|
||||
return ret;
|
||||
}
|
||||
for (i = 0; i < fw->size - 1; i += 4)
|
||||
writel(*((uint32_t *)(fw->data + i)), pmb_addr + i);
|
||||
release_firmware(fw);
|
||||
|
||||
reg = readw(mcucsr_base + MD32_EN_CFG);
|
||||
writew(reg | MD32_EN, mcucsr_base + MD32_EN_CFG);
|
||||
dev_dbg(dev, "Firmware loading/trigger ok.\n");
|
||||
|
||||
/* Setup LED */
|
||||
phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
|
||||
MTK_PHY_LED0_POLARITY);
|
||||
|
||||
phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
|
||||
MTK_PHY_LED0_ON_LINK10 |
|
||||
MTK_PHY_LED0_ON_LINK100 |
|
||||
MTK_PHY_LED0_ON_LINK1000 |
|
||||
MTK_PHY_LED0_ON_LINK2500);
|
||||
|
||||
phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
|
||||
MTK_PHY_LED1_ON_FDX | MTK_PHY_LED1_ON_HDX);
|
||||
|
||||
pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led");
|
||||
if (IS_ERR(pinctrl)) {
|
||||
dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n");
|
||||
return PTR_ERR(pinctrl);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev)
|
||||
{
|
||||
bool changed = false;
|
||||
u32 adv;
|
||||
int ret;
|
||||
|
||||
if (phydev->autoneg == AUTONEG_DISABLE) {
|
||||
/* Configure half duplex with genphy_setup_forced,
|
||||
* because genphy_c45_pma_setup_forced does not support.
|
||||
*/
|
||||
return phydev->duplex != DUPLEX_FULL
|
||||
? genphy_setup_forced(phydev)
|
||||
: genphy_c45_pma_setup_forced(phydev);
|
||||
}
|
||||
|
||||
ret = genphy_c45_an_config_aneg(phydev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
if (ret > 0)
|
||||
changed = true;
|
||||
|
||||
adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
|
||||
ret = phy_modify_changed(phydev, MII_CTRL1000,
|
||||
ADVERTISE_1000FULL | ADVERTISE_1000HALF,
|
||||
adv);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
if (ret > 0)
|
||||
changed = true;
|
||||
|
||||
return genphy_c45_check_and_restart_aneg(phydev, changed);
|
||||
}
|
||||
|
||||
static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = genphy_read_abilities(phydev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* We don't support HDX at MAC layer on mt798x.
|
||||
* So mask phy's HDX capabilities, too.
|
||||
*/
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
|
||||
phydev->supported);
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
|
||||
phydev->supported);
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
|
||||
phydev->supported);
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
|
||||
phydev->supported);
|
||||
linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = genphy_update_link(phydev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
phydev->speed = SPEED_UNKNOWN;
|
||||
phydev->duplex = DUPLEX_UNKNOWN;
|
||||
phydev->pause = 0;
|
||||
phydev->asym_pause = 0;
|
||||
|
||||
if (!phydev->link)
|
||||
return 0;
|
||||
|
||||
if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
|
||||
ret = genphy_c45_read_lpa(phydev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
/* Read the link partner's 1G advertisement */
|
||||
ret = phy_read(phydev, MII_STAT1000);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret);
|
||||
} else if (phydev->autoneg == AUTONEG_DISABLE) {
|
||||
linkmode_zero(phydev->lp_advertising);
|
||||
}
|
||||
|
||||
ret = phy_read(phydev, PHY_AUX_CTRL_STATUS);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
switch (FIELD_GET(PHY_AUX_SPEED_MASK, ret)) {
|
||||
case PHY_AUX_SPD_10:
|
||||
phydev->speed = SPEED_10;
|
||||
break;
|
||||
case PHY_AUX_SPD_100:
|
||||
phydev->speed = SPEED_100;
|
||||
break;
|
||||
case PHY_AUX_SPD_1000:
|
||||
phydev->speed = SPEED_1000;
|
||||
break;
|
||||
case PHY_AUX_SPD_2500:
|
||||
phydev->speed = SPEED_2500;
|
||||
phydev->duplex = DUPLEX_FULL; /* 2.5G must be FDX */
|
||||
break;
|
||||
}
|
||||
|
||||
ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LINK_STATUS_MISC);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
phydev->duplex = (ret & MTK_PHY_FDX_ENABLE) ? DUPLEX_FULL : DUPLEX_HALF;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct phy_driver mtk_gephy_driver[] = {
|
||||
{
|
||||
PHY_ID_MATCH_EXACT(0x00339c11),
|
||||
.name = "MediaTek MT798x 2.5GbE PHY",
|
||||
.config_init = mt798x_2p5ge_phy_config_init,
|
||||
.config_aneg = mt798x_2p5ge_phy_config_aneg,
|
||||
.get_features = mt798x_2p5ge_phy_get_features,
|
||||
.read_status = mt798x_2p5ge_phy_read_status,
|
||||
},
|
||||
};
|
||||
|
||||
module_phy_driver(mtk_gephy_driver);
|
||||
|
||||
static struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl[] = {
|
||||
{ PHY_ID_MATCH_VENDOR(0x00339c00) },
|
||||
{ }
|
||||
};
|
||||
|
||||
MODULE_DESCRIPTION("MediaTek 2.5Gb Ethernet PHY driver");
|
||||
MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl);
|
||||
MODULE_FIRMWARE(MEDAITEK_2P5GE_PHY_DMB_FW);
|
||||
MODULE_FIRMWARE(MEDIATEK_2P5GE_PHY_PMB_FW);
|
File diff suppressed because it is too large
Load diff
|
@ -0,0 +1,276 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (c) 2023 MediaTek Inc.
|
||||
* Author: Sam Shih <sam.shih@mediatek.com>
|
||||
* Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_MT7988_H
|
||||
#define _DT_BINDINGS_CLK_MT7988_H
|
||||
|
||||
/* APMIXEDSYS */
|
||||
|
||||
#define CLK_APMIXED_NETSYSPLL 0
|
||||
#define CLK_APMIXED_MPLL 1
|
||||
#define CLK_APMIXED_MMPLL 2
|
||||
#define CLK_APMIXED_APLL2 3
|
||||
#define CLK_APMIXED_NET1PLL 4
|
||||
#define CLK_APMIXED_NET2PLL 5
|
||||
#define CLK_APMIXED_WEDMCUPLL 6
|
||||
#define CLK_APMIXED_SGMPLL 7
|
||||
#define CLK_APMIXED_ARM_B 8
|
||||
#define CLK_APMIXED_CCIPLL2_B 9
|
||||
#define CLK_APMIXED_USXGMIIPLL 10
|
||||
#define CLK_APMIXED_MSDCPLL 11
|
||||
|
||||
/* TOPCKGEN */
|
||||
|
||||
#define CLK_TOP_XTAL 0
|
||||
#define CLK_TOP_XTAL_D2 1
|
||||
#define CLK_TOP_RTC_32K 2
|
||||
#define CLK_TOP_RTC_32P7K 3
|
||||
#define CLK_TOP_MPLL_D2 4
|
||||
#define CLK_TOP_MPLL_D3_D2 5
|
||||
#define CLK_TOP_MPLL_D4 6
|
||||
#define CLK_TOP_MPLL_D8 7
|
||||
#define CLK_TOP_MPLL_D8_D2 8
|
||||
#define CLK_TOP_MMPLL_D2 9
|
||||
#define CLK_TOP_MMPLL_D3_D5 10
|
||||
#define CLK_TOP_MMPLL_D4 11
|
||||
#define CLK_TOP_MMPLL_D6_D2 12
|
||||
#define CLK_TOP_MMPLL_D8 13
|
||||
#define CLK_TOP_APLL2_D4 14
|
||||
#define CLK_TOP_NET1PLL_D4 15
|
||||
#define CLK_TOP_NET1PLL_D5 16
|
||||
#define CLK_TOP_NET1PLL_D5_D2 17
|
||||
#define CLK_TOP_NET1PLL_D5_D4 18
|
||||
#define CLK_TOP_NET1PLL_D8 19
|
||||
#define CLK_TOP_NET1PLL_D8_D2 20
|
||||
#define CLK_TOP_NET1PLL_D8_D4 21
|
||||
#define CLK_TOP_NET1PLL_D8_D8 22
|
||||
#define CLK_TOP_NET1PLL_D8_D16 23
|
||||
#define CLK_TOP_NET2PLL_D2 24
|
||||
#define CLK_TOP_NET2PLL_D4 25
|
||||
#define CLK_TOP_NET2PLL_D4_D4 26
|
||||
#define CLK_TOP_NET2PLL_D4_D8 27
|
||||
#define CLK_TOP_NET2PLL_D6 28
|
||||
#define CLK_TOP_NET2PLL_D8 29
|
||||
#define CLK_TOP_NETSYS_SEL 30
|
||||
#define CLK_TOP_NETSYS_500M_SEL 31
|
||||
#define CLK_TOP_NETSYS_2X_SEL 32
|
||||
#define CLK_TOP_NETSYS_GSW_SEL 33
|
||||
#define CLK_TOP_ETH_GMII_SEL 34
|
||||
#define CLK_TOP_NETSYS_MCU_SEL 35
|
||||
#define CLK_TOP_NETSYS_PAO_2X_SEL 36
|
||||
#define CLK_TOP_EIP197_SEL 37
|
||||
#define CLK_TOP_AXI_INFRA_SEL 38
|
||||
#define CLK_TOP_UART_SEL 39
|
||||
#define CLK_TOP_EMMC_250M_SEL 40
|
||||
#define CLK_TOP_EMMC_400M_SEL 41
|
||||
#define CLK_TOP_SPI_SEL 42
|
||||
#define CLK_TOP_SPIM_MST_SEL 43
|
||||
#define CLK_TOP_NFI1X_SEL 44
|
||||
#define CLK_TOP_SPINFI_SEL 45
|
||||
#define CLK_TOP_PWM_SEL 46
|
||||
#define CLK_TOP_I2C_SEL 47
|
||||
#define CLK_TOP_PCIE_MBIST_250M_SEL 48
|
||||
#define CLK_TOP_PEXTP_TL_SEL 49
|
||||
#define CLK_TOP_PEXTP_TL_P1_SEL 50
|
||||
#define CLK_TOP_PEXTP_TL_P2_SEL 51
|
||||
#define CLK_TOP_PEXTP_TL_P3_SEL 52
|
||||
#define CLK_TOP_USB_SYS_SEL 53
|
||||
#define CLK_TOP_USB_SYS_P1_SEL 54
|
||||
#define CLK_TOP_USB_XHCI_SEL 55
|
||||
#define CLK_TOP_USB_XHCI_P1_SEL 56
|
||||
#define CLK_TOP_USB_FRMCNT_SEL 57
|
||||
#define CLK_TOP_USB_FRMCNT_P1_SEL 58
|
||||
#define CLK_TOP_AUD_SEL 59
|
||||
#define CLK_TOP_A1SYS_SEL 60
|
||||
#define CLK_TOP_AUD_L_SEL 61
|
||||
#define CLK_TOP_A_TUNER_SEL 62
|
||||
#define CLK_TOP_SSPXTP_SEL 63
|
||||
#define CLK_TOP_USB_PHY_SEL 64
|
||||
#define CLK_TOP_USXGMII_SBUS_0_SEL 65
|
||||
#define CLK_TOP_USXGMII_SBUS_1_SEL 66
|
||||
#define CLK_TOP_SGM_0_SEL 67
|
||||
#define CLK_TOP_SGM_SBUS_0_SEL 68
|
||||
#define CLK_TOP_SGM_1_SEL 69
|
||||
#define CLK_TOP_SGM_SBUS_1_SEL 70
|
||||
#define CLK_TOP_XFI_PHY_0_XTAL_SEL 71
|
||||
#define CLK_TOP_XFI_PHY_1_XTAL_SEL 72
|
||||
#define CLK_TOP_SYSAXI_SEL 73
|
||||
#define CLK_TOP_SYSAPB_SEL 74
|
||||
#define CLK_TOP_ETH_REFCK_50M_SEL 75
|
||||
#define CLK_TOP_ETH_SYS_200M_SEL 76
|
||||
#define CLK_TOP_ETH_SYS_SEL 77
|
||||
#define CLK_TOP_ETH_XGMII_SEL 78
|
||||
#define CLK_TOP_BUS_TOPS_SEL 79
|
||||
#define CLK_TOP_NPU_TOPS_SEL 80
|
||||
#define CLK_TOP_DRAMC_SEL 81
|
||||
#define CLK_TOP_DRAMC_MD32_SEL 82
|
||||
#define CLK_TOP_INFRA_F26M_SEL 83
|
||||
#define CLK_TOP_PEXTP_P0_SEL 84
|
||||
#define CLK_TOP_PEXTP_P1_SEL 85
|
||||
#define CLK_TOP_PEXTP_P2_SEL 86
|
||||
#define CLK_TOP_PEXTP_P3_SEL 87
|
||||
#define CLK_TOP_DA_XTP_GLB_P0_SEL 88
|
||||
#define CLK_TOP_DA_XTP_GLB_P1_SEL 89
|
||||
#define CLK_TOP_DA_XTP_GLB_P2_SEL 90
|
||||
#define CLK_TOP_DA_XTP_GLB_P3_SEL 91
|
||||
#define CLK_TOP_CKM_SEL 92
|
||||
#define CLK_TOP_DA_SEL 93
|
||||
#define CLK_TOP_PEXTP_SEL 94
|
||||
#define CLK_TOP_TOPS_P2_26M_SEL 95
|
||||
#define CLK_TOP_MCUSYS_BACKUP_625M_SEL 96
|
||||
#define CLK_TOP_NETSYS_SYNC_250M_SEL 97
|
||||
#define CLK_TOP_MACSEC_SEL 98
|
||||
#define CLK_TOP_NETSYS_TOPS_400M_SEL 99
|
||||
#define CLK_TOP_NETSYS_PPEFB_250M_SEL 100
|
||||
#define CLK_TOP_NETSYS_WARP_SEL 101
|
||||
#define CLK_TOP_ETH_MII_SEL 102
|
||||
#define CLK_TOP_NPU_SEL 103
|
||||
#define CLK_TOP_AUD_I2S_M 104
|
||||
|
||||
/* MCUSYS */
|
||||
|
||||
#define CLK_MCU_BUS_DIV_SEL 0
|
||||
#define CLK_MCU_ARM_DIV_SEL 1
|
||||
|
||||
/* INFRACFG_AO */
|
||||
|
||||
#define CLK_INFRA_MUX_UART0_SEL 0
|
||||
#define CLK_INFRA_MUX_UART1_SEL 1
|
||||
#define CLK_INFRA_MUX_UART2_SEL 2
|
||||
#define CLK_INFRA_MUX_SPI0_SEL 3
|
||||
#define CLK_INFRA_MUX_SPI1_SEL 4
|
||||
#define CLK_INFRA_MUX_SPI2_SEL 5
|
||||
#define CLK_INFRA_PWM_SEL 6
|
||||
#define CLK_INFRA_PWM_CK1_SEL 7
|
||||
#define CLK_INFRA_PWM_CK2_SEL 8
|
||||
#define CLK_INFRA_PWM_CK3_SEL 9
|
||||
#define CLK_INFRA_PWM_CK4_SEL 10
|
||||
#define CLK_INFRA_PWM_CK5_SEL 11
|
||||
#define CLK_INFRA_PWM_CK6_SEL 12
|
||||
#define CLK_INFRA_PWM_CK7_SEL 13
|
||||
#define CLK_INFRA_PWM_CK8_SEL 14
|
||||
#define CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15
|
||||
#define CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16
|
||||
#define CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17
|
||||
#define CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18
|
||||
|
||||
/* INFRACFG */
|
||||
|
||||
#define CLK_INFRA_PCIE_PERI_26M_CK_P0 19
|
||||
#define CLK_INFRA_PCIE_PERI_26M_CK_P1 20
|
||||
#define CLK_INFRA_PCIE_PERI_26M_CK_P2 21
|
||||
#define CLK_INFRA_PCIE_PERI_26M_CK_P3 22
|
||||
#define CLK_INFRA_66M_GPT_BCK 23
|
||||
#define CLK_INFRA_66M_PWM_HCK 24
|
||||
#define CLK_INFRA_66M_PWM_BCK 25
|
||||
#define CLK_INFRA_66M_PWM_CK1 26
|
||||
#define CLK_INFRA_66M_PWM_CK2 27
|
||||
#define CLK_INFRA_66M_PWM_CK3 28
|
||||
#define CLK_INFRA_66M_PWM_CK4 29
|
||||
#define CLK_INFRA_66M_PWM_CK5 30
|
||||
#define CLK_INFRA_66M_PWM_CK6 31
|
||||
#define CLK_INFRA_66M_PWM_CK7 32
|
||||
#define CLK_INFRA_66M_PWM_CK8 33
|
||||
#define CLK_INFRA_133M_CQDMA_BCK 34
|
||||
#define CLK_INFRA_66M_AUD_SLV_BCK 35
|
||||
#define CLK_INFRA_AUD_26M 36
|
||||
#define CLK_INFRA_AUD_L 37
|
||||
#define CLK_INFRA_AUD_AUD 38
|
||||
#define CLK_INFRA_AUD_EG2 39
|
||||
#define CLK_INFRA_DRAMC_F26M 40
|
||||
#define CLK_INFRA_133M_DBG_ACKM 41
|
||||
#define CLK_INFRA_66M_AP_DMA_BCK 42
|
||||
#define CLK_INFRA_66M_SEJ_BCK 43
|
||||
#define CLK_INFRA_PRE_CK_SEJ_F13M 44
|
||||
#define CLK_INFRA_26M_THERM_SYSTEM 45
|
||||
#define CLK_INFRA_I2C_BCK 46
|
||||
#define CLK_INFRA_52M_UART0_CK 47
|
||||
#define CLK_INFRA_52M_UART1_CK 48
|
||||
#define CLK_INFRA_52M_UART2_CK 49
|
||||
#define CLK_INFRA_NFI 50
|
||||
#define CLK_INFRA_SPINFI 51
|
||||
#define CLK_INFRA_66M_NFI_HCK 52
|
||||
#define CLK_INFRA_104M_SPI0 53
|
||||
#define CLK_INFRA_104M_SPI1 54
|
||||
#define CLK_INFRA_104M_SPI2_BCK 55
|
||||
#define CLK_INFRA_66M_SPI0_HCK 56
|
||||
#define CLK_INFRA_66M_SPI1_HCK 57
|
||||
#define CLK_INFRA_66M_SPI2_HCK 58
|
||||
#define CLK_INFRA_66M_FLASHIF_AXI 59
|
||||
#define CLK_INFRA_RTC 60
|
||||
#define CLK_INFRA_26M_ADC_BCK 61
|
||||
#define CLK_INFRA_RC_ADC 62
|
||||
#define CLK_INFRA_MSDC400 63
|
||||
#define CLK_INFRA_MSDC2_HCK 64
|
||||
#define CLK_INFRA_133M_MSDC_0_HCK 65
|
||||
#define CLK_INFRA_66M_MSDC_0_HCK 66
|
||||
#define CLK_INFRA_133M_CPUM_BCK 67
|
||||
#define CLK_INFRA_BIST2FPC 68
|
||||
#define CLK_INFRA_I2C_X16W_MCK_CK_P1 69
|
||||
#define CLK_INFRA_I2C_X16W_PCK_CK_P1 70
|
||||
#define CLK_INFRA_133M_USB_HCK 71
|
||||
#define CLK_INFRA_133M_USB_HCK_CK_P1 72
|
||||
#define CLK_INFRA_66M_USB_HCK 73
|
||||
#define CLK_INFRA_66M_USB_HCK_CK_P1 74
|
||||
#define CLK_INFRA_USB_SYS 75
|
||||
#define CLK_INFRA_USB_SYS_CK_P1 76
|
||||
#define CLK_INFRA_USB_REF 77
|
||||
#define CLK_INFRA_USB_CK_P1 78
|
||||
#define CLK_INFRA_USB_FRMCNT 79
|
||||
#define CLK_INFRA_USB_FRMCNT_CK_P1 80
|
||||
#define CLK_INFRA_USB_PIPE 81
|
||||
#define CLK_INFRA_USB_PIPE_CK_P1 82
|
||||
#define CLK_INFRA_USB_UTMI 83
|
||||
#define CLK_INFRA_USB_UTMI_CK_P1 84
|
||||
#define CLK_INFRA_USB_XHCI 85
|
||||
#define CLK_INFRA_USB_XHCI_CK_P1 86
|
||||
#define CLK_INFRA_PCIE_GFMUX_TL_P0 87
|
||||
#define CLK_INFRA_PCIE_GFMUX_TL_P1 88
|
||||
#define CLK_INFRA_PCIE_GFMUX_TL_P2 89
|
||||
#define CLK_INFRA_PCIE_GFMUX_TL_P3 90
|
||||
#define CLK_INFRA_PCIE_PIPE_P0 91
|
||||
#define CLK_INFRA_PCIE_PIPE_P1 92
|
||||
#define CLK_INFRA_PCIE_PIPE_P2 93
|
||||
#define CLK_INFRA_PCIE_PIPE_P3 94
|
||||
#define CLK_INFRA_133M_PCIE_CK_P0 95
|
||||
#define CLK_INFRA_133M_PCIE_CK_P1 96
|
||||
#define CLK_INFRA_133M_PCIE_CK_P2 97
|
||||
#define CLK_INFRA_133M_PCIE_CK_P3 98
|
||||
|
||||
/* ETHDMA */
|
||||
|
||||
#define CLK_ETHDMA_XGP1_EN 0
|
||||
#define CLK_ETHDMA_XGP2_EN 1
|
||||
#define CLK_ETHDMA_XGP3_EN 2
|
||||
#define CLK_ETHDMA_FE_EN 3
|
||||
#define CLK_ETHDMA_GP2_EN 4
|
||||
#define CLK_ETHDMA_GP1_EN 5
|
||||
#define CLK_ETHDMA_GP3_EN 6
|
||||
#define CLK_ETHDMA_ESW_EN 7
|
||||
#define CLK_ETHDMA_CRYPT0_EN 8
|
||||
#define CLK_ETHDMA_NR_CLK 9
|
||||
|
||||
/* SGMIISYS_0 */
|
||||
|
||||
#define CLK_SGM0_TX_EN 0
|
||||
#define CLK_SGM0_RX_EN 1
|
||||
#define CLK_SGMII0_NR_CLK 2
|
||||
|
||||
/* SGMIISYS_1 */
|
||||
|
||||
#define CLK_SGM1_TX_EN 0
|
||||
#define CLK_SGM1_RX_EN 1
|
||||
#define CLK_SGMII1_NR_CLK 2
|
||||
|
||||
/* ETHWARP */
|
||||
|
||||
#define CLK_ETHWARP_WOCPU2_EN 0
|
||||
#define CLK_ETHWARP_WOCPU1_EN 1
|
||||
#define CLK_ETHWARP_WOCPU0_EN 2
|
||||
#define CLK_ETHWARP_NR_CLK 3
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_MT7988_H */
|
|
@ -0,0 +1,40 @@
|
|||
. /lib/functions/leds.sh
|
||||
. /lib/functions/uci-defaults.sh
|
||||
|
||||
board=$(board_name)
|
||||
|
||||
board_config_update
|
||||
|
||||
case $board in
|
||||
cudy,wr3000-v1)
|
||||
ucidef_set_led_netdev "wan" "wan" "blue:wan" "wan"
|
||||
;;
|
||||
mercusys,mr90x-v1)
|
||||
ucidef_set_led_netdev "lan0" "lan0" "green:lan0" "lan0" "link tx rx"
|
||||
ucidef_set_led_netdev "lan1" "lan2" "green:lan1" "lan1" "link tx rx"
|
||||
ucidef_set_led_netdev "lan2" "lan2" "green:lan2" "lan2" "link tx rx"
|
||||
ucidef_set_led_netdev "wan" "wan" "green:wan" "eth1" "link tx rx"
|
||||
;;
|
||||
netgear,wax220)
|
||||
ucidef_set_led_netdev "eth0" "LAN" "green:lan" "eth0"
|
||||
ucidef_set_led_netdev "wlan2g" "WLAN2G" "blue:wlan2g" "phy0-ap0"
|
||||
ucidef_set_led_netdev "wlan5g" "WLAN5G" "blue:wlan5g" "phy1-ap0"
|
||||
;;
|
||||
xiaomi,mi-router-wr30u-112m-nmbm|\
|
||||
xiaomi,mi-router-wr30u-stock|\
|
||||
xiaomi,mi-router-wr30u-ubootmod)
|
||||
ucidef_set_led_netdev "wan" "wan" "blue:network" "wan"
|
||||
;;
|
||||
xiaomi,redmi-router-ax6000-stock|\
|
||||
xiaomi,redmi-router-ax6000-ubootmod)
|
||||
ucidef_set_led_netdev "wan" "wan" "rgb:network" "wan"
|
||||
;;
|
||||
z8102axx)
|
||||
ucidef_set_led_netdev "4g" "4g" "4g:status" "wwan0"
|
||||
ucidef_set_led_netdev "4g2" "4g2" "4g2:status" "wwan1"
|
||||
;;
|
||||
esac
|
||||
|
||||
board_config_flush
|
||||
|
||||
exit 0
|
499
6.6/target/linux/mediatek/filogic/config-6.6
Normal file
499
6.6/target/linux/mediatek/filogic/config-6.6
Normal file
|
@ -0,0 +1,499 @@
|
|||
CONFIG_64BIT=y
|
||||
# CONFIG_AHCI_MTK is not set
|
||||
CONFIG_AQUANTIA_PHY=y
|
||||
CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
|
||||
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
|
||||
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
|
||||
CONFIG_ARCH_KEEP_MEMBLOCK=y
|
||||
# CONFIG_ARCH_MA35 is not set
|
||||
CONFIG_ARCH_MEDIATEK=y
|
||||
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
|
||||
CONFIG_ARCH_MMAP_RND_BITS=18
|
||||
CONFIG_ARCH_MMAP_RND_BITS_MAX=24
|
||||
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
|
||||
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
|
||||
CONFIG_ARCH_NR_GPIO=0
|
||||
CONFIG_ARCH_PROC_KCORE_TEXT=y
|
||||
CONFIG_ARCH_SPARSEMEM_ENABLE=y
|
||||
CONFIG_ARCH_STACKWALK=y
|
||||
CONFIG_ARCH_SUSPEND_POSSIBLE=y
|
||||
CONFIG_ARCH_WANTS_NO_INSTR=y
|
||||
CONFIG_ARCH_WANTS_THP_SWAP=y
|
||||
CONFIG_ARM64=y
|
||||
CONFIG_ARM64_4K_PAGES=y
|
||||
CONFIG_ARM64_ERRATUM_843419=y
|
||||
# CONFIG_ARM64_ERRATUM_2645198 is not set
|
||||
# CONFIG_ARM64_ERRATUM_2966298 is not set
|
||||
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
|
||||
CONFIG_ARM64_PAGE_SHIFT=12
|
||||
CONFIG_ARM64_PA_BITS=48
|
||||
CONFIG_ARM64_PA_BITS_48=y
|
||||
CONFIG_ARM64_TAGGED_ADDR_ABI=y
|
||||
CONFIG_ARM64_VA_BITS=39
|
||||
CONFIG_ARM64_VA_BITS_39=y
|
||||
CONFIG_ARM_AMBA=y
|
||||
CONFIG_ARM_ARCH_TIMER=y
|
||||
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
|
||||
CONFIG_ARM_GIC=y
|
||||
CONFIG_ARM_GIC_V2M=y
|
||||
CONFIG_ARM_GIC_V3=y
|
||||
CONFIG_ARM_GIC_V3_ITS=y
|
||||
CONFIG_ARM_GIC_V3_ITS_PCI=y
|
||||
CONFIG_ARM_MEDIATEK_CPUFREQ=y
|
||||
CONFIG_ARM_PMU=y
|
||||
CONFIG_ARM_PSCI_FW=y
|
||||
CONFIG_ATA=y
|
||||
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_BLK_MQ_PCI=y
|
||||
CONFIG_BLK_PM=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_BSD_PROCESS_ACCT_V3=y
|
||||
# CONFIG_BT_NXPUART is not set
|
||||
CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
|
||||
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
|
||||
CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
|
||||
CONFIG_CC_NO_ARRAY_BOUNDS=y
|
||||
CONFIG_CLKSRC_MMIO=y
|
||||
CONFIG_CLONE_BACKWARDS=y
|
||||
CONFIG_CMDLINE_OVERRIDE=y
|
||||
CONFIG_COMMON_CLK=y
|
||||
CONFIG_COMMON_CLK_MEDIATEK=y
|
||||
CONFIG_COMMON_CLK_MEDIATEK_FHCTL=y
|
||||
# CONFIG_COMMON_CLK_MT2712 is not set
|
||||
# CONFIG_COMMON_CLK_MT6779 is not set
|
||||
# CONFIG_COMMON_CLK_MT6795 is not set
|
||||
# CONFIG_COMMON_CLK_MT6797 is not set
|
||||
# CONFIG_COMMON_CLK_MT7622 is not set
|
||||
CONFIG_COMMON_CLK_MT7981=y
|
||||
CONFIG_COMMON_CLK_MT7981_ETHSYS=y
|
||||
CONFIG_COMMON_CLK_MT7986=y
|
||||
CONFIG_COMMON_CLK_MT7986_ETHSYS=y
|
||||
CONFIG_COMMON_CLK_MT7988=y
|
||||
# CONFIG_COMMON_CLK_MT8173 is not set
|
||||
# CONFIG_COMMON_CLK_MT8183 is not set
|
||||
# CONFIG_COMMON_CLK_MT8186 is not set
|
||||
# CONFIG_COMMON_CLK_MT8188 is not set
|
||||
# CONFIG_COMMON_CLK_MT8195 is not set
|
||||
# CONFIG_COMMON_CLK_MT8365 is not set
|
||||
# CONFIG_COMMON_CLK_MT8516 is not set
|
||||
# CONFIG_COMMON_CLK_RK808 is not set
|
||||
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
|
||||
# CONFIG_COMPAT_32BIT_TIME is not set
|
||||
CONFIG_CONFIGFS_FS=y
|
||||
CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
|
||||
CONFIG_CONTEXT_TRACKING=y
|
||||
CONFIG_CONTEXT_TRACKING_IDLE=y
|
||||
# CONFIG_CPUFREQ_DT is not set
|
||||
# CONFIG_CPUFREQ_DT_PLATDEV is not set
|
||||
CONFIG_CPU_FREQ=y
|
||||
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
|
||||
CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
|
||||
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
|
||||
CONFIG_CPU_FREQ_GOV_COMMON=y
|
||||
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
|
||||
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
|
||||
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
|
||||
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
|
||||
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
|
||||
CONFIG_CPU_FREQ_GOV_USERSPACE=y
|
||||
CONFIG_CPU_FREQ_STAT=y
|
||||
CONFIG_CPU_LITTLE_ENDIAN=y
|
||||
CONFIG_CPU_RMAP=y
|
||||
CONFIG_CPU_THERMAL=y
|
||||
CONFIG_CRC16=y
|
||||
CONFIG_CRYPTO_AES_ARM64=y
|
||||
CONFIG_CRYPTO_AES_ARM64_CE=y
|
||||
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
|
||||
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
|
||||
CONFIG_CRYPTO_CMAC=y
|
||||
CONFIG_CRYPTO_CRC32=y
|
||||
CONFIG_CRYPTO_CRC32C=y
|
||||
CONFIG_CRYPTO_CRYPTD=y
|
||||
CONFIG_CRYPTO_DEFLATE=y
|
||||
CONFIG_CRYPTO_DRBG=y
|
||||
CONFIG_CRYPTO_DRBG_HMAC=y
|
||||
CONFIG_CRYPTO_DRBG_MENU=y
|
||||
CONFIG_CRYPTO_ECB=y
|
||||
CONFIG_CRYPTO_ECC=y
|
||||
CONFIG_CRYPTO_ECDH=y
|
||||
CONFIG_CRYPTO_GHASH_ARM64_CE=y
|
||||
CONFIG_CRYPTO_HASH_INFO=y
|
||||
CONFIG_CRYPTO_HMAC=y
|
||||
CONFIG_CRYPTO_JITTERENTROPY=y
|
||||
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
|
||||
CONFIG_CRYPTO_LIB_SHA1=y
|
||||
CONFIG_CRYPTO_LIB_SHA256=y
|
||||
CONFIG_CRYPTO_LIB_UTILS=y
|
||||
CONFIG_CRYPTO_LZO=y
|
||||
CONFIG_CRYPTO_RNG=y
|
||||
CONFIG_CRYPTO_RNG2=y
|
||||
CONFIG_CRYPTO_RNG_DEFAULT=y
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
CONFIG_CRYPTO_SHA256_ARM64=y
|
||||
CONFIG_CRYPTO_SHA2_ARM64_CE=y
|
||||
CONFIG_CRYPTO_SHA3=y
|
||||
CONFIG_CRYPTO_SHA512=y
|
||||
CONFIG_CRYPTO_ZSTD=y
|
||||
CONFIG_DCACHE_WORD_ACCESS=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_DEBUG_MISC=y
|
||||
CONFIG_DIMLIB=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_DMATEST=y
|
||||
CONFIG_DMA_DIRECT_REMAP=y
|
||||
CONFIG_DMA_ENGINE=y
|
||||
CONFIG_DMA_ENGINE_RAID=y
|
||||
CONFIG_DMA_OF=y
|
||||
CONFIG_DMA_VIRTUAL_CHANNELS=y
|
||||
CONFIG_DTC=y
|
||||
CONFIG_EDAC_SUPPORT=y
|
||||
CONFIG_EINT_MTK=y
|
||||
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_F2FS_FS=y
|
||||
CONFIG_FIT_PARTITION=y
|
||||
CONFIG_FIXED_PHY=y
|
||||
CONFIG_FIX_EARLYCON_MEM=y
|
||||
CONFIG_FRAME_POINTER=y
|
||||
CONFIG_FS_IOMAP=y
|
||||
CONFIG_FS_MBCACHE=y
|
||||
CONFIG_FWNODE_MDIO=y
|
||||
CONFIG_FW_LOADER_PAGED_BUF=y
|
||||
CONFIG_FW_LOADER_SYSFS=y
|
||||
CONFIG_GCC11_NO_ARRAY_BOUNDS=y
|
||||
CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_REGS=y
|
||||
CONFIG_GENERIC_ALLOCATOR=y
|
||||
CONFIG_GENERIC_ARCH_TOPOLOGY=y
|
||||
CONFIG_GENERIC_BUG=y
|
||||
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
|
||||
CONFIG_GENERIC_CPU_AUTOPROBE=y
|
||||
CONFIG_GENERIC_CPU_VULNERABILITIES=y
|
||||
CONFIG_GENERIC_CSUM=y
|
||||
CONFIG_GENERIC_EARLY_IOREMAP=y
|
||||
CONFIG_GENERIC_GETTIMEOFDAY=y
|
||||
CONFIG_GENERIC_IDLE_POLL_SETUP=y
|
||||
CONFIG_GENERIC_IOREMAP=y
|
||||
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
|
||||
CONFIG_GENERIC_IRQ_SHOW=y
|
||||
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
|
||||
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
|
||||
CONFIG_GENERIC_MSI_IRQ=y
|
||||
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_GENERIC_PCI_IOMAP=y
|
||||
CONFIG_GENERIC_PHY=y
|
||||
CONFIG_GENERIC_PINCONF=y
|
||||
CONFIG_GENERIC_PINCTRL_GROUPS=y
|
||||
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
|
||||
CONFIG_GENERIC_SCHED_CLOCK=y
|
||||
CONFIG_GENERIC_SMP_IDLE_THREAD=y
|
||||
CONFIG_GENERIC_STRNCPY_FROM_USER=y
|
||||
CONFIG_GENERIC_STRNLEN_USER=y
|
||||
CONFIG_GENERIC_TIME_VSYSCALL=y
|
||||
CONFIG_GLOB=y
|
||||
CONFIG_GPIO_CDEV=y
|
||||
CONFIG_GPIO_HISI=y
|
||||
CONFIG_GRO_CELLS=y
|
||||
CONFIG_HARDIRQS_SW_RESEND=y
|
||||
CONFIG_HAS_DMA=y
|
||||
CONFIG_HAS_IOMEM=y
|
||||
CONFIG_HAS_IOPORT_MAP=y
|
||||
CONFIG_HWMON=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_HW_RANDOM_MTK=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_BOARDINFO=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
# CONFIG_I2C_HISI is not set
|
||||
CONFIG_I2C_MT65XX=y
|
||||
CONFIG_ICPLUS_PHY=y
|
||||
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
|
||||
CONFIG_INITRAMFS_SOURCE=""
|
||||
# CONFIG_INPUT_RK805_PWRKEY is not set
|
||||
CONFIG_IRQCHIP=y
|
||||
CONFIG_IRQ_DOMAIN=y
|
||||
CONFIG_IRQ_DOMAIN_HIERARCHY=y
|
||||
CONFIG_IRQ_FORCED_THREADING=y
|
||||
CONFIG_IRQ_TIME_ACCOUNTING=y
|
||||
CONFIG_IRQ_WORK=y
|
||||
CONFIG_JBD2=y
|
||||
CONFIG_JUMP_LABEL=y
|
||||
# CONFIG_KEYBOARD_MT6779 is not set
|
||||
CONFIG_LIBFDT=y
|
||||
CONFIG_LOCK_DEBUGGING_SUPPORT=y
|
||||
CONFIG_LOCK_SPIN_ON_OWNER=y
|
||||
CONFIG_LZO_COMPRESS=y
|
||||
CONFIG_LZO_DECOMPRESS=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_MAXLINEAR_GPHY=y
|
||||
CONFIG_MDIO_BUS=y
|
||||
CONFIG_MDIO_DEVICE=y
|
||||
CONFIG_MDIO_DEVRES=y
|
||||
CONFIG_MEDIATEK_2P5G_PHY=y
|
||||
CONFIG_MEDIATEK_GE_PHY=y
|
||||
CONFIG_MEDIATEK_GE_SOC_PHY=y
|
||||
CONFIG_MEDIATEK_WATCHDOG=y
|
||||
CONFIG_MEMFD_CREATE=y
|
||||
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
|
||||
CONFIG_MFD_SYSCON=y
|
||||
CONFIG_MFD_RK8XX_I2C=y
|
||||
CONFIG_MFD_RK8XX_SPI=y
|
||||
CONFIG_MIGRATION=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_BLOCK=y
|
||||
CONFIG_MMC_CQHCI=y
|
||||
CONFIG_MMC_MTK=y
|
||||
CONFIG_MODULES_TREE_LOOKUP=y
|
||||
CONFIG_MODULES_USE_ELF_RELA=y
|
||||
CONFIG_MTD_NAND_CORE=y
|
||||
CONFIG_MTD_NAND_ECC=y
|
||||
CONFIG_MTD_NAND_ECC_MEDIATEK=y
|
||||
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
|
||||
CONFIG_MTD_NAND_MTK=y
|
||||
CONFIG_MTD_NAND_MTK_BMT=y
|
||||
CONFIG_MTD_PARSER_TRX=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_MTD_SPI_NAND=y
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_MTD_SPLIT_FIRMWARE=y
|
||||
CONFIG_MTD_SPLIT_FIT_FW=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_BEB_LIMIT=20
|
||||
CONFIG_MTD_UBI_BLOCK=y
|
||||
CONFIG_MTD_UBI_FASTMAP=y
|
||||
CONFIG_MTD_UBI_WL_THRESHOLD=4096
|
||||
# CONFIG_MTK_CMDQ is not set
|
||||
# CONFIG_MTK_CQDMA is not set
|
||||
CONFIG_MTK_HSDMA=y
|
||||
CONFIG_MTK_INFRACFG=y
|
||||
CONFIG_MTK_LVTS_THERMAL=y
|
||||
# CONFIG_MTK_LVTS_THERMAL_DEBUGFS is not set
|
||||
CONFIG_MTK_PMIC_WRAP=y
|
||||
CONFIG_MTK_SCPSYS=y
|
||||
CONFIG_MTK_SCPSYS_PM_DOMAINS=y
|
||||
CONFIG_MTK_SOC_THERMAL=y
|
||||
# CONFIG_MTK_SVS is not set
|
||||
CONFIG_MTK_THERMAL=y
|
||||
CONFIG_MTK_TIMER=y
|
||||
# CONFIG_MTK_UART_APDMA is not set
|
||||
CONFIG_MUTEX_SPIN_ON_OWNER=y
|
||||
CONFIG_NEED_DMA_MAP_STATE=y
|
||||
CONFIG_NEED_SG_DMA_LENGTH=y
|
||||
CONFIG_NET_DEVLINK=y
|
||||
CONFIG_NET_DSA=y
|
||||
# CONFIG_NET_DSA_MSCC_OCELOT_EXT is not set
|
||||
CONFIG_NET_DSA_MT7530=y
|
||||
CONFIG_NET_DSA_MT7530_MDIO=y
|
||||
CONFIG_NET_DSA_MT7530_MMIO=y
|
||||
CONFIG_NET_DSA_TAG_MTK=y
|
||||
CONFIG_NET_DSA_TAG_NONE=y
|
||||
CONFIG_NET_FLOW_LIMIT=y
|
||||
CONFIG_NET_MEDIATEK_SOC=y
|
||||
CONFIG_NET_MEDIATEK_SOC_USXGMII=y
|
||||
CONFIG_NET_MEDIATEK_SOC_WED=y
|
||||
CONFIG_NET_SELFTESTS=y
|
||||
CONFIG_NET_SWITCHDEV=y
|
||||
CONFIG_NET_VENDOR_MEDIATEK=y
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NO_HZ_COMMON=y
|
||||
CONFIG_NO_HZ_IDLE=y
|
||||
CONFIG_NR_CPUS=4
|
||||
CONFIG_NVMEM=y
|
||||
CONFIG_NVMEM_MTK_EFUSE=y
|
||||
CONFIG_NVMEM_SYSFS=y
|
||||
CONFIG_OF=y
|
||||
CONFIG_OF_ADDRESS=y
|
||||
CONFIG_OF_DYNAMIC=y
|
||||
CONFIG_OF_EARLY_FLATTREE=y
|
||||
CONFIG_OF_FLATTREE=y
|
||||
CONFIG_OF_GPIO=y
|
||||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_KOBJ=y
|
||||
CONFIG_OF_MDIO=y
|
||||
CONFIG_OF_OVERLAY=y
|
||||
CONFIG_OF_RESOLVE=y
|
||||
CONFIG_PADATA=y
|
||||
CONFIG_PAGE_POOL=y
|
||||
CONFIG_PAGE_POOL_STATS=y
|
||||
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
|
||||
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
|
||||
CONFIG_PARTITION_PERCPU=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCIEAER=y
|
||||
CONFIG_PCIEASPM=y
|
||||
# CONFIG_PCIEASPM_DEFAULT is not set
|
||||
CONFIG_PCIEASPM_PERFORMANCE=y
|
||||
# CONFIG_PCIEASPM_POWERSAVE is not set
|
||||
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
# CONFIG_PCIE_MEDIATEK is not set
|
||||
CONFIG_PCIE_MEDIATEK_GEN3=y
|
||||
CONFIG_PCIE_PME=y
|
||||
CONFIG_PCI_DEBUG=y
|
||||
CONFIG_PCI_DOMAINS=y
|
||||
CONFIG_PCI_DOMAINS_GENERIC=y
|
||||
# CONFIG_PCI_DYNAMIC_OF_NODES is not set
|
||||
CONFIG_PCI_MSI=y
|
||||
CONFIG_PCI_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_PCS_MTK_LYNXI=y
|
||||
CONFIG_PERF_EVENTS=y
|
||||
CONFIG_PGTABLE_LEVELS=3
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHYLIB_LEDS=y
|
||||
CONFIG_PHYLINK=y
|
||||
CONFIG_PHYS_ADDR_T_64BIT=y
|
||||
# CONFIG_PHY_MTK_DP is not set
|
||||
# CONFIG_PHY_MTK_PCIE is not set
|
||||
CONFIG_PHY_MTK_TPHY=y
|
||||
# CONFIG_PHY_MTK_UFS is not set
|
||||
CONFIG_PHY_MTK_XSPHY=y
|
||||
CONFIG_PINCTRL=y
|
||||
# CONFIG_PINCTRL_MT2712 is not set
|
||||
# CONFIG_PINCTRL_MT6765 is not set
|
||||
# CONFIG_PINCTRL_MT6795 is not set
|
||||
# CONFIG_PINCTRL_MT6797 is not set
|
||||
# CONFIG_PINCTRL_MT7622 is not set
|
||||
CONFIG_PINCTRL_MT7981=y
|
||||
CONFIG_PINCTRL_MT7986=y
|
||||
CONFIG_PINCTRL_MT7988=y
|
||||
# CONFIG_PINCTRL_MT8173 is not set
|
||||
# CONFIG_PINCTRL_MT8183 is not set
|
||||
# CONFIG_PINCTRL_MT8186 is not set
|
||||
# CONFIG_PINCTRL_MT8188 is not set
|
||||
# CONFIG_PINCTRL_MT8516 is not set
|
||||
CONFIG_PINCTRL_MTK_MOORE=y
|
||||
CONFIG_PINCTRL_MTK_V2=y
|
||||
# CONFIG_PINCTRL_RK805 is not set
|
||||
# CONFIG_PINCTRL_SINGLE is not set
|
||||
CONFIG_PM=y
|
||||
CONFIG_PM_CLK=y
|
||||
CONFIG_PM_GENERIC_DOMAINS=y
|
||||
CONFIG_PM_GENERIC_DOMAINS_OF=y
|
||||
CONFIG_PM_OPP=y
|
||||
CONFIG_POLYNOMIAL=y
|
||||
CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_RESET_SYSCON=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_PREEMPT_NONE_BUILD=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_PSTORE=y
|
||||
CONFIG_PSTORE_COMPRESS=y
|
||||
CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
|
||||
CONFIG_PSTORE_CONSOLE=y
|
||||
CONFIG_PSTORE_DEFLATE_COMPRESS=y
|
||||
CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y
|
||||
CONFIG_PSTORE_PMSG=y
|
||||
CONFIG_PSTORE_RAM=y
|
||||
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
|
||||
CONFIG_PWM=y
|
||||
CONFIG_PWM_MEDIATEK=y
|
||||
# CONFIG_PWM_MTK_DISP is not set
|
||||
CONFIG_PWM_SYSFS=y
|
||||
CONFIG_QUEUED_RWLOCKS=y
|
||||
CONFIG_QUEUED_SPINLOCKS=y
|
||||
CONFIG_RANDSTRUCT_NONE=y
|
||||
CONFIG_RAS=y
|
||||
CONFIG_RATIONAL=y
|
||||
# CONFIG_RAVE_SP_CORE is not set
|
||||
CONFIG_REALTEK_PHY=y
|
||||
CONFIG_REED_SOLOMON=y
|
||||
CONFIG_REED_SOLOMON_DEC8=y
|
||||
CONFIG_REED_SOLOMON_ENC8=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_REGMAP_I2C=y
|
||||
CONFIG_REGMAP_MMIO=y
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_REGULATOR_MT6380=y
|
||||
# CONFIG_REGULATOR_RK808 is not set
|
||||
CONFIG_REGULATOR_RT5190A=y
|
||||
CONFIG_RESET_CONTROLLER=y
|
||||
CONFIG_RESET_TI_SYSCON=y
|
||||
CONFIG_RFS_ACCEL=y
|
||||
# CONFIG_ROCKCHIP_ERRATUM_3588001 is not set
|
||||
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
|
||||
CONFIG_RPS=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
# CONFIG_RTC_DRV_RK808 is not set
|
||||
CONFIG_RTC_DRV_MT7622=y
|
||||
CONFIG_RTC_I2C_AND_SPI=y
|
||||
# CONFIG_RTL8367S_GSW is not set
|
||||
CONFIG_RWSEM_SPIN_ON_OWNER=y
|
||||
CONFIG_SCHED_MC=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SCSI_COMMON=y
|
||||
# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
|
||||
CONFIG_SERIAL_8250_FSL=y
|
||||
CONFIG_SERIAL_8250_MT6577=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=3
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=3
|
||||
CONFIG_SERIAL_DEV_BUS=y
|
||||
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
|
||||
# CONFIG_SERIAL_EARLYCON_SEMIHOST is not set
|
||||
CONFIG_SERIAL_MCTRL_GPIO=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
CONFIG_SGL_ALLOC=y
|
||||
CONFIG_SG_POOL=y
|
||||
CONFIG_SMP=y
|
||||
# CONFIG_SPI_SN_F_OSPI is not set
|
||||
CONFIG_SOCK_RX_QUEUE_MAPPING=y
|
||||
CONFIG_SOFTIRQ_ON_OWN_STACK=y
|
||||
CONFIG_SPARSEMEM=y
|
||||
CONFIG_SPARSEMEM_EXTREME=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_DYNAMIC=y
|
||||
CONFIG_SPI_MASTER=y
|
||||
CONFIG_SPI_MEM=y
|
||||
CONFIG_SPI_MT65XX=y
|
||||
# CONFIG_SPI_MTK_NOR is not set
|
||||
CONFIG_SPI_MTK_SNFI=y
|
||||
# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
|
||||
CONFIG_SQUASHFS_DECOMP_SINGLE=y
|
||||
CONFIG_SRCU=y
|
||||
CONFIG_SWIOTLB=y
|
||||
CONFIG_SWPHY=y
|
||||
CONFIG_SYSCTL_EXCEPTION_TRACE=y
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
|
||||
CONFIG_THERMAL_GOV_BANG_BANG=y
|
||||
CONFIG_THERMAL_GOV_FAIR_SHARE=y
|
||||
CONFIG_THERMAL_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_GOV_USER_SPACE=y
|
||||
CONFIG_THERMAL_HWMON=y
|
||||
CONFIG_THERMAL_OF=y
|
||||
CONFIG_THERMAL_WRITABLE_TRIPS=y
|
||||
CONFIG_THREAD_INFO_IN_TASK=y
|
||||
CONFIG_TICK_CPU_ACCOUNTING=y
|
||||
CONFIG_TIMER_OF=y
|
||||
CONFIG_TIMER_PROBE=y
|
||||
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
|
||||
CONFIG_TREE_RCU=y
|
||||
CONFIG_TREE_SRCU=y
|
||||
CONFIG_UBIFS_FS=y
|
||||
# CONFIG_UCLAMP_TASK is not set
|
||||
# CONFIG_UNMAP_KERNEL_AT_EL0 is not set
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_VMAP_STACK=y
|
||||
CONFIG_WATCHDOG_CORE=y
|
||||
CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC=y
|
||||
CONFIG_WATCHDOG_PRETIMEOUT_GOV=y
|
||||
# CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP is not set
|
||||
CONFIG_WATCHDOG_PRETIMEOUT_GOV_PANIC=y
|
||||
CONFIG_WATCHDOG_PRETIMEOUT_GOV_SEL=m
|
||||
CONFIG_WATCHDOG_SYSFS=y
|
||||
CONFIG_XPS=y
|
||||
CONFIG_XXHASH=y
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
CONFIG_ZONE_DMA32=y
|
||||
CONFIG_ZSTD_COMMON=y
|
||||
CONFIG_ZSTD_COMPRESS=y
|
||||
CONFIG_ZSTD_DECOMPRESS=y
|
711
6.6/target/linux/mediatek/image/filogic.mk
Normal file
711
6.6/target/linux/mediatek/image/filogic.mk
Normal file
|
@ -0,0 +1,711 @@
|
|||
DTS_DIR := $(DTS_DIR)/mediatek
|
||||
|
||||
define Image/Prepare
|
||||
# For UBI we want only one extra block
|
||||
rm -f $(KDIR)/ubi_mark
|
||||
echo -ne '\xde\xad\xc0\xde' > $(KDIR)/ubi_mark
|
||||
endef
|
||||
|
||||
define Build/mt7981-bl2
|
||||
cat $(STAGING_DIR_IMAGE)/mt7981-$1-bl2.img >> $@
|
||||
endef
|
||||
|
||||
define Build/mt7981-bl31-uboot
|
||||
cat $(STAGING_DIR_IMAGE)/mt7981_$1-u-boot.fip >> $@
|
||||
endef
|
||||
|
||||
define Build/mt7986-bl2
|
||||
cat $(STAGING_DIR_IMAGE)/mt7986-$1-bl2.img >> $@
|
||||
endef
|
||||
|
||||
define Build/mt7986-bl31-uboot
|
||||
cat $(STAGING_DIR_IMAGE)/mt7986_$1-u-boot.fip >> $@
|
||||
endef
|
||||
|
||||
define Build/mt7988-bl2
|
||||
cat $(STAGING_DIR_IMAGE)/mt7988-$1-bl2.img >> $@
|
||||
endef
|
||||
|
||||
define Build/mt7988-bl31-uboot
|
||||
cat $(STAGING_DIR_IMAGE)/mt7988_$1-u-boot.fip >> $@
|
||||
endef
|
||||
|
||||
define Build/mt798x-gpt
|
||||
cp $@ $@.tmp 2>/dev/null || true
|
||||
ptgen -g -o $@.tmp -a 1 -l 1024 \
|
||||
$(if $(findstring sdmmc,$1), \
|
||||
-H \
|
||||
-t 0x83 -N bl2 -r -p 4079k@17k \
|
||||
) \
|
||||
-t 0x83 -N ubootenv -r -p 512k@4M \
|
||||
-t 0x83 -N factory -r -p 2M@4608k \
|
||||
-t 0xef -N fip -r -p 4M@6656k \
|
||||
-N recovery -r -p 32M@12M \
|
||||
$(if $(findstring sdmmc,$1), \
|
||||
-N install -r -p 20M@44M \
|
||||
-t 0x2e -N production -p $(CONFIG_TARGET_ROOTFS_PARTSIZE)M@64M \
|
||||
) \
|
||||
$(if $(findstring emmc,$1), \
|
||||
-t 0x2e -N production -p $(CONFIG_TARGET_ROOTFS_PARTSIZE)M@64M \
|
||||
)
|
||||
cat $@.tmp >> $@
|
||||
rm $@.tmp
|
||||
endef
|
||||
|
||||
metadata_gl_json = \
|
||||
'{ $(if $(IMAGE_METADATA),$(IMAGE_METADATA)$(comma)) \
|
||||
"metadata_version": "1.1", \
|
||||
"compat_version": "$(call json_quote,$(compat_version))", \
|
||||
$(if $(DEVICE_COMPAT_MESSAGE),"compat_message": "$(call json_quote,$(DEVICE_COMPAT_MESSAGE))"$(comma)) \
|
||||
$(if $(filter-out 1.0,$(compat_version)),"new_supported_devices": \
|
||||
[$(call metadata_devices,$(SUPPORTED_DEVICES))]$(comma) \
|
||||
"supported_devices": ["$(call json_quote,$(legacy_supported_message))"]$(comma)) \
|
||||
$(if $(filter 1.0,$(compat_version)),"supported_devices":[$(call metadata_devices,$(SUPPORTED_DEVICES))]$(comma)) \
|
||||
"version": { \
|
||||
"release": "$(call json_quote,$(VERSION_NUMBER))", \
|
||||
"date": "$(shell TZ='Asia/Chongqing' date '+%Y%m%d%H%M%S')", \
|
||||
"dist": "$(call json_quote,$(VERSION_DIST))", \
|
||||
"version": "$(call json_quote,$(VERSION_NUMBER))", \
|
||||
"revision": "$(call json_quote,$(REVISION))", \
|
||||
"target": "$(call json_quote,$(TARGETID))", \
|
||||
"board": "$(call json_quote,$(if $(BOARD_NAME),$(BOARD_NAME),$(DEVICE_NAME)))" \
|
||||
} \
|
||||
}'
|
||||
|
||||
define Build/append-gl-metadata
|
||||
$(if $(SUPPORTED_DEVICES),-echo $(call metadata_gl_json,$(SUPPORTED_DEVICES)) | fwtool -I - $@)
|
||||
sha256sum "$@" | cut -d" " -f1 > "$@.sha256sum"
|
||||
[ ! -s "$(BUILD_KEY)" -o ! -s "$(BUILD_KEY).ucert" -o ! -s "$@" ] || { \
|
||||
cp "$(BUILD_KEY).ucert" "$@.ucert" ;\
|
||||
usign -S -m "$@" -s "$(BUILD_KEY)" -x "$@.sig" ;\
|
||||
ucert -A -c "$@.ucert" -x "$@.sig" ;\
|
||||
fwtool -S "$@.ucert" "$@" ;\
|
||||
}
|
||||
endef
|
||||
|
||||
define Build/zyxel-nwa-fit-filogic
|
||||
$(TOPDIR)/scripts/mkits-zyxel-fit-filogic.sh \
|
||||
$@.its $@ "80 e1 ff ff ff ff ff ff ff ff"
|
||||
PATH=$(LINUX_DIR)/scripts/dtc:$(PATH) mkimage -f $@.its $@.new
|
||||
@mv $@.new $@
|
||||
endef
|
||||
|
||||
define Build/cetron-header
|
||||
$(eval magic=$(word 1,$(1)))
|
||||
$(eval model=$(word 2,$(1)))
|
||||
( \
|
||||
dd if=/dev/zero bs=856 count=1 2>/dev/null; \
|
||||
printf "$(model)," | dd bs=128 count=1 conv=sync 2>/dev/null; \
|
||||
md5sum $@ | cut -f1 -d" " | dd bs=32 count=1 2>/dev/null; \
|
||||
printf "$(magic)" | dd bs=4 count=1 conv=sync 2>/dev/null; \
|
||||
cat $@; \
|
||||
) > $@.tmp
|
||||
fw_crc=$$(gzip -c $@.tmp | tail -c 8 | od -An -N4 -tx4 --endian little | tr -d ' \n'); \
|
||||
printf "$$(echo $$fw_crc | sed 's/../\\x&/g')" | cat - $@.tmp > $@
|
||||
rm $@.tmp
|
||||
endef
|
||||
|
||||
define Device/asus_tuf-ax4200
|
||||
DEVICE_VENDOR := ASUS
|
||||
DEVICE_MODEL := TUF-AX4200
|
||||
DEVICE_DTS := mt7986a-asus-tuf-ax4200
|
||||
DEVICE_DTS_DIR := ../dts
|
||||
DEVICE_DTS_LOADADDR := 0x47000000
|
||||
DEVICE_PACKAGES := kmod-usb3 kmod-mt7986-firmware mt7986-wo-firmware
|
||||
IMAGES := sysupgrade.bin
|
||||
KERNEL := kernel-bin | lzma | \
|
||||
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
|
||||
KERNEL_INITRAMFS := kernel-bin | lzma | \
|
||||
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
|
||||
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
|
||||
endef
|
||||
TARGET_DEVICES += asus_tuf-ax4200
|
||||
|
||||
define Device/acer_predator-w6
|
||||
DEVICE_VENDOR := Acer
|
||||
DEVICE_MODEL := Predator W6
|
||||
DEVICE_DTS := mt7986a-acer-predator-w6
|
||||
DEVICE_DTS_DIR := ../dts
|
||||
DEVICE_DTS_LOADADDR := 0x47000000
|
||||
DEVICE_PACKAGES := kmod-usb3 kmod-mt7986-firmware kmod-mt7916-firmware mt7986-wo-firmware e2fsprogs f2fsck mkf2fs
|
||||
IMAGES := sysupgrade.bin
|
||||
KERNEL := kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
|
||||
KERNEL_INITRAMFS := kernel-bin | lzma | \
|
||||
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
|
||||
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
|
||||
endef
|
||||
TARGET_DEVICES += acer_predator-w6
|
||||
|
||||
define Device/bananapi_bpi-r3
|
||||
DEVICE_VENDOR := Bananapi
|
||||
DEVICE_MODEL := BPi-R3
|
||||
DEVICE_DTS := mt7986a-bananapi-bpi-r3
|
||||
DEVICE_DTS_CONFIG := config-mt7986a-bananapi-bpi-r3
|
||||
DEVICE_DTS_OVERLAY:= mt7986a-bananapi-bpi-r3-emmc mt7986a-bananapi-bpi-r3-nand mt7986a-bananapi-bpi-r3-nor mt7986a-bananapi-bpi-r3-sd
|
||||
DEVICE_DTS_DIR := $(DTS_DIR)/
|
||||
DEVICE_DTS_LOADADDR := 0x43f00000
|
||||
DEVICE_PACKAGES := kmod-hwmon-pwmfan kmod-i2c-gpio kmod-mt7986-firmware kmod-sfp kmod-usb3 e2fsprogs f2fsck mkf2fs mt7986-wo-firmware
|
||||
IMAGES := sysupgrade.itb
|
||||
KERNEL_LOADADDR := 0x44000000
|
||||
KERNEL_INITRAMFS_SUFFIX := -recovery.itb
|
||||
ARTIFACTS := \
|
||||
emmc-preloader.bin emmc-bl31-uboot.fip \
|
||||
nor-preloader.bin nor-bl31-uboot.fip \
|
||||
sdcard.img.gz \
|
||||
snand-preloader.bin snand-bl31-uboot.fip
|
||||
ARTIFACT/emmc-preloader.bin := mt7986-bl2 emmc-ddr4
|
||||
ARTIFACT/emmc-bl31-uboot.fip := mt7986-bl31-uboot bananapi_bpi-r3-emmc
|
||||
ARTIFACT/nor-preloader.bin := mt7986-bl2 nor-ddr4
|
||||
ARTIFACT/nor-bl31-uboot.fip := mt7986-bl31-uboot bananapi_bpi-r3-nor
|
||||
ARTIFACT/snand-preloader.bin := mt7986-bl2 spim-nand-ddr4
|
||||
ARTIFACT/snand-bl31-uboot.fip := mt7986-bl31-uboot bananapi_bpi-r3-snand
|
||||
ARTIFACT/sdcard.img.gz := mt798x-gpt sdmmc |\
|
||||
pad-to 17k | mt7986-bl2 sdmmc-ddr4 |\
|
||||
pad-to 6656k | mt7986-bl31-uboot bananapi_bpi-r3-sdmmc |\
|
||||
$(if $(CONFIG_TARGET_ROOTFS_INITRAMFS),\
|
||||
pad-to 12M | append-image-stage initramfs-recovery.itb | check-size 44m |\
|
||||
) \
|
||||
pad-to 44M | mt7986-bl2 spim-nand-ddr4 |\
|
||||
pad-to 45M | mt7986-bl31-uboot bananapi_bpi-r3-snand |\
|
||||
pad-to 49M | mt7986-bl2 nor-ddr4 |\
|
||||
pad-to 50M | mt7986-bl31-uboot bananapi_bpi-r3-nor |\
|
||||
pad-to 51M | mt7986-bl2 emmc-ddr4 |\
|
||||
pad-to 52M | mt7986-bl31-uboot bananapi_bpi-r3-emmc |\
|
||||
pad-to 56M | mt798x-gpt emmc |\
|
||||
$(if $(CONFIG_TARGET_ROOTFS_SQUASHFS),\
|
||||
pad-to 64M | append-image squashfs-sysupgrade.itb | check-size |\
|
||||
) \
|
||||
gzip
|
||||
IMAGE_SIZE := $$(shell expr 64 + $$(CONFIG_TARGET_ROOTFS_PARTSIZE))m
|
||||
KERNEL := kernel-bin | gzip
|
||||
KERNEL_INITRAMFS := kernel-bin | lzma | \
|
||||
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
|
||||
IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | pad-rootfs | append-metadata
|
||||
DEVICE_DTC_FLAGS := --pad 4096
|
||||
DEVICE_COMPAT_VERSION := 1.1
|
||||
DEVICE_COMPAT_MESSAGE := Device tree overlay mechanism needs bootloader update
|
||||
endef
|
||||
TARGET_DEVICES += bananapi_bpi-r3
|
||||
|
||||
define Device/cetron_ct3003
|
||||
DEVICE_VENDOR := Cetron
|
||||
DEVICE_MODEL := CT3003
|
||||
DEVICE_DTS := mt7981b-cetron-ct3003
|
||||
DEVICE_DTS_DIR := ../dts
|
||||
SUPPORTED_DEVICES += mediatek,mt7981-spim-snand-rfb
|
||||
DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
|
||||
UBINIZE_OPTS := -E 5
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
KERNEL_IN_UBI := 1
|
||||
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
|
||||
IMAGES += factory.bin
|
||||
IMAGE/factory.bin := $$(IMAGE/sysupgrade.bin) | cetron-header rd30 CT3003
|
||||
endef
|
||||
TARGET_DEVICES += cetron_ct3003
|
||||
|
||||
define Device/cudy_wr3000-v1
|
||||
DEVICE_VENDOR := Cudy
|
||||
DEVICE_MODEL := WR3000
|
||||
DEVICE_VARIANT := v1
|
||||
DEVICE_DTS := mt7981b-cudy-wr3000-v1
|
||||
DEVICE_DTS_DIR := ../dts
|
||||
DEVICE_DTS_LOADADDR := 0x47000000
|
||||
IMAGES := sysupgrade.bin
|
||||
IMAGE_SIZE := 15424k
|
||||
SUPPORTED_DEVICES += R31
|
||||
KERNEL := kernel-bin | lzma | \
|
||||
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
|
||||
KERNEL_INITRAMFS := kernel-bin | lzma | \
|
||||
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
|
||||
IMAGE/sysupgrade.bin := append-kernel | pad-to 128k | append-rootfs | pad-rootfs | check-size | append-metadata
|
||||
DEVICE_PACKAGES := kmod-mt7981-firmware
|
||||
endef
|
||||
TARGET_DEVICES += cudy_wr3000-v1
|
||||
|
||||
define Device/glinet_gl-mt3000
|
||||
DEVICE_VENDOR := GL.iNet
|
||||
DEVICE_MODEL := GL-MT3000
|
||||
DEVICE_DTS := mt7981b-glinet-gl-mt3000
|
||||
DEVICE_DTS_DIR := ../dts
|
||||
SUPPORTED_DEVICES += glinet,mt3000-snand
|
||||
DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware kmod-hwmon-pwmfan kmod-usb3
|
||||
UBINIZE_OPTS := -E 5
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
IMAGE_SIZE := 246272k
|
||||
KERNEL_IN_UBI := 1
|
||||
IMAGE/sysupgrade.bin := sysupgrade-tar | append-gl-metadata
|
||||
endef
|
||||
TARGET_DEVICES += glinet_gl-mt3000
|
||||
|
||||
define Device/h3c_magic-nx30-pro
|
||||
DEVICE_VENDOR := H3C
|
||||
DEVICE_MODEL := Magic NX30 Pro
|
||||
DEVICE_DTS := mt7981b-h3c-magic-nx30-pro
|
||||
DEVICE_DTS_DIR := ../dts
|
||||
UBINIZE_OPTS := -E 5
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
KERNEL_IN_UBI := 1
|
||||
UBOOTENV_IN_UBI := 1
|
||||
IMAGE_SIZE := 65536k
|
||||
IMAGES := sysupgrade.itb
|
||||
KERNEL_INITRAMFS_SUFFIX := -recovery.itb
|
||||
KERNEL := kernel-bin | gzip
|
||||
KERNEL_INITRAMFS := kernel-bin | lzma | \
|
||||
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
|
||||
IMAGE/sysupgrade.itb := append-kernel | \
|
||||
fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata
|
||||
DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
|
||||
ARTIFACTS := preloader.bin bl31-uboot.fip
|
||||
ARTIFACT/preloader.bin := mt7981-bl2 spim-nand-ddr3
|
||||
ARTIFACT/bl31-uboot.fip := mt7981-bl31-uboot h3c_magic-nx30-pro
|
||||
endef
|
||||
TARGET_DEVICES += h3c_magic-nx30-pro
|
||||
|
||||
define Device/netgear_wax220
|
||||
DEVICE_VENDOR := NETGEAR
|
||||
DEVICE_MODEL := WAX220
|
||||
DEVICE_DTS := mt7986b-netgear-wax220
|
||||
DEVICE_DTS_DIR := ../dts
|
||||
NETGEAR_ENC_MODEL := WAX220
|
||||
NETGEAR_ENC_REGION := US
|
||||
DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware
|
||||
KERNEL_INITRAMFS_SUFFIX := -recovery.itb
|
||||
IMAGE_SIZE := 32768k
|
||||
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
|
||||
IMAGES += factory.img
|
||||
# Padding to 10M seems to be required by OEM web interface
|
||||
IMAGE/factory.img := sysupgrade-tar | \
|
||||
pad-to 10M | check-size | netgear-encrypted-factory
|
||||
endef
|
||||
TARGET_DEVICES += netgear_wax220
|
||||
|
||||
define Device/mediatek_mt7981-rfb
|
||||
DEVICE_VENDOR := MediaTek
|
||||
DEVICE_MODEL := MT7981 rfb
|
||||
DEVICE_DTS := mt7981-rfb
|
||||
DEVICE_DTS_OVERLAY:= \
|
||||
mt7981-rfb-spim-nand \
|
||||
mt7981-rfb-mxl-2p5g-phy-eth1 \
|
||||
mt7981-rfb-mxl-2p5g-phy-swp5
|
||||
DEVICE_DTS_DIR := $(DTS_DIR)/
|
||||
DEVICE_DTC_FLAGS := --pad 4096
|
||||
DEVICE_DTS_LOADADDR := 0x43f00000
|
||||
DEVICE_PACKAGES := kmod-mt7981-firmware kmod-usb3 e2fsprogs f2fsck mkf2fs mt7981-wo-firmware
|
||||
KERNEL_LOADADDR := 0x44000000
|
||||
KERNEL := kernel-bin | gzip
|
||||
KERNEL_INITRAMFS := kernel-bin | lzma | \
|
||||
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
|
||||
KERNEL_INITRAMFS_SUFFIX := .itb
|
||||
KERNEL_IN_UBI := 1
|
||||
UBOOTENV_IN_UBI := 1
|
||||
IMAGES := sysupgrade.itb
|
||||
IMAGE_SIZE := $$(shell expr 64 + $$(CONFIG_TARGET_ROOTFS_PARTSIZE))m
|
||||
IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-with-rootfs | pad-rootfs | append-metadata
|
||||
ARTIFACTS := \
|
||||
emmc-preloader.bin emmc-bl31-uboot.fip \
|
||||
nor-preloader.bin nor-bl31-uboot.fip \
|
||||
sdcard.img.gz \
|
||||
snfi-nand-preloader.bin snfi-nand-bl31-uboot.fip \
|
||||
spim-nand-preloader.bin spim-nand-bl31-uboot.fip
|
||||
ARTIFACT/emmc-preloader.bin := mt7981-bl2 emmc-ddr3
|
||||
ARTIFACT/emmc-bl31-uboot.fip := mt7981-bl31-uboot rfb-emmc
|
||||
ARTIFACT/nor-preloader.bin := mt7981-bl2 nor-ddr3
|
||||
ARTIFACT/nor-bl31-uboot.fip := mt7981-bl31-uboot rfb-emmc
|
||||
ARTIFACT/snfi-nand-preloader.bin := mt7981-bl2 snand-ddr3
|
||||
ARTIFACT/snfi-nand-bl31-uboot.fip := mt7981-bl31-uboot rfb-snfi
|
||||
ARTIFACT/spim-nand-preloader.bin := mt7981-bl2 spim-nand-ddr3
|
||||
ARTIFACT/spim-nand-bl31-uboot.fip := mt7981-bl31-uboot rfb-spim-nand
|
||||
ARTIFACT/sdcard.img.gz := mt798x-gpt sdmmc |\
|
||||
pad-to 17k | mt7981-bl2 sdmmc-ddr3 |\
|
||||
pad-to 6656k | mt7981-bl31-uboot rfb-sd |\
|
||||
$(if $(CONFIG_TARGET_ROOTFS_INITRAMFS),\
|
||||
pad-to 12M | append-image-stage initramfs.itb | check-size 44m |\
|
||||
) \
|
||||
pad-to 44M | mt7981-bl2 spim-nand-ddr3 |\
|
||||
pad-to 45M | mt7981-bl31-uboot rfb-spim-nand |\
|
||||
pad-to 49M | mt7981-bl2 nor-ddr3 |\
|
||||
pad-to 50M | mt7981-bl31-uboot rfb-nor |\
|
||||
pad-to 51M | mt7981-bl2 snand-ddr3 |\
|
||||
pad-to 53M | mt7981-bl31-uboot rfb-snfi |\
|
||||
$(if $(CONFIG_TARGET_ROOTFS_SQUASHFS),\
|
||||
pad-to 64M | append-image squashfs-sysupgrade.itb | check-size |\
|
||||
) \
|
||||
gzip
|
||||
endef
|
||||
TARGET_DEVICES += mediatek_mt7981-rfb
|
||||
|
||||
define Device/mediatek_mt7986a-rfb-nand
|
||||
DEVICE_VENDOR := MediaTek
|
||||
DEVICE_MODEL := MT7986 rfba AP (NAND)
|
||||
DEVICE_DTS := mt7986a-rfb-spim-nand
|
||||
DEVICE_DTS_DIR := $(DTS_DIR)/
|
||||
DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware
|
||||
SUPPORTED_DEVICES := mediatek,mt7986a-rfb-snand
|
||||
UBINIZE_OPTS := -E 5
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
IMAGE_SIZE := 65536k
|
||||
KERNEL_IN_UBI := 1
|
||||
IMAGES += factory.bin
|
||||
IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE)
|
||||
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
|
||||
KERNEL = kernel-bin | lzma | \
|
||||
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
|
||||
KERNEL_INITRAMFS = kernel-bin | lzma | \
|
||||
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd
|
||||
endef
|
||||
TARGET_DEVICES += mediatek_mt7986a-rfb-nand
|
||||
|
||||
define Device/mediatek_mt7986b-rfb
|
||||
DEVICE_VENDOR := MediaTek
|
||||
DEVICE_MODEL := MTK7986 rfbb AP
|
||||
DEVICE_DTS := mt7986b-rfb
|
||||
DEVICE_DTS_DIR := $(DTS_DIR)/
|
||||
DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware
|
||||
SUPPORTED_DEVICES := mediatek,mt7986b-rfb
|
||||
UBINIZE_OPTS := -E 5
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
IMAGE_SIZE := 65536k
|
||||
KERNEL_IN_UBI := 1
|
||||
IMAGES += factory.bin
|
||||
IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE)
|
||||
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
|
||||
endef
|
||||
TARGET_DEVICES += mediatek_mt7986b-rfb
|
||||
|
||||
define Device/mediatek_mt7988a-rfb
|
||||
DEVICE_VENDOR := MediaTek
|
||||
DEVICE_MODEL := MT7988A rfb
|
||||
DEVICE_DTS := mt7988a-rfb
|
||||
DEVICE_DTS_OVERLAY:= \
|
||||
mt7988a-rfb-emmc \
|
||||
mt7988a-rfb-sd \
|
||||
mt7988a-rfb-snfi-nand \
|
||||
mt7988a-rfb-spim-nand \
|
||||
mt7988a-rfb-spim-nor \
|
||||
mt7988a-rfb-eth1-aqr \
|
||||
mt7988a-rfb-eth1-i2p5g-phy \
|
||||
mt7988a-rfb-eth1-mxl \
|
||||
mt7988a-rfb-eth1-sfp \
|
||||
mt7988a-rfb-eth2-aqr \
|
||||
mt7988a-rfb-eth2-mxl \
|
||||
mt7988a-rfb-eth2-sfp
|
||||
DEVICE_DTS_DIR := $(DTS_DIR)/
|
||||
DEVICE_DTC_FLAGS := --pad 4096
|
||||
DEVICE_DTS_LOADADDR := 0x45f00000
|
||||
DEVICE_PACKAGES := kmod-sfp
|
||||
KERNEL_LOADADDR := 0x46000000
|
||||
KERNEL := kernel-bin | gzip
|
||||
KERNEL_INITRAMFS := kernel-bin | lzma | \
|
||||
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
|
||||
KERNEL_INITRAMFS_SUFFIX := .itb
|
||||
KERNEL_IN_UBI := 1
|
||||
IMAGE_SIZE := $$(shell expr 64 + $$(CONFIG_TARGET_ROOTFS_PARTSIZE))m
|
||||
IMAGES := sysupgrade.itb
|
||||
IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-with-rootfs | pad-rootfs | append-metadata
|
||||
ARTIFACTS := \
|
||||
emmc-gpt.bin emmc-preloader.bin emmc-bl31-uboot.fip \
|
||||
nor-preloader.bin nor-bl31-uboot.fip \
|
||||
sdcard.img.gz \
|
||||
snand-preloader.bin snand-bl31-uboot.fip
|
||||
ARTIFACT/emmc-gpt.bin := mt798x-gpt emmc
|
||||
ARTIFACT/emmc-preloader.bin := mt7988-bl2 emmc-comb
|
||||
ARTIFACT/emmc-bl31-uboot.fip := mt7988-bl31-uboot rfb-emmc
|
||||
ARTIFACT/nor-preloader.bin := mt7988-bl2 nor-comb
|
||||
ARTIFACT/nor-bl31-uboot.fip := mt7988-bl31-uboot rfb-nor
|
||||
ARTIFACT/snand-preloader.bin := mt7988-bl2 spim-nand-comb
|
||||
ARTIFACT/snand-bl31-uboot.fip := mt7988-bl31-uboot rfb-snand
|
||||
ARTIFACT/sdcard.img.gz := mt798x-gpt sdmmc |\
|
||||
pad-to 17k | mt7988-bl2 sdmmc-comb |\
|
||||
pad-to 6656k | mt7988-bl31-uboot rfb-sd |\
|
||||
$(if $(CONFIG_TARGET_ROOTFS_INITRAMFS),\
|
||||
pad-to 12M | append-image-stage initramfs.itb | check-size 44m |\
|
||||
) \
|
||||
pad-to 44M | mt7988-bl2 spim-nand-comb |\
|
||||
pad-to 45M | mt7988-bl31-uboot rfb-snand |\
|
||||
pad-to 51M | mt7988-bl2 nor-comb |\
|
||||
pad-to 51M | mt7988-bl31-uboot rfb-nor |\
|
||||
pad-to 55M | mt7988-bl2 emmc-comb |\
|
||||
pad-to 56M | mt7988-bl31-uboot rfb-emmc |\
|
||||
pad-to 62M | mt798x-gpt emmc |\
|
||||
$(if $(CONFIG_TARGET_ROOTFS_SQUASHFS),\
|
||||
pad-to 64M | append-image squashfs-sysupgrade.itb | check-size |\
|
||||
) \
|
||||
gzip
|
||||
endef
|
||||
TARGET_DEVICES += mediatek_mt7988a-rfb
|
||||
|
||||
define Device/mercusys_mr90x-v1
|
||||
DEVICE_VENDOR := Mercusys
|
||||
DEVICE_MODEL := MR90X v1
|
||||
DEVICE_DTS := mt7986b-mercusys-mr90x-v1
|
||||
DEVICE_DTS_DIR := ../dts
|
||||
DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware
|
||||
UBINIZE_OPTS := -E 5
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
IMAGE_SIZE := 51200k
|
||||
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
|
||||
endef
|
||||
TARGET_DEVICES += mercusys_mr90x-v1
|
||||
|
||||
define Device/qihoo_360t7
|
||||
DEVICE_VENDOR := Qihoo
|
||||
DEVICE_MODEL := 360T7
|
||||
DEVICE_DTS := mt7981b-qihoo-360t7
|
||||
DEVICE_DTS_DIR := ../dts
|
||||
UBINIZE_OPTS := -E 5
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
KERNEL_IN_UBI := 1
|
||||
UBOOTENV_IN_UBI := 1
|
||||
IMAGES := sysupgrade.itb
|
||||
KERNEL_INITRAMFS_SUFFIX := -recovery.itb
|
||||
KERNEL := kernel-bin | gzip
|
||||
KERNEL_INITRAMFS := kernel-bin | lzma | \
|
||||
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
|
||||
IMAGE/sysupgrade.itb := append-kernel | \
|
||||
fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata
|
||||
DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
|
||||
ARTIFACTS := preloader.bin bl31-uboot.fip
|
||||
ARTIFACT/preloader.bin := mt7981-bl2 spim-nand-ddr3
|
||||
ARTIFACT/bl31-uboot.fip := mt7981-bl31-uboot qihoo_360t7
|
||||
endef
|
||||
TARGET_DEVICES += qihoo_360t7
|
||||
|
||||
define Device/tplink_tl-xdr-common
|
||||
DEVICE_VENDOR := TP-Link
|
||||
DEVICE_DTS_DIR := ../dts
|
||||
UBINIZE_OPTS := -E 5
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
KERNEL_IN_UBI := 1
|
||||
UBOOTENV_IN_UBI := 1
|
||||
IMAGES := sysupgrade.itb
|
||||
KERNEL_INITRAMFS_SUFFIX := -recovery.itb
|
||||
KERNEL := kernel-bin | gzip
|
||||
KERNEL_INITRAMFS := kernel-bin | lzma | \
|
||||
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
|
||||
IMAGE/sysupgrade.itb := append-kernel | \
|
||||
fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-with-rootfs | append-metadata
|
||||
DEVICE_PACKAGES := kmod-usb3 kmod-mt7986-firmware mt7986-wo-firmware
|
||||
ARTIFACTS := preloader.bin bl31-uboot.fip
|
||||
ARTIFACT/preloader.bin := mt7986-bl2 spim-nand-ddr3
|
||||
endef
|
||||
|
||||
define Device/tplink_tl-xdr4288
|
||||
DEVICE_MODEL := TL-XDR4288
|
||||
DEVICE_DTS := mt7986a-tplink-tl-xdr4288
|
||||
ARTIFACT/bl31-uboot.fip := mt7986-bl31-uboot tplink_tl-xdr4288
|
||||
$(call Device/tplink_tl-xdr-common)
|
||||
endef
|
||||
TARGET_DEVICES += tplink_tl-xdr4288
|
||||
|
||||
define Device/tplink_tl-xdr6086
|
||||
DEVICE_MODEL := TL-XDR6086
|
||||
DEVICE_DTS := mt7986a-tplink-tl-xdr6086
|
||||
ARTIFACT/bl31-uboot.fip := mt7986-bl31-uboot tplink_tl-xdr6086
|
||||
$(call Device/tplink_tl-xdr-common)
|
||||
endef
|
||||
TARGET_DEVICES += tplink_tl-xdr6086
|
||||
|
||||
define Device/tplink_tl-xdr6088
|
||||
DEVICE_MODEL := TL-XDR6088
|
||||
DEVICE_DTS := mt7986a-tplink-tl-xdr6088
|
||||
ARTIFACT/bl31-uboot.fip := mt7986-bl31-uboot tplink_tl-xdr6088
|
||||
$(call Device/tplink_tl-xdr-common)
|
||||
endef
|
||||
TARGET_DEVICES += tplink_tl-xdr6088
|
||||
|
||||
define Device/ubnt_unifi-6-plus
|
||||
DEVICE_VENDOR := Ubiquiti
|
||||
DEVICE_MODEL := UniFi 6 Plus
|
||||
DEVICE_DTS := mt7981a-ubnt-unifi-6-plus
|
||||
DEVICE_DTS_DIR := ../dts
|
||||
DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware e2fsprogs f2fsck mkf2fs fdisk partx-utils
|
||||
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
|
||||
endef
|
||||
TARGET_DEVICES += ubnt_unifi-6-plus
|
||||
|
||||
define Device/xiaomi_mi-router-wr30u-112m-nmbm
|
||||
DEVICE_VENDOR := Xiaomi
|
||||
DEVICE_MODEL := Mi Router WR30U (112M UBI with NMBM-Enabled layout)
|
||||
DEVICE_DTS := mt7981b-xiaomi-mi-router-wr30u-112m-nmbm
|
||||
DEVICE_DTS_DIR := ../dts
|
||||
UBINIZE_OPTS := -E 5
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
|
||||
ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
|
||||
ARTIFACTS := initramfs-factory.ubi
|
||||
ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-kernel.bin | ubinize-kernel
|
||||
endif
|
||||
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
|
||||
endef
|
||||
TARGET_DEVICES += xiaomi_mi-router-wr30u-112m-nmbm
|
||||
|
||||
define Device/xiaomi_mi-router-wr30u-stock
|
||||
DEVICE_VENDOR := Xiaomi
|
||||
DEVICE_MODEL := Mi Router WR30U (stock layout)
|
||||
DEVICE_DTS := mt7981b-xiaomi-mi-router-wr30u-stock
|
||||
DEVICE_DTS_DIR := ../dts
|
||||
UBINIZE_OPTS := -E 5
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
|
||||
ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
|
||||
ARTIFACTS := initramfs-factory.ubi
|
||||
ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-kernel.bin | ubinize-kernel
|
||||
endif
|
||||
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
|
||||
endef
|
||||
TARGET_DEVICES += xiaomi_mi-router-wr30u-stock
|
||||
|
||||
define Device/xiaomi_mi-router-wr30u-ubootmod
|
||||
DEVICE_VENDOR := Xiaomi
|
||||
DEVICE_MODEL := Mi Router WR30U (OpenWrt U-Boot layout)
|
||||
DEVICE_DTS := mt7981b-xiaomi-mi-router-wr30u-ubootmod
|
||||
DEVICE_DTS_DIR := ../dts
|
||||
UBINIZE_OPTS := -E 5
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
|
||||
KERNEL_IN_UBI := 1
|
||||
UBOOTENV_IN_UBI := 1
|
||||
IMAGES := sysupgrade.itb
|
||||
KERNEL_INITRAMFS_SUFFIX := -recovery.itb
|
||||
KERNEL := kernel-bin | gzip
|
||||
KERNEL_INITRAMFS := kernel-bin | lzma | \
|
||||
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
|
||||
IMAGE/sysupgrade.itb := append-kernel | \
|
||||
fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata
|
||||
ARTIFACTS := preloader.bin bl31-uboot.fip
|
||||
ARTIFACT/preloader.bin := mt7981-bl2 spim-nand-ddr3
|
||||
ARTIFACT/bl31-uboot.fip := mt7981-bl31-uboot xiaomi_mi-router-wr30u
|
||||
ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
|
||||
ARTIFACTS += initramfs-factory.ubi
|
||||
ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-recovery.itb | ubinize-kernel
|
||||
endif
|
||||
endef
|
||||
TARGET_DEVICES += xiaomi_mi-router-wr30u-ubootmod
|
||||
|
||||
define Device/xiaomi_redmi-router-ax6000-stock
|
||||
DEVICE_VENDOR := Xiaomi
|
||||
DEVICE_MODEL := Redmi Router AX6000 (stock layout)
|
||||
DEVICE_DTS := mt7986a-xiaomi-redmi-router-ax6000-stock
|
||||
DEVICE_DTS_DIR := ../dts
|
||||
DEVICE_PACKAGES := kmod-leds-ws2812b kmod-mt7986-firmware mt7986-wo-firmware
|
||||
UBINIZE_OPTS := -E 5
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
|
||||
ARTIFACTS := initramfs-factory.ubi
|
||||
ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-kernel.bin | ubinize-kernel
|
||||
endif
|
||||
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
|
||||
endef
|
||||
TARGET_DEVICES += xiaomi_redmi-router-ax6000-stock
|
||||
|
||||
define Device/xiaomi_redmi-router-ax6000-ubootmod
|
||||
DEVICE_VENDOR := Xiaomi
|
||||
DEVICE_MODEL := Redmi Router AX6000 (OpenWrt U-Boot layout)
|
||||
DEVICE_DTS := mt7986a-xiaomi-redmi-router-ax6000-ubootmod
|
||||
DEVICE_DTS_DIR := ../dts
|
||||
DEVICE_PACKAGES := kmod-leds-ws2812b kmod-mt7986-firmware mt7986-wo-firmware
|
||||
KERNEL_INITRAMFS_SUFFIX := -recovery.itb
|
||||
IMAGES := sysupgrade.itb
|
||||
UBINIZE_OPTS := -E 5
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
KERNEL_IN_UBI := 1
|
||||
UBOOTENV_IN_UBI := 1
|
||||
KERNEL := kernel-bin | gzip
|
||||
KERNEL_INITRAMFS := kernel-bin | lzma | \
|
||||
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
|
||||
IMAGE/sysupgrade.itb := append-kernel | \
|
||||
fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata
|
||||
ARTIFACTS := preloader.bin bl31-uboot.fip
|
||||
ARTIFACT/preloader.bin := mt7986-bl2 spim-nand-ddr4
|
||||
ARTIFACT/bl31-uboot.fip := mt7986-bl31-uboot xiaomi_redmi-router-ax6000
|
||||
ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
|
||||
ARTIFACTS += initramfs-factory.ubi
|
||||
ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-recovery.itb | ubinize-kernel
|
||||
endif
|
||||
endef
|
||||
TARGET_DEVICES += xiaomi_redmi-router-ax6000-ubootmod
|
||||
|
||||
define Device/zyxel_ex5601-t0-stock
|
||||
DEVICE_VENDOR := Zyxel
|
||||
DEVICE_MODEL := EX5601-T0 (stock layout)
|
||||
DEVICE_DTS := mt7986a-zyxel-ex5601-t0-stock
|
||||
DEVICE_DTS_DIR := ../dts
|
||||
DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware
|
||||
SUPPORTED_DEVICES := mediatek,mt7986a-rfb-snand
|
||||
UBINIZE_OPTS := -E 5
|
||||
BLOCKSIZE := 256k
|
||||
PAGESIZE := 4096
|
||||
IMAGE_SIZE := 65536k
|
||||
KERNEL_IN_UBI := 1
|
||||
IMAGES += factory.bin
|
||||
IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE)
|
||||
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
|
||||
KERNEL = kernel-bin | lzma | \
|
||||
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
|
||||
KERNEL_INITRAMFS = kernel-bin | lzma | \
|
||||
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd
|
||||
endef
|
||||
TARGET_DEVICES += zyxel_ex5601-t0-stock
|
||||
|
||||
define Device/zyxel_ex5700-telenor
|
||||
DEVICE_VENDOR := ZyXEL
|
||||
DEVICE_MODEL := EX5700 (Telenor)
|
||||
DEVICE_DTS := mt7986a-zyxel-ex5700-telenor
|
||||
DEVICE_DTS_DIR := ../dts
|
||||
DEVICE_PACKAGES := kmod-mt7916-firmware kmod-ubootenv-nvram kmod-usb3 kmod-mt7986-firmware mt7986-wo-firmware
|
||||
UBINIZE_OPTS := -E 5
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
IMAGE_SIZE := 65536k
|
||||
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
|
||||
endef
|
||||
TARGET_DEVICES += zyxel_ex5700-telenor
|
||||
|
||||
define Device/zyxel_nwa50ax-pro
|
||||
DEVICE_VENDOR := ZyXEL
|
||||
DEVICE_MODEL := NWA50AX Pro
|
||||
DEVICE_DTS := mt7981b-zyxel-nwa50ax-pro
|
||||
DEVICE_DTS_DIR := ../dts
|
||||
DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware zyxel-bootconfig
|
||||
DEVICE_DTS_LOADADDR := 0x44000000
|
||||
UBINIZE_OPTS := -E 5
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
IMAGE_SIZE := 51200k
|
||||
KERNEL_IN_UBI := 1
|
||||
IMAGES += factory.bin
|
||||
IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE) | zyxel-nwa-fit-filogic
|
||||
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
|
||||
endef
|
||||
TARGET_DEVICES += zyxel_nwa50ax-pro
|
||||
|
||||
define Device/z8102ax
|
||||
DEVICE_VENDOR := ZBT
|
||||
DEVICE_MODEL := Z8102AX
|
||||
DEVICE_DTS := mt7981b-zbt-z8102ax
|
||||
DEVICE_DTS_DIR := ../dts
|
||||
DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
|
||||
UBINIZE_OPTS := -E 5
|
||||
BLOCKSIZE := 128k
|
||||
PAGESIZE := 2048
|
||||
IMAGE_SIZE := 51200k
|
||||
ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
|
||||
ARTIFACTS := initramfs-factory.ubi
|
||||
ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-kernel.bin | ubinize-kernel
|
||||
endif
|
||||
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
|
||||
endef
|
||||
TARGET_DEVICES += z8102ax
|
|
@ -0,0 +1,34 @@
|
|||
From f8ed4088ed9c61ae92193da6130d04c37e7b19f2 Mon Sep 17 00:00:00 2001
|
||||
From: Frank Wunderlich <frank-w@public-files.de>
|
||||
Date: Sun, 20 Aug 2023 17:31:33 +0200
|
||||
Subject: [PATCH 20/22] arm64: dts: mt7986: define 3W max power to both SFP on
|
||||
BPI-R3
|
||||
|
||||
All SFP power supplies are connected to the system VDD33 which is 3v3/8A.
|
||||
Set 3A per SFP slot to allow SFPs work which need more power than the
|
||||
default 1W.
|
||||
|
||||
Fixes: 8e01fb15b815 ("arm64: dts: mt7986: add Bananapi R3")
|
||||
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
|
||||
---
|
||||
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
|
||||
@@ -126,6 +126,7 @@
|
||||
compatible = "sff,sfp";
|
||||
i2c-bus = <&i2c_sfp1>;
|
||||
los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
|
||||
+ maximum-power-milliwatt = <3000>;
|
||||
mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
|
||||
tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
|
||||
tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
|
||||
@@ -137,6 +138,7 @@
|
||||
i2c-bus = <&i2c_sfp2>;
|
||||
los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
|
||||
mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
|
||||
+ maximum-power-milliwatt = <3000>;
|
||||
tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
|
||||
tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
|
||||
};
|
|
@ -0,0 +1,59 @@
|
|||
From aa3d6df9803c267725dc72286bb91602b7579882 Mon Sep 17 00:00:00 2001
|
||||
From: Frank Wunderlich <frank-w@public-files.de>
|
||||
Date: Sun, 20 Aug 2023 17:31:34 +0200
|
||||
Subject: [PATCH 21/22] arm64: dts: mt7986: change cooling trips
|
||||
|
||||
Add Critical and hot trips for emergency system shutdown and limiting
|
||||
system load.
|
||||
|
||||
Change passive trip to active to make sure fan is activated on the
|
||||
lowest trip.
|
||||
|
||||
Fixes: 1f5be05132f3 ("arm64: dts: mt7986: add thermal-zones")
|
||||
Suggested-by: Daniel Golle <daniel@makrotopia.org>
|
||||
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
|
||||
---
|
||||
arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 20 ++++++++++++++++----
|
||||
1 file changed, 16 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
|
||||
@@ -610,22 +610,34 @@
|
||||
thermal-sensors = <&thermal 0>;
|
||||
|
||||
trips {
|
||||
+ cpu_trip_crit: crit {
|
||||
+ temperature = <125000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+
|
||||
+ cpu_trip_hot: hot {
|
||||
+ temperature = <120000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "hot";
|
||||
+ };
|
||||
+
|
||||
cpu_trip_active_high: active-high {
|
||||
temperature = <115000>;
|
||||
hysteresis = <2000>;
|
||||
type = "active";
|
||||
};
|
||||
|
||||
- cpu_trip_active_low: active-low {
|
||||
+ cpu_trip_active_med: active-med {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "active";
|
||||
};
|
||||
|
||||
- cpu_trip_passive: passive {
|
||||
- temperature = <40000>;
|
||||
+ cpu_trip_active_low: active-low {
|
||||
+ temperature = <60000>;
|
||||
hysteresis = <2000>;
|
||||
- type = "passive";
|
||||
+ type = "active";
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,38 @@
|
|||
From 6ddf23526955b8dbedfeaa57e691261fd73f9d4e Mon Sep 17 00:00:00 2001
|
||||
From: Frank Wunderlich <frank-w@public-files.de>
|
||||
Date: Sun, 20 Aug 2023 17:31:35 +0200
|
||||
Subject: [PATCH 22/22] arm64: dts: mt7986: change thermal trips on BPI-R3
|
||||
|
||||
Apply new naming after mt7986 thermal trips were changed.
|
||||
|
||||
Fixes: c26f779a2295 ("arm64: dts: mt7986: add pwm-fan and cooling-maps to BPI-R3 dts")
|
||||
Suggested-by: Daniel Golle <daniel@makrotopia.org>
|
||||
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
|
||||
---
|
||||
.../boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 10 +++++-----
|
||||
1 file changed, 5 insertions(+), 5 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
|
||||
@@ -152,16 +152,16 @@
|
||||
trip = <&cpu_trip_active_high>;
|
||||
};
|
||||
|
||||
- cpu-active-low {
|
||||
+ cpu-active-med {
|
||||
/* active: set fan to cooling level 1 */
|
||||
cooling-device = <&fan 1 1>;
|
||||
- trip = <&cpu_trip_active_low>;
|
||||
+ trip = <&cpu_trip_active_med>;
|
||||
};
|
||||
|
||||
- cpu-passive {
|
||||
- /* passive: set fan to cooling level 0 */
|
||||
+ cpu-active-low {
|
||||
+ /* active: set fan to cooling level 0 */
|
||||
cooling-device = <&fan 0 0>;
|
||||
- trip = <&cpu_trip_passive>;
|
||||
+ trip = <&cpu_trip_active_low>;
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,107 @@
|
|||
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
|
||||
@@ -1,7 +1,6 @@
|
||||
/*
|
||||
- * Copyright (c) 2017 MediaTek Inc.
|
||||
- * Author: Ming Huang <ming.huang@mediatek.com>
|
||||
- * Sean Wang <sean.wang@mediatek.com>
|
||||
+ * Copyright (c) 2018 MediaTek Inc.
|
||||
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
|
||||
*
|
||||
* SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
*/
|
||||
@@ -24,7 +23,7 @@
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
|
||||
+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
|
||||
};
|
||||
|
||||
cpus {
|
||||
@@ -45,18 +44,18 @@
|
||||
key-factory {
|
||||
label = "factory";
|
||||
linux,code = <BTN_0>;
|
||||
- gpios = <&pio 0 0>;
|
||||
+ gpios = <&pio 0 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
key-wps {
|
||||
label = "wps";
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
- gpios = <&pio 102 0>;
|
||||
+ gpios = <&pio 102 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
- reg = <0 0x40000000 0 0x20000000>;
|
||||
+ reg = <0 0x40000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
reg_1p8v: regulator-1p8v {
|
||||
@@ -132,22 +131,22 @@
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
- label = "lan0";
|
||||
+ label = "lan1";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
- label = "lan1";
|
||||
+ label = "lan2";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
- label = "lan2";
|
||||
+ label = "lan3";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
- label = "lan3";
|
||||
+ label = "lan4";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
@@ -240,7 +239,22 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&pcie1 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie1_pins>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&pio {
|
||||
+ /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
|
||||
+ * SATA functions. i.e. output-high: PCIe, output-low: SATA
|
||||
+ */
|
||||
+ asm_sel {
|
||||
+ gpio-hog;
|
||||
+ gpios = <90 GPIO_ACTIVE_HIGH>;
|
||||
+ output-high;
|
||||
+ };
|
||||
+
|
||||
/* eMMC is shared pin with parallel NAND */
|
||||
emmc_pins_default: emmc-pins-default {
|
||||
mux {
|
||||
@@ -517,11 +531,11 @@
|
||||
};
|
||||
|
||||
&sata {
|
||||
- status = "okay";
|
||||
+ status = "disabled";
|
||||
};
|
||||
|
||||
&sata_phy {
|
||||
- status = "okay";
|
||||
+ status = "disabled";
|
||||
};
|
||||
|
||||
&spi0 {
|
|
@ -0,0 +1,20 @@
|
|||
From d6a596012150960f0f3a214d31bbac4b607dbd1e Mon Sep 17 00:00:00 2001
|
||||
From: Chuanhong Guo <gch981213@gmail.com>
|
||||
Date: Fri, 29 Apr 2022 10:40:56 +0800
|
||||
Subject: [PATCH] arm: mediatek: select arch timer for mt7623
|
||||
|
||||
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
|
||||
---
|
||||
arch/arm/mach-mediatek/Kconfig | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/arch/arm/mach-mediatek/Kconfig
|
||||
+++ b/arch/arm/mach-mediatek/Kconfig
|
||||
@@ -26,6 +26,7 @@ config MACH_MT6592
|
||||
config MACH_MT7623
|
||||
bool "MediaTek MT7623 SoCs support"
|
||||
default ARCH_MEDIATEK
|
||||
+ select HAVE_ARM_ARCH_TIMER
|
||||
|
||||
config MACH_MT7629
|
||||
bool "MediaTek MT7629 SoCs support"
|
|
@ -0,0 +1,10 @@
|
|||
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||
@@ -578,6 +578,7 @@
|
||||
compatible = "mediatek,mt7622-nor",
|
||||
"mediatek,mt8173-nor";
|
||||
reg = <0 0x11014000 0 0xe0>;
|
||||
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
|
||||
clocks = <&pericfg CLK_PERI_FLASH_PD>,
|
||||
<&topckgen CLK_TOP_FLASH_SEL>;
|
||||
clock-names = "spi", "sf";
|
|
@ -0,0 +1,16 @@
|
|||
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||
@@ -134,6 +134,13 @@
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
+ /* 64 KiB reserved for ramoops/pstore */
|
||||
+ ramoops@42ff0000 {
|
||||
+ compatible = "ramoops";
|
||||
+ reg = <0 0x42ff0000 0 0x10000>;
|
||||
+ record-size = <0x1000>;
|
||||
+ };
|
||||
+
|
||||
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
|
||||
secmon_reserved: secmon@43000000 {
|
||||
reg = <0 0x43000000 0 0x30000>;
|
|
@ -0,0 +1,11 @@
|
|||
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
|
||||
@@ -24,7 +24,7 @@
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
|
||||
+ bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
|
||||
};
|
||||
|
||||
cpus {
|
|
@ -0,0 +1,37 @@
|
|||
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
|
||||
@@ -20,6 +20,7 @@
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
+ ethernet0 = &gmac0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@@ -164,22 +165,22 @@
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
- label = "lan0";
|
||||
+ label = "lan1";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
- label = "lan1";
|
||||
+ label = "lan2";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
- label = "lan2";
|
||||
+ label = "lan3";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
- label = "lan3";
|
||||
+ label = "lan4";
|
||||
};
|
||||
|
||||
port@6 {
|
|
@ -0,0 +1,47 @@
|
|||
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
|
||||
@@ -21,6 +21,10 @@
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
ethernet0 = &gmac0;
|
||||
+ led-boot = &led_system_green;
|
||||
+ led-failsafe = &led_system_blue;
|
||||
+ led-running = &led_system_green;
|
||||
+ led-upgrade = &led_system_blue;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@@ -44,8 +48,8 @@
|
||||
compatible = "gpio-keys";
|
||||
|
||||
factory-key {
|
||||
- label = "factory";
|
||||
- linux,code = <BTN_0>;
|
||||
+ label = "reset";
|
||||
+ linux,code = <KEY_RESTART>;
|
||||
gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
@@ -59,17 +63,17 @@
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
- led-0 {
|
||||
+ led_system_green: led-0 {
|
||||
label = "bpi-r64:pio:green";
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
- led-1 {
|
||||
- label = "bpi-r64:pio:red";
|
||||
- color = <LED_COLOR_ID_RED>;
|
||||
- gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
|
||||
+ led_system_blue: led-1 {
|
||||
+ label = "bpi-r64:pio:blue";
|
||||
+ color = <LED_COLOR_ID_BLUE>;
|
||||
+ gpios = <&pio 85 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
|
@ -0,0 +1,20 @@
|
|||
--- a/drivers/mtd/nand/spi/core.c
|
||||
+++ b/drivers/mtd/nand/spi/core.c
|
||||
@@ -724,7 +724,7 @@ static int spinand_mtd_write(struct mtd_
|
||||
static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos)
|
||||
{
|
||||
struct spinand_device *spinand = nand_to_spinand(nand);
|
||||
- u8 marker[2] = { };
|
||||
+ u8 marker[1] = { };
|
||||
struct nand_page_io_req req = {
|
||||
.pos = *pos,
|
||||
.ooblen = sizeof(marker),
|
||||
@@ -735,7 +735,7 @@ static bool spinand_isbad(struct nand_de
|
||||
|
||||
spinand_select_target(spinand, pos->target);
|
||||
spinand_read_page(spinand, &req);
|
||||
- if (marker[0] != 0xff || marker[1] != 0xff)
|
||||
+ if (marker[0] != 0xff)
|
||||
return true;
|
||||
|
||||
return false;
|
|
@ -0,0 +1,68 @@
|
|||
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
|
||||
@@ -538,6 +538,65 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+&bch {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&snfi {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&serial_nand_pins>;
|
||||
+ status = "okay";
|
||||
+ flash@0 {
|
||||
+ compatible = "spi-nand";
|
||||
+ reg = <0>;
|
||||
+ spi-tx-bus-width = <4>;
|
||||
+ spi-rx-bus-width = <4>;
|
||||
+ nand-ecc-engine = <&snfi>;
|
||||
+
|
||||
+ partitions {
|
||||
+ compatible = "fixed-partitions";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ partition@0 {
|
||||
+ label = "Preloader";
|
||||
+ reg = <0x00000 0x0080000>;
|
||||
+ read-only;
|
||||
+ };
|
||||
+
|
||||
+ partition@80000 {
|
||||
+ label = "ATF";
|
||||
+ reg = <0x80000 0x0040000>;
|
||||
+ };
|
||||
+
|
||||
+ partition@c0000 {
|
||||
+ label = "Bootloader";
|
||||
+ reg = <0xc0000 0x0080000>;
|
||||
+ };
|
||||
+
|
||||
+ partition@140000 {
|
||||
+ label = "Config";
|
||||
+ reg = <0x140000 0x0080000>;
|
||||
+ };
|
||||
+
|
||||
+ partition@1c0000 {
|
||||
+ label = "Factory";
|
||||
+ reg = <0x1c0000 0x0100000>;
|
||||
+ };
|
||||
+
|
||||
+ partition@200000 {
|
||||
+ label = "firmware";
|
||||
+ reg = <0x2c0000 0x2000000>;
|
||||
+ };
|
||||
+
|
||||
+ partition@2200000 {
|
||||
+ label = "User_data";
|
||||
+ reg = <0x22c0000 0x4000000>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
&spi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spic0_pins>;
|
|
@ -0,0 +1,18 @@
|
|||
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
|
||||
@@ -579,7 +579,7 @@
|
||||
reg = <0x140000 0x0080000>;
|
||||
};
|
||||
|
||||
- partition@1c0000 {
|
||||
+ factory: partition@1c0000 {
|
||||
label = "Factory";
|
||||
reg = <0x1c0000 0x0100000>;
|
||||
};
|
||||
@@ -640,5 +640,6 @@
|
||||
&wmac {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wmac_pins>;
|
||||
+ mediatek,mtd-eeprom = <&factory 0x0000>;
|
||||
status = "okay";
|
||||
};
|
|
@ -0,0 +1,106 @@
|
|||
From patchwork Tue Apr 26 19:51:36 2022
|
||||
Content-Type: text/plain; charset="utf-8"
|
||||
MIME-Version: 1.0
|
||||
Content-Transfer-Encoding: 7bit
|
||||
X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
|
||||
X-Patchwork-Id: 12827872
|
||||
Return-Path:
|
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||||
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||||
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||||
id 1njRDu-0006aF-4F; Tue, 26 Apr 2022 21:51:46 +0200
|
||||
Date: Tue, 26 Apr 2022 20:51:36 +0100
|
||||
From: Daniel Golle <daniel@makrotopia.org>
|
||||
To: devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org,
|
||||
linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
|
||||
Cc: Rob Herring <robh+dt@kernel.org>,
|
||||
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
|
||||
Matthias Brugger <matthias.bgg@gmail.com>
|
||||
Subject: [PATCH] arm64: dts: mediatek: mt7622: fix GICv2 range
|
||||
Message-ID: <YmhNSLgp/yg8Vr1F@makrotopia.org>
|
||||
MIME-Version: 1.0
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
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|
||||
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|
||||
Errors-To:
|
||||
linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org
|
||||
|
||||
With the current range specified for the CPU interface there is an
|
||||
error message at boot:
|
||||
|
||||
GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set
|
||||
|
||||
Setting irqchip.gicv2_force_probe=1 in bootargs results in:
|
||||
|
||||
GIC: Aliased GICv2 at 0x0000000010320000, trying to find the canonical range over 128kB
|
||||
GIC: Adjusting CPU interface base to 0x000000001032f000
|
||||
GIC: Using split EOI/Deactivate mode
|
||||
|
||||
Using the adjusted CPU interface base and 8K size results in only the
|
||||
final line remaining and fully working system as well as /proc/interrupts
|
||||
showing additional IPI3,4,5,6:
|
||||
|
||||
IPI3: 0 0 CPU stop (for crash dump) interrupts
|
||||
IPI4: 0 0 Timer broadcast interrupts
|
||||
IPI5: 0 0 IRQ work interrupts
|
||||
IPI6: 0 0 CPU wake-up interrupts
|
||||
|
||||
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||
---
|
||||
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||
@@ -346,7 +346,7 @@
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-parent = <&gic>;
|
||||
reg = <0 0x10310000 0 0x1000>,
|
||||
- <0 0x10320000 0 0x1000>,
|
||||
+ <0 0x1032f000 0 0x2000>,
|
||||
<0 0x10340000 0 0x2000>,
|
||||
<0 0x10360000 0 0x2000>;
|
||||
};
|
|
@ -0,0 +1,17 @@
|
|||
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
|
||||
@@ -68,6 +68,14 @@
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
+
|
||||
+ /* 64 KiB reserved for ramoops/pstore */
|
||||
+ ramoops@42ff0000 {
|
||||
+ compatible = "ramoops";
|
||||
+ reg = <0 0x42ff0000 0 0x10000>;
|
||||
+ record-size = <0x1000>;
|
||||
+ };
|
||||
+
|
||||
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
|
||||
secmon_reserved: secmon@43000000 {
|
||||
reg = <0 0x43000000 0 0x30000>;
|
|
@ -0,0 +1,196 @@
|
|||
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
|
||||
@@ -23,6 +23,10 @@
|
||||
serial0 = &uart0;
|
||||
ethernet0 = &gmac0;
|
||||
ethernet1 = &gmac1;
|
||||
+ led-boot = &green_led;
|
||||
+ led-failsafe = &green_led;
|
||||
+ led-running = &green_led;
|
||||
+ led-upgrade = &blue_led;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@@ -419,27 +423,27 @@
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
- label = "lan0";
|
||||
+ label = "lan1";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
- label = "lan1";
|
||||
+ label = "lan2";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
- label = "lan2";
|
||||
+ label = "lan3";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
- label = "lan3";
|
||||
+ label = "lan4";
|
||||
};
|
||||
|
||||
port5: port@5 {
|
||||
reg = <5>;
|
||||
- label = "lan4";
|
||||
+ label = "sfp2";
|
||||
phy-mode = "2500base-x";
|
||||
sfp = <&sfp2>;
|
||||
managed = "in-band-status";
|
||||
@@ -490,9 +494,137 @@
|
||||
|
||||
&wifi {
|
||||
status = "okay";
|
||||
- pinctrl-names = "default", "dbdc";
|
||||
+ pinctrl-names = "default";
|
||||
pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>;
|
||||
- pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>;
|
||||
+
|
||||
+ mediatek,eeprom-data = <0x86790900 0x000c4326 0x60000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x01000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000800 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x24649090 0x00280000 0x05100000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00021e00 0x021e0002 0x1e00021e 0x00022800 0x02280002 0x28000228 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00008080 0x8080fdf7
|
||||
+ 0x0903150d 0x80808080 0x80808080 0x05050d0d 0x1313c6c6 0xc3c3c200 0x00c200c2 0x00008182
|
||||
+ 0x8585c2c2 0x82828282 0x858500c2 0xc2000081 0x82858587 0x87c2c200 0x81818285 0x858787c2
|
||||
+ 0xc2000081 0x82858587 0x87c2c200 0x00818285 0x858787c2 0xc2000081 0x82858587 0x87c4c4c2
|
||||
+ 0xc100c300 0xc3c3c100 0x818383c3 0xc3c3c100 0x81838300 0xc2c2c2c0 0x81828484 0x000000c3
|
||||
+ 0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x838686c2 0xc2c2c081 0x82848486 0x86c3c3c3
|
||||
+ 0xc1008183 0x838686c3 0xc3c3c100 0x81838386 0x86c3c3c3 0xc1008183 0x83868622 0x28002228
|
||||
+ 0x00222800 0x22280000 0xdddddddd 0xdddddddd 0xddbbbbbb 0xccccccdd 0xdddddddd 0xdddddddd
|
||||
+ 0xeeeeeecc 0xccccdddd 0xdddddddd 0x004a5662 0x0000004a 0x56620000 0x004a5662 0x0000004a
|
||||
+ 0x56620000 0x88888888 0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600
|
||||
+ 0x33333326 0x26262626 0x26262600 0x33333326 0x26262626 0x26262600 0x00000000 0xf0f0cc00
|
||||
+ 0x00000000 0x0000aaaa 0xaabbbbbb 0xcccccccc 0xccccbbbb 0xbbbbbbbb 0xbbbbbbaa 0xaaaabbbb
|
||||
+ 0xbbaaaaaa 0x999999aa 0xaaaabbbb 0xbbcccccc 0x00000000 0x0000aaaa 0xaa000000 0xbbbbbbbb
|
||||
+ 0xbbbbaaaa 0xaa999999 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb
|
||||
+ 0x00000000 0x00000000 0x00000000 0x99999999 0x9999aaaa 0xaaaaaaaa 0x999999aa 0xaaaaaaaa
|
||||
+ 0xaaaaaaaa 0xaaaaaaaa 0xaaaabbbb 0xbbbbbbbb 0x00000000 0x0000eeee 0xeeffffff 0xcccccccc
|
||||
+ 0xccccdddd 0xddbbbbbb 0xccccccbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbbbbb 0xbbbbcccc 0xccdddddd
|
||||
+ 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051
|
||||
+ 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200
|
||||
+ 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e
|
||||
+ 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051
|
||||
+ 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200
|
||||
+ 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e 0x00516200 0x686e0051 0x6200686e
|
||||
+ 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888 0x88888888
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000001 0x06000100 0x01050002 0x00ff0300
|
||||
+ 0xf900fe03 0x00000000 0x00000000 0x0000009b 0x6e370000 0x00000000 0x00fc0009 0x0a00fe00
|
||||
+ 0x060700fe 0x00070800 0x05000b0a 0x00000000 0x00000000 0x000000e2 0x96460000 0x00000000
|
||||
+ 0x000400f7 0xf8000300 0xfcfe0003 0x00fbfc00 0xee00e3f2 0x00000000 0x00000000 0x00000011
|
||||
+ 0xbb550000 0x00000000 0x000600f6 0xfc000300 0xfbfe0004 0x00fafe00 0xf600ecf2 0x00000000
|
||||
+ 0x00000000 0x0000001f 0xbf580000 0x00000000 0x000600f5 0xf6000400 0xf8f90004 0x00f7f800
|
||||
+ 0xf700f0f4 0x00000000 0x00000000 0x00000024 0xbe570000 0x00000000 0x000800f8 0xfe000600
|
||||
+ 0xf8fd0007 0x00f9fe00 0xf500f0f4 0x00000000 0x00000000 0x0000002d 0xd6610000 0x00000000
|
||||
+ 0x000400f7 0xfc000500 0xf7fc0005 0x00f7fc00 0xf900f5f8 0x00000000 0x00000000 0x00000026
|
||||
+ 0xd96e0000 0x00000000 0x000400f7 0xf9000600 0xf5f70005 0x00f5f800 0xf900f4f7 0x00000000
|
||||
+ 0x00000000 0x0000001b 0xce690000 0x00000000 0x000300f8 0xf8000600 0xf6f60004 0x00f6f700
|
||||
+ 0xf900f4f7 0x00000000 0x00000000 0x00000018 0xd8720000 0x00000000 0x00000000 0x02404002
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0xc1c2c1c2 0x41c341c3 0x3fc13fc1 0x40c13fc2 0x3fc240c1 0x41c040c0 0x3fc23fc2 0x40c13fc2
|
||||
+ 0x3fc140c0 0x41c040c0 0x3fc33fc3 0x40c23fc2 0x3fc240c1 0x41c040c0 0x3fc23fc2 0x40c23fc2
|
||||
+ 0x3fc140c1 0x41c040c0 0x00000000 0x00000000 0x41c741c7 0xc1c7c1c7 0x00000000 0x00000000
|
||||
+ 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0
|
||||
+ 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0 0x3fc03fc0
|
||||
+ 0x00a0ce00 0x00000000 0xb6840000 0x00000000 0x00000000 0x00000000 0x18181818 0x18181818
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x004b5763 0x0000004b 0x57630000 0x004b5763 0x0000004b 0x57630000 0x88888888 0x08474759
|
||||
+ 0x69780849 0x49596d7a 0x0849495a 0x6d790848 0x48596c78 0x08484858 0x6a780848 0x48586a78
|
||||
+ 0x08484858 0x6c78084a 0x4a5b6d79 0x08474759 0x697a0848 0x48596b79 0x08484859 0x6c7a0848
|
||||
+ 0x48586c79 0x08484857 0x68770848 0x48576877 0x08484857 0x6a77084a 0x4a5a6a77 0x08464659
|
||||
+ 0x69790848 0x48586b79 0x08484858 0x6c7a0848 0x48596c79 0x08484857 0x68770848 0x48576877
|
||||
+ 0x08494958 0x6d7a084b 0x4b5c6c77 0x0847475a 0x6a7b0849 0x495a6e7c 0x0849495a 0x6e7c0849
|
||||
+ 0x495b6e7c 0x08494959 0x6a7a0849 0x49596a7a 0x084a4a5a 0x6f7d084b 0x4b5c6e7b 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x85848484
|
||||
+ 0xc3c4c4c5 0xc4c3c33f 0xc3c3c2c2 0xc2c2c03f 0xc3c3c3c4 0xc4c4c33f 0xc2c2c2c2 0xc1c3c1c1
|
||||
+ 0xc0c08282 0x83848686 0x88880000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00001111 0x00000000
|
||||
+ 0x8080f703 0x10808080 0x80050d13 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x000000a4 0xce000000 0x0000b684 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
|
||||
+ 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
|
||||
|
||||
led {
|
||||
led-active-low;
|
||||
--- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso
|
||||
@@ -55,6 +55,7 @@
|
||||
partition@c00000 {
|
||||
label = "fit";
|
||||
reg = <0xc00000 0x1400000>;
|
||||
+ compatible = "denx,fit";
|
||||
};
|
||||
};
|
||||
};
|
|
@ -0,0 +1,66 @@
|
|||
From 28f9a5e2a3f5441ab5594669ed82da11e32277a9 Mon Sep 17 00:00:00 2001
|
||||
From: Kristian Evensen <kristian.evensen@gmail.com>
|
||||
Date: Mon, 30 Apr 2018 14:38:01 +0200
|
||||
Subject: [PATCH] phy: phy-mtk-tphy: Add hifsys-support
|
||||
|
||||
---
|
||||
drivers/phy/mediatek/phy-mtk-tphy.c | 20 ++++++++++++++++++++
|
||||
1 file changed, 20 insertions(+)
|
||||
|
||||
--- a/drivers/phy/mediatek/phy-mtk-tphy.c
|
||||
+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
|
||||
@@ -17,6 +17,8 @@
|
||||
#include <linux/phy/phy.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
+#include <linux/mfd/syscon.h>
|
||||
+#include <linux/regmap.h>
|
||||
|
||||
#include "phy-mtk-io.h"
|
||||
|
||||
@@ -264,6 +266,9 @@
|
||||
|
||||
#define TPHY_CLKS_CNT 2
|
||||
|
||||
+#define HIF_SYSCFG1 0x14
|
||||
+#define HIF_SYSCFG1_PHY2_MASK (0x3 << 20)
|
||||
+
|
||||
enum mtk_phy_version {
|
||||
MTK_PHY_V1 = 1,
|
||||
MTK_PHY_V2,
|
||||
@@ -331,6 +336,7 @@ struct mtk_tphy {
|
||||
void __iomem *sif_base; /* only shared sif */
|
||||
const struct mtk_phy_pdata *pdata;
|
||||
struct mtk_phy_instance **phys;
|
||||
+ struct regmap *hif;
|
||||
int nphys;
|
||||
int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
|
||||
int src_coef; /* coefficient for slew rate calibrate */
|
||||
@@ -596,6 +602,10 @@ static void pcie_phy_instance_init(struc
|
||||
if (tphy->pdata->version != MTK_PHY_V1)
|
||||
return;
|
||||
|
||||
+ if (tphy->hif)
|
||||
+ regmap_update_bits(tphy->hif, HIF_SYSCFG1,
|
||||
+ HIF_SYSCFG1_PHY2_MASK, 0);
|
||||
+
|
||||
mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG0,
|
||||
P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H,
|
||||
FIELD_PREP(P3A_RG_XTAL_EXT_PE1H, 0x2) |
|
||||
@@ -1241,6 +1251,16 @@ static int mtk_tphy_probe(struct platfor
|
||||
&tphy->src_coef);
|
||||
}
|
||||
|
||||
+ if (of_find_property(np, "mediatek,phy-switch", NULL)) {
|
||||
+ tphy->hif = syscon_regmap_lookup_by_phandle(np,
|
||||
+ "mediatek,phy-switch");
|
||||
+ if (IS_ERR(tphy->hif)) {
|
||||
+ dev_err(&pdev->dev,
|
||||
+ "missing \"mediatek,phy-switch\" phandle\n");
|
||||
+ return PTR_ERR(tphy->hif);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
port = 0;
|
||||
for_each_child_of_node(np, child_np) {
|
||||
struct mtk_phy_instance *instance;
|
|
@ -0,0 +1,65 @@
|
|||
From 11db447f257231e08065989100311df57b7f1f1c Mon Sep 17 00:00:00 2001
|
||||
From: Daniel Golle <daniel@makrotopia.org>
|
||||
Date: Sat, 26 Aug 2023 21:06:14 +0100
|
||||
Subject: [PATCH] pinctrl: mediatek: mt7981: add additional uart groups
|
||||
|
||||
Add uart2_0_tx_rx (pin 4, 5) and uart1_2 (pins 9, 10) groups.
|
||||
|
||||
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||
---
|
||||
drivers/pinctrl/mediatek/pinctrl-mt7981.c | 16 +++++++++++++---
|
||||
1 file changed, 13 insertions(+), 3 deletions(-)
|
||||
|
||||
--- a/drivers/pinctrl/mediatek/pinctrl-mt7981.c
|
||||
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7981.c
|
||||
@@ -611,6 +611,9 @@ static int mt7981_wo0_jtag_1_funcs[] = {
|
||||
static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, };
|
||||
static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, };
|
||||
|
||||
+static int mt7981_uart2_0_tx_rx_pins[] = { 4, 5, };
|
||||
+static int mt7981_uart2_0_tx_rx_funcs[] = { 3, 3, };
|
||||
+
|
||||
/* GBE_LED0 */
|
||||
static int mt7981_gbe_led0_pins[] = { 8, };
|
||||
static int mt7981_gbe_led0_funcs[] = { 3, };
|
||||
@@ -731,6 +734,9 @@ static int mt7981_uart1_0_funcs[] = { 4,
|
||||
static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, };
|
||||
static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, };
|
||||
|
||||
+static int mt7981_uart1_2_pins[] = { 9, 10, };
|
||||
+static int mt7981_uart1_2_funcs[] = { 2, 2, };
|
||||
+
|
||||
/* UART2 */
|
||||
static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, };
|
||||
static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, };
|
||||
@@ -805,6 +811,8 @@ static const struct group_desc mt7981_gr
|
||||
PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0),
|
||||
/* @GPIO(4,7) WM_JTAG(3) */
|
||||
PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0),
|
||||
+ /* @GPIO(4,5) WM_JTAG(4) */
|
||||
+ PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7981_uart2_0_tx_rx),
|
||||
/* @GPIO(8) GBE_LED0(3) */
|
||||
PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0),
|
||||
/* @GPIO(4,6) PTA_EXT(4) */
|
||||
@@ -861,6 +869,8 @@ static const struct group_desc mt7981_gr
|
||||
PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0),
|
||||
/* @GPIO(26,29): UART1(2) */
|
||||
PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1),
|
||||
+ /* @GPIO(9,10): UART1(2) */
|
||||
+ PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2),
|
||||
/* @GPIO(22,25): UART1(3) */
|
||||
PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1),
|
||||
/* @GPIO(22,24) PTA_EXT(4) */
|
||||
@@ -922,9 +932,9 @@ static const struct group_desc mt7981_gr
|
||||
*/
|
||||
static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1",
|
||||
"wa_aice3", "wm_aice1_2", };
|
||||
-static const char *mt7981_uart_groups[] = { "wm_uart_0", "uart2_0",
|
||||
- "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", "net_wo0_uart_txd_2",
|
||||
- "uart1_0", "uart1_1", "uart2_1", "wm_aurt_1", "wm_aurt_2", "uart0", };
|
||||
+static const char *mt7981_uart_groups[] = { "net_wo0_uart_txd_0", "net_wo0_uart_txd_1",
|
||||
+ "net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart2_0",
|
||||
+ "uart2_0_tx_rx", "uart2_1", "wm_uart_0", "wm_aurt_1", "wm_aurt_2", };
|
||||
static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", };
|
||||
static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", };
|
||||
static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", };
|
|
@ -0,0 +1,24 @@
|
|||
--- a/drivers/clk/mediatek/clk-pll.c
|
||||
+++ b/drivers/clk/mediatek/clk-pll.c
|
||||
@@ -141,7 +141,10 @@ static void mtk_pll_set_rate_regs(struct
|
||||
pll->data->pcw_shift);
|
||||
val |= pcw << pll->data->pcw_shift;
|
||||
writel(val, pll->pcw_addr);
|
||||
- chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
|
||||
+ if (pll->data->pcw_chg_shift)
|
||||
+ chg = readl(pll->pcw_chg_addr) | BIT(pll->data->pcw_chg_shift);
|
||||
+ else
|
||||
+ chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
|
||||
writel(chg, pll->pcw_chg_addr);
|
||||
if (pll->tuner_addr)
|
||||
writel(val + 1, pll->tuner_addr);
|
||||
--- a/drivers/clk/mediatek/clk-pll.h
|
||||
+++ b/drivers/clk/mediatek/clk-pll.h
|
||||
@@ -42,6 +42,7 @@ struct mtk_pll_data {
|
||||
u32 pcw_reg;
|
||||
int pcw_shift;
|
||||
u32 pcw_chg_reg;
|
||||
+ int pcw_chg_shift;
|
||||
const struct mtk_pll_div_table *div_table;
|
||||
const char *parent_name;
|
||||
u32 en_reg;
|
|
@ -0,0 +1,34 @@
|
|||
--- a/drivers/mtd/nand/spi/core.c
|
||||
+++ b/drivers/mtd/nand/spi/core.c
|
||||
@@ -19,6 +19,7 @@
|
||||
#include <linux/string.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/spi/spi-mem.h>
|
||||
+#include <linux/mtd/mtk_bmt.h>
|
||||
|
||||
static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val)
|
||||
{
|
||||
@@ -1344,6 +1345,7 @@ static int spinand_probe(struct spi_mem
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
+ mtk_bmt_attach(mtd);
|
||||
ret = mtd_device_register(mtd, NULL, 0);
|
||||
if (ret)
|
||||
goto err_spinand_cleanup;
|
||||
@@ -1351,6 +1353,7 @@ static int spinand_probe(struct spi_mem
|
||||
return 0;
|
||||
|
||||
err_spinand_cleanup:
|
||||
+ mtk_bmt_detach(mtd);
|
||||
spinand_cleanup(spinand);
|
||||
|
||||
return ret;
|
||||
@@ -1369,6 +1372,7 @@ static int spinand_remove(struct spi_mem
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
+ mtk_bmt_detach(mtd);
|
||||
spinand_cleanup(spinand);
|
||||
|
||||
return 0;
|
|
@ -0,0 +1,10 @@
|
|||
--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
|
||||
@@ -552,6 +552,7 @@
|
||||
spi-tx-bus-width = <4>;
|
||||
spi-rx-bus-width = <4>;
|
||||
nand-ecc-engine = <&snfi>;
|
||||
+ mediatek,bmt-v2;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
|
@ -0,0 +1,41 @@
|
|||
From 4983a1517e7ddbc6f53fc07607e4ebeb51412843 Mon Sep 17 00:00:00 2001
|
||||
From: Sam Shih <sam.shih@mediatek.com>
|
||||
Date: Tue, 28 Feb 2023 19:59:22 +0800
|
||||
Subject: [PATCH 21/21] cpufreq: mediatek: Add support for MT7988
|
||||
|
||||
This add cpufreq support for mediatek MT7988 SoC.
|
||||
|
||||
The platform data of MT7988 is different from previous MediaTek SoCs,
|
||||
so we add a new compatible and platform data for it.
|
||||
|
||||
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
|
||||
---
|
||||
drivers/cpufreq/mediatek-cpufreq.c | 10 ++++++++++
|
||||
1 file changed, 10 insertions(+)
|
||||
|
||||
--- a/drivers/cpufreq/mediatek-cpufreq.c
|
||||
+++ b/drivers/cpufreq/mediatek-cpufreq.c
|
||||
@@ -709,6 +709,15 @@ static const struct mtk_cpufreq_platform
|
||||
.ccifreq_supported = false,
|
||||
};
|
||||
|
||||
+static const struct mtk_cpufreq_platform_data mt7988_platform_data = {
|
||||
+ .min_volt_shift = 100000,
|
||||
+ .max_volt_shift = 200000,
|
||||
+ .proc_max_volt = 900000,
|
||||
+ .sram_min_volt = 0,
|
||||
+ .sram_max_volt = 1150000,
|
||||
+ .ccifreq_supported = true,
|
||||
+};
|
||||
+
|
||||
static const struct mtk_cpufreq_platform_data mt8183_platform_data = {
|
||||
.min_volt_shift = 100000,
|
||||
.max_volt_shift = 200000,
|
||||
@@ -742,6 +751,7 @@ static const struct of_device_id mtk_cpu
|
||||
{ .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
|
||||
{ .compatible = "mediatek,mt7622", .data = &mt7622_platform_data },
|
||||
{ .compatible = "mediatek,mt7623", .data = &mt7623_platform_data },
|
||||
+ { .compatible = "mediatek,mt7988", .data = &mt7988_platform_data },
|
||||
{ .compatible = "mediatek,mt8167", .data = &mt8516_platform_data },
|
||||
{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
|
||||
{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
|
|
@ -0,0 +1,27 @@
|
|||
--- a/drivers/crypto/inside-secure/safexcel.c
|
||||
+++ b/drivers/crypto/inside-secure/safexcel.c
|
||||
@@ -600,6 +600,14 @@ static int safexcel_hw_init(struct safex
|
||||
val |= EIP197_MST_CTRL_TX_MAX_CMD(5);
|
||||
writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
|
||||
}
|
||||
+ /*
|
||||
+ * Set maximum number of TX commands to 2^4 = 16 for EIP97 HW2.1/HW2.3
|
||||
+ */
|
||||
+ else {
|
||||
+ val = 0;
|
||||
+ val |= EIP97_MST_CTRL_TX_MAX_CMD(4);
|
||||
+ writel(val, EIP197_HIA_AIC(priv) + EIP197_HIA_MST_CTRL);
|
||||
+ }
|
||||
|
||||
/* Configure wr/rd cache values */
|
||||
writel(EIP197_MST_CTRL_RD_CACHE(RD_CACHE_4BITS) |
|
||||
--- a/drivers/crypto/inside-secure/safexcel.h
|
||||
+++ b/drivers/crypto/inside-secure/safexcel.h
|
||||
@@ -315,6 +315,7 @@
|
||||
#define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0)
|
||||
#define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4)
|
||||
#define EIP197_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 20)
|
||||
+#define EIP97_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 4)
|
||||
#define EIP197_MST_CTRL_BYTE_SWAP BIT(24)
|
||||
#define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25)
|
||||
#define EIP197_MST_CTRL_BYTE_SWAP_BITS GENMASK(25, 24)
|
|
@ -0,0 +1,26 @@
|
|||
--- a/drivers/crypto/inside-secure/safexcel.h
|
||||
+++ b/drivers/crypto/inside-secure/safexcel.h
|
||||
@@ -737,6 +737,9 @@ enum safexcel_eip_version {
|
||||
/* Priority we use for advertising our algorithms */
|
||||
#define SAFEXCEL_CRA_PRIORITY 300
|
||||
|
||||
+/* System cache line size */
|
||||
+#define SYSTEM_CACHELINE_SIZE 64
|
||||
+
|
||||
/* SM3 digest result for zero length message */
|
||||
#define EIP197_SM3_ZEROM_HASH "\x1A\xB2\x1D\x83\x55\xCF\xA1\x7F" \
|
||||
"\x8E\x61\x19\x48\x31\xE8\x1A\x8F" \
|
||||
--- a/drivers/crypto/inside-secure/safexcel_hash.c
|
||||
+++ b/drivers/crypto/inside-secure/safexcel_hash.c
|
||||
@@ -55,9 +55,9 @@ struct safexcel_ahash_req {
|
||||
u8 block_sz; /* block size, only set once */
|
||||
u8 digest_sz; /* output digest size, only set once */
|
||||
__le32 state[SHA3_512_BLOCK_SIZE /
|
||||
- sizeof(__le32)] __aligned(sizeof(__le32));
|
||||
+ sizeof(__le32)] __aligned(SYSTEM_CACHELINE_SIZE);
|
||||
|
||||
- u64 len;
|
||||
+ u64 len __aligned(SYSTEM_CACHELINE_SIZE);
|
||||
u64 processed;
|
||||
|
||||
u8 cache[HASH_CACHE_SIZE] __aligned(sizeof(u32));
|
|
@ -0,0 +1,33 @@
|
|||
--- a/drivers/tty/serial/8250/8250.h
|
||||
+++ b/drivers/tty/serial/8250/8250.h
|
||||
@@ -86,6 +86,7 @@ struct serial8250_config {
|
||||
* STOP PARITY EPAR SPAR WLEN5 WLEN6
|
||||
*/
|
||||
#define UART_CAP_NOTEMT BIT(18) /* UART without interrupt on TEMT available */
|
||||
+#define UART_CAP_NMOD BIT(19) /* UART doesn't do termios */
|
||||
|
||||
#define UART_BUG_QUOT BIT(0) /* UART has buggy quot LSB */
|
||||
#define UART_BUG_TXEN BIT(1) /* UART has buggy TX IIR status */
|
||||
--- a/drivers/tty/serial/8250/8250_port.c
|
||||
+++ b/drivers/tty/serial/8250/8250_port.c
|
||||
@@ -287,7 +287,7 @@ static const struct serial8250_config ua
|
||||
.tx_loadsz = 16,
|
||||
.fcr = UART_FCR_ENABLE_FIFO |
|
||||
UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
|
||||
- .flags = UART_CAP_FIFO,
|
||||
+ .flags = UART_CAP_FIFO | UART_CAP_NMOD,
|
||||
},
|
||||
[PORT_NPCM] = {
|
||||
.name = "Nuvoton 16550",
|
||||
@@ -2770,6 +2770,11 @@ serial8250_do_set_termios(struct uart_po
|
||||
unsigned long flags;
|
||||
unsigned int baud, quot, frac = 0;
|
||||
|
||||
+ if (up->capabilities & UART_CAP_NMOD) {
|
||||
+ termios->c_cflag = 0;
|
||||
+ return;
|
||||
+ }
|
||||
+
|
||||
if (up->capabilities & UART_CAP_MINI) {
|
||||
termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
|
||||
if ((termios->c_cflag & CSIZE) == CS5 ||
|
|
@ -0,0 +1,25 @@
|
|||
--- a/drivers/net/phy/Kconfig
|
||||
+++ b/drivers/net/phy/Kconfig
|
||||
@@ -389,6 +389,12 @@ config ROCKCHIP_PHY
|
||||
help
|
||||
Currently supports the integrated Ethernet PHY.
|
||||
|
||||
+config RTL8367S_GSW
|
||||
+ tristate "rtl8367 Gigabit Switch support for mt7622"
|
||||
+ depends on NET_VENDOR_MEDIATEK
|
||||
+ help
|
||||
+ This driver supports rtl8367s in mt7622
|
||||
+
|
||||
config SMSC_PHY
|
||||
tristate "SMSC PHYs"
|
||||
help
|
||||
--- a/drivers/net/phy/Makefile
|
||||
+++ b/drivers/net/phy/Makefile
|
||||
@@ -98,6 +98,7 @@ obj-$(CONFIG_QSEMI_PHY) += qsemi.o
|
||||
obj-$(CONFIG_REALTEK_PHY) += realtek.o
|
||||
obj-$(CONFIG_RENESAS_PHY) += uPD60620.o
|
||||
obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o
|
||||
+obj-$(CONFIG_RTL8367S_GSW) += rtk/
|
||||
obj-$(CONFIG_SMSC_PHY) += smsc.o
|
||||
obj-$(CONFIG_STE10XP) += ste10Xp.o
|
||||
obj-$(CONFIG_TERANETICS_PHY) += teranetics.o
|
|
@ -0,0 +1,34 @@
|
|||
From: qizhong cheng <qizhong.cheng@mediatek.com>
|
||||
Date: Mon, 27 Dec 2021 21:31:10 +0800
|
||||
Subject: [PATCH] PCI: mediatek: Assert PERST# for 100ms for power and clock to
|
||||
stabilize
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
|
||||
2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
|
||||
be delayed 100ms (TPVPERL) for the power and clock to become stable.
|
||||
|
||||
Link: https://lore.kernel.org/r/20211227133110.14500-1-qizhong.cheng@mediatek.com
|
||||
Signed-off-by: qizhong cheng <qizhong.cheng@mediatek.com>
|
||||
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
|
||||
Acked-by: Pali Rohár <pali@kernel.org>
|
||||
---
|
||||
|
||||
--- a/drivers/pci/controller/pcie-mediatek.c
|
||||
+++ b/drivers/pci/controller/pcie-mediatek.c
|
||||
@@ -702,6 +702,13 @@ static int mtk_pcie_startup_port_v2(stru
|
||||
*/
|
||||
msleep(100);
|
||||
|
||||
+ /*
|
||||
+ * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
|
||||
+ * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
|
||||
+ * be delayed 100ms (TPVPERL) for the power and clock to become stable.
|
||||
+ */
|
||||
+ msleep(100);
|
||||
+
|
||||
/* De-assert PHY, PE, PIPE, MAC and configuration reset */
|
||||
val = readl(port->base + PCIE_RST_CTRL);
|
||||
val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
|
|
@ -0,0 +1,28 @@
|
|||
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||
@@ -849,6 +849,12 @@
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
+
|
||||
+ slot0: pcie@0,0 {
|
||||
+ reg = <0x0000 0 0 0 0>;
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+ };
|
||||
};
|
||||
|
||||
pcie1: pcie@1a145000 {
|
||||
@@ -887,6 +893,12 @@
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
+
|
||||
+ slot1: pcie@1,0 {
|
||||
+ reg = <0x0800 0 0 0 0>;
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+ };
|
||||
};
|
||||
|
||||
sata: sata@1a200000 {
|
|
@ -0,0 +1,23 @@
|
|||
From: Felix Fietkau <nbd@nbd.name>
|
||||
Date: Fri, 4 Sep 2020 18:33:27 +0200
|
||||
Subject: [PATCH] pcie-mediatek: fix clearing interrupt status
|
||||
|
||||
Clearing the status needs to happen after running the handler, otherwise
|
||||
we will get an extra spurious interrupt after the cause has been cleared
|
||||
|
||||
Signed-off-by: Felix Fietkau <nbd@nbd.name>
|
||||
---
|
||||
|
||||
--- a/drivers/pci/controller/pcie-mediatek.c
|
||||
+++ b/drivers/pci/controller/pcie-mediatek.c
|
||||
@@ -607,9 +607,9 @@ static void mtk_pcie_intr_handler(struct
|
||||
if (status & INTX_MASK) {
|
||||
for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
|
||||
/* Clear the INTx */
|
||||
- writel(1 << bit, port->base + PCIE_INT_STATUS);
|
||||
generic_handle_domain_irq(port->irq_domain,
|
||||
bit - INTX_SHIFT);
|
||||
+ writel(1 << bit, port->base + PCIE_INT_STATUS);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
From: Felix Fietkau <nbd@nbd.name>
|
||||
Date: Fri, 4 Sep 2020 18:42:42 +0200
|
||||
Subject: [PATCH] pci: pcie-mediatek: add support for coherent DMA
|
||||
|
||||
It improves performance by eliminating the need for a cache flush for DMA on
|
||||
attached devices
|
||||
|
||||
Signed-off-by: Felix Fietkau <nbd@nbd.name>
|
||||
---
|
||||
|
||||
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||
@@ -837,6 +837,9 @@
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
|
||||
status = "disabled";
|
||||
+ dma-coherent;
|
||||
+ mediatek,hifsys = <&hifsys>;
|
||||
+ mediatek,cci-control = <&cci_control2>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
@@ -881,6 +884,9 @@
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
|
||||
status = "disabled";
|
||||
+ dma-coherent;
|
||||
+ mediatek,hifsys = <&hifsys>;
|
||||
+ mediatek,cci-control = <&cci_control2>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
--- a/drivers/pci/controller/pcie-mediatek.c
|
||||
+++ b/drivers/pci/controller/pcie-mediatek.c
|
||||
@@ -20,6 +20,7 @@
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_pci.h>
|
||||
#include <linux/of_platform.h>
|
||||
+#include <linux/of_address.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/phy/phy.h>
|
||||
#include <linux/platform_device.h>
|
||||
@@ -139,6 +140,11 @@
|
||||
#define PCIE_LINK_STATUS_V2 0x804
|
||||
#define PCIE_PORT_LINKUP_V2 BIT(10)
|
||||
|
||||
+/* DMA channel mapping */
|
||||
+#define HIFSYS_DMA_AG_MAP 0x008
|
||||
+#define HIFSYS_DMA_AG_MAP_PCIE0 BIT(0)
|
||||
+#define HIFSYS_DMA_AG_MAP_PCIE1 BIT(1)
|
||||
+
|
||||
struct mtk_pcie_port;
|
||||
|
||||
/**
|
||||
@@ -1054,6 +1060,27 @@ static int mtk_pcie_setup(struct mtk_pci
|
||||
struct mtk_pcie_port *port, *tmp;
|
||||
int err, slot;
|
||||
|
||||
+ if (of_dma_is_coherent(node)) {
|
||||
+ struct regmap *con;
|
||||
+ u32 mask;
|
||||
+
|
||||
+ con = syscon_regmap_lookup_by_phandle(node,
|
||||
+ "mediatek,cci-control");
|
||||
+ /* enable CPU/bus coherency */
|
||||
+ if (!IS_ERR(con))
|
||||
+ regmap_write(con, 0, 3);
|
||||
+
|
||||
+ con = syscon_regmap_lookup_by_phandle(node,
|
||||
+ "mediatek,hifsys");
|
||||
+ if (IS_ERR(con)) {
|
||||
+ dev_err(dev, "missing hifsys node\n");
|
||||
+ return PTR_ERR(con);
|
||||
+ }
|
||||
+
|
||||
+ mask = HIFSYS_DMA_AG_MAP_PCIE0 | HIFSYS_DMA_AG_MAP_PCIE1;
|
||||
+ regmap_update_bits(con, HIFSYS_DMA_AG_MAP, mask, mask);
|
||||
+ }
|
||||
+
|
||||
slot = of_get_pci_domain_nr(dev->of_node);
|
||||
if (slot < 0) {
|
||||
for_each_available_child_of_node(node, child) {
|
|
@ -0,0 +1,27 @@
|
|||
From: Jip de Beer <gpk6x3591g0l@opayq.com>
|
||||
Date: Sun, 9 Jan 2022 13:14:04 +0100
|
||||
Subject: [PATCH] mediatek mt7622: fix 300mhz typo in dts
|
||||
|
||||
The lowest frequency should be 300MHz, since that is the label
|
||||
assigned to the OPP in the mt7622.dtsi device tree, while there is one
|
||||
missing zero in the actual value.
|
||||
|
||||
To be clear, the lowest frequency should be 300MHz instead of 30MHz.
|
||||
|
||||
As mentioned @dangowrt on the OpenWrt forum there is no benefit in
|
||||
leaving 30MHz as the lowest frequency.
|
||||
|
||||
Signed-off-by: Jip de Beer <gpk6x3591g0l@opayq.com>
|
||||
Signed-off-by: Fritz D. Ansel <fdansel@yandex.ru>
|
||||
---
|
||||
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||
@@ -24,7 +24,7 @@
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
opp-300000000 {
|
||||
- opp-hz = /bits/ 64 <30000000>;
|
||||
+ opp-hz = /bits/ 64 <300000000>;
|
||||
opp-microvolt = <950000>;
|
||||
};
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
||||
@@ -23,11 +23,17 @@
|
||||
cpu_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
opp-shared;
|
||||
- opp-300000000 {
|
||||
- opp-hz = /bits/ 64 <300000000>;
|
||||
- opp-microvolt = <950000>;
|
||||
- };
|
||||
-
|
||||
+ /* Due to the bug described at the link below, remove the 300 MHz clock to avoid a low
|
||||
+ * voltage condition that can cause a hang when rebooting the RT3200/E8450.
|
||||
+ *
|
||||
+ * https://forum.openwrt.org/t/belkin-rt3200-linksys-e8450-wifi-ax-discussion/94302/1490
|
||||
+ *
|
||||
+ * opp-300000000 {
|
||||
+ * opp-hz = /bits/ 64 <300000000>;
|
||||
+ * opp-microvolt = <950000>;
|
||||
+ * };
|
||||
+ *
|
||||
+ */
|
||||
opp-437500000 {
|
||||
opp-hz = /bits/ 64 <437500000>;
|
||||
opp-microvolt = <1000000>;
|
|
@ -0,0 +1,63 @@
|
|||
From a969b663c866129ed9eb217785a6574fbe826f1d Mon Sep 17 00:00:00 2001
|
||||
From: Daniel Golle <daniel@makrotopia.org>
|
||||
Date: Thu, 6 Apr 2023 23:36:50 +0100
|
||||
Subject: [PATCH] net: phy: mxl-gpy: don't use SGMII AN if using phylink
|
||||
|
||||
MAC drivers using phylink expect SGMII in-band-status to be switched off
|
||||
when attached to a PHY. Make sure this is the case also for mxl-gpy which
|
||||
keeps SGMII in-band-status in case of SGMII interface mode is used.
|
||||
|
||||
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||
---
|
||||
drivers/net/phy/mxl-gpy.c | 19 ++++++++++++++++---
|
||||
1 file changed, 16 insertions(+), 3 deletions(-)
|
||||
|
||||
--- a/drivers/net/phy/mxl-gpy.c
|
||||
+++ b/drivers/net/phy/mxl-gpy.c
|
||||
@@ -367,8 +367,11 @@ static bool gpy_2500basex_chk(struct phy
|
||||
|
||||
phydev->speed = SPEED_2500;
|
||||
phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
|
||||
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
|
||||
- VSPEC1_SGMII_CTRL_ANEN, 0);
|
||||
+
|
||||
+ if (!phydev->phylink)
|
||||
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
|
||||
+ VSPEC1_SGMII_CTRL_ANEN, 0);
|
||||
+
|
||||
return true;
|
||||
}
|
||||
|
||||
@@ -392,6 +395,14 @@ static int gpy_config_aneg(struct phy_de
|
||||
u32 adv;
|
||||
int ret;
|
||||
|
||||
+ /* Disable SGMII auto-negotiation if using phylink */
|
||||
+ if (phydev->phylink) {
|
||||
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
|
||||
+ VSPEC1_SGMII_CTRL_ANEN, 0);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
if (phydev->autoneg == AUTONEG_DISABLE) {
|
||||
/* Configure half duplex with genphy_setup_forced,
|
||||
* because genphy_c45_pma_setup_forced does not support.
|
||||
@@ -482,6 +493,8 @@ static void gpy_update_interface(struct
|
||||
switch (phydev->speed) {
|
||||
case SPEED_2500:
|
||||
phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
|
||||
+ if (phydev->phylink)
|
||||
+ break;
|
||||
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
|
||||
VSPEC1_SGMII_CTRL_ANEN, 0);
|
||||
if (ret < 0)
|
||||
@@ -493,7 +506,7 @@ static void gpy_update_interface(struct
|
||||
case SPEED_100:
|
||||
case SPEED_10:
|
||||
phydev->interface = PHY_INTERFACE_MODE_SGMII;
|
||||
- if (gpy_sgmii_aneg_en(phydev))
|
||||
+ if (phydev->phylink || gpy_sgmii_aneg_en(phydev))
|
||||
break;
|
||||
/* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed
|
||||
* if ANEG is disabled (in 2500-BaseX mode).
|
|
@ -0,0 +1,39 @@
|
|||
From 128dc09b0af36772062142ce9e85b19c84ac789a Mon Sep 17 00:00:00 2001
|
||||
From: Daniel Golle <daniel@makrotopia.org>
|
||||
Date: Tue, 28 Feb 2023 17:53:37 +0000
|
||||
Subject: [PATCH] net: phy: add driver for MediaTek 2.5G PHY
|
||||
|
||||
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||
---
|
||||
drivers/net/phy/Kconfig | 7 ++
|
||||
drivers/net/phy/Makefile | 1 +
|
||||
drivers/net/phy/mediatek-2p5ge.c | 220 +++++++++++++++++++++++++++++++
|
||||
3 files changed, 226 insertions(+)
|
||||
create mode 100644 drivers/net/phy/mediatek-2p5ge.c
|
||||
|
||||
--- a/drivers/net/phy/Kconfig
|
||||
+++ b/drivers/net/phy/Kconfig
|
||||
@@ -326,6 +326,13 @@ config MEDIATEK_GE_SOC_PHY
|
||||
present in the SoCs efuse and will dynamically calibrate VCM
|
||||
(common-mode voltage) during startup.
|
||||
|
||||
+config MEDIATEK_2P5G_PHY
|
||||
+ tristate "MediaTek 2.5G Ethernet PHY"
|
||||
+ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
|
||||
+ default NET_MEDIATEK_SOC
|
||||
+ help
|
||||
+ Supports the MediaTek 2.5G Ethernet PHY.
|
||||
+
|
||||
config MICREL_PHY
|
||||
tristate "Micrel PHYs"
|
||||
depends on PTP_1588_CLOCK_OPTIONAL
|
||||
--- a/drivers/net/phy/Makefile
|
||||
+++ b/drivers/net/phy/Makefile
|
||||
@@ -83,6 +83,7 @@ obj-$(CONFIG_MARVELL_10G_PHY) += marvell
|
||||
obj-$(CONFIG_MARVELL_PHY) += marvell.o
|
||||
obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o
|
||||
obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o
|
||||
+obj-$(CONFIG_MEDIATEK_2P5G_PHY) += mediatek-2p5ge.o
|
||||
obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o
|
||||
obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o
|
||||
obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o
|
|
@ -0,0 +1,45 @@
|
|||
From 3bf827929a44c17bfb1bf1000b143c02ce26a929 Mon Sep 17 00:00:00 2001
|
||||
From: Daniel Golle <daniel@makrotopia.org>
|
||||
Date: Sat, 26 Aug 2023 21:56:51 +0100
|
||||
Subject: [PATCH] i2c: mt65xx: allow optional pmic clock
|
||||
|
||||
Using the I2C host controller on the MT7981 SoC requires 4 clocks to
|
||||
be enabled. One of them, the pmic clk, is only enabled in case
|
||||
'mediatek,have-pmic' is also set which has other consequences which
|
||||
are not desired in this case.
|
||||
|
||||
Allow defining a pmic clk even in case the 'mediatek,have-pmic' propterty
|
||||
is not present and the bus is not used to connect to a pmic, but may
|
||||
still require to enable the pmic clock.
|
||||
|
||||
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||
---
|
||||
drivers/i2c/busses/i2c-mt65xx.c | 12 ++++++++----
|
||||
1 file changed, 8 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/drivers/i2c/busses/i2c-mt65xx.c
|
||||
+++ b/drivers/i2c/busses/i2c-mt65xx.c
|
||||
@@ -1444,15 +1444,19 @@ static int mtk_i2c_probe(struct platform
|
||||
if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk))
|
||||
return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_ARB].clk);
|
||||
|
||||
+ i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get_optional(&pdev->dev, "pmic");
|
||||
+ if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) {
|
||||
+ dev_err(&pdev->dev, "cannot get pmic clock\n");
|
||||
+ return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk);
|
||||
+ }
|
||||
+
|
||||
if (i2c->have_pmic) {
|
||||
- i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = devm_clk_get(&pdev->dev, "pmic");
|
||||
- if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk)) {
|
||||
+ if (!i2c->clocks[I2C_MT65XX_CLK_PMIC].clk) {
|
||||
dev_err(&pdev->dev, "cannot get pmic clock\n");
|
||||
- return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_PMIC].clk);
|
||||
+ return -ENODEV;
|
||||
}
|
||||
speed_clk = I2C_MT65XX_CLK_PMIC;
|
||||
} else {
|
||||
- i2c->clocks[I2C_MT65XX_CLK_PMIC].clk = NULL;
|
||||
speed_clk = I2C_MT65XX_CLK_MAIN;
|
||||
}
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
|
||||
@@ -314,7 +314,7 @@
|
||||
/* Attention: GPIO 90 is used to switch between PCIe@1,0 and
|
||||
* SATA functions. i.e. output-high: PCIe, output-low: SATA
|
||||
*/
|
||||
- asm_sel {
|
||||
+ asmsel: asm_sel {
|
||||
gpio-hog;
|
||||
gpios = <90 GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-sata.dtso
|
||||
@@ -0,0 +1,31 @@
|
||||
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
|
||||
+
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+
|
||||
+/dts-v1/;
|
||||
+/plugin/;
|
||||
+
|
||||
+/ {
|
||||
+ compatible = "bananapi,bpi-r64", "mediatek,mt7622";
|
||||
+
|
||||
+ fragment@0 {
|
||||
+ target = <&asmsel>;
|
||||
+ __overlay__ {
|
||||
+ gpios = <90 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ fragment@1 {
|
||||
+ target = <&sata>;
|
||||
+ __overlay__ {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ fragment@2 {
|
||||
+ target = <&sata_phy>;
|
||||
+ __overlay__ {
|
||||
+ status = "okay";
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-pcie1.dtso
|
||||
@@ -0,0 +1,17 @@
|
||||
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
|
||||
+
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+
|
||||
+/dts-v1/;
|
||||
+/plugin/;
|
||||
+
|
||||
+/ {
|
||||
+ compatible = "bananapi,bpi-r64", "mediatek,mt7622";
|
||||
+
|
||||
+ fragment@0 {
|
||||
+ target = <&asmsel>;
|
||||
+ __overlay__ {
|
||||
+ gpios = <90 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
|
@ -0,0 +1,54 @@
|
|||
--- a/arch/arm/Kconfig
|
||||
+++ b/arch/arm/Kconfig
|
||||
@@ -1589,6 +1589,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
|
||||
|
||||
endchoice
|
||||
|
||||
+config CMDLINE_OVERRIDE
|
||||
+ bool "Use alternative cmdline from device tree"
|
||||
+ help
|
||||
+ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can
|
||||
+ be used, this is not a good option for kernels that are shared across
|
||||
+ devices. This setting enables using "chosen/cmdline-override" as the
|
||||
+ cmdline if it exists in the device tree.
|
||||
+
|
||||
config CMDLINE
|
||||
string "Default kernel command string"
|
||||
default ""
|
||||
--- a/drivers/of/fdt.c
|
||||
+++ b/drivers/of/fdt.c
|
||||
@@ -1187,6 +1187,17 @@ int __init early_init_dt_scan_chosen(cha
|
||||
if (p != NULL && l > 0)
|
||||
strlcat(cmdline, p, min_t(int, strlen(cmdline) + (int)l, COMMAND_LINE_SIZE));
|
||||
|
||||
+ /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different
|
||||
+ * device tree option of chosen/bootargs-override. This is
|
||||
+ * helpful on boards where u-boot sets bootargs, and is unable
|
||||
+ * to be modified.
|
||||
+ */
|
||||
+#ifdef CONFIG_CMDLINE_OVERRIDE
|
||||
+ p = of_get_flat_dt_prop(node, "bootargs-override", &l);
|
||||
+ if (p != NULL && l > 0)
|
||||
+ strlcpy(cmdline, p, min((int)l, COMMAND_LINE_SIZE));
|
||||
+#endif
|
||||
+
|
||||
handle_cmdline:
|
||||
/*
|
||||
* CONFIG_CMDLINE is meant to be a default in case nothing else
|
||||
--- a/arch/arm64/Kconfig
|
||||
+++ b/arch/arm64/Kconfig
|
||||
@@ -2221,6 +2221,14 @@ config CMDLINE_FORCE
|
||||
|
||||
endchoice
|
||||
|
||||
+config CMDLINE_OVERRIDE
|
||||
+ bool "Use alternative cmdline from device tree"
|
||||
+ help
|
||||
+ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can
|
||||
+ be used, this is not a good option for kernels that are shared across
|
||||
+ devices. This setting enables using "chosen/cmdline-override" as the
|
||||
+ cmdline if it exists in the device tree.
|
||||
+
|
||||
config EFI_STUB
|
||||
bool
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
|
||||
@@ -641,5 +641,28 @@
|
||||
};
|
||||
|
||||
&wmac {
|
||||
+ mediatek,eeprom-data = <0x22760500 0x0 0x0 0x0
|
||||
+ 0x0 0x0 0x0 0x0
|
||||
+ 0x0 0x0 0x0 0x0
|
||||
+ 0x0 0x44000020 0x0 0x10002000
|
||||
+ 0x4400 0x4000000 0x0 0x0
|
||||
+ 0x200000b3 0x40b6c3c3 0x26000000 0x41c42600
|
||||
+ 0x41c4 0x26000000 0xc0c52600 0x0
|
||||
+ 0x0 0x0 0x0 0x0
|
||||
+ 0x0 0x0 0x0 0x0
|
||||
+ 0x0 0x0 0x0 0x0
|
||||
+ 0x0 0x0 0x0 0x0
|
||||
+ 0x0 0x0 0x0 0xc6c6
|
||||
+ 0xc3c3c2c1 0xc300c3 0x818181 0x83c1c182
|
||||
+ 0x83838382 0x0 0x0 0x0
|
||||
+ 0x0 0x0 0x0 0x0
|
||||
+ 0x84002e00 0x90000087 0x8a000000 0x0
|
||||
+ 0x0 0x0 0x0 0x0
|
||||
+ 0x0 0x0 0x0 0x0
|
||||
+ 0xb000009 0x0 0x0 0x0
|
||||
+ 0x0 0x0 0x0 0x0
|
||||
+ 0x0 0x0 0x0 0x0
|
||||
+ 0x0 0x0 0x0 0x7707>;
|
||||
+
|
||||
status = "okay";
|
||||
};
|
|
@ -0,0 +1,18 @@
|
|||
--- a/drivers/spi/spi-mt65xx.c
|
||||
+++ b/drivers/spi/spi-mt65xx.c
|
||||
@@ -1225,8 +1225,15 @@ static int mtk_spi_probe(struct platform
|
||||
if (ret < 0)
|
||||
return dev_err_probe(dev, ret, "failed to enable hclk\n");
|
||||
|
||||
+ ret = clk_prepare_enable(mdata->sel_clk);
|
||||
+ if (ret < 0) {
|
||||
+ clk_disable_unprepare(mdata->spi_hclk);
|
||||
+ return dev_err_probe(dev, ret, "failed to enable sel_clk\n");
|
||||
+ }
|
||||
+
|
||||
ret = clk_prepare_enable(mdata->spi_clk);
|
||||
if (ret < 0) {
|
||||
+ clk_disable_unprepare(mdata->sel_clk);
|
||||
clk_disable_unprepare(mdata->spi_hclk);
|
||||
return dev_err_probe(dev, ret, "failed to enable spi_clk\n");
|
||||
}
|
|
@ -0,0 +1,44 @@
|
|||
From 3cf212c4ce6cd72c09bc47f35f539ba0afd4d106 Mon Sep 17 00:00:00 2001
|
||||
Message-Id: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org>
|
||||
From: Lorenzo Bianconi <lorenzo@kernel.org>
|
||||
Date: Sun, 12 Mar 2023 16:40:31 +0100
|
||||
Subject: [PATCH net-next 1/2] net: ethernet: mtk_wed: rename
|
||||
mtk_wed_get_memory_region in mtk_wed_get_reserved_memory_region
|
||||
|
||||
This is a preliminary patch to move wed ilm/dlm and cpuboot properties in
|
||||
dedicated dts nodes.
|
||||
|
||||
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
|
||||
---
|
||||
drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 8 ++++----
|
||||
1 file changed, 4 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
|
||||
+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
|
||||
@@ -215,8 +215,8 @@ int mtk_wed_mcu_msg_update(struct mtk_we
|
||||
}
|
||||
|
||||
static int
|
||||
-mtk_wed_get_memory_region(struct mtk_wed_wo *wo,
|
||||
- struct mtk_wed_wo_memory_region *region)
|
||||
+mtk_wed_get_reserved_memory_region(struct mtk_wed_wo *wo,
|
||||
+ struct mtk_wed_wo_memory_region *region)
|
||||
{
|
||||
struct reserved_mem *rmem;
|
||||
struct device_node *np;
|
||||
@@ -311,13 +311,13 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
|
||||
|
||||
/* load firmware region metadata */
|
||||
for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
|
||||
- ret = mtk_wed_get_memory_region(wo, &mem_region[i]);
|
||||
+ ret = mtk_wed_get_reserved_memory_region(wo, &mem_region[i]);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
wo->boot.name = "wo-boot";
|
||||
- ret = mtk_wed_get_memory_region(wo, &wo->boot);
|
||||
+ ret = mtk_wed_get_reserved_memory_region(wo, &wo->boot);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
From 247e566e3459481f1fa98733534bfed767e18b42 Mon Sep 17 00:00:00 2001
|
||||
Message-Id: <247e566e3459481f1fa98733534bfed767e18b42.1678620342.git.lorenzo@kernel.org>
|
||||
From: Lorenzo Bianconi <lorenzo@kernel.org>
|
||||
Date: Sat, 11 Mar 2023 16:32:41 +0100
|
||||
Subject: [PATCH net-next] arm64: dts: mt7986: move cpuboot in a dedicated node
|
||||
|
||||
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
|
||||
---
|
||||
arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 21 +++++++++++----------
|
||||
1 file changed, 11 insertions(+), 10 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
|
||||
@@ -121,12 +121,6 @@
|
||||
reg = <0 0x151f8000 0 0x2000>;
|
||||
no-map;
|
||||
};
|
||||
-
|
||||
- wo_boot: wo-boot@15194000 {
|
||||
- reg = <0 0x15194000 0 0x1000>;
|
||||
- no-map;
|
||||
- };
|
||||
-
|
||||
};
|
||||
|
||||
timer {
|
||||
@@ -518,10 +512,11 @@
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
|
||||
memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
|
||||
- <&wo_data>, <&wo_boot>;
|
||||
+ <&wo_data>;
|
||||
memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
|
||||
- "wo-data", "wo-boot";
|
||||
+ "wo-data";
|
||||
mediatek,wo-ccif = <&wo_ccif0>;
|
||||
+ mediatek,wo-cpuboot = <&wo_cpuboot>;
|
||||
};
|
||||
|
||||
wed1: wed@15011000 {
|
||||
@@ -531,10 +526,11 @@
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
|
||||
memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
|
||||
- <&wo_data>, <&wo_boot>;
|
||||
+ <&wo_data>;
|
||||
memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
|
||||
- "wo-data", "wo-boot";
|
||||
+ "wo-data";
|
||||
mediatek,wo-ccif = <&wo_ccif1>;
|
||||
+ mediatek,wo-cpuboot = <&wo_cpuboot>;
|
||||
};
|
||||
|
||||
wo_ccif0: syscon@151a5000 {
|
||||
@@ -551,6 +547,11 @@
|
||||
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
+ wo_cpuboot: syscon@15194000 {
|
||||
+ compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
|
||||
+ reg = <0 0x15194000 0 0x1000>;
|
||||
+ };
|
||||
+
|
||||
eth: ethernet@15100000 {
|
||||
compatible = "mediatek,mt7986-eth";
|
||||
reg = <0 0x15100000 0 0x80000>;
|
|
@ -0,0 +1,89 @@
|
|||
From f292d1bf83ec160bef2532b58aa08f5b71041923 Mon Sep 17 00:00:00 2001
|
||||
Message-Id: <f292d1bf83ec160bef2532b58aa08f5b71041923.1678716918.git.lorenzo@kernel.org>
|
||||
In-Reply-To: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org>
|
||||
References: <3cf212c4ce6cd72c09bc47f35f539ba0afd4d106.1678716918.git.lorenzo@kernel.org>
|
||||
From: Lorenzo Bianconi <lorenzo@kernel.org>
|
||||
Date: Sat, 11 Mar 2023 18:13:04 +0100
|
||||
Subject: [PATCH net-next 2/2] net: ethernet: mtk_wed: move cpuboot in a
|
||||
dedicated dts node
|
||||
|
||||
Since the cpuboot memory region is not part of the RAM SoC, move cpuboot
|
||||
in a deidicated syscon node.
|
||||
This patch helps to keep backward-compatibility with older version of
|
||||
uboot codebase where we have a limit of 8 reserved-memory dts child
|
||||
nodes.
|
||||
Keep backward-compatibility with older dts version where cpuboot was
|
||||
defined as reserved-memory child node.
|
||||
|
||||
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
|
||||
---
|
||||
drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 34 +++++++++++++++++----
|
||||
drivers/net/ethernet/mediatek/mtk_wed_wo.h | 3 +-
|
||||
2 files changed, 30 insertions(+), 7 deletions(-)
|
||||
|
||||
--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
|
||||
+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
|
||||
@@ -18,12 +18,23 @@
|
||||
|
||||
static u32 wo_r32(struct mtk_wed_wo *wo, u32 reg)
|
||||
{
|
||||
- return readl(wo->boot.addr + reg);
|
||||
+ u32 val;
|
||||
+
|
||||
+ if (!wo->boot_regmap)
|
||||
+ return readl(wo->boot.addr + reg);
|
||||
+
|
||||
+ if (regmap_read(wo->boot_regmap, reg, &val))
|
||||
+ val = ~0;
|
||||
+
|
||||
+ return val;
|
||||
}
|
||||
|
||||
static void wo_w32(struct mtk_wed_wo *wo, u32 reg, u32 val)
|
||||
{
|
||||
- writel(val, wo->boot.addr + reg);
|
||||
+ if (wo->boot_regmap)
|
||||
+ regmap_write(wo->boot_regmap, reg, val);
|
||||
+ else
|
||||
+ writel(val, wo->boot.addr + reg);
|
||||
}
|
||||
|
||||
static struct sk_buff *
|
||||
@@ -316,10 +327,21 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
|
||||
return ret;
|
||||
}
|
||||
|
||||
- wo->boot.name = "wo-boot";
|
||||
- ret = mtk_wed_get_reserved_memory_region(wo, &wo->boot);
|
||||
- if (ret)
|
||||
- return ret;
|
||||
+ wo->boot_regmap = syscon_regmap_lookup_by_phandle(wo->hw->node,
|
||||
+ "mediatek,wo-cpuboot");
|
||||
+ if (IS_ERR(wo->boot_regmap)) {
|
||||
+ if (wo->boot_regmap != ERR_PTR(-ENODEV))
|
||||
+ return PTR_ERR(wo->boot_regmap);
|
||||
+
|
||||
+ /* For backward compatibility, we need to check if cpu_boot
|
||||
+ * is defined through reserved memory property.
|
||||
+ */
|
||||
+ wo->boot_regmap = NULL;
|
||||
+ wo->boot.name = "wo-boot";
|
||||
+ ret = mtk_wed_get_reserved_memory_region(wo, &wo->boot);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+ }
|
||||
|
||||
/* set dummy cr */
|
||||
wed_w32(wo->hw->wed_dev, MTK_WED_SCR0 + 4 * MTK_WED_DUMMY_CR_FWDL,
|
||||
--- a/drivers/net/ethernet/mediatek/mtk_wed_wo.h
|
||||
+++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.h
|
||||
@@ -228,7 +228,8 @@ struct mtk_wed_wo_queue {
|
||||
|
||||
struct mtk_wed_wo {
|
||||
struct mtk_wed_hw *hw;
|
||||
- struct mtk_wed_wo_memory_region boot;
|
||||
+ struct mtk_wed_wo_memory_region boot; /* backward compatibility */
|
||||
+ struct regmap *boot_regmap;
|
||||
|
||||
struct mtk_wed_wo_queue q_tx;
|
||||
struct mtk_wed_wo_queue q_rx;
|
|
@ -0,0 +1,91 @@
|
|||
From f3565e6c2276411275e707a5442d3f69cc111273 Mon Sep 17 00:00:00 2001
|
||||
Message-Id: <f3565e6c2276411275e707a5442d3f69cc111273.1678718888.git.lorenzo@kernel.org>
|
||||
From: Lorenzo Bianconi <lorenzo@kernel.org>
|
||||
Date: Sun, 12 Mar 2023 18:51:47 +0100
|
||||
Subject: [PATCH net-next 1/3] net: ethernet: mtk_wed: move ilm a dedicated dts
|
||||
node
|
||||
|
||||
Since the ilm memory region is not part of the RAM SoC, move ilm in a
|
||||
deidicated syscon node.
|
||||
This patch helps to keep backward-compatibility with older version of
|
||||
uboot codebase where we have a limit of 8 reserved-memory dts child
|
||||
nodes.
|
||||
Keep backward-compatibility with older dts version where ilm was defined
|
||||
as reserved-memory child node.
|
||||
|
||||
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
|
||||
---
|
||||
drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 55 ++++++++++++++++++---
|
||||
1 file changed, 49 insertions(+), 6 deletions(-)
|
||||
|
||||
--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
|
||||
+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
|
||||
@@ -300,6 +300,52 @@ next:
|
||||
}
|
||||
|
||||
static int
|
||||
+mtk_wed_mcu_load_memory_regions(struct mtk_wed_wo *wo,
|
||||
+ struct mtk_wed_wo_memory_region *region)
|
||||
+{
|
||||
+ struct device_node *np;
|
||||
+ int ret;
|
||||
+
|
||||
+ /* firmware EMI memory region */
|
||||
+ ret = mtk_wed_get_reserved_memory_region(wo,
|
||||
+ ®ion[MTK_WED_WO_REGION_EMI]);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ /* firmware DATA memory region */
|
||||
+ ret = mtk_wed_get_reserved_memory_region(wo,
|
||||
+ ®ion[MTK_WED_WO_REGION_DATA]);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ np = of_parse_phandle(wo->hw->node, "mediatek,wo-ilm", 0);
|
||||
+ if (np) {
|
||||
+ struct mtk_wed_wo_memory_region *ilm_region;
|
||||
+ struct resource res;
|
||||
+
|
||||
+ ret = of_address_to_resource(np, 0, &res);
|
||||
+ of_node_put(np);
|
||||
+
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ ilm_region = ®ion[MTK_WED_WO_REGION_ILM];
|
||||
+ ilm_region->phy_addr = res.start;
|
||||
+ ilm_region->size = resource_size(&res);
|
||||
+ ilm_region->addr = devm_ioremap(wo->hw->dev, res.start,
|
||||
+ resource_size(&res));
|
||||
+
|
||||
+ return IS_ERR(ilm_region->addr) ? PTR_ERR(ilm_region->addr) : 0;
|
||||
+ }
|
||||
+
|
||||
+ /* For backward compatibility, we need to check if ILM
|
||||
+ * node is defined through reserved memory property.
|
||||
+ */
|
||||
+ return mtk_wed_get_reserved_memory_region(wo,
|
||||
+ ®ion[MTK_WED_WO_REGION_ILM]);
|
||||
+}
|
||||
+
|
||||
+static int
|
||||
mtk_wed_mcu_load_firmware(struct mtk_wed_wo *wo)
|
||||
{
|
||||
static struct mtk_wed_wo_memory_region mem_region[] = {
|
||||
@@ -320,12 +366,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
|
||||
u32 val, boot_cr;
|
||||
int ret, i;
|
||||
|
||||
- /* load firmware region metadata */
|
||||
- for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
|
||||
- ret = mtk_wed_get_reserved_memory_region(wo, &mem_region[i]);
|
||||
- if (ret)
|
||||
- return ret;
|
||||
- }
|
||||
+ ret = mtk_wed_mcu_load_memory_regions(wo, mem_region);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
|
||||
wo->boot_regmap = syscon_regmap_lookup_by_phandle(wo->hw->node,
|
||||
"mediatek,wo-cpuboot");
|
|
@ -0,0 +1,57 @@
|
|||
From b74ba226be2c45091b93bd49192bdd6d2178729e Mon Sep 17 00:00:00 2001
|
||||
Message-Id: <b74ba226be2c45091b93bd49192bdd6d2178729e.1678718888.git.lorenzo@kernel.org>
|
||||
In-Reply-To: <f3565e6c2276411275e707a5442d3f69cc111273.1678718888.git.lorenzo@kernel.org>
|
||||
References: <f3565e6c2276411275e707a5442d3f69cc111273.1678718888.git.lorenzo@kernel.org>
|
||||
From: Lorenzo Bianconi <lorenzo@kernel.org>
|
||||
Date: Mon, 13 Mar 2023 15:45:16 +0100
|
||||
Subject: [PATCH net-next 3/3] net: ethernet: mtk_wed: move dlm a dedicated dts
|
||||
node
|
||||
|
||||
Since the dlm memory region is not part of the RAM SoC, move dlm in a
|
||||
deidicated syscon node.
|
||||
This patch helps to keep backward-compatibility with older version of
|
||||
uboot codebase where we have a limit of 8 reserved-memory dts child
|
||||
nodes.
|
||||
Keep backward-compatibility with older dts version where dlm was defined
|
||||
as reserved-memory child node.
|
||||
|
||||
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
|
||||
---
|
||||
drivers/net/ethernet/mediatek/mtk_wed.c | 19 +++++++++++++++++++
|
||||
1 file changed, 19 insertions(+)
|
||||
|
||||
--- a/drivers/net/ethernet/mediatek/mtk_wed.c
|
||||
+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
|
||||
@@ -814,6 +814,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device
|
||||
struct device_node *np;
|
||||
int index;
|
||||
|
||||
+ np = of_parse_phandle(dev->hw->node, "mediatek,wo-dlm", 0);
|
||||
+ if (np) {
|
||||
+ struct resource res;
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = of_address_to_resource(np, 0, &res);
|
||||
+ of_node_put(np);
|
||||
+
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
+ dev->rro.miod_phys = res.start;
|
||||
+ goto out;
|
||||
+ }
|
||||
+
|
||||
+ /* For backward compatibility, we need to check if DLM
|
||||
+ * node is defined through reserved memory property.
|
||||
+ */
|
||||
index = of_property_match_string(dev->hw->node, "memory-region-names",
|
||||
"wo-dlm");
|
||||
if (index < 0)
|
||||
@@ -830,6 +848,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device
|
||||
return -ENODEV;
|
||||
|
||||
dev->rro.miod_phys = rmem->base;
|
||||
+out:
|
||||
dev->rro.fdbk_phys = MTK_WED_MIOD_COUNT + dev->rro.miod_phys;
|
||||
|
||||
return mtk_wed_rro_ring_alloc(dev, &dev->rro.ring,
|
|
@ -0,0 +1,83 @@
|
|||
From 01561065af5bf1d2a4244896d897e3a1eafbcd46 Mon Sep 17 00:00:00 2001
|
||||
Message-Id: <01561065af5bf1d2a4244896d897e3a1eafbcd46.1678717704.git.lorenzo@kernel.org>
|
||||
From: Lorenzo Bianconi <lorenzo@kernel.org>
|
||||
Date: Mon, 13 Mar 2023 15:10:56 +0100
|
||||
Subject: [PATCH net-next] arm64: dts: mt7986: move ilm in a dedicated node
|
||||
|
||||
Since the ilm memory region is not part of the RAM SoC, move ilm in a
|
||||
deidicated syscon node.
|
||||
This patch helps to keep backward-compatibility with older version of
|
||||
uboot codebase where we have a limit of 8 reserved-memory dts child
|
||||
nodes.
|
||||
|
||||
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
|
||||
---
|
||||
arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 34 +++++++++++------------
|
||||
1 file changed, 16 insertions(+), 18 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
|
||||
@@ -97,16 +97,6 @@
|
||||
no-map;
|
||||
};
|
||||
|
||||
- wo_ilm0: wo-ilm@151e0000 {
|
||||
- reg = <0 0x151e0000 0 0x8000>;
|
||||
- no-map;
|
||||
- };
|
||||
-
|
||||
- wo_ilm1: wo-ilm@151f0000 {
|
||||
- reg = <0 0x151f0000 0 0x8000>;
|
||||
- no-map;
|
||||
- };
|
||||
-
|
||||
wo_data: wo-data@4fd80000 {
|
||||
reg = <0 0x4fd80000 0 0x240000>;
|
||||
no-map;
|
||||
@@ -511,11 +501,10 @@
|
||||
reg = <0 0x15010000 0 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
|
||||
- <&wo_data>;
|
||||
- memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
|
||||
- "wo-data";
|
||||
+ memory-region = <&wo_emi0>, <&wo_dlm0>, <&wo_data>;
|
||||
+ memory-region-names = "wo-emi", "wo-dlm", "wo-data";
|
||||
mediatek,wo-ccif = <&wo_ccif0>;
|
||||
+ mediatek,wo-ilm = <&wo_ilm0>;
|
||||
mediatek,wo-cpuboot = <&wo_cpuboot>;
|
||||
};
|
||||
|
||||
@@ -525,11 +514,10 @@
|
||||
reg = <0 0x15011000 0 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
|
||||
- <&wo_data>;
|
||||
- memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
|
||||
- "wo-data";
|
||||
+ memory-region = <&wo_emi1>, <&wo_dlm1>, <&wo_data>;
|
||||
+ memory-region-names = "wo-emi", "wo-dlm", "wo-data";
|
||||
mediatek,wo-ccif = <&wo_ccif1>;
|
||||
+ mediatek,wo-ilm = <&wo_ilm1>;
|
||||
mediatek,wo-cpuboot = <&wo_cpuboot>;
|
||||
};
|
||||
|
||||
@@ -547,6 +535,16 @@
|
||||
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
+ wo_ilm0: syscon@151e0000 {
|
||||
+ compatible = "mediatek,mt7986-wo-ilm", "syscon";
|
||||
+ reg = <0 0x151e0000 0 0x8000>;
|
||||
+ };
|
||||
+
|
||||
+ wo_ilm1: syscon@151f0000 {
|
||||
+ compatible = "mediatek,mt7986-wo-ilm", "syscon";
|
||||
+ reg = <0 0x151f0000 0 0x8000>;
|
||||
+ };
|
||||
+
|
||||
wo_cpuboot: syscon@15194000 {
|
||||
compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
|
||||
reg = <0 0x15194000 0 0x1000>;
|
|
@ -0,0 +1,81 @@
|
|||
From 9f76be683a8ec498563c294bc1cc279468058302 Mon Sep 17 00:00:00 2001
|
||||
Message-Id: <9f76be683a8ec498563c294bc1cc279468058302.1678719283.git.lorenzo@kernel.org>
|
||||
From: Lorenzo Bianconi <lorenzo@kernel.org>
|
||||
Date: Mon, 13 Mar 2023 15:53:30 +0100
|
||||
Subject: [PATCH net-next] arm64: dts: mt7986: move dlm in a dedicated node
|
||||
|
||||
Since the dlm memory region is not part of the RAM SoC, move dlm in a
|
||||
deidicated syscon node.
|
||||
This patch helps to keep backward-compatibility with older version of
|
||||
uboot codebase where we have a limit of 8 reserved-memory dts child
|
||||
nodes.
|
||||
|
||||
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
|
||||
---
|
||||
arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 30 ++++++++++++-----------
|
||||
1 file changed, 16 insertions(+), 14 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
|
||||
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
|
||||
@@ -101,16 +101,6 @@
|
||||
reg = <0 0x4fd80000 0 0x240000>;
|
||||
no-map;
|
||||
};
|
||||
-
|
||||
- wo_dlm0: wo-dlm@151e8000 {
|
||||
- reg = <0 0x151e8000 0 0x2000>;
|
||||
- no-map;
|
||||
- };
|
||||
-
|
||||
- wo_dlm1: wo-dlm@151f8000 {
|
||||
- reg = <0 0x151f8000 0 0x2000>;
|
||||
- no-map;
|
||||
- };
|
||||
};
|
||||
|
||||
timer {
|
||||
@@ -501,10 +491,11 @@
|
||||
reg = <0 0x15010000 0 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- memory-region = <&wo_emi0>, <&wo_dlm0>, <&wo_data>;
|
||||
- memory-region-names = "wo-emi", "wo-dlm", "wo-data";
|
||||
+ memory-region = <&wo_emi0>, <&wo_data>;
|
||||
+ memory-region-names = "wo-emi", "wo-data";
|
||||
mediatek,wo-ccif = <&wo_ccif0>;
|
||||
mediatek,wo-ilm = <&wo_ilm0>;
|
||||
+ mediatek,wo-dlm = <&wo_dlm0>;
|
||||
mediatek,wo-cpuboot = <&wo_cpuboot>;
|
||||
};
|
||||
|
||||
@@ -514,10 +505,11 @@
|
||||
reg = <0 0x15011000 0 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- memory-region = <&wo_emi1>, <&wo_dlm1>, <&wo_data>;
|
||||
- memory-region-names = "wo-emi", "wo-dlm", "wo-data";
|
||||
+ memory-region = <&wo_emi1>, <&wo_data>;
|
||||
+ memory-region-names = "wo-emi", "wo-data";
|
||||
mediatek,wo-ccif = <&wo_ccif1>;
|
||||
mediatek,wo-ilm = <&wo_ilm1>;
|
||||
+ mediatek,wo-dlm = <&wo_dlm1>;
|
||||
mediatek,wo-cpuboot = <&wo_cpuboot>;
|
||||
};
|
||||
|
||||
@@ -545,6 +537,16 @@
|
||||
reg = <0 0x151f0000 0 0x8000>;
|
||||
};
|
||||
|
||||
+ wo_dlm0: syscon@151e8000 {
|
||||
+ compatible = "mediatek,mt7986-wo-dlm", "syscon";
|
||||
+ reg = <0 0x151e8000 0 0x2000>;
|
||||
+ };
|
||||
+
|
||||
+ wo_dlm1: syscon@151f8000 {
|
||||
+ compatible = "mediatek,mt7986-wo-dlm", "syscon";
|
||||
+ reg = <0 0x151f8000 0 0x2000>;
|
||||
+ };
|
||||
+
|
||||
wo_cpuboot: syscon@15194000 {
|
||||
compatible = "mediatek,mt7986-wo-cpuboot", "syscon";
|
||||
reg = <0 0x15194000 0 0x1000>;
|
3
build.sh
3
build.sh
|
@ -756,6 +756,9 @@ if [ "$OMR_KERNEL" = "6.6" ]; then
|
|||
find target/linux/x86 -type f -name Makefile -exec sed -i 's%KERNEL_PATCHVER:=5.15%KERNEL_PATCHVER:=6.6%g' {} \;
|
||||
find target/linux/x86 -type f -name Makefile -exec sed -i 's%KERNEL_PATCHVER:=6.1%KERNEL_PATCHVER:=6.6%g' {} \;
|
||||
echo "Done"
|
||||
echo "Set to kernel 6.6 for mediatek"
|
||||
find target/linux/mediatek -type f -name Makefile -exec sed -i 's%KERNEL_PATCHVER:=5.15%KERNEL_PATCHVER:=6.6%g' {} \;
|
||||
echo "Done"
|
||||
echo "CONFIG_VERSION_CODE=6.6" >> ".config"
|
||||
echo "# CONFIG_PACKAGE_kmod-gpio-button-hotplug is not set" >> ".config"
|
||||
echo "# CONFIG_PACKAGE_kmod-meraki-mx100 is not set" >> ".config"
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue