mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
Remove 5.15 support
This commit is contained in:
Ycarus (Yannick Chabanois)
parent
81a4caeb39
commit
f735d6c75a
141 changed files with 0 additions and 34820 deletions
File diff suppressed because it is too large
Load diff
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@ -1,24 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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include $(TOPDIR)/rules.mk
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BOARD:=rockchip
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BOARDNAME:=Rockchip
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FEATURES:=ext4 audio usb usbgadget display gpio fpu pci pcie rootfs-part boot-part squashfs
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SUBTARGETS:=armv8
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KERNEL_PATCHVER:=5.15
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KERNEL_TESTING_PATCHVER:=6.1
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define Target/Description
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Build firmware image for Rockchip SoC devices.
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endef
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include $(INCLUDE_DIR)/target.mk
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DEFAULT_PACKAGES += uboot-envtools partx-utils e2fsprogs mkf2fs kmod-gpio-button-hotplug \
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automount autocore-arm e2fsprogs ethtool haveged htop usb-modeswitch
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KERNELNAME:=Image dtbs
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$(eval $(call BuildTarget))
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@ -1,43 +0,0 @@
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#!/bin/sh
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. /lib/functions/leds.sh
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. /lib/functions/uci-defaults.sh
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board=$(board_name)
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boardname="${board##*,}"
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board_config_update
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case $board in
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friendlyarm,nanopi-r2c|\
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friendlyarm,nanopi-r2s|\
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xunlong,orangepi-r1-plus|\
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xunlong,orangepi-r1-plus-lts)
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ucidef_set_led_netdev "wan" "WAN" "$boardname:green:wan" "eth0"
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ucidef_set_led_netdev "lan" "LAN" "$boardname:green:lan" "eth1"
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;;
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friendlyarm,nanopi-r4s|\
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friendlyarm,nanopi-r4se|\
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sharevdi,guangmiao-g4c)
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ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth0"
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ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth1"
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;;
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friendlyarm,nanopi-r5c)
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ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth1"
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ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth0"
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;;
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friendlyarm,nanopi-r5s)
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ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth0"
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ucidef_set_led_netdev "lan1" "LAN1" "green:lan1" "eth1"
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ucidef_set_led_netdev "lan2" "LAN2" "green:lan2" "eth2"
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;;
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hinlink,opc-h66k|\
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hinlink,opc-h68k|\
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hinlink,opc-h69k)
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ucidef_set_led_netdev "wan" "WAN" "blue:net" "eth0"
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;;
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esac
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board_config_flush
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exit 0
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@ -1,128 +0,0 @@
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#!/bin/sh
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. /lib/functions/uci-defaults.sh
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. /lib/functions/system.sh
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rockchip_setup_interfaces()
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{
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local board="$1"
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case "$board" in
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ariaboard,photonicat|\
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dilusense,dlfr100|\
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ezpro,mrkaio-m68s|\
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ezpro,mrkaio-m68s-plus|\
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hinlink,opc-h66k|\
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friendlyarm,nanopi-r2c|\
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friendlyarm,nanopi-r2s|\
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friendlyarm,nanopi-r4s|\
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friendlyarm,nanopi-r4se|\
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rocktech,mpc1903|\
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sharevdi,h3399pc|\
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sharevdi,guangmiao-g4c|\
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xunlong,orangepi-r1-plus|\
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xunlong,orangepi-r1-plus-lts)
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ucidef_set_interfaces_lan_wan 'eth1' 'eth0'
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;;
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hinlink,opc-h68k|\
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hinlink,opc-h69k)
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ucidef_set_interfaces_lan_wan 'eth1 eth2 eth3' 'eth0'
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;;
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fastrhino,r66s|\
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firefly,rk3568-roc-pc|\
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friendlyarm,nanopi-r5c|\
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radxa,e25)
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ucidef_set_interfaces_lan_wan 'eth0' 'eth1'
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;;
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fastrhino,r68s)
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ucidef_set_interfaces_lan_wan 'eth0 eth2 eth3' 'eth1'
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;;
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friendlyarm,nanopi-r5s)
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ucidef_set_interfaces_lan_wan "eth1 eth2" "eth0"
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;;
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*)
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ucidef_set_interface_lan 'eth0'
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;;
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esac
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}
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generate_mac_from_mmc_cid()
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{
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local sd_hash=$(sha256sum /sys/class/block/mmcblk*/device/cid | head -n 1)
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local mac_base=$(macaddr_canonicalize "$(echo "${sd_hash}" | dd bs=1 count=12 2>/dev/null)")
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echo "$(macaddr_unsetbit_mc "$(macaddr_setbit_la "${mac_base}")")"
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}
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nanopi_r4s_get_mac()
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{
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local interface=$1
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local eeprom_path="/sys/bus/i2c/devices/2-0051/eeprom"
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local address
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if [ -f "$eeprom_path" ]; then
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address=$(get_mac_binary "$eeprom_path" 0xfa)
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if [ "$interface" = "lan" ]; then
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address=$(macaddr_setbit_la "$address")
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fi
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else
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address=$(generate_mac_from_mmc_cid)
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if [ "$interface" = "lan" ]; then
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address=$(macaddr_add "$address" 1)
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fi
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fi
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echo "$address"
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}
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rockchip_setup_macs()
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{
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local board="$1"
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local lan_mac=""
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local wan_mac=""
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local label_mac=""
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case "$board" in
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ariaboard,photonicat|\
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dilusense,dlfr100|\
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ezpro,mrkaio-m68s|\
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ezpro,mrkaio-m68s-plus|\
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hinlink,opc-h66k|\
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hinlink,opc-h68k|\
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hinlink,opc-h69k|\
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fastrhino,r66s|\
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fastrhino,r68s|\
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firefly,rk3568-roc-pc|\
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friendlyarm,nanopi-r2c|\
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friendlyarm,nanopi-r2s|\
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friendlyarm,nanopi-r5s|\
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friendlyarm,nanopi-r5c|\
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sharevdi,h3399pc|\
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sharevdi,guangmiao-g4c|\
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rocktech,mpc1903)
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wan_mac=$(generate_mac_from_mmc_cid)
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lan_mac=$(macaddr_add "$wan_mac" +1)
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;;
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friendlyarm,nanopi-r4s|\
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friendlyarm,nanopi-r4se)
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wan_mac=$(nanopi_r4s_get_mac wan)
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lan_mac=$(nanopi_r4s_get_mac lan)
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;;
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xunlong,orangepi-r1-plus|\
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xunlong,orangepi-r1-plus-lts)
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lan_mac=$(cat /sys/class/net/eth1/address)
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wan_mac=$(macaddr_add "$lan_mac" -1)
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;;
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esac
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[ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac
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[ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" $wan_mac
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[ -n "$label_mac" ] && ucidef_set_label_macaddr $label_mac
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}
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board_config_update
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board=$(board_name)
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rockchip_setup_interfaces $board
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rockchip_setup_macs $board
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board_config_flush
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exit 0
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@ -1,56 +0,0 @@
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#!/bin/sh
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[ "$ACTION" = add ] || exit
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get_device_irq() {
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local device="$1"
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local line
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local seconds
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# wait up to 10 seconds for the irq/device to appear
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for seconds in $(seq 0 9); do
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line=$(grep -m 1 "${device}\$" /proc/interrupts) && break
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sleep 1
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done
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echo ${line} | sed 's/:.*//'
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}
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set_interface_core() {
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local core_mask="$1"
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local interface="$2"
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local device="$3"
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[ -z "${device}" ] && device="$interface"
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local irq=$(get_device_irq "$device")
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echo "${core_mask}" > /proc/irq/${irq}/smp_affinity
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}
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case "$(board_name)" in
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fastrhino,r66s|\
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friendlyarm,nanopi-r5c|\
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firefly,rk3568-roc-pc)
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set_interface_core 2 "eth0"
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set_interface_core 4 "eth1"
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;;
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friendlyarm,nanopi-r2c|\
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friendlyarm,nanopi-r2s|\
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xunlong,orangepi-r1-plus|\
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xunlong,orangepi-r1-plus-lts)
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set_interface_core 2 "eth0"
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set_interface_core 4 "eth1" "xhci-hcd:usb3"
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;;
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friendlyarm,nanopi-r4s|\
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friendlyarm,nanopi-r4se|\
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sharevdi,guangmiao-g4c)
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set_interface_core 10 "eth0"
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set_interface_core 20 "eth1"
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;;
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friendlyarm,nanopi-r5s)
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set_interface_core 0 "eth0"
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set_interface_core 2 "eth1"
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set_interface_core 4 "eth2"
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;;
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esac
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@ -1,6 +0,0 @@
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#!/bin/sh
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if [ "${ACTION}" = "add" ]; then
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usbmode -s && sleep 5
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[ -n "$(cat /proc/net/wireless | grep wlan)" ] && wifi config && wifi
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fi
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@ -1,15 +0,0 @@
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#!/bin/sh /etc/rc.common
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# Copyright (C) 2006-2011 OpenWrt.org
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START=99
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. /lib/functions/system.sh
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boot() {
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case $(board_name) in
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rongpin,king3399)
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echo 50 > /sys/class/gpio/export && echo high > /sys/class/gpio/gpio50/direction
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echo 56 > /sys/class/gpio/export && echo high > /sys/class/gpio/gpio56/direction
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;;
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esac
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}
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@ -1,7 +0,0 @@
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#!/bin/sh
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uci -q batch <<-EOF >/dev/null
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set network.globals.packet_steering=1
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commit network
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EOF
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exit 0
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@ -1,16 +0,0 @@
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move_config() {
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local partdev
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. /lib/upgrade/common.sh
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if export_bootdevice && export_partdevice partdev 1; then
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if mount -o rw,noatime "/dev/$partdev" /mnt; then
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if [ -f "/mnt/$BACKUP_FILE" ]; then
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mv -f "/mnt/$BACKUP_FILE" /
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fi
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umount /mnt
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fi
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fi
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}
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boot_hook_add preinit_mount_root move_config
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@ -1,86 +0,0 @@
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platform_check_image() {
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local diskdev partdev diff
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export_bootdevice && export_partdevice diskdev 0 || {
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echo "Unable to determine upgrade device"
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return 1
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}
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get_partitions "/dev/$diskdev" bootdisk
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#extract the boot sector from the image
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get_image "$@" | dd of=/tmp/image.bs count=1 bs=512b 2>/dev/null
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get_partitions /tmp/image.bs image
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#compare tables
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diff="$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)"
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rm -f /tmp/image.bs /tmp/partmap.bootdisk /tmp/partmap.image
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|
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if [ -n "$diff" ]; then
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echo "Partition layout has changed. Full image will be written."
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ask_bool 0 "Abort" && exit 1
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return 0
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fi
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}
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platform_copy_config() {
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local partdev
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if export_partdevice partdev 1; then
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mount -o rw,noatime "/dev/$partdev" /mnt
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cp -af "$UPGRADE_BACKUP" "/mnt/$BACKUP_FILE"
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umount /mnt
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fi
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}
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platform_do_upgrade() {
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local diskdev partdev diff
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|
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export_bootdevice && export_partdevice diskdev 0 || {
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echo "Unable to determine upgrade device"
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return 1
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}
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|
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sync
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|
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if [ "$UPGRADE_OPT_SAVE_PARTITIONS" = "1" ]; then
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get_partitions "/dev/$diskdev" bootdisk
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|
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#extract the boot sector from the image
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get_image "$@" | dd of=/tmp/image.bs count=1 bs=512b
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get_partitions /tmp/image.bs image
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|
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#compare tables
|
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diff="$(grep -F -x -v -f /tmp/partmap.bootdisk /tmp/partmap.image)"
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else
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diff=1
|
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fi
|
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|
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if [ -n "$diff" ]; then
|
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get_image "$@" | dd of="/dev/$diskdev" bs=4096 conv=fsync
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|
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# Separate removal and addtion is necessary; otherwise, partition 1
|
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# will be missing if it overlaps with the old partition 2
|
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partx -d - "/dev/$diskdev"
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partx -a - "/dev/$diskdev"
|
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|
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return 0
|
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fi
|
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|
||||
#iterate over each partition from the image and write it to the boot disk
|
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while read part start size; do
|
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if export_partdevice partdev $part; then
|
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echo "Writing image to /dev/$partdev..."
|
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get_image "$@" | dd of="/dev/$partdev" ibs="512" obs=1M skip="$start" count="$size" conv=fsync
|
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else
|
||||
echo "Unable to find partition $part device, skipped."
|
||||
fi
|
||||
done < /tmp/partmap.image
|
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|
||||
#copy partition uuid
|
||||
echo "Writing new UUID to /dev/$diskdev..."
|
||||
get_image "$@" | dd of="/dev/$diskdev" bs=1 skip=440 count=4 seek=440 conv=fsync
|
||||
}
|
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|
|
@ -1,675 +0,0 @@
|
|||
CONFIG_64BIT=y
|
||||
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
|
||||
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
|
||||
CONFIG_ARCH_KEEP_MEMBLOCK=y
|
||||
CONFIG_ARCH_MMAP_RND_BITS=18
|
||||
CONFIG_ARCH_MMAP_RND_BITS_MAX=33
|
||||
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
|
||||
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
|
||||
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
|
||||
CONFIG_ARCH_PROC_KCORE_TEXT=y
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
|
||||
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
|
||||
CONFIG_ARCH_SPARSEMEM_ENABLE=y
|
||||
CONFIG_ARCH_STACKWALK=y
|
||||
CONFIG_ARCH_SUSPEND_POSSIBLE=y
|
||||
CONFIG_ARC_EMAC_CORE=y
|
||||
CONFIG_ARM64=y
|
||||
CONFIG_ARM64_4K_PAGES=y
|
||||
CONFIG_ARM64_CNP=y
|
||||
# CONFIG_ARM64_ERRATUM_1165522 is not set
|
||||
# CONFIG_ARM64_ERRATUM_1286807 is not set
|
||||
# CONFIG_ARM64_ERRATUM_1418040 is not set
|
||||
CONFIG_ARM64_ERRATUM_819472=y
|
||||
CONFIG_ARM64_ERRATUM_824069=y
|
||||
CONFIG_ARM64_ERRATUM_826319=y
|
||||
CONFIG_ARM64_ERRATUM_827319=y
|
||||
CONFIG_ARM64_ERRATUM_832075=y
|
||||
CONFIG_ARM64_ERRATUM_843419=y
|
||||
CONFIG_ARM64_ERRATUM_845719=y
|
||||
CONFIG_ARM64_ERRATUM_858921=y
|
||||
CONFIG_ARM64_HW_AFDBM=y
|
||||
CONFIG_ARM64_MODULE_PLTS=y
|
||||
CONFIG_ARM64_PAGE_SHIFT=12
|
||||
CONFIG_ARM64_PAN=y
|
||||
CONFIG_ARM64_PA_BITS=48
|
||||
CONFIG_ARM64_PA_BITS_48=y
|
||||
CONFIG_ARM64_PTR_AUTH=y
|
||||
CONFIG_ARM64_RAS_EXTN=y
|
||||
CONFIG_ARM64_SVE=y
|
||||
# CONFIG_ARM64_SW_TTBR0_PAN is not set
|
||||
CONFIG_ARM64_TAGGED_ADDR_ABI=y
|
||||
CONFIG_ARM64_UAO=y
|
||||
CONFIG_ARM64_VA_BITS=48
|
||||
# CONFIG_ARM64_VA_BITS_39 is not set
|
||||
CONFIG_ARM64_VA_BITS_48=y
|
||||
CONFIG_ARM64_VHE=y
|
||||
CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
|
||||
# CONFIG_ARMV8_DEPRECATED is not set
|
||||
CONFIG_ARM_AMBA=y
|
||||
CONFIG_ARM_ARCH_TIMER=y
|
||||
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
|
||||
CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
|
||||
CONFIG_ARM_CPUIDLE=y
|
||||
CONFIG_ARM_GIC=y
|
||||
CONFIG_ARM_GIC_V2M=y
|
||||
CONFIG_ARM_GIC_V3=y
|
||||
CONFIG_ARM_GIC_V3_ITS=y
|
||||
CONFIG_ARM_GIC_V3_ITS_PCI=y
|
||||
CONFIG_ARM_MHU=y
|
||||
CONFIG_ARM_PSCI_CPUIDLE=y
|
||||
CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
|
||||
CONFIG_ARM_PSCI_FW=y
|
||||
CONFIG_ARM_RK3328_DMC_DEVFREQ=y
|
||||
# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
|
||||
# CONFIG_ARM_SCMI_PROTOCOL is not set
|
||||
CONFIG_ARM_SCPI_CPUFREQ=y
|
||||
CONFIG_ARM_SCPI_POWER_DOMAIN=y
|
||||
CONFIG_ARM_SCPI_PROTOCOL=y
|
||||
CONFIG_ARM_SMMU=y
|
||||
CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
|
||||
# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
|
||||
CONFIG_ARM_SMMU_V3=y
|
||||
# CONFIG_ARM_SMMU_V3_SVA is not set
|
||||
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
CONFIG_BACKLIGHT_GPIO=y
|
||||
CONFIG_BACKLIGHT_PWM=y
|
||||
CONFIG_BLK_DEV_BSG=y
|
||||
CONFIG_BLK_DEV_BSGLIB=y
|
||||
# CONFIG_BLK_DEV_INITRD is not set
|
||||
CONFIG_BLK_DEV_INTEGRITY=y
|
||||
CONFIG_BLK_DEV_INTEGRITY_T10=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_NVME=y
|
||||
CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_BLK_MQ_PCI=y
|
||||
CONFIG_BLK_PM=y
|
||||
CONFIG_BLK_SCSI_REQUEST=y
|
||||
CONFIG_BLOCK_COMPAT=y
|
||||
CONFIG_BRCMSTB_GISB_ARB=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_BSD_PROCESS_ACCT_V3=y
|
||||
# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set
|
||||
# CONFIG_CHARGER_BQ25980 is not set
|
||||
CONFIG_CHARGER_GPIO=y
|
||||
CONFIG_CLKDEV_LOOKUP=y
|
||||
CONFIG_CLKSRC_MMIO=y
|
||||
CONFIG_CLK_PX30=y
|
||||
CONFIG_CLK_RK3036=y
|
||||
CONFIG_CLK_RK312X=y
|
||||
CONFIG_CLK_RK3188=y
|
||||
CONFIG_CLK_RK322X=y
|
||||
CONFIG_CLK_RK3308=y
|
||||
CONFIG_CLK_RK3328=y
|
||||
CONFIG_CLK_RK3368=y
|
||||
CONFIG_CLK_RK3399=y
|
||||
CONFIG_CLK_RV110X=y
|
||||
CONFIG_CLONE_BACKWARDS=y
|
||||
CONFIG_CMA=y
|
||||
CONFIG_CMA_ALIGNMENT=8
|
||||
CONFIG_CMA_AREAS=7
|
||||
# CONFIG_CMA_DEBUG is not set
|
||||
# CONFIG_CMA_DEBUGFS is not set
|
||||
CONFIG_CMA_SIZE_MBYTES=64
|
||||
# CONFIG_CMA_SIZE_SEL_MAX is not set
|
||||
CONFIG_CMA_SIZE_SEL_MBYTES=y
|
||||
# CONFIG_CMA_SIZE_SEL_MIN is not set
|
||||
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
|
||||
CONFIG_COMMON_CLK=y
|
||||
CONFIG_COMMON_CLK_RK808=y
|
||||
CONFIG_COMMON_CLK_ROCKCHIP=y
|
||||
CONFIG_COMMON_CLK_SCPI=y
|
||||
CONFIG_COMPAT=y
|
||||
CONFIG_COMPAT_32BIT_TIME=y
|
||||
CONFIG_COMPAT_BINFMT_ELF=y
|
||||
CONFIG_COMPAT_NETLINK_MESSAGES=y
|
||||
CONFIG_COMPAT_OLD_SIGACTION=y
|
||||
CONFIG_CONFIGFS_FS=y
|
||||
CONFIG_CONSOLE_TRANSLATIONS=y
|
||||
CONFIG_CONTIG_ALLOC=y
|
||||
CONFIG_CPUFREQ_DT=y
|
||||
CONFIG_CPUFREQ_DT_PLATDEV=y
|
||||
CONFIG_CPU_FREQ=y
|
||||
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
|
||||
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
|
||||
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
|
||||
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
|
||||
# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
|
||||
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
|
||||
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
|
||||
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
|
||||
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
|
||||
CONFIG_CPU_FREQ_STAT=y
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_CPU_IDLE_GOV_MENU=y
|
||||
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
|
||||
CONFIG_CPU_ISOLATION=y
|
||||
CONFIG_CPU_PM=y
|
||||
CONFIG_CPU_RMAP=y
|
||||
CONFIG_CPU_THERMAL=y
|
||||
CONFIG_CRASH_CORE=y
|
||||
CONFIG_CRASH_DUMP=y
|
||||
CONFIG_CRC16=y
|
||||
# CONFIG_CRC32_SARWATE is not set
|
||||
CONFIG_CRC32_SLICEBY8=y
|
||||
CONFIG_CRC_T10DIF=y
|
||||
CONFIG_CROSS_MEMORY_ATTACH=y
|
||||
CONFIG_CRYPTO_AEAD=y
|
||||
CONFIG_CRYPTO_AEAD2=y
|
||||
CONFIG_CRYPTO_CRC32=y
|
||||
CONFIG_CRYPTO_CRC32C=y
|
||||
CONFIG_CRYPTO_CRCT10DIF=y
|
||||
# CONFIG_CRYPTO_DEV_ROCKCHIP is not set
|
||||
CONFIG_CRYPTO_DRBG=y
|
||||
CONFIG_CRYPTO_DRBG_HMAC=y
|
||||
CONFIG_CRYPTO_DRBG_MENU=y
|
||||
CONFIG_CRYPTO_HASH=y
|
||||
CONFIG_CRYPTO_HASH2=y
|
||||
CONFIG_CRYPTO_JITTERENTROPY=y
|
||||
CONFIG_CRYPTO_MANAGER=y
|
||||
CONFIG_CRYPTO_MANAGER2=y
|
||||
CONFIG_CRYPTO_NULL2=y
|
||||
CONFIG_CRYPTO_RNG=y
|
||||
CONFIG_CRYPTO_RNG2=y
|
||||
CONFIG_CRYPTO_RNG_DEFAULT=y
|
||||
CONFIG_DCACHE_WORD_ACCESS=y
|
||||
CONFIG_DEBUG_BUGVERBOSE=y
|
||||
# CONFIG_DEVFREQ_GOV_PASSIVE is not set
|
||||
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
|
||||
CONFIG_DEVFREQ_GOV_POWERSAVE=y
|
||||
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
|
||||
CONFIG_DEVFREQ_GOV_USERSPACE=y
|
||||
# CONFIG_DEVFREQ_THERMAL is not set
|
||||
CONFIG_DEVMEM=y
|
||||
# CONFIG_DEVPORT is not set
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_DMA_CMA=y
|
||||
CONFIG_DMA_DIRECT_REMAP=y
|
||||
CONFIG_DMA_ENGINE=y
|
||||
CONFIG_DMA_OF=y
|
||||
CONFIG_DMA_OPS=y
|
||||
CONFIG_DMA_REMAP=y
|
||||
CONFIG_DMA_SHARED_BUFFER=y
|
||||
CONFIG_DNOTIFY=y
|
||||
# CONFIG_DRM_ROCKCHIP is not set
|
||||
CONFIG_DTC=y
|
||||
CONFIG_DT_IDLE_STATES=y
|
||||
CONFIG_DUMMY_CONSOLE=y
|
||||
CONFIG_DWMAC_DWC_QOS_ETH=y
|
||||
CONFIG_DWMAC_GENERIC=y
|
||||
CONFIG_DWMAC_ROCKCHIP=y
|
||||
CONFIG_EDAC_SUPPORT=y
|
||||
CONFIG_EEPROM_AT24=y
|
||||
CONFIG_EMAC_ROCKCHIP=y
|
||||
CONFIG_ENABLE_MUST_CHECK=y
|
||||
CONFIG_ENERGY_MODEL=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_EXT4_FS_POSIX_ACL=y
|
||||
CONFIG_EXTCON=y
|
||||
CONFIG_F2FS_FS=y
|
||||
CONFIG_FANOTIFY=y
|
||||
CONFIG_FHANDLE=y
|
||||
CONFIG_FIXED_PHY=y
|
||||
CONFIG_FIX_EARLYCON_MEM=y
|
||||
# CONFIG_FLATMEM_MANUAL is not set
|
||||
# CONFIG_FORTIFY_SOURCE is not set
|
||||
CONFIG_FRAME_POINTER=y
|
||||
CONFIG_FRAME_WARN=2048
|
||||
CONFIG_FS_IOMAP=y
|
||||
CONFIG_FS_MBCACHE=y
|
||||
CONFIG_FS_POSIX_ACL=y
|
||||
# CONFIG_FUJITSU_ERRATUM_010001 is not set
|
||||
CONFIG_FW_LOADER_PAGED_BUF=y
|
||||
CONFIG_GENERIC_ALLOCATOR=y
|
||||
CONFIG_GENERIC_ARCH_TOPOLOGY=y
|
||||
CONFIG_GENERIC_BUG=y
|
||||
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
|
||||
CONFIG_GENERIC_CPU_AUTOPROBE=y
|
||||
CONFIG_GENERIC_CPU_VULNERABILITIES=y
|
||||
CONFIG_GENERIC_CSUM=y
|
||||
CONFIG_GENERIC_EARLY_IOREMAP=y
|
||||
CONFIG_GENERIC_GETTIMEOFDAY=y
|
||||
CONFIG_GENERIC_IDLE_POLL_SETUP=y
|
||||
CONFIG_GENERIC_IRQ_CHIP=y
|
||||
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
|
||||
CONFIG_GENERIC_IRQ_MIGRATION=y
|
||||
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
|
||||
CONFIG_GENERIC_IRQ_SHOW=y
|
||||
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
|
||||
CONFIG_GENERIC_MSI_IRQ=y
|
||||
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_GENERIC_PCI_IOMAP=y
|
||||
CONFIG_GENERIC_PHY=y
|
||||
CONFIG_GENERIC_PINCONF=y
|
||||
CONFIG_GENERIC_SCHED_CLOCK=y
|
||||
CONFIG_GENERIC_SMP_IDLE_THREAD=y
|
||||
CONFIG_GENERIC_STRNCPY_FROM_USER=y
|
||||
CONFIG_GENERIC_STRNLEN_USER=y
|
||||
CONFIG_GENERIC_TIME_VSYSCALL=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIOLIB_IRQCHIP=y
|
||||
CONFIG_GPIO_DWAPB=y
|
||||
CONFIG_GPIO_GENERIC=y
|
||||
CONFIG_GPIO_GENERIC_PLATFORM=y
|
||||
CONFIG_HANDLE_DOMAIN_IRQ=y
|
||||
# CONFIG_HARDENED_USERCOPY is not set
|
||||
CONFIG_HARDIRQS_SW_RESEND=y
|
||||
CONFIG_HAS_DMA=y
|
||||
CONFIG_HAS_IOMEM=y
|
||||
CONFIG_HAS_IOPORT_MAP=y
|
||||
CONFIG_HID=y
|
||||
CONFIG_HID_GENERIC=y
|
||||
# CONFIG_HISI_HIKEY_USB is not set
|
||||
CONFIG_HOLES_IN_ZONE=y
|
||||
CONFIG_HOTPLUG_CPU=y
|
||||
CONFIG_HOTPLUG_PCI=y
|
||||
# CONFIG_HOTPLUG_PCI_CPCI is not set
|
||||
# CONFIG_HOTPLUG_PCI_PCIE is not set
|
||||
# CONFIG_HOTPLUG_PCI_SHPC is not set
|
||||
CONFIG_HUGETLBFS=y
|
||||
CONFIG_HUGETLB_PAGE=y
|
||||
CONFIG_HWMON=y
|
||||
CONFIG_HWSPINLOCK=y
|
||||
CONFIG_HW_CONSOLE=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_HW_RANDOM_ROCKCHIP=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_BOARDINFO=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_COMPAT=y
|
||||
CONFIG_I2C_HELPER_AUTO=y
|
||||
CONFIG_I2C_RK3X=y
|
||||
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
|
||||
CONFIG_INDIRECT_PIO=y
|
||||
CONFIG_INPUT=y
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_INPUT_FF_MEMLESS=y
|
||||
CONFIG_INPUT_KEYBOARD=y
|
||||
CONFIG_INPUT_LEDS=y
|
||||
CONFIG_INPUT_MATRIXKMAP=y
|
||||
# CONFIG_INPUT_MISC is not set
|
||||
# CONFIG_INPUT_RK805_PWRKEY is not set
|
||||
CONFIG_IOMMU_API=y
|
||||
# CONFIG_IOMMU_DEBUGFS is not set
|
||||
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
|
||||
CONFIG_IOMMU_DMA=y
|
||||
CONFIG_IOMMU_IOVA=y
|
||||
CONFIG_IOMMU_IO_PGTABLE=y
|
||||
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
|
||||
CONFIG_IOMMU_IO_PGTABLE_LPAE=y
|
||||
# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
|
||||
CONFIG_IOMMU_SUPPORT=y
|
||||
# CONFIG_IO_STRICT_DEVMEM is not set
|
||||
CONFIG_IO_URING=y
|
||||
CONFIG_IRQCHIP=y
|
||||
CONFIG_IRQ_DOMAIN=y
|
||||
CONFIG_IRQ_DOMAIN_HIERARCHY=y
|
||||
CONFIG_IRQ_FORCED_THREADING=y
|
||||
CONFIG_IRQ_MSI_IOMMU=y
|
||||
CONFIG_IRQ_TIME_ACCOUNTING=y
|
||||
CONFIG_IRQ_WORK=y
|
||||
CONFIG_JBD2=y
|
||||
CONFIG_JFFS2_ZLIB=y
|
||||
CONFIG_JUMP_LABEL=y
|
||||
CONFIG_KALLSYMS=y
|
||||
CONFIG_KEXEC_CORE=y
|
||||
CONFIG_KEXEC_FILE=y
|
||||
# CONFIG_KEXEC_SIG is not set
|
||||
CONFIG_KSM=y
|
||||
# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
|
||||
CONFIG_LEDS_GPIO=y
|
||||
# CONFIG_LEDS_LP50XX is not set
|
||||
CONFIG_LEDS_PWM=y
|
||||
CONFIG_LEDS_SYSCON=y
|
||||
CONFIG_LEDS_TRIGGER_CPU=y
|
||||
CONFIG_LEDS_TRIGGER_PANIC=y
|
||||
CONFIG_LEGACY_PTYS=y
|
||||
CONFIG_LEGACY_PTY_COUNT=16
|
||||
CONFIG_LIBCRC32C=y
|
||||
CONFIG_LIBFDT=y
|
||||
CONFIG_LLD_VERSION=0
|
||||
CONFIG_LOCALVERSION_AUTO=y
|
||||
CONFIG_LOCK_DEBUGGING_SUPPORT=y
|
||||
CONFIG_LOCK_SPIN_ON_OWNER=y
|
||||
CONFIG_LOG_BUF_SHIFT=19
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_MAGIC_SYSRQ_SERIAL=y
|
||||
CONFIG_MAILBOX=y
|
||||
# CONFIG_MAILBOX_TEST is not set
|
||||
CONFIG_MANDATORY_FILE_LOCKING=y
|
||||
CONFIG_MDIO_BUS=y
|
||||
CONFIG_MDIO_BUS_MUX=y
|
||||
CONFIG_MDIO_BUS_MUX_GPIO=y
|
||||
CONFIG_MDIO_BUS_MUX_MMIOREG=y
|
||||
CONFIG_MDIO_DEVICE=y
|
||||
CONFIG_MEMFD_CREATE=y
|
||||
CONFIG_MEMORY_ISOLATION=y
|
||||
CONFIG_MFD_CORE=y
|
||||
# CONFIG_MFD_KHADAS_MCU is not set
|
||||
CONFIG_MFD_RK808=y
|
||||
# CONFIG_MFD_ROHM_BD71828 is not set
|
||||
CONFIG_MFD_SYSCON=y
|
||||
CONFIG_MIGRATION=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_BLOCK=y
|
||||
CONFIG_MMC_BLOCK_MINORS=32
|
||||
CONFIG_MMC_CQHCI=y
|
||||
CONFIG_MMC_DW=y
|
||||
# CONFIG_MMC_DW_BLUEFIELD is not set
|
||||
# CONFIG_MMC_DW_EXYNOS is not set
|
||||
# CONFIG_MMC_DW_HI3798CV200 is not set
|
||||
# CONFIG_MMC_DW_K3 is not set
|
||||
# CONFIG_MMC_DW_PCI is not set
|
||||
CONFIG_MMC_DW_PLTFM=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_OF_ARASAN=y
|
||||
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
|
||||
# CONFIG_MMC_SDHCI_PCI is not set
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
CONFIG_MODULES_USE_ELF_RELA=y
|
||||
CONFIG_MOTORCOMM_PHY=y
|
||||
CONFIG_MQ_IOSCHED_DEADLINE=y
|
||||
# CONFIG_MTD_CFI is not set
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
|
||||
CONFIG_MTD_SPLIT_FIRMWARE=y
|
||||
CONFIG_MUTEX_SPIN_ON_OWNER=y
|
||||
CONFIG_NEED_DMA_MAP_STATE=y
|
||||
CONFIG_NEED_SG_DMA_LENGTH=y
|
||||
CONFIG_NET_FLOW_LIMIT=y
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NOP_USB_XCEIV=y
|
||||
CONFIG_NO_HZ_COMMON=y
|
||||
CONFIG_NO_HZ_IDLE=y
|
||||
CONFIG_NR_CPUS=256
|
||||
CONFIG_NVMEM=y
|
||||
CONFIG_NVMEM_SYSFS=y
|
||||
CONFIG_NVME_CORE=y
|
||||
# CONFIG_NVME_HWMON is not set
|
||||
# CONFIG_NVME_MULTIPATH is not set
|
||||
# CONFIG_NVME_TCP is not set
|
||||
CONFIG_OF=y
|
||||
CONFIG_OF_ADDRESS=y
|
||||
CONFIG_OF_DYNAMIC=y
|
||||
CONFIG_OF_EARLY_FLATTREE=y
|
||||
CONFIG_OF_FLATTREE=y
|
||||
CONFIG_OF_GPIO=y
|
||||
CONFIG_OF_IOMMU=y
|
||||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_KOBJ=y
|
||||
CONFIG_OF_MDIO=y
|
||||
CONFIG_OF_NET=y
|
||||
CONFIG_OF_OVERLAY=y
|
||||
CONFIG_OF_RESOLVE=y
|
||||
CONFIG_OLD_SIGSUSPEND3=y
|
||||
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
|
||||
CONFIG_PADATA=y
|
||||
CONFIG_PAGE_POOL=y
|
||||
# CONFIG_PANIC_ON_OOPS is not set
|
||||
CONFIG_PANIC_ON_OOPS_VALUE=0
|
||||
CONFIG_PANIC_TIMEOUT=0
|
||||
# CONFIG_PARTITION_ADVANCED is not set
|
||||
CONFIG_PARTITION_PERCPU=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCIEAER=y
|
||||
CONFIG_PCIEASPM=y
|
||||
CONFIG_PCIEASPM_DEFAULT=y
|
||||
# CONFIG_PCIEASPM_PERFORMANCE is not set
|
||||
# CONFIG_PCIEASPM_POWERSAVE is not set
|
||||
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
CONFIG_PCIE_PME=y
|
||||
CONFIG_PCIE_ROCKCHIP=y
|
||||
CONFIG_PCIE_ROCKCHIP_HOST=y
|
||||
CONFIG_PCI_DOMAINS=y
|
||||
CONFIG_PCI_DOMAINS_GENERIC=y
|
||||
CONFIG_PCI_MSI=y
|
||||
CONFIG_PCI_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_PCI_STUB=y
|
||||
CONFIG_PCS_XPCS=y
|
||||
CONFIG_PGTABLE_LEVELS=4
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHYLINK=y
|
||||
CONFIG_PHYS_ADDR_T_64BIT=y
|
||||
CONFIG_PHY_ROCKCHIP_DP=y
|
||||
# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
|
||||
CONFIG_PHY_ROCKCHIP_EMMC=y
|
||||
# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
|
||||
# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_PCIE=y
|
||||
CONFIG_PHY_ROCKCHIP_TYPEC=y
|
||||
CONFIG_PHY_ROCKCHIP_USB=y
|
||||
CONFIG_PINCTRL=y
|
||||
# CONFIG_PINCTRL_RK805 is not set
|
||||
CONFIG_PINCTRL_ROCKCHIP=y
|
||||
# CONFIG_PINCTRL_SINGLE is not set
|
||||
CONFIG_PL330_DMA=y
|
||||
CONFIG_PLATFORM_MHU=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_PM_CLK=y
|
||||
CONFIG_PM_DEVFREQ=y
|
||||
# CONFIG_PM_DEVFREQ_EVENT is not set
|
||||
CONFIG_PM_GENERIC_DOMAINS=y
|
||||
CONFIG_PM_GENERIC_DOMAINS_OF=y
|
||||
CONFIG_PM_OPP=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_POWER_SUPPLY_HWMON=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_PREEMPTION=y
|
||||
CONFIG_PREEMPT_COUNT=y
|
||||
# CONFIG_PREEMPT_NONE is not set
|
||||
CONFIG_PREEMPT_RCU=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
# CONFIG_PRINT_QUOTA_WARNING is not set
|
||||
CONFIG_PROC_PAGE_MONITOR=y
|
||||
CONFIG_PROC_VMCORE=y
|
||||
CONFIG_PWM=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_PWM_SYSFS=y
|
||||
# CONFIG_QFMT_V1 is not set
|
||||
# CONFIG_QFMT_V2 is not set
|
||||
CONFIG_QUEUED_RWLOCKS=y
|
||||
CONFIG_QUEUED_SPINLOCKS=y
|
||||
CONFIG_QUOTA=y
|
||||
CONFIG_QUOTACTL=y
|
||||
# CONFIG_QUOTA_NETLINK_INTERFACE is not set
|
||||
CONFIG_RAID_ATTRS=y
|
||||
CONFIG_RANDOMIZE_BASE=y
|
||||
CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
|
||||
CONFIG_RAS=y
|
||||
CONFIG_RATIONAL=y
|
||||
# CONFIG_RAVE_SP_CORE is not set
|
||||
CONFIG_RCU_CPU_STALL_TIMEOUT=21
|
||||
# CONFIG_RCU_EXPERT is not set
|
||||
CONFIG_RCU_NEED_SEGCBLIST=y
|
||||
CONFIG_RCU_STALL_COMMON=y
|
||||
CONFIG_RCU_TRACE=y
|
||||
CONFIG_REALTEK_PHY=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_REGMAP_I2C=y
|
||||
CONFIG_REGMAP_IRQ=y
|
||||
CONFIG_REGMAP_MMIO=y
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_FAN53555=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_REGULATOR_GPIO=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_REGULATOR_RK808=y
|
||||
# CONFIG_REGULATOR_RT4801 is not set
|
||||
# CONFIG_REGULATOR_RTMV20 is not set
|
||||
CONFIG_RELOCATABLE=y
|
||||
CONFIG_RESET_CONTROLLER=y
|
||||
CONFIG_RFS_ACCEL=y
|
||||
CONFIG_ROCKCHIP_EFUSE=y
|
||||
CONFIG_ROCKCHIP_GRF=y
|
||||
CONFIG_ROCKCHIP_IODOMAIN=y
|
||||
CONFIG_ROCKCHIP_IOMMU=y
|
||||
CONFIG_ROCKCHIP_MBOX=y
|
||||
# CONFIG_ROCKCHIP_OTP is not set
|
||||
CONFIG_ROCKCHIP_PHY=y
|
||||
CONFIG_ROCKCHIP_PM_DOMAINS=y
|
||||
# CONFIG_ROCKCHIP_SARADC is not set
|
||||
CONFIG_ROCKCHIP_THERMAL=y
|
||||
CONFIG_ROCKCHIP_TIMER=y
|
||||
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
|
||||
CONFIG_RPS=y
|
||||
CONFIG_RSEQ=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_RK808=y
|
||||
# CONFIG_RTC_DRV_RV3032 is not set
|
||||
CONFIG_RTC_I2C_AND_SPI=y
|
||||
CONFIG_RTC_NVMEM=y
|
||||
# CONFIG_RUNTIME_TESTING_MENU is not set
|
||||
CONFIG_RWSEM_SPIN_ON_OWNER=y
|
||||
CONFIG_SCHED_MC=y
|
||||
CONFIG_SCSI=y
|
||||
# CONFIG_SCSI_LOWLEVEL is not set
|
||||
# CONFIG_SCSI_PROC_FS is not set
|
||||
CONFIG_SCSI_SAS_ATTRS=y
|
||||
CONFIG_SCSI_SAS_HOST_SMP=y
|
||||
CONFIG_SCSI_SAS_LIBSAS=y
|
||||
# CONFIG_SECURITY_DMESG_RESTRICT is not set
|
||||
CONFIG_SENSORS_ARM_SCPI=y
|
||||
# CONFIG_SENSORS_MR75203 is not set
|
||||
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
CONFIG_SERIAL_8250_DWLIB=y
|
||||
CONFIG_SERIAL_8250_EXAR=y
|
||||
CONFIG_SERIAL_8250_EXTENDED=y
|
||||
CONFIG_SERIAL_8250_FSL=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=4
|
||||
CONFIG_SERIAL_8250_PCI=y
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
|
||||
CONFIG_SERIAL_8250_SHARE_IRQ=y
|
||||
CONFIG_SERIAL_AMBA_PL011=y
|
||||
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
|
||||
CONFIG_SERIAL_DEV_BUS=y
|
||||
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
|
||||
CONFIG_SERIAL_MCTRL_GPIO=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
CONFIG_SERIO=y
|
||||
CONFIG_SERIO_AMBAKMI=y
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
CONFIG_SG_POOL=y
|
||||
CONFIG_SIMPLE_PM_BUS=y
|
||||
CONFIG_SLUB_DEBUG=y
|
||||
CONFIG_SMP=y
|
||||
# CONFIG_SND_SOC_ROCKCHIP is not set
|
||||
CONFIG_SPARSEMEM=y
|
||||
CONFIG_SPARSEMEM_EXTREME=y
|
||||
CONFIG_SPARSEMEM_MANUAL=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_BITBANG=y
|
||||
CONFIG_SPI_DYNAMIC=y
|
||||
CONFIG_SPI_MASTER=y
|
||||
CONFIG_SPI_MEM=y
|
||||
CONFIG_SPI_ROCKCHIP=y
|
||||
CONFIG_SPI_SPIDEV=y
|
||||
# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
|
||||
CONFIG_SQUASHFS_DECOMP_SINGLE=y
|
||||
# CONFIG_SQUASHFS_EMBEDDED is not set
|
||||
CONFIG_SQUASHFS_FILE_CACHE=y
|
||||
# CONFIG_SQUASHFS_FILE_DIRECT is not set
|
||||
CONFIG_SRAM=y
|
||||
CONFIG_SRCU=y
|
||||
CONFIG_STACKPROTECTOR=y
|
||||
CONFIG_STACKPROTECTOR_STRONG=y
|
||||
# CONFIG_STAGING is not set
|
||||
CONFIG_STMMAC_ETH=y
|
||||
CONFIG_STMMAC_PLATFORM=y
|
||||
# CONFIG_STMMAC_SELFTESTS is not set
|
||||
CONFIG_STRICT_DEVMEM=y
|
||||
# CONFIG_STRIP_ASM_SYMS is not set
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_SWIOTLB=y
|
||||
CONFIG_SWPHY=y
|
||||
CONFIG_SYNC_FILE=y
|
||||
CONFIG_SYSCTL_EXCEPTION_TRACE=y
|
||||
CONFIG_SYSFS_SYSCALL=y
|
||||
CONFIG_SYSVIPC_COMPAT=y
|
||||
CONFIG_SYS_SUPPORTS_HUGETLBFS=y
|
||||
# CONFIG_TEXTSEARCH is not set
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
|
||||
CONFIG_THERMAL_EMULATION=y
|
||||
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
|
||||
CONFIG_THERMAL_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_HWMON=y
|
||||
CONFIG_THERMAL_OF=y
|
||||
CONFIG_THREAD_INFO_IN_TASK=y
|
||||
CONFIG_TICK_CPU_ACCOUNTING=y
|
||||
CONFIG_TIMER_OF=y
|
||||
CONFIG_TIMER_PROBE=y
|
||||
CONFIG_TRACE_CLOCK=y
|
||||
CONFIG_TRANSPARENT_HUGEPAGE=y
|
||||
CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
|
||||
# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
|
||||
CONFIG_TREE_RCU=y
|
||||
CONFIG_TREE_SRCU=y
|
||||
CONFIG_TYPEC=y
|
||||
# CONFIG_TYPEC_DP_ALTMODE is not set
|
||||
CONFIG_TYPEC_FUSB302=y
|
||||
# CONFIG_TYPEC_HD3SS3220 is not set
|
||||
# CONFIG_TYPEC_MUX_PI3USB30532 is not set
|
||||
# CONFIG_TYPEC_STUSB160X is not set
|
||||
# CONFIG_TYPEC_TCPCI is not set
|
||||
CONFIG_TYPEC_TCPM=y
|
||||
# CONFIG_TYPEC_TPS6598X is not set
|
||||
# CONFIG_UACCE is not set
|
||||
# CONFIG_UCLAMP_TASK is not set
|
||||
# CONFIG_UEVENT_HELPER is not set
|
||||
CONFIG_UNINLINE_SPIN_UNLOCK=y
|
||||
CONFIG_UNMAP_KERNEL_AT_EL0=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_COMMON=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_HOST=y
|
||||
CONFIG_USB_DWC3_OF_SIMPLE=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD_PLATFORM=y
|
||||
# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
|
||||
CONFIG_USB_HID=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_PHY=y
|
||||
CONFIG_USB_ROLE_SWITCH=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_ULPI_BUS=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_PLATFORM=y
|
||||
# CONFIG_VIRTIO_MENU is not set
|
||||
CONFIG_VMAP_STACK=y
|
||||
CONFIG_VM_EVENT_COUNTERS=y
|
||||
CONFIG_VT=y
|
||||
CONFIG_VT_CONSOLE=y
|
||||
CONFIG_VT_HW_CONSOLE_BINDING=y
|
||||
# CONFIG_WATCHDOG is not set
|
||||
CONFIG_XARRAY_MULTI=y
|
||||
CONFIG_XPS=y
|
||||
CONFIG_XXHASH=y
|
||||
CONFIG_XZ_DEC_ARM=y
|
||||
CONFIG_XZ_DEC_ARMTHUMB=y
|
||||
CONFIG_XZ_DEC_BCJ=y
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
CONFIG_ZONE_DMA32=y
|
||||
|
|
@ -1,686 +0,0 @@
|
|||
CONFIG_64BIT=y
|
||||
CONFIG_AF_UNIX_OOB=y
|
||||
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
|
||||
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
|
||||
CONFIG_ARCH_KEEP_MEMBLOCK=y
|
||||
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
|
||||
CONFIG_ARCH_MMAP_RND_BITS=18
|
||||
CONFIG_ARCH_MMAP_RND_BITS_MAX=33
|
||||
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
|
||||
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
|
||||
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
|
||||
CONFIG_ARCH_PROC_KCORE_TEXT=y
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_ARCH_SPARSEMEM_ENABLE=y
|
||||
CONFIG_ARCH_STACKWALK=y
|
||||
CONFIG_ARCH_SUSPEND_POSSIBLE=y
|
||||
CONFIG_ARCH_WANTS_NO_INSTR=y
|
||||
CONFIG_ARCH_WANTS_THP_SWAP=y
|
||||
CONFIG_ARC_EMAC_CORE=y
|
||||
CONFIG_ARM64=y
|
||||
CONFIG_ARM64_4K_PAGES=y
|
||||
CONFIG_ARM64_CNP=y
|
||||
CONFIG_ARM64_CRYPTO=y
|
||||
CONFIG_ARM64_EPAN=y
|
||||
CONFIG_ARM64_ERRATUM_819472=y
|
||||
CONFIG_ARM64_ERRATUM_824069=y
|
||||
CONFIG_ARM64_ERRATUM_826319=y
|
||||
CONFIG_ARM64_ERRATUM_827319=y
|
||||
CONFIG_ARM64_ERRATUM_832075=y
|
||||
CONFIG_ARM64_ERRATUM_843419=y
|
||||
CONFIG_ARM64_ERRATUM_845719=y
|
||||
CONFIG_ARM64_ERRATUM_858921=y
|
||||
CONFIG_ARM64_ERRATUM_1742098=y
|
||||
CONFIG_ARM64_HW_AFDBM=y
|
||||
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
|
||||
CONFIG_ARM64_MODULE_PLTS=y
|
||||
CONFIG_ARM64_PAGE_SHIFT=12
|
||||
CONFIG_ARM64_PAN=y
|
||||
CONFIG_ARM64_PA_BITS=48
|
||||
CONFIG_ARM64_PA_BITS_48=y
|
||||
CONFIG_ARM64_PTR_AUTH=y
|
||||
CONFIG_ARM64_PTR_AUTH_KERNEL=y
|
||||
CONFIG_ARM64_RAS_EXTN=y
|
||||
CONFIG_ARM64_SVE=y
|
||||
# CONFIG_ARM64_SW_TTBR0_PAN is not set
|
||||
CONFIG_ARM64_TAGGED_ADDR_ABI=y
|
||||
CONFIG_ARM64_VA_BITS=48
|
||||
# CONFIG_ARM64_VA_BITS_39 is not set
|
||||
CONFIG_ARM64_VA_BITS_48=y
|
||||
CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
|
||||
# CONFIG_ARMV8_DEPRECATED is not set
|
||||
CONFIG_ARM_AMBA=y
|
||||
CONFIG_ARM_ARCH_TIMER=y
|
||||
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
|
||||
CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
|
||||
CONFIG_ARM_CPUIDLE=y
|
||||
CONFIG_ARM_GIC=y
|
||||
CONFIG_ARM_GIC_V2M=y
|
||||
CONFIG_ARM_GIC_V3=y
|
||||
CONFIG_ARM_GIC_V3_ITS=y
|
||||
CONFIG_ARM_GIC_V3_ITS_PCI=y
|
||||
CONFIG_ARM_MHU=y
|
||||
# CONFIG_ARM_MHU_V2 is not set
|
||||
CONFIG_ARM_PSCI_CPUIDLE=y
|
||||
CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
|
||||
CONFIG_ARM_PSCI_FW=y
|
||||
CONFIG_ARM_RK3328_DMC_DEVFREQ=y
|
||||
# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
|
||||
# CONFIG_ARM_SCMI_CPUFREQ is not set
|
||||
CONFIG_ARM_SCMI_HAVE_SHMEM=y
|
||||
CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
|
||||
CONFIG_ARM_SCMI_POWER_DOMAIN=y
|
||||
CONFIG_ARM_SCMI_PROTOCOL=y
|
||||
CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
|
||||
CONFIG_ARM_SCMI_TRANSPORT_SMC=y
|
||||
CONFIG_ARM_SCPI_CPUFREQ=y
|
||||
CONFIG_ARM_SCPI_POWER_DOMAIN=y
|
||||
CONFIG_ARM_SCPI_PROTOCOL=y
|
||||
CONFIG_ARM_SMMU=y
|
||||
CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
|
||||
# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
|
||||
CONFIG_ARM_SMMU_V3=y
|
||||
# CONFIG_ARM_SMMU_V3_SVA is not set
|
||||
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
CONFIG_BACKLIGHT_GPIO=y
|
||||
CONFIG_BACKLIGHT_PWM=y
|
||||
CONFIG_BINARY_PRINTF=y
|
||||
CONFIG_BLK_DEV_BSG=y
|
||||
CONFIG_BLK_DEV_BSGLIB=y
|
||||
CONFIG_BLK_DEV_BSG_COMMON=y
|
||||
# CONFIG_BLK_DEV_INITRD is not set
|
||||
CONFIG_BLK_DEV_INTEGRITY=y
|
||||
CONFIG_BLK_DEV_INTEGRITY_T10=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_NVME=y
|
||||
CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_BLK_MQ_PCI=y
|
||||
CONFIG_BLK_PM=y
|
||||
CONFIG_BLOCK_COMPAT=y
|
||||
CONFIG_BRCMSTB_GISB_ARB=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_BSD_PROCESS_ACCT_V3=y
|
||||
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
|
||||
CONFIG_CHARGER_GPIO=y
|
||||
CONFIG_CLKSRC_MMIO=y
|
||||
CONFIG_CLK_PX30=y
|
||||
CONFIG_CLK_RK3308=y
|
||||
CONFIG_CLK_RK3328=y
|
||||
CONFIG_CLK_RK3368=y
|
||||
CONFIG_CLK_RK3399=y
|
||||
CONFIG_CLK_RK3568=y
|
||||
CONFIG_CLONE_BACKWARDS=y
|
||||
CONFIG_CMA=y
|
||||
CONFIG_CMA_ALIGNMENT=8
|
||||
CONFIG_CMA_AREAS=7
|
||||
# CONFIG_CMA_DEBUG is not set
|
||||
# CONFIG_CMA_DEBUGFS is not set
|
||||
CONFIG_CMA_SIZE_MBYTES=64
|
||||
# CONFIG_CMA_SIZE_SEL_MAX is not set
|
||||
CONFIG_CMA_SIZE_SEL_MBYTES=y
|
||||
# CONFIG_CMA_SIZE_SEL_MIN is not set
|
||||
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
|
||||
# CONFIG_CMA_SYSFS is not set
|
||||
CONFIG_COMMON_CLK=y
|
||||
CONFIG_COMMON_CLK_RK808=y
|
||||
CONFIG_COMMON_CLK_ROCKCHIP=y
|
||||
CONFIG_COMMON_CLK_SCMI=y
|
||||
CONFIG_COMMON_CLK_SCPI=y
|
||||
CONFIG_COMPAT=y
|
||||
CONFIG_COMPAT_32BIT_TIME=y
|
||||
CONFIG_COMPAT_BINFMT_ELF=y
|
||||
CONFIG_COMPAT_NETLINK_MESSAGES=y
|
||||
CONFIG_COMPAT_OLD_SIGACTION=y
|
||||
CONFIG_CONFIGFS_FS=y
|
||||
CONFIG_CONSOLE_TRANSLATIONS=y
|
||||
CONFIG_CONTIG_ALLOC=y
|
||||
CONFIG_CPUFREQ_DT=y
|
||||
CONFIG_CPUFREQ_DT_PLATDEV=y
|
||||
CONFIG_CPU_FREQ=y
|
||||
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
|
||||
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
|
||||
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
|
||||
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
|
||||
# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
|
||||
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
|
||||
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
|
||||
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
|
||||
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
|
||||
CONFIG_CPU_FREQ_STAT=y
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_CPU_IDLE_GOV_MENU=y
|
||||
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
|
||||
CONFIG_CPU_ISOLATION=y
|
||||
CONFIG_CPU_PM=y
|
||||
CONFIG_CPU_RMAP=y
|
||||
CONFIG_CPU_THERMAL=y
|
||||
CONFIG_CRASH_CORE=y
|
||||
CONFIG_CRASH_DUMP=y
|
||||
CONFIG_CRC16=y
|
||||
# CONFIG_CRC32_SARWATE is not set
|
||||
CONFIG_CRC32_SLICEBY8=y
|
||||
CONFIG_CRC_T10DIF=y
|
||||
CONFIG_CROSS_MEMORY_ATTACH=y
|
||||
CONFIG_CRYPTO_AES_ARM64=y
|
||||
CONFIG_CRYPTO_AES_ARM64_CE=y
|
||||
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
|
||||
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
|
||||
CONFIG_CRYPTO_CRC32=y
|
||||
CONFIG_CRYPTO_CRC32C=y
|
||||
CONFIG_CRYPTO_CRCT10DIF=y
|
||||
CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
|
||||
CONFIG_CRYPTO_CRYPTD=y
|
||||
CONFIG_CRYPTO_DEV_ROCKCHIP=y
|
||||
CONFIG_CRYPTO_GHASH_ARM64_CE=y
|
||||
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
|
||||
CONFIG_CRYPTO_RNG2=y
|
||||
CONFIG_CRYPTO_SIMD=y
|
||||
CONFIG_DCACHE_WORD_ACCESS=y
|
||||
CONFIG_DEBUG_BUGVERBOSE=y
|
||||
CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI=y
|
||||
# CONFIG_DEVFREQ_GOV_PASSIVE is not set
|
||||
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
|
||||
CONFIG_DEVFREQ_GOV_POWERSAVE=y
|
||||
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
|
||||
CONFIG_DEVFREQ_GOV_USERSPACE=y
|
||||
# CONFIG_DEVFREQ_THERMAL is not set
|
||||
CONFIG_DEVMEM=y
|
||||
# CONFIG_DEVPORT is not set
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_DMA_CMA=y
|
||||
CONFIG_DMA_DIRECT_REMAP=y
|
||||
CONFIG_DMA_ENGINE=y
|
||||
CONFIG_DMA_OF=y
|
||||
CONFIG_DMA_OPS=y
|
||||
CONFIG_DMA_REMAP=y
|
||||
CONFIG_DMA_SHARED_BUFFER=y
|
||||
CONFIG_DNOTIFY=y
|
||||
CONFIG_DTC=y
|
||||
CONFIG_DT_IDLE_STATES=y
|
||||
CONFIG_DUMMY_CONSOLE=y
|
||||
CONFIG_DWMAC_DWC_QOS_ETH=y
|
||||
CONFIG_DWMAC_GENERIC=y
|
||||
CONFIG_DWMAC_ROCKCHIP=y
|
||||
CONFIG_DW_WATCHDOG=y
|
||||
CONFIG_EDAC_SUPPORT=y
|
||||
CONFIG_EEPROM_AT24=y
|
||||
CONFIG_EMAC_ROCKCHIP=y
|
||||
CONFIG_ENERGY_MODEL=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_EXT4_FS_POSIX_ACL=y
|
||||
CONFIG_EXTCON=y
|
||||
CONFIG_F2FS_FS=y
|
||||
CONFIG_FANOTIFY=y
|
||||
CONFIG_FHANDLE=y
|
||||
CONFIG_FIXED_PHY=y
|
||||
CONFIG_FIX_EARLYCON_MEM=y
|
||||
# CONFIG_FORTIFY_SOURCE is not set
|
||||
CONFIG_FRAME_POINTER=y
|
||||
CONFIG_FRAME_WARN=2048
|
||||
CONFIG_FS_IOMAP=y
|
||||
CONFIG_FS_MBCACHE=y
|
||||
CONFIG_FS_POSIX_ACL=y
|
||||
CONFIG_FWNODE_MDIO=y
|
||||
CONFIG_FW_LOADER_PAGED_BUF=y
|
||||
CONFIG_GENERIC_ALLOCATOR=y
|
||||
CONFIG_GENERIC_ARCH_TOPOLOGY=y
|
||||
CONFIG_GENERIC_BUG=y
|
||||
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
|
||||
CONFIG_GENERIC_CPU_AUTOPROBE=y
|
||||
CONFIG_GENERIC_CPU_VULNERABILITIES=y
|
||||
CONFIG_GENERIC_CSUM=y
|
||||
CONFIG_GENERIC_EARLY_IOREMAP=y
|
||||
CONFIG_GENERIC_FIND_FIRST_BIT=y
|
||||
CONFIG_GENERIC_GETTIMEOFDAY=y
|
||||
CONFIG_GENERIC_IDLE_POLL_SETUP=y
|
||||
CONFIG_GENERIC_IRQ_CHIP=y
|
||||
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
|
||||
CONFIG_GENERIC_IRQ_MIGRATION=y
|
||||
CONFIG_GENERIC_IRQ_SHOW=y
|
||||
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
|
||||
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
|
||||
CONFIG_GENERIC_MSI_IRQ=y
|
||||
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_GENERIC_PCI_IOMAP=y
|
||||
CONFIG_GENERIC_PHY=y
|
||||
CONFIG_GENERIC_PINCONF=y
|
||||
CONFIG_GENERIC_SCHED_CLOCK=y
|
||||
CONFIG_GENERIC_SMP_IDLE_THREAD=y
|
||||
CONFIG_GENERIC_STRNCPY_FROM_USER=y
|
||||
CONFIG_GENERIC_STRNLEN_USER=y
|
||||
CONFIG_GENERIC_TIME_VSYSCALL=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIOLIB_IRQCHIP=y
|
||||
CONFIG_GPIO_CDEV=y
|
||||
CONFIG_GPIO_DWAPB=y
|
||||
CONFIG_GPIO_GENERIC=y
|
||||
CONFIG_GPIO_GENERIC_PLATFORM=y
|
||||
CONFIG_GPIO_ROCKCHIP=y
|
||||
CONFIG_HANDLE_DOMAIN_IRQ=y
|
||||
# CONFIG_HARDENED_USERCOPY is not set
|
||||
CONFIG_HARDIRQS_SW_RESEND=y
|
||||
CONFIG_HAS_DMA=y
|
||||
CONFIG_HAS_IOMEM=y
|
||||
CONFIG_HAS_IOPORT_MAP=y
|
||||
CONFIG_HID=y
|
||||
CONFIG_HID_GENERIC=y
|
||||
CONFIG_HOTPLUG_CPU=y
|
||||
CONFIG_HOTPLUG_PCI=y
|
||||
# CONFIG_HOTPLUG_PCI_CPCI is not set
|
||||
# CONFIG_HOTPLUG_PCI_PCIE is not set
|
||||
# CONFIG_HOTPLUG_PCI_SHPC is not set
|
||||
CONFIG_HUGETLBFS=y
|
||||
CONFIG_HUGETLB_PAGE=y
|
||||
CONFIG_HWMON=y
|
||||
CONFIG_HWSPINLOCK=y
|
||||
CONFIG_HW_CONSOLE=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_HW_RANDOM_ROCKCHIP=y
|
||||
CONFIG_HZ=250
|
||||
# CONFIG_HZ_100 is not set
|
||||
CONFIG_HZ_250=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_BOARDINFO=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_COMPAT=y
|
||||
CONFIG_I2C_HELPER_AUTO=y
|
||||
CONFIG_I2C_RK3X=y
|
||||
# CONFIG_IIO_SCMI is not set
|
||||
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
|
||||
CONFIG_INDIRECT_PIO=y
|
||||
CONFIG_INPUT=y
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_INPUT_FF_MEMLESS=y
|
||||
CONFIG_INPUT_KEYBOARD=y
|
||||
CONFIG_INPUT_LEDS=y
|
||||
CONFIG_INPUT_MATRIXKMAP=y
|
||||
# CONFIG_INPUT_MISC is not set
|
||||
# CONFIG_INPUT_RK805_PWRKEY is not set
|
||||
CONFIG_IOMMU_API=y
|
||||
# CONFIG_IOMMU_DEBUGFS is not set
|
||||
# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
|
||||
CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
|
||||
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
|
||||
CONFIG_IOMMU_DMA=y
|
||||
CONFIG_IOMMU_IOVA=y
|
||||
CONFIG_IOMMU_IO_PGTABLE=y
|
||||
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
|
||||
CONFIG_IOMMU_IO_PGTABLE_LPAE=y
|
||||
# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
|
||||
CONFIG_IOMMU_SUPPORT=y
|
||||
# CONFIG_IO_STRICT_DEVMEM is not set
|
||||
CONFIG_IO_URING=y
|
||||
CONFIG_IRQCHIP=y
|
||||
CONFIG_IRQ_DOMAIN=y
|
||||
CONFIG_IRQ_DOMAIN_HIERARCHY=y
|
||||
CONFIG_IRQ_FORCED_THREADING=y
|
||||
CONFIG_IRQ_MSI_IOMMU=y
|
||||
CONFIG_IRQ_TIME_ACCOUNTING=y
|
||||
CONFIG_IRQ_WORK=y
|
||||
CONFIG_JBD2=y
|
||||
CONFIG_JFFS2_ZLIB=y
|
||||
CONFIG_JUMP_LABEL=y
|
||||
CONFIG_KALLSYMS=y
|
||||
CONFIG_KCMP=y
|
||||
CONFIG_KEXEC_CORE=y
|
||||
CONFIG_KEXEC_FILE=y
|
||||
CONFIG_KSM=y
|
||||
# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
|
||||
CONFIG_LEDS_GPIO=y
|
||||
CONFIG_LEDS_PWM=y
|
||||
CONFIG_LEDS_SYSCON=y
|
||||
CONFIG_LEDS_TRIGGER_CPU=y
|
||||
CONFIG_LEDS_TRIGGER_PANIC=y
|
||||
CONFIG_LEGACY_PTYS=y
|
||||
CONFIG_LEGACY_PTY_COUNT=16
|
||||
CONFIG_LIBCRC32C=y
|
||||
CONFIG_LIBFDT=y
|
||||
CONFIG_LIB_MEMNEQ=y
|
||||
CONFIG_LOCALVERSION_AUTO=y
|
||||
CONFIG_LOCK_DEBUGGING_SUPPORT=y
|
||||
CONFIG_LOCK_SPIN_ON_OWNER=y
|
||||
CONFIG_LOG_BUF_SHIFT=19
|
||||
CONFIG_LTO_NONE=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_MAGIC_SYSRQ_SERIAL=y
|
||||
CONFIG_MAILBOX=y
|
||||
# CONFIG_MAILBOX_TEST is not set
|
||||
CONFIG_MDIO_BUS=y
|
||||
CONFIG_MDIO_BUS_MUX=y
|
||||
CONFIG_MDIO_BUS_MUX_GPIO=y
|
||||
CONFIG_MDIO_BUS_MUX_MMIOREG=y
|
||||
CONFIG_MDIO_DEVICE=y
|
||||
CONFIG_MDIO_DEVRES=y
|
||||
CONFIG_MEMFD_CREATE=y
|
||||
CONFIG_MEMORY_ISOLATION=y
|
||||
CONFIG_MFD_CORE=y
|
||||
# CONFIG_MFD_KHADAS_MCU is not set
|
||||
CONFIG_MFD_RK808=y
|
||||
CONFIG_MFD_SYSCON=y
|
||||
CONFIG_MIGRATION=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_BLOCK=y
|
||||
CONFIG_MMC_BLOCK_MINORS=32
|
||||
CONFIG_MMC_CQHCI=y
|
||||
CONFIG_MMC_DW=y
|
||||
# CONFIG_MMC_DW_BLUEFIELD is not set
|
||||
# CONFIG_MMC_DW_EXYNOS is not set
|
||||
# CONFIG_MMC_DW_HI3798CV200 is not set
|
||||
# CONFIG_MMC_DW_K3 is not set
|
||||
# CONFIG_MMC_DW_PCI is not set
|
||||
CONFIG_MMC_DW_PLTFM=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_OF_ARASAN=y
|
||||
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
|
||||
# CONFIG_MMC_SDHCI_PCI is not set
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
CONFIG_MODULES_USE_ELF_RELA=y
|
||||
CONFIG_MOTORCOMM_PHY=y
|
||||
CONFIG_MQ_IOSCHED_DEADLINE=y
|
||||
# CONFIG_MTD_CFI is not set
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
|
||||
CONFIG_MTD_SPLIT_FIRMWARE=y
|
||||
CONFIG_MUTEX_SPIN_ON_OWNER=y
|
||||
CONFIG_NEED_DMA_MAP_STATE=y
|
||||
CONFIG_NEED_SG_DMA_LENGTH=y
|
||||
CONFIG_NET_FLOW_LIMIT=y
|
||||
CONFIG_NET_SELFTESTS=y
|
||||
CONFIG_NET_SOCK_MSG=y
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NOP_USB_XCEIV=y
|
||||
CONFIG_NO_HZ_COMMON=y
|
||||
CONFIG_NO_HZ_IDLE=y
|
||||
CONFIG_NR_CPUS=256
|
||||
CONFIG_NVMEM=y
|
||||
CONFIG_NVMEM_SYSFS=y
|
||||
CONFIG_NVME_CORE=y
|
||||
# CONFIG_NVME_HWMON is not set
|
||||
# CONFIG_NVME_MULTIPATH is not set
|
||||
CONFIG_OF=y
|
||||
CONFIG_OF_ADDRESS=y
|
||||
CONFIG_OF_DYNAMIC=y
|
||||
CONFIG_OF_EARLY_FLATTREE=y
|
||||
CONFIG_OF_FLATTREE=y
|
||||
CONFIG_OF_GPIO=y
|
||||
CONFIG_OF_IOMMU=y
|
||||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_KOBJ=y
|
||||
CONFIG_OF_MDIO=y
|
||||
CONFIG_OF_OVERLAY=y
|
||||
CONFIG_OF_RESOLVE=y
|
||||
CONFIG_OLD_SIGSUSPEND3=y
|
||||
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
|
||||
CONFIG_PADATA=y
|
||||
CONFIG_PAGE_POOL=y
|
||||
# CONFIG_PANIC_ON_OOPS is not set
|
||||
CONFIG_PANIC_ON_OOPS_VALUE=0
|
||||
CONFIG_PANIC_TIMEOUT=0
|
||||
# CONFIG_PARTITION_ADVANCED is not set
|
||||
CONFIG_PARTITION_PERCPU=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCIEAER=y
|
||||
CONFIG_PCIEASPM=y
|
||||
CONFIG_PCIEASPM_DEFAULT=y
|
||||
# CONFIG_PCIEASPM_PERFORMANCE is not set
|
||||
# CONFIG_PCIEASPM_POWERSAVE is not set
|
||||
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
CONFIG_PCIE_DW=y
|
||||
CONFIG_PCIE_DW_HOST=y
|
||||
CONFIG_PCIE_PME=y
|
||||
CONFIG_PCIE_ROCKCHIP=y
|
||||
CONFIG_PCIE_ROCKCHIP_DW_HOST=y
|
||||
CONFIG_PCIE_ROCKCHIP_HOST=y
|
||||
CONFIG_PCI_DOMAINS=y
|
||||
CONFIG_PCI_DOMAINS_GENERIC=y
|
||||
CONFIG_PCI_MSI=y
|
||||
CONFIG_PCI_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_PCI_STUB=y
|
||||
CONFIG_PCS_XPCS=y
|
||||
CONFIG_PGTABLE_LEVELS=4
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHYLINK=y
|
||||
CONFIG_PHYS_ADDR_T_64BIT=y
|
||||
CONFIG_PHY_ROCKCHIP_DP=y
|
||||
# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
|
||||
CONFIG_PHY_ROCKCHIP_EMMC=y
|
||||
# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set
|
||||
# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
|
||||
# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
|
||||
CONFIG_PHY_ROCKCHIP_PCIE=y
|
||||
CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
|
||||
CONFIG_PHY_ROCKCHIP_TYPEC=y
|
||||
CONFIG_PHY_ROCKCHIP_USB=y
|
||||
CONFIG_PINCTRL=y
|
||||
# CONFIG_PINCTRL_RK805 is not set
|
||||
CONFIG_PINCTRL_ROCKCHIP=y
|
||||
# CONFIG_PINCTRL_SINGLE is not set
|
||||
CONFIG_PL330_DMA=y
|
||||
CONFIG_PLATFORM_MHU=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_PM_CLK=y
|
||||
CONFIG_PM_DEVFREQ=y
|
||||
CONFIG_PM_DEVFREQ_EVENT=y
|
||||
CONFIG_PM_GENERIC_DOMAINS=y
|
||||
CONFIG_PM_GENERIC_DOMAINS_OF=y
|
||||
CONFIG_PM_OPP=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_POWER_SUPPLY_HWMON=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_PREEMPTION=y
|
||||
CONFIG_PREEMPT_COUNT=y
|
||||
# CONFIG_PREEMPT_NONE is not set
|
||||
CONFIG_PREEMPT_RCU=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
# CONFIG_PRINT_QUOTA_WARNING is not set
|
||||
CONFIG_PROC_PAGE_MONITOR=y
|
||||
CONFIG_PROC_VMCORE=y
|
||||
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
|
||||
CONFIG_PWM=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_PWM_SYSFS=y
|
||||
# CONFIG_QFMT_V1 is not set
|
||||
# CONFIG_QFMT_V2 is not set
|
||||
CONFIG_QUEUED_RWLOCKS=y
|
||||
CONFIG_QUEUED_SPINLOCKS=y
|
||||
CONFIG_QUOTA=y
|
||||
CONFIG_QUOTACTL=y
|
||||
# CONFIG_QUOTA_NETLINK_INTERFACE is not set
|
||||
CONFIG_RAID_ATTRS=y
|
||||
CONFIG_RANDOMIZE_BASE=y
|
||||
CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
|
||||
CONFIG_RAS=y
|
||||
CONFIG_RATIONAL=y
|
||||
# CONFIG_RAVE_SP_CORE is not set
|
||||
CONFIG_RCU_TRACE=y
|
||||
CONFIG_REALTEK_PHY=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_REGMAP_I2C=y
|
||||
CONFIG_REGMAP_IRQ=y
|
||||
CONFIG_REGMAP_MMIO=y
|
||||
CONFIG_REGULATOR=y
|
||||
# CONFIG_REGULATOR_ARM_SCMI is not set
|
||||
CONFIG_REGULATOR_FAN53555=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_REGULATOR_GPIO=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_REGULATOR_RK808=y
|
||||
CONFIG_RELOCATABLE=y
|
||||
CONFIG_RESET_CONTROLLER=y
|
||||
CONFIG_RESET_SCMI=y
|
||||
CONFIG_RFS_ACCEL=y
|
||||
CONFIG_ROCKCHIP_EFUSE=y
|
||||
CONFIG_ROCKCHIP_ERRATUM_114514=y
|
||||
CONFIG_ROCKCHIP_GRF=y
|
||||
CONFIG_ROCKCHIP_IODOMAIN=y
|
||||
CONFIG_ROCKCHIP_IOMMU=y
|
||||
CONFIG_ROCKCHIP_MBOX=y
|
||||
# CONFIG_ROCKCHIP_OTP is not set
|
||||
CONFIG_ROCKCHIP_PHY=y
|
||||
CONFIG_ROCKCHIP_PM_DOMAINS=y
|
||||
CONFIG_ROCKCHIP_THERMAL=y
|
||||
CONFIG_ROCKCHIP_TIMER=y
|
||||
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
|
||||
CONFIG_RPS=y
|
||||
CONFIG_RSEQ=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_RK808=y
|
||||
CONFIG_RTC_I2C_AND_SPI=y
|
||||
CONFIG_RTC_NVMEM=y
|
||||
# CONFIG_RUNTIME_TESTING_MENU is not set
|
||||
CONFIG_RWSEM_SPIN_ON_OWNER=y
|
||||
CONFIG_SCHED_MC=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SCSI_COMMON=y
|
||||
# CONFIG_SCSI_LOWLEVEL is not set
|
||||
# CONFIG_SCSI_PROC_FS is not set
|
||||
CONFIG_SCSI_SAS_ATTRS=y
|
||||
CONFIG_SCSI_SAS_HOST_SMP=y
|
||||
CONFIG_SCSI_SAS_LIBSAS=y
|
||||
# CONFIG_SECURITY_DMESG_RESTRICT is not set
|
||||
# CONFIG_SENSORS_ARM_SCMI is not set
|
||||
CONFIG_SENSORS_ARM_SCPI=y
|
||||
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
CONFIG_SERIAL_8250_DWLIB=y
|
||||
CONFIG_SERIAL_8250_EXAR=y
|
||||
CONFIG_SERIAL_8250_EXTENDED=y
|
||||
CONFIG_SERIAL_8250_FSL=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=4
|
||||
CONFIG_SERIAL_8250_PCI=y
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
|
||||
CONFIG_SERIAL_8250_SHARE_IRQ=y
|
||||
CONFIG_SERIAL_AMBA_PL011=y
|
||||
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
|
||||
CONFIG_SERIAL_DEV_BUS=y
|
||||
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
|
||||
CONFIG_SERIAL_MCTRL_GPIO=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
CONFIG_SERIO=y
|
||||
CONFIG_SERIO_AMBAKMI=y
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
CONFIG_SG_POOL=y
|
||||
CONFIG_SLUB_DEBUG=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SOCK_RX_QUEUE_MAPPING=y
|
||||
CONFIG_SPARSEMEM=y
|
||||
CONFIG_SPARSEMEM_EXTREME=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_BITBANG=y
|
||||
CONFIG_SPI_DYNAMIC=y
|
||||
CONFIG_SPI_MASTER=y
|
||||
CONFIG_SPI_MEM=y
|
||||
CONFIG_SPI_ROCKCHIP=y
|
||||
CONFIG_SPI_ROCKCHIP_SFC=y
|
||||
CONFIG_SPI_SPIDEV=y
|
||||
# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
|
||||
CONFIG_SQUASHFS_DECOMP_SINGLE=y
|
||||
# CONFIG_SQUASHFS_EMBEDDED is not set
|
||||
CONFIG_SQUASHFS_FILE_CACHE=y
|
||||
# CONFIG_SQUASHFS_FILE_DIRECT is not set
|
||||
CONFIG_SRAM=y
|
||||
CONFIG_SRCU=y
|
||||
CONFIG_STACKPROTECTOR=y
|
||||
CONFIG_STACKPROTECTOR_PER_TASK=y
|
||||
CONFIG_STACKPROTECTOR_STRONG=y
|
||||
CONFIG_STACKTRACE=y
|
||||
# CONFIG_STAGING is not set
|
||||
CONFIG_STMMAC_ETH=y
|
||||
CONFIG_STMMAC_PLATFORM=y
|
||||
# CONFIG_STMMAC_SELFTESTS is not set
|
||||
CONFIG_STRICT_DEVMEM=y
|
||||
# CONFIG_STRIP_ASM_SYMS is not set
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_SWIOTLB=y
|
||||
CONFIG_SWPHY=y
|
||||
CONFIG_SYNC_FILE=y
|
||||
CONFIG_SYSCTL_EXCEPTION_TRACE=y
|
||||
CONFIG_SYSFS_SYSCALL=y
|
||||
CONFIG_SYSVIPC_COMPAT=y
|
||||
# CONFIG_TEXTSEARCH is not set
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
|
||||
CONFIG_THERMAL_EMULATION=y
|
||||
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
|
||||
CONFIG_THERMAL_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_HWMON=y
|
||||
CONFIG_THERMAL_OF=y
|
||||
CONFIG_THREAD_INFO_IN_TASK=y
|
||||
CONFIG_TICK_CPU_ACCOUNTING=y
|
||||
CONFIG_TIMER_OF=y
|
||||
CONFIG_TIMER_PROBE=y
|
||||
CONFIG_TRACE_CLOCK=y
|
||||
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
|
||||
CONFIG_TRANSPARENT_HUGEPAGE=y
|
||||
CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
|
||||
# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
|
||||
CONFIG_TREE_RCU=y
|
||||
CONFIG_TREE_SRCU=y
|
||||
CONFIG_TYPEC=y
|
||||
# CONFIG_TYPEC_DP_ALTMODE is not set
|
||||
CONFIG_TYPEC_FUSB302=y
|
||||
# CONFIG_TYPEC_HD3SS3220 is not set
|
||||
# CONFIG_TYPEC_MUX_PI3USB30532 is not set
|
||||
# CONFIG_TYPEC_STUSB160X is not set
|
||||
# CONFIG_TYPEC_TCPCI is not set
|
||||
CONFIG_TYPEC_TCPM=y
|
||||
# CONFIG_TYPEC_TPS6598X is not set
|
||||
# CONFIG_UACCE is not set
|
||||
# CONFIG_UCLAMP_TASK is not set
|
||||
# CONFIG_UEVENT_HELPER is not set
|
||||
CONFIG_UNINLINE_SPIN_UNLOCK=y
|
||||
CONFIG_UNMAP_KERNEL_AT_EL0=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_COMMON=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_HOST=y
|
||||
CONFIG_USB_DWC3_OF_SIMPLE=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD_PLATFORM=y
|
||||
# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
|
||||
CONFIG_USB_HID=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_PHY=y
|
||||
CONFIG_USB_ROLE_SWITCH=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_ULPI_BUS=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_PLATFORM=y
|
||||
# CONFIG_VIRTIO_MENU is not set
|
||||
CONFIG_VMAP_STACK=y
|
||||
CONFIG_VM_EVENT_COUNTERS=y
|
||||
CONFIG_VT=y
|
||||
CONFIG_VT_CONSOLE=y
|
||||
CONFIG_VT_HW_CONSOLE_BINDING=y
|
||||
CONFIG_WATCHDOG_CORE=y
|
||||
CONFIG_XARRAY_MULTI=y
|
||||
CONFIG_XPS=y
|
||||
CONFIG_XXHASH=y
|
||||
CONFIG_XZ_DEC_ARM=y
|
||||
CONFIG_XZ_DEC_ARMTHUMB=y
|
||||
CONFIG_XZ_DEC_BCJ=y
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
CONFIG_ZONE_DMA32=y
|
||||
|
|
@ -1,654 +0,0 @@
|
|||
CONFIG_64BIT=y
|
||||
CONFIG_ARCH_CLOCKSOURCE_DATA=y
|
||||
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
|
||||
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
|
||||
CONFIG_ARCH_KEEP_MEMBLOCK=y
|
||||
CONFIG_ARCH_MMAP_RND_BITS=18
|
||||
CONFIG_ARCH_MMAP_RND_BITS_MAX=33
|
||||
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
|
||||
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
|
||||
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
|
||||
CONFIG_ARCH_PROC_KCORE_TEXT=y
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
|
||||
CONFIG_ARCH_SPARSEMEM_DEFAULT=y
|
||||
CONFIG_ARCH_SPARSEMEM_ENABLE=y
|
||||
CONFIG_ARCH_SUSPEND_POSSIBLE=y
|
||||
CONFIG_ARC_EMAC_CORE=y
|
||||
CONFIG_ARM64=y
|
||||
CONFIG_ARM64_4K_PAGES=y
|
||||
CONFIG_ARM64_CNP=y
|
||||
CONFIG_ARM64_CONT_SHIFT=4
|
||||
# CONFIG_ARM64_ERRATUM_1165522 is not set
|
||||
# CONFIG_ARM64_ERRATUM_1286807 is not set
|
||||
# CONFIG_ARM64_ERRATUM_1418040 is not set
|
||||
CONFIG_ARM64_ERRATUM_819472=y
|
||||
CONFIG_ARM64_ERRATUM_824069=y
|
||||
CONFIG_ARM64_ERRATUM_826319=y
|
||||
CONFIG_ARM64_ERRATUM_827319=y
|
||||
CONFIG_ARM64_ERRATUM_832075=y
|
||||
CONFIG_ARM64_ERRATUM_843419=y
|
||||
CONFIG_ARM64_ERRATUM_845719=y
|
||||
CONFIG_ARM64_ERRATUM_858921=y
|
||||
CONFIG_ARM64_HW_AFDBM=y
|
||||
CONFIG_ARM64_LSE_ATOMICS=y
|
||||
CONFIG_ARM64_MODULE_PLTS=y
|
||||
CONFIG_ARM64_PAGE_SHIFT=12
|
||||
CONFIG_ARM64_PAN=y
|
||||
CONFIG_ARM64_PA_BITS=48
|
||||
CONFIG_ARM64_PA_BITS_48=y
|
||||
CONFIG_ARM64_PTR_AUTH=y
|
||||
CONFIG_ARM64_RAS_EXTN=y
|
||||
CONFIG_ARM64_SSBD=y
|
||||
CONFIG_ARM64_SVE=y
|
||||
# CONFIG_ARM64_SW_TTBR0_PAN is not set
|
||||
CONFIG_ARM64_TAGGED_ADDR_ABI=y
|
||||
CONFIG_ARM64_UAO=y
|
||||
CONFIG_ARM64_VA_BITS=48
|
||||
# CONFIG_ARM64_VA_BITS_39 is not set
|
||||
CONFIG_ARM64_VA_BITS_48=y
|
||||
CONFIG_ARM64_VHE=y
|
||||
CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
|
||||
# CONFIG_ARMV8_DEPRECATED is not set
|
||||
CONFIG_ARM_AMBA=y
|
||||
CONFIG_ARM_ARCH_TIMER=y
|
||||
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
|
||||
CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
|
||||
CONFIG_ARM_CPUIDLE=y
|
||||
CONFIG_ARM_GIC=y
|
||||
CONFIG_ARM_GIC_V2M=y
|
||||
CONFIG_ARM_GIC_V3=y
|
||||
CONFIG_ARM_GIC_V3_ITS=y
|
||||
CONFIG_ARM_GIC_V3_ITS_PCI=y
|
||||
CONFIG_ARM_MHU=y
|
||||
CONFIG_ARM_PSCI_CPUIDLE=y
|
||||
CONFIG_ARM_PSCI_FW=y
|
||||
CONFIG_ARM_RK3328_DMC_DEVFREQ=y
|
||||
# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
|
||||
# CONFIG_ARM_SCMI_PROTOCOL is not set
|
||||
CONFIG_ARM_SCPI_CPUFREQ=y
|
||||
CONFIG_ARM_SCPI_POWER_DOMAIN=y
|
||||
CONFIG_ARM_SCPI_PROTOCOL=y
|
||||
CONFIG_ARM_SMMU=y
|
||||
CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
|
||||
CONFIG_ARM_SMMU_V3=y
|
||||
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
CONFIG_BACKLIGHT_GPIO=y
|
||||
CONFIG_BACKLIGHT_PWM=y
|
||||
CONFIG_BLK_DEV_BSG=y
|
||||
CONFIG_BLK_DEV_BSGLIB=y
|
||||
# CONFIG_BLK_DEV_INITRD is not set
|
||||
CONFIG_BLK_DEV_INTEGRITY=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_NVME=y
|
||||
CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_BLK_MQ_PCI=y
|
||||
CONFIG_BLK_PM=y
|
||||
CONFIG_BLK_SCSI_REQUEST=y
|
||||
CONFIG_BLOCK_COMPAT=y
|
||||
CONFIG_BRCMSTB_GISB_ARB=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_BSD_PROCESS_ACCT_V3=y
|
||||
# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set
|
||||
CONFIG_CHARGER_GPIO=y
|
||||
CONFIG_CLKDEV_LOOKUP=y
|
||||
CONFIG_CLKSRC_MMIO=y
|
||||
CONFIG_CLONE_BACKWARDS=y
|
||||
CONFIG_CMA=y
|
||||
CONFIG_CMA_ALIGNMENT=8
|
||||
CONFIG_CMA_AREAS=7
|
||||
# CONFIG_CMA_DEBUG is not set
|
||||
# CONFIG_CMA_DEBUGFS is not set
|
||||
CONFIG_CMA_SIZE_MBYTES=64
|
||||
# CONFIG_CMA_SIZE_SEL_MAX is not set
|
||||
CONFIG_CMA_SIZE_SEL_MBYTES=y
|
||||
# CONFIG_CMA_SIZE_SEL_MIN is not set
|
||||
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
|
||||
CONFIG_COMMON_CLK=y
|
||||
CONFIG_COMMON_CLK_RK808=y
|
||||
CONFIG_COMMON_CLK_SCPI=y
|
||||
CONFIG_COMPAT=y
|
||||
CONFIG_COMPAT_32BIT_TIME=y
|
||||
CONFIG_COMPAT_BINFMT_ELF=y
|
||||
CONFIG_COMPAT_NETLINK_MESSAGES=y
|
||||
CONFIG_COMPAT_OLD_SIGACTION=y
|
||||
CONFIG_CONFIGFS_FS=y
|
||||
CONFIG_CONSOLE_TRANSLATIONS=y
|
||||
CONFIG_CONTIG_ALLOC=y
|
||||
CONFIG_CPUFREQ_DT=y
|
||||
CONFIG_CPUFREQ_DT_PLATDEV=y
|
||||
CONFIG_CPU_FREQ=y
|
||||
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
|
||||
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
|
||||
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
|
||||
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
|
||||
# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
|
||||
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
|
||||
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
|
||||
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
|
||||
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
|
||||
CONFIG_CPU_FREQ_STAT=y
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_CPU_IDLE_GOV_MENU=y
|
||||
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
|
||||
CONFIG_CPU_ISOLATION=y
|
||||
CONFIG_CPU_PM=y
|
||||
CONFIG_CPU_RMAP=y
|
||||
CONFIG_CPU_THERMAL=y
|
||||
CONFIG_CRASH_CORE=y
|
||||
CONFIG_CRASH_DUMP=y
|
||||
CONFIG_CRC16=y
|
||||
# CONFIG_CRC32_SARWATE is not set
|
||||
CONFIG_CRC32_SLICEBY8=y
|
||||
CONFIG_CRC_T10DIF=y
|
||||
CONFIG_CROSS_MEMORY_ATTACH=y
|
||||
CONFIG_CRYPTO_AEAD=y
|
||||
CONFIG_CRYPTO_AEAD2=y
|
||||
CONFIG_CRYPTO_CRC32=y
|
||||
CONFIG_CRYPTO_CRC32C=y
|
||||
CONFIG_CRYPTO_CRCT10DIF=y
|
||||
# CONFIG_CRYPTO_DEV_ROCKCHIP is not set
|
||||
CONFIG_CRYPTO_DRBG=y
|
||||
CONFIG_CRYPTO_DRBG_HMAC=y
|
||||
CONFIG_CRYPTO_DRBG_MENU=y
|
||||
CONFIG_CRYPTO_HASH=y
|
||||
CONFIG_CRYPTO_HASH2=y
|
||||
CONFIG_CRYPTO_JITTERENTROPY=y
|
||||
CONFIG_CRYPTO_MANAGER=y
|
||||
CONFIG_CRYPTO_MANAGER2=y
|
||||
CONFIG_CRYPTO_NULL2=y
|
||||
CONFIG_CRYPTO_RNG=y
|
||||
CONFIG_CRYPTO_RNG2=y
|
||||
CONFIG_CRYPTO_RNG_DEFAULT=y
|
||||
CONFIG_DCACHE_WORD_ACCESS=y
|
||||
CONFIG_DEBUG_BUGVERBOSE=y
|
||||
# CONFIG_DEVFREQ_GOV_PASSIVE is not set
|
||||
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
|
||||
CONFIG_DEVFREQ_GOV_POWERSAVE=y
|
||||
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
|
||||
CONFIG_DEVFREQ_GOV_USERSPACE=y
|
||||
# CONFIG_DEVFREQ_THERMAL is not set
|
||||
CONFIG_DEVMEM=y
|
||||
# CONFIG_DEVPORT is not set
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_DMA_CMA=y
|
||||
CONFIG_DMA_DIRECT_REMAP=y
|
||||
CONFIG_DMA_ENGINE=y
|
||||
CONFIG_DMA_OF=y
|
||||
CONFIG_DMA_REMAP=y
|
||||
CONFIG_DMA_SHARED_BUFFER=y
|
||||
CONFIG_DNOTIFY=y
|
||||
CONFIG_DRM_RCAR_WRITEBACK=y
|
||||
# CONFIG_DRM_ROCKCHIP is not set
|
||||
CONFIG_DTC=y
|
||||
CONFIG_DT_IDLE_STATES=y
|
||||
CONFIG_DUMMY_CONSOLE=y
|
||||
CONFIG_DWMAC_DWC_QOS_ETH=y
|
||||
CONFIG_DWMAC_GENERIC=y
|
||||
CONFIG_DWMAC_ROCKCHIP=y
|
||||
CONFIG_EDAC_SUPPORT=y
|
||||
CONFIG_EEPROM_AT24=y
|
||||
CONFIG_EMAC_ROCKCHIP=y
|
||||
CONFIG_ENABLE_MUST_CHECK=y
|
||||
CONFIG_ENERGY_MODEL=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_EXT4_FS_POSIX_ACL=y
|
||||
CONFIG_EXTCON=y
|
||||
CONFIG_F2FS_FS=y
|
||||
CONFIG_FANOTIFY=y
|
||||
CONFIG_FHANDLE=y
|
||||
CONFIG_FIXED_PHY=y
|
||||
CONFIG_FIX_EARLYCON_MEM=y
|
||||
# CONFIG_FLATMEM_MANUAL is not set
|
||||
# CONFIG_FORTIFY_SOURCE is not set
|
||||
CONFIG_FRAME_POINTER=y
|
||||
CONFIG_FRAME_WARN=2048
|
||||
CONFIG_FS_IOMAP=y
|
||||
CONFIG_FS_MBCACHE=y
|
||||
CONFIG_FS_POSIX_ACL=y
|
||||
# CONFIG_FUJITSU_ERRATUM_010001 is not set
|
||||
CONFIG_FW_LOADER_PAGED_BUF=y
|
||||
CONFIG_GENERIC_ALLOCATOR=y
|
||||
CONFIG_GENERIC_ARCH_TOPOLOGY=y
|
||||
CONFIG_GENERIC_BUG=y
|
||||
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
|
||||
CONFIG_GENERIC_CPU_AUTOPROBE=y
|
||||
CONFIG_GENERIC_CPU_VULNERABILITIES=y
|
||||
CONFIG_GENERIC_CSUM=y
|
||||
CONFIG_GENERIC_EARLY_IOREMAP=y
|
||||
CONFIG_GENERIC_GETTIMEOFDAY=y
|
||||
CONFIG_GENERIC_IDLE_POLL_SETUP=y
|
||||
CONFIG_GENERIC_IRQ_CHIP=y
|
||||
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
|
||||
CONFIG_GENERIC_IRQ_MIGRATION=y
|
||||
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
|
||||
CONFIG_GENERIC_IRQ_SHOW=y
|
||||
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
|
||||
CONFIG_GENERIC_MSI_IRQ=y
|
||||
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_GENERIC_PCI_IOMAP=y
|
||||
CONFIG_GENERIC_PHY=y
|
||||
CONFIG_GENERIC_PINCONF=y
|
||||
CONFIG_GENERIC_SCHED_CLOCK=y
|
||||
CONFIG_GENERIC_SMP_IDLE_THREAD=y
|
||||
CONFIG_GENERIC_STRNCPY_FROM_USER=y
|
||||
CONFIG_GENERIC_STRNLEN_USER=y
|
||||
CONFIG_GENERIC_TIME_VSYSCALL=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIO_DWAPB=y
|
||||
CONFIG_GPIO_GENERIC=y
|
||||
CONFIG_GPIO_GENERIC_PLATFORM=y
|
||||
CONFIG_HANDLE_DOMAIN_IRQ=y
|
||||
# CONFIG_HARDENED_USERCOPY is not set
|
||||
CONFIG_HARDEN_BRANCH_PREDICTOR=y
|
||||
CONFIG_HARDIRQS_SW_RESEND=y
|
||||
CONFIG_HAS_DMA=y
|
||||
CONFIG_HAS_IOMEM=y
|
||||
CONFIG_HAS_IOPORT_MAP=y
|
||||
CONFIG_HID=y
|
||||
CONFIG_HID_GENERIC=y
|
||||
CONFIG_HOLES_IN_ZONE=y
|
||||
CONFIG_HOTPLUG_CPU=y
|
||||
CONFIG_HOTPLUG_PCI=y
|
||||
# CONFIG_HOTPLUG_PCI_CPCI is not set
|
||||
# CONFIG_HOTPLUG_PCI_PCIE is not set
|
||||
# CONFIG_HOTPLUG_PCI_SHPC is not set
|
||||
CONFIG_HUGETLBFS=y
|
||||
CONFIG_HUGETLB_PAGE=y
|
||||
CONFIG_HWMON=y
|
||||
CONFIG_HWSPINLOCK=y
|
||||
CONFIG_HW_CONSOLE=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_HW_RANDOM_ROCKCHIP=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_BOARDINFO=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_COMPAT=y
|
||||
CONFIG_I2C_HELPER_AUTO=y
|
||||
CONFIG_I2C_RK3X=y
|
||||
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
|
||||
CONFIG_INDIRECT_PIO=y
|
||||
CONFIG_INPUT=y
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_INPUT_FF_MEMLESS=y
|
||||
CONFIG_INPUT_KEYBOARD=y
|
||||
CONFIG_INPUT_LEDS=y
|
||||
CONFIG_INPUT_MATRIXKMAP=y
|
||||
# CONFIG_INPUT_MISC is not set
|
||||
# CONFIG_INPUT_RK805_PWRKEY is not set
|
||||
CONFIG_IOMMU_API=y
|
||||
# CONFIG_IOMMU_DEBUGFS is not set
|
||||
# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
|
||||
CONFIG_IOMMU_DMA=y
|
||||
CONFIG_IOMMU_IOVA=y
|
||||
CONFIG_IOMMU_IO_PGTABLE=y
|
||||
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
|
||||
CONFIG_IOMMU_IO_PGTABLE_LPAE=y
|
||||
# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
|
||||
CONFIG_IOMMU_SUPPORT=y
|
||||
# CONFIG_IO_STRICT_DEVMEM is not set
|
||||
CONFIG_IO_URING=y
|
||||
CONFIG_IRQCHIP=y
|
||||
CONFIG_IRQ_DOMAIN=y
|
||||
CONFIG_IRQ_DOMAIN_HIERARCHY=y
|
||||
CONFIG_IRQ_FORCED_THREADING=y
|
||||
CONFIG_IRQ_MSI_IOMMU=y
|
||||
CONFIG_IRQ_TIME_ACCOUNTING=y
|
||||
CONFIG_IRQ_WORK=y
|
||||
CONFIG_JBD2=y
|
||||
CONFIG_JFFS2_ZLIB=y
|
||||
CONFIG_JUMP_LABEL=y
|
||||
CONFIG_KALLSYMS=y
|
||||
CONFIG_KEXEC_CORE=y
|
||||
CONFIG_KEXEC_FILE=y
|
||||
# CONFIG_KEXEC_SIG is not set
|
||||
CONFIG_KSM=y
|
||||
# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
|
||||
CONFIG_LEDS_GPIO=y
|
||||
CONFIG_LEDS_PWM=y
|
||||
CONFIG_LEDS_SYSCON=y
|
||||
CONFIG_LEDS_TRIGGER_CPU=y
|
||||
CONFIG_LEDS_TRIGGER_PANIC=y
|
||||
CONFIG_LEGACY_PTYS=y
|
||||
CONFIG_LEGACY_PTY_COUNT=16
|
||||
CONFIG_LIBCRC32C=y
|
||||
CONFIG_LIBFDT=y
|
||||
CONFIG_LOCALVERSION_AUTO=y
|
||||
CONFIG_LOCK_DEBUGGING_SUPPORT=y
|
||||
CONFIG_LOCK_SPIN_ON_OWNER=y
|
||||
CONFIG_LOG_BUF_SHIFT=19
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_MAGIC_SYSRQ_SERIAL=y
|
||||
CONFIG_MAILBOX=y
|
||||
# CONFIG_MAILBOX_TEST is not set
|
||||
CONFIG_MANDATORY_FILE_LOCKING=y
|
||||
CONFIG_MDIO_BUS=y
|
||||
CONFIG_MDIO_BUS_MUX=y
|
||||
CONFIG_MDIO_BUS_MUX_GPIO=y
|
||||
CONFIG_MDIO_BUS_MUX_MMIOREG=y
|
||||
CONFIG_MDIO_DEVICE=y
|
||||
CONFIG_MEMFD_CREATE=y
|
||||
CONFIG_MEMORY_ISOLATION=y
|
||||
CONFIG_MFD_CORE=y
|
||||
CONFIG_MFD_RK808=y
|
||||
CONFIG_MFD_SYSCON=y
|
||||
CONFIG_MIGRATION=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_BLOCK=y
|
||||
CONFIG_MMC_BLOCK_MINORS=32
|
||||
CONFIG_MMC_CQHCI=y
|
||||
CONFIG_MMC_DW=y
|
||||
# CONFIG_MMC_DW_BLUEFIELD is not set
|
||||
# CONFIG_MMC_DW_EXYNOS is not set
|
||||
# CONFIG_MMC_DW_HI3798CV200 is not set
|
||||
# CONFIG_MMC_DW_K3 is not set
|
||||
# CONFIG_MMC_DW_PCI is not set
|
||||
CONFIG_MMC_DW_PLTFM=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_OF_ARASAN=y
|
||||
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
|
||||
# CONFIG_MMC_SDHCI_PCI is not set
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
CONFIG_MODULES_USE_ELF_RELA=y
|
||||
CONFIG_MOTORCOMM_PHY=y
|
||||
CONFIG_MQ_IOSCHED_DEADLINE=y
|
||||
# CONFIG_MTD_CFI is not set
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
|
||||
CONFIG_MTD_SPLIT_FIRMWARE=y
|
||||
CONFIG_MUTEX_SPIN_ON_OWNER=y
|
||||
CONFIG_NEED_DMA_MAP_STATE=y
|
||||
CONFIG_NEED_SG_DMA_LENGTH=y
|
||||
CONFIG_NET_FLOW_LIMIT=y
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NOP_USB_XCEIV=y
|
||||
CONFIG_NO_HZ_COMMON=y
|
||||
CONFIG_NO_HZ_IDLE=y
|
||||
CONFIG_NR_CPUS=256
|
||||
CONFIG_NVMEM=y
|
||||
CONFIG_NVMEM_SYSFS=y
|
||||
CONFIG_NVME_CORE=y
|
||||
# CONFIG_NVME_MULTIPATH is not set
|
||||
# CONFIG_NVME_TCP is not set
|
||||
CONFIG_OF=y
|
||||
CONFIG_OF_ADDRESS=y
|
||||
CONFIG_OF_DYNAMIC=y
|
||||
CONFIG_OF_EARLY_FLATTREE=y
|
||||
CONFIG_OF_FLATTREE=y
|
||||
CONFIG_OF_GPIO=y
|
||||
CONFIG_OF_IOMMU=y
|
||||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_KOBJ=y
|
||||
CONFIG_OF_MDIO=y
|
||||
CONFIG_OF_NET=y
|
||||
CONFIG_OF_OVERLAY=y
|
||||
CONFIG_OF_RESOLVE=y
|
||||
CONFIG_OLD_SIGSUSPEND3=y
|
||||
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
|
||||
CONFIG_PADATA=y
|
||||
CONFIG_PAGE_POOL=y
|
||||
# CONFIG_PANIC_ON_OOPS is not set
|
||||
CONFIG_PANIC_ON_OOPS_VALUE=0
|
||||
CONFIG_PANIC_TIMEOUT=0
|
||||
# CONFIG_PARTITION_ADVANCED is not set
|
||||
CONFIG_PARTITION_PERCPU=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCIEAER=y
|
||||
CONFIG_PCIEASPM=y
|
||||
# CONFIG_PCIEASPM_DEBUG is not set
|
||||
CONFIG_PCIEASPM_DEFAULT=y
|
||||
# CONFIG_PCIEASPM_PERFORMANCE is not set
|
||||
# CONFIG_PCIEASPM_POWERSAVE is not set
|
||||
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
CONFIG_PCIE_PME=y
|
||||
CONFIG_PCIE_ROCKCHIP=y
|
||||
CONFIG_PCIE_ROCKCHIP_HOST=y
|
||||
CONFIG_PCI_DOMAINS=y
|
||||
CONFIG_PCI_DOMAINS_GENERIC=y
|
||||
CONFIG_PCI_MSI=y
|
||||
CONFIG_PCI_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_PCI_STUB=y
|
||||
CONFIG_PGTABLE_LEVELS=4
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHYLINK=y
|
||||
CONFIG_PHYS_ADDR_T_64BIT=y
|
||||
CONFIG_PHY_ROCKCHIP_DP=y
|
||||
CONFIG_PHY_ROCKCHIP_EMMC=y
|
||||
# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB3=y
|
||||
CONFIG_PHY_ROCKCHIP_PCIE=y
|
||||
CONFIG_PHY_ROCKCHIP_TYPEC=y
|
||||
CONFIG_PHY_ROCKCHIP_USB=y
|
||||
CONFIG_PINCTRL=y
|
||||
# CONFIG_PINCTRL_RK805 is not set
|
||||
CONFIG_PINCTRL_ROCKCHIP=y
|
||||
# CONFIG_PINCTRL_SINGLE is not set
|
||||
CONFIG_PL330_DMA=y
|
||||
CONFIG_PLATFORM_MHU=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_PM_CLK=y
|
||||
CONFIG_PM_DEVFREQ=y
|
||||
# CONFIG_PM_DEVFREQ_EVENT is not set
|
||||
CONFIG_PM_GENERIC_DOMAINS=y
|
||||
CONFIG_PM_GENERIC_DOMAINS_OF=y
|
||||
CONFIG_PM_OPP=y
|
||||
CONFIG_POWER_AVS=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_POWER_SUPPLY_HWMON=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_PREEMPTION=y
|
||||
CONFIG_PREEMPT_COUNT=y
|
||||
# CONFIG_PREEMPT_NONE is not set
|
||||
CONFIG_PREEMPT_RCU=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
# CONFIG_PRINT_QUOTA_WARNING is not set
|
||||
CONFIG_PROC_PAGE_MONITOR=y
|
||||
CONFIG_PROC_VMCORE=y
|
||||
CONFIG_PWM=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_PWM_SYSFS=y
|
||||
# CONFIG_QFMT_V1 is not set
|
||||
# CONFIG_QFMT_V2 is not set
|
||||
CONFIG_QUEUED_RWLOCKS=y
|
||||
CONFIG_QUEUED_SPINLOCKS=y
|
||||
CONFIG_QUOTA=y
|
||||
CONFIG_QUOTACTL=y
|
||||
# CONFIG_QUOTA_NETLINK_INTERFACE is not set
|
||||
CONFIG_RAID_ATTRS=y
|
||||
CONFIG_RANDOMIZE_BASE=y
|
||||
CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
|
||||
CONFIG_RAS=y
|
||||
CONFIG_RATIONAL=y
|
||||
# CONFIG_RAVE_SP_CORE is not set
|
||||
CONFIG_RCU_CPU_STALL_TIMEOUT=21
|
||||
# CONFIG_RCU_EXPERT is not set
|
||||
CONFIG_RCU_NEED_SEGCBLIST=y
|
||||
CONFIG_RCU_STALL_COMMON=y
|
||||
CONFIG_RCU_TRACE=y
|
||||
CONFIG_REALTEK_PHY=y
|
||||
CONFIG_REFCOUNT_FULL=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_REGMAP_I2C=y
|
||||
CONFIG_REGMAP_IRQ=y
|
||||
CONFIG_REGMAP_MMIO=y
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_FAN53555=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_REGULATOR_GPIO=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_REGULATOR_RK808=y
|
||||
CONFIG_RELOCATABLE=y
|
||||
CONFIG_RESET_CONTROLLER=y
|
||||
CONFIG_RFS_ACCEL=y
|
||||
# CONFIG_ROCKCHIP_ANALOGIX_DP is not set
|
||||
# CONFIG_ROCKCHIP_CDN_DP is not set
|
||||
CONFIG_ROCKCHIP_EFUSE=y
|
||||
CONFIG_ROCKCHIP_GRF=y
|
||||
CONFIG_ROCKCHIP_IODOMAIN=y
|
||||
CONFIG_ROCKCHIP_IOMMU=y
|
||||
CONFIG_ROCKCHIP_MBOX=y
|
||||
CONFIG_ROCKCHIP_PHY=y
|
||||
CONFIG_ROCKCHIP_PM_DOMAINS=y
|
||||
# CONFIG_ROCKCHIP_RGB is not set
|
||||
# CONFIG_ROCKCHIP_RK3066_HDMI is not set
|
||||
# CONFIG_ROCKCHIP_SARADC is not set
|
||||
CONFIG_ROCKCHIP_THERMAL=y
|
||||
CONFIG_ROCKCHIP_TIMER=y
|
||||
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
|
||||
CONFIG_RPS=y
|
||||
CONFIG_RSEQ=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_RK808=y
|
||||
CONFIG_RTC_I2C_AND_SPI=y
|
||||
CONFIG_RTC_NVMEM=y
|
||||
# CONFIG_RUNTIME_TESTING_MENU is not set
|
||||
CONFIG_RWSEM_SPIN_ON_OWNER=y
|
||||
CONFIG_SCHED_MC=y
|
||||
CONFIG_SCSI=y
|
||||
# CONFIG_SCSI_LOWLEVEL is not set
|
||||
# CONFIG_SCSI_PROC_FS is not set
|
||||
CONFIG_SCSI_SAS_ATTRS=y
|
||||
CONFIG_SCSI_SAS_HOST_SMP=y
|
||||
CONFIG_SCSI_SAS_LIBSAS=y
|
||||
# CONFIG_SECURITY_DMESG_RESTRICT is not set
|
||||
CONFIG_SENSORS_ARM_SCPI=y
|
||||
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
CONFIG_SERIAL_8250_DWLIB=y
|
||||
CONFIG_SERIAL_8250_EXAR=y
|
||||
CONFIG_SERIAL_8250_EXTENDED=y
|
||||
CONFIG_SERIAL_8250_FSL=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=4
|
||||
CONFIG_SERIAL_8250_PCI=y
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
|
||||
CONFIG_SERIAL_8250_SHARE_IRQ=y
|
||||
CONFIG_SERIAL_AMBA_PL011=y
|
||||
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
|
||||
CONFIG_SERIAL_DEV_BUS=y
|
||||
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
|
||||
CONFIG_SERIAL_MCTRL_GPIO=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
CONFIG_SERIO=y
|
||||
CONFIG_SERIO_AMBAKMI=y
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
CONFIG_SG_POOL=y
|
||||
CONFIG_SIMPLE_PM_BUS=y
|
||||
CONFIG_SLUB_DEBUG=y
|
||||
CONFIG_SMP=y
|
||||
# CONFIG_SND_SOC_ROCKCHIP is not set
|
||||
CONFIG_SPARSEMEM=y
|
||||
CONFIG_SPARSEMEM_EXTREME=y
|
||||
CONFIG_SPARSEMEM_MANUAL=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_BITBANG=y
|
||||
CONFIG_SPI_DYNAMIC=y
|
||||
CONFIG_SPI_MASTER=y
|
||||
CONFIG_SPI_MEM=y
|
||||
CONFIG_SPI_ROCKCHIP=y
|
||||
CONFIG_SPI_SPIDEV=y
|
||||
# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
|
||||
CONFIG_SQUASHFS_DECOMP_SINGLE=y
|
||||
# CONFIG_SQUASHFS_EMBEDDED is not set
|
||||
CONFIG_SQUASHFS_FILE_CACHE=y
|
||||
# CONFIG_SQUASHFS_FILE_DIRECT is not set
|
||||
CONFIG_SRAM=y
|
||||
CONFIG_SRCU=y
|
||||
CONFIG_STACKPROTECTOR=y
|
||||
CONFIG_STACKPROTECTOR_STRONG=y
|
||||
# CONFIG_STAGING is not set
|
||||
CONFIG_STMMAC_ETH=y
|
||||
CONFIG_STMMAC_PLATFORM=y
|
||||
# CONFIG_STMMAC_SELFTESTS is not set
|
||||
CONFIG_STRICT_DEVMEM=y
|
||||
# CONFIG_STRIP_ASM_SYMS is not set
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_SWIOTLB=y
|
||||
CONFIG_SWPHY=y
|
||||
CONFIG_SYNC_FILE=y
|
||||
CONFIG_SYSCTL_EXCEPTION_TRACE=y
|
||||
CONFIG_SYSFS_SYSCALL=y
|
||||
CONFIG_SYSVIPC_COMPAT=y
|
||||
CONFIG_SYS_SUPPORTS_HUGETLBFS=y
|
||||
# CONFIG_TEXTSEARCH is not set
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
|
||||
CONFIG_THERMAL_EMULATION=y
|
||||
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
|
||||
CONFIG_THERMAL_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_HWMON=y
|
||||
CONFIG_THERMAL_OF=y
|
||||
CONFIG_THREAD_INFO_IN_TASK=y
|
||||
CONFIG_TICK_CPU_ACCOUNTING=y
|
||||
CONFIG_TIMER_OF=y
|
||||
CONFIG_TIMER_PROBE=y
|
||||
CONFIG_TRACE_CLOCK=y
|
||||
CONFIG_TRANSPARENT_HUGEPAGE=y
|
||||
CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
|
||||
# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
|
||||
CONFIG_TRANSPARENT_HUGE_PAGECACHE=y
|
||||
CONFIG_TREE_SRCU=y
|
||||
CONFIG_TYPEC=y
|
||||
# CONFIG_TYPEC_DP_ALTMODE is not set
|
||||
CONFIG_TYPEC_FUSB302=y
|
||||
# CONFIG_TYPEC_MUX_PI3USB30532 is not set
|
||||
# CONFIG_TYPEC_TCPCI is not set
|
||||
CONFIG_TYPEC_TCPM=y
|
||||
# CONFIG_TYPEC_TPS6598X is not set
|
||||
# CONFIG_UCLAMP_TASK is not set
|
||||
# CONFIG_UEVENT_HELPER is not set
|
||||
CONFIG_UNINLINE_SPIN_UNLOCK=y
|
||||
CONFIG_UNMAP_KERNEL_AT_EL0=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_COMMON=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_DUAL_ROLE=y
|
||||
CONFIG_USB_DWC3_HOST=y
|
||||
CONFIG_USB_DWC3_OF_SIMPLE=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD_PLATFORM=y
|
||||
# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
|
||||
CONFIG_USB_HID=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_PHY=y
|
||||
CONFIG_USB_ROLE_SWITCH=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_ULPI_BUS=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_PLATFORM=y
|
||||
# CONFIG_VIRTIO_MENU is not set
|
||||
CONFIG_VMAP_STACK=y
|
||||
CONFIG_VM_EVENT_COUNTERS=y
|
||||
CONFIG_VT=y
|
||||
CONFIG_VT_CONSOLE=y
|
||||
CONFIG_VT_HW_CONSOLE_BINDING=y
|
||||
# CONFIG_WATCHDOG is not set
|
||||
CONFIG_XARRAY_MULTI=y
|
||||
CONFIG_XPS=y
|
||||
CONFIG_XXHASH=y
|
||||
CONFIG_XZ_DEC_ARM=y
|
||||
CONFIG_XZ_DEC_ARMTHUMB=y
|
||||
CONFIG_XZ_DEC_BCJ=y
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
CONFIG_ZONE_DMA32=y
|
||||
|
|
@ -1,696 +0,0 @@
|
|||
CONFIG_64BIT=y
|
||||
CONFIG_AF_UNIX_OOB=y
|
||||
CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
|
||||
CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
|
||||
CONFIG_ARCH_DMA_ADDR_T_64BIT=y
|
||||
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
|
||||
CONFIG_ARCH_KEEP_MEMBLOCK=y
|
||||
CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
|
||||
CONFIG_ARCH_MMAP_RND_BITS_MAX=33
|
||||
CONFIG_ARCH_MMAP_RND_BITS_MIN=18
|
||||
CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
|
||||
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
|
||||
CONFIG_ARCH_PROC_KCORE_TEXT=y
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_ARCH_SPARSEMEM_ENABLE=y
|
||||
CONFIG_ARCH_STACKWALK=y
|
||||
CONFIG_ARCH_SUSPEND_POSSIBLE=y
|
||||
CONFIG_ARCH_WANTS_NO_INSTR=y
|
||||
CONFIG_ARCH_WANTS_THP_SWAP=y
|
||||
CONFIG_ARC_EMAC_CORE=y
|
||||
CONFIG_ARM64=y
|
||||
CONFIG_ARM64_CNP=y
|
||||
CONFIG_ARM64_CRYPTO=y
|
||||
CONFIG_ARM64_EPAN=y
|
||||
CONFIG_ARM64_ERRATUM_819472=y
|
||||
CONFIG_ARM64_ERRATUM_824069=y
|
||||
CONFIG_ARM64_ERRATUM_826319=y
|
||||
CONFIG_ARM64_ERRATUM_827319=y
|
||||
CONFIG_ARM64_ERRATUM_832075=y
|
||||
CONFIG_ARM64_ERRATUM_843419=y
|
||||
CONFIG_ARM64_ERRATUM_845719=y
|
||||
CONFIG_ARM64_ERRATUM_858921=y
|
||||
CONFIG_ARM64_ERRATUM_1742098=y
|
||||
CONFIG_ARM64_HW_AFDBM=y
|
||||
CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
|
||||
CONFIG_ARM64_MODULE_PLTS=y
|
||||
CONFIG_ARM64_PAGE_SHIFT=12
|
||||
CONFIG_ARM64_PAN=y
|
||||
CONFIG_ARM64_PA_BITS=48
|
||||
CONFIG_ARM64_PA_BITS_48=y
|
||||
CONFIG_ARM64_PTR_AUTH=y
|
||||
CONFIG_ARM64_PTR_AUTH_KERNEL=y
|
||||
CONFIG_ARM64_RAS_EXTN=y
|
||||
CONFIG_ARM64_SVE=y
|
||||
# CONFIG_ARM64_SW_TTBR0_PAN is not set
|
||||
CONFIG_ARM64_TAGGED_ADDR_ABI=y
|
||||
CONFIG_ARM64_VA_BITS=48
|
||||
# CONFIG_ARM64_VA_BITS_39 is not set
|
||||
CONFIG_ARM64_VA_BITS_48=y
|
||||
CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
|
||||
# CONFIG_ARMV8_DEPRECATED is not set
|
||||
CONFIG_ARM_AMBA=y
|
||||
CONFIG_ARM_ARCH_TIMER=y
|
||||
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
|
||||
CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
|
||||
CONFIG_ARM_CPUIDLE=y
|
||||
CONFIG_ARM_GIC=y
|
||||
CONFIG_ARM_GIC_V2M=y
|
||||
CONFIG_ARM_GIC_V3=y
|
||||
CONFIG_ARM_GIC_V3_ITS=y
|
||||
CONFIG_ARM_GIC_V3_ITS_PCI=y
|
||||
CONFIG_ARM_MHU=y
|
||||
CONFIG_ARM_PSCI_CPUIDLE=y
|
||||
CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
|
||||
CONFIG_ARM_PSCI_FW=y
|
||||
CONFIG_ARM_RK3328_DMC_DEVFREQ=y
|
||||
# CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
|
||||
# CONFIG_ARM_SCMI_CPUFREQ is not set
|
||||
CONFIG_ARM_SCMI_POWER_CONTROL=y
|
||||
CONFIG_ARM_SCMI_POWER_DOMAIN=y
|
||||
CONFIG_ARM_SCMI_PROTOCOL=y
|
||||
CONFIG_ARM_SCMI_TRANSPORT_MAILBOX=y
|
||||
CONFIG_ARM_SCMI_TRANSPORT_SMC=y
|
||||
# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set
|
||||
CONFIG_ARM_SCPI_CPUFREQ=y
|
||||
CONFIG_ARM_SCPI_POWER_DOMAIN=y
|
||||
CONFIG_ARM_SCPI_PROTOCOL=y
|
||||
CONFIG_ARM_SMMU=y
|
||||
CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT=y
|
||||
# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
|
||||
CONFIG_ARM_SMMU_V3=y
|
||||
# CONFIG_ARM_SMMU_V3_SVA is not set
|
||||
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
CONFIG_BACKLIGHT_GPIO=y
|
||||
CONFIG_BACKLIGHT_PWM=y
|
||||
CONFIG_BINARY_PRINTF=y
|
||||
CONFIG_BLK_DEV_BSG=y
|
||||
CONFIG_BLK_DEV_BSGLIB=y
|
||||
CONFIG_BLK_DEV_BSG_COMMON=y
|
||||
# CONFIG_BLK_DEV_INITRD is not set
|
||||
CONFIG_BLK_DEV_INTEGRITY=y
|
||||
CONFIG_BLK_DEV_INTEGRITY_T10=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_NVME=y
|
||||
CONFIG_BLK_DEV_PCIESSD_MTIP32XX=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_BLK_MQ_PCI=y
|
||||
CONFIG_BLK_PM=y
|
||||
CONFIG_BLOCK_COMPAT=y
|
||||
CONFIG_BRCMSTB_GISB_ARB=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_BSD_PROCESS_ACCT_V3=y
|
||||
CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
|
||||
CONFIG_CHARGER_GPIO=y
|
||||
CONFIG_CLKSRC_MMIO=y
|
||||
CONFIG_CLK_PX30=y
|
||||
CONFIG_CLK_RK3308=y
|
||||
CONFIG_CLK_RK3328=y
|
||||
CONFIG_CLK_RK3368=y
|
||||
CONFIG_CLK_RK3399=y
|
||||
CONFIG_CLK_RK3568=y
|
||||
CONFIG_CLONE_BACKWARDS=y
|
||||
CONFIG_CMA=y
|
||||
CONFIG_CMA_ALIGNMENT=8
|
||||
CONFIG_CMA_AREAS=7
|
||||
# CONFIG_CMA_DEBUG is not set
|
||||
# CONFIG_CMA_DEBUGFS is not set
|
||||
CONFIG_CMA_SIZE_MBYTES=64
|
||||
# CONFIG_CMA_SIZE_SEL_MAX is not set
|
||||
CONFIG_CMA_SIZE_SEL_MBYTES=y
|
||||
# CONFIG_CMA_SIZE_SEL_MIN is not set
|
||||
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
|
||||
CONFIG_COMMON_CLK=y
|
||||
CONFIG_COMMON_CLK_RK808=y
|
||||
CONFIG_COMMON_CLK_ROCKCHIP=y
|
||||
CONFIG_COMMON_CLK_SCMI=y
|
||||
CONFIG_COMMON_CLK_SCPI=y
|
||||
CONFIG_COMPAT=y
|
||||
CONFIG_COMPAT_32BIT_TIME=y
|
||||
CONFIG_COMPAT_BINFMT_ELF=y
|
||||
CONFIG_COMPAT_NETLINK_MESSAGES=y
|
||||
CONFIG_COMPAT_OLD_SIGACTION=y
|
||||
CONFIG_CONFIGFS_FS=y
|
||||
CONFIG_CONSOLE_TRANSLATIONS=y
|
||||
CONFIG_CONTEXT_TRACKING=y
|
||||
CONFIG_CONTEXT_TRACKING_IDLE=y
|
||||
CONFIG_CONTIG_ALLOC=y
|
||||
CONFIG_CPUFREQ_DT=y
|
||||
CONFIG_CPUFREQ_DT_PLATDEV=y
|
||||
CONFIG_CPU_FREQ=y
|
||||
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
|
||||
CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
|
||||
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
|
||||
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
|
||||
# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
|
||||
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
|
||||
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
|
||||
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
|
||||
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
|
||||
CONFIG_CPU_FREQ_STAT=y
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_CPU_IDLE_GOV_MENU=y
|
||||
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
|
||||
CONFIG_CPU_ISOLATION=y
|
||||
CONFIG_CPU_PM=y
|
||||
CONFIG_CPU_RMAP=y
|
||||
CONFIG_CPU_THERMAL=y
|
||||
CONFIG_CRASH_CORE=y
|
||||
CONFIG_CRASH_DUMP=y
|
||||
CONFIG_CRC16=y
|
||||
# CONFIG_CRC32_SARWATE is not set
|
||||
CONFIG_CRC32_SLICEBY8=y
|
||||
CONFIG_CRC64=y
|
||||
CONFIG_CRC64_ROCKSOFT=y
|
||||
CONFIG_CRC_T10DIF=y
|
||||
CONFIG_CROSS_MEMORY_ATTACH=y
|
||||
CONFIG_CRYPTO_AES_ARM64=y
|
||||
CONFIG_CRYPTO_AES_ARM64_CE=y
|
||||
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
|
||||
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
|
||||
CONFIG_CRYPTO_CRC32=y
|
||||
CONFIG_CRYPTO_CRC32C=y
|
||||
CONFIG_CRYPTO_CRC64_ROCKSOFT=y
|
||||
CONFIG_CRYPTO_CRCT10DIF=y
|
||||
CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
|
||||
CONFIG_CRYPTO_CRYPTD=y
|
||||
CONFIG_CRYPTO_GHASH_ARM64_CE=y
|
||||
CONFIG_CRYPTO_LIB_SHA1=y
|
||||
CONFIG_CRYPTO_LIB_SHA256=y
|
||||
CONFIG_CRYPTO_NULL2=y
|
||||
CONFIG_CRYPTO_RNG2=y
|
||||
CONFIG_CRYPTO_SIMD=y
|
||||
CONFIG_DCACHE_WORD_ACCESS=y
|
||||
CONFIG_DEBUG_BUGVERBOSE=y
|
||||
# CONFIG_DEVFREQ_GOV_PASSIVE is not set
|
||||
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
|
||||
CONFIG_DEVFREQ_GOV_POWERSAVE=y
|
||||
CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
|
||||
CONFIG_DEVFREQ_GOV_USERSPACE=y
|
||||
# CONFIG_DEVFREQ_THERMAL is not set
|
||||
CONFIG_DEVMEM=y
|
||||
# CONFIG_DEVPORT is not set
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_DMA_CMA=y
|
||||
CONFIG_DMA_DIRECT_REMAP=y
|
||||
CONFIG_DMA_ENGINE=y
|
||||
CONFIG_DMA_OF=y
|
||||
CONFIG_DMA_OPS=y
|
||||
CONFIG_DMA_SHARED_BUFFER=y
|
||||
CONFIG_DNOTIFY=y
|
||||
CONFIG_DTC=y
|
||||
CONFIG_DT_IDLE_GENPD=y
|
||||
CONFIG_DT_IDLE_STATES=y
|
||||
CONFIG_DUMMY_CONSOLE=y
|
||||
CONFIG_DWMAC_DWC_QOS_ETH=y
|
||||
CONFIG_DWMAC_GENERIC=y
|
||||
CONFIG_DWMAC_ROCKCHIP=y
|
||||
CONFIG_DW_WATCHDOG=y
|
||||
CONFIG_EDAC_SUPPORT=y
|
||||
CONFIG_EEPROM_AT24=y
|
||||
CONFIG_EMAC_ROCKCHIP=y
|
||||
CONFIG_ENERGY_MODEL=y
|
||||
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_EXT4_FS_POSIX_ACL=y
|
||||
CONFIG_EXTCON=y
|
||||
CONFIG_F2FS_FS=y
|
||||
CONFIG_FANOTIFY=y
|
||||
CONFIG_FHANDLE=y
|
||||
CONFIG_FIXED_PHY=y
|
||||
CONFIG_FIX_EARLYCON_MEM=y
|
||||
# CONFIG_FORTIFY_SOURCE is not set
|
||||
CONFIG_FRAME_POINTER=y
|
||||
CONFIG_FRAME_WARN=2048
|
||||
CONFIG_FS_IOMAP=y
|
||||
CONFIG_FS_MBCACHE=y
|
||||
CONFIG_FS_POSIX_ACL=y
|
||||
CONFIG_FWNODE_MDIO=y
|
||||
CONFIG_FW_LOADER_PAGED_BUF=y
|
||||
CONFIG_FW_LOADER_SYSFS=y
|
||||
CONFIG_GENERIC_ALLOCATOR=y
|
||||
CONFIG_GENERIC_ARCH_TOPOLOGY=y
|
||||
CONFIG_GENERIC_BUG=y
|
||||
CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS=y
|
||||
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
|
||||
CONFIG_GENERIC_CPU_AUTOPROBE=y
|
||||
CONFIG_GENERIC_CPU_VULNERABILITIES=y
|
||||
CONFIG_GENERIC_CSUM=y
|
||||
CONFIG_GENERIC_EARLY_IOREMAP=y
|
||||
CONFIG_GENERIC_GETTIMEOFDAY=y
|
||||
CONFIG_GENERIC_IDLE_POLL_SETUP=y
|
||||
CONFIG_GENERIC_IOREMAP=y
|
||||
CONFIG_GENERIC_IRQ_CHIP=y
|
||||
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
|
||||
CONFIG_GENERIC_IRQ_MIGRATION=y
|
||||
CONFIG_GENERIC_IRQ_SHOW=y
|
||||
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
|
||||
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
|
||||
CONFIG_GENERIC_MSI_IRQ=y
|
||||
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_GENERIC_PCI_IOMAP=y
|
||||
CONFIG_GENERIC_PHY=y
|
||||
CONFIG_GENERIC_PINCONF=y
|
||||
CONFIG_GENERIC_SCHED_CLOCK=y
|
||||
CONFIG_GENERIC_SMP_IDLE_THREAD=y
|
||||
CONFIG_GENERIC_STRNCPY_FROM_USER=y
|
||||
CONFIG_GENERIC_STRNLEN_USER=y
|
||||
CONFIG_GENERIC_TIME_VSYSCALL=y
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIOLIB_IRQCHIP=y
|
||||
CONFIG_GPIO_CDEV=y
|
||||
CONFIG_GPIO_DWAPB=y
|
||||
CONFIG_GPIO_GENERIC=y
|
||||
CONFIG_GPIO_GENERIC_PLATFORM=y
|
||||
CONFIG_GPIO_ROCKCHIP=y
|
||||
# CONFIG_HARDENED_USERCOPY is not set
|
||||
CONFIG_HARDIRQS_SW_RESEND=y
|
||||
CONFIG_HAS_DMA=y
|
||||
CONFIG_HAS_IOMEM=y
|
||||
CONFIG_HAS_IOPORT_MAP=y
|
||||
CONFIG_HID=y
|
||||
CONFIG_HID_GENERIC=y
|
||||
CONFIG_HOTPLUG_CPU=y
|
||||
CONFIG_HOTPLUG_PCI=y
|
||||
# CONFIG_HOTPLUG_PCI_CPCI is not set
|
||||
# CONFIG_HOTPLUG_PCI_PCIE is not set
|
||||
CONFIG_HUGETLBFS=y
|
||||
CONFIG_HUGETLB_PAGE=y
|
||||
# CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP is not set
|
||||
CONFIG_HWMON=y
|
||||
CONFIG_HWSPINLOCK=y
|
||||
CONFIG_HW_CONSOLE=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_HW_RANDOM_ROCKCHIP=y
|
||||
CONFIG_HZ=250
|
||||
# CONFIG_HZ_100 is not set
|
||||
CONFIG_HZ_250=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_BOARDINFO=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_COMPAT=y
|
||||
CONFIG_I2C_HELPER_AUTO=y
|
||||
CONFIG_I2C_RK3X=y
|
||||
CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
|
||||
CONFIG_INDIRECT_PIO=y
|
||||
CONFIG_INPUT=y
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_INPUT_FF_MEMLESS=y
|
||||
CONFIG_INPUT_KEYBOARD=y
|
||||
CONFIG_INPUT_LEDS=y
|
||||
CONFIG_INPUT_MATRIXKMAP=y
|
||||
# CONFIG_INPUT_MISC is not set
|
||||
CONFIG_IOMMU_API=y
|
||||
# CONFIG_IOMMU_DEBUGFS is not set
|
||||
# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
|
||||
CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
|
||||
CONFIG_IOMMU_DMA=y
|
||||
CONFIG_IOMMU_IOVA=y
|
||||
CONFIG_IOMMU_IO_PGTABLE=y
|
||||
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
|
||||
CONFIG_IOMMU_IO_PGTABLE_LPAE=y
|
||||
# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
|
||||
CONFIG_IOMMU_SUPPORT=y
|
||||
# CONFIG_IO_STRICT_DEVMEM is not set
|
||||
CONFIG_IO_URING=y
|
||||
CONFIG_IRQCHIP=y
|
||||
CONFIG_IRQ_DOMAIN=y
|
||||
CONFIG_IRQ_DOMAIN_HIERARCHY=y
|
||||
CONFIG_IRQ_FORCED_THREADING=y
|
||||
CONFIG_IRQ_MSI_IOMMU=y
|
||||
CONFIG_IRQ_TIME_ACCOUNTING=y
|
||||
CONFIG_IRQ_WORK=y
|
||||
CONFIG_JBD2=y
|
||||
CONFIG_JFFS2_ZLIB=y
|
||||
CONFIG_JUMP_LABEL=y
|
||||
CONFIG_KALLSYMS=y
|
||||
CONFIG_KEXEC_CORE=y
|
||||
CONFIG_KEXEC_FILE=y
|
||||
# CONFIG_KEXEC_SIG is not set
|
||||
CONFIG_KSM=y
|
||||
# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
|
||||
CONFIG_LEDS_GPIO=y
|
||||
CONFIG_LEDS_PWM=y
|
||||
CONFIG_LEDS_SYSCON=y
|
||||
CONFIG_LEDS_TRIGGER_CPU=y
|
||||
CONFIG_LEDS_TRIGGER_PANIC=y
|
||||
CONFIG_LEGACY_PTYS=y
|
||||
CONFIG_LEGACY_PTY_COUNT=16
|
||||
CONFIG_LIBCRC32C=y
|
||||
CONFIG_LIBFDT=y
|
||||
CONFIG_LOCALVERSION_AUTO=y
|
||||
CONFIG_LOCK_DEBUGGING_SUPPORT=y
|
||||
CONFIG_LOCK_SPIN_ON_OWNER=y
|
||||
CONFIG_LOG_BUF_SHIFT=19
|
||||
CONFIG_LTO_NONE=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_MAGIC_SYSRQ_SERIAL=y
|
||||
CONFIG_MAILBOX=y
|
||||
# CONFIG_MAILBOX_TEST is not set
|
||||
CONFIG_MDIO_BUS=y
|
||||
CONFIG_MDIO_BUS_MUX=y
|
||||
CONFIG_MDIO_BUS_MUX_GPIO=y
|
||||
CONFIG_MDIO_BUS_MUX_MMIOREG=y
|
||||
CONFIG_MDIO_DEVICE=y
|
||||
CONFIG_MDIO_DEVRES=y
|
||||
CONFIG_MEMFD_CREATE=y
|
||||
CONFIG_MEMORY_ISOLATION=y
|
||||
CONFIG_MFD_CORE=y
|
||||
# CONFIG_MFD_KHADAS_MCU is not set
|
||||
CONFIG_MFD_RK808=y
|
||||
CONFIG_MFD_SYSCON=y
|
||||
CONFIG_MIGRATION=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_BLOCK=y
|
||||
CONFIG_MMC_BLOCK_MINORS=32
|
||||
CONFIG_MMC_CQHCI=y
|
||||
CONFIG_MMC_DW=y
|
||||
# CONFIG_MMC_DW_BLUEFIELD is not set
|
||||
# CONFIG_MMC_DW_EXYNOS is not set
|
||||
# CONFIG_MMC_DW_HI3798CV200 is not set
|
||||
# CONFIG_MMC_DW_K3 is not set
|
||||
# CONFIG_MMC_DW_PCI is not set
|
||||
CONFIG_MMC_DW_PLTFM=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_OF_ARASAN=y
|
||||
CONFIG_MMC_SDHCI_OF_DWCMSHC=y
|
||||
# CONFIG_MMC_SDHCI_PCI is not set
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
CONFIG_MODULES_USE_ELF_RELA=y
|
||||
CONFIG_MOTORCOMM_PHY=y
|
||||
CONFIG_MQ_IOSCHED_DEADLINE=y
|
||||
# CONFIG_MTD_CFI is not set
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set
|
||||
CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y
|
||||
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
|
||||
CONFIG_MTD_SPLIT_FIRMWARE=y
|
||||
CONFIG_MUTEX_SPIN_ON_OWNER=y
|
||||
CONFIG_NEED_DMA_MAP_STATE=y
|
||||
CONFIG_NEED_SG_DMA_LENGTH=y
|
||||
CONFIG_NET_FLOW_LIMIT=y
|
||||
CONFIG_NET_SELFTESTS=y
|
||||
CONFIG_NET_SOCK_MSG=y
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NOP_USB_XCEIV=y
|
||||
CONFIG_NO_HZ_COMMON=y
|
||||
CONFIG_NO_HZ_IDLE=y
|
||||
CONFIG_NR_CPUS=256
|
||||
CONFIG_NVMEM=y
|
||||
# CONFIG_NVMEM_RMEM is not set
|
||||
CONFIG_NVMEM_SYSFS=y
|
||||
CONFIG_NVME_CORE=y
|
||||
# CONFIG_NVME_HWMON is not set
|
||||
# CONFIG_NVME_MULTIPATH is not set
|
||||
CONFIG_OF=y
|
||||
CONFIG_OF_ADDRESS=y
|
||||
CONFIG_OF_DYNAMIC=y
|
||||
CONFIG_OF_EARLY_FLATTREE=y
|
||||
CONFIG_OF_FLATTREE=y
|
||||
CONFIG_OF_GPIO=y
|
||||
CONFIG_OF_IOMMU=y
|
||||
CONFIG_OF_IRQ=y
|
||||
CONFIG_OF_KOBJ=y
|
||||
CONFIG_OF_MDIO=y
|
||||
CONFIG_OF_NET=y
|
||||
CONFIG_OF_OVERLAY=y
|
||||
CONFIG_OF_RESOLVE=y
|
||||
CONFIG_OLD_SIGSUSPEND3=y
|
||||
# CONFIG_OVERLAY_FS_XINO_AUTO is not set
|
||||
CONFIG_PADATA=y
|
||||
CONFIG_PAGE_POOL=y
|
||||
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
|
||||
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
|
||||
CONFIG_PAHOLE_VERSION=0
|
||||
# CONFIG_PANIC_ON_OOPS is not set
|
||||
CONFIG_PANIC_ON_OOPS_VALUE=0
|
||||
CONFIG_PANIC_TIMEOUT=0
|
||||
# CONFIG_PARTITION_ADVANCED is not set
|
||||
CONFIG_PARTITION_PERCPU=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCIEAER=y
|
||||
CONFIG_PCIEASPM=y
|
||||
CONFIG_PCIEASPM_DEFAULT=y
|
||||
# CONFIG_PCIEASPM_PERFORMANCE is not set
|
||||
# CONFIG_PCIEASPM_POWERSAVE is not set
|
||||
# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
CONFIG_PCIE_DW=y
|
||||
CONFIG_PCIE_DW_HOST=y
|
||||
CONFIG_PCIE_PME=y
|
||||
CONFIG_PCIE_ROCKCHIP=y
|
||||
CONFIG_PCIE_ROCKCHIP_DW_HOST=y
|
||||
CONFIG_PCIE_ROCKCHIP_HOST=y
|
||||
CONFIG_PCI_DOMAINS=y
|
||||
CONFIG_PCI_DOMAINS_GENERIC=y
|
||||
CONFIG_PCI_MSI=y
|
||||
CONFIG_PCI_MSI_IRQ_DOMAIN=y
|
||||
CONFIG_PCI_STUB=y
|
||||
CONFIG_PCS_XPCS=y
|
||||
CONFIG_PGTABLE_LEVELS=4
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHYLINK=y
|
||||
CONFIG_PHYS_ADDR_T_64BIT=y
|
||||
CONFIG_PHY_ROCKCHIP_DP=y
|
||||
# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
|
||||
CONFIG_PHY_ROCKCHIP_EMMC=y
|
||||
# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set
|
||||
# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
|
||||
# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
|
||||
CONFIG_PHY_ROCKCHIP_PCIE=y
|
||||
CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
|
||||
CONFIG_PHY_ROCKCHIP_TYPEC=y
|
||||
CONFIG_PHY_ROCKCHIP_USB=y
|
||||
CONFIG_PINCTRL=y
|
||||
# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set
|
||||
# CONFIG_PINCTRL_RK805 is not set
|
||||
CONFIG_PINCTRL_ROCKCHIP=y
|
||||
# CONFIG_PINCTRL_SINGLE is not set
|
||||
CONFIG_PL330_DMA=y
|
||||
CONFIG_PLATFORM_MHU=y
|
||||
CONFIG_PM=y
|
||||
CONFIG_PM_CLK=y
|
||||
CONFIG_PM_DEVFREQ=y
|
||||
# CONFIG_PM_DEVFREQ_EVENT is not set
|
||||
CONFIG_PM_GENERIC_DOMAINS=y
|
||||
CONFIG_PM_GENERIC_DOMAINS_OF=y
|
||||
CONFIG_PM_OPP=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_SUPPLY=y
|
||||
CONFIG_POWER_SUPPLY_HWMON=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_PREEMPTION=y
|
||||
CONFIG_PREEMPT_BUILD=y
|
||||
CONFIG_PREEMPT_COUNT=y
|
||||
# CONFIG_PREEMPT_NONE is not set
|
||||
CONFIG_PREEMPT_RCU=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
# CONFIG_PRINT_QUOTA_WARNING is not set
|
||||
CONFIG_PROC_PAGE_MONITOR=y
|
||||
CONFIG_PROC_VMCORE=y
|
||||
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
|
||||
CONFIG_PWM=y
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_PWM_SYSFS=y
|
||||
# CONFIG_QFMT_V1 is not set
|
||||
# CONFIG_QFMT_V2 is not set
|
||||
CONFIG_QUEUED_RWLOCKS=y
|
||||
CONFIG_QUEUED_SPINLOCKS=y
|
||||
CONFIG_QUOTA=y
|
||||
CONFIG_QUOTACTL=y
|
||||
# CONFIG_QUOTA_NETLINK_INTERFACE is not set
|
||||
CONFIG_RAID_ATTRS=y
|
||||
CONFIG_RANDOMIZE_BASE=y
|
||||
CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
|
||||
CONFIG_RANDSTRUCT_NONE=y
|
||||
CONFIG_RAS=y
|
||||
CONFIG_RATIONAL=y
|
||||
# CONFIG_RAVE_SP_CORE is not set
|
||||
CONFIG_RCU_TRACE=y
|
||||
CONFIG_REALTEK_PHY=y
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_REGMAP_I2C=y
|
||||
CONFIG_REGMAP_IRQ=y
|
||||
CONFIG_REGMAP_MMIO=y
|
||||
CONFIG_REGULATOR=y
|
||||
# CONFIG_REGULATOR_ARM_SCMI is not set
|
||||
CONFIG_REGULATOR_FAN53555=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_REGULATOR_GPIO=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_REGULATOR_RK808=y
|
||||
CONFIG_RELOCATABLE=y
|
||||
CONFIG_RESET_CONTROLLER=y
|
||||
CONFIG_RESET_SCMI=y
|
||||
CONFIG_RFS_ACCEL=y
|
||||
CONFIG_ROCKCHIP_EFUSE=y
|
||||
CONFIG_ROCKCHIP_ERRATUM_114514=y
|
||||
CONFIG_ROCKCHIP_GRF=y
|
||||
CONFIG_ROCKCHIP_IODOMAIN=y
|
||||
CONFIG_ROCKCHIP_IOMMU=y
|
||||
CONFIG_ROCKCHIP_MBOX=y
|
||||
# CONFIG_ROCKCHIP_OTP is not set
|
||||
CONFIG_ROCKCHIP_PHY=y
|
||||
CONFIG_ROCKCHIP_PM_DOMAINS=y
|
||||
CONFIG_ROCKCHIP_THERMAL=y
|
||||
CONFIG_ROCKCHIP_TIMER=y
|
||||
CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
|
||||
CONFIG_RPS=y
|
||||
CONFIG_RSEQ=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_RK808=y
|
||||
CONFIG_RTC_I2C_AND_SPI=y
|
||||
CONFIG_RTC_NVMEM=y
|
||||
# CONFIG_RUNTIME_TESTING_MENU is not set
|
||||
CONFIG_RWSEM_SPIN_ON_OWNER=y
|
||||
CONFIG_SCHED_MC=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SCSI_COMMON=y
|
||||
# CONFIG_SCSI_LOWLEVEL is not set
|
||||
# CONFIG_SCSI_PROC_FS is not set
|
||||
CONFIG_SCSI_SAS_ATTRS=y
|
||||
CONFIG_SCSI_SAS_HOST_SMP=y
|
||||
CONFIG_SCSI_SAS_LIBSAS=y
|
||||
# CONFIG_SECURITY_DMESG_RESTRICT is not set
|
||||
# CONFIG_SENSORS_ARM_SCMI is not set
|
||||
CONFIG_SENSORS_ARM_SCPI=y
|
||||
CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
CONFIG_SERIAL_8250_DWLIB=y
|
||||
CONFIG_SERIAL_8250_EXAR=y
|
||||
CONFIG_SERIAL_8250_EXTENDED=y
|
||||
CONFIG_SERIAL_8250_FSL=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=4
|
||||
CONFIG_SERIAL_8250_PCI=y
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
|
||||
CONFIG_SERIAL_8250_SHARE_IRQ=y
|
||||
CONFIG_SERIAL_AMBA_PL011=y
|
||||
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
|
||||
CONFIG_SERIAL_DEV_BUS=y
|
||||
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
|
||||
CONFIG_SERIAL_MCTRL_GPIO=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
CONFIG_SERIO=y
|
||||
CONFIG_SERIO_AMBAKMI=y
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
CONFIG_SG_POOL=y
|
||||
CONFIG_SLUB_DEBUG=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SOCK_RX_QUEUE_MAPPING=y
|
||||
CONFIG_SPARSEMEM=y
|
||||
CONFIG_SPARSEMEM_EXTREME=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP=y
|
||||
CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_BITBANG=y
|
||||
CONFIG_SPI_DYNAMIC=y
|
||||
CONFIG_SPI_MASTER=y
|
||||
CONFIG_SPI_MEM=y
|
||||
CONFIG_SPI_ROCKCHIP=y
|
||||
CONFIG_SPI_SPIDEV=y
|
||||
# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
|
||||
CONFIG_SQUASHFS_DECOMP_SINGLE=y
|
||||
# CONFIG_SQUASHFS_EMBEDDED is not set
|
||||
CONFIG_SQUASHFS_FILE_CACHE=y
|
||||
# CONFIG_SQUASHFS_FILE_DIRECT is not set
|
||||
CONFIG_SRAM=y
|
||||
CONFIG_SRCU=y
|
||||
CONFIG_STACKDEPOT=y
|
||||
CONFIG_STACKPROTECTOR=y
|
||||
CONFIG_STACKPROTECTOR_PER_TASK=y
|
||||
CONFIG_STACKPROTECTOR_STRONG=y
|
||||
CONFIG_STACKTRACE=y
|
||||
# CONFIG_STAGING is not set
|
||||
CONFIG_STMMAC_ETH=y
|
||||
CONFIG_STMMAC_PLATFORM=y
|
||||
# CONFIG_STMMAC_SELFTESTS is not set
|
||||
CONFIG_STRICT_DEVMEM=y
|
||||
# CONFIG_STRIP_ASM_SYMS is not set
|
||||
# CONFIG_SWAP is not set
|
||||
CONFIG_SWIOTLB=y
|
||||
CONFIG_SWPHY=y
|
||||
CONFIG_SYNC_FILE=y
|
||||
CONFIG_SYSCTL_EXCEPTION_TRACE=y
|
||||
CONFIG_SYSFS_SYSCALL=y
|
||||
CONFIG_SYSVIPC_COMPAT=y
|
||||
# CONFIG_TEXTSEARCH is not set
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
|
||||
CONFIG_THERMAL_EMULATION=y
|
||||
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
|
||||
CONFIG_THERMAL_GOV_STEP_WISE=y
|
||||
CONFIG_THERMAL_HWMON=y
|
||||
CONFIG_THERMAL_OF=y
|
||||
CONFIG_THREAD_INFO_IN_TASK=y
|
||||
CONFIG_TICK_CPU_ACCOUNTING=y
|
||||
CONFIG_TIMER_OF=y
|
||||
CONFIG_TIMER_PROBE=y
|
||||
CONFIG_TRACE_CLOCK=y
|
||||
CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
|
||||
CONFIG_TRANSPARENT_HUGEPAGE=y
|
||||
CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
|
||||
# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
|
||||
CONFIG_TRANS_TABLE=y
|
||||
CONFIG_TREE_RCU=y
|
||||
CONFIG_TREE_SRCU=y
|
||||
CONFIG_TYPEC=y
|
||||
CONFIG_TYPEC_FUSB302=y
|
||||
# CONFIG_TYPEC_HD3SS3220 is not set
|
||||
# CONFIG_TYPEC_MUX_PI3USB30532 is not set
|
||||
# CONFIG_TYPEC_STUSB160X is not set
|
||||
# CONFIG_TYPEC_TCPCI is not set
|
||||
CONFIG_TYPEC_TCPM=y
|
||||
# CONFIG_TYPEC_TPS6598X is not set
|
||||
# CONFIG_UACCE is not set
|
||||
# CONFIG_UCLAMP_TASK is not set
|
||||
# CONFIG_UEVENT_HELPER is not set
|
||||
CONFIG_UNINLINE_SPIN_UNLOCK=y
|
||||
CONFIG_UNMAP_KERNEL_AT_EL0=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_COMMON=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_HOST=y
|
||||
CONFIG_USB_DWC3_OF_SIMPLE=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD_PLATFORM=y
|
||||
# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
|
||||
CONFIG_USB_HID=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_PHY=y
|
||||
CONFIG_USB_ROLE_SWITCH=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_SUPPORT=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_ULPI_BUS=y
|
||||
CONFIG_USB_ULPI_VIEWPORT=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_PLATFORM=y
|
||||
# CONFIG_VIRTIO_MENU is not set
|
||||
CONFIG_VMAP_STACK=y
|
||||
CONFIG_VM_EVENT_COUNTERS=y
|
||||
CONFIG_VT=y
|
||||
CONFIG_VT_CONSOLE=y
|
||||
CONFIG_VT_HW_CONSOLE_BINDING=y
|
||||
CONFIG_WATCHDOG_CORE=y
|
||||
CONFIG_XARRAY_MULTI=y
|
||||
CONFIG_XPS=y
|
||||
CONFIG_XXHASH=y
|
||||
CONFIG_XZ_DEC_ARM=y
|
||||
CONFIG_XZ_DEC_ARMTHUMB=y
|
||||
CONFIG_XZ_DEC_BCJ=y
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_ZLIB_INFLATE=y
|
||||
CONFIG_ZONE_DMA32=y
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
ARCH:=aarch64
|
||||
SUBTARGET:=armv8
|
||||
BOARDNAME:=RK33xx/RK35xx boards (64 bit)
|
||||
|
||||
define Target/Description
|
||||
Build firmware image for Rockchip RK33xx/RK35xx devices.
|
||||
This firmware features a 64 bit kernel.
|
||||
endef
|
||||
|
|
@ -1,311 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#include <dt-bindings/clock/rockchip-ddr.h>
|
||||
#include <dt-bindings/memory/rk3328-dram.h>
|
||||
|
||||
/ {
|
||||
ddr_timing: ddr_timing {
|
||||
compatible = "rockchip,ddr-timing";
|
||||
ddr3_speed_bin = <DDR3_DEFAULT>;
|
||||
ddr4_speed_bin = <DDR4_DEFAULT>;
|
||||
pd_idle = <0>;
|
||||
sr_idle = <0>;
|
||||
sr_mc_gate_idle = <0>;
|
||||
srpd_lite_idle = <0>;
|
||||
standby_idle = <0>;
|
||||
|
||||
auto_pd_dis_freq = <1066>;
|
||||
auto_sr_dis_freq = <800>;
|
||||
ddr3_dll_dis_freq = <300>;
|
||||
ddr4_dll_dis_freq = <625>;
|
||||
phy_dll_dis_freq = <400>;
|
||||
|
||||
ddr3_odt_dis_freq = <100>;
|
||||
phy_ddr3_odt_dis_freq = <100>;
|
||||
ddr3_drv = <DDR3_DS_40ohm>;
|
||||
ddr3_odt = <DDR3_ODT_120ohm>;
|
||||
phy_ddr3_ca_drv = <PHY_DDR3_RON_RTT_34ohm>;
|
||||
phy_ddr3_ck_drv = <PHY_DDR3_RON_RTT_45ohm>;
|
||||
phy_ddr3_dq_drv = <PHY_DDR3_RON_RTT_34ohm>;
|
||||
phy_ddr3_odt = <PHY_DDR3_RON_RTT_225ohm>;
|
||||
|
||||
lpddr3_odt_dis_freq = <666>;
|
||||
phy_lpddr3_odt_dis_freq = <666>;
|
||||
lpddr3_drv = <LP3_DS_40ohm>;
|
||||
lpddr3_odt = <LP3_ODT_240ohm>;
|
||||
phy_lpddr3_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
|
||||
phy_lpddr3_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
|
||||
phy_lpddr3_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
|
||||
phy_lpddr3_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
|
||||
|
||||
lpddr4_odt_dis_freq = <800>;
|
||||
phy_lpddr4_odt_dis_freq = <800>;
|
||||
lpddr4_drv = <LP4_PDDS_60ohm>;
|
||||
lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
|
||||
lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
|
||||
phy_lpddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_40ohm>;
|
||||
phy_lpddr4_ck_cs_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
|
||||
phy_lpddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_80ohm>;
|
||||
phy_lpddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_60ohm>;
|
||||
|
||||
ddr4_odt_dis_freq = <666>;
|
||||
phy_ddr4_odt_dis_freq = <666>;
|
||||
ddr4_drv = <DDR4_DS_34ohm>;
|
||||
ddr4_odt = <DDR4_RTT_NOM_240ohm>;
|
||||
phy_ddr4_ca_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
|
||||
phy_ddr4_ck_drv = <PHY_DDR4_LPDDR3_RON_RTT_43ohm>;
|
||||
phy_ddr4_dq_drv = <PHY_DDR4_LPDDR3_RON_RTT_34ohm>;
|
||||
phy_ddr4_odt = <PHY_DDR4_LPDDR3_RON_RTT_240ohm>;
|
||||
|
||||
/* CA de-skew, one step is 47.8ps, range 0-15 */
|
||||
ddr3a1_ddr4a9_de-skew = <7>;
|
||||
ddr3a0_ddr4a10_de-skew = <7>;
|
||||
ddr3a3_ddr4a6_de-skew = <8>;
|
||||
ddr3a2_ddr4a4_de-skew = <8>;
|
||||
ddr3a5_ddr4a8_de-skew = <7>;
|
||||
ddr3a4_ddr4a5_de-skew = <9>;
|
||||
ddr3a7_ddr4a11_de-skew = <7>;
|
||||
ddr3a6_ddr4a7_de-skew = <9>;
|
||||
ddr3a9_ddr4a0_de-skew = <8>;
|
||||
ddr3a8_ddr4a13_de-skew = <7>;
|
||||
ddr3a11_ddr4a3_de-skew = <9>;
|
||||
ddr3a10_ddr4cs0_de-skew = <7>;
|
||||
ddr3a13_ddr4a2_de-skew = <8>;
|
||||
ddr3a12_ddr4ba1_de-skew = <7>;
|
||||
ddr3a15_ddr4odt0_de-skew = <7>;
|
||||
ddr3a14_ddr4a1_de-skew = <8>;
|
||||
ddr3ba1_ddr4a15_de-skew = <7>;
|
||||
ddr3ba0_ddr4bg0_de-skew = <7>;
|
||||
ddr3ras_ddr4cke_de-skew = <7>;
|
||||
ddr3ba2_ddr4ba0_de-skew = <8>;
|
||||
ddr3we_ddr4bg1_de-skew = <8>;
|
||||
ddr3cas_ddr4a12_de-skew = <7>;
|
||||
ddr3ckn_ddr4ckn_de-skew = <8>;
|
||||
ddr3ckp_ddr4ckp_de-skew = <8>;
|
||||
ddr3cke_ddr4a16_de-skew = <8>;
|
||||
ddr3odt0_ddr4a14_de-skew = <7>;
|
||||
ddr3cs0_ddr4act_de-skew = <8>;
|
||||
ddr3reset_ddr4reset_de-skew = <7>;
|
||||
ddr3cs1_ddr4cs1_de-skew = <7>;
|
||||
ddr3odt1_ddr4odt1_de-skew = <7>;
|
||||
|
||||
/* DATA de-skew
|
||||
* RX one step is 25.1ps, range 0-15
|
||||
* TX one step is 47.8ps, range 0-15
|
||||
*/
|
||||
cs0_dm0_rx_de-skew = <7>;
|
||||
cs0_dm0_tx_de-skew = <8>;
|
||||
cs0_dq0_rx_de-skew = <7>;
|
||||
cs0_dq0_tx_de-skew = <8>;
|
||||
cs0_dq1_rx_de-skew = <7>;
|
||||
cs0_dq1_tx_de-skew = <8>;
|
||||
cs0_dq2_rx_de-skew = <7>;
|
||||
cs0_dq2_tx_de-skew = <8>;
|
||||
cs0_dq3_rx_de-skew = <7>;
|
||||
cs0_dq3_tx_de-skew = <8>;
|
||||
cs0_dq4_rx_de-skew = <7>;
|
||||
cs0_dq4_tx_de-skew = <8>;
|
||||
cs0_dq5_rx_de-skew = <7>;
|
||||
cs0_dq5_tx_de-skew = <8>;
|
||||
cs0_dq6_rx_de-skew = <7>;
|
||||
cs0_dq6_tx_de-skew = <8>;
|
||||
cs0_dq7_rx_de-skew = <7>;
|
||||
cs0_dq7_tx_de-skew = <8>;
|
||||
cs0_dqs0_rx_de-skew = <6>;
|
||||
cs0_dqs0p_tx_de-skew = <9>;
|
||||
cs0_dqs0n_tx_de-skew = <9>;
|
||||
|
||||
cs0_dm1_rx_de-skew = <7>;
|
||||
cs0_dm1_tx_de-skew = <7>;
|
||||
cs0_dq8_rx_de-skew = <7>;
|
||||
cs0_dq8_tx_de-skew = <8>;
|
||||
cs0_dq9_rx_de-skew = <7>;
|
||||
cs0_dq9_tx_de-skew = <7>;
|
||||
cs0_dq10_rx_de-skew = <7>;
|
||||
cs0_dq10_tx_de-skew = <8>;
|
||||
cs0_dq11_rx_de-skew = <7>;
|
||||
cs0_dq11_tx_de-skew = <7>;
|
||||
cs0_dq12_rx_de-skew = <7>;
|
||||
cs0_dq12_tx_de-skew = <8>;
|
||||
cs0_dq13_rx_de-skew = <7>;
|
||||
cs0_dq13_tx_de-skew = <7>;
|
||||
cs0_dq14_rx_de-skew = <7>;
|
||||
cs0_dq14_tx_de-skew = <8>;
|
||||
cs0_dq15_rx_de-skew = <7>;
|
||||
cs0_dq15_tx_de-skew = <7>;
|
||||
cs0_dqs1_rx_de-skew = <7>;
|
||||
cs0_dqs1p_tx_de-skew = <9>;
|
||||
cs0_dqs1n_tx_de-skew = <9>;
|
||||
|
||||
cs0_dm2_rx_de-skew = <7>;
|
||||
cs0_dm2_tx_de-skew = <8>;
|
||||
cs0_dq16_rx_de-skew = <7>;
|
||||
cs0_dq16_tx_de-skew = <8>;
|
||||
cs0_dq17_rx_de-skew = <7>;
|
||||
cs0_dq17_tx_de-skew = <8>;
|
||||
cs0_dq18_rx_de-skew = <7>;
|
||||
cs0_dq18_tx_de-skew = <8>;
|
||||
cs0_dq19_rx_de-skew = <7>;
|
||||
cs0_dq19_tx_de-skew = <8>;
|
||||
cs0_dq20_rx_de-skew = <7>;
|
||||
cs0_dq20_tx_de-skew = <8>;
|
||||
cs0_dq21_rx_de-skew = <7>;
|
||||
cs0_dq21_tx_de-skew = <8>;
|
||||
cs0_dq22_rx_de-skew = <7>;
|
||||
cs0_dq22_tx_de-skew = <8>;
|
||||
cs0_dq23_rx_de-skew = <7>;
|
||||
cs0_dq23_tx_de-skew = <8>;
|
||||
cs0_dqs2_rx_de-skew = <6>;
|
||||
cs0_dqs2p_tx_de-skew = <9>;
|
||||
cs0_dqs2n_tx_de-skew = <9>;
|
||||
|
||||
cs0_dm3_rx_de-skew = <7>;
|
||||
cs0_dm3_tx_de-skew = <7>;
|
||||
cs0_dq24_rx_de-skew = <7>;
|
||||
cs0_dq24_tx_de-skew = <8>;
|
||||
cs0_dq25_rx_de-skew = <7>;
|
||||
cs0_dq25_tx_de-skew = <7>;
|
||||
cs0_dq26_rx_de-skew = <7>;
|
||||
cs0_dq26_tx_de-skew = <7>;
|
||||
cs0_dq27_rx_de-skew = <7>;
|
||||
cs0_dq27_tx_de-skew = <7>;
|
||||
cs0_dq28_rx_de-skew = <7>;
|
||||
cs0_dq28_tx_de-skew = <7>;
|
||||
cs0_dq29_rx_de-skew = <7>;
|
||||
cs0_dq29_tx_de-skew = <7>;
|
||||
cs0_dq30_rx_de-skew = <7>;
|
||||
cs0_dq30_tx_de-skew = <7>;
|
||||
cs0_dq31_rx_de-skew = <7>;
|
||||
cs0_dq31_tx_de-skew = <7>;
|
||||
cs0_dqs3_rx_de-skew = <7>;
|
||||
cs0_dqs3p_tx_de-skew = <9>;
|
||||
cs0_dqs3n_tx_de-skew = <9>;
|
||||
|
||||
cs1_dm0_rx_de-skew = <7>;
|
||||
cs1_dm0_tx_de-skew = <8>;
|
||||
cs1_dq0_rx_de-skew = <7>;
|
||||
cs1_dq0_tx_de-skew = <8>;
|
||||
cs1_dq1_rx_de-skew = <7>;
|
||||
cs1_dq1_tx_de-skew = <8>;
|
||||
cs1_dq2_rx_de-skew = <7>;
|
||||
cs1_dq2_tx_de-skew = <8>;
|
||||
cs1_dq3_rx_de-skew = <7>;
|
||||
cs1_dq3_tx_de-skew = <8>;
|
||||
cs1_dq4_rx_de-skew = <7>;
|
||||
cs1_dq4_tx_de-skew = <8>;
|
||||
cs1_dq5_rx_de-skew = <7>;
|
||||
cs1_dq5_tx_de-skew = <8>;
|
||||
cs1_dq6_rx_de-skew = <7>;
|
||||
cs1_dq6_tx_de-skew = <8>;
|
||||
cs1_dq7_rx_de-skew = <7>;
|
||||
cs1_dq7_tx_de-skew = <8>;
|
||||
cs1_dqs0_rx_de-skew = <6>;
|
||||
cs1_dqs0p_tx_de-skew = <9>;
|
||||
cs1_dqs0n_tx_de-skew = <9>;
|
||||
|
||||
cs1_dm1_rx_de-skew = <7>;
|
||||
cs1_dm1_tx_de-skew = <7>;
|
||||
cs1_dq8_rx_de-skew = <7>;
|
||||
cs1_dq8_tx_de-skew = <8>;
|
||||
cs1_dq9_rx_de-skew = <7>;
|
||||
cs1_dq9_tx_de-skew = <7>;
|
||||
cs1_dq10_rx_de-skew = <7>;
|
||||
cs1_dq10_tx_de-skew = <8>;
|
||||
cs1_dq11_rx_de-skew = <7>;
|
||||
cs1_dq11_tx_de-skew = <7>;
|
||||
cs1_dq12_rx_de-skew = <7>;
|
||||
cs1_dq12_tx_de-skew = <8>;
|
||||
cs1_dq13_rx_de-skew = <7>;
|
||||
cs1_dq13_tx_de-skew = <7>;
|
||||
cs1_dq14_rx_de-skew = <7>;
|
||||
cs1_dq14_tx_de-skew = <8>;
|
||||
cs1_dq15_rx_de-skew = <7>;
|
||||
cs1_dq15_tx_de-skew = <7>;
|
||||
cs1_dqs1_rx_de-skew = <7>;
|
||||
cs1_dqs1p_tx_de-skew = <9>;
|
||||
cs1_dqs1n_tx_de-skew = <9>;
|
||||
|
||||
cs1_dm2_rx_de-skew = <7>;
|
||||
cs1_dm2_tx_de-skew = <8>;
|
||||
cs1_dq16_rx_de-skew = <7>;
|
||||
cs1_dq16_tx_de-skew = <8>;
|
||||
cs1_dq17_rx_de-skew = <7>;
|
||||
cs1_dq17_tx_de-skew = <8>;
|
||||
cs1_dq18_rx_de-skew = <7>;
|
||||
cs1_dq18_tx_de-skew = <8>;
|
||||
cs1_dq19_rx_de-skew = <7>;
|
||||
cs1_dq19_tx_de-skew = <8>;
|
||||
cs1_dq20_rx_de-skew = <7>;
|
||||
cs1_dq20_tx_de-skew = <8>;
|
||||
cs1_dq21_rx_de-skew = <7>;
|
||||
cs1_dq21_tx_de-skew = <8>;
|
||||
cs1_dq22_rx_de-skew = <7>;
|
||||
cs1_dq22_tx_de-skew = <8>;
|
||||
cs1_dq23_rx_de-skew = <7>;
|
||||
cs1_dq23_tx_de-skew = <8>;
|
||||
cs1_dqs2_rx_de-skew = <6>;
|
||||
cs1_dqs2p_tx_de-skew = <9>;
|
||||
cs1_dqs2n_tx_de-skew = <9>;
|
||||
|
||||
cs1_dm3_rx_de-skew = <7>;
|
||||
cs1_dm3_tx_de-skew = <7>;
|
||||
cs1_dq24_rx_de-skew = <7>;
|
||||
cs1_dq24_tx_de-skew = <8>;
|
||||
cs1_dq25_rx_de-skew = <7>;
|
||||
cs1_dq25_tx_de-skew = <7>;
|
||||
cs1_dq26_rx_de-skew = <7>;
|
||||
cs1_dq26_tx_de-skew = <7>;
|
||||
cs1_dq27_rx_de-skew = <7>;
|
||||
cs1_dq27_tx_de-skew = <7>;
|
||||
cs1_dq28_rx_de-skew = <7>;
|
||||
cs1_dq28_tx_de-skew = <7>;
|
||||
cs1_dq29_rx_de-skew = <7>;
|
||||
cs1_dq29_tx_de-skew = <7>;
|
||||
cs1_dq30_rx_de-skew = <7>;
|
||||
cs1_dq30_tx_de-skew = <7>;
|
||||
cs1_dq31_rx_de-skew = <7>;
|
||||
cs1_dq31_tx_de-skew = <7>;
|
||||
cs1_dqs3_rx_de-skew = <7>;
|
||||
cs1_dqs3p_tx_de-skew = <9>;
|
||||
cs1_dqs3n_tx_de-skew = <9>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,733 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/pwm/pwm.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "rk3399.dtsi"
|
||||
#include "rk3399-opp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Dilusense DLFR100";
|
||||
compatible = "dilusense,dlfr100", "rockchip,rk3399";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
clkin_gmac: external-gmac-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "clkin_gmac";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
clocks = <&rk808 1>;
|
||||
clock-names = "ext_clock";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_enable_h>;
|
||||
reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
vcc5v0_host: vcc5v0-host-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_host_en>;
|
||||
regulator-name = "vcc5v0_host";
|
||||
};
|
||||
|
||||
vcc_phy: vcc-phy-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_phy";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc_sd: vcc-sd {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc_sd_h>;
|
||||
regulator-name = "vcc_sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
adc-keys {
|
||||
compatible = "adc-keys";
|
||||
io-channels = <&saradc 1>;
|
||||
io-channel-names = "buttons";
|
||||
keyup-threshold-microvolt = <1800000>;
|
||||
poll-interval = <100>;
|
||||
|
||||
button-up {
|
||||
label = "Volume Up";
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
press-threshold-microvolt = <100000>;
|
||||
};
|
||||
|
||||
button-down {
|
||||
label = "Volume Down";
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
press-threshold-microvolt = <300000>;
|
||||
};
|
||||
|
||||
back {
|
||||
label = "Back";
|
||||
linux,code = <KEY_BACK>;
|
||||
press-threshold-microvolt = <985000>;
|
||||
};
|
||||
|
||||
menu {
|
||||
label = "Menu";
|
||||
linux,code = <KEY_MENU>;
|
||||
press-threshold-microvolt = <0x1314000>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
autorepeat;
|
||||
pinctrl-0 = <&pwr_btn>;
|
||||
|
||||
power {
|
||||
debounce-interval = <100>;
|
||||
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
|
||||
label = "GPIO Key Power";
|
||||
linux,code = <KEY_POWER>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
rt5640-sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "realtek,rt5640-codec";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,mclk-fs = <256>;
|
||||
simple-audio-card,widgets =
|
||||
"Microphone", "Mic Jack",
|
||||
"Headphone", "Headphones";
|
||||
simple-audio-card,routing =
|
||||
"Mic Jack", "micbias1",
|
||||
"Headphones", "HPOL",
|
||||
"Headphones", "HPOR";
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&i2s0>;
|
||||
};
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&rt5640>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu_l0 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l1 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l2 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l3 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_b0 {
|
||||
cpu-supply = <&vdd_cpu_b>;
|
||||
};
|
||||
|
||||
&cpu_b1 {
|
||||
cpu-supply = <&vdd_cpu_b>;
|
||||
};
|
||||
|
||||
&emmc_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac {
|
||||
assigned-clocks = <&cru SCLK_RMII_SRC>;
|
||||
assigned-clock-parents = <&clkin_gmac>;
|
||||
clock_in_out = "input";
|
||||
phy-supply = <&vcc_phy>;
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&rtl8211e>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>;
|
||||
tx_delay = <0x28>;
|
||||
rx_delay = <0x11>;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rtl8211e: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
rk808: pmic@1b {
|
||||
compatible = "rockchip,rk808";
|
||||
reg = <0x1b>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "rk808-clkout1", "rk808-clkout2";
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
vcc10-supply = <&vcc3v3_sys>;
|
||||
vcc11-supply = <&vcc3v3_sys>;
|
||||
vcc12-supply = <&vcc3v3_sys>;
|
||||
vddio-supply = <&vcc1v8_pmu>;
|
||||
|
||||
regulators {
|
||||
vdd_center: DCDC_REG1 {
|
||||
regulator-name = "vdd_center";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_l: DCDC_REG2 {
|
||||
regulator-name = "vdd_cpu_l";
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG4 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc1v8_dvp: LDO_REG1 {
|
||||
regulator-name = "vcc1v8_dvp";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v0_tp: LDO_REG2 {
|
||||
regulator-name = "vcc3v0_tp";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc1v8_pmu: LDO_REG3 {
|
||||
regulator-name = "vcc1v8_pmu";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sdio: LDO_REG4 {
|
||||
regulator-name = "vcc_sdio";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca3v0_codec: LDO_REG5 {
|
||||
regulator-name = "vcca3v0_codec";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v5: LDO_REG6 {
|
||||
regulator-name = "vcc_1v5";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1500000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_codec: LDO_REG7 {
|
||||
regulator-name = "vcca1v8_codec";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v0: LDO_REG8 {
|
||||
regulator-name = "vcc_3v0";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_s3: SWITCH_REG1 {
|
||||
regulator-name = "vcc3v3_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_s0: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_b: regulator@40 {
|
||||
compatible = "silergy,syr827";
|
||||
reg = <0x40>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
pinctrl-0 = <&vsel1_pin>;
|
||||
pinctrl-names = "default";
|
||||
regulator-name = "vdd_cpu_b";
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-ramp-delay = <1000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-state = <3>;
|
||||
vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: regulator@41 {
|
||||
compatible = "silergy,syr828";
|
||||
reg = <0x41>;
|
||||
pinctrl-0 = <&vsel2_pin>;
|
||||
pinctrl-names = "default";
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-ramp-delay = <1000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-state = <3>;
|
||||
vsel-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
isl1208@6f {
|
||||
compatible = "isil,isl1208";
|
||||
reg = <0x6f>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
i2c-scl-rising-time-ns = <300>;
|
||||
i2c-scl-falling-time-ns = <15>;
|
||||
status = "okay";
|
||||
|
||||
rt5640: rt5640@1c {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "realtek,rt5640";
|
||||
reg = <0x1c>;
|
||||
realtek,in1-differential;
|
||||
pinctrl-0 = <&i2s_8ch_mclk>;
|
||||
clocks = <&cru SCLK_I2S_8CH_OUT>;
|
||||
clock-names = "mclk";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2s0 {
|
||||
rockchip,playback-channels = <8>;
|
||||
rockchip,capture-channels = <8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2s2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&io_domains {
|
||||
status = "okay";
|
||||
|
||||
bt656-supply = <&vcc_3v0>;
|
||||
audio-supply = <&vcca1v8_codec>;
|
||||
sdmmc-supply = <&vcc_sdio>;
|
||||
gpio1830-supply = <&vcc_3v0>;
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
ep-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
max-link-speed = <1>;
|
||||
num-lanes = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_clkreqn_cpm>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0 {
|
||||
reg = <0x00000000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie-eth@0,0 {
|
||||
compatible = "realtek,r8168";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
realtek,led-data = <0x87>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
buttons {
|
||||
pwr_btn: pwr-btn {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
i2s0 {
|
||||
i2s_8ch_mclk: i2s-8ch-mclk {
|
||||
rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int_l: pmic-int-l {
|
||||
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
vsel1_pin: vsel1-pin {
|
||||
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
|
||||
vsel2_pin: vsel2-pin {
|
||||
rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
|
||||
pmic_dvs2:pmic-dvs2 {
|
||||
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio-pwrseq {
|
||||
wifi_enable_h: wifi-enable-h {
|
||||
rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb2 {
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sd {
|
||||
vcc_sd_h: vcc-sd-h {
|
||||
rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac {
|
||||
phy_intb: phy-intb {
|
||||
rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
phy_rstb: phy-rstb {
|
||||
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdio0 {
|
||||
bus-width = <4>;
|
||||
disable-wp;
|
||||
cap-sd-highspeed;
|
||||
cap-sdio-irq;
|
||||
keep-power-in-suspend;
|
||||
clock-frequency = <50000000>;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
clock-frequency = <150000000>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_cd>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc_sd>;
|
||||
vqmmc-supply = <&vcc_sdio>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tcphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tcphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
/* tshut mode 0:CRU 1:GPIO */
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
/* tshut polarity 0:LOW 1:HIGH */
|
||||
rockchip,hw-tshut-polarity = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_xfer &uart0_cts>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&usbdrd3_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&vopb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -1,664 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "rk3399.dtsi"
|
||||
#include "rk3399-opp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SHAREVDI GuangMiao G4C";
|
||||
compatible = "sharevdi,guangmiao-g4c", "rockchip,rk3399";
|
||||
|
||||
/delete-node/ display-subsystem;
|
||||
|
||||
aliases {
|
||||
led-boot = &status_led;
|
||||
led-failsafe = &status_led;
|
||||
led-running = &status_led;
|
||||
led-upgrade = &status_led;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
clkin_gmac: external-gmac-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "clkin_gmac";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
vcc_sys: vcc-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc_sys";
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_sys";
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
vcc_0v9: vcc-0v9 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vcc_0v9";
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
vcc5v0_host0: vcc5v0-host0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc5v0_host0";
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
vdd_log: vdd-log {
|
||||
compatible = "pwm-regulator";
|
||||
pwms = <&pwm2 0 25000 1>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-name = "vdd_log";
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&reset_button_pin>;
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
debounce-interval = <100>;
|
||||
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lan_led_pin>, <&status_led_pin>, <&wan_led_pin>;
|
||||
|
||||
lan_led: led-lan {
|
||||
gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:lan";
|
||||
};
|
||||
|
||||
status_led: led-status {
|
||||
gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:status";
|
||||
};
|
||||
|
||||
wan_led: led-wan {
|
||||
gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:wan";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu_b0 {
|
||||
cpu-supply = <&vdd_cpu_b>;
|
||||
};
|
||||
|
||||
&cpu_b1 {
|
||||
cpu-supply = <&vdd_cpu_b>;
|
||||
};
|
||||
|
||||
&cpu_l0 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l1 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l2 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l3 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&emmc_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac {
|
||||
assigned-clock-parents = <&clkin_gmac>;
|
||||
assigned-clocks = <&cru SCLK_RMII_SRC>;
|
||||
clock_in_out = "input";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_pmeb>, <&phy_rstb>;
|
||||
phy-handle = <&rtl8211e>;
|
||||
phy-mode = "rgmii";
|
||||
phy-supply = <&vcc3v3_s3>;
|
||||
tx_delay = <0x28>;
|
||||
rx_delay = <0x11>;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
compatible = "snps,dwmac-mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
rtl8211e: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
|
||||
reset-assert-us = <10000>;
|
||||
reset-deassert-us = <30000>;
|
||||
reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <400000>;
|
||||
i2c-scl-rising-time-ns = <160>;
|
||||
i2c-scl-falling-time-ns = <30>;
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu_b: regulator@40 {
|
||||
compatible = "silergy,syr827";
|
||||
reg = <0x40>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cpu_b_sleep>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-name = "vdd_cpu_b";
|
||||
regulator-ramp-delay = <1000>;
|
||||
vin-supply = <&vcc_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: regulator@41 {
|
||||
compatible = "silergy,syr828";
|
||||
reg = <0x41>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gpu_sleep>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-ramp-delay = <1000>;
|
||||
vin-supply = <&vcc_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk808: pmic@1b {
|
||||
compatible = "rockchip,rk808";
|
||||
reg = <0x1b>;
|
||||
clock-output-names = "rtc_clko_soc", "rtc_clko_wifi";
|
||||
#clock-cells = <1>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int_l>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc_sys>;
|
||||
vcc2-supply = <&vcc_sys>;
|
||||
vcc3-supply = <&vcc_sys>;
|
||||
vcc4-supply = <&vcc_sys>;
|
||||
vcc6-supply = <&vcc_sys>;
|
||||
vcc7-supply = <&vcc_sys>;
|
||||
vcc8-supply = <&vcc_3v0>;
|
||||
vcc9-supply = <&vcc_sys>;
|
||||
vcc10-supply = <&vcc_sys>;
|
||||
vcc11-supply = <&vcc_sys>;
|
||||
vcc12-supply = <&vcc_sys>;
|
||||
vddio-supply = <&vcc_3v0>;
|
||||
|
||||
regulators {
|
||||
vdd_center: DCDC_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_center";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_l: DCDC_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_cpu_l";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc_ddr";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_vldo1: LDO_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_vldo1";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_vldo2: LDO_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_vldo2";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sdio: LDO_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc_sdio";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v0_sd: LDO_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-name = "vcc3v0_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v5: LDO_REG6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-name = "vcc_1v5";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1500000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_codec: LDO_REG7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca1v8_codec";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v0: LDO_REG8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-name = "vcc_3v0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_s3: SWITCH_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc3v3_s3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_s0: SWITCH_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc3v3_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
i2c-scl-rising-time-ns = <450>;
|
||||
i2c-scl-falling-time-ns = <15>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&io_domains {
|
||||
bt656-supply = <&vcc_1v8>;
|
||||
audio-supply = <&vcca1v8_codec>;
|
||||
sdmmc-supply = <&vcc_sdio>;
|
||||
gpio1830-supply = <&vcc_3v0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
ep-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
max-link-speed = <1>;
|
||||
num-lanes = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_clkreqnb_cpm>;
|
||||
vpcie0v9-supply = <&vcc_0v9>;
|
||||
vpcie1v8-supply = <&vcca_1v8>;
|
||||
vpcie3v3-supply = <&vcc3v3_sys>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0 {
|
||||
reg = <0x00000000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie-eth@0,0 {
|
||||
compatible = "realtek,r8168";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
|
||||
realtek,led-data = <0x87>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
gpio-leds {
|
||||
lan_led_pin: lan-led-pin {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
status_led_pin: status-led-pin {
|
||||
rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
wan_led_pin: wan-led-pin {
|
||||
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
gmac {
|
||||
phy_intb: phy-intb {
|
||||
rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
phy_pmeb: phy-pmeb {
|
||||
rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
phy_rstb: phy-rstb {
|
||||
rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
cpu_b_sleep: cpu-b-sleep {
|
||||
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
|
||||
gpu_sleep: gpu-sleep {
|
||||
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
|
||||
pmic_int_l: pmic-int-l {
|
||||
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
rockchip-key {
|
||||
reset_button_pin: reset-button-pin {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio {
|
||||
bt_reg_on_h: bt-reg-on-h {
|
||||
/* external pullup to VCC1V8_PMUPLL */
|
||||
rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sdmmc {
|
||||
sdmmc0_det_l: sdmmc0-det-l {
|
||||
rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmu1830-supply = <&vcc_3v0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
pinctrl-names = "active";
|
||||
pinctrl-0 = <&pwm2_pin_pull_down>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcc_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
mmc-hs200-1_8v;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>;
|
||||
vqmmc-supply = <&vcc_sdio>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tcphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tcphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0_host {
|
||||
phy-supply = <&vcc5v0_host0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1_host {
|
||||
phy-supply = <&vcc5v0_host0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd3_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_0 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_1 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -1,837 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/input/linux-event-codes.h>
|
||||
#include "rk3399.dtsi"
|
||||
#include "rk3399-opp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SHAREVDI H3399PC";
|
||||
compatible = "sharevdi,h3399pc", "rockchip,rk3399";
|
||||
|
||||
aliases {
|
||||
mmc0 = &sdio0;
|
||||
mmc1 = &sdmmc;
|
||||
mmc2 = &sdhci;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
clkin_gmac: external-gmac-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "clkin_gmac";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
dc_12v: dc-12v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dc_12v";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
autorepeat;
|
||||
|
||||
power {
|
||||
debounce-interval = <100>;
|
||||
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
|
||||
label = "GPIO Key Power";
|
||||
linux,code = <KEY_POWER>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&work_led_pin>, <&diy_led_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
work_led: led-0 {
|
||||
label = "work";
|
||||
default-state = "on";
|
||||
gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
diy_led: led-1 {
|
||||
label = "diy";
|
||||
default-state = "off";
|
||||
gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
sound: sound {
|
||||
compatible = "audio-graph-card";
|
||||
label = "Analog";
|
||||
dais = <&i2s0_p0>;
|
||||
};
|
||||
|
||||
sound-dit {
|
||||
compatible = "audio-graph-card";
|
||||
label = "SPDIF";
|
||||
dais = <&spdif_p0>;
|
||||
};
|
||||
|
||||
spdif-dit {
|
||||
compatible = "linux,spdif-dit";
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
port {
|
||||
dit_p0_0: endpoint {
|
||||
remote-endpoint = <&spdif_p0_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
clocks = <&rk808 1>;
|
||||
clock-names = "ext_clock";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_enable_h>;
|
||||
|
||||
/*
|
||||
* On the module itself this is one of these (depending
|
||||
* on the actual card populated):
|
||||
* - SDIO_RESET_L_WL_REG_ON
|
||||
* - PDN (power down when low)
|
||||
*/
|
||||
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
sound-dit {
|
||||
compatible = "audio-graph-card";
|
||||
label = "SPDIF";
|
||||
dais = <&spdif_p0>;
|
||||
};
|
||||
|
||||
spdif-dit {
|
||||
compatible = "linux,spdif-dit";
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
port {
|
||||
dit_p0_0: endpoint {
|
||||
remote-endpoint = <&spdif_p0_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* switched by pmic_sleep */
|
||||
vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc1v8_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc_1v8>;
|
||||
};
|
||||
|
||||
vcc1v8_sys: vcc1v8-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc1v8_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie: vcc3v3-pcie-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_pwr_en>;
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc3v3_3g: vcc3v3-3g-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_3g_drv>;
|
||||
regulator-name = "vcc3v3_3g";
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
/* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */
|
||||
vcc5v0_host: vcc5v0-host-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_host_en &vcc5v0_host3_en>;
|
||||
regulator-name = "vcc5v0_host";
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
vcc5v0_hub: vcc5v0-hub-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_hub_en>;
|
||||
regulator-name = "vcc5v0_host";
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
vcc_sys: vcc-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vdd_log: vdd-log {
|
||||
compatible = "pwm-regulator";
|
||||
pwms = <&pwm2 0 25000 1>;
|
||||
regulator-name = "vdd_log";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
vin-supply = <&vcc_sys>;
|
||||
};
|
||||
|
||||
vcc_phy: vcc-phy-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_phy";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu_l0 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l1 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l2 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l3 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_b0 {
|
||||
cpu-supply = <&vdd_cpu_b>;
|
||||
};
|
||||
|
||||
&cpu_b1 {
|
||||
cpu-supply = <&vdd_cpu_b>;
|
||||
};
|
||||
|
||||
&emmc_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac {
|
||||
assigned-clocks = <&cru SCLK_RMII_SRC>;
|
||||
assigned-clock-parents = <&clkin_gmac>;
|
||||
clock_in_out = "input";
|
||||
phy-supply = <&vcc_lan>;
|
||||
phy-mode = "rgmii";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins>;
|
||||
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 10000 50000>;
|
||||
tx_delay = <0x28>;
|
||||
rx_delay = <0x11>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&i2c3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_cec>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <400000>;
|
||||
i2c-scl-rising-time-ns = <168>;
|
||||
i2c-scl-falling-time-ns = <4>;
|
||||
status = "okay";
|
||||
|
||||
rk808: pmic@1b {
|
||||
compatible = "rockchip,rk808";
|
||||
reg = <0x1b>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "xin32k", "rk808-clkout2";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int_l>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
vcc10-supply = <&vcc3v3_sys>;
|
||||
vcc11-supply = <&vcc3v3_sys>;
|
||||
vcc12-supply = <&vcc3v3_sys>;
|
||||
vddio-supply = <&vcc1v8_pmu>;
|
||||
|
||||
regulators {
|
||||
vdd_center: DCDC_REG1 {
|
||||
regulator-name = "vdd_center";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_l: DCDC_REG2 {
|
||||
regulator-name = "vdd_cpu_l";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG4 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc2v8_dvp: LDO_REG1 {
|
||||
regulator-name = "vcc2v8_dvp";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
vcc1v8_dvp: LDO_REG2 {
|
||||
regulator-name = "vcc1v8_dvp";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc1v8_pmu: LDO_REG3 {
|
||||
regulator-name = "vcc1v8_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sdio: LDO_REG4 {
|
||||
regulator-name = "vcc_sdio";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca3v0_codec: LDO_REG5 {
|
||||
regulator-name = "vcca3v0_codec";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v5: LDO_REG6 {
|
||||
regulator-name = "vcc_1v5";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1500000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_codec: LDO_REG7 {
|
||||
regulator-name = "vcca1v8_codec";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v0: LDO_REG8 {
|
||||
regulator-name = "vcc_3v0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_s3: vcc_lan: SWITCH_REG1 {
|
||||
regulator-name = "vcc3v3_s3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_s0: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_s0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_b: regulator@40 {
|
||||
compatible = "silergy,syr827";
|
||||
reg = <0x40>;
|
||||
fcs,suspend-voltage-selector = <0>;
|
||||
regulator-name = "vdd_cpu_b";
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-ramp-delay = <1000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vcc_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: regulator@41 {
|
||||
compatible = "silergy,syr828";
|
||||
reg = <0x41>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-ramp-delay = <1000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vcc_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
i2c-scl-rising-time-ns = <300>;
|
||||
i2c-scl-falling-time-ns = <15>;
|
||||
status = "okay";
|
||||
|
||||
es8316: codec@11 {
|
||||
compatible = "everest,es8316";
|
||||
reg = <0x11>;
|
||||
clocks = <&cru SCLK_I2S_8CH_OUT>;
|
||||
clock-names = "mclk";
|
||||
#sound-dai-cells = <0>;
|
||||
pinctrl-0 = <&i2s_8ch_mclk>;
|
||||
spk-con-gpio = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
hp-det-gpio = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
port {
|
||||
es8316_p0_0: endpoint {
|
||||
remote-endpoint = <&i2s0_p0_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2s0 {
|
||||
rockchip,playback-channels = <8>;
|
||||
rockchip,capture-channels = <8>;
|
||||
status = "okay";
|
||||
|
||||
i2s0_p0: port {
|
||||
i2s0_p0_0: endpoint {
|
||||
dai-format = "i2s";
|
||||
mclk-fs = <256>;
|
||||
remote-endpoint = <&es8316_p0_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2s1 {
|
||||
rockchip,playback-channels = <2>;
|
||||
rockchip,capture-channels = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2s2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&io_domains {
|
||||
status = "okay";
|
||||
|
||||
bt656-supply = <&vcc1v8_dvp>;
|
||||
audio-supply = <&vcca1v8_codec>;
|
||||
sdmmc-supply = <&vcc_sdio>;
|
||||
gpio1830-supply = <&vcc_3v0>;
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
|
||||
max-link-speed = <1>;
|
||||
num-lanes = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_clkreqn_cpm>;
|
||||
status = "okay";
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
|
||||
pcie@0 {
|
||||
reg = <0x00000000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pcie-eth@0,0 {
|
||||
compatible = "realtek,r8168";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
realtek,led-data = <0x87>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmu1830-supply = <&vcc_3v0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
i2s0 {
|
||||
i2s_8ch_mclk: i2s-8ch-mclk {
|
||||
rockchip,pins = <4 RK_PB4 1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
work_led_pin: work-led-pin {
|
||||
rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
diy_led_pin: diy-led-pin {
|
||||
rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie {
|
||||
pcie_pwr_en: pcie-pwr-en {
|
||||
rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
pcie_3g_drv: pcie-3g-drv {
|
||||
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int_l: pmic-int-l {
|
||||
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
vsel1_pin: vsel1-pin {
|
||||
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
|
||||
vsel2_pin: vsel2-pin {
|
||||
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio-pwrseq {
|
||||
wifi_enable_h: wifi-enable-h {
|
||||
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb2 {
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
vcc5v0_host3_en: vcc5v0-host3-en {
|
||||
rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
vcc5v0_hub_en: vcc5v0-hub-en {
|
||||
rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca1v8_s3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdio0 {
|
||||
bus-width = <4>;
|
||||
cap-sdio-irq;
|
||||
cap-sd-highspeed;
|
||||
keep-power-in-suspend;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
|
||||
sd-uhs-sdr104;
|
||||
|
||||
/* Power supply */
|
||||
vqmmc-supply = <&vcc1v8_s3>; /* IO line */
|
||||
vmmc-supply = <&vcc_sdio>; /* card's power */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
disable-wp;
|
||||
cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
|
||||
max-frequency = <150000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spdif {
|
||||
pinctrl-0 = <&spdif_bus_1>;
|
||||
status = "okay";
|
||||
|
||||
spdif_p0: port {
|
||||
spdif_p0_0: endpoint {
|
||||
remote-endpoint = <&dit_p0_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&tcphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tcphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
/* tshut mode 0:CRU 1:GPIO */
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
/* tshut polarity 0:LOW 1:HIGH */
|
||||
rockchip,hw-tshut-polarity = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_xfer &uart0_cts>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&usbdrd3_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&vopb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,687 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "rk3399.dtsi"
|
||||
#include "rk3399-opp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Rocktech MPC1903";
|
||||
compatible = "rocktech,mpc1903", "rockchip,rk3399";
|
||||
|
||||
aliases {
|
||||
mmc0 = &sdmmc;
|
||||
mmc1 = &sdhci;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
clkin_gmac: external-gmac-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "clkin_gmac";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
clocks = <&rk808 1>;
|
||||
clock-names = "ext_clock";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_enable_h>;
|
||||
reset-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
vcc12v_dcin: dc-12v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc12v_dcin";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc5v0_host: vcc5v0-host {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_host_en>;
|
||||
regulator-name = "vcc5v0_host";
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc5v0_hub: vcc5v0-hub {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_hub_en>;
|
||||
regulator-name = "vcc5v0_hub";
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc3v3_gsm: vcc3v3-gsm {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc3v3_gsm_en>;
|
||||
regulator-name = "vcc3v3_gsm";
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
vcc_lan: vcc-phy {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_lan";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vdd_log: vdd-log {
|
||||
compatible = "pwm-regulator";
|
||||
pwms = <&pwm2 0 25000 1>;
|
||||
regulator-name = "vdd_log";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&status_led_pin>;
|
||||
|
||||
status_led: status-led {
|
||||
label = "status_led";
|
||||
linux,default-trigger = "heartbeat";
|
||||
gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu_l0 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l1 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l2 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_l3 {
|
||||
cpu-supply = <&vdd_cpu_l>;
|
||||
};
|
||||
|
||||
&cpu_b0 {
|
||||
cpu-supply = <&vdd_cpu_b>;
|
||||
};
|
||||
|
||||
&cpu_b1 {
|
||||
cpu-supply = <&vdd_cpu_b>;
|
||||
};
|
||||
|
||||
&emmc_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac {
|
||||
assigned-clocks = <&cru SCLK_RMII_SRC>;
|
||||
assigned-clock-parents = <&clkin_gmac>;
|
||||
clock_in_out = "input";
|
||||
phy-supply = <&vcc_lan>;
|
||||
phy-mode = "rgmii";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins>;
|
||||
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 10000 50000>;
|
||||
tx_delay = <0x28>;
|
||||
rx_delay = <0x11>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&i2c3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_i2c_xfer>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <400000>;
|
||||
i2c-scl-rising-time-ns = <168>;
|
||||
i2c-scl-falling-time-ns = <4>;
|
||||
status = "okay";
|
||||
|
||||
rk808: pmic@1b {
|
||||
compatible = "rockchip,rk808";
|
||||
reg = <0x1b>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "xin32k", "rk808-clkout2";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int_l>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc5v0_sys>;
|
||||
vcc2-supply = <&vcc5v0_sys>;
|
||||
vcc3-supply = <&vcc5v0_sys>;
|
||||
vcc4-supply = <&vcc5v0_sys>;
|
||||
vcc6-supply = <&vcc5v0_sys>;
|
||||
vcc7-supply = <&vcc5v0_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc5v0_sys>;
|
||||
vcc10-supply = <&vcc5v0_sys>;
|
||||
vcc11-supply = <&vcc5v0_sys>;
|
||||
vcc12-supply = <&vcc3v3_sys>;
|
||||
vddio-supply = <&vcc_3v0>;
|
||||
|
||||
regulators {
|
||||
vdd_center: DCDC_REG1 {
|
||||
regulator-name = "vdd_center";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_l: DCDC_REG2 {
|
||||
regulator-name = "vdd_cpu_l";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG4 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
gen_1v8: LDO_REG1 {
|
||||
regulator-name = "gen_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
gen_3v0: LDO_REG2 {
|
||||
regulator-name = "gen_3v0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc1v8_pmu: LDO_REG3 {
|
||||
regulator-name = "vcc1v8_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sdio: LDO_REG4 {
|
||||
regulator-name = "vcc_sdio";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca3v0_codec: LDO_REG5 {
|
||||
regulator-name = "vcca3v0_codec";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v5: LDO_REG6 {
|
||||
regulator-name = "vcc_1v5";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc1v8_codec: LDO_REG7 {
|
||||
regulator-name = "vcc1v8_codec";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v0: LDO_REG8 {
|
||||
regulator-name = "vcc_3v0";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3000000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_s3: SWITCH_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc3v3_s3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_s0: SWITCH_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc3v3_s0";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vdd_cpu_b: regulator@40 {
|
||||
compatible = "silergy,syr827";
|
||||
reg = <0x40>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vsel1_pin>;
|
||||
regulator-name = "vdd_cpu_b";
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-ramp-delay = <1000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: regulator@41 {
|
||||
compatible = "silergy,syr828";
|
||||
reg = <0x41>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vsel2_pin>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-ramp-delay = <1000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rtc: pcf85263@51 {
|
||||
compatible = "nxp,pcf85263";
|
||||
reg = <0x51>;
|
||||
pinctrl-0 = <&rtc_int>;
|
||||
rtc_int_gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
i2c-scl-rising-time-ns = <300>;
|
||||
i2c-scl-falling-time-ns = <15>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
clock-frequency = <400000>;
|
||||
i2c-scl-rising-time-ns = <450>;
|
||||
i2c-scl-falling-time-ns = <15>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2s0 {
|
||||
rockchip,i2s-broken-burst-len;
|
||||
rockchip,playback-channels = <8>;
|
||||
rockchip,capture-channels = <8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2s2 {
|
||||
rockchip,bclk-fs = <128>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&io_domains {
|
||||
status = "okay";
|
||||
|
||||
bt656-supply = <&vcc_3v0>;
|
||||
audio-supply = <&vcc1v8_codec>;
|
||||
sdmmc-supply = <&vcc_sdio>;
|
||||
gpio1830-supply = <&vcc_3v0>;
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
status = "okay";
|
||||
|
||||
pmu1830-supply = <&vcc_3v0>;
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
bt {
|
||||
bt_enable_h: bt-enable-h {
|
||||
rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int_l: pmic-int-l {
|
||||
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
vsel1_pin: vsel1-pin {
|
||||
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
|
||||
vsel2_pin: vsel2-pin {
|
||||
rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
};
|
||||
};
|
||||
|
||||
usb2 {
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_hub_en: vcc5v0-hub-en {
|
||||
rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
vcc3v3_gsm_en: vcc3v3-gsm-en {
|
||||
rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
wifi {
|
||||
wifi_enable_h: wifi-enable-h {
|
||||
rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
rtc {
|
||||
rtc_int: rtc-int {
|
||||
rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
led {
|
||||
status_led_pin: status-led-pin {
|
||||
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
rockchip-key {
|
||||
power_key: power-key {
|
||||
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
status = "okay";
|
||||
|
||||
vref-supply = <&vcc_1v8>;
|
||||
};
|
||||
|
||||
&sdio0 {
|
||||
bus-width = <4>;
|
||||
clock-frequency = <50000000>;
|
||||
cap-sdio-irq;
|
||||
cap-sd-highspeed;
|
||||
keep-power-in-suspend;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
|
||||
sd-uhs-sdr104;
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
max-frequency = <150000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
mmc-hs400-1_8v;
|
||||
mmc-hs400-enhanced-strobe;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tcphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tcphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
status = "okay";
|
||||
rockchip,hw-tshut-temp = <120000>;
|
||||
/* tshut mode 0:CRU 1:GPIO */
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
/* tshut polarity 0:LOW 1:HIGH */
|
||||
rockchip,hw-tshut-polarity = <1>;
|
||||
};
|
||||
|
||||
&u2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy0_host {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy1_host {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&usbdrd3_1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&vopb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopb_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vopl_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3399-nanopi-r4s.dts"
|
||||
|
||||
/ {
|
||||
model = "FriendlyElec NanoPi R4SE";
|
||||
compatible = "friendlyarm,nanopi-r4se", "rockchip,rk3399";
|
||||
};
|
||||
|
||||
|
||||
&emmc_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -1,526 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
led-boot = &led_work;
|
||||
led-failsafe = &led_work;
|
||||
led-running = &led_work;
|
||||
led-upgrade = &led_work;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
vcc12v_dcin: vcc12v-dcin {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-name = "vcc12v_dcin";
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_sys";
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_sys";
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_usb: vcc5v0-usb {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_usb";
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg: vcc5v0-usb-otg {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_otg_en>;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_usb_otg";
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie: vcc3v3-pcie {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&reset_button_pin>;
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
debounce-interval = <50>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_work_en>;
|
||||
|
||||
led_work: led-0 {
|
||||
label = "blue:work-led";
|
||||
gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&display_subsystem {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1390000>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-name = "vcc_ddr";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-name = "vdda0v9_image";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda_0v9";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_acodec";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-init-microvolt = <950000>;
|
||||
regulator-name = "vcca1v8_image";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <950000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc_3v3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc3v3_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
data-lanes = <1 2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x1 {
|
||||
num-lanes = <1>;
|
||||
reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0,0 {
|
||||
reg = <0x00100000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
rtl8125_1: pcie-eth@10,0 {
|
||||
compatible = "pci10ec,8125";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
|
||||
realtek,led-data = <0x238>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
num-lanes = <1>;
|
||||
reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0,0 {
|
||||
reg = <0x00200000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
rtl8125_2: pcie-eth@20,0 {
|
||||
compatible = "pci10ec,8125";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
|
||||
realtek,led-data = <0x238>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
led_work_en: led_work_en {
|
||||
rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
rockchip-key {
|
||||
reset_button_pin: reset-button-pin {
|
||||
rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc3v3_pmu>;
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
phy-supply = <&vcc5v0_usb_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
|
@ -1,660 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
// Copyright (c) 2022 AmadeusGhost <amadeus@jmu.edu.cn>
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
mmc0 = &sdmmc0;
|
||||
mmc1 = &sdhci;
|
||||
|
||||
led-boot = &led_work;
|
||||
led-failsafe = &led_work;
|
||||
led-running = &led_work;
|
||||
led-upgrade = &led_work;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
hdmi-con {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&reset_button_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
debounce-interval = <50>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_net_en>, <&led_sata_en>, <&led_work_en>;
|
||||
|
||||
net {
|
||||
label = "blue:net";
|
||||
gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
sata {
|
||||
label = "amber:sata";
|
||||
gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led_work: work {
|
||||
label = "green:work";
|
||||
gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc12v_dcin: vcc12v-dcin {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-name = "vcc12v_dcin";
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_sys";
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_sys";
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_usb: vcc5v0-usb {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_usb";
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_host: vcc5v0-usb-host {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_host_en>;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_usb_host";
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie: vcc3v3-pcie {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
startup-delay-us = <5000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
rk809-sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,name = "Analog RK809";
|
||||
simple-audio-card,mclk-fs = <256>;
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&i2s1_8ch>;
|
||||
};
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&rk809>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
avdd-0v9-supply = <&vdda0v9_image>;
|
||||
avdd-1v8-supply = <&vcca1v8_image>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_in {
|
||||
hdmi_in_vp0: endpoint {
|
||||
remote-endpoint = <&vp0_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_out {
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1390000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
|
||||
#clock-cells = <1>;
|
||||
clock-names = "mclk";
|
||||
clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
|
||||
rockchip,system-power-controller;
|
||||
#sound-dai-cells = <0>;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-name = "vcc_ddr";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-name = "vdda0v9_image";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda_0v9";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_acodec";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca1v8_image";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
codec {
|
||||
mic-in-differential;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&i2s0_8ch {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2s1_8ch {
|
||||
rockchip,trcm-sync-tx-only;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie2x1 {
|
||||
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
data-lanes = <1 2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x1 {
|
||||
num-lanes = <1>;
|
||||
reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0,0 {
|
||||
reg = <0x00100000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
rtl8125_1: pcie-eth@10,0 {
|
||||
compatible = "pci10ec,8125";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
num-lanes = <1>;
|
||||
reset-gpios = <&gpio2 RK_PD0 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0,0 {
|
||||
reg = <0x00200000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
rtl8125_2: pcie-eth@20,0 {
|
||||
compatible = "pci10ec,8125";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
button {
|
||||
reset_button_pin: reset-button-pin {
|
||||
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
led_net_en: led_net_en {
|
||||
rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
led_sata_en: led_sata_en {
|
||||
rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
led_work_en: led_work_en {
|
||||
rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb_host_en: vcc5v0_usb_host_en {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc3v3_pmu>;
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio2-supply = <&vcc_1v8>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi_in_vp0>;
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
|
@ -1,119 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
// Copyright (c) 2023 mleaf <mleaf90@gmail.com>
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3568-mrkaio-m68s.dtsi"
|
||||
|
||||
/ {
|
||||
model = "EZPRO Mrkaio M68S PLUS";
|
||||
compatible = "ezpro,mrkaio-m68s-plus", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
led-boot = &led_sys;
|
||||
led-failsafe = &led_sys;
|
||||
led-running = &led_sys;
|
||||
led-upgrade = &led_sys;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_sys_en>;
|
||||
|
||||
led_sys: sys {
|
||||
label = "red:sys";
|
||||
gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
switch_otg: switch-otg {
|
||||
compatible = "regulator-fixed";
|
||||
gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb_otg_switch_en>;
|
||||
regulator-name = "switch_otg";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc3v3_pcie: vcc3v3-pcie {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
startup-delay-us = <5000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie2x1 {
|
||||
num-viewport = <4>;
|
||||
reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0,0 {
|
||||
reg = <0x00000000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
r8125_1: pcie@01,0 {
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
data-lanes = <1 2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x1 {
|
||||
num-viewport = <4>;
|
||||
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0,0 {
|
||||
reg = <0x00100000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
r8125_2: pcie@10,0 {
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
num-lanes = <1>;
|
||||
max-link-speed = <2>;
|
||||
num-ib-windows = <8>;
|
||||
num-ob-windows = <8>;
|
||||
num-viewport = <4>;
|
||||
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
led_sys_en: led_sys_en {
|
||||
rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb_host_en: vcc5v0_usb_host_en {
|
||||
rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
|
||||
rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
usb_otg_switch_en: usb-otg-switch_en {
|
||||
rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,154 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
// Copyright (c) 2022 AmadeusGhost <amadeus@jmu.edu.cn>
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3568-mrkaio-m68s.dtsi"
|
||||
|
||||
/ {
|
||||
model = "EZPRO Mrkaio M68S";
|
||||
compatible = "ezpro,mrkaio-m68s", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
ethernet1 = &gmac1;
|
||||
|
||||
led-boot = &led_sys;
|
||||
led-failsafe = &led_sys;
|
||||
led-running = &led_sys;
|
||||
led-upgrade = &led_sys;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_sata_en>, <&led_sys_en>;
|
||||
|
||||
sata {
|
||||
label = "blue:sata";
|
||||
gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led_sys: sys {
|
||||
label = "red:sys";
|
||||
gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
switch_otg: switch-otg {
|
||||
compatible = "regulator-fixed";
|
||||
gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb_otg_switch_en>;
|
||||
regulator-name = "switch_otg";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcc5v0_ahci: vcc5v0-ahci {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sata_pwr_en>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_ahci";
|
||||
};
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
&gmac0_rgmii_clk
|
||||
&gmac0_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x3c>;
|
||||
rx_delay = <0x2f>;
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
&gmac1m1_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x42>;
|
||||
rx_delay = <0x28>;
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
led_sata_en: led_sata_en {
|
||||
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
led_sys_en: led_sys_en {
|
||||
rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sata {
|
||||
sata_pwr_en: sata-pwr-en {
|
||||
rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb_host_en: vcc5v0_usb_host_en {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
usb_otg_switch_en: usb-otg-switch_en {
|
||||
rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sata2 {
|
||||
target-supply = <&vcc5v0_ahci>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -1,523 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
mmc0 = &sdmmc0;
|
||||
mmc1 = &sdhci;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
hdmi-con {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
dc_12v: dc-12v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-name = "dc_12v";
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_sys";
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-name = "vcc5v0_sys";
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_host: vcc5v0-usb-host {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_host_en>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc5v0_usb_host";
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg: vcc5v0-usb-otg {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_otg_en>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc5v0_usb_otg";
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
avdd-0v9-supply = <&vdda0v9_image>;
|
||||
avdd-1v8-supply = <&vcca1v8_image>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_in {
|
||||
hdmi_in_vp0: endpoint {
|
||||
remote-endpoint = <&vp0_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_out {
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1390000>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-name = "vcc_ddr";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcc_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda0v9_image";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda_0v9";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_acodec";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vccio_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca_1v8";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-name = "vcca1v8_image";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc_3v3";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc3v3_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&i2s0_8ch {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&pinctrl {
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc3v3_pmu>;
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio2-supply = <&vcc_1v8>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
phy-supply = <&vcc5v0_usb_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi_in_vp0>;
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
|
@ -1,681 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
|
||||
* (http://www.friendlyarm.com)
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
model = "FriendlyElec NanoPi R5C";
|
||||
compatible = "friendlyarm,nanopi-r5c","rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &rtl8125_1;
|
||||
ethernet1 = &rtl8125_2;
|
||||
mmc0 = &sdmmc0;
|
||||
mmc1 = &sdhci;
|
||||
|
||||
led-boot = &sys_led;
|
||||
led-failsafe = &sys_led;
|
||||
led-running = &sys_led;
|
||||
led-upgrade = &sys_led;
|
||||
};
|
||||
|
||||
chosen: chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
hdmi-con {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&sys_led_pin>, <&lan_led_pin>,
|
||||
<&wan_led_pin>, <&wlan_led_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
sys_led: led-0 {
|
||||
gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||
label = "red:power";
|
||||
};
|
||||
|
||||
wan_led: led-1 {
|
||||
gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:wan";
|
||||
};
|
||||
|
||||
lan_led: led-2 {
|
||||
gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:lan";
|
||||
};
|
||||
|
||||
wlan_led: led-3 {
|
||||
gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:wlan";
|
||||
};
|
||||
};
|
||||
|
||||
vdd_5v: vdd-5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_5v";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vdd_5v>;
|
||||
};
|
||||
|
||||
vcc3v3_sysp: vcc3v3-sysp {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sysp";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vdd_5v>;
|
||||
};
|
||||
|
||||
vcc5v0_sysp: vcc5v0-sysp {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sysp";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc3v3_sysp>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_host: vcc5v0-usb-host {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_host_en>;
|
||||
regulator-name = "vcc5v0_usb_host";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_sysp>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg: vcc5v0-usb-otg {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_otg_en>;
|
||||
regulator-name = "vcc5v0_usb_otg";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_sysp>;
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
avdd-0v9-supply = <&vdda0v9_image>;
|
||||
avdd-1v8-supply = <&vcca1v8_image>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_in {
|
||||
hdmi_in_vp0: endpoint {
|
||||
remote-endpoint = <&vp0_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_out {
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
i2c-scl-rising-time-ns = <160>;
|
||||
i2c-scl-falling-time-ns = <30>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1390000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-name = "vdda0v9_image";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-name = "vdda_0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-name = "vccio_acodec";
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-name = "vcca_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-name = "vcca1v8_image";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_sd";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
i2c-scl-rising-time-ns = <160>;
|
||||
i2c-scl-falling-time-ns = <30>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
hym8563: hym8563@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "xin32k";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hym8563_int>;
|
||||
};
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&i2s0_8ch {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&pcie2x1 {
|
||||
num-lanes = <1>;
|
||||
num-viewport = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&m2_w_disable_pin>;
|
||||
reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
data-lanes = <1 2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x1 {
|
||||
num-lanes = <1>;
|
||||
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
pcie@10 {
|
||||
reg = <0x00100000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
rtl8125_1: pcie-eth@10,0 {
|
||||
compatible = "pci10ec,8125";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
|
||||
realtek,led-data = <0x78>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
num-lanes = <1>;
|
||||
reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
pcie@20 {
|
||||
reg = <0x00200000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
rtl8125_2: pcie-eth@20,0 {
|
||||
compatible = "pci10ec,8125";
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
|
||||
realtek,led-data = <0x78>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
sys_led_pin: sys-led-pin {
|
||||
rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
lan_led_pin: lan-led-pin {
|
||||
rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
wan_led_pin: wan-led-pin {
|
||||
rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
wlan_led_pin: wlan-led-pin {
|
||||
rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
hym8563 {
|
||||
hym8563_int: hym8563-int {
|
||||
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
m2-pins {
|
||||
m2_w_disable_pin: m2-w-disable-pin {
|
||||
rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb_host_en: vcc5v0_usb_host_en {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
phy-supply = <&vcc5v0_usb_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi_in_vp0>;
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
|
@ -1,710 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
|
||||
* (http://www.friendlyarm.com)
|
||||
*
|
||||
* Copyright (c) 2022 Marty Jones <mj8263788@gmail.com>
|
||||
* Copyright (c) 2022 Tianling Shen <cnsztl@gmail.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
model = "FriendlyElec NanoPi R5S";
|
||||
compatible = "friendlyarm,nanopi-r5s","rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
mmc0 = &sdmmc0;
|
||||
mmc1 = &sdhci;
|
||||
|
||||
led-boot = &sys_led;
|
||||
led-failsafe = &sys_led;
|
||||
led-running = &sys_led;
|
||||
led-upgrade = &sys_led;
|
||||
};
|
||||
|
||||
chosen: chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
hdmi-con {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>,
|
||||
<&sys_led_pin>, <&wan_led_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
lan1_led: led-0 {
|
||||
gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:lan1";
|
||||
};
|
||||
|
||||
lan2_led: led-1 {
|
||||
gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:lan2";
|
||||
};
|
||||
|
||||
sys_led: led-2 {
|
||||
gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
label = "red:power";
|
||||
};
|
||||
|
||||
wan_led: led-3 {
|
||||
gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
label = "green:wan";
|
||||
};
|
||||
};
|
||||
|
||||
vdd_5v: vdd-5v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_5v";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vdd_5v>;
|
||||
};
|
||||
|
||||
vcc3v3_sysp: vcc3v3-sysp {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sysp";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vdd_5v>;
|
||||
};
|
||||
|
||||
vcc5v0_sysp: vcc5v0-sysp {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sysp";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc3v3_sysp>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_host: vcc5v0-usb-host {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_host_en>;
|
||||
regulator-name = "vcc5v0_usb_host";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_sysp>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie: vcc3v3-pcie {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
startup-delay-us = <5000>;
|
||||
vin-supply = <&vcc3v3_sysp>;
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
clock_in_out = "output";
|
||||
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
&gmac0_rgmii_clk
|
||||
&gmac0_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 15ms, 50ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 15000 50000>;
|
||||
tx_delay = <0x3c>;
|
||||
rx_delay = <0x2f>;
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
avdd-0v9-supply = <&vdda0v9_image>;
|
||||
avdd-1v8-supply = <&vcca1v8_image>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_in {
|
||||
hdmi_in_vp0: endpoint {
|
||||
remote-endpoint = <&vp0_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_out {
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
i2c-scl-rising-time-ns = <160>;
|
||||
i2c-scl-falling-time-ns = <30>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1390000>;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-name = "vdda0v9_image";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-name = "vdda_0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-name = "vccio_acodec";
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-name = "vcca_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-name = "vcca1v8_image";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_sd";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
i2c-scl-rising-time-ns = <160>;
|
||||
i2c-scl-falling-time-ns = <30>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
hym8563: hym8563@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
clock-output-names = "xin32k";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hym8563_int>;
|
||||
};
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&i2s0_8ch {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy0: phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x1>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac_int>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie2x1 {
|
||||
num-lanes = <1>;
|
||||
num-viewport = <4>;
|
||||
reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
pcie@00 {
|
||||
reg = <0x00000000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
r8125_1: pcie@01,0 {
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
data-lanes = <1 2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x1 {
|
||||
num-lanes = <1>;
|
||||
num-viewport = <4>;
|
||||
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
pcie@10 {
|
||||
reg = <0x00100000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
r8125_2: pcie@10,0 {
|
||||
reg = <0x000000 0 0 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
num-lanes = <1>;
|
||||
max-link-speed = <2>;
|
||||
num-ib-windows = <8>;
|
||||
num-ob-windows = <8>;
|
||||
num-viewport = <4>;
|
||||
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
lan1_led_pin: lan1-led-pin {
|
||||
rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
lan2_led_pin: lan2-led-pin {
|
||||
rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sys_led_pin: sys-led-pin {
|
||||
rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
wan_led_pin: wan-led-pin {
|
||||
rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
eth_phy {
|
||||
gmac_int: gmac-int {
|
||||
rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
hym8563 {
|
||||
hym8563_int: hym8563-int {
|
||||
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb_host_en: vcc5v0_usb_host_en {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_host {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi_in_vp0>;
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
|
@ -1,20 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
// Copyright (c) 2022 AmadeusGhost <amadeus@jmu.edu.cn>
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3568-hinlink-opc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "HINLINK OPC-H66K Board";
|
||||
compatible = "hinlink,opc-h66k", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &rtl8125_1;
|
||||
ethernet1 = &rtl8125_2;
|
||||
};
|
||||
};
|
||||
|
||||
&vcc3v3_pcie {
|
||||
gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
|
@ -1,76 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
// Copyright (c) 2022 AmadeusGhost <amadeus@jmu.edu.cn>
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3568-hinlink-opc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "HINLINK OPC-H68K Board";
|
||||
compatible = "hinlink,opc-h68k", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
ethernet1 = &gmac1;
|
||||
};
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
&gmac0_rgmii_clk
|
||||
&gmac0_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x3c>;
|
||||
rx_delay = <0x2f>;
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
&gmac1m1_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x4f>;
|
||||
rx_delay = <0x26>;
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&vcc3v3_pcie {
|
||||
gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
|
@ -1,89 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
// Copyright (c) 2023 AmadeusGhost <amadeus@jmu.edu.cn>
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3568-hinlink-opc.dtsi"
|
||||
|
||||
/ {
|
||||
model = "HINLINK OPC-H69K Board";
|
||||
compatible = "hinlink,opc-h69k", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
ethernet1 = &gmac1;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0_opp_table {
|
||||
/delete-node/ opp-1608000000;
|
||||
/delete-node/ opp-1800000000;
|
||||
/delete-node/ opp-1992000000;
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&gpu_opp_table {
|
||||
/delete-node/ opp-700000000;
|
||||
/delete-node/ opp-800000000;
|
||||
};
|
||||
#endif
|
||||
|
||||
&gmac0 {
|
||||
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
&gmac0_rgmii_clk
|
||||
&gmac0_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x3c>;
|
||||
rx_delay = <0x2f>;
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
&gmac1m1_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x4f>;
|
||||
rx_delay = <0x26>;
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&vcc3v3_pcie {
|
||||
gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
|
@ -1,592 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Ariaboard Photonicat";
|
||||
compatible = "ariaboard,photonicat", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
ethernet1 = &gmac1;
|
||||
mmc0 = &sdhci;
|
||||
mmc1 = &sdmmc0;
|
||||
mmc2 = &sdmmc1;
|
||||
};
|
||||
|
||||
chosen: chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
gmac0_xpcsclk: xpcs-gmac0-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "clk_gmac0_xpcs_mii";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
hdmi-con {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
modem-rfkill {
|
||||
compatible = "rfkill-gpio";
|
||||
name = "modem-rfkill";
|
||||
type = "wwan";
|
||||
reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
|
||||
shutdown-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
clocks = <&pmucru CLK_RTC_32K>;
|
||||
clock-names = "ext_clock";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_enable_h &clk32k_out1>;
|
||||
reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
vcc_1v8: vcc-1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
vcc_3v3: vcc-3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
vcc_sysin: vcc-sysin {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_sysin";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
vcc_syson: vcc-syson {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_syson";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc_sysin>;
|
||||
};
|
||||
|
||||
vdda_0v9: vdda-0v9 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdda_0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
vcca_1v8: vcca-1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcca_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
/* pi6c pcie clock generator */
|
||||
vcc3v3_pi6c: vcc3v3-pi6c {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_enable_h>;
|
||||
regulator-name = "vcc3v3_pi6c";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc_syson>;
|
||||
};
|
||||
|
||||
/* actually fed by vcc_syson, dependent
|
||||
* on pi6c clock generator
|
||||
*/
|
||||
vcc3v3_pcie: vcc3v3-pcie {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc3v3_pi6c>;
|
||||
};
|
||||
|
||||
vcc3v3_ngff: vcc3v3-ngff {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ngffpcie_enable_h>;
|
||||
regulator-name = "vcc3v3_ngff";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
vcc3v3_sd: vcc3v3_sd {
|
||||
compatible = "regulator-fixed";
|
||||
gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc_sd_h>;
|
||||
regulator-boot-on;
|
||||
regulator-name = "vcc3v3_sd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc_3v3>;
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc_syson>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg: vcc5v0-usb-otg {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_otg_en>;
|
||||
regulator-name = "vcc5v0_usb_otg";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc_sysin>;
|
||||
};
|
||||
|
||||
vdd_gpu: vdd-gpu {
|
||||
compatible = "pwm-regulator";
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-settling-time-up-us = <250>;
|
||||
|
||||
pwms = <&pwm2 0 5000 1>;
|
||||
pwm-supply = <&vcc_syson>;
|
||||
};
|
||||
|
||||
vdd_logic: vdd-logic {
|
||||
compatible = "pwm-regulator";
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
regulator-settling-time-up-us = <250>;
|
||||
|
||||
pwms = <&pwm1 0 5000 1>;
|
||||
pwm-supply = <&vcc_syson>;
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>;
|
||||
assigned-clock-parents = <&gmac0_xpcsclk>;
|
||||
power-domains = <&power RK3568_PD_PIPE>;
|
||||
phys = <&combphy2 PHY_TYPE_SGMII>;
|
||||
phy-handle = <&sgmii_phy>;
|
||||
phy-mode = "sgmii";
|
||||
phy-supply = <&vcc_3v3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim>;
|
||||
rockchip,xpcs = <&xpcs>;
|
||||
snps,reset-gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0xff>;
|
||||
rx_delay = <0xff>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-handle = <&rgmii_phy>;
|
||||
phy-mode = "rgmii";
|
||||
phy-supply = <&vcc_3v3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
&gmac1m1_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x30>;
|
||||
rx_delay = <0x10>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
avdd-0v9-supply = <&vdda_0v9>;
|
||||
avdd-1v8-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_in {
|
||||
hdmi_in_vp0: endpoint {
|
||||
remote-endpoint = <&vp0_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_out {
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1390000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc_syson>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2m1_xfer>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&i2s0_8ch {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&mdio0 {
|
||||
sgmii_phy: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
phy-supply = <&vcc3v3_pi6c>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
bt {
|
||||
bt_enable_h: bt-enable-h {
|
||||
rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie {
|
||||
pcie_enable_h: pcie-enable-h {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio-pwrseq {
|
||||
wifi_enable_h: wifi-enable-h {
|
||||
rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
ngffpcie_enable_h: ngffpcie-enable-h {
|
||||
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_sd {
|
||||
vcc_sd_h: vcc-sd-h {
|
||||
rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc_3v3>;
|
||||
pmuio2-supply = <&vcc_3v3>;
|
||||
vccio1-supply = <&vcc_3v3>;
|
||||
vccio3-supply = <&vcc_3v3>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_3v3>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
|
||||
vmmc-supply = <&vcc_3v3>;
|
||||
vqmmc-supply = <&vcc_1v8>;
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
no-1-8-v;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc1 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
keep-power-in-suspend;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sys>;
|
||||
vqmmc-supply = <&vcc_1v8>;
|
||||
status = "okay";
|
||||
|
||||
sdio_wifi@1 {
|
||||
reg = <1>;
|
||||
interrupt-parent = <&gpio2>;
|
||||
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "host-wake";
|
||||
};
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
|
||||
status = "okay";
|
||||
uart-has-rtscts;
|
||||
|
||||
bluetooth {
|
||||
compatible = "qcom,qca9377-bt";
|
||||
enable-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
clocks = <&pmucru CLK_RTC_32K>;
|
||||
clock-names = "lpo";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&bt_enable_h>;
|
||||
vddio-supply = <&vcc_1v8>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
extcon = <&usb2phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
phy-supply = <&vcc3v3_ngff>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
phy-supply = <&vcc5v0_usb_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
phy-supply = <&vcc5v0_usb_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi_in_vp0>;
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
&xin32k {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&clk32k_out1>;
|
||||
};
|
||||
|
||||
&xpcs {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3568-fastrhino.dtsi"
|
||||
|
||||
/ {
|
||||
model = "FastRhino R66S";
|
||||
compatible = "fastrhino,r66s", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
mmc0 = &sdmmc0;
|
||||
};
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -1,83 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3568-fastrhino.dtsi"
|
||||
|
||||
/ {
|
||||
model = "FastRhino R68S";
|
||||
compatible = "fastrhino,r68s", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
ethernet1 = &gmac1;
|
||||
mmc0 = &sdhci;
|
||||
};
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
&gmac0_rgmii_clk
|
||||
&gmac0_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x3c>;
|
||||
rx_delay = <0x2f>;
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
&gmac1m1_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x4f>;
|
||||
rx_delay = <0x26>;
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -1,418 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "radxa,cm3i", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
mmc0 = &sdhci;
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led_user: led-0 {
|
||||
gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
function = LED_FUNCTION_HEARTBEAT;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_user_en>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie30_avdd0v9: pcie30-avdd0v9-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie30_avdd0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
pcie30_avdd1v8: pcie30-avdd1v8-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie30_avdd1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v_input>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v_input>;
|
||||
};
|
||||
|
||||
/* labeled +5v_input in schematic */
|
||||
vcc5v_input: vcc5v-input-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v_input";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&display_subsystem {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v_input>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
rockchip,system-power-controller;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-name = "vdda0v9_image";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-name = "vdda_0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-name = "vccio_acodec";
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-name = "vcca_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-name = "vcca1v8_image";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
led_user_en: led_user_en {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc3v3_pmu>;
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio2-supply = <&vcc_1v8>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
vmmc-supply = <&vcc_3v3>;
|
||||
vqmmc-supply = <&vcc_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
extcon = <&usb2phy0>;
|
||||
};
|
||||
|
|
@ -1,251 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
#include "rk3568-radxa-cm3i.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Radxa E25 Carrier Board";
|
||||
compatible = "radxa,e25", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
mmc1 = &sdmmc0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
adc-keys {
|
||||
compatible = "adc-keys";
|
||||
io-channels = <&saradc 0>;
|
||||
io-channel-names = "buttons";
|
||||
keyup-threshold-microvolt = <1750000>;
|
||||
|
||||
button-power {
|
||||
label = "Power";
|
||||
linux,code = <KEY_POWER>;
|
||||
press-threshold-microvolt = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm-leds {
|
||||
compatible = "pwm-leds-multicolor";
|
||||
|
||||
multi-led {
|
||||
color = <LED_COLOR_ID_RGB>;
|
||||
max-brightness = <255>;
|
||||
|
||||
led-red {
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
pwms = <&pwm1 0 1000000 0>;
|
||||
};
|
||||
|
||||
led-green {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
pwms = <&pwm2 0 1000000 0>;
|
||||
};
|
||||
|
||||
led-blue {
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
pwms = <&pwm12 0 1000000 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
vbus_typec: vbus-typec-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vbus_typec_en>;
|
||||
regulator-name = "vbus_typec";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc3v3_minipcie: vcc3v3-minipcie-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&minipcie_enable_h>;
|
||||
regulator-name = "vcc3v3_minipcie";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc3v3_ngff: vcc3v3-ngff-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ngffpcie_enable_h>;
|
||||
regulator-name = "vcc3v3_ngff";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
/* actually fed by vcc5v0_sys, dependent
|
||||
* on pi6c clock generator
|
||||
*/
|
||||
vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie30x1_enable_h>;
|
||||
regulator-name = "vcc3v3_pcie30x1";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc3v3_pi6c_05>;
|
||||
};
|
||||
|
||||
vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_enable_h>;
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie2x1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie20_reset_h>;
|
||||
reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pi6c_05>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
data-lanes = <1 2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x1 {
|
||||
num-lanes = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie30x1m0_pins>;
|
||||
reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie30x1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
num-lanes = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie30x2_reset_h>;
|
||||
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pi6c_05>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pcie {
|
||||
pcie20_reset_h: pcie20-reset-h {
|
||||
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pcie30x1_enable_h: pcie30x1-enable-h {
|
||||
rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pcie30x2_reset_h: pcie30x2-reset-h {
|
||||
rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pcie_enable_h: pcie-enable-h {
|
||||
rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
minipcie_enable_h: minipcie-enable-h {
|
||||
rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
ngffpcie_enable_h: ngffpcie-enable-h {
|
||||
rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vbus_typec_en: vbus_typec_en {
|
||||
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm12 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm12m1_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata1 {
|
||||
ahci-supply = <&vcc3v3_pi6c_05>;
|
||||
target-supply = <&vcc3v3_pcie30x1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
/* Also used in pcie30x1_clkreqnm0 */
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
phy-supply = <&vbus_typec>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_host {
|
||||
phy-supply = <&vcc3v3_minipcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
phy-supply = <&vcc3v3_ngff>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -1,796 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Firefly Station P2";
|
||||
compatible = "firefly,rk3568-roc-pc", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac0;
|
||||
ethernet1 = &gmac1;
|
||||
mmc0 = &sdmmc0;
|
||||
mmc1 = &sdhci;
|
||||
};
|
||||
|
||||
chosen: chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
hdmi-con {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_work_en>, <&led_user_en>;
|
||||
|
||||
led-work {
|
||||
label = "blue:work";
|
||||
gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
led-user {
|
||||
label = "yellow:user";
|
||||
gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
rk809-sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,name = "Analog RK809";
|
||||
simple-audio-card,mclk-fs = <256>;
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&i2s1_8ch>;
|
||||
};
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&rk809>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio_pwrseq: sdio-pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
clocks = <&rk809 1>;
|
||||
clock-names = "ext_clock";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_enable_h>;
|
||||
reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>;
|
||||
post-power-on-delay-ms = <100>;
|
||||
};
|
||||
|
||||
dc_12v: dc-12v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "dc_12v";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
vcc5v0_usb: vcc5v0-usb {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_usb";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&dc_12v>;
|
||||
};
|
||||
|
||||
pcie30_avdd0v9: pcie30-avdd0v9 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie30_avdd0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
pcie30_avdd1v8: pcie30-avdd1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie30_avdd1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
pcie_pi6c_oe: pcie-pi6c-oe {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie_pi6c_oe_en";
|
||||
regulator-always-on;
|
||||
gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_pi6c_oe_en>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie: vcc3v3_pi6c: vcc3v3-pcie {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-always-on;
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_enable_h>;
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc5v0_host: vcc5v0-host {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_host";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_host_en>;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
vcc5v0_otg: vcc5v0-otg {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_otg";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_otg_en>;
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
vcc_hub_reset: vcc-hub-reset {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc_hub_reset";
|
||||
regulator-always-on;
|
||||
enable-active-high;
|
||||
gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc_hub_reset_en>;
|
||||
};
|
||||
|
||||
vcc3v3_lcd0_n: vcc3v3-lcd0-n {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_lcd0_n";
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_lcd1_n: vcc3v3-lcd1-n {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_lcd1_n";
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
phy-mode = "rgmii";
|
||||
clock_in_out = "output";
|
||||
|
||||
snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
|
||||
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
&gmac0_rx_bus2
|
||||
&gmac0_rgmii_clk
|
||||
&gmac0_rgmii_bus
|
||||
&gmac0_clkinout>;
|
||||
|
||||
tx_delay = <0x3c>;
|
||||
rx_delay = <0x2f>;
|
||||
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
phy-mode = "rgmii";
|
||||
clock_in_out = "output";
|
||||
|
||||
snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
&gmac1m1_rgmii_bus
|
||||
&gmac1m1_clkinout>;
|
||||
|
||||
tx_delay = <0x4f>;
|
||||
rx_delay = <0x26>;
|
||||
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
avdd-0v9-supply = <&vdda0v9_image>;
|
||||
avdd-1v8-supply = <&vcca1v8_image>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_in {
|
||||
hdmi_in_vp0: endpoint {
|
||||
remote-endpoint = <&vp0_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_out {
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <712500>;
|
||||
regulator-max-microvolt = <1390000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
|
||||
#clock-cells = <1>;
|
||||
clock-names = "mclk";
|
||||
clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>;
|
||||
rockchip,system-power-controller;
|
||||
#sound-dai-cells = <0>;
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
wakeup-source;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-name = "vdda0v9_image";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-name = "vdda_0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-name = "vccio_acodec";
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-name = "vcca_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-name = "vcca1v8_image";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&i2s0_8ch {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2s1_8ch {
|
||||
rockchip,trcm-sync-tx-only;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
rgmii_phy0: phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
leds {
|
||||
led_work_en: led_work_en {
|
||||
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
led_user_en: led_user_en {
|
||||
rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio-pwrseq {
|
||||
wifi_enable_h: wifi-enable-h {
|
||||
rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_otg_en: vcc5v0-otg-en {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc_hub_reset_en: vcc-hub-reset-en {
|
||||
rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
fusb0_int {
|
||||
fusb0_int: fusb0-int {
|
||||
rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie {
|
||||
pcie_enable_h: pcie-enable-h {
|
||||
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pcie_reset_h: pcie-reset-h {
|
||||
rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pcie_pi6c_oe_en: pcie-pi6c-oe-en {
|
||||
rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
phy-supply = <&pcie_pi6c_oe>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_reset_h>;
|
||||
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc3v3_pmu>;
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio2-supply = <&vcc_1v8>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc2 {
|
||||
max-frequency = <150000000>;
|
||||
supports-sdio;
|
||||
bus-width = <4>;
|
||||
disable-wp;
|
||||
cap-sd-highspeed;
|
||||
cap-sdio-irq;
|
||||
keep-power-in-suspend;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
|
||||
sd-uhs-sdr104;
|
||||
mmc-pwrseq = <&sdio_pwrseq>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_host {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
extcon = <&usb2phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi_in_vp0>;
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
|
@ -1,770 +0,0 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Radxa ROCK3 Model A";
|
||||
compatible = "radxa,rock3a", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac1;
|
||||
mmc0 = &sdmmc0;
|
||||
mmc1 = &sdhci;
|
||||
};
|
||||
|
||||
chosen: chosen {
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
hdmi-con {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
|
||||
port {
|
||||
hdmi_con_in: endpoint {
|
||||
remote-endpoint = <&hdmi_out_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led_user: led-0 {
|
||||
gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
function = LED_FUNCTION_HEARTBEAT;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_user_en>;
|
||||
};
|
||||
};
|
||||
|
||||
rk809-sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,name = "Analog RK809";
|
||||
simple-audio-card,mclk-fs = <256>;
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&i2s1_8ch>;
|
||||
};
|
||||
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&rk809>;
|
||||
};
|
||||
};
|
||||
|
||||
vcc12v_dcin: vcc12v-dcin {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc12v_dcin";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vcc3v3_sys: vcc3v3-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_sys: vcc5v0-sys {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_usb: vcc5v0-usb {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_usb";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_host: vcc5v0-usb-host {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_host_en>;
|
||||
regulator-name = "vcc5v0_usb_host";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_hub: vcc5v0-usb-hub {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_hub_en>;
|
||||
regulator-name = "vcc5v0_usb_hub";
|
||||
regulator-always-on;
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg: vcc5v0-usb-otg {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_usb_otg_en>;
|
||||
regulator-name = "vcc5v0_usb_otg";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
pcie30_avdd0v9: pcie30-avdd0v9 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie30_avdd0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
pcie30_avdd1v8: pcie30-avdd1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie30_avdd1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
};
|
||||
|
||||
/* pi6c pcie clock generator */
|
||||
vcc3v3_pi6c_03: vcc3v3-pi6c-03 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_pi6c_03";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie: vcc3v3-pcie {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_enable_h>;
|
||||
regulator-name = "vcc3v3_pcie";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc_cam: vcc-cam {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc_cam_en>;
|
||||
regulator-name = "vcc_cam";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_mipi: vcc-mipi {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc_mipi_en>;
|
||||
regulator-name = "vcc_mipi";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu2 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&cpu3 {
|
||||
cpu-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&gmac1 {
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
&gmac1m1_rgmii_bus>;
|
||||
snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
tx_delay = <0x42>;
|
||||
rx_delay = <0x28>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&gpu {
|
||||
mali-supply = <&vdd_gpu>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
avdd-0v9-supply = <&vdda0v9_image>;
|
||||
avdd-1v8-supply = <&vcca1v8_image>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi_in {
|
||||
hdmi_in_vp0: endpoint {
|
||||
remote-endpoint = <&vp0_out_hdmi>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_out {
|
||||
hdmi_out_con: endpoint {
|
||||
remote-endpoint = <&hdmi_con_in>;
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi_sound {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
vdd_cpu: regulator@1c {
|
||||
compatible = "tcs,tcs4525";
|
||||
reg = <0x1c>;
|
||||
fcs,suspend-voltage-selector = <1>;
|
||||
regulator-name = "vdd_cpu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-ramp-delay = <2300>;
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
rk809: pmic@20 {
|
||||
compatible = "rockchip,rk809";
|
||||
reg = <0x20>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
|
||||
#clock-cells = <1>;
|
||||
clock-names = "mclk";
|
||||
clocks = <&cru I2S1_MCLKOUT_TX>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
|
||||
rockchip,system-power-controller;
|
||||
#sound-dai-cells = <0>;
|
||||
wakeup-source;
|
||||
|
||||
vcc1-supply = <&vcc3v3_sys>;
|
||||
vcc2-supply = <&vcc3v3_sys>;
|
||||
vcc3-supply = <&vcc3v3_sys>;
|
||||
vcc4-supply = <&vcc3v3_sys>;
|
||||
vcc5-supply = <&vcc3v3_sys>;
|
||||
vcc6-supply = <&vcc3v3_sys>;
|
||||
vcc7-supply = <&vcc3v3_sys>;
|
||||
vcc8-supply = <&vcc3v3_sys>;
|
||||
vcc9-supply = <&vcc3v3_sys>;
|
||||
|
||||
regulators {
|
||||
vdd_logic: DCDC_REG1 {
|
||||
regulator-name = "vdd_logic";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_gpu: DCDC_REG2 {
|
||||
regulator-name = "vdd_gpu";
|
||||
regulator-always-on;
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_ddr: DCDC_REG3 {
|
||||
regulator-name = "vcc_ddr";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-initial-mode = <0x2>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_npu: DCDC_REG4 {
|
||||
regulator-name = "vdd_npu";
|
||||
regulator-init-microvolt = <900000>;
|
||||
regulator-initial-mode = <0x2>;
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-ramp-delay = <6001>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_1v8: DCDC_REG5 {
|
||||
regulator-name = "vcc_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_image: LDO_REG1 {
|
||||
regulator-name = "vdda0v9_image";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda_0v9: LDO_REG2 {
|
||||
regulator-name = "vdda_0v9";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda0v9_pmu: LDO_REG3 {
|
||||
regulator-name = "vdda0v9_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <900000>;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-name = "vccio_acodec";
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vccio_sd: LDO_REG5 {
|
||||
regulator-name = "vccio_sd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_pmu: LDO_REG6 {
|
||||
regulator-name = "vcc3v3_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca_1v8: LDO_REG7 {
|
||||
regulator-name = "vcca_1v8";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_pmu: LDO_REG8 {
|
||||
regulator-name = "vcca1v8_pmu";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1800000>;
|
||||
};
|
||||
};
|
||||
|
||||
vcca1v8_image: LDO_REG9 {
|
||||
regulator-name = "vcca1v8_image";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc_3v3: SWITCH_REG1 {
|
||||
regulator-name = "vcc_3v3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vcc3v3_sd: SWITCH_REG2 {
|
||||
regulator-name = "vcc3v3_sd";
|
||||
|
||||
regulator-state-mem {
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
codec {
|
||||
mic-in-differential;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
status = "okay";
|
||||
|
||||
hym8563: rtc@51 {
|
||||
compatible = "haoyu,hym8563";
|
||||
reg = <0x51>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "rtcic_32kout";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hym8563_int>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&i2s0_8ch {
|
||||
status = "okay";
|
||||
};
|
||||
#endif
|
||||
|
||||
&i2s1_8ch {
|
||||
rockchip,trcm-sync-tx-only;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie2x1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_reset_h>;
|
||||
reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
phy-supply = <&vcc3v3_pi6c_03>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie30x2m1_pins>;
|
||||
reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
cam {
|
||||
vcc_cam_en: vcc_cam_en {
|
||||
rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
display {
|
||||
vcc_mipi_en: vcc_mipi_en {
|
||||
rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
hym8563 {
|
||||
hym8563_int: hym8563-int {
|
||||
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
led_user_en: led_user_en {
|
||||
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie {
|
||||
pcie_enable_h: pcie-enable-h {
|
||||
rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
pcie_reset_h: pcie-reset-h {
|
||||
rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pmic {
|
||||
pmic_int: pmic_int {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
usb {
|
||||
vcc5v0_usb_host_en: vcc5v0_usb_host_en {
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_hub_en: vcc5v0_usb_hub_en {
|
||||
rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
pmuio1-supply = <&vcc3v3_pmu>;
|
||||
pmuio2-supply = <&vcc3v3_pmu>;
|
||||
vccio1-supply = <&vccio_acodec>;
|
||||
vccio2-supply = <&vcc_1v8>;
|
||||
vccio3-supply = <&vccio_sd>;
|
||||
vccio4-supply = <&vcc_1v8>;
|
||||
vccio5-supply = <&vcc_3v3>;
|
||||
vccio6-supply = <&vcc_1v8>;
|
||||
vccio7-supply = <&vcc_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&saradc {
|
||||
vref-supply = <&vcca_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
vmmc-supply = <&vcc_3v3>;
|
||||
vqmmc-supply = <&vcc_1v8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
sd-uhs-sdr104;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
extcon = <&usb2phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_xhci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
phy-supply = <&vcc5v0_usb_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_host {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2phy1_otg {
|
||||
phy-supply = <&vcc5v0_usb_host>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#ifdef DTS_NO_LEGACY
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vop_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vp0 {
|
||||
vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
remote-endpoint = <&hdmi_in_vp0>;
|
||||
};
|
||||
};
|
||||
#endif
|
||||
|
|
@ -1,310 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* rockchip-rng.c Random Number Generator driver for the Rockchip
|
||||
*
|
||||
* Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd.
|
||||
* Author: Lin Jinhan <troy.lin@rock-chips.com>
|
||||
*
|
||||
*/
|
||||
#include <linux/clk.h>
|
||||
#include <linux/hw_random.h>
|
||||
#include <linux/iopoll.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
|
||||
#define _SBF(s, v) ((v) << (s))
|
||||
#define HIWORD_UPDATE(val, mask, shift) \
|
||||
((val) << (shift) | (mask) << ((shift) + 16))
|
||||
|
||||
#define ROCKCHIP_AUTOSUSPEND_DELAY 100
|
||||
#define ROCKCHIP_POLL_PERIOD_US 100
|
||||
#define ROCKCHIP_POLL_TIMEOUT_US 10000
|
||||
#define RK_MAX_RNG_BYTE (32)
|
||||
|
||||
/* start of CRYPTO V1 register define */
|
||||
#define CRYPTO_V1_CTRL 0x0008
|
||||
#define CRYPTO_V1_RNG_START BIT(8)
|
||||
#define CRYPTO_V1_RNG_FLUSH BIT(9)
|
||||
|
||||
#define CRYPTO_V1_TRNG_CTRL 0x0200
|
||||
#define CRYPTO_V1_OSC_ENABLE BIT(16)
|
||||
#define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x) (x)
|
||||
|
||||
#define CRYPTO_V1_TRNG_DOUT_0 0x0204
|
||||
/* end of CRYPTO V1 register define */
|
||||
|
||||
/* start of CRYPTO V2 register define */
|
||||
#define CRYPTO_V2_RNG_CTL 0x0400
|
||||
#define CRYPTO_V2_RNG_64_BIT_LEN _SBF(4, 0x00)
|
||||
#define CRYPTO_V2_RNG_128_BIT_LEN _SBF(4, 0x01)
|
||||
#define CRYPTO_V2_RNG_192_BIT_LEN _SBF(4, 0x02)
|
||||
#define CRYPTO_V2_RNG_256_BIT_LEN _SBF(4, 0x03)
|
||||
#define CRYPTO_V2_RNG_FATESY_SOC_RING _SBF(2, 0x00)
|
||||
#define CRYPTO_V2_RNG_SLOWER_SOC_RING_0 _SBF(2, 0x01)
|
||||
#define CRYPTO_V2_RNG_SLOWER_SOC_RING_1 _SBF(2, 0x02)
|
||||
#define CRYPTO_V2_RNG_SLOWEST_SOC_RING _SBF(2, 0x03)
|
||||
#define CRYPTO_V2_RNG_ENABLE BIT(1)
|
||||
#define CRYPTO_V2_RNG_START BIT(0)
|
||||
#define CRYPTO_V2_RNG_SAMPLE_CNT 0x0404
|
||||
#define CRYPTO_V2_RNG_DOUT_0 0x0410
|
||||
/* end of CRYPTO V2 register define */
|
||||
|
||||
struct rk_rng_soc_data {
|
||||
int (*rk_rng_read)(struct hwrng *rng, void *buf, size_t max, bool wait);
|
||||
};
|
||||
|
||||
struct rk_rng {
|
||||
struct device *dev;
|
||||
struct hwrng rng;
|
||||
void __iomem *mem;
|
||||
struct rk_rng_soc_data *soc_data;
|
||||
int clk_num;
|
||||
struct clk_bulk_data *clk_bulks;
|
||||
};
|
||||
|
||||
static void rk_rng_writel(struct rk_rng *rng, u32 val, u32 offset)
|
||||
{
|
||||
__raw_writel(val, rng->mem + offset);
|
||||
}
|
||||
|
||||
static u32 rk_rng_readl(struct rk_rng *rng, u32 offset)
|
||||
{
|
||||
return __raw_readl(rng->mem + offset);
|
||||
}
|
||||
|
||||
static int rk_rng_init(struct hwrng *rng)
|
||||
{
|
||||
int ret;
|
||||
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
|
||||
|
||||
dev_dbg(rk_rng->dev, "clk_bulk_prepare_enable.\n");
|
||||
|
||||
ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks);
|
||||
if (ret < 0) {
|
||||
dev_err(rk_rng->dev, "failed to enable clks %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rk_rng_cleanup(struct hwrng *rng)
|
||||
{
|
||||
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
|
||||
|
||||
dev_dbg(rk_rng->dev, "clk_bulk_disable_unprepare.\n");
|
||||
clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks);
|
||||
}
|
||||
|
||||
static void rk_rng_read_regs(struct rk_rng *rng, u32 offset, void *buf,
|
||||
size_t size)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
for (i = 0; i < size; i += 4)
|
||||
*(u32 *)(buf + i) = be32_to_cpu(rk_rng_readl(rng, offset + i));
|
||||
}
|
||||
|
||||
static int rk_rng_v1_read(struct hwrng *rng, void *buf, size_t max, bool wait)
|
||||
{
|
||||
int ret = 0;
|
||||
u32 reg_ctrl = 0;
|
||||
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
|
||||
|
||||
ret = pm_runtime_get_sync(rk_rng->dev);
|
||||
if (ret < 0) {
|
||||
pm_runtime_put_noidle(rk_rng->dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* enable osc_ring to get entropy, sample period is set as 100 */
|
||||
reg_ctrl = CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100);
|
||||
rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_TRNG_CTRL);
|
||||
|
||||
reg_ctrl = HIWORD_UPDATE(CRYPTO_V1_RNG_START, CRYPTO_V1_RNG_START, 0);
|
||||
|
||||
rk_rng_writel(rk_rng, reg_ctrl, CRYPTO_V1_CTRL);
|
||||
|
||||
ret = readl_poll_timeout(rk_rng->mem + CRYPTO_V1_CTRL, reg_ctrl,
|
||||
!(reg_ctrl & CRYPTO_V1_RNG_START),
|
||||
ROCKCHIP_POLL_PERIOD_US,
|
||||
ROCKCHIP_POLL_TIMEOUT_US);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
|
||||
ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
|
||||
|
||||
rk_rng_read_regs(rk_rng, CRYPTO_V1_TRNG_DOUT_0, buf, ret);
|
||||
|
||||
out:
|
||||
/* close TRNG */
|
||||
rk_rng_writel(rk_rng, HIWORD_UPDATE(0, CRYPTO_V1_RNG_START, 0),
|
||||
CRYPTO_V1_CTRL);
|
||||
|
||||
pm_runtime_mark_last_busy(rk_rng->dev);
|
||||
pm_runtime_put_sync_autosuspend(rk_rng->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rk_rng_v2_read(struct hwrng *rng, void *buf, size_t max, bool wait)
|
||||
{
|
||||
int ret = 0;
|
||||
u32 reg_ctrl = 0;
|
||||
struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng);
|
||||
|
||||
ret = pm_runtime_get_sync(rk_rng->dev);
|
||||
if (ret < 0) {
|
||||
pm_runtime_put_noidle(rk_rng->dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* enable osc_ring to get entropy, sample period is set as 100 */
|
||||
rk_rng_writel(rk_rng, 100, CRYPTO_V2_RNG_SAMPLE_CNT);
|
||||
|
||||
reg_ctrl |= CRYPTO_V2_RNG_256_BIT_LEN;
|
||||
reg_ctrl |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0;
|
||||
reg_ctrl |= CRYPTO_V2_RNG_ENABLE;
|
||||
reg_ctrl |= CRYPTO_V2_RNG_START;
|
||||
|
||||
rk_rng_writel(rk_rng, HIWORD_UPDATE(reg_ctrl, 0xffff, 0),
|
||||
CRYPTO_V2_RNG_CTL);
|
||||
|
||||
ret = readl_poll_timeout(rk_rng->mem + CRYPTO_V2_RNG_CTL, reg_ctrl,
|
||||
!(reg_ctrl & CRYPTO_V2_RNG_START),
|
||||
ROCKCHIP_POLL_PERIOD_US,
|
||||
ROCKCHIP_POLL_TIMEOUT_US);
|
||||
if (ret < 0)
|
||||
goto out;
|
||||
|
||||
ret = min_t(size_t, max, RK_MAX_RNG_BYTE);
|
||||
|
||||
rk_rng_read_regs(rk_rng, CRYPTO_V2_RNG_DOUT_0, buf, ret);
|
||||
|
||||
out:
|
||||
/* close TRNG */
|
||||
rk_rng_writel(rk_rng, HIWORD_UPDATE(0, 0xffff, 0), CRYPTO_V2_RNG_CTL);
|
||||
|
||||
pm_runtime_mark_last_busy(rk_rng->dev);
|
||||
pm_runtime_put_sync_autosuspend(rk_rng->dev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct rk_rng_soc_data rk_rng_v1_soc_data = {
|
||||
.rk_rng_read = rk_rng_v1_read,
|
||||
};
|
||||
|
||||
static const struct rk_rng_soc_data rk_rng_v2_soc_data = {
|
||||
.rk_rng_read = rk_rng_v2_read,
|
||||
};
|
||||
|
||||
static const struct of_device_id rk_rng_dt_match[] = {
|
||||
{
|
||||
.compatible = "rockchip,cryptov1-rng",
|
||||
.data = (void *)&rk_rng_v1_soc_data,
|
||||
},
|
||||
{
|
||||
.compatible = "rockchip,cryptov2-rng",
|
||||
.data = (void *)&rk_rng_v2_soc_data,
|
||||
},
|
||||
{ },
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(of, rk_rng_dt_match);
|
||||
|
||||
static int rk_rng_probe(struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
struct rk_rng *rk_rng;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
const struct of_device_id *match;
|
||||
|
||||
dev_dbg(&pdev->dev, "probing...\n");
|
||||
rk_rng = devm_kzalloc(&pdev->dev, sizeof(struct rk_rng), GFP_KERNEL);
|
||||
if (!rk_rng)
|
||||
return -ENOMEM;
|
||||
|
||||
match = of_match_node(rk_rng_dt_match, np);
|
||||
rk_rng->soc_data = (struct rk_rng_soc_data *)match->data;
|
||||
|
||||
rk_rng->dev = &pdev->dev;
|
||||
rk_rng->rng.name = "rockchip";
|
||||
#ifndef CONFIG_PM
|
||||
rk_rng->rng.init = rk_rng_init;
|
||||
rk_rng->rng.cleanup = rk_rng_cleanup,
|
||||
#endif
|
||||
rk_rng->rng.read = rk_rng->soc_data->rk_rng_read;
|
||||
rk_rng->rng.quality = 999;
|
||||
|
||||
rk_rng->mem = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
|
||||
if (IS_ERR(rk_rng->mem))
|
||||
return PTR_ERR(rk_rng->mem);
|
||||
|
||||
rk_rng->clk_num = devm_clk_bulk_get_all(&pdev->dev, &rk_rng->clk_bulks);
|
||||
if (rk_rng->clk_num < 0) {
|
||||
dev_err(&pdev->dev, "failed to get clks property\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, rk_rng);
|
||||
|
||||
pm_runtime_set_autosuspend_delay(&pdev->dev,
|
||||
ROCKCHIP_AUTOSUSPEND_DELAY);
|
||||
pm_runtime_use_autosuspend(&pdev->dev);
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
|
||||
ret = devm_hwrng_register(&pdev->dev, &rk_rng->rng);
|
||||
if (ret) {
|
||||
pm_runtime_dont_use_autosuspend(&pdev->dev);
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int rk_rng_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct rk_rng *rk_rng = dev_get_drvdata(dev);
|
||||
|
||||
rk_rng_cleanup(&rk_rng->rng);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk_rng_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct rk_rng *rk_rng = dev_get_drvdata(dev);
|
||||
|
||||
return rk_rng_init(&rk_rng->rng);
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops rk_rng_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend,
|
||||
rk_rng_runtime_resume, NULL)
|
||||
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
||||
pm_runtime_force_resume)
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
static struct platform_driver rk_rng_driver = {
|
||||
.driver = {
|
||||
.name = "rockchip-rng",
|
||||
#ifdef CONFIG_PM
|
||||
.pm = &rk_rng_pm_ops,
|
||||
#endif
|
||||
.of_match_table = rk_rng_dt_match,
|
||||
},
|
||||
.probe = rk_rng_probe,
|
||||
};
|
||||
|
||||
module_platform_driver(rk_rng_driver);
|
||||
|
||||
MODULE_DESCRIPTION("ROCKCHIP H/W Random Number Generator driver");
|
||||
MODULE_AUTHOR("Lin Jinhan <troy.lin@rock-chips.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -1,852 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
|
||||
* Author: Lin Huang <hl@rock-chips.com>
|
||||
*/
|
||||
|
||||
#include <linux/arm-smccc.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/devfreq.h>
|
||||
#include <linux/devfreq-event.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/iversion.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_opp.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/regulator/consumer.h>
|
||||
#include <linux/rwsem.h>
|
||||
#include <linux/suspend.h>
|
||||
#include <linux/version.h>
|
||||
|
||||
#include <soc/rockchip/rockchip_sip.h>
|
||||
|
||||
#define DTS_PAR_OFFSET (4096)
|
||||
|
||||
struct share_params {
|
||||
u32 hz;
|
||||
u32 lcdc_type;
|
||||
u32 vop;
|
||||
u32 vop_dclk_mode;
|
||||
u32 sr_idle_en;
|
||||
u32 addr_mcu_el3;
|
||||
/*
|
||||
* 1: need to wait flag1
|
||||
* 0: never wait flag1
|
||||
*/
|
||||
u32 wait_flag1;
|
||||
/*
|
||||
* 1: need to wait flag1
|
||||
* 0: never wait flag1
|
||||
*/
|
||||
u32 wait_flag0;
|
||||
u32 complt_hwirq;
|
||||
/* if need, add parameter after */
|
||||
};
|
||||
|
||||
static struct share_params *ddr_psci_param;
|
||||
|
||||
/* hope this define can adapt all future platform */
|
||||
static const char * const rk3328_dts_timing[] = {
|
||||
"ddr3_speed_bin",
|
||||
"ddr4_speed_bin",
|
||||
"pd_idle",
|
||||
"sr_idle",
|
||||
"sr_mc_gate_idle",
|
||||
"srpd_lite_idle",
|
||||
"standby_idle",
|
||||
|
||||
"auto_pd_dis_freq",
|
||||
"auto_sr_dis_freq",
|
||||
"ddr3_dll_dis_freq",
|
||||
"ddr4_dll_dis_freq",
|
||||
"phy_dll_dis_freq",
|
||||
|
||||
"ddr3_odt_dis_freq",
|
||||
"phy_ddr3_odt_dis_freq",
|
||||
"ddr3_drv",
|
||||
"ddr3_odt",
|
||||
"phy_ddr3_ca_drv",
|
||||
"phy_ddr3_ck_drv",
|
||||
"phy_ddr3_dq_drv",
|
||||
"phy_ddr3_odt",
|
||||
|
||||
"lpddr3_odt_dis_freq",
|
||||
"phy_lpddr3_odt_dis_freq",
|
||||
"lpddr3_drv",
|
||||
"lpddr3_odt",
|
||||
"phy_lpddr3_ca_drv",
|
||||
"phy_lpddr3_ck_drv",
|
||||
"phy_lpddr3_dq_drv",
|
||||
"phy_lpddr3_odt",
|
||||
|
||||
"lpddr4_odt_dis_freq",
|
||||
"phy_lpddr4_odt_dis_freq",
|
||||
"lpddr4_drv",
|
||||
"lpddr4_dq_odt",
|
||||
"lpddr4_ca_odt",
|
||||
"phy_lpddr4_ca_drv",
|
||||
"phy_lpddr4_ck_cs_drv",
|
||||
"phy_lpddr4_dq_drv",
|
||||
"phy_lpddr4_odt",
|
||||
|
||||
"ddr4_odt_dis_freq",
|
||||
"phy_ddr4_odt_dis_freq",
|
||||
"ddr4_drv",
|
||||
"ddr4_odt",
|
||||
"phy_ddr4_ca_drv",
|
||||
"phy_ddr4_ck_drv",
|
||||
"phy_ddr4_dq_drv",
|
||||
"phy_ddr4_odt",
|
||||
};
|
||||
|
||||
static const char * const rk3328_dts_ca_timing[] = {
|
||||
"ddr3a1_ddr4a9_de-skew",
|
||||
"ddr3a0_ddr4a10_de-skew",
|
||||
"ddr3a3_ddr4a6_de-skew",
|
||||
"ddr3a2_ddr4a4_de-skew",
|
||||
"ddr3a5_ddr4a8_de-skew",
|
||||
"ddr3a4_ddr4a5_de-skew",
|
||||
"ddr3a7_ddr4a11_de-skew",
|
||||
"ddr3a6_ddr4a7_de-skew",
|
||||
"ddr3a9_ddr4a0_de-skew",
|
||||
"ddr3a8_ddr4a13_de-skew",
|
||||
"ddr3a11_ddr4a3_de-skew",
|
||||
"ddr3a10_ddr4cs0_de-skew",
|
||||
"ddr3a13_ddr4a2_de-skew",
|
||||
"ddr3a12_ddr4ba1_de-skew",
|
||||
"ddr3a15_ddr4odt0_de-skew",
|
||||
"ddr3a14_ddr4a1_de-skew",
|
||||
"ddr3ba1_ddr4a15_de-skew",
|
||||
"ddr3ba0_ddr4bg0_de-skew",
|
||||
"ddr3ras_ddr4cke_de-skew",
|
||||
"ddr3ba2_ddr4ba0_de-skew",
|
||||
"ddr3we_ddr4bg1_de-skew",
|
||||
"ddr3cas_ddr4a12_de-skew",
|
||||
"ddr3ckn_ddr4ckn_de-skew",
|
||||
"ddr3ckp_ddr4ckp_de-skew",
|
||||
"ddr3cke_ddr4a16_de-skew",
|
||||
"ddr3odt0_ddr4a14_de-skew",
|
||||
"ddr3cs0_ddr4act_de-skew",
|
||||
"ddr3reset_ddr4reset_de-skew",
|
||||
"ddr3cs1_ddr4cs1_de-skew",
|
||||
"ddr3odt1_ddr4odt1_de-skew",
|
||||
};
|
||||
|
||||
static const char * const rk3328_dts_cs0_timing[] = {
|
||||
"cs0_dm0_rx_de-skew",
|
||||
"cs0_dm0_tx_de-skew",
|
||||
"cs0_dq0_rx_de-skew",
|
||||
"cs0_dq0_tx_de-skew",
|
||||
"cs0_dq1_rx_de-skew",
|
||||
"cs0_dq1_tx_de-skew",
|
||||
"cs0_dq2_rx_de-skew",
|
||||
"cs0_dq2_tx_de-skew",
|
||||
"cs0_dq3_rx_de-skew",
|
||||
"cs0_dq3_tx_de-skew",
|
||||
"cs0_dq4_rx_de-skew",
|
||||
"cs0_dq4_tx_de-skew",
|
||||
"cs0_dq5_rx_de-skew",
|
||||
"cs0_dq5_tx_de-skew",
|
||||
"cs0_dq6_rx_de-skew",
|
||||
"cs0_dq6_tx_de-skew",
|
||||
"cs0_dq7_rx_de-skew",
|
||||
"cs0_dq7_tx_de-skew",
|
||||
"cs0_dqs0_rx_de-skew",
|
||||
"cs0_dqs0p_tx_de-skew",
|
||||
"cs0_dqs0n_tx_de-skew",
|
||||
|
||||
"cs0_dm1_rx_de-skew",
|
||||
"cs0_dm1_tx_de-skew",
|
||||
"cs0_dq8_rx_de-skew",
|
||||
"cs0_dq8_tx_de-skew",
|
||||
"cs0_dq9_rx_de-skew",
|
||||
"cs0_dq9_tx_de-skew",
|
||||
"cs0_dq10_rx_de-skew",
|
||||
"cs0_dq10_tx_de-skew",
|
||||
"cs0_dq11_rx_de-skew",
|
||||
"cs0_dq11_tx_de-skew",
|
||||
"cs0_dq12_rx_de-skew",
|
||||
"cs0_dq12_tx_de-skew",
|
||||
"cs0_dq13_rx_de-skew",
|
||||
"cs0_dq13_tx_de-skew",
|
||||
"cs0_dq14_rx_de-skew",
|
||||
"cs0_dq14_tx_de-skew",
|
||||
"cs0_dq15_rx_de-skew",
|
||||
"cs0_dq15_tx_de-skew",
|
||||
"cs0_dqs1_rx_de-skew",
|
||||
"cs0_dqs1p_tx_de-skew",
|
||||
"cs0_dqs1n_tx_de-skew",
|
||||
|
||||
"cs0_dm2_rx_de-skew",
|
||||
"cs0_dm2_tx_de-skew",
|
||||
"cs0_dq16_rx_de-skew",
|
||||
"cs0_dq16_tx_de-skew",
|
||||
"cs0_dq17_rx_de-skew",
|
||||
"cs0_dq17_tx_de-skew",
|
||||
"cs0_dq18_rx_de-skew",
|
||||
"cs0_dq18_tx_de-skew",
|
||||
"cs0_dq19_rx_de-skew",
|
||||
"cs0_dq19_tx_de-skew",
|
||||
"cs0_dq20_rx_de-skew",
|
||||
"cs0_dq20_tx_de-skew",
|
||||
"cs0_dq21_rx_de-skew",
|
||||
"cs0_dq21_tx_de-skew",
|
||||
"cs0_dq22_rx_de-skew",
|
||||
"cs0_dq22_tx_de-skew",
|
||||
"cs0_dq23_rx_de-skew",
|
||||
"cs0_dq23_tx_de-skew",
|
||||
"cs0_dqs2_rx_de-skew",
|
||||
"cs0_dqs2p_tx_de-skew",
|
||||
"cs0_dqs2n_tx_de-skew",
|
||||
|
||||
"cs0_dm3_rx_de-skew",
|
||||
"cs0_dm3_tx_de-skew",
|
||||
"cs0_dq24_rx_de-skew",
|
||||
"cs0_dq24_tx_de-skew",
|
||||
"cs0_dq25_rx_de-skew",
|
||||
"cs0_dq25_tx_de-skew",
|
||||
"cs0_dq26_rx_de-skew",
|
||||
"cs0_dq26_tx_de-skew",
|
||||
"cs0_dq27_rx_de-skew",
|
||||
"cs0_dq27_tx_de-skew",
|
||||
"cs0_dq28_rx_de-skew",
|
||||
"cs0_dq28_tx_de-skew",
|
||||
"cs0_dq29_rx_de-skew",
|
||||
"cs0_dq29_tx_de-skew",
|
||||
"cs0_dq30_rx_de-skew",
|
||||
"cs0_dq30_tx_de-skew",
|
||||
"cs0_dq31_rx_de-skew",
|
||||
"cs0_dq31_tx_de-skew",
|
||||
"cs0_dqs3_rx_de-skew",
|
||||
"cs0_dqs3p_tx_de-skew",
|
||||
"cs0_dqs3n_tx_de-skew",
|
||||
};
|
||||
|
||||
static const char * const rk3328_dts_cs1_timing[] = {
|
||||
"cs1_dm0_rx_de-skew",
|
||||
"cs1_dm0_tx_de-skew",
|
||||
"cs1_dq0_rx_de-skew",
|
||||
"cs1_dq0_tx_de-skew",
|
||||
"cs1_dq1_rx_de-skew",
|
||||
"cs1_dq1_tx_de-skew",
|
||||
"cs1_dq2_rx_de-skew",
|
||||
"cs1_dq2_tx_de-skew",
|
||||
"cs1_dq3_rx_de-skew",
|
||||
"cs1_dq3_tx_de-skew",
|
||||
"cs1_dq4_rx_de-skew",
|
||||
"cs1_dq4_tx_de-skew",
|
||||
"cs1_dq5_rx_de-skew",
|
||||
"cs1_dq5_tx_de-skew",
|
||||
"cs1_dq6_rx_de-skew",
|
||||
"cs1_dq6_tx_de-skew",
|
||||
"cs1_dq7_rx_de-skew",
|
||||
"cs1_dq7_tx_de-skew",
|
||||
"cs1_dqs0_rx_de-skew",
|
||||
"cs1_dqs0p_tx_de-skew",
|
||||
"cs1_dqs0n_tx_de-skew",
|
||||
|
||||
"cs1_dm1_rx_de-skew",
|
||||
"cs1_dm1_tx_de-skew",
|
||||
"cs1_dq8_rx_de-skew",
|
||||
"cs1_dq8_tx_de-skew",
|
||||
"cs1_dq9_rx_de-skew",
|
||||
"cs1_dq9_tx_de-skew",
|
||||
"cs1_dq10_rx_de-skew",
|
||||
"cs1_dq10_tx_de-skew",
|
||||
"cs1_dq11_rx_de-skew",
|
||||
"cs1_dq11_tx_de-skew",
|
||||
"cs1_dq12_rx_de-skew",
|
||||
"cs1_dq12_tx_de-skew",
|
||||
"cs1_dq13_rx_de-skew",
|
||||
"cs1_dq13_tx_de-skew",
|
||||
"cs1_dq14_rx_de-skew",
|
||||
"cs1_dq14_tx_de-skew",
|
||||
"cs1_dq15_rx_de-skew",
|
||||
"cs1_dq15_tx_de-skew",
|
||||
"cs1_dqs1_rx_de-skew",
|
||||
"cs1_dqs1p_tx_de-skew",
|
||||
"cs1_dqs1n_tx_de-skew",
|
||||
|
||||
"cs1_dm2_rx_de-skew",
|
||||
"cs1_dm2_tx_de-skew",
|
||||
"cs1_dq16_rx_de-skew",
|
||||
"cs1_dq16_tx_de-skew",
|
||||
"cs1_dq17_rx_de-skew",
|
||||
"cs1_dq17_tx_de-skew",
|
||||
"cs1_dq18_rx_de-skew",
|
||||
"cs1_dq18_tx_de-skew",
|
||||
"cs1_dq19_rx_de-skew",
|
||||
"cs1_dq19_tx_de-skew",
|
||||
"cs1_dq20_rx_de-skew",
|
||||
"cs1_dq20_tx_de-skew",
|
||||
"cs1_dq21_rx_de-skew",
|
||||
"cs1_dq21_tx_de-skew",
|
||||
"cs1_dq22_rx_de-skew",
|
||||
"cs1_dq22_tx_de-skew",
|
||||
"cs1_dq23_rx_de-skew",
|
||||
"cs1_dq23_tx_de-skew",
|
||||
"cs1_dqs2_rx_de-skew",
|
||||
"cs1_dqs2p_tx_de-skew",
|
||||
"cs1_dqs2n_tx_de-skew",
|
||||
|
||||
"cs1_dm3_rx_de-skew",
|
||||
"cs1_dm3_tx_de-skew",
|
||||
"cs1_dq24_rx_de-skew",
|
||||
"cs1_dq24_tx_de-skew",
|
||||
"cs1_dq25_rx_de-skew",
|
||||
"cs1_dq25_tx_de-skew",
|
||||
"cs1_dq26_rx_de-skew",
|
||||
"cs1_dq26_tx_de-skew",
|
||||
"cs1_dq27_rx_de-skew",
|
||||
"cs1_dq27_tx_de-skew",
|
||||
"cs1_dq28_rx_de-skew",
|
||||
"cs1_dq28_tx_de-skew",
|
||||
"cs1_dq29_rx_de-skew",
|
||||
"cs1_dq29_tx_de-skew",
|
||||
"cs1_dq30_rx_de-skew",
|
||||
"cs1_dq30_tx_de-skew",
|
||||
"cs1_dq31_rx_de-skew",
|
||||
"cs1_dq31_tx_de-skew",
|
||||
"cs1_dqs3_rx_de-skew",
|
||||
"cs1_dqs3p_tx_de-skew",
|
||||
"cs1_dqs3n_tx_de-skew",
|
||||
};
|
||||
|
||||
struct rk3328_ddr_dts_config_timing {
|
||||
unsigned int ddr3_speed_bin;
|
||||
unsigned int ddr4_speed_bin;
|
||||
unsigned int pd_idle;
|
||||
unsigned int sr_idle;
|
||||
unsigned int sr_mc_gate_idle;
|
||||
unsigned int srpd_lite_idle;
|
||||
unsigned int standby_idle;
|
||||
|
||||
unsigned int auto_pd_dis_freq;
|
||||
unsigned int auto_sr_dis_freq;
|
||||
/* for ddr3 only */
|
||||
unsigned int ddr3_dll_dis_freq;
|
||||
/* for ddr4 only */
|
||||
unsigned int ddr4_dll_dis_freq;
|
||||
unsigned int phy_dll_dis_freq;
|
||||
|
||||
unsigned int ddr3_odt_dis_freq;
|
||||
unsigned int phy_ddr3_odt_dis_freq;
|
||||
unsigned int ddr3_drv;
|
||||
unsigned int ddr3_odt;
|
||||
unsigned int phy_ddr3_ca_drv;
|
||||
unsigned int phy_ddr3_ck_drv;
|
||||
unsigned int phy_ddr3_dq_drv;
|
||||
unsigned int phy_ddr3_odt;
|
||||
|
||||
unsigned int lpddr3_odt_dis_freq;
|
||||
unsigned int phy_lpddr3_odt_dis_freq;
|
||||
unsigned int lpddr3_drv;
|
||||
unsigned int lpddr3_odt;
|
||||
unsigned int phy_lpddr3_ca_drv;
|
||||
unsigned int phy_lpddr3_ck_drv;
|
||||
unsigned int phy_lpddr3_dq_drv;
|
||||
unsigned int phy_lpddr3_odt;
|
||||
|
||||
unsigned int lpddr4_odt_dis_freq;
|
||||
unsigned int phy_lpddr4_odt_dis_freq;
|
||||
unsigned int lpddr4_drv;
|
||||
unsigned int lpddr4_dq_odt;
|
||||
unsigned int lpddr4_ca_odt;
|
||||
unsigned int phy_lpddr4_ca_drv;
|
||||
unsigned int phy_lpddr4_ck_cs_drv;
|
||||
unsigned int phy_lpddr4_dq_drv;
|
||||
unsigned int phy_lpddr4_odt;
|
||||
|
||||
unsigned int ddr4_odt_dis_freq;
|
||||
unsigned int phy_ddr4_odt_dis_freq;
|
||||
unsigned int ddr4_drv;
|
||||
unsigned int ddr4_odt;
|
||||
unsigned int phy_ddr4_ca_drv;
|
||||
unsigned int phy_ddr4_ck_drv;
|
||||
unsigned int phy_ddr4_dq_drv;
|
||||
unsigned int phy_ddr4_odt;
|
||||
|
||||
unsigned int ca_skew[15];
|
||||
unsigned int cs0_skew[44];
|
||||
unsigned int cs1_skew[44];
|
||||
|
||||
unsigned int available;
|
||||
};
|
||||
|
||||
struct rk3328_ddr_de_skew_setting {
|
||||
unsigned int ca_de_skew[30];
|
||||
unsigned int cs0_de_skew[84];
|
||||
unsigned int cs1_de_skew[84];
|
||||
};
|
||||
|
||||
struct rk3328_dmcfreq {
|
||||
struct device *dev;
|
||||
struct devfreq *devfreq;
|
||||
struct devfreq_simple_ondemand_data ondemand_data;
|
||||
struct clk *dmc_clk;
|
||||
struct devfreq_event_dev *edev;
|
||||
struct mutex lock;
|
||||
struct regulator *vdd_center;
|
||||
unsigned long rate, target_rate;
|
||||
unsigned long volt, target_volt;
|
||||
|
||||
int (*set_auto_self_refresh)(u32 en);
|
||||
};
|
||||
|
||||
static void
|
||||
rk3328_de_skew_setting_2_register(struct rk3328_ddr_de_skew_setting *de_skew,
|
||||
struct rk3328_ddr_dts_config_timing *tim)
|
||||
{
|
||||
u32 n;
|
||||
u32 offset;
|
||||
u32 shift;
|
||||
|
||||
memset_io(tim->ca_skew, 0, sizeof(tim->ca_skew));
|
||||
memset_io(tim->cs0_skew, 0, sizeof(tim->cs0_skew));
|
||||
memset_io(tim->cs1_skew, 0, sizeof(tim->cs1_skew));
|
||||
|
||||
/* CA de-skew */
|
||||
for (n = 0; n < ARRAY_SIZE(de_skew->ca_de_skew); n++) {
|
||||
offset = n / 2;
|
||||
shift = n % 2;
|
||||
/* 0 => 4; 1 => 0 */
|
||||
shift = (shift == 0) ? 4 : 0;
|
||||
tim->ca_skew[offset] &= ~(0xf << shift);
|
||||
tim->ca_skew[offset] |= (de_skew->ca_de_skew[n] << shift);
|
||||
}
|
||||
|
||||
/* CS0 data de-skew */
|
||||
for (n = 0; n < ARRAY_SIZE(de_skew->cs0_de_skew); n++) {
|
||||
offset = ((n / 21) * 11) + ((n % 21) / 2);
|
||||
shift = ((n % 21) % 2);
|
||||
if ((n % 21) == 20)
|
||||
shift = 0;
|
||||
else
|
||||
/* 0 => 4; 1 => 0 */
|
||||
shift = (shift == 0) ? 4 : 0;
|
||||
tim->cs0_skew[offset] &= ~(0xf << shift);
|
||||
tim->cs0_skew[offset] |= (de_skew->cs0_de_skew[n] << shift);
|
||||
}
|
||||
|
||||
/* CS1 data de-skew */
|
||||
for (n = 0; n < ARRAY_SIZE(de_skew->cs1_de_skew); n++) {
|
||||
offset = ((n / 21) * 11) + ((n % 21) / 2);
|
||||
shift = ((n % 21) % 2);
|
||||
if ((n % 21) == 20)
|
||||
shift = 0;
|
||||
else
|
||||
/* 0 => 4; 1 => 0 */
|
||||
shift = (shift == 0) ? 4 : 0;
|
||||
tim->cs1_skew[offset] &= ~(0xf << shift);
|
||||
tim->cs1_skew[offset] |= (de_skew->cs1_de_skew[n] << shift);
|
||||
}
|
||||
}
|
||||
|
||||
static void of_get_rk3328_timings(struct device *dev,
|
||||
struct device_node *np, uint32_t *timing)
|
||||
{
|
||||
struct device_node *np_tim;
|
||||
u32 *p;
|
||||
struct rk3328_ddr_dts_config_timing *dts_timing;
|
||||
struct rk3328_ddr_de_skew_setting *de_skew;
|
||||
int ret = 0;
|
||||
u32 i;
|
||||
|
||||
dts_timing =
|
||||
(struct rk3328_ddr_dts_config_timing *)(timing +
|
||||
DTS_PAR_OFFSET / 4);
|
||||
|
||||
np_tim = of_parse_phandle(np, "ddr_timing", 0);
|
||||
if (!np_tim) {
|
||||
ret = -EINVAL;
|
||||
goto end;
|
||||
}
|
||||
de_skew = kmalloc(sizeof(*de_skew), GFP_KERNEL);
|
||||
if (!de_skew) {
|
||||
ret = -ENOMEM;
|
||||
goto end;
|
||||
}
|
||||
|
||||
p = (u32 *)dts_timing;
|
||||
for (i = 0; i < ARRAY_SIZE(rk3328_dts_timing); i++) {
|
||||
ret |= of_property_read_u32(np_tim, rk3328_dts_timing[i],
|
||||
p + i);
|
||||
}
|
||||
p = (u32 *)de_skew->ca_de_skew;
|
||||
for (i = 0; i < ARRAY_SIZE(rk3328_dts_ca_timing); i++) {
|
||||
ret |= of_property_read_u32(np_tim, rk3328_dts_ca_timing[i],
|
||||
p + i);
|
||||
}
|
||||
p = (u32 *)de_skew->cs0_de_skew;
|
||||
for (i = 0; i < ARRAY_SIZE(rk3328_dts_cs0_timing); i++) {
|
||||
ret |= of_property_read_u32(np_tim, rk3328_dts_cs0_timing[i],
|
||||
p + i);
|
||||
}
|
||||
p = (u32 *)de_skew->cs1_de_skew;
|
||||
for (i = 0; i < ARRAY_SIZE(rk3328_dts_cs1_timing); i++) {
|
||||
ret |= of_property_read_u32(np_tim, rk3328_dts_cs1_timing[i],
|
||||
p + i);
|
||||
}
|
||||
if (!ret)
|
||||
rk3328_de_skew_setting_2_register(de_skew, dts_timing);
|
||||
|
||||
kfree(de_skew);
|
||||
end:
|
||||
if (!ret) {
|
||||
dts_timing->available = 1;
|
||||
} else {
|
||||
dts_timing->available = 0;
|
||||
dev_err(dev, "of_get_ddr_timings: fail\n");
|
||||
}
|
||||
|
||||
of_node_put(np_tim);
|
||||
}
|
||||
|
||||
static int rockchip_ddr_set_auto_self_refresh(uint32_t en)
|
||||
{
|
||||
struct arm_smccc_res res;
|
||||
|
||||
ddr_psci_param->sr_idle_en = en;
|
||||
|
||||
arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
|
||||
SHARE_PAGE_TYPE_DDR, 0, ROCKCHIP_SIP_CONFIG_DRAM_SET_AT_SR,
|
||||
0, 0, 0, 0, &res);
|
||||
|
||||
return res.a0;
|
||||
}
|
||||
|
||||
static int rk3328_dmc_init(struct platform_device *pdev,
|
||||
struct rk3328_dmcfreq *dmcfreq)
|
||||
{
|
||||
struct arm_smccc_res res;
|
||||
u32 size, page_num;
|
||||
|
||||
arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
|
||||
0, 0, ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION,
|
||||
0, 0, 0, 0, &res);
|
||||
if (res.a0 || (res.a1 < 0x101)) {
|
||||
dev_err(&pdev->dev,
|
||||
"trusted firmware need to update or is invalid\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
dev_notice(&pdev->dev, "current ATF version 0x%lx\n", res.a1);
|
||||
|
||||
/*
|
||||
* first 4KB is used for interface parameters
|
||||
* after 4KB * N is dts parameters
|
||||
*/
|
||||
size = sizeof(struct rk3328_ddr_dts_config_timing);
|
||||
page_num = DIV_ROUND_UP(size, 4096) + 1;
|
||||
|
||||
arm_smccc_smc(ROCKCHIP_SIP_SHARE_MEM,
|
||||
page_num, SHARE_PAGE_TYPE_DDR, 0,
|
||||
0, 0, 0, 0, &res);
|
||||
if (res.a0 != 0) {
|
||||
dev_err(&pdev->dev, "no ATF memory for init\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ddr_psci_param = ioremap(res.a1, page_num << 12);
|
||||
of_get_rk3328_timings(&pdev->dev, pdev->dev.of_node,
|
||||
(uint32_t *)ddr_psci_param);
|
||||
|
||||
arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ,
|
||||
SHARE_PAGE_TYPE_DDR, 0, ROCKCHIP_SIP_CONFIG_DRAM_INIT,
|
||||
0, 0, 0, 0, &res);
|
||||
if (res.a0) {
|
||||
dev_err(&pdev->dev, "Rockchip dram init error %lx\n", res.a0);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
dmcfreq->set_auto_self_refresh = rockchip_ddr_set_auto_self_refresh;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk3328_dmcfreq_target(struct device *dev, unsigned long *freq,
|
||||
u32 flags)
|
||||
{
|
||||
struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);
|
||||
struct dev_pm_opp *opp;
|
||||
unsigned long old_clk_rate = dmcfreq->rate;
|
||||
unsigned long target_volt, target_rate;
|
||||
int err;
|
||||
|
||||
opp = devfreq_recommended_opp(dev, freq, flags);
|
||||
if (IS_ERR(opp))
|
||||
return PTR_ERR(opp);
|
||||
|
||||
target_rate = dev_pm_opp_get_freq(opp);
|
||||
target_volt = dev_pm_opp_get_voltage(opp);
|
||||
dev_pm_opp_put(opp);
|
||||
|
||||
if (dmcfreq->rate == target_rate)
|
||||
return 0;
|
||||
|
||||
mutex_lock(&dmcfreq->lock);
|
||||
|
||||
/*
|
||||
* If frequency scaling from low to high, adjust voltage first.
|
||||
* If frequency scaling from high to low, adjust frequency first.
|
||||
*/
|
||||
if (old_clk_rate < target_rate) {
|
||||
err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
|
||||
target_volt);
|
||||
if (err) {
|
||||
dev_err(dev, "Cannot set voltage %lu uV\n",
|
||||
target_volt);
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
|
||||
if (err) {
|
||||
dev_err(dev, "Cannot set frequency %lu (%d)\n", target_rate,
|
||||
err);
|
||||
regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
|
||||
dmcfreq->volt);
|
||||
goto out;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check the dpll rate,
|
||||
* There only two result we will get,
|
||||
* 1. Ddr frequency scaling fail, we still get the old rate.
|
||||
* 2. Ddr frequency scaling sucessful, we get the rate we set.
|
||||
*/
|
||||
dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
|
||||
|
||||
/* If get the incorrect rate, set voltage to old value. */
|
||||
if (dmcfreq->rate != target_rate) {
|
||||
dev_err(dev, "Got wrong frequency, Request %lu, Current %lu\n",
|
||||
target_rate, dmcfreq->rate);
|
||||
regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
|
||||
dmcfreq->volt);
|
||||
goto out;
|
||||
} else if (old_clk_rate > target_rate)
|
||||
err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
|
||||
target_volt);
|
||||
if (err)
|
||||
dev_err(dev, "Cannot set voltage %lu uV\n", target_volt);
|
||||
|
||||
dmcfreq->rate = target_rate;
|
||||
dmcfreq->volt = target_volt;
|
||||
|
||||
out:
|
||||
mutex_unlock(&dmcfreq->lock);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int rk3328_dmcfreq_get_dev_status(struct device *dev,
|
||||
struct devfreq_dev_status *stat)
|
||||
{
|
||||
struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);
|
||||
struct devfreq_event_data edata;
|
||||
int ret = 0;
|
||||
|
||||
ret = devfreq_event_get_event(dmcfreq->edev, &edata);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
stat->current_frequency = dmcfreq->rate;
|
||||
stat->busy_time = edata.load_count;
|
||||
stat->total_time = edata.total_count;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rk3328_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq)
|
||||
{
|
||||
struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);
|
||||
|
||||
*freq = dmcfreq->rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct devfreq_dev_profile rk3328_devfreq_dmc_profile = {
|
||||
.polling_ms = 200,
|
||||
.target = rk3328_dmcfreq_target,
|
||||
.get_dev_status = rk3328_dmcfreq_get_dev_status,
|
||||
.get_cur_freq = rk3328_dmcfreq_get_cur_freq,
|
||||
};
|
||||
|
||||
static __maybe_unused int rk3328_dmcfreq_suspend(struct device *dev)
|
||||
{
|
||||
struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);
|
||||
int ret = 0;
|
||||
|
||||
ret = devfreq_event_disable_edev(dmcfreq->edev);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to disable the devfreq-event devices\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devfreq_suspend_device(dmcfreq->devfreq);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to suspend the devfreq devices\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static __maybe_unused int rk3328_dmcfreq_resume(struct device *dev)
|
||||
{
|
||||
struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(dev);
|
||||
int ret = 0;
|
||||
|
||||
ret = devfreq_event_enable_edev(dmcfreq->edev);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to enable the devfreq-event devices\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devfreq_resume_device(dmcfreq->devfreq);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to resume the devfreq devices\n");
|
||||
return ret;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(rk3328_dmcfreq_pm, rk3328_dmcfreq_suspend,
|
||||
rk3328_dmcfreq_resume);
|
||||
|
||||
static int rk3328_dmcfreq_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct rk3328_dmcfreq *data;
|
||||
struct dev_pm_opp *opp;
|
||||
int ret;
|
||||
|
||||
data = devm_kzalloc(dev, sizeof(struct rk3328_dmcfreq), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
mutex_init(&data->lock);
|
||||
|
||||
data->vdd_center = devm_regulator_get(dev, "center");
|
||||
if (IS_ERR(data->vdd_center)) {
|
||||
if (PTR_ERR(data->vdd_center) == -EPROBE_DEFER)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
dev_err(dev, "Cannot get the regulator \"center\"\n");
|
||||
return PTR_ERR(data->vdd_center);
|
||||
}
|
||||
|
||||
data->dmc_clk = devm_clk_get(dev, "dmc_clk");
|
||||
if (IS_ERR(data->dmc_clk)) {
|
||||
if (PTR_ERR(data->dmc_clk) == -EPROBE_DEFER)
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
dev_err(dev, "Cannot get the clk dmc_clk\n");
|
||||
return PTR_ERR(data->dmc_clk);
|
||||
}
|
||||
|
||||
#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 9, 0)
|
||||
data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
|
||||
#else
|
||||
data->edev = devfreq_event_get_edev_by_phandle(dev, "devfreq-events", 0);
|
||||
#endif
|
||||
if (IS_ERR(data->edev))
|
||||
return -EPROBE_DEFER;
|
||||
|
||||
ret = devfreq_event_enable_edev(data->edev);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to enable devfreq-event devices\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = rk3328_dmc_init(pdev, data);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/*
|
||||
* We add a devfreq driver to our parent since it has a device tree node
|
||||
* with operating points.
|
||||
*/
|
||||
if (dev_pm_opp_of_add_table(dev)) {
|
||||
dev_err(dev, "Invalid operating-points in device tree.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
of_property_read_u32(np, "upthreshold",
|
||||
&data->ondemand_data.upthreshold);
|
||||
of_property_read_u32(np, "downdifferential",
|
||||
&data->ondemand_data.downdifferential);
|
||||
|
||||
data->rate = clk_get_rate(data->dmc_clk);
|
||||
|
||||
opp = devfreq_recommended_opp(dev, &data->rate, 0);
|
||||
if (IS_ERR(opp)) {
|
||||
ret = PTR_ERR(opp);
|
||||
goto err_free_opp;
|
||||
}
|
||||
|
||||
data->rate = dev_pm_opp_get_freq(opp);
|
||||
data->volt = dev_pm_opp_get_voltage(opp);
|
||||
dev_pm_opp_put(opp);
|
||||
|
||||
rk3328_devfreq_dmc_profile.initial_freq = data->rate;
|
||||
|
||||
data->devfreq = devm_devfreq_add_device(dev,
|
||||
&rk3328_devfreq_dmc_profile,
|
||||
DEVFREQ_GOV_SIMPLE_ONDEMAND,
|
||||
&data->ondemand_data);
|
||||
if (IS_ERR(data->devfreq)) {
|
||||
ret = PTR_ERR(data->devfreq);
|
||||
goto err_free_opp;
|
||||
}
|
||||
|
||||
devm_devfreq_register_opp_notifier(dev, data->devfreq);
|
||||
|
||||
data->dev = dev;
|
||||
platform_set_drvdata(pdev, data);
|
||||
|
||||
return 0;
|
||||
|
||||
err_free_opp:
|
||||
dev_pm_opp_of_remove_table(&pdev->dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rk3328_dmcfreq_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct rk3328_dmcfreq *dmcfreq = dev_get_drvdata(&pdev->dev);
|
||||
|
||||
/*
|
||||
* Before remove the opp table we need to unregister the opp notifier.
|
||||
*/
|
||||
devm_devfreq_unregister_opp_notifier(dmcfreq->dev, dmcfreq->devfreq);
|
||||
dev_pm_opp_of_remove_table(dmcfreq->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id rk3328dmc_devfreq_of_match[] = {
|
||||
{ .compatible = "rockchip,rk3328-dmc" },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rk3328dmc_devfreq_of_match);
|
||||
|
||||
static struct platform_driver rk3328_dmcfreq_driver = {
|
||||
.probe = rk3328_dmcfreq_probe,
|
||||
.remove = rk3328_dmcfreq_remove,
|
||||
.driver = {
|
||||
.name = "rk3328-dmc-freq",
|
||||
.pm = &rk3328_dmcfreq_pm,
|
||||
.of_match_table = rk3328dmc_devfreq_of_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(rk3328_dmcfreq_driver);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
|
||||
MODULE_DESCRIPTION("RK3328 dmcfreq driver with devfreq framework");
|
||||
|
|
@ -1,63 +0,0 @@
|
|||
/*
|
||||
*
|
||||
* Copyright (C) 2017 ROCKCHIP, Inc.
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H
|
||||
#define _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H
|
||||
|
||||
#define DDR2_DEFAULT (0)
|
||||
|
||||
#define DDR3_800D (0) /* 5-5-5 */
|
||||
#define DDR3_800E (1) /* 6-6-6 */
|
||||
#define DDR3_1066E (2) /* 6-6-6 */
|
||||
#define DDR3_1066F (3) /* 7-7-7 */
|
||||
#define DDR3_1066G (4) /* 8-8-8 */
|
||||
#define DDR3_1333F (5) /* 7-7-7 */
|
||||
#define DDR3_1333G (6) /* 8-8-8 */
|
||||
#define DDR3_1333H (7) /* 9-9-9 */
|
||||
#define DDR3_1333J (8) /* 10-10-10 */
|
||||
#define DDR3_1600G (9) /* 8-8-8 */
|
||||
#define DDR3_1600H (10) /* 9-9-9 */
|
||||
#define DDR3_1600J (11) /* 10-10-10 */
|
||||
#define DDR3_1600K (12) /* 11-11-11 */
|
||||
#define DDR3_1866J (13) /* 10-10-10 */
|
||||
#define DDR3_1866K (14) /* 11-11-11 */
|
||||
#define DDR3_1866L (15) /* 12-12-12 */
|
||||
#define DDR3_1866M (16) /* 13-13-13 */
|
||||
#define DDR3_2133K (17) /* 11-11-11 */
|
||||
#define DDR3_2133L (18) /* 12-12-12 */
|
||||
#define DDR3_2133M (19) /* 13-13-13 */
|
||||
#define DDR3_2133N (20) /* 14-14-14 */
|
||||
#define DDR3_DEFAULT (21)
|
||||
#define DDR_DDR2 (22)
|
||||
#define DDR_LPDDR (23)
|
||||
#define DDR_LPDDR2 (24)
|
||||
|
||||
#define DDR4_1600J (0) /* 10-10-10 */
|
||||
#define DDR4_1600K (1) /* 11-11-11 */
|
||||
#define DDR4_1600L (2) /* 12-12-12 */
|
||||
#define DDR4_1866L (3) /* 12-12-12 */
|
||||
#define DDR4_1866M (4) /* 13-13-13 */
|
||||
#define DDR4_1866N (5) /* 14-14-14 */
|
||||
#define DDR4_2133N (6) /* 14-14-14 */
|
||||
#define DDR4_2133P (7) /* 15-15-15 */
|
||||
#define DDR4_2133R (8) /* 16-16-16 */
|
||||
#define DDR4_2400P (9) /* 15-15-15 */
|
||||
#define DDR4_2400R (10) /* 16-16-16 */
|
||||
#define DDR4_2400U (11) /* 18-18-18 */
|
||||
#define DDR4_DEFAULT (12)
|
||||
|
||||
#define PAUSE_CPU_STACK_SIZE 16
|
||||
|
||||
#endif
|
||||
|
|
@ -1,159 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H
|
||||
#define _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H
|
||||
|
||||
#define DDR3_DS_34ohm (34)
|
||||
#define DDR3_DS_40ohm (40)
|
||||
|
||||
#define DDR3_ODT_DIS (0)
|
||||
#define DDR3_ODT_40ohm (40)
|
||||
#define DDR3_ODT_60ohm (60)
|
||||
#define DDR3_ODT_120ohm (120)
|
||||
|
||||
#define LP2_DS_34ohm (34)
|
||||
#define LP2_DS_40ohm (40)
|
||||
#define LP2_DS_48ohm (48)
|
||||
#define LP2_DS_60ohm (60)
|
||||
#define LP2_DS_68_6ohm (68) /* optional */
|
||||
#define LP2_DS_80ohm (80)
|
||||
#define LP2_DS_120ohm (120) /* optional */
|
||||
|
||||
#define LP3_DS_34ohm (34)
|
||||
#define LP3_DS_40ohm (40)
|
||||
#define LP3_DS_48ohm (48)
|
||||
#define LP3_DS_60ohm (60)
|
||||
#define LP3_DS_80ohm (80)
|
||||
#define LP3_DS_34D_40U (3440)
|
||||
#define LP3_DS_40D_48U (4048)
|
||||
#define LP3_DS_34D_48U (3448)
|
||||
|
||||
#define LP3_ODT_DIS (0)
|
||||
#define LP3_ODT_60ohm (60)
|
||||
#define LP3_ODT_120ohm (120)
|
||||
#define LP3_ODT_240ohm (240)
|
||||
|
||||
#define LP4_PDDS_40ohm (40)
|
||||
#define LP4_PDDS_48ohm (48)
|
||||
#define LP4_PDDS_60ohm (60)
|
||||
#define LP4_PDDS_80ohm (80)
|
||||
#define LP4_PDDS_120ohm (120)
|
||||
#define LP4_PDDS_240ohm (240)
|
||||
|
||||
#define LP4_DQ_ODT_40ohm (40)
|
||||
#define LP4_DQ_ODT_48ohm (48)
|
||||
#define LP4_DQ_ODT_60ohm (60)
|
||||
#define LP4_DQ_ODT_80ohm (80)
|
||||
#define LP4_DQ_ODT_120ohm (120)
|
||||
#define LP4_DQ_ODT_240ohm (240)
|
||||
#define LP4_DQ_ODT_DIS (0)
|
||||
|
||||
#define LP4_CA_ODT_40ohm (40)
|
||||
#define LP4_CA_ODT_48ohm (48)
|
||||
#define LP4_CA_ODT_60ohm (60)
|
||||
#define LP4_CA_ODT_80ohm (80)
|
||||
#define LP4_CA_ODT_120ohm (120)
|
||||
#define LP4_CA_ODT_240ohm (240)
|
||||
#define LP4_CA_ODT_DIS (0)
|
||||
|
||||
#define DDR4_DS_34ohm (34)
|
||||
#define DDR4_DS_48ohm (48)
|
||||
#define DDR4_RTT_NOM_DIS (0)
|
||||
#define DDR4_RTT_NOM_60ohm (60)
|
||||
#define DDR4_RTT_NOM_120ohm (120)
|
||||
#define DDR4_RTT_NOM_40ohm (40)
|
||||
#define DDR4_RTT_NOM_240ohm (240)
|
||||
#define DDR4_RTT_NOM_48ohm (48)
|
||||
#define DDR4_RTT_NOM_80ohm (80)
|
||||
#define DDR4_RTT_NOM_34ohm (34)
|
||||
|
||||
#define PHY_DDR3_RON_RTT_DISABLE (0)
|
||||
#define PHY_DDR3_RON_RTT_451ohm (1)
|
||||
#define PHY_DDR3_RON_RTT_225ohm (2)
|
||||
#define PHY_DDR3_RON_RTT_150ohm (3)
|
||||
#define PHY_DDR3_RON_RTT_112ohm (4)
|
||||
#define PHY_DDR3_RON_RTT_90ohm (5)
|
||||
#define PHY_DDR3_RON_RTT_75ohm (6)
|
||||
#define PHY_DDR3_RON_RTT_64ohm (7)
|
||||
#define PHY_DDR3_RON_RTT_56ohm (16)
|
||||
#define PHY_DDR3_RON_RTT_50ohm (17)
|
||||
#define PHY_DDR3_RON_RTT_45ohm (18)
|
||||
#define PHY_DDR3_RON_RTT_41ohm (19)
|
||||
#define PHY_DDR3_RON_RTT_37ohm (20)
|
||||
#define PHY_DDR3_RON_RTT_34ohm (21)
|
||||
#define PHY_DDR3_RON_RTT_33ohm (22)
|
||||
#define PHY_DDR3_RON_RTT_30ohm (23)
|
||||
#define PHY_DDR3_RON_RTT_28ohm (24)
|
||||
#define PHY_DDR3_RON_RTT_26ohm (25)
|
||||
#define PHY_DDR3_RON_RTT_25ohm (26)
|
||||
#define PHY_DDR3_RON_RTT_23ohm (27)
|
||||
#define PHY_DDR3_RON_RTT_22ohm (28)
|
||||
#define PHY_DDR3_RON_RTT_21ohm (29)
|
||||
#define PHY_DDR3_RON_RTT_20ohm (30)
|
||||
#define PHY_DDR3_RON_RTT_19ohm (31)
|
||||
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_480ohm (1)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_240ohm (2)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_160ohm (3)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_120ohm (4)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_96ohm (5)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_80ohm (6)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_68ohm (7)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_60ohm (16)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_53ohm (17)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_48ohm (18)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_43ohm (19)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_40ohm (20)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_37ohm (21)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_34ohm (22)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_32ohm (23)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_30ohm (24)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_28ohm (25)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_26ohm (26)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_25ohm (27)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_24ohm (28)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_22ohm (29)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_21ohm (30)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_20ohm (31)
|
||||
|
||||
#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H*/
|
||||
|
|
@ -1,82 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
include $(TOPDIR)/rules.mk
|
||||
include $(INCLUDE_DIR)/image.mk
|
||||
|
||||
DEVICE_VARS += UBOOT_DEVICE_NAME
|
||||
|
||||
define Build/Compile
|
||||
$(CP) $(LINUX_DIR)/COPYING $(KDIR)/COPYING.linux
|
||||
endef
|
||||
|
||||
### Image scripts ###
|
||||
define Build/boot-common
|
||||
# This creates a new folder copies the dtb (as rockchip.dtb)
|
||||
# and the kernel image (as kernel.img)
|
||||
rm -fR $@.boot
|
||||
mkdir -p $@.boot
|
||||
|
||||
$(CP) $(DTS_DIR)/$(DEVICE_DTS).dtb $@.boot/rockchip.dtb
|
||||
$(CP) $(IMAGE_KERNEL) $@.boot/kernel.img
|
||||
endef
|
||||
|
||||
define Build/boot-script
|
||||
# Make an U-boot image and copy it to the boot partition
|
||||
mkimage -A arm -O linux -T script -C none -a 0 -e 0 -d $(if $(1),$(1),mmc).bootscript $@.boot/boot.scr
|
||||
endef
|
||||
|
||||
define Build/pine64-img
|
||||
# Creates the final SD/eMMC images,
|
||||
# combining boot partition, root partition as well as the u-boot bootloader
|
||||
|
||||
# Generate a new partition table in $@ with 32 MiB of
|
||||
# alignment padding for the idbloader and u-boot to fit:
|
||||
# http://opensource.rock-chips.com/wiki_Boot_option#Boot_flow
|
||||
#
|
||||
# U-Boot SPL expects the U-Boot ITB to be located at sector 0x4000 (8 MiB) on the MMC storage
|
||||
PADDING=1 $(SCRIPT_DIR)/gen_image_generic.sh \
|
||||
$@ \
|
||||
$(CONFIG_TARGET_KERNEL_PARTSIZE) $@.boot \
|
||||
$(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS) \
|
||||
32768
|
||||
|
||||
# Copy the idbloader and the u-boot image to the image at sector 0x40 and 0x4000
|
||||
dd if="$(STAGING_DIR_IMAGE)"/$(UBOOT_DEVICE_NAME)-idbloader.img of="$@" seek=64 conv=notrunc
|
||||
dd if="$(STAGING_DIR_IMAGE)"/$(UBOOT_DEVICE_NAME)-u-boot.itb of="$@" seek=16384 conv=notrunc
|
||||
endef
|
||||
|
||||
define Build/pine64-bin
|
||||
# Typical Rockchip boot flow with Rockchip miniloader
|
||||
# Rockchp idbLoader which is combinded by Rockchip ddr init bin
|
||||
# and miniloader bin from Rockchip rkbin project
|
||||
|
||||
# Generate a new partition table in $@ with 32 MiB of alignment
|
||||
# padding for the idbloader, uboot and trust image to fit:
|
||||
# http://opensource.rock-chips.com/wiki_Boot_option#Boot_flow
|
||||
PADDING=1 $(SCRIPT_DIR)/gen_image_generic.sh \
|
||||
$@ \
|
||||
$(CONFIG_TARGET_KERNEL_PARTSIZE) $@.boot \
|
||||
$(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS) \
|
||||
32768
|
||||
|
||||
# Copy the idbloader, uboot and trust image to the image at sector 0x40, 0x4000 and 0x6000
|
||||
dd if="$(STAGING_DIR_IMAGE)"/$(SOC)-idbloader.bin of="$@" seek=64 conv=notrunc
|
||||
dd if="$(STAGING_DIR_IMAGE)"/$(UBOOT_DEVICE_NAME)-uboot.img of="$@" seek=16384 conv=notrunc
|
||||
dd if="$(STAGING_DIR_IMAGE)"/$(SOC)-trust.bin of="$@" seek=24576 conv=notrunc
|
||||
endef
|
||||
|
||||
### Devices ###
|
||||
define Device/Default
|
||||
PROFILES := Default
|
||||
KERNEL := kernel-bin
|
||||
IMAGES := sysupgrade.img.gz
|
||||
DEVICE_DTS = rockchip/$$(SOC)-$(lastword $(subst _, ,$(1)))
|
||||
endef
|
||||
|
||||
ifdef CONFIG_LINUX_6_1
|
||||
DTS_CPPFLAGS += -DDTS_NO_LEGACY
|
||||
endif
|
||||
|
||||
include $(SUBTARGET).mk
|
||||
|
||||
$(eval $(call BuildImage))
|
||||
|
|
@ -1,273 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
#
|
||||
# Copyright (C) 2020 Tobias Maedel
|
||||
|
||||
define Device/ariaboard_photonicat
|
||||
DEVICE_VENDOR := Ariaboard
|
||||
DEVICE_MODEL := Photonicat
|
||||
SOC := rk3568
|
||||
UBOOT_DEVICE_NAME := photonicat-rk3568
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := ath10k-firmware-qca9377-sdio kmod-ath10k kmod-ath10k-sdio pcat-manager
|
||||
endef
|
||||
TARGET_DEVICES += ariaboard_photonicat
|
||||
|
||||
define Device/dilusense_dlfr100
|
||||
DEVICE_VENDOR := Dilusense
|
||||
DEVICE_MODEL := DLFR100
|
||||
SOC := rk3399
|
||||
UBOOT_DEVICE_NAME := dilusense-dlfr100-rk3399
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-bin | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-r8168 -urngd
|
||||
endef
|
||||
TARGET_DEVICES += dilusense_dlfr100
|
||||
|
||||
define Device/ezpro_mrkaio-m68s
|
||||
DEVICE_VENDOR := EZPRO
|
||||
DEVICE_MODEL := Mrkaio M68S
|
||||
SOC := rk3568
|
||||
UBOOT_DEVICE_NAME := mrkaio-m68s-rk3568
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-ata-ahci kmod-ata-ahci-platform
|
||||
endef
|
||||
TARGET_DEVICES += ezpro_mrkaio-m68s
|
||||
|
||||
define Device/ezpro_mrkaio-m68s-plus
|
||||
DEVICE_VENDOR := EZPRO
|
||||
DEVICE_MODEL := Mrkaio M68S PLUS
|
||||
SOC := rk3568
|
||||
UBOOT_DEVICE_NAME := mrkaio-m68s-rk3568
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-r8125 kmod-ata-ahci kmod-ata-ahci-platform kmod-nvme kmod-scsi-core
|
||||
endef
|
||||
TARGET_DEVICES += ezpro_mrkaio-m68s-plus
|
||||
|
||||
define Device/hinlink_common
|
||||
DEVICE_VENDOR := HINLINK
|
||||
UBOOT_DEVICE_NAME := opc-h68k-rk3568
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-ata-ahci-platform kmod-mt7921e kmod-r8125 kmod-usb-serial-cp210x wpad-openssl
|
||||
endef
|
||||
|
||||
define Device/hinlink_opc-h66k
|
||||
$(call Device/hinlink_common)
|
||||
DEVICE_MODEL := OPC-H66K
|
||||
SOC := rk3568
|
||||
endef
|
||||
TARGET_DEVICES += hinlink_opc-h66k
|
||||
|
||||
define Device/hinlink_opc-h68k
|
||||
$(call Device/hinlink_common)
|
||||
DEVICE_MODEL := OPC-H68K
|
||||
SOC := rk3568
|
||||
endef
|
||||
TARGET_DEVICES += hinlink_opc-h68k
|
||||
|
||||
define Device/hinlink_opc-h69k
|
||||
$(call Device/hinlink_common)
|
||||
DEVICE_MODEL := OPC-H69K
|
||||
SOC := rk3568
|
||||
DEVICE_PACKAGES += kmod-usb-serial-option uqmi
|
||||
endef
|
||||
TARGET_DEVICES += hinlink_opc-h69k
|
||||
|
||||
define Device/fastrhino_common
|
||||
DEVICE_VENDOR := FastRhino
|
||||
SOC := rk3568
|
||||
UBOOT_DEVICE_NAME := r66s-rk3568
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-r8125
|
||||
endef
|
||||
|
||||
define Device/fastrhino_r66s
|
||||
$(call Device/fastrhino_common)
|
||||
DEVICE_MODEL := R66S
|
||||
endef
|
||||
TARGET_DEVICES += fastrhino_r66s
|
||||
|
||||
define Device/fastrhino_r68s
|
||||
$(call Device/fastrhino_common)
|
||||
DEVICE_MODEL := R68S
|
||||
endef
|
||||
TARGET_DEVICES += fastrhino_r68s
|
||||
|
||||
define Device/friendlyarm_nanopi-neo3
|
||||
DEVICE_VENDOR := FriendlyARM
|
||||
DEVICE_MODEL := NanoPi NEO3
|
||||
SOC := rk3328
|
||||
UBOOT_DEVICE_NAME := nanopi-r2s-rk3328
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-bin | gzip | append-metadata
|
||||
endef
|
||||
TARGET_DEVICES += friendlyarm_nanopi-neo3
|
||||
|
||||
define Device/friendlyarm_nanopi-r2c
|
||||
DEVICE_VENDOR := FriendlyARM
|
||||
DEVICE_MODEL := NanoPi R2C
|
||||
SOC := rk3328
|
||||
UBOOT_DEVICE_NAME := nanopi-r2c-rk3328
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-bin | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-usb-net-rtl8152
|
||||
endef
|
||||
TARGET_DEVICES += friendlyarm_nanopi-r2c
|
||||
|
||||
define Device/friendlyarm_nanopi-r2s
|
||||
DEVICE_VENDOR := FriendlyARM
|
||||
DEVICE_MODEL := NanoPi R2S
|
||||
SOC := rk3328
|
||||
UBOOT_DEVICE_NAME := nanopi-r2s-rk3328
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-bin | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-usb-net-rtl8152
|
||||
endef
|
||||
TARGET_DEVICES += friendlyarm_nanopi-r2s
|
||||
|
||||
define Device/friendlyarm_nanopi-r4s
|
||||
DEVICE_VENDOR := FriendlyARM
|
||||
DEVICE_MODEL := NanoPi R4S
|
||||
SOC := rk3399
|
||||
UBOOT_DEVICE_NAME := nanopi-r4s-rk3399
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r4s | pine64-bin | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-r8168 -urngd
|
||||
endef
|
||||
TARGET_DEVICES += friendlyarm_nanopi-r4s
|
||||
|
||||
define Device/friendlyarm_nanopi-r4se
|
||||
DEVICE_VENDOR := FriendlyARM
|
||||
DEVICE_MODEL := NanoPi R4SE
|
||||
SOC := rk3399
|
||||
UBOOT_DEVICE_NAME := nanopi-r4se-rk3399
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r4s | pine64-bin | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-r8168 -urngd
|
||||
endef
|
||||
TARGET_DEVICES += friendlyarm_nanopi-r4se
|
||||
|
||||
define Device/friendlyarm_nanopi-r5c
|
||||
DEVICE_VENDOR := FriendlyARM
|
||||
DEVICE_MODEL := NanoPi R5C
|
||||
SOC := rk3568
|
||||
UBOOT_DEVICE_NAME := nanopi-r5s-rk3568
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-r8125 kmod-nvme kmod-scsi-core
|
||||
endef
|
||||
TARGET_DEVICES += friendlyarm_nanopi-r5c
|
||||
|
||||
define Device/friendlyarm_nanopi-r5s
|
||||
DEVICE_VENDOR := FriendlyARM
|
||||
DEVICE_MODEL := NanoPi R5S
|
||||
SOC := rk3568
|
||||
UBOOT_DEVICE_NAME := nanopi-r5s-rk3568
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-r8125 kmod-nvme kmod-scsi-core
|
||||
endef
|
||||
TARGET_DEVICES += friendlyarm_nanopi-r5s
|
||||
|
||||
define Device/firefly_station-p2
|
||||
DEVICE_VENDOR := Firefly
|
||||
DEVICE_MODEL := Station P2
|
||||
DEVICE_DTS := rockchip/rk3568-roc-pc
|
||||
UBOOT_DEVICE_NAME := station-p2-rk3568
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-brcmfmac kmod-ikconfig kmod-ata-ahci-platform station-p2-firmware wpad-openssl
|
||||
endef
|
||||
TARGET_DEVICES += firefly_station-p2
|
||||
|
||||
define Device/pine64_rockpro64
|
||||
DEVICE_VENDOR := Pine64
|
||||
DEVICE_MODEL := RockPro64
|
||||
SOC := rk3399
|
||||
UBOOT_DEVICE_NAME := rockpro64-rk3399
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := -urngd
|
||||
endef
|
||||
TARGET_DEVICES += pine64_rockpro64
|
||||
|
||||
define Device/radxa_e25
|
||||
DEVICE_VENDOR := Radxa
|
||||
DEVICE_MODEL := E25
|
||||
DEVICE_DTS := rockchip/rk3568-radxa-e25
|
||||
UBOOT_DEVICE_NAME := radxa-e25-rk3568
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-ata-ahci-platform kmod-r8125
|
||||
endef
|
||||
TARGET_DEVICES += radxa_e25
|
||||
|
||||
define Device/radxa_rock-3a
|
||||
DEVICE_VENDOR := Radxa
|
||||
DEVICE_MODEL := ROCK3 A
|
||||
SOC := rk3568
|
||||
SUPPORTED_DEVICES := radxa,rock3a
|
||||
UBOOT_DEVICE_NAME := rock-3a-rk3568
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r5s | pine64-img | gzip | append-metadata
|
||||
endef
|
||||
TARGET_DEVICES += radxa_rock-3a
|
||||
|
||||
define Device/radxa_rock-pi-4
|
||||
DEVICE_VENDOR := Radxa
|
||||
DEVICE_MODEL := ROCK Pi 4
|
||||
SOC := rk3399
|
||||
SUPPORTED_DEVICES := radxa,rockpi4
|
||||
UBOOT_DEVICE_NAME := rock-pi-4-rk3399
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := -urngd
|
||||
endef
|
||||
TARGET_DEVICES += radxa_rock-pi-4
|
||||
|
||||
define Device/rongpin_king3399
|
||||
DEVICE_VENDOR := Rongpin
|
||||
DEVICE_MODEL := King3399
|
||||
SOC := rk3399
|
||||
UBOOT_DEVICE_NAME := rongpin-king3399-rk3399
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r4s | pine64-bin | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-r8168 -urngd kmod-brcmfmac cypress-firmware-4356-sdio rongpin-king3399-firmware wpad-openssl
|
||||
endef
|
||||
TARGET_DEVICES += rongpin_king3399
|
||||
|
||||
define Device/rocktech_mpc1903
|
||||
DEVICE_VENDOR := Rocktech
|
||||
DEVICE_MODEL := MPC1903
|
||||
SOC := rk3399
|
||||
SUPPORTED_DEVICES := rocktech,mpc1903
|
||||
UBOOT_DEVICE_NAME := rocktech-mpc1903-rk3399
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script | pine64-bin | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-usb-net-smsc75xx kmod-usb-serial-cp210x -urngd
|
||||
endef
|
||||
TARGET_DEVICES += rocktech_mpc1903
|
||||
|
||||
define Device/sharevdi_h3399pc
|
||||
DEVICE_VENDOR := SHAREVDI
|
||||
DEVICE_MODEL := H3399PC
|
||||
SOC := rk3399
|
||||
UBOOT_DEVICE_NAME := sharevdi-h3399pc-rk3399
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r4s | pine64-bin | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-r8168 -urngd
|
||||
endef
|
||||
TARGET_DEVICES += sharevdi_h3399pc
|
||||
|
||||
define Device/sharevdi_guangmiao-g4c
|
||||
DEVICE_VENDOR := SHAREVDI
|
||||
DEVICE_MODEL := GuangMiao G4C
|
||||
SOC := rk3399
|
||||
UBOOT_DEVICE_NAME := guangmiao-g4c-rk3399
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r4s | pine64-img | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-r8168 -urngd
|
||||
endef
|
||||
TARGET_DEVICES += sharevdi_guangmiao-g4c
|
||||
|
||||
define Device/xunlong_orangepi-r1-plus
|
||||
DEVICE_VENDOR := Xunlong
|
||||
DEVICE_MODEL := Orange Pi R1 Plus
|
||||
SOC := rk3328
|
||||
UBOOT_DEVICE_NAME := orangepi-r1-plus-rk3328
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-bin | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-usb-net-rtl8152
|
||||
endef
|
||||
TARGET_DEVICES += xunlong_orangepi-r1-plus
|
||||
|
||||
define Device/xunlong_orangepi-r1-plus-lts
|
||||
DEVICE_VENDOR := Xunlong
|
||||
DEVICE_MODEL := Orange Pi R1 Plus LTS
|
||||
SOC := rk3328
|
||||
UBOOT_DEVICE_NAME := orangepi-r1-plus-lts-rk3328
|
||||
IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-bin | gzip | append-metadata
|
||||
DEVICE_PACKAGES := kmod-usb-net-rtl8152
|
||||
endef
|
||||
TARGET_DEVICES += xunlong_orangepi-r1-plus-lts
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
part uuid mmc ${devnum}:2 uuid
|
||||
|
||||
setenv bootargs "console=ttyS2,1500000 console=tty1 earlycon=uart8250,mmio32,0xff1a0000 root=PARTUUID=${uuid} rw rootwait"
|
||||
|
||||
load mmc ${devnum}:1 ${fdt_addr_r} rockchip.dtb
|
||||
load mmc ${devnum}:1 ${kernel_addr_r} kernel.img
|
||||
|
||||
booti ${kernel_addr_r} - ${fdt_addr_r}
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
part uuid mmc ${devnum}:2 uuid
|
||||
|
||||
setenv bootargs "console=ttyS2,1500000 earlycon=uart8250,mmio32,0xff130000 root=PARTUUID=${uuid} rw rootwait"
|
||||
|
||||
load mmc ${devnum}:1 ${fdt_addr_r} rockchip.dtb
|
||||
load mmc ${devnum}:1 ${kernel_addr_r} kernel.img
|
||||
|
||||
booti ${kernel_addr_r} - ${fdt_addr_r}
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
part uuid mmc ${devnum}:2 uuid
|
||||
|
||||
setenv bootargs "console=ttyS2,1500000 earlycon=uart8250,mmio32,0xff1a0000 root=PARTUUID=${uuid} rw rootwait"
|
||||
|
||||
load mmc ${devnum}:1 ${fdt_addr_r} rockchip.dtb
|
||||
load mmc ${devnum}:1 ${kernel_addr_r} kernel.img
|
||||
|
||||
booti ${kernel_addr_r} - ${fdt_addr_r}
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
part uuid mmc ${devnum}:2 uuid
|
||||
|
||||
setenv bootargs "console=ttyS2,1500000 earlycon=uart8250,mmio32,0xfe660000 root=PARTUUID=${uuid} rw rootwait"
|
||||
|
||||
load mmc ${devnum}:1 ${fdt_addr_r} rockchip.dtb
|
||||
load mmc ${devnum}:1 ${kernel_addr_r} kernel.img
|
||||
|
||||
booti ${kernel_addr_r} - ${fdt_addr_r}
|
||||
|
|
@ -1,70 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
#
|
||||
# Copyright (C) 2020 OpenWrt.org
|
||||
|
||||
define KernelPackage/drm-rockchip
|
||||
SUBMENU:=$(VIDEO_MENU)
|
||||
TITLE:=Rockchip DRM support
|
||||
DEPENDS:=@TARGET_rockchip +kmod-backlight +kmod-drm-kms-helper \
|
||||
+kmod-multimedia-input +LINUX_6_1:kmod-drm-display-helper
|
||||
KCONFIG:= \
|
||||
CONFIG_DRM_ROCKCHIP \
|
||||
CONFIG_DRM_LOAD_EDID_FIRMWARE=y \
|
||||
CONFIG_DRM_FBDEV_EMULATION=y \
|
||||
CONFIG_DRM_FBDEV_OVERALLOC=100 \
|
||||
CONFIG_DRM_BRIDGE=y \
|
||||
CONFIG_HDMI=y \
|
||||
CONFIG_PHY_ROCKCHIP_INNO_HDMI \
|
||||
CONFIG_DRM_DW_HDMI \
|
||||
CONFIG_DRM_DW_HDMI_CEC \
|
||||
CONFIG_ROCKCHIP_ANALOGIX_DP=n \
|
||||
CONFIG_ROCKCHIP_CDN_DP=n \
|
||||
CONFIG_ROCKCHIP_DW_HDMI=y \
|
||||
CONFIG_ROCKCHIP_DW_MIPI_DSI=y \
|
||||
CONFIG_ROCKCHIP_INNO_HDMI=y \
|
||||
CONFIG_ROCKCHIP_LVDS=y \
|
||||
CONFIG_ROCKCHIP_RGB=n \
|
||||
CONFIG_ROCKCHIP_RK3066_HDMI=n \
|
||||
CONFIG_ROCKCHIP_VOP=y \
|
||||
CONFIG_ROCKCHIP_VOP2=y \
|
||||
CONFIG_DRM_GEM_CMA_HELPER@lt6.1 \
|
||||
CONFIG_DRM_GEM_DMA_HELPER@ge6.1 \
|
||||
CONFIG_DRM_PANEL=y \
|
||||
CONFIG_DRM_PANEL_BRIDGE=y \
|
||||
CONFIG_DRM_PANEL_SIMPLE
|
||||
FILES:= \
|
||||
$(LINUX_DIR)/drivers/gpu/drm/bridge/synopsys/dw-hdmi.ko \
|
||||
$(LINUX_DIR)/drivers/gpu/drm/bridge/synopsys/dw-hdmi-cec.ko \
|
||||
$(LINUX_DIR)/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.ko \
|
||||
$(LINUX_DIR)/drivers/phy/rockchip/phy-rockchip-inno-hdmi.ko \
|
||||
$(LINUX_DIR)/drivers/gpu/drm/drm_dp_aux_bus.ko@lt5.19 \
|
||||
$(LINUX_DIR)/drivers/gpu/drm/drm_dma_helper.ko@ge6.1 \
|
||||
$(LINUX_DIR)/drivers/gpu/drm/panel/panel-simple.ko \
|
||||
$(LINUX_DIR)/drivers/gpu/drm/rockchip/rockchipdrm.ko \
|
||||
$(LINUX_DIR)/drivers/media/cec/core/cec.ko
|
||||
AUTOLOAD:=$(call AutoProbe,rockchipdrm phy-rockchip-inno-hdmi dw-hdmi-cec)
|
||||
endef
|
||||
|
||||
define KernelPackage/drm-rockchip/description
|
||||
Direct Rendering Manager (DRM) support for Rockchip
|
||||
endef
|
||||
|
||||
$(eval $(call KernelPackage,drm-rockchip))
|
||||
|
||||
define KernelPackage/saradc-rockchip
|
||||
SUBMENU:=$(IIO_MENU)
|
||||
TITLE:=Rockchip SARADC support
|
||||
DEPENDS:=@TARGET_rockchip +kmod-industrialio-triggered-buffer
|
||||
KCONFIG:= \
|
||||
CONFIG_RESET_CONTROLLER=y \
|
||||
CONFIG_ROCKCHIP_SARADC
|
||||
FILES:= \
|
||||
$(LINUX_DIR)/drivers/iio/adc/rockchip_saradc.ko
|
||||
AUTOLOAD:=$(call AutoProbe,rockchip_saradc)
|
||||
endef
|
||||
|
||||
define KernelPackage/saradc-rockchip/description
|
||||
Support for the SARADC found in SoCs from Rockchip
|
||||
endef
|
||||
|
||||
$(eval $(call KernelPackage,saradc-rockchip))
|
||||
|
|
@ -1,35 +0,0 @@
|
|||
From 2076121eecc18fa31ae749c6ddc5648be96f0b5e Mon Sep 17 00:00:00 2001
|
||||
From: Simon Xue <xxm@rock-chips.com>
|
||||
Date: Mon, 5 Jul 2021 09:26:10 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: add saradc node for rk3568
|
||||
|
||||
Add the core dt-node for the rk3568's saradc.
|
||||
|
||||
Signed-off-by: Simon Xue <xxm@rock-chips.com>
|
||||
Link: https://lore.kernel.org/r/20210705012610.3831-1-xxm@rock-chips.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 12 ++++++++++++
|
||||
1 file changed, 12 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
@@ -754,6 +754,18 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ saradc: saradc@fe720000 {
|
||||
+ compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
|
||||
+ reg = <0x0 0xfe720000 0x0 0x100>;
|
||||
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
|
||||
+ clock-names = "saradc", "apb_pclk";
|
||||
+ resets = <&cru SRST_P_SARADC>;
|
||||
+ reset-names = "saradc-apb";
|
||||
+ #io-channel-cells = <1>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
pinctrl: pinctrl {
|
||||
compatible = "rockchip,rk3568-pinctrl";
|
||||
rockchip,grf = <&grf>;
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
From bc6c96d850419e71dbc9b0094ccc9b668ba9be43 Mon Sep 17 00:00:00 2001
|
||||
From: David Bauer <mail@david-bauer.net>
|
||||
Date: Mon, 28 Sep 2020 22:54:52 +0200
|
||||
Subject: [PATCH] rockchip: rk3328: add compatible to NanoPi R2S ethernet PHY
|
||||
|
||||
This adds the compatible property to the NanoPi R2S ethernet PHY node.
|
||||
Otherwise, the PHY might not be probed, as the PHY ID reads all 0xff
|
||||
when it is still in reset.
|
||||
|
||||
Signed-off-by: David Bauer <mail@david-bauer.net>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
|
||||
@@ -156,6 +156,8 @@
|
||||
#size-cells = <0>;
|
||||
|
||||
rtl8211e: ethernet-phy@1 {
|
||||
+ compatible = "ethernet-phy-id001c.c915",
|
||||
+ "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
pinctrl-0 = <ð_phy_reset_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
|
@ -1,35 +0,0 @@
|
|||
From 43f3999d1836117ab2e601aec9a9e6f292ce4958 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Mon, 7 Jun 2021 15:45:37 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: add EEPROM node for NanoPi R4S
|
||||
|
||||
NanoPi R4S has a EEPROM attached to the 2nd I2C bus (U92), which
|
||||
stores the MAC address.
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
---
|
||||
.../boot/dts/rockchip/rk3399-nanopi-r4s.dts | 18 ++++++++++++++++++
|
||||
1 file changed, 18 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
|
||||
@@ -68,6 +68,19 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+&i2c2 {
|
||||
+ eeprom@51 {
|
||||
+ compatible = "microchip,24c02", "atmel,24c02";
|
||||
+ reg = <0x51>;
|
||||
+ pagesize = <16>;
|
||||
+ size = <256>;
|
||||
+
|
||||
+ mac_address: mac-address@fa {
|
||||
+ reg = <0xfa 0x06>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
&i2c4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1,28 +0,0 @@
|
|||
From 02832ed8ae2c8b130efea4e43d3ecac50b4b7933 Mon Sep 17 00:00:00 2001
|
||||
From: Johan Jonker <jbx6244@gmail.com>
|
||||
Date: Thu, 30 Sep 2021 13:05:16 +0200
|
||||
Subject: [PATCH] thermal/drivers/rockchip_thermal: Allow more resets for tsadc
|
||||
node
|
||||
|
||||
The tsadc node in rk356x.dtsi has more resets then currently supported
|
||||
by the rockchip_thermal.c driver, so use
|
||||
devm_reset_control_array_get() to reset them all.
|
||||
|
||||
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20210930110517.14323-3-jbx6244@gmail.com
|
||||
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
---
|
||||
drivers/thermal/rockchip_thermal.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/thermal/rockchip_thermal.c
|
||||
+++ b/drivers/thermal/rockchip_thermal.c
|
||||
@@ -1383,7 +1383,7 @@ static int rockchip_thermal_probe(struct
|
||||
if (IS_ERR(thermal->regs))
|
||||
return PTR_ERR(thermal->regs);
|
||||
|
||||
- thermal->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb");
|
||||
+ thermal->reset = devm_reset_control_array_get(&pdev->dev, false, false);
|
||||
if (IS_ERR(thermal->reset)) {
|
||||
error = PTR_ERR(thermal->reset);
|
||||
dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error);
|
||||
|
|
@ -1,67 +0,0 @@
|
|||
From 884d2b845477cd0a18302444dc20fe2d9a01743e Mon Sep 17 00:00:00 2001
|
||||
From: David Wu <david.wu@rock-chips.com>
|
||||
Date: Mon, 13 Dec 2021 19:15:15 +0800
|
||||
Subject: [PATCH] net: stmmac: Add GFP_DMA32 for rx buffers if no 64 capability
|
||||
|
||||
Use page_pool_alloc_pages instead of page_pool_dev_alloc_pages, which
|
||||
can give the gfp parameter, in the case of not supporting 64-bit width,
|
||||
using 32-bit address memory can reduce a copy from swiotlb.
|
||||
|
||||
Signed-off-by: David Wu <david.wu@rock-chips.com>
|
||||
Signed-off-by: David S. Miller <davem@davemloft.net>
|
||||
---
|
||||
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 16 ++++++++++++----
|
||||
1 file changed, 12 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
|
||||
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
|
||||
@@ -1487,16 +1487,20 @@ static int stmmac_init_rx_buffers(struct
|
||||
{
|
||||
struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue];
|
||||
struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
|
||||
+ gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN);
|
||||
+
|
||||
+ if (priv->dma_cap.addr64 <= 32)
|
||||
+ gfp |= GFP_DMA32;
|
||||
|
||||
if (!buf->page) {
|
||||
- buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
|
||||
+ buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp);
|
||||
if (!buf->page)
|
||||
return -ENOMEM;
|
||||
buf->page_offset = stmmac_rx_offset(priv);
|
||||
}
|
||||
|
||||
if (priv->sph && !buf->sec_page) {
|
||||
- buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool);
|
||||
+ buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp);
|
||||
if (!buf->sec_page)
|
||||
return -ENOMEM;
|
||||
|
||||
@@ -4633,6 +4637,10 @@ static inline void stmmac_rx_refill(stru
|
||||
struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue];
|
||||
int dirty = stmmac_rx_dirty(priv, queue);
|
||||
unsigned int entry = rx_q->dirty_rx;
|
||||
+ gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN);
|
||||
+
|
||||
+ if (priv->dma_cap.addr64 <= 32)
|
||||
+ gfp |= GFP_DMA32;
|
||||
|
||||
while (dirty-- > 0) {
|
||||
struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
|
||||
@@ -4645,13 +4653,13 @@ static inline void stmmac_rx_refill(stru
|
||||
p = rx_q->dma_rx + entry;
|
||||
|
||||
if (!buf->page) {
|
||||
- buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
|
||||
+ buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp);
|
||||
if (!buf->page)
|
||||
break;
|
||||
}
|
||||
|
||||
if (priv->sph && !buf->sec_page) {
|
||||
- buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool);
|
||||
+ buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp);
|
||||
if (!buf->sec_page)
|
||||
break;
|
||||
|
||||
|
|
@ -1,266 +0,0 @@
|
|||
From e1152a526b16951fbebba5540cfcbb9394532431 Mon Sep 17 00:00:00 2001
|
||||
From: Liang Chen <cl@rock-chips.com>
|
||||
Date: Thu, 24 Jun 2021 21:10:27 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: add pmu and qos nodes for rk3568
|
||||
|
||||
Add the power-management and QoS nodes to the core rk3568 dtsi.
|
||||
|
||||
Signed-off-by: Liang Chen <cl@rock-chips.com>
|
||||
Link: https://lore.kernel.org/r/20210624131027.3719-1-cl@rock-chips.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 229 +++++++++++++++++++++++
|
||||
1 file changed, 229 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
@@ -8,6 +8,7 @@
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
+#include <dt-bindings/power/rk3568-power.h>
|
||||
#include <dt-bindings/soc/rockchip,boot-mode.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
@@ -257,6 +258,99 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ pmu: power-management@fdd90000 {
|
||||
+ compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
|
||||
+ reg = <0x0 0xfdd90000 0x0 0x1000>;
|
||||
+
|
||||
+ power: power-controller {
|
||||
+ compatible = "rockchip,rk3568-power-controller";
|
||||
+ #power-domain-cells = <1>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ /* These power domains are grouped by VD_GPU */
|
||||
+ power-domain@RK3568_PD_GPU {
|
||||
+ reg = <RK3568_PD_GPU>;
|
||||
+ clocks = <&cru ACLK_GPU_PRE>,
|
||||
+ <&cru PCLK_GPU_PRE>;
|
||||
+ pm_qos = <&qos_gpu>;
|
||||
+ #power-domain-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ /* These power domains are grouped by VD_LOGIC */
|
||||
+ power-domain@RK3568_PD_VI {
|
||||
+ reg = <RK3568_PD_VI>;
|
||||
+ clocks = <&cru HCLK_VI>,
|
||||
+ <&cru PCLK_VI>;
|
||||
+ pm_qos = <&qos_isp>,
|
||||
+ <&qos_vicap0>,
|
||||
+ <&qos_vicap1>;
|
||||
+ #power-domain-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ power-domain@RK3568_PD_VO {
|
||||
+ reg = <RK3568_PD_VO>;
|
||||
+ clocks = <&cru HCLK_VO>,
|
||||
+ <&cru PCLK_VO>,
|
||||
+ <&cru ACLK_VOP_PRE>;
|
||||
+ pm_qos = <&qos_hdcp>,
|
||||
+ <&qos_vop_m0>,
|
||||
+ <&qos_vop_m1>;
|
||||
+ #power-domain-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ power-domain@RK3568_PD_RGA {
|
||||
+ reg = <RK3568_PD_RGA>;
|
||||
+ clocks = <&cru HCLK_RGA_PRE>,
|
||||
+ <&cru PCLK_RGA_PRE>;
|
||||
+ pm_qos = <&qos_ebc>,
|
||||
+ <&qos_iep>,
|
||||
+ <&qos_jpeg_dec>,
|
||||
+ <&qos_jpeg_enc>,
|
||||
+ <&qos_rga_rd>,
|
||||
+ <&qos_rga_wr>;
|
||||
+ #power-domain-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ power-domain@RK3568_PD_VPU {
|
||||
+ reg = <RK3568_PD_VPU>;
|
||||
+ clocks = <&cru HCLK_VPU_PRE>;
|
||||
+ pm_qos = <&qos_vpu>;
|
||||
+ #power-domain-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ power-domain@RK3568_PD_RKVDEC {
|
||||
+ clocks = <&cru HCLK_RKVDEC_PRE>;
|
||||
+ reg = <RK3568_PD_RKVDEC>;
|
||||
+ pm_qos = <&qos_rkvdec>;
|
||||
+ #power-domain-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ power-domain@RK3568_PD_RKVENC {
|
||||
+ reg = <RK3568_PD_RKVENC>;
|
||||
+ clocks = <&cru HCLK_RKVENC_PRE>;
|
||||
+ pm_qos = <&qos_rkvenc_rd_m0>,
|
||||
+ <&qos_rkvenc_rd_m1>,
|
||||
+ <&qos_rkvenc_wr_m0>;
|
||||
+ #power-domain-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ power-domain@RK3568_PD_PIPE {
|
||||
+ reg = <RK3568_PD_PIPE>;
|
||||
+ clocks = <&cru PCLK_PIPE>;
|
||||
+ pm_qos = <&qos_pcie2x1>,
|
||||
+ <&qos_pcie3x1>,
|
||||
+ <&qos_pcie3x2>,
|
||||
+ <&qos_sata0>,
|
||||
+ <&qos_sata1>,
|
||||
+ <&qos_sata2>,
|
||||
+ <&qos_usb3_0>,
|
||||
+ <&qos_usb3_1>;
|
||||
+ #power-domain-cells = <0>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
sdmmc2: mmc@fe000000 {
|
||||
compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
reg = <0x0 0xfe000000 0x0 0x4000>;
|
||||
@@ -271,6 +365,141 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ qos_gpu: qos@fe128000 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe128000 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ qos_rkvenc_rd_m0: qos@fe138080 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe138080 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ qos_rkvenc_rd_m1: qos@fe138100 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe138100 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ qos_rkvenc_wr_m0: qos@fe138180 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe138180 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ qos_isp: qos@fe148000 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe148000 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ qos_vicap0: qos@fe148080 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe148080 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ qos_vicap1: qos@fe148100 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe148100 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ qos_vpu: qos@fe150000 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe150000 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ qos_ebc: qos@fe158000 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe158000 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ qos_iep: qos@fe158100 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe158100 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ qos_jpeg_dec: qos@fe158180 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe158180 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ qos_jpeg_enc: qos@fe158200 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe158200 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ qos_rga_rd: qos@fe158280 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe158280 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ qos_rga_wr: qos@fe158300 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe158300 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ qos_npu: qos@fe180000 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe180000 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ qos_pcie2x1: qos@fe190000 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe190000 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ qos_pcie3x1: qos@fe190080 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe190080 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ qos_pcie3x2: qos@fe190100 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe190100 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ qos_sata0: qos@fe190200 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe190200 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ qos_sata1: qos@fe190280 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe190280 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ qos_sata2: qos@fe190300 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe190300 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ qos_usb3_0: qos@fe190380 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe190380 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ qos_usb3_1: qos@fe190400 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe190400 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ qos_rkvdec: qos@fe198000 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe198000 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ qos_hdcp: qos@fe1a8000 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe1a8000 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ qos_vop_m0: qos@fe1a8080 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe1a8080 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ qos_vop_m1: qos@fe1a8100 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe1a8100 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
sdmmc0: mmc@fe2b0000 {
|
||||
compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
reg = <0x0 0xfe2b0000 0x0 0x4000>;
|
||||
|
|
@ -1,35 +0,0 @@
|
|||
From 2076121eecc18fa31ae749c6ddc5648be96f0b5e Mon Sep 17 00:00:00 2001
|
||||
From: Simon Xue <xxm@rock-chips.com>
|
||||
Date: Mon, 5 Jul 2021 09:26:10 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: add saradc node for rk3568
|
||||
|
||||
Add the core dt-node for the rk3568's saradc.
|
||||
|
||||
Signed-off-by: Simon Xue <xxm@rock-chips.com>
|
||||
Link: https://lore.kernel.org/r/20210705012610.3831-1-xxm@rock-chips.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 12 ++++++++++++
|
||||
1 file changed, 12 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
@@ -754,6 +754,18 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ saradc: saradc@fe720000 {
|
||||
+ compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
|
||||
+ reg = <0x0 0xfe720000 0x0 0x100>;
|
||||
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
|
||||
+ clock-names = "saradc", "apb_pclk";
|
||||
+ resets = <&cru SRST_P_SARADC>;
|
||||
+ reset-names = "saradc-apb";
|
||||
+ #io-channel-cells = <1>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
pinctrl: pinctrl {
|
||||
compatible = "rockchip,rk3568-pinctrl";
|
||||
rockchip,grf = <&grf>;
|
||||
|
|
@ -1,21 +0,0 @@
|
|||
From 4e50d2173b67115a5574f4f4ce64ec9c5d9c136e Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Sat, 10 Jul 2021 11:10:31 -0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: move rk3568 dtsi to rk356x dtsi
|
||||
|
||||
In preparation for separating the rk3568 and rk3566 device trees, move
|
||||
the base rk3568 dtsi to rk356x dtsi.
|
||||
This will allow us to strip out the rk3568 specific nodes.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20210710151034.32857-2-pgwipeout@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/{rk3568.dtsi => rk356x.dtsi} | 0
|
||||
1 file changed, 0 insertions(+), 0 deletions(-)
|
||||
rename arch/arm64/boot/dts/rockchip/{rk3568.dtsi => rk356x.dtsi} (100%)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
similarity index 100%
|
||||
rename from arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
rename to arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
|
|
@ -1,135 +0,0 @@
|
|||
From 5067f459e5ee22857eeb4f659219db8e28c6263e Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Sat, 10 Jul 2021 11:10:32 -0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: split rk3568 device tree
|
||||
|
||||
In preparation for the rk3566 inclusion, split apart the rk3568 specific
|
||||
nodes into a separate device tree.
|
||||
This allows us to create the rk3566 device tree without deleting nodes.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20210710151034.32857-3-pgwipeout@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 48 ++++++++++++++++++++++++
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 36 ------------------
|
||||
2 files changed, 48 insertions(+), 36 deletions(-)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
@@ -0,0 +1,48 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
||||
+ */
|
||||
+
|
||||
+#include "rk356x.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ compatible = "rockchip,rk3568";
|
||||
+
|
||||
+ qos_pcie3x1: qos@fe190080 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe190080 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ qos_pcie3x2: qos@fe190100 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe190100 0x0 0x20>;
|
||||
+ };
|
||||
+
|
||||
+ qos_sata0: qos@fe190200 {
|
||||
+ compatible = "rockchip,rk3568-qos", "syscon";
|
||||
+ reg = <0x0 0xfe190200 0x0 0x20>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cpu0_opp_table {
|
||||
+ opp-1992000000 {
|
||||
+ opp-hz = /bits/ 64 <1992000000>;
|
||||
+ opp-microvolt = <1150000 1150000 1150000>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&power {
|
||||
+ power-domain@RK3568_PD_PIPE {
|
||||
+ reg = <RK3568_PD_PIPE>;
|
||||
+ clocks = <&cru PCLK_PIPE>;
|
||||
+ pm_qos = <&qos_pcie2x1>,
|
||||
+ <&qos_pcie3x1>,
|
||||
+ <&qos_pcie3x2>,
|
||||
+ <&qos_sata0>,
|
||||
+ <&qos_sata1>,
|
||||
+ <&qos_sata2>,
|
||||
+ <&qos_usb3_0>,
|
||||
+ <&qos_usb3_1>;
|
||||
+ #power-domain-cells = <0>;
|
||||
+ };
|
||||
+};
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -13,8 +13,6 @@
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
/ {
|
||||
- compatible = "rockchip,rk3568";
|
||||
-
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
@@ -121,11 +119,6 @@
|
||||
opp-hz = /bits/ 64 <1800000000>;
|
||||
opp-microvolt = <1050000 1050000 1150000>;
|
||||
};
|
||||
-
|
||||
- opp-1992000000 {
|
||||
- opp-hz = /bits/ 64 <1992000000>;
|
||||
- opp-microvolt = <1150000 1150000 1150000>;
|
||||
- };
|
||||
};
|
||||
|
||||
firmware {
|
||||
@@ -334,20 +327,6 @@
|
||||
<&qos_rkvenc_wr_m0>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
-
|
||||
- power-domain@RK3568_PD_PIPE {
|
||||
- reg = <RK3568_PD_PIPE>;
|
||||
- clocks = <&cru PCLK_PIPE>;
|
||||
- pm_qos = <&qos_pcie2x1>,
|
||||
- <&qos_pcie3x1>,
|
||||
- <&qos_pcie3x2>,
|
||||
- <&qos_sata0>,
|
||||
- <&qos_sata1>,
|
||||
- <&qos_sata2>,
|
||||
- <&qos_usb3_0>,
|
||||
- <&qos_usb3_1>;
|
||||
- #power-domain-cells = <0>;
|
||||
- };
|
||||
};
|
||||
};
|
||||
|
||||
@@ -445,21 +424,6 @@
|
||||
reg = <0x0 0xfe190000 0x0 0x20>;
|
||||
};
|
||||
|
||||
- qos_pcie3x1: qos@fe190080 {
|
||||
- compatible = "rockchip,rk3568-qos", "syscon";
|
||||
- reg = <0x0 0xfe190080 0x0 0x20>;
|
||||
- };
|
||||
-
|
||||
- qos_pcie3x2: qos@fe190100 {
|
||||
- compatible = "rockchip,rk3568-qos", "syscon";
|
||||
- reg = <0x0 0xfe190100 0x0 0x20>;
|
||||
- };
|
||||
-
|
||||
- qos_sata0: qos@fe190200 {
|
||||
- compatible = "rockchip,rk3568-qos", "syscon";
|
||||
- reg = <0x0 0xfe190200 0x0 0x20>;
|
||||
- };
|
||||
-
|
||||
qos_sata1: qos@fe190280 {
|
||||
compatible = "rockchip,rk3568-qos", "syscon";
|
||||
reg = <0x0 0xfe190280 0x0 0x20>;
|
||||
|
|
@ -1,39 +0,0 @@
|
|||
From 016c0e8a7a6e7820fb54d8ff8a4a2928a3016421 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Sat, 10 Jul 2021 11:10:33 -0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: add rk3566 dtsi
|
||||
|
||||
Add the rk3566 dtsi which includes the soc specific changes for this
|
||||
chip.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20210710151034.32857-4-pgwipeout@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3566.dtsi | 20 ++++++++++++++++++++
|
||||
1 file changed, 20 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566.dtsi
|
||||
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
|
||||
@@ -0,0 +1,20 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+#include "rk356x.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ compatible = "rockchip,rk3566";
|
||||
+};
|
||||
+
|
||||
+&power {
|
||||
+ power-domain@RK3568_PD_PIPE {
|
||||
+ reg = <RK3568_PD_PIPE>;
|
||||
+ clocks = <&cru PCLK_PIPE>;
|
||||
+ pm_qos = <&qos_pcie2x1>,
|
||||
+ <&qos_sata1>,
|
||||
+ <&qos_sata2>,
|
||||
+ <&qos_usb3_0>,
|
||||
+ <&qos_usb3_1>;
|
||||
+ #power-domain-cells = <0>;
|
||||
+ };
|
||||
+};
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
From 0edcfec3fafa1fe58fd9a3be727742881ec340c3 Mon Sep 17 00:00:00 2001
|
||||
From: Liang Chen <cl@rock-chips.com>
|
||||
Date: Tue, 22 Jun 2021 12:29:07 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: add watchdog to rk3568
|
||||
|
||||
Add the watchdog node to rk3568.
|
||||
|
||||
Signed-off-by: Liang Chen <cl@rock-chips.com>
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Link: https://lore.kernel.org/r/20210622102907.99242-2-heiko@sntech.de
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 8 ++++++++
|
||||
1 file changed, 8 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -592,6 +592,14 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ wdt: watchdog@fe600000 {
|
||||
+ compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
|
||||
+ reg = <0x0 0xfe600000 0x0 0x100>;
|
||||
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
|
||||
+ clock-names = "tclk", "pclk";
|
||||
+ };
|
||||
+
|
||||
uart1: serial@fe650000 {
|
||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xfe650000 0x0 0x100>;
|
||||
|
|
@ -1,28 +0,0 @@
|
|||
From b6c1a590148c63f822091912b4c09c79fbb13971 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Wed, 28 Jul 2021 14:00:27 -0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: fix rk3568 mbi-alias
|
||||
|
||||
The mbi-alias incorrectly points to 0xfd100000 when it should point to
|
||||
0xfd410000.
|
||||
This fixes MSIs on rk3568.
|
||||
|
||||
Fixes: a3adc0b9071d ("arm64: dts: rockchip: add core dtsi for RK3568 SoC")
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20210728180034.717953-2-pgwipeout@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -195,7 +195,7 @@
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
- mbi-alias = <0x0 0xfd100000>;
|
||||
+ mbi-alias = <0x0 0xfd410000>;
|
||||
mbi-ranges = <296 24>;
|
||||
msi-controller;
|
||||
};
|
||||
|
|
@ -1,72 +0,0 @@
|
|||
From 0dcec571cee519989d9536fd31328cdcbc0a45c7 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Wed, 28 Jul 2021 14:00:30 -0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: add rk356x gmac1 node
|
||||
|
||||
Add the gmac1 controller to the rk356x device tree.
|
||||
This is the controller common to both the rk3568 and rk3566.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20210728180034.717953-5-pgwipeout@gmail.com
|
||||
[adjusted sorting a bit]
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++++++++++++++++++++++++
|
||||
1 file changed, 47 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -344,6 +344,53 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ gmac1: ethernet@fe010000 {
|
||||
+ compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
|
||||
+ reg = <0x0 0xfe010000 0x0 0x10000>;
|
||||
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "macirq", "eth_wake_irq";
|
||||
+ clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
|
||||
+ <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
|
||||
+ <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
|
||||
+ <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>;
|
||||
+ clock-names = "stmmaceth", "mac_clk_rx",
|
||||
+ "mac_clk_tx", "clk_mac_refout",
|
||||
+ "aclk_mac", "pclk_mac",
|
||||
+ "clk_mac_speed", "ptp_ref";
|
||||
+ resets = <&cru SRST_A_GMAC1>;
|
||||
+ reset-names = "stmmaceth";
|
||||
+ rockchip,grf = <&grf>;
|
||||
+ snps,axi-config = <&gmac1_stmmac_axi_setup>;
|
||||
+ snps,mixed-burst;
|
||||
+ snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
|
||||
+ snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
|
||||
+ snps,tso;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ mdio1: mdio {
|
||||
+ compatible = "snps,dwmac-mdio";
|
||||
+ #address-cells = <0x1>;
|
||||
+ #size-cells = <0x0>;
|
||||
+ };
|
||||
+
|
||||
+ gmac1_stmmac_axi_setup: stmmac-axi-config {
|
||||
+ snps,blen = <0 0 0 0 16 8 4>;
|
||||
+ snps,rd_osr_lmt = <8>;
|
||||
+ snps,wr_osr_lmt = <4>;
|
||||
+ };
|
||||
+
|
||||
+ gmac1_mtl_rx_setup: rx-queues-config {
|
||||
+ snps,rx-queues-to-use = <1>;
|
||||
+ queue0 {};
|
||||
+ };
|
||||
+
|
||||
+ gmac1_mtl_tx_setup: tx-queues-config {
|
||||
+ snps,tx-queues-to-use = <1>;
|
||||
+ queue0 {};
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
qos_gpu: qos@fe128000 {
|
||||
compatible = "rockchip,rk3568-qos", "syscon";
|
||||
reg = <0x0 0xfe128000 0x0 0x20>;
|
||||
|
|
@ -1,36 +0,0 @@
|
|||
From f7c5b9c2a1af765de0aae3a21073e051e95448bf Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Wed, 28 Jul 2021 14:00:32 -0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: adjust rk3568 pll clocks
|
||||
|
||||
The rk3568 gpll should run at 1200mhz and the ppll should run at 200mhz.
|
||||
These are set incorrectly by the bootloader, so fix them here.
|
||||
|
||||
gpll boots at 1188mhz, but to get most accurate dividers for all
|
||||
gpll_dividers it needs to run at 1200mhz, otherwise everyone downstream
|
||||
isn't quite right.
|
||||
|
||||
ppll feeds the combophys, which has a divide by 2 clock, so 200mhz is
|
||||
required to reach a 100mhz clock input for them.
|
||||
|
||||
The vendor-kernel also makes this fix.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
[pulled deeper explanation from discussion into commit message]
|
||||
Link: https://lore.kernel.org/r/20210728180034.717953-7-pgwipeout@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -222,6 +222,8 @@
|
||||
reg = <0x0 0xfdd20000 0x0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
+ assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
|
||||
+ assigned-clock-rates = <1200000000>, <200000000>;
|
||||
};
|
||||
|
||||
i2c0: i2c@fdd40000 {
|
||||
|
|
@ -1,73 +0,0 @@
|
|||
From b8d41e5053cd823817344cc5e7a2bfda508effff Mon Sep 17 00:00:00 2001
|
||||
From: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Date: Thu, 29 Jul 2021 11:39:12 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: add gmac0 node to rk3568
|
||||
|
||||
While both RK3566 and RK3568 feature the gmac1 node, the gmac0
|
||||
node is exclusive to the RK3568.
|
||||
|
||||
Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20210729093913.8917-2-michael.riesch@wolfvision.net
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 49 ++++++++++++++++++++++++
|
||||
1 file changed, 49 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
@@ -22,6 +22,55 @@
|
||||
compatible = "rockchip,rk3568-qos", "syscon";
|
||||
reg = <0x0 0xfe190200 0x0 0x20>;
|
||||
};
|
||||
+
|
||||
+ gmac0: ethernet@fe2a0000 {
|
||||
+ compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
|
||||
+ reg = <0x0 0xfe2a0000 0x0 0x10000>;
|
||||
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "macirq", "eth_wake_irq";
|
||||
+ clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
|
||||
+ <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
|
||||
+ <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
|
||||
+ <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
|
||||
+ <&cru PCLK_XPCS>;
|
||||
+ clock-names = "stmmaceth", "mac_clk_rx",
|
||||
+ "mac_clk_tx", "clk_mac_refout",
|
||||
+ "aclk_mac", "pclk_mac",
|
||||
+ "clk_mac_speed", "ptp_ref",
|
||||
+ "pclk_xpcs";
|
||||
+ resets = <&cru SRST_A_GMAC0>;
|
||||
+ reset-names = "stmmaceth";
|
||||
+ rockchip,grf = <&grf>;
|
||||
+ snps,axi-config = <&gmac0_stmmac_axi_setup>;
|
||||
+ snps,mixed-burst;
|
||||
+ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
|
||||
+ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
|
||||
+ snps,tso;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ mdio0: mdio {
|
||||
+ compatible = "snps,dwmac-mdio";
|
||||
+ #address-cells = <0x1>;
|
||||
+ #size-cells = <0x0>;
|
||||
+ };
|
||||
+
|
||||
+ gmac0_stmmac_axi_setup: stmmac-axi-config {
|
||||
+ snps,blen = <0 0 0 0 16 8 4>;
|
||||
+ snps,rd_osr_lmt = <8>;
|
||||
+ snps,wr_osr_lmt = <4>;
|
||||
+ };
|
||||
+
|
||||
+ gmac0_mtl_rx_setup: rx-queues-config {
|
||||
+ snps,rx-queues-to-use = <1>;
|
||||
+ queue0 {};
|
||||
+ };
|
||||
+
|
||||
+ gmac0_mtl_tx_setup: tx-queues-config {
|
||||
+ snps,tx-queues-to-use = <1>;
|
||||
+ queue0 {};
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
&cpu0_opp_table {
|
||||
|
|
@ -1,28 +0,0 @@
|
|||
From 2dbcb2514c83416f2d0731bb0744a6c132f5c8c6 Mon Sep 17 00:00:00 2001
|
||||
From: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Date: Thu, 5 Aug 2021 14:01:03 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: add core io domains node for rk356x
|
||||
|
||||
Enable the PMU IO domains for the RK3566 and the RK3568.
|
||||
|
||||
Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20210805120107.27007-4-michael.riesch@wolfvision.net
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 5 +++++
|
||||
1 file changed, 5 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -203,6 +203,11 @@
|
||||
pmugrf: syscon@fdc20000 {
|
||||
compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xfdc20000 0x0 0x10000>;
|
||||
+
|
||||
+ pmu_io_domains: io-domains {
|
||||
+ compatible = "rockchip,rk3568-pmu-io-voltage-domain";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
};
|
||||
|
||||
grf: syscon@fdc60000 {
|
||||
|
|
@ -1,63 +0,0 @@
|
|||
From 3d9170c3ea221f495902cc42fcea1c072c0af7c7 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Wed, 28 Jul 2021 14:00:29 -0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: add rk356x gpio debounce clocks
|
||||
|
||||
The rk356x added a debounce clock to the gpio devices. This clock is
|
||||
necessary for the new v2 gpio driver to bind.
|
||||
Add the clocks to the rk356x device tree.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20210728180034.717953-4-pgwipeout@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 10 +++++-----
|
||||
1 file changed, 5 insertions(+), 5 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -804,7 +804,7 @@
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0xfdd60000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- clocks = <&pmucru PCLK_GPIO0>;
|
||||
+ clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
@@ -815,7 +815,7 @@
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0xfe740000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- clocks = <&cru PCLK_GPIO1>;
|
||||
+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
@@ -826,7 +826,7 @@
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0xfe750000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- clocks = <&cru PCLK_GPIO2>;
|
||||
+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
@@ -837,7 +837,7 @@
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0xfe760000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- clocks = <&cru PCLK_GPIO3>;
|
||||
+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
@@ -848,7 +848,7 @@
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x0 0xfe770000 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- clocks = <&cru PCLK_GPIO4>;
|
||||
+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
|
|
@ -1,139 +0,0 @@
|
|||
From 1330875dc2a3742fd41127e78d5036f2d8f261da Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Wed, 28 Jul 2021 14:00:31 -0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: add rk3568 tsadc nodes
|
||||
|
||||
Add the thermal and tsadc nodes to the rk3568 device tree.
|
||||
There are two sensors, one for the cpu, one for the gpu.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20210728180034.717953-6-pgwipeout@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
.../boot/dts/rockchip/rk3568-pinctrl.dtsi | 9 +++
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 70 +++++++++++++++++++
|
||||
2 files changed, 79 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
|
||||
@@ -3108,4 +3108,13 @@
|
||||
<4 RK_PA0 3 &pcfg_pull_none_drv_level_2>;
|
||||
};
|
||||
};
|
||||
+
|
||||
+ tsadc {
|
||||
+ /omit-if-no-ref/
|
||||
+ tsadc_pin: tsadc-pin {
|
||||
+ rockchip,pins =
|
||||
+ /* tsadc_pin */
|
||||
+ <0 RK_PA1 0 &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -50,6 +50,7 @@
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0 0x0>;
|
||||
clocks = <&scmi_clk 0>;
|
||||
+ #cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
};
|
||||
@@ -58,6 +59,7 @@
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0 0x100>;
|
||||
+ #cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
};
|
||||
@@ -66,6 +68,7 @@
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0 0x200>;
|
||||
+ #cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
};
|
||||
@@ -74,6 +77,7 @@
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x0 0x300>;
|
||||
+ #cooling-cells = <2>;
|
||||
enable-method = "psci";
|
||||
operating-points-v2 = <&cpu0_opp_table>;
|
||||
};
|
||||
@@ -780,6 +784,72 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ thermal_zones: thermal-zones {
|
||||
+ cpu_thermal: cpu-thermal {
|
||||
+ polling-delay-passive = <100>;
|
||||
+ polling-delay = <1000>;
|
||||
+
|
||||
+ thermal-sensors = <&tsadc 0>;
|
||||
+
|
||||
+ trips {
|
||||
+ cpu_alert0: cpu_alert0 {
|
||||
+ temperature = <70000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+ cpu_alert1: cpu_alert1 {
|
||||
+ temperature = <75000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "passive";
|
||||
+ };
|
||||
+ cpu_crit: cpu_crit {
|
||||
+ temperature = <95000>;
|
||||
+ hysteresis = <2000>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cooling-maps {
|
||||
+ map0 {
|
||||
+ trip = <&cpu_alert0>;
|
||||
+ cooling-device =
|
||||
+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
||||
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gpu_thermal: gpu-thermal {
|
||||
+ polling-delay-passive = <20>; /* milliseconds */
|
||||
+ polling-delay = <1000>; /* milliseconds */
|
||||
+
|
||||
+ thermal-sensors = <&tsadc 1>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ tsadc: tsadc@fe710000 {
|
||||
+ compatible = "rockchip,rk3568-tsadc";
|
||||
+ reg = <0x0 0xfe710000 0x0 0x100>;
|
||||
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
|
||||
+ assigned-clock-rates = <17000000>, <700000>;
|
||||
+ clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
|
||||
+ clock-names = "tsadc", "apb_pclk";
|
||||
+ resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>,
|
||||
+ <&cru SRST_TSADCPHY>;
|
||||
+ reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
|
||||
+ rockchip,grf = <&grf>;
|
||||
+ rockchip,hw-tshut-temp = <95000>;
|
||||
+ pinctrl-names = "init", "default", "sleep";
|
||||
+ pinctrl-0 = <&tsadc_pin>;
|
||||
+ pinctrl-1 = <&tsadc_shutorg>;
|
||||
+ pinctrl-2 = <&tsadc_pin>;
|
||||
+ #thermal-sensor-cells = <1>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
saradc: saradc@fe720000 {
|
||||
compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
|
||||
reg = <0x0 0xfe720000 0x0 0x100>;
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
From 95ad4dbe5f43bf67036775df56c848aa8ffea8e2 Mon Sep 17 00:00:00 2001
|
||||
From: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Date: Mon, 23 Aug 2021 14:39:11 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: add missing rockchip,grf property to
|
||||
rk356x
|
||||
|
||||
This commit fixes the error messages
|
||||
|
||||
rockchip_clk_register_muxgrf: regmap not available
|
||||
rockchip_clk_register_branches: failed to register clock clk_ddr1x: -524
|
||||
|
||||
during boot by providing the missing rockchip,grf property.
|
||||
|
||||
Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Tested-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20210823123911.12095-2-michael.riesch@wolfvision.net
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -233,6 +233,7 @@
|
||||
#reset-cells = <1>;
|
||||
assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
|
||||
assigned-clock-rates = <1200000000>, <200000000>;
|
||||
+ rockchip,grf = <&grf>;
|
||||
};
|
||||
|
||||
i2c0: i2c@fdd40000 {
|
||||
|
|
@ -1,207 +0,0 @@
|
|||
From 98419a39d1dc276ac395c230ba2e6cf435a624b9 Mon Sep 17 00:00:00 2001
|
||||
From: Liang Chen <cl@rock-chips.com>
|
||||
Date: Mon, 26 Jul 2021 11:03:55 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: add pwm nodes for rk3568
|
||||
|
||||
Add the pwm controller nodes to the core rk3568 dtsi.
|
||||
|
||||
Signed-off-by: Liang Chen <cl@rock-chips.com>
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Link: https://lore.kernel.org/r/20210726090355.1548483-2-heiko@sntech.de
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 176 +++++++++++++++++++++++
|
||||
1 file changed, 176 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -263,6 +263,50 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ pwm0: pwm@fdd70000 {
|
||||
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
+ reg = <0x0 0xfdd70000 0x0 0x10>;
|
||||
+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
|
||||
+ clock-names = "pwm", "pclk";
|
||||
+ pinctrl-0 = <&pwm0m0_pins>;
|
||||
+ pinctrl-names = "active";
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm1: pwm@fdd70010 {
|
||||
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
+ reg = <0x0 0xfdd70010 0x0 0x10>;
|
||||
+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
|
||||
+ clock-names = "pwm", "pclk";
|
||||
+ pinctrl-0 = <&pwm1m0_pins>;
|
||||
+ pinctrl-names = "active";
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm2: pwm@fdd70020 {
|
||||
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
+ reg = <0x0 0xfdd70020 0x0 0x10>;
|
||||
+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
|
||||
+ clock-names = "pwm", "pclk";
|
||||
+ pinctrl-0 = <&pwm2m0_pins>;
|
||||
+ pinctrl-names = "active";
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm3: pwm@fdd70030 {
|
||||
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
+ reg = <0x0 0xfdd70030 0x0 0x10>;
|
||||
+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
|
||||
+ clock-names = "pwm", "pclk";
|
||||
+ pinctrl-0 = <&pwm3_pins>;
|
||||
+ pinctrl-names = "active";
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
pmu: power-management@fdd90000 {
|
||||
compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xfdd90000 0x0 0x1000>;
|
||||
@@ -863,6 +907,138 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ pwm4: pwm@fe6e0000 {
|
||||
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
+ reg = <0x0 0xfe6e0000 0x0 0x10>;
|
||||
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
||||
+ clock-names = "pwm", "pclk";
|
||||
+ pinctrl-0 = <&pwm4_pins>;
|
||||
+ pinctrl-names = "active";
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm5: pwm@fe6e0010 {
|
||||
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
+ reg = <0x0 0xfe6e0010 0x0 0x10>;
|
||||
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
||||
+ clock-names = "pwm", "pclk";
|
||||
+ pinctrl-0 = <&pwm5_pins>;
|
||||
+ pinctrl-names = "active";
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm6: pwm@fe6e0020 {
|
||||
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
+ reg = <0x0 0xfe6e0020 0x0 0x10>;
|
||||
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
||||
+ clock-names = "pwm", "pclk";
|
||||
+ pinctrl-0 = <&pwm6_pins>;
|
||||
+ pinctrl-names = "active";
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm7: pwm@fe6e0030 {
|
||||
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
+ reg = <0x0 0xfe6e0030 0x0 0x10>;
|
||||
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
||||
+ clock-names = "pwm", "pclk";
|
||||
+ pinctrl-0 = <&pwm7_pins>;
|
||||
+ pinctrl-names = "active";
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm8: pwm@fe6f0000 {
|
||||
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
+ reg = <0x0 0xfe6f0000 0x0 0x10>;
|
||||
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
+ clock-names = "pwm", "pclk";
|
||||
+ pinctrl-0 = <&pwm8m0_pins>;
|
||||
+ pinctrl-names = "active";
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm9: pwm@fe6f0010 {
|
||||
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
+ reg = <0x0 0xfe6f0010 0x0 0x10>;
|
||||
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
+ clock-names = "pwm", "pclk";
|
||||
+ pinctrl-0 = <&pwm9m0_pins>;
|
||||
+ pinctrl-names = "active";
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm10: pwm@fe6f0020 {
|
||||
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
+ reg = <0x0 0xfe6f0020 0x0 0x10>;
|
||||
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
+ clock-names = "pwm", "pclk";
|
||||
+ pinctrl-0 = <&pwm10m0_pins>;
|
||||
+ pinctrl-names = "active";
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm11: pwm@fe6f0030 {
|
||||
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
+ reg = <0x0 0xfe6f0030 0x0 0x10>;
|
||||
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
||||
+ clock-names = "pwm", "pclk";
|
||||
+ pinctrl-0 = <&pwm11m0_pins>;
|
||||
+ pinctrl-names = "active";
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm12: pwm@fe700000 {
|
||||
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
+ reg = <0x0 0xfe700000 0x0 0x10>;
|
||||
+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
||||
+ clock-names = "pwm", "pclk";
|
||||
+ pinctrl-0 = <&pwm12m0_pins>;
|
||||
+ pinctrl-names = "active";
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm13: pwm@fe700010 {
|
||||
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
+ reg = <0x0 0xfe700010 0x0 0x10>;
|
||||
+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
||||
+ clock-names = "pwm", "pclk";
|
||||
+ pinctrl-0 = <&pwm13m0_pins>;
|
||||
+ pinctrl-names = "active";
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm14: pwm@fe700020 {
|
||||
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
+ reg = <0x0 0xfe700020 0x0 0x10>;
|
||||
+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
||||
+ clock-names = "pwm", "pclk";
|
||||
+ pinctrl-0 = <&pwm14m0_pins>;
|
||||
+ pinctrl-names = "active";
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ pwm15: pwm@fe700030 {
|
||||
+ compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
|
||||
+ reg = <0x0 0xfe700030 0x0 0x10>;
|
||||
+ clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
||||
+ clock-names = "pwm", "pclk";
|
||||
+ pinctrl-0 = <&pwm15m0_pins>;
|
||||
+ pinctrl-names = "active";
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
pinctrl: pinctrl {
|
||||
compatible = "rockchip,rk3568-pinctrl";
|
||||
rockchip,grf = <&grf>;
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
From a65e6523e6dcf1dc4ea167ab78ca6fad01f16d91 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Fri, 15 Oct 2021 13:13:01 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: add spdif node to rk356x
|
||||
|
||||
This adds the spdif node to the rk356x device tree.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20211015111303.1365328-1-frattaroli.nicolas@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 14 ++++++++++++++
|
||||
1 file changed, 14 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -608,6 +608,20 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ spdif: spdif@fe460000 {
|
||||
+ compatible = "rockchip,rk3568-spdif";
|
||||
+ reg = <0x0 0xfe460000 0x0 0x1000>;
|
||||
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clock-names = "mclk", "hclk";
|
||||
+ clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
|
||||
+ dmas = <&dmac1 1>;
|
||||
+ dma-names = "tx";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&spdifm0_tx>;
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
dmac0: dmac@fe530000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x0 0xfe530000 0x0 0x4000>;
|
||||
|
|
@ -1,53 +0,0 @@
|
|||
From ef5c913570040df1955dd49cea221783468faeaf Mon Sep 17 00:00:00 2001
|
||||
From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
|
||||
Date: Sat, 16 Oct 2021 12:53:52 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add i2s1 on rk356x
|
||||
|
||||
This adds the necessary device tree node on rk3566 and rk3568
|
||||
to enable the I2S1 TDM audio controller.
|
||||
|
||||
I2S0 has not been added, as it is connected to HDMI and there is
|
||||
no way to test that it's working without a functioning video
|
||||
clock (read: VOP2 driver).
|
||||
|
||||
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20211016105354.116513-4-frattaroli.nicolas@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 25 ++++++++++++++++++++++++
|
||||
1 file changed, 25 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -622,6 +622,31 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ i2s1_8ch: i2s@fe410000 {
|
||||
+ compatible = "rockchip,rk3568-i2s-tdm";
|
||||
+ reg = <0x0 0xfe410000 0x0 0x1000>;
|
||||
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>;
|
||||
+ assigned-clock-rates = <1188000000>, <1188000000>;
|
||||
+ clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>,
|
||||
+ <&cru HCLK_I2S1_8CH>;
|
||||
+ clock-names = "mclk_tx", "mclk_rx", "hclk";
|
||||
+ dmas = <&dmac1 3>, <&dmac1 2>;
|
||||
+ dma-names = "rx", "tx";
|
||||
+ resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
|
||||
+ reset-names = "tx-m", "rx-m";
|
||||
+ rockchip,grf = <&grf>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
|
||||
+ &i2s1m0_lrcktx &i2s1m0_lrckrx
|
||||
+ &i2s1m0_sdi0 &i2s1m0_sdi1
|
||||
+ &i2s1m0_sdi2 &i2s1m0_sdi3
|
||||
+ &i2s1m0_sdo0 &i2s1m0_sdo1
|
||||
+ &i2s1m0_sdo2 &i2s1m0_sdo3>;
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
dmac0: dmac@fe530000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x0 0xfe530000 0x0 0x4000>;
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
From 5c9e66c6b75a754025c74bde7b7a6c52674d8aa1 Mon Sep 17 00:00:00 2001
|
||||
From: Johan Jonker <jbx6244@gmail.com>
|
||||
Date: Thu, 30 Sep 2021 13:05:17 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: fix resets in tsadc node for rk356x
|
||||
|
||||
In the rockchip_thermal.c driver we now get the resets with
|
||||
a devm_reset_control_array_get() function, so remove
|
||||
the reset-names property as it is no longer needed.
|
||||
Although no longer required in rockchip-thermal.yaml
|
||||
sort tsadc-apb as first item.
|
||||
|
||||
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20210930110517.14323-4-jbx6244@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 3 +--
|
||||
1 file changed, 1 insertion(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -921,9 +921,8 @@
|
||||
assigned-clock-rates = <17000000>, <700000>;
|
||||
clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
|
||||
clock-names = "tsadc", "apb_pclk";
|
||||
- resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>,
|
||||
+ resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>,
|
||||
<&cru SRST_TSADCPHY>;
|
||||
- reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
|
||||
rockchip,grf = <&grf>;
|
||||
rockchip,hw-tshut-temp = <95000>;
|
||||
pinctrl-names = "init", "default", "sleep";
|
||||
|
|
@ -1,97 +0,0 @@
|
|||
From aaa552d84580e9213d0e2bf0f9243477d1227bdd Mon Sep 17 00:00:00 2001
|
||||
From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
|
||||
Date: Sat, 27 Nov 2021 15:19:08 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add spi nodes on rk356x
|
||||
|
||||
This adds the four spi nodes (spi0, spi1, spi2, spi3) to the
|
||||
rk356x dtsi. These are from the downstream device tree, though
|
||||
I have double-checked that their interrupts and DMA numbers are
|
||||
correct. I have also tested spi1 with an SPI device.
|
||||
|
||||
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20211127141910.12649-3-frattaroli.nicolas@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 64 ++++++++++++++++++++++++
|
||||
1 file changed, 64 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -39,6 +39,10 @@
|
||||
serial7 = &uart7;
|
||||
serial8 = &uart8;
|
||||
serial9 = &uart9;
|
||||
+ spi0 = &spi0;
|
||||
+ spi1 = &spi1;
|
||||
+ spi2 = &spi2;
|
||||
+ spi3 = &spi3;
|
||||
};
|
||||
|
||||
cpus {
|
||||
@@ -742,6 +746,66 @@
|
||||
clock-names = "tclk", "pclk";
|
||||
};
|
||||
|
||||
+ spi0: spi@fe610000 {
|
||||
+ compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
|
||||
+ reg = <0x0 0xfe610000 0x0 0x1000>;
|
||||
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
|
||||
+ clock-names = "spiclk", "apb_pclk";
|
||||
+ dmas = <&dmac0 20>, <&dmac0 21>;
|
||||
+ dma-names = "tx", "rx";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ spi1: spi@fe620000 {
|
||||
+ compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
|
||||
+ reg = <0x0 0xfe620000 0x0 0x1000>;
|
||||
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
|
||||
+ clock-names = "spiclk", "apb_pclk";
|
||||
+ dmas = <&dmac0 22>, <&dmac0 23>;
|
||||
+ dma-names = "tx", "rx";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ spi2: spi@fe630000 {
|
||||
+ compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
|
||||
+ reg = <0x0 0xfe630000 0x0 0x1000>;
|
||||
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
|
||||
+ clock-names = "spiclk", "apb_pclk";
|
||||
+ dmas = <&dmac0 24>, <&dmac0 25>;
|
||||
+ dma-names = "tx", "rx";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ spi3: spi@fe640000 {
|
||||
+ compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
|
||||
+ reg = <0x0 0xfe640000 0x0 0x1000>;
|
||||
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
|
||||
+ clock-names = "spiclk", "apb_pclk";
|
||||
+ dmas = <&dmac0 26>, <&dmac0 27>;
|
||||
+ dma-names = "tx", "rx";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
uart1: serial@fe650000 {
|
||||
compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
|
||||
reg = <0x0 0xfe650000 0x0 0x100>;
|
||||
|
|
@ -1,139 +0,0 @@
|
|||
From cca4da59db28cdd284d34835be9f109f37bf0803 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Wed, 15 Dec 2021 16:02:51 -0500
|
||||
Subject: [PATCH] arm64: dts: rockchip: add usb2 nodes to rk3568 device tree
|
||||
|
||||
Add the requisite nodes to the rk3568 device tree to enable the usb2
|
||||
device controllers.
|
||||
Includes the usb2phy nodes, usb2phy grf nodes, and usb2 controller
|
||||
nodes.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20211215210252.120923-8-pgwipeout@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 98 ++++++++++++++++++++++++
|
||||
1 file changed, 98 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -208,6 +208,50 @@
|
||||
msi-controller;
|
||||
};
|
||||
|
||||
+ usb_host0_ehci: usb@fd800000 {
|
||||
+ compatible = "generic-ehci";
|
||||
+ reg = <0x0 0xfd800000 0x0 0x40000>;
|
||||
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
|
||||
+ <&cru PCLK_USB>;
|
||||
+ phys = <&u2phy1_otg>;
|
||||
+ phy-names = "usb";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ usb_host0_ohci: usb@fd840000 {
|
||||
+ compatible = "generic-ohci";
|
||||
+ reg = <0x0 0xfd840000 0x0 0x40000>;
|
||||
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
|
||||
+ <&cru PCLK_USB>;
|
||||
+ phys = <&u2phy1_otg>;
|
||||
+ phy-names = "usb";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ usb_host1_ehci: usb@fd880000 {
|
||||
+ compatible = "generic-ehci";
|
||||
+ reg = <0x0 0xfd880000 0x0 0x40000>;
|
||||
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
|
||||
+ <&cru PCLK_USB>;
|
||||
+ phys = <&u2phy1_host>;
|
||||
+ phy-names = "usb";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ usb_host1_ohci: usb@fd8c0000 {
|
||||
+ compatible = "generic-ohci";
|
||||
+ reg = <0x0 0xfd8c0000 0x0 0x40000>;
|
||||
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
|
||||
+ <&cru PCLK_USB>;
|
||||
+ phys = <&u2phy1_host>;
|
||||
+ phy-names = "usb";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
pmugrf: syscon@fdc20000 {
|
||||
compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xfdc20000 0x0 0x10000>;
|
||||
@@ -223,6 +267,16 @@
|
||||
reg = <0x0 0xfdc60000 0x0 0x10000>;
|
||||
};
|
||||
|
||||
+ usb2phy0_grf: syscon@fdca0000 {
|
||||
+ compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
|
||||
+ reg = <0x0 0xfdca0000 0x0 0x8000>;
|
||||
+ };
|
||||
+
|
||||
+ usb2phy1_grf: syscon@fdca8000 {
|
||||
+ compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
|
||||
+ reg = <0x0 0xfdca8000 0x0 0x8000>;
|
||||
+ };
|
||||
+
|
||||
pmucru: clock-controller@fdd00000 {
|
||||
compatible = "rockchip,rk3568-pmucru";
|
||||
reg = <0x0 0xfdd00000 0x0 0x1000>;
|
||||
@@ -1141,6 +1195,50 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ u2phy0: usb2phy@fe8a0000 {
|
||||
+ compatible = "rockchip,rk3568-usb2phy";
|
||||
+ reg = <0x0 0xfe8a0000 0x0 0x10000>;
|
||||
+ clocks = <&pmucru CLK_USBPHY0_REF>;
|
||||
+ clock-names = "phyclk";
|
||||
+ clock-output-names = "clk_usbphy0_480m";
|
||||
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ rockchip,usbgrf = <&usb2phy0_grf>;
|
||||
+ #clock-cells = <0>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ u2phy0_host: host-port {
|
||||
+ #phy-cells = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ u2phy0_otg: otg-port {
|
||||
+ #phy-cells = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ u2phy1: usb2phy@fe8b0000 {
|
||||
+ compatible = "rockchip,rk3568-usb2phy";
|
||||
+ reg = <0x0 0xfe8b0000 0x0 0x10000>;
|
||||
+ clocks = <&pmucru CLK_USBPHY1_REF>;
|
||||
+ clock-names = "phyclk";
|
||||
+ clock-output-names = "clk_usbphy1_480m";
|
||||
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ rockchip,usbgrf = <&usb2phy1_grf>;
|
||||
+ #clock-cells = <0>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ u2phy1_host: host-port {
|
||||
+ #phy-cells = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ u2phy1_otg: otg-port {
|
||||
+ #phy-cells = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
pinctrl: pinctrl {
|
||||
compatible = "rockchip,rk3568-pinctrl";
|
||||
rockchip,grf = <&grf>;
|
||||
|
|
@ -1,54 +0,0 @@
|
|||
From 85a8bccfa945680dc561f06b65ea01341d2033fc Mon Sep 17 00:00:00 2001
|
||||
From: Frank Wunderlich <frank-w@public-files.de>
|
||||
Date: Sun, 23 Jan 2022 14:35:10 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: drop pclk_xpcs from gmac0 on rk3568
|
||||
|
||||
pclk_xpcs is not supported by mainline driver and breaks dtbs_check
|
||||
|
||||
following warnings occour, and many more
|
||||
|
||||
rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clocks:
|
||||
[[15, 386], [15, 389], [15, 389], [15, 184], [15, 180], [15, 181],
|
||||
[15, 389], [15, 185], [15, 172]] is too long
|
||||
From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml
|
||||
rk3568-evb1-v10.dt.yaml: ethernet@fe2a0000: clock-names:
|
||||
['stmmaceth', 'mac_clk_rx', 'mac_clk_tx', 'clk_mac_refout', 'aclk_mac',
|
||||
'pclk_mac', 'clk_mac_speed', 'ptp_ref', 'pclk_xpcs'] is too long
|
||||
From schema: Documentation/devicetree/bindings/net/snps,dwmac.yaml
|
||||
|
||||
after removing it, the clock and other warnings are gone.
|
||||
|
||||
pclk_xpcs on gmac is used to support QSGMII, but this requires a driver
|
||||
supporting it.
|
||||
Once xpcs support is introduced, the clock can be added to the
|
||||
documentation and both controllers.
|
||||
|
||||
Fixes: b8d41e5053cd ("arm64: dts: rockchip: add gmac0 node to rk3568")
|
||||
Co-developed-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
|
||||
Acked-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20220123133510.135651-1-linux@fw-web.de
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 6 ++----
|
||||
1 file changed, 2 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
@@ -32,13 +32,11 @@
|
||||
clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
|
||||
<&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
|
||||
<&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
|
||||
- <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
|
||||
- <&cru PCLK_XPCS>;
|
||||
+ <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
|
||||
clock-names = "stmmaceth", "mac_clk_rx",
|
||||
"mac_clk_tx", "clk_mac_refout",
|
||||
"aclk_mac", "pclk_mac",
|
||||
- "clk_mac_speed", "ptp_ref",
|
||||
- "pclk_xpcs";
|
||||
+ "clk_mac_speed", "ptp_ref";
|
||||
resets = <&cru SRST_A_GMAC0>;
|
||||
reset-names = "stmmaceth";
|
||||
rockchip,grf = <&grf>;
|
||||
|
|
@ -1,45 +0,0 @@
|
|||
From 9c19c531dc98d7ba49b44802a607042e763ebe21 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Wed, 15 Dec 2021 16:02:47 -0500
|
||||
Subject: [PATCH] phy: phy-rockchip-inno-usb2: support #address_cells = 2
|
||||
|
||||
New Rockchip devices have the usb phy nodes as standalone devices.
|
||||
These nodes have register nodes with #address_cells = 2, but only use 32
|
||||
bit addresses.
|
||||
|
||||
Adjust the driver to check if the returned address is "0", and adjust
|
||||
the index in that case.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20211215210252.120923-4-pgwipeout@gmail.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 11 ++++++++++-
|
||||
1 file changed, 10 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -1100,12 +1100,21 @@ static int rockchip_usb2phy_probe(struct
|
||||
rphy->usbgrf = NULL;
|
||||
}
|
||||
|
||||
- if (of_property_read_u32(np, "reg", ®)) {
|
||||
+ if (of_property_read_u32_index(np, "reg", 0, ®)) {
|
||||
dev_err(dev, "the reg property is not assigned in %pOFn node\n",
|
||||
np);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
+ /* support address_cells=2 */
|
||||
+ if (reg == 0) {
|
||||
+ if (of_property_read_u32_index(np, "reg", 1, ®)) {
|
||||
+ dev_err(dev, "the reg property is not assigned in %pOFn node\n",
|
||||
+ np);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
rphy->dev = dev;
|
||||
phy_cfgs = match->data;
|
||||
rphy->chg_state = USB_CHG_STATE_UNDEFINED;
|
||||
|
|
@ -1,44 +0,0 @@
|
|||
From e6915e1acca57bc4fdb61dccd5cc2e49f72ef743 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Wed, 15 Dec 2021 16:02:48 -0500
|
||||
Subject: [PATCH] phy: phy-rockchip-inno-usb2: support standalone phy nodes
|
||||
|
||||
New Rockchip devices have the usb2 phy devices as standalone nodes
|
||||
instead of children of the grf node.
|
||||
Allow the driver to find the grf node from a phandle.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20211215210252.120923-5-pgwipeout@gmail.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 17 ++++++++++++-----
|
||||
1 file changed, 12 insertions(+), 5 deletions(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -1083,12 +1083,19 @@ static int rockchip_usb2phy_probe(struct
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
- if (!dev->parent || !dev->parent->of_node)
|
||||
- return -EINVAL;
|
||||
+ if (!dev->parent || !dev->parent->of_node) {
|
||||
+ rphy->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbgrf");
|
||||
+ if (IS_ERR(rphy->grf)) {
|
||||
+ dev_err(dev, "failed to locate usbgrf\n");
|
||||
+ return PTR_ERR(rphy->grf);
|
||||
+ }
|
||||
+ }
|
||||
|
||||
- rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
|
||||
- if (IS_ERR(rphy->grf))
|
||||
- return PTR_ERR(rphy->grf);
|
||||
+ else {
|
||||
+ rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
|
||||
+ if (IS_ERR(rphy->grf))
|
||||
+ return PTR_ERR(rphy->grf);
|
||||
+ }
|
||||
|
||||
if (of_device_is_compatible(np, "rockchip,rv1108-usb2phy")) {
|
||||
rphy->usbgrf =
|
||||
|
|
@ -1,237 +0,0 @@
|
|||
From ed2b5a8e6b98d042b323afbe177a5dc618921b31 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Wed, 15 Dec 2021 16:02:49 -0500
|
||||
Subject: [PATCH] phy: phy-rockchip-inno-usb2: support muxed interrupts
|
||||
|
||||
The rk3568 usb2phy has a single muxed interrupt that handles all
|
||||
interrupts.
|
||||
Allow the driver to plug in only a single interrupt as necessary.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20211215210252.120923-6-pgwipeout@gmail.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 168 +++++++++++++-----
|
||||
1 file changed, 119 insertions(+), 49 deletions(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -204,6 +204,7 @@ struct rockchip_usb2phy_port {
|
||||
* @dcd_retries: The retry count used to track Data contact
|
||||
* detection process.
|
||||
* @edev: extcon device for notification registration
|
||||
+ * @irq: muxed interrupt for single irq configuration
|
||||
* @phy_cfg: phy register configuration, assigned by driver data.
|
||||
* @ports: phy port instance.
|
||||
*/
|
||||
@@ -218,6 +219,7 @@ struct rockchip_usb2phy {
|
||||
enum power_supply_type chg_type;
|
||||
u8 dcd_retries;
|
||||
struct extcon_dev *edev;
|
||||
+ int irq;
|
||||
const struct rockchip_usb2phy_cfg *phy_cfg;
|
||||
struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS];
|
||||
};
|
||||
@@ -936,6 +938,102 @@ static irqreturn_t rockchip_usb2phy_otg_
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
+static irqreturn_t rockchip_usb2phy_irq(int irq, void *data)
|
||||
+{
|
||||
+ struct rockchip_usb2phy *rphy = data;
|
||||
+ struct rockchip_usb2phy_port *rport;
|
||||
+ irqreturn_t ret = IRQ_NONE;
|
||||
+ unsigned int index;
|
||||
+
|
||||
+ for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
|
||||
+ rport = &rphy->ports[index];
|
||||
+ if (!rport->phy)
|
||||
+ continue;
|
||||
+
|
||||
+ /* Handle linestate irq for both otg port and host port */
|
||||
+ ret = rockchip_usb2phy_linestate_irq(irq, rport);
|
||||
+ }
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int rockchip_usb2phy_port_irq_init(struct rockchip_usb2phy *rphy,
|
||||
+ struct rockchip_usb2phy_port *rport,
|
||||
+ struct device_node *child_np)
|
||||
+{
|
||||
+ int ret;
|
||||
+
|
||||
+ /*
|
||||
+ * If the usb2 phy used combined irq for otg and host port,
|
||||
+ * don't need to init otg and host port irq separately.
|
||||
+ */
|
||||
+ if (rphy->irq > 0)
|
||||
+ return 0;
|
||||
+
|
||||
+ switch (rport->port_id) {
|
||||
+ case USB2PHY_PORT_HOST:
|
||||
+ rport->ls_irq = of_irq_get_byname(child_np, "linestate");
|
||||
+ if (rport->ls_irq < 0) {
|
||||
+ dev_err(rphy->dev, "no linestate irq provided\n");
|
||||
+ return rport->ls_irq;
|
||||
+ }
|
||||
+
|
||||
+ ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
|
||||
+ rockchip_usb2phy_linestate_irq,
|
||||
+ IRQF_ONESHOT,
|
||||
+ "rockchip_usb2phy", rport);
|
||||
+ if (ret) {
|
||||
+ dev_err(rphy->dev, "failed to request linestate irq handle\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+ break;
|
||||
+ case USB2PHY_PORT_OTG:
|
||||
+ /*
|
||||
+ * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate
|
||||
+ * interrupts muxed together, so probe the otg-mux interrupt first,
|
||||
+ * if not found, then look for the regular interrupts one by one.
|
||||
+ */
|
||||
+ rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux");
|
||||
+ if (rport->otg_mux_irq > 0) {
|
||||
+ ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq,
|
||||
+ NULL,
|
||||
+ rockchip_usb2phy_otg_mux_irq,
|
||||
+ IRQF_ONESHOT,
|
||||
+ "rockchip_usb2phy_otg",
|
||||
+ rport);
|
||||
+ if (ret) {
|
||||
+ dev_err(rphy->dev,
|
||||
+ "failed to request otg-mux irq handle\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+ } else {
|
||||
+ rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
|
||||
+ if (rport->bvalid_irq < 0) {
|
||||
+ dev_err(rphy->dev, "no vbus valid irq provided\n");
|
||||
+ ret = rport->bvalid_irq;
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq,
|
||||
+ NULL,
|
||||
+ rockchip_usb2phy_bvalid_irq,
|
||||
+ IRQF_ONESHOT,
|
||||
+ "rockchip_usb2phy_bvalid",
|
||||
+ rport);
|
||||
+ if (ret) {
|
||||
+ dev_err(rphy->dev,
|
||||
+ "failed to request otg-bvalid irq handle\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+ }
|
||||
+ break;
|
||||
+ default:
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
|
||||
struct rockchip_usb2phy_port *rport,
|
||||
struct device_node *child_np)
|
||||
@@ -949,18 +1047,9 @@ static int rockchip_usb2phy_host_port_in
|
||||
mutex_init(&rport->mutex);
|
||||
INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
|
||||
|
||||
- rport->ls_irq = of_irq_get_byname(child_np, "linestate");
|
||||
- if (rport->ls_irq < 0) {
|
||||
- dev_err(rphy->dev, "no linestate irq provided\n");
|
||||
- return rport->ls_irq;
|
||||
- }
|
||||
-
|
||||
- ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
|
||||
- rockchip_usb2phy_linestate_irq,
|
||||
- IRQF_ONESHOT,
|
||||
- "rockchip_usb2phy", rport);
|
||||
+ ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np);
|
||||
if (ret) {
|
||||
- dev_err(rphy->dev, "failed to request linestate irq handle\n");
|
||||
+ dev_err(rphy->dev, "failed to setup host irq\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -1009,44 +1098,10 @@ static int rockchip_usb2phy_otg_port_ini
|
||||
INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
|
||||
INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
|
||||
|
||||
- /*
|
||||
- * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate
|
||||
- * interrupts muxed together, so probe the otg-mux interrupt first,
|
||||
- * if not found, then look for the regular interrupts one by one.
|
||||
- */
|
||||
- rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux");
|
||||
- if (rport->otg_mux_irq > 0) {
|
||||
- ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq,
|
||||
- NULL,
|
||||
- rockchip_usb2phy_otg_mux_irq,
|
||||
- IRQF_ONESHOT,
|
||||
- "rockchip_usb2phy_otg",
|
||||
- rport);
|
||||
- if (ret) {
|
||||
- dev_err(rphy->dev,
|
||||
- "failed to request otg-mux irq handle\n");
|
||||
- goto out;
|
||||
- }
|
||||
- } else {
|
||||
- rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
|
||||
- if (rport->bvalid_irq < 0) {
|
||||
- dev_err(rphy->dev, "no vbus valid irq provided\n");
|
||||
- ret = rport->bvalid_irq;
|
||||
- goto out;
|
||||
- }
|
||||
-
|
||||
- ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq,
|
||||
- NULL,
|
||||
- rockchip_usb2phy_bvalid_irq,
|
||||
- IRQF_ONESHOT,
|
||||
- "rockchip_usb2phy_bvalid",
|
||||
- rport);
|
||||
- if (ret) {
|
||||
- dev_err(rphy->dev,
|
||||
- "failed to request otg-bvalid irq handle\n");
|
||||
- goto out;
|
||||
- }
|
||||
- }
|
||||
+ ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np);
|
||||
+ if (ret) {
|
||||
+ dev_err(rphy->dev, "failed to init irq for host port\n");
|
||||
+ goto out;
|
||||
|
||||
if (!IS_ERR(rphy->edev)) {
|
||||
rport->event_nb.notifier_call = rockchip_otg_event;
|
||||
@@ -1126,6 +1181,7 @@ static int rockchip_usb2phy_probe(struct
|
||||
phy_cfgs = match->data;
|
||||
rphy->chg_state = USB_CHG_STATE_UNDEFINED;
|
||||
rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
|
||||
+ rphy->irq = platform_get_irq_optional(pdev, 0);
|
||||
platform_set_drvdata(pdev, rphy);
|
||||
|
||||
ret = rockchip_usb2phy_extcon_register(rphy);
|
||||
@@ -1205,6 +1261,20 @@ next_child:
|
||||
}
|
||||
|
||||
provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
||||
+
|
||||
+ if (rphy->irq > 0) {
|
||||
+ ret = devm_request_threaded_irq(rphy->dev, rphy->irq, NULL,
|
||||
+ rockchip_usb2phy_irq,
|
||||
+ IRQF_ONESHOT,
|
||||
+ "rockchip_usb2phy",
|
||||
+ rphy);
|
||||
+ if (ret) {
|
||||
+ dev_err(rphy->dev,
|
||||
+ "failed to request usb2phy irq handle\n");
|
||||
+ goto put_child;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
return PTR_ERR_OR_ZERO(provider);
|
||||
|
||||
put_child:
|
||||
|
|
@ -1,104 +0,0 @@
|
|||
From 42b559727a45d79c811f493515eb9b7e56016421 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Wed, 15 Dec 2021 16:02:50 -0500
|
||||
Subject: [PATCH] phy: phy-rockchip-inno-usb2: add rk3568 support
|
||||
|
||||
The rk3568 usb2phy is a standalone device with a single muxed interrupt.
|
||||
Add support for the registers to the usb2phy driver.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20211215210252.120923-7-pgwipeout@gmail.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 65 +++++++++++++++++++
|
||||
1 file changed, 65 insertions(+)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -1102,6 +1102,7 @@ static int rockchip_usb2phy_otg_port_ini
|
||||
if (ret) {
|
||||
dev_err(rphy->dev, "failed to init irq for host port\n");
|
||||
goto out;
|
||||
+ }
|
||||
|
||||
if (!IS_ERR(rphy->edev)) {
|
||||
rport->event_nb.notifier_call = rockchip_otg_event;
|
||||
@@ -1513,6 +1514,69 @@ static const struct rockchip_usb2phy_cfg
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
+static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
|
||||
+ {
|
||||
+ .reg = 0xfe8a0000,
|
||||
+ .num_ports = 2,
|
||||
+ .clkout_ctl = { 0x0008, 4, 4, 1, 0 },
|
||||
+ .port_cfgs = {
|
||||
+ [USB2PHY_PORT_OTG] = {
|
||||
+ .phy_sus = { 0x0000, 8, 0, 0, 0x1d1 },
|
||||
+ .bvalid_det_en = { 0x0080, 2, 2, 0, 1 },
|
||||
+ .bvalid_det_st = { 0x0084, 2, 2, 0, 1 },
|
||||
+ .bvalid_det_clr = { 0x0088, 2, 2, 0, 1 },
|
||||
+ .utmi_avalid = { 0x00c0, 10, 10, 0, 1 },
|
||||
+ .utmi_bvalid = { 0x00c0, 9, 9, 0, 1 },
|
||||
+ },
|
||||
+ [USB2PHY_PORT_HOST] = {
|
||||
+ /* Select suspend control from controller */
|
||||
+ .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d2 },
|
||||
+ .ls_det_en = { 0x0080, 1, 1, 0, 1 },
|
||||
+ .ls_det_st = { 0x0084, 1, 1, 0, 1 },
|
||||
+ .ls_det_clr = { 0x0088, 1, 1, 0, 1 },
|
||||
+ .utmi_ls = { 0x00c0, 17, 16, 0, 1 },
|
||||
+ .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 }
|
||||
+ }
|
||||
+ },
|
||||
+ .chg_det = {
|
||||
+ .opmode = { 0x0000, 3, 0, 5, 1 },
|
||||
+ .cp_det = { 0x00c0, 24, 24, 0, 1 },
|
||||
+ .dcp_det = { 0x00c0, 23, 23, 0, 1 },
|
||||
+ .dp_det = { 0x00c0, 25, 25, 0, 1 },
|
||||
+ .idm_sink_en = { 0x0008, 8, 8, 0, 1 },
|
||||
+ .idp_sink_en = { 0x0008, 7, 7, 0, 1 },
|
||||
+ .idp_src_en = { 0x0008, 9, 9, 0, 1 },
|
||||
+ .rdm_pdwn_en = { 0x0008, 10, 10, 0, 1 },
|
||||
+ .vdm_src_en = { 0x0008, 12, 12, 0, 1 },
|
||||
+ .vdp_src_en = { 0x0008, 11, 11, 0, 1 },
|
||||
+ },
|
||||
+ },
|
||||
+ {
|
||||
+ .reg = 0xfe8b0000,
|
||||
+ .num_ports = 2,
|
||||
+ .clkout_ctl = { 0x0008, 4, 4, 1, 0 },
|
||||
+ .port_cfgs = {
|
||||
+ [USB2PHY_PORT_OTG] = {
|
||||
+ .phy_sus = { 0x0000, 8, 0, 0x1d2, 0x1d1 },
|
||||
+ .ls_det_en = { 0x0080, 0, 0, 0, 1 },
|
||||
+ .ls_det_st = { 0x0084, 0, 0, 0, 1 },
|
||||
+ .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
|
||||
+ .utmi_ls = { 0x00c0, 5, 4, 0, 1 },
|
||||
+ .utmi_hstdet = { 0x00c0, 7, 7, 0, 1 }
|
||||
+ },
|
||||
+ [USB2PHY_PORT_HOST] = {
|
||||
+ .phy_sus = { 0x0004, 8, 0, 0x1d2, 0x1d1 },
|
||||
+ .ls_det_en = { 0x0080, 1, 1, 0, 1 },
|
||||
+ .ls_det_st = { 0x0084, 1, 1, 0, 1 },
|
||||
+ .ls_det_clr = { 0x0088, 1, 1, 0, 1 },
|
||||
+ .utmi_ls = { 0x00c0, 17, 16, 0, 1 },
|
||||
+ .utmi_hstdet = { 0x00c0, 19, 19, 0, 1 }
|
||||
+ }
|
||||
+ },
|
||||
+ },
|
||||
+ { /* sentinel */ }
|
||||
+};
|
||||
+
|
||||
static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
|
||||
{
|
||||
.reg = 0x100,
|
||||
@@ -1562,6 +1626,7 @@ static const struct of_device_id rockchi
|
||||
{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
|
||||
{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
|
||||
{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
|
||||
+ { .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
|
||||
{ .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs },
|
||||
{}
|
||||
};
|
||||
|
|
@ -1,105 +0,0 @@
|
|||
From 78f7186095db5a64009d44c18843a03dbc72d896 Mon Sep 17 00:00:00 2001
|
||||
From: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Date: Thu, 27 Jan 2022 20:04:55 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: rename and sort the rk356x usb2 phy
|
||||
handles
|
||||
|
||||
All nodes and handles related to USB have the prefix usb or usb2,
|
||||
whereas the phy handles are prefixed with u2phy. Rename for
|
||||
consistency reasons and to facilitate sorting.
|
||||
|
||||
This patch also updates the handles in the only board file that
|
||||
uses them (rk3566-quartz64-a.dts).
|
||||
|
||||
Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20220127190456.2195527-1-michael.riesch@wolfvision.net
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
.../boot/dts/rockchip/rk3566-quartz64-a.dts | 18 ++++++++---------
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 20 +++++++++----------
|
||||
2 files changed, 19 insertions(+), 19 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -214,7 +214,7 @@
|
||||
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
|
||||
<&cru PCLK_USB>;
|
||||
- phys = <&u2phy1_otg>;
|
||||
+ phys = <&usb2phy1_otg>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -225,7 +225,7 @@
|
||||
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
|
||||
<&cru PCLK_USB>;
|
||||
- phys = <&u2phy1_otg>;
|
||||
+ phys = <&usb2phy1_otg>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -236,7 +236,7 @@
|
||||
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
|
||||
<&cru PCLK_USB>;
|
||||
- phys = <&u2phy1_host>;
|
||||
+ phys = <&usb2phy1_host>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -247,7 +247,7 @@
|
||||
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
|
||||
<&cru PCLK_USB>;
|
||||
- phys = <&u2phy1_host>;
|
||||
+ phys = <&usb2phy1_host>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -1195,7 +1195,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
- u2phy0: usb2phy@fe8a0000 {
|
||||
+ usb2phy0: usb2phy@fe8a0000 {
|
||||
compatible = "rockchip,rk3568-usb2phy";
|
||||
reg = <0x0 0xfe8a0000 0x0 0x10000>;
|
||||
clocks = <&pmucru CLK_USBPHY0_REF>;
|
||||
@@ -1206,18 +1206,18 @@
|
||||
#clock-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
- u2phy0_host: host-port {
|
||||
+ usb2phy0_host: host-port {
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
- u2phy0_otg: otg-port {
|
||||
+ usb2phy0_otg: otg-port {
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
- u2phy1: usb2phy@fe8b0000 {
|
||||
+ usb2phy1: usb2phy@fe8b0000 {
|
||||
compatible = "rockchip,rk3568-usb2phy";
|
||||
reg = <0x0 0xfe8b0000 0x0 0x10000>;
|
||||
clocks = <&pmucru CLK_USBPHY1_REF>;
|
||||
@@ -1228,12 +1228,12 @@
|
||||
#clock-cells = <0>;
|
||||
status = "disabled";
|
||||
|
||||
- u2phy1_host: host-port {
|
||||
+ usb2phy1_host: host-port {
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
- u2phy1_otg: otg-port {
|
||||
+ usb2phy1_otg: otg-port {
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -1,633 +0,0 @@
|
|||
From 7160820d742a16313f7802e33c2956c19548e488 Mon Sep 17 00:00:00 2001
|
||||
From: Yifeng Zhao <yifeng.zhao@rock-chips.com>
|
||||
Date: Tue, 8 Feb 2022 17:13:25 +0800
|
||||
Subject: [PATCH] phy: rockchip: add naneng combo phy for RK3568
|
||||
|
||||
This patch implements a combo phy driver for Rockchip SoCs
|
||||
with NaNeng IP block. This phy can be used as pcie-phy, usb3-phy,
|
||||
sata-phy or sgmii-phy.
|
||||
|
||||
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
|
||||
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
|
||||
Tested-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Tested-by: Frank Wunderlich <frank-w@public-files.de>
|
||||
Link: https://lore.kernel.org/r/20220208091326.12495-4-yifeng.zhao@rock-chips.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/Kconfig | 8 +
|
||||
drivers/phy/rockchip/Makefile | 1 +
|
||||
.../rockchip/phy-rockchip-naneng-combphy.c | 581 ++++++++++++++++++
|
||||
3 files changed, 590 insertions(+)
|
||||
create mode 100644 drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
|
||||
|
||||
--- a/drivers/phy/rockchip/Kconfig
|
||||
+++ b/drivers/phy/rockchip/Kconfig
|
||||
@@ -66,6 +66,14 @@ config PHY_ROCKCHIP_INNO_DSIDPHY
|
||||
Enable this to support the Rockchip MIPI/LVDS/TTL PHY with
|
||||
Innosilicon IP block.
|
||||
|
||||
+config PHY_ROCKCHIP_NANENG_COMBO_PHY
|
||||
+ tristate "Rockchip NANENG COMBO PHY Driver"
|
||||
+ depends on ARCH_ROCKCHIP && OF
|
||||
+ select GENERIC_PHY
|
||||
+ help
|
||||
+ Enable this to support the Rockchip PCIe/USB3.0/SATA/QSGMII
|
||||
+ combo PHY with NaNeng IP block.
|
||||
+
|
||||
config PHY_ROCKCHIP_PCIE
|
||||
tristate "Rockchip PCIe PHY Driver"
|
||||
depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST
|
||||
--- a/drivers/phy/rockchip/Makefile
|
||||
+++ b/drivers/phy/rockchip/Makefile
|
||||
@@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY)
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) += phy-rockchip-inno-hdmi.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
|
||||
+obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
|
||||
@@ -0,0 +1,581 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0
|
||||
+/*
|
||||
+ * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
|
||||
+ *
|
||||
+ * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
|
||||
+ */
|
||||
+
|
||||
+#include <dt-bindings/phy/phy.h>
|
||||
+#include <linux/clk.h>
|
||||
+#include <linux/mfd/syscon.h>
|
||||
+#include <linux/of_device.h>
|
||||
+#include <linux/phy/phy.h>
|
||||
+#include <linux/regmap.h>
|
||||
+#include <linux/reset.h>
|
||||
+#include <linux/units.h>
|
||||
+
|
||||
+#define BIT_WRITEABLE_SHIFT 16
|
||||
+#define REF_CLOCK_24MHz (24 * HZ_PER_MHZ)
|
||||
+#define REF_CLOCK_25MHz (25 * HZ_PER_MHZ)
|
||||
+#define REF_CLOCK_100MHz (100 * HZ_PER_MHZ)
|
||||
+
|
||||
+/* COMBO PHY REG */
|
||||
+#define PHYREG6 0x14
|
||||
+#define PHYREG6_PLL_DIV_MASK GENMASK(7, 6)
|
||||
+#define PHYREG6_PLL_DIV_SHIFT 6
|
||||
+#define PHYREG6_PLL_DIV_2 1
|
||||
+
|
||||
+#define PHYREG7 0x18
|
||||
+#define PHYREG7_TX_RTERM_MASK GENMASK(7, 4)
|
||||
+#define PHYREG7_TX_RTERM_SHIFT 4
|
||||
+#define PHYREG7_TX_RTERM_50OHM 8
|
||||
+#define PHYREG7_RX_RTERM_MASK GENMASK(3, 0)
|
||||
+#define PHYREG7_RX_RTERM_SHIFT 0
|
||||
+#define PHYREG7_RX_RTERM_44OHM 15
|
||||
+
|
||||
+#define PHYREG8 0x1C
|
||||
+#define PHYREG8_SSC_EN BIT(4)
|
||||
+
|
||||
+#define PHYREG11 0x28
|
||||
+#define PHYREG11_SU_TRIM_0_7 0xF0
|
||||
+
|
||||
+#define PHYREG12 0x2C
|
||||
+#define PHYREG12_PLL_LPF_ADJ_VALUE 4
|
||||
+
|
||||
+#define PHYREG13 0x30
|
||||
+#define PHYREG13_RESISTER_MASK GENMASK(5, 4)
|
||||
+#define PHYREG13_RESISTER_SHIFT 0x4
|
||||
+#define PHYREG13_RESISTER_HIGH_Z 3
|
||||
+#define PHYREG13_CKRCV_AMP0 BIT(7)
|
||||
+
|
||||
+#define PHYREG14 0x34
|
||||
+#define PHYREG14_CKRCV_AMP1 BIT(0)
|
||||
+
|
||||
+#define PHYREG15 0x38
|
||||
+#define PHYREG15_CTLE_EN BIT(0)
|
||||
+#define PHYREG15_SSC_CNT_MASK GENMASK(7, 6)
|
||||
+#define PHYREG15_SSC_CNT_SHIFT 6
|
||||
+#define PHYREG15_SSC_CNT_VALUE 1
|
||||
+
|
||||
+#define PHYREG16 0x3C
|
||||
+#define PHYREG16_SSC_CNT_VALUE 0x5f
|
||||
+
|
||||
+#define PHYREG18 0x44
|
||||
+#define PHYREG18_PLL_LOOP 0x32
|
||||
+
|
||||
+#define PHYREG32 0x7C
|
||||
+#define PHYREG32_SSC_MASK GENMASK(7, 4)
|
||||
+#define PHYREG32_SSC_DIR_SHIFT 4
|
||||
+#define PHYREG32_SSC_UPWARD 0
|
||||
+#define PHYREG32_SSC_DOWNWARD 1
|
||||
+#define PHYREG32_SSC_OFFSET_SHIFT 6
|
||||
+#define PHYREG32_SSC_OFFSET_500PPM 1
|
||||
+
|
||||
+#define PHYREG33 0x80
|
||||
+#define PHYREG33_PLL_KVCO_MASK GENMASK(4, 2)
|
||||
+#define PHYREG33_PLL_KVCO_SHIFT 2
|
||||
+#define PHYREG33_PLL_KVCO_VALUE 2
|
||||
+
|
||||
+struct rockchip_combphy_priv;
|
||||
+
|
||||
+struct combphy_reg {
|
||||
+ u16 offset;
|
||||
+ u16 bitend;
|
||||
+ u16 bitstart;
|
||||
+ u16 disable;
|
||||
+ u16 enable;
|
||||
+};
|
||||
+
|
||||
+struct rockchip_combphy_grfcfg {
|
||||
+ struct combphy_reg pcie_mode_set;
|
||||
+ struct combphy_reg usb_mode_set;
|
||||
+ struct combphy_reg sgmii_mode_set;
|
||||
+ struct combphy_reg qsgmii_mode_set;
|
||||
+ struct combphy_reg pipe_rxterm_set;
|
||||
+ struct combphy_reg pipe_txelec_set;
|
||||
+ struct combphy_reg pipe_txcomp_set;
|
||||
+ struct combphy_reg pipe_clk_25m;
|
||||
+ struct combphy_reg pipe_clk_100m;
|
||||
+ struct combphy_reg pipe_phymode_sel;
|
||||
+ struct combphy_reg pipe_rate_sel;
|
||||
+ struct combphy_reg pipe_rxterm_sel;
|
||||
+ struct combphy_reg pipe_txelec_sel;
|
||||
+ struct combphy_reg pipe_txcomp_sel;
|
||||
+ struct combphy_reg pipe_clk_ext;
|
||||
+ struct combphy_reg pipe_sel_usb;
|
||||
+ struct combphy_reg pipe_sel_qsgmii;
|
||||
+ struct combphy_reg pipe_phy_status;
|
||||
+ struct combphy_reg con0_for_pcie;
|
||||
+ struct combphy_reg con1_for_pcie;
|
||||
+ struct combphy_reg con2_for_pcie;
|
||||
+ struct combphy_reg con3_for_pcie;
|
||||
+ struct combphy_reg con0_for_sata;
|
||||
+ struct combphy_reg con1_for_sata;
|
||||
+ struct combphy_reg con2_for_sata;
|
||||
+ struct combphy_reg con3_for_sata;
|
||||
+ struct combphy_reg pipe_con0_for_sata;
|
||||
+ struct combphy_reg pipe_xpcs_phy_ready;
|
||||
+};
|
||||
+
|
||||
+struct rockchip_combphy_cfg {
|
||||
+ const struct rockchip_combphy_grfcfg *grfcfg;
|
||||
+ int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
|
||||
+};
|
||||
+
|
||||
+struct rockchip_combphy_priv {
|
||||
+ u8 type;
|
||||
+ void __iomem *mmio;
|
||||
+ int num_clks;
|
||||
+ struct clk_bulk_data *clks;
|
||||
+ struct device *dev;
|
||||
+ struct regmap *pipe_grf;
|
||||
+ struct regmap *phy_grf;
|
||||
+ struct phy *phy;
|
||||
+ struct reset_control *phy_rst;
|
||||
+ const struct rockchip_combphy_cfg *cfg;
|
||||
+ bool enable_ssc;
|
||||
+ bool ext_refclk;
|
||||
+ struct clk *refclk;
|
||||
+};
|
||||
+
|
||||
+static void rockchip_combphy_updatel(struct rockchip_combphy_priv *priv,
|
||||
+ int mask, int val, int reg)
|
||||
+{
|
||||
+ unsigned int temp;
|
||||
+
|
||||
+ temp = readl(priv->mmio + reg);
|
||||
+ temp = (temp & ~(mask)) | val;
|
||||
+ writel(temp, priv->mmio + reg);
|
||||
+}
|
||||
+
|
||||
+static int rockchip_combphy_param_write(struct regmap *base,
|
||||
+ const struct combphy_reg *reg, bool en)
|
||||
+{
|
||||
+ u32 val, mask, tmp;
|
||||
+
|
||||
+ tmp = en ? reg->enable : reg->disable;
|
||||
+ mask = GENMASK(reg->bitend, reg->bitstart);
|
||||
+ val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
|
||||
+
|
||||
+ return regmap_write(base, reg->offset, val);
|
||||
+}
|
||||
+
|
||||
+static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv)
|
||||
+{
|
||||
+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
|
||||
+ u32 mask, val;
|
||||
+
|
||||
+ mask = GENMASK(cfg->pipe_phy_status.bitend,
|
||||
+ cfg->pipe_phy_status.bitstart);
|
||||
+
|
||||
+ regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val);
|
||||
+ val = (val & mask) >> cfg->pipe_phy_status.bitstart;
|
||||
+
|
||||
+ return val;
|
||||
+}
|
||||
+
|
||||
+static int rockchip_combphy_init(struct phy *phy)
|
||||
+{
|
||||
+ struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
|
||||
+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
|
||||
+ u32 val;
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
|
||||
+ if (ret) {
|
||||
+ dev_err(priv->dev, "failed to enable clks\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ switch (priv->type) {
|
||||
+ case PHY_TYPE_PCIE:
|
||||
+ case PHY_TYPE_USB3:
|
||||
+ case PHY_TYPE_SATA:
|
||||
+ case PHY_TYPE_SGMII:
|
||||
+ case PHY_TYPE_QSGMII:
|
||||
+ if (priv->cfg->combphy_cfg)
|
||||
+ ret = priv->cfg->combphy_cfg(priv);
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_err(priv->dev, "incompatible PHY type\n");
|
||||
+ ret = -EINVAL;
|
||||
+ break;
|
||||
+ }
|
||||
+
|
||||
+ if (ret) {
|
||||
+ dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type);
|
||||
+ goto err_clk;
|
||||
+ }
|
||||
+
|
||||
+ ret = reset_control_deassert(priv->phy_rst);
|
||||
+ if (ret)
|
||||
+ goto err_clk;
|
||||
+
|
||||
+ if (priv->type == PHY_TYPE_USB3) {
|
||||
+ ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready,
|
||||
+ priv, val,
|
||||
+ val == cfg->pipe_phy_status.enable,
|
||||
+ 10, 1000);
|
||||
+ if (ret)
|
||||
+ dev_warn(priv->dev, "wait phy status ready timeout\n");
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+
|
||||
+err_clk:
|
||||
+ clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int rockchip_combphy_exit(struct phy *phy)
|
||||
+{
|
||||
+ struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
|
||||
+
|
||||
+ clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
|
||||
+ reset_control_assert(priv->phy_rst);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct phy_ops rochchip_combphy_ops = {
|
||||
+ .init = rockchip_combphy_init,
|
||||
+ .exit = rockchip_combphy_exit,
|
||||
+ .owner = THIS_MODULE,
|
||||
+};
|
||||
+
|
||||
+static struct phy *rockchip_combphy_xlate(struct device *dev, struct of_phandle_args *args)
|
||||
+{
|
||||
+ struct rockchip_combphy_priv *priv = dev_get_drvdata(dev);
|
||||
+
|
||||
+ if (args->args_count != 1) {
|
||||
+ dev_err(dev, "invalid number of arguments\n");
|
||||
+ return ERR_PTR(-EINVAL);
|
||||
+ }
|
||||
+
|
||||
+ if (priv->type != PHY_NONE && priv->type != args->args[0])
|
||||
+ dev_warn(dev, "phy type select %d overwriting type %d\n",
|
||||
+ args->args[0], priv->type);
|
||||
+
|
||||
+ priv->type = args->args[0];
|
||||
+
|
||||
+ return priv->phy;
|
||||
+}
|
||||
+
|
||||
+static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv)
|
||||
+{
|
||||
+ int i;
|
||||
+
|
||||
+ priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
|
||||
+ if (priv->num_clks < 1)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ priv->refclk = NULL;
|
||||
+ for (i = 0; i < priv->num_clks; i++) {
|
||||
+ if (!strncmp(priv->clks[i].id, "ref", 3)) {
|
||||
+ priv->refclk = priv->clks[i].clk;
|
||||
+ break;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ if (!priv->refclk) {
|
||||
+ dev_err(dev, "no refclk found\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf");
|
||||
+ if (IS_ERR(priv->pipe_grf)) {
|
||||
+ dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n");
|
||||
+ return PTR_ERR(priv->pipe_grf);
|
||||
+ }
|
||||
+
|
||||
+ priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf");
|
||||
+ if (IS_ERR(priv->phy_grf)) {
|
||||
+ dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n");
|
||||
+ return PTR_ERR(priv->phy_grf);
|
||||
+ }
|
||||
+
|
||||
+ priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc");
|
||||
+
|
||||
+ priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk");
|
||||
+
|
||||
+ priv->phy_rst = devm_reset_control_array_get_exclusive(dev);
|
||||
+ if (IS_ERR(priv->phy_rst))
|
||||
+ return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n");
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rockchip_combphy_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct phy_provider *phy_provider;
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ struct rockchip_combphy_priv *priv;
|
||||
+ const struct rockchip_combphy_cfg *phy_cfg;
|
||||
+ struct resource *res;
|
||||
+ int ret;
|
||||
+
|
||||
+ phy_cfg = of_device_get_match_data(dev);
|
||||
+ if (!phy_cfg) {
|
||||
+ dev_err(dev, "no OF match data provided\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
+ if (!priv)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
|
||||
+ if (IS_ERR(priv->mmio)) {
|
||||
+ ret = PTR_ERR(priv->mmio);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ priv->dev = dev;
|
||||
+ priv->type = PHY_NONE;
|
||||
+ priv->cfg = phy_cfg;
|
||||
+
|
||||
+ ret = rockchip_combphy_parse_dt(dev, priv);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = reset_control_assert(priv->phy_rst);
|
||||
+ if (ret) {
|
||||
+ dev_err(dev, "failed to reset phy\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops);
|
||||
+ if (IS_ERR(priv->phy)) {
|
||||
+ dev_err(dev, "failed to create combphy\n");
|
||||
+ return PTR_ERR(priv->phy);
|
||||
+ }
|
||||
+
|
||||
+ dev_set_drvdata(dev, priv);
|
||||
+ phy_set_drvdata(priv->phy, priv);
|
||||
+
|
||||
+ phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate);
|
||||
+
|
||||
+ return PTR_ERR_OR_ZERO(phy_provider);
|
||||
+}
|
||||
+
|
||||
+static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
|
||||
+{
|
||||
+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
|
||||
+ unsigned long rate;
|
||||
+ u32 val;
|
||||
+
|
||||
+ switch (priv->type) {
|
||||
+ case PHY_TYPE_PCIE:
|
||||
+ /* Set SSC downward spread spectrum. */
|
||||
+ rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
|
||||
+ PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
|
||||
+ PHYREG32);
|
||||
+
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
|
||||
+ break;
|
||||
+
|
||||
+ case PHY_TYPE_USB3:
|
||||
+ /* Set SSC downward spread spectrum. */
|
||||
+ rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
|
||||
+ PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
|
||||
+ PHYREG32);
|
||||
+
|
||||
+ /* Enable adaptive CTLE for USB3.0 Rx. */
|
||||
+ val = readl(priv->mmio + PHYREG15);
|
||||
+ val |= PHYREG15_CTLE_EN;
|
||||
+ writel(val, priv->mmio + PHYREG15);
|
||||
+
|
||||
+ /* Set PLL KVCO fine tuning signals. */
|
||||
+ rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
|
||||
+ PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT,
|
||||
+ PHYREG33);
|
||||
+
|
||||
+ /* Enable controlling random jitter. */
|
||||
+ writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
|
||||
+
|
||||
+ /* Set PLL input clock divider 1/2. */
|
||||
+ rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
|
||||
+ PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT,
|
||||
+ PHYREG6);
|
||||
+
|
||||
+ writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
|
||||
+ writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
|
||||
+
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
|
||||
+ break;
|
||||
+
|
||||
+ case PHY_TYPE_SATA:
|
||||
+ /* Enable adaptive CTLE for SATA Rx. */
|
||||
+ val = readl(priv->mmio + PHYREG15);
|
||||
+ val |= PHYREG15_CTLE_EN;
|
||||
+ writel(val, priv->mmio + PHYREG15);
|
||||
+ /*
|
||||
+ * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA.
|
||||
+ * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm)
|
||||
+ */
|
||||
+ val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
|
||||
+ val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
|
||||
+ writel(val, priv->mmio + PHYREG7);
|
||||
+
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true);
|
||||
+ rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
|
||||
+ break;
|
||||
+
|
||||
+ case PHY_TYPE_SGMII:
|
||||
+ rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true);
|
||||
+ break;
|
||||
+
|
||||
+ case PHY_TYPE_QSGMII:
|
||||
+ rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true);
|
||||
+ break;
|
||||
+
|
||||
+ default:
|
||||
+ dev_err(priv->dev, "incompatible PHY type\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ rate = clk_get_rate(priv->refclk);
|
||||
+
|
||||
+ switch (rate) {
|
||||
+ case REF_CLOCK_24MHz:
|
||||
+ if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
|
||||
+ /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */
|
||||
+ val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT;
|
||||
+ rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
|
||||
+ val, PHYREG15);
|
||||
+
|
||||
+ writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
|
||||
+ }
|
||||
+ break;
|
||||
+
|
||||
+ case REF_CLOCK_25MHz:
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
|
||||
+ break;
|
||||
+
|
||||
+ case REF_CLOCK_100MHz:
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
|
||||
+ if (priv->type == PHY_TYPE_PCIE) {
|
||||
+ /* PLL KVCO fine tuning. */
|
||||
+ val = PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT;
|
||||
+ rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
|
||||
+ val, PHYREG33);
|
||||
+
|
||||
+ /* Enable controlling random jitter. */
|
||||
+ writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
|
||||
+
|
||||
+ val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT;
|
||||
+ rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
|
||||
+ val, PHYREG6);
|
||||
+
|
||||
+ writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
|
||||
+ writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
|
||||
+ } else if (priv->type == PHY_TYPE_SATA) {
|
||||
+ /* downward spread spectrum +500ppm */
|
||||
+ val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT;
|
||||
+ val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT;
|
||||
+ rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
|
||||
+ }
|
||||
+ break;
|
||||
+
|
||||
+ default:
|
||||
+ dev_err(priv->dev, "unsupported rate: %lu\n", rate);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ if (priv->ext_refclk) {
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
|
||||
+ if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
|
||||
+ val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
|
||||
+ val |= PHYREG13_CKRCV_AMP0;
|
||||
+ rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
|
||||
+
|
||||
+ val = readl(priv->mmio + PHYREG14);
|
||||
+ val |= PHYREG14_CKRCV_AMP1;
|
||||
+ writel(val, priv->mmio + PHYREG14);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ if (priv->enable_ssc) {
|
||||
+ val = readl(priv->mmio + PHYREG8);
|
||||
+ val |= PHYREG8_SSC_EN;
|
||||
+ writel(val, priv->mmio + PHYREG8);
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = {
|
||||
+ /* pipe-phy-grf */
|
||||
+ .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
|
||||
+ .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
|
||||
+ .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 },
|
||||
+ .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 },
|
||||
+ .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
|
||||
+ .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
|
||||
+ .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
|
||||
+ .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
|
||||
+ .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
|
||||
+ .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
|
||||
+ .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
|
||||
+ .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
|
||||
+ .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
|
||||
+ .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
|
||||
+ .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
|
||||
+ .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 },
|
||||
+ .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 },
|
||||
+ .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
|
||||
+ .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
|
||||
+ .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
|
||||
+ .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
|
||||
+ .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
|
||||
+ .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 },
|
||||
+ .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 },
|
||||
+ .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 },
|
||||
+ .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 },
|
||||
+ /* pipe-grf */
|
||||
+ .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 },
|
||||
+ .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 },
|
||||
+};
|
||||
+
|
||||
+static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
|
||||
+ .grfcfg = &rk3568_combphy_grfcfgs,
|
||||
+ .combphy_cfg = rk3568_combphy_cfg,
|
||||
+};
|
||||
+
|
||||
+static const struct of_device_id rockchip_combphy_of_match[] = {
|
||||
+ {
|
||||
+ .compatible = "rockchip,rk3568-naneng-combphy",
|
||||
+ .data = &rk3568_combphy_cfgs,
|
||||
+ },
|
||||
+ { },
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match);
|
||||
+
|
||||
+static struct platform_driver rockchip_combphy_driver = {
|
||||
+ .probe = rockchip_combphy_probe,
|
||||
+ .driver = {
|
||||
+ .name = "rockchip-naneng-combphy",
|
||||
+ .of_match_table = rockchip_combphy_of_match,
|
||||
+ },
|
||||
+};
|
||||
+module_platform_driver(rockchip_combphy_driver);
|
||||
+
|
||||
+MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver");
|
||||
+MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -1,122 +0,0 @@
|
|||
From 3cc8cd2d25954ed5794df2d190b81c7325c584e3 Mon Sep 17 00:00:00 2001
|
||||
From: Yifeng Zhao <yifeng.zhao@rock-chips.com>
|
||||
Date: Tue, 8 Feb 2022 17:13:26 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: add naneng combo phy nodes for rk3568
|
||||
|
||||
Add the core dt-node for the rk3568's naneng combo phys.
|
||||
|
||||
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
|
||||
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
|
||||
Tested-by: Frank Wunderlich <frank-w@public-files.de>
|
||||
Link: https://lore.kernel.org/r/20220208091326.12495-5-yifeng.zhao@rock-chips.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 +++++++++++
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++++++++++++++++++++++++
|
||||
2 files changed, 68 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
@@ -8,6 +8,11 @@
|
||||
/ {
|
||||
compatible = "rockchip,rk3568";
|
||||
|
||||
+ pipe_phy_grf0: syscon@fdc70000 {
|
||||
+ compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
|
||||
+ reg = <0x0 0xfdc70000 0x0 0x1000>;
|
||||
+ };
|
||||
+
|
||||
qos_pcie3x1: qos@fe190080 {
|
||||
compatible = "rockchip,rk3568-qos", "syscon";
|
||||
reg = <0x0 0xfe190080 0x0 0x20>;
|
||||
@@ -69,6 +74,22 @@
|
||||
queue0 {};
|
||||
};
|
||||
};
|
||||
+
|
||||
+ combphy0: phy@fe820000 {
|
||||
+ compatible = "rockchip,rk3568-naneng-combphy";
|
||||
+ reg = <0x0 0xfe820000 0x0 0x100>;
|
||||
+ clocks = <&pmucru CLK_PCIEPHY0_REF>,
|
||||
+ <&cru PCLK_PIPEPHY0>,
|
||||
+ <&cru PCLK_PIPE>;
|
||||
+ clock-names = "ref", "apb", "pipe";
|
||||
+ assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
|
||||
+ assigned-clock-rates = <100000000>;
|
||||
+ resets = <&cru SRST_PIPEPHY0>;
|
||||
+ rockchip,pipe-grf = <&pipegrf>;
|
||||
+ rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
|
||||
+ #phy-cells = <1>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
};
|
||||
|
||||
&cpu0_opp_table {
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -262,11 +262,26 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ pipegrf: syscon@fdc50000 {
|
||||
+ compatible = "rockchip,rk3568-pipe-grf", "syscon";
|
||||
+ reg = <0x0 0xfdc50000 0x0 0x1000>;
|
||||
+ };
|
||||
+
|
||||
grf: syscon@fdc60000 {
|
||||
compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
|
||||
reg = <0x0 0xfdc60000 0x0 0x10000>;
|
||||
};
|
||||
|
||||
+ pipe_phy_grf1: syscon@fdc80000 {
|
||||
+ compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
|
||||
+ reg = <0x0 0xfdc80000 0x0 0x1000>;
|
||||
+ };
|
||||
+
|
||||
+ pipe_phy_grf2: syscon@fdc90000 {
|
||||
+ compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
|
||||
+ reg = <0x0 0xfdc90000 0x0 0x1000>;
|
||||
+ };
|
||||
+
|
||||
usb2phy0_grf: syscon@fdca0000 {
|
||||
compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
|
||||
reg = <0x0 0xfdca0000 0x0 0x8000>;
|
||||
@@ -1195,6 +1210,38 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ combphy1: phy@fe830000 {
|
||||
+ compatible = "rockchip,rk3568-naneng-combphy";
|
||||
+ reg = <0x0 0xfe830000 0x0 0x100>;
|
||||
+ clocks = <&pmucru CLK_PCIEPHY1_REF>,
|
||||
+ <&cru PCLK_PIPEPHY1>,
|
||||
+ <&cru PCLK_PIPE>;
|
||||
+ clock-names = "ref", "apb", "pipe";
|
||||
+ assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
|
||||
+ assigned-clock-rates = <100000000>;
|
||||
+ resets = <&cru SRST_PIPEPHY1>;
|
||||
+ rockchip,pipe-grf = <&pipegrf>;
|
||||
+ rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
|
||||
+ #phy-cells = <1>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ combphy2: phy@fe840000 {
|
||||
+ compatible = "rockchip,rk3568-naneng-combphy";
|
||||
+ reg = <0x0 0xfe840000 0x0 0x100>;
|
||||
+ clocks = <&pmucru CLK_PCIEPHY2_REF>,
|
||||
+ <&cru PCLK_PIPEPHY2>,
|
||||
+ <&cru PCLK_PIPE>;
|
||||
+ clock-names = "ref", "apb", "pipe";
|
||||
+ assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
|
||||
+ assigned-clock-rates = <100000000>;
|
||||
+ resets = <&cru SRST_PIPEPHY2>;
|
||||
+ rockchip,pipe-grf = <&pipegrf>;
|
||||
+ rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
|
||||
+ #phy-cells = <1>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
usb2phy0: usb2phy@fe8a0000 {
|
||||
compatible = "rockchip,rk3568-usb2phy";
|
||||
reg = <0x0 0xfe8a0000 0x0 0x10000>;
|
||||
|
|
@ -1,76 +0,0 @@
|
|||
From 16c0f95d9ed14f033b5f1bd37e96d257b60c198c Mon Sep 17 00:00:00 2001
|
||||
From: Frank Wunderlich <frank-w@public-files.de>
|
||||
Date: Fri, 11 Mar 2022 22:03:57 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add sata nodes to rk356x
|
||||
|
||||
RK356x supports up to 3 sata controllers which were compatible with the
|
||||
existing snps,dwc-ahci binding.
|
||||
|
||||
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
|
||||
Link: https://lore.kernel.org/r/20220311210357.222830-7-linux@fw-web.de
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 14 ++++++++++++
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 28 ++++++++++++++++++++++++
|
||||
2 files changed, 42 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
@@ -8,6 +8,20 @@
|
||||
/ {
|
||||
compatible = "rockchip,rk3568";
|
||||
|
||||
+ sata0: sata@fc000000 {
|
||||
+ compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
|
||||
+ reg = <0 0xfc000000 0 0x1000>;
|
||||
+ clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
|
||||
+ <&cru CLK_SATA0_RXOOB>;
|
||||
+ clock-names = "sata", "pmalive", "rxoob";
|
||||
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ phys = <&combphy0 PHY_TYPE_SATA>;
|
||||
+ phy-names = "sata-phy";
|
||||
+ ports-implemented = <0x1>;
|
||||
+ power-domains = <&power RK3568_PD_PIPE>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
pipe_phy_grf0: syscon@fdc70000 {
|
||||
compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
|
||||
reg = <0x0 0xfdc70000 0x0 0x1000>;
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -196,6 +196,34 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ sata1: sata@fc400000 {
|
||||
+ compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
|
||||
+ reg = <0 0xfc400000 0 0x1000>;
|
||||
+ clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
|
||||
+ <&cru CLK_SATA1_RXOOB>;
|
||||
+ clock-names = "sata", "pmalive", "rxoob";
|
||||
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ phys = <&combphy1 PHY_TYPE_SATA>;
|
||||
+ phy-names = "sata-phy";
|
||||
+ ports-implemented = <0x1>;
|
||||
+ power-domains = <&power RK3568_PD_PIPE>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ sata2: sata@fc800000 {
|
||||
+ compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
|
||||
+ reg = <0 0xfc800000 0 0x1000>;
|
||||
+ clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
|
||||
+ <&cru CLK_SATA2_RXOOB>;
|
||||
+ clock-names = "sata", "pmalive", "rxoob";
|
||||
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ phys = <&combphy2 PHY_TYPE_SATA>;
|
||||
+ phy-names = "sata-phy";
|
||||
+ ports-implemented = <0x1>;
|
||||
+ power-domains = <&power RK3568_PD_PIPE>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
gic: interrupt-controller@fd400000 {
|
||||
compatible = "arm,gic-v3";
|
||||
reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
|
||||
|
|
@ -1,46 +0,0 @@
|
|||
From 62b20e6e0dde8d5633e3d94b028f86fb24b31d22 Mon Sep 17 00:00:00 2001
|
||||
From: Bin Yang <yangbin@rock-chips.com>
|
||||
Date: Mon, 28 Feb 2022 08:56:56 -0500
|
||||
Subject: [PATCH] usb: dwc3: core: do not use 3.0 clock when operating in 2.0
|
||||
mode
|
||||
|
||||
In the 3.0 device core, if the core is programmed to operate in
|
||||
2.0 only, then setting the GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK makes
|
||||
the internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe)
|
||||
clock. Enabling this feature allows the pipe3 clock to be not-running
|
||||
when forcibly operating in 2.0 device mode.
|
||||
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20220228135700.1089526-6-pgwipeout@gmail.com
|
||||
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
||||
---
|
||||
drivers/usb/dwc3/core.c | 5 +++++
|
||||
drivers/usb/dwc3/core.h | 1 +
|
||||
2 files changed, 6 insertions(+)
|
||||
|
||||
--- a/drivers/usb/dwc3/core.c
|
||||
+++ b/drivers/usb/dwc3/core.c
|
||||
@@ -1090,6 +1090,11 @@ static int dwc3_core_init(struct dwc3 *d
|
||||
if (dwc->parkmode_disable_ss_quirk)
|
||||
reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
|
||||
|
||||
+ if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) &&
|
||||
+ (dwc->maximum_speed == USB_SPEED_HIGH ||
|
||||
+ dwc->maximum_speed == USB_SPEED_FULL))
|
||||
+ reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
|
||||
+
|
||||
dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
|
||||
}
|
||||
|
||||
--- a/drivers/usb/dwc3/core.h
|
||||
+++ b/drivers/usb/dwc3/core.h
|
||||
@@ -258,6 +258,7 @@
|
||||
/* Global User Control 1 Register */
|
||||
#define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT BIT(31)
|
||||
#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
|
||||
+#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT(26)
|
||||
#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
|
||||
#define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
|
||||
#define DWC3_GUCTL1_RESUME_OPMODE_HS_HOST BIT(10)
|
||||
|
|
@ -1,54 +0,0 @@
|
|||
From c4313e75001492f8a288d3ffd595544cbc880821 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Sat, 5 Mar 2022 16:58:34 -0500
|
||||
Subject: [PATCH] mmc: dw_mmc: Support setting f_min from host drivers
|
||||
|
||||
Host drivers may not be able to support frequencies as low as dw-mmc
|
||||
supports. Unfortunately f_min isn't available when the drv_data->init
|
||||
function is called, as the mmc_host struct hasn't been set up yet.
|
||||
|
||||
Support the host drivers saving the requested minimum frequency, so we
|
||||
can later set f_min when it is available.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20220305215835.2210388-2-pgwipeout@gmail.com
|
||||
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
||||
---
|
||||
drivers/mmc/host/dw_mmc.c | 7 ++++++-
|
||||
drivers/mmc/host/dw_mmc.h | 2 ++
|
||||
2 files changed, 8 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/mmc/host/dw_mmc.c
|
||||
+++ b/drivers/mmc/host/dw_mmc.c
|
||||
@@ -2853,7 +2853,12 @@ static int dw_mci_init_slot_caps(struct
|
||||
if (host->pdata->caps2)
|
||||
mmc->caps2 = host->pdata->caps2;
|
||||
|
||||
- mmc->f_min = DW_MCI_FREQ_MIN;
|
||||
+ /* if host has set a minimum_freq, we should respect it */
|
||||
+ if (host->minimum_speed)
|
||||
+ mmc->f_min = host->minimum_speed;
|
||||
+ else
|
||||
+ mmc->f_min = DW_MCI_FREQ_MIN;
|
||||
+
|
||||
if (!mmc->f_max)
|
||||
mmc->f_max = DW_MCI_FREQ_MAX;
|
||||
|
||||
--- a/drivers/mmc/host/dw_mmc.h
|
||||
+++ b/drivers/mmc/host/dw_mmc.h
|
||||
@@ -99,6 +99,7 @@ struct dw_mci_dma_slave {
|
||||
* @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
|
||||
* rate and timeout calculations.
|
||||
* @current_speed: Configured rate of the controller.
|
||||
+ * @minimum_speed: Stored minimum rate of the controller.
|
||||
* @fifoth_val: The value of FIFOTH register.
|
||||
* @verid: Denote Version ID.
|
||||
* @dev: Device associated with the MMC controller.
|
||||
@@ -200,6 +201,7 @@ struct dw_mci {
|
||||
|
||||
u32 bus_hz;
|
||||
u32 current_speed;
|
||||
+ u32 minimum_speed;
|
||||
u32 fifoth_val;
|
||||
u16 verid;
|
||||
struct device *dev;
|
||||
|
|
@ -1,79 +0,0 @@
|
|||
From 52c92286b71e28d88642a4a416f40fbdb6cbb46f Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Sat, 5 Mar 2022 16:58:35 -0500
|
||||
Subject: [PATCH] mmc: dw-mmc-rockchip: Fix handling invalid clock rates
|
||||
|
||||
The Rockchip rk356x ciu clock cannot be set as low as the dw-mmc
|
||||
hardware supports. This leads to a situation during card initialization
|
||||
where the clock is set lower than the clock driver can support. The
|
||||
dw-mmc-rockchip driver spews errors when this happens.
|
||||
For normal operation this only happens a few times during boot, but when
|
||||
cd-broken is enabled (in cases such as the SoQuartz module) this fires
|
||||
multiple times each poll cycle.
|
||||
|
||||
Fix this by testing the lowest possible frequency that the clock driver
|
||||
can support which is within the mmc specification. Divide that rate by
|
||||
the internal divider and set f_min to this.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20220305215835.2210388-3-pgwipeout@gmail.com
|
||||
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
|
||||
---
|
||||
drivers/mmc/host/dw_mmc-rockchip.c | 27 +++++++++++++++++++++++----
|
||||
1 file changed, 23 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/drivers/mmc/host/dw_mmc-rockchip.c
|
||||
+++ b/drivers/mmc/host/dw_mmc-rockchip.c
|
||||
@@ -15,7 +15,9 @@
|
||||
#include "dw_mmc.h"
|
||||
#include "dw_mmc-pltfm.h"
|
||||
|
||||
-#define RK3288_CLKGEN_DIV 2
|
||||
+#define RK3288_CLKGEN_DIV 2
|
||||
+
|
||||
+static const unsigned int freqs[] = { 100000, 200000, 300000, 400000 };
|
||||
|
||||
struct dw_mci_rockchip_priv_data {
|
||||
struct clk *drv_clk;
|
||||
@@ -51,7 +53,7 @@ static void dw_mci_rk3288_set_ios(struct
|
||||
|
||||
ret = clk_set_rate(host->ciu_clk, cclkin);
|
||||
if (ret)
|
||||
- dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
|
||||
+ dev_warn(host->dev, "failed to set rate %uHz err: %d\n", cclkin, ret);
|
||||
|
||||
bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
|
||||
if (bus_hz != host->bus_hz) {
|
||||
@@ -290,13 +292,30 @@ static int dw_mci_rk3288_parse_dt(struct
|
||||
|
||||
static int dw_mci_rockchip_init(struct dw_mci *host)
|
||||
{
|
||||
+ int ret, i;
|
||||
+
|
||||
/* It is slot 8 on Rockchip SoCs */
|
||||
host->sdio_id0 = 8;
|
||||
|
||||
- if (of_device_is_compatible(host->dev->of_node,
|
||||
- "rockchip,rk3288-dw-mshc"))
|
||||
+ if (of_device_is_compatible(host->dev->of_node, "rockchip,rk3288-dw-mshc")) {
|
||||
host->bus_hz /= RK3288_CLKGEN_DIV;
|
||||
|
||||
+ /* clock driver will fail if the clock is less than the lowest source clock
|
||||
+ * divided by the internal clock divider. Test for the lowest available
|
||||
+ * clock and set the minimum freq to clock / clock divider.
|
||||
+ */
|
||||
+
|
||||
+ for (i = 0; i < ARRAY_SIZE(freqs); i++) {
|
||||
+ ret = clk_round_rate(host->ciu_clk, freqs[i] * RK3288_CLKGEN_DIV);
|
||||
+ if (ret > 0) {
|
||||
+ host->minimum_speed = ret / RK3288_CLKGEN_DIV;
|
||||
+ break;
|
||||
+ }
|
||||
+ }
|
||||
+ if (ret < 0)
|
||||
+ dev_warn(host->dev, "no valid minimum freq: %d\n", ret);
|
||||
+ }
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
From 4d94b98f2e2407e3f053b2546f86c76179fea644 Mon Sep 17 00:00:00 2001
|
||||
From: Ondrej Jirman <megous@megous.com>
|
||||
Date: Sun, 29 Aug 2021 04:51:53 +0200
|
||||
Subject: [PATCH] mfd: rk808: Add support for power off on RK817
|
||||
|
||||
RK817 has a power-off bit in SYS_CFG3. Add support for powering
|
||||
off the PMIC.
|
||||
|
||||
Signed-off-by: Ondrej Jirman <megous@megous.com>
|
||||
Signed-off-by: Lee Jones <lee.jones@linaro.org>
|
||||
---
|
||||
drivers/mfd/rk808.c | 4 ++++
|
||||
1 file changed, 4 insertions(+)
|
||||
|
||||
--- a/drivers/mfd/rk808.c
|
||||
+++ b/drivers/mfd/rk808.c
|
||||
@@ -543,6 +543,10 @@ static void rk808_pm_power_off(void)
|
||||
reg = RK808_DEVCTRL_REG,
|
||||
bit = DEV_OFF_RST;
|
||||
break;
|
||||
+ case RK817_ID:
|
||||
+ reg = RK817_SYS_CFG(3);
|
||||
+ bit = DEV_OFF;
|
||||
+ break;
|
||||
case RK818_ID:
|
||||
reg = RK818_DEVCTRL_REG;
|
||||
bit = DEV_OFF;
|
||||
|
|
@ -1,110 +0,0 @@
|
|||
From 56f216d8efbc1212bf5ff8a6ff5e29927965e8db Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Tue, 8 Feb 2022 14:40:23 -0500
|
||||
Subject: [PATCH] mfd: rk808: Add reboot support to rk808.c
|
||||
|
||||
This adds reboot support to the rk808 pmic driver and enables it for
|
||||
the rk809 and rk817 devices.
|
||||
This only enables if the rockchip,system-power-controller flag is set.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
|
||||
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
|
||||
Signed-off-by: Lee Jones <lee.jones@linaro.org>
|
||||
Link: https://lore.kernel.org/r/20220208194023.929720-1-pgwipeout@gmail.com
|
||||
---
|
||||
drivers/mfd/rk808.c | 44 +++++++++++++++++++++++++++++++++++++++
|
||||
include/linux/mfd/rk808.h | 1 +
|
||||
2 files changed, 45 insertions(+)
|
||||
|
||||
--- a/drivers/mfd/rk808.c
|
||||
+++ b/drivers/mfd/rk808.c
|
||||
@@ -19,6 +19,7 @@
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/regmap.h>
|
||||
+#include <linux/reboot.h>
|
||||
|
||||
struct rk808_reg_data {
|
||||
int addr;
|
||||
@@ -543,6 +544,7 @@ static void rk808_pm_power_off(void)
|
||||
reg = RK808_DEVCTRL_REG,
|
||||
bit = DEV_OFF_RST;
|
||||
break;
|
||||
+ case RK809_ID:
|
||||
case RK817_ID:
|
||||
reg = RK817_SYS_CFG(3);
|
||||
bit = DEV_OFF;
|
||||
@@ -559,6 +561,34 @@ static void rk808_pm_power_off(void)
|
||||
dev_err(&rk808_i2c_client->dev, "Failed to shutdown device!\n");
|
||||
}
|
||||
|
||||
+static int rk808_restart_notify(struct notifier_block *this, unsigned long mode, void *cmd)
|
||||
+{
|
||||
+ struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client);
|
||||
+ unsigned int reg, bit;
|
||||
+ int ret;
|
||||
+
|
||||
+ switch (rk808->variant) {
|
||||
+ case RK809_ID:
|
||||
+ case RK817_ID:
|
||||
+ reg = RK817_SYS_CFG(3);
|
||||
+ bit = DEV_RST;
|
||||
+ break;
|
||||
+
|
||||
+ default:
|
||||
+ return NOTIFY_DONE;
|
||||
+ }
|
||||
+ ret = regmap_update_bits(rk808->regmap, reg, bit, bit);
|
||||
+ if (ret)
|
||||
+ dev_err(&rk808_i2c_client->dev, "Failed to restart device!\n");
|
||||
+
|
||||
+ return NOTIFY_DONE;
|
||||
+}
|
||||
+
|
||||
+static struct notifier_block rk808_restart_handler = {
|
||||
+ .notifier_call = rk808_restart_notify,
|
||||
+ .priority = 192,
|
||||
+};
|
||||
+
|
||||
static void rk8xx_shutdown(struct i2c_client *client)
|
||||
{
|
||||
struct rk808 *rk808 = i2c_get_clientdata(client);
|
||||
@@ -727,6 +757,18 @@ static int rk808_probe(struct i2c_client
|
||||
if (of_property_read_bool(np, "rockchip,system-power-controller")) {
|
||||
rk808_i2c_client = client;
|
||||
pm_power_off = rk808_pm_power_off;
|
||||
+
|
||||
+ switch (rk808->variant) {
|
||||
+ case RK809_ID:
|
||||
+ case RK817_ID:
|
||||
+ ret = register_restart_handler(&rk808_restart_handler);
|
||||
+ if (ret)
|
||||
+ dev_warn(&client->dev, "failed to register rst handler, %d\n", ret);
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_dbg(&client->dev, "pmic controlled board reset not supported\n");
|
||||
+ break;
|
||||
+ }
|
||||
}
|
||||
|
||||
return 0;
|
||||
@@ -749,6 +791,8 @@ static int rk808_remove(struct i2c_clien
|
||||
if (pm_power_off == rk808_pm_power_off)
|
||||
pm_power_off = NULL;
|
||||
|
||||
+ unregister_restart_handler(&rk808_restart_handler);
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
--- a/include/linux/mfd/rk808.h
|
||||
+++ b/include/linux/mfd/rk808.h
|
||||
@@ -373,6 +373,7 @@ enum rk805_reg {
|
||||
#define SWITCH2_EN BIT(6)
|
||||
#define SWITCH1_EN BIT(5)
|
||||
#define DEV_OFF_RST BIT(3)
|
||||
+#define DEV_RST BIT(2)
|
||||
#define DEV_OFF BIT(0)
|
||||
#define RTC_STOP BIT(0)
|
||||
|
||||
|
|
@ -1,51 +0,0 @@
|
|||
From 5c0bb71138770d85ea840acd379edc6471b867ee Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Fri, 8 Apr 2022 11:12:34 -0400
|
||||
Subject: [PATCH] soc: rockchip: set dwc3 clock for rk3566
|
||||
|
||||
The rk3566 dwc3 otg port clock is unavailable at boot, as it defaults to
|
||||
the combophy as the clock source. As combophy0 doesn't exist on rk3566,
|
||||
we need to set the clock source to the usb2 phy instead.
|
||||
|
||||
Add handling to the grf driver to handle this on boot.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20220408151237.3165046-3-pgwipeout@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
drivers/soc/rockchip/grf.c | 17 +++++++++++++++++
|
||||
1 file changed, 17 insertions(+)
|
||||
|
||||
--- a/drivers/soc/rockchip/grf.c
|
||||
+++ b/drivers/soc/rockchip/grf.c
|
||||
@@ -108,6 +108,20 @@ static const struct rockchip_grf_info rk
|
||||
.num_values = ARRAY_SIZE(rk3399_defaults),
|
||||
};
|
||||
|
||||
+#define RK3566_GRF_USB3OTG0_CON1 0x0104
|
||||
+
|
||||
+static const struct rockchip_grf_value rk3566_defaults[] __initconst = {
|
||||
+ { "usb3otg port switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(0, 1, 12) },
|
||||
+ { "usb3otg clock switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 7) },
|
||||
+ { "usb3otg disable usb3", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 0) },
|
||||
+};
|
||||
+
|
||||
+static const struct rockchip_grf_info rk3566_pipegrf __initconst = {
|
||||
+ .values = rk3566_defaults,
|
||||
+ .num_values = ARRAY_SIZE(rk3566_defaults),
|
||||
+};
|
||||
+
|
||||
+
|
||||
static const struct of_device_id rockchip_grf_dt_match[] __initconst = {
|
||||
{
|
||||
.compatible = "rockchip,rk3036-grf",
|
||||
@@ -130,6 +144,9 @@ static const struct of_device_id rockchi
|
||||
}, {
|
||||
.compatible = "rockchip,rk3399-grf",
|
||||
.data = (void *)&rk3399_grf,
|
||||
+ }, {
|
||||
+ .compatible = "rockchip,rk3566-pipe-grf",
|
||||
+ .data = (void *)&rk3566_pipegrf,
|
||||
},
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
|
@ -1,118 +0,0 @@
|
|||
From 9f4c480f24e2ce1d464ff9d5f8a249a485acdc7f Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Fri, 8 Apr 2022 11:12:35 -0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: add rk356x dwc3 usb3 nodes
|
||||
|
||||
Add the dwc3 device nodes to the rk356x device trees.
|
||||
The rk3566 has one usb2 capable dwc3 otg controller and one usb3 capable
|
||||
dwc3 host controller.
|
||||
The rk3568 has one usb3 capable dwc3 otg controller and one usb3 capable
|
||||
dwc3 host controller.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Tested-by: Frank Wunderlich <frank-w@public-files.de>
|
||||
Link: https://lore.kernel.org/r/20220408151237.3165046-4-pgwipeout@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3566.dtsi | 11 ++++++++
|
||||
arch/arm64/boot/dts/rockchip/rk3568.dtsi | 9 ++++++
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 35 +++++++++++++++++++++++-
|
||||
3 files changed, 54 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
|
||||
@@ -6,6 +6,10 @@
|
||||
compatible = "rockchip,rk3566";
|
||||
};
|
||||
|
||||
+&pipegrf {
|
||||
+ compatible = "rockchip,rk3566-pipe-grf", "syscon";
|
||||
+};
|
||||
+
|
||||
&power {
|
||||
power-domain@RK3568_PD_PIPE {
|
||||
reg = <RK3568_PD_PIPE>;
|
||||
@@ -18,3 +22,10 @@
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
+
|
||||
+&usb_host0_xhci {
|
||||
+ phys = <&usb2phy0_otg>;
|
||||
+ phy-names = "usb2-phy";
|
||||
+ extcon = <&usb2phy0>;
|
||||
+ maximum-speed = "high-speed";
|
||||
+};
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
|
||||
@@ -113,6 +113,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&pipegrf {
|
||||
+ compatible = "rockchip,rk3568-pipe-grf", "syscon";
|
||||
+};
|
||||
+
|
||||
&power {
|
||||
power-domain@RK3568_PD_PIPE {
|
||||
reg = <RK3568_PD_PIPE>;
|
||||
@@ -128,3 +132,8 @@
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
+
|
||||
+&usb_host0_xhci {
|
||||
+ phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
|
||||
+ phy-names = "usb2-phy", "usb3-phy";
|
||||
+};
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -224,6 +224,40 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ usb_host0_xhci: usb@fcc00000 {
|
||||
+ compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
|
||||
+ reg = <0x0 0xfcc00000 0x0 0x400000>;
|
||||
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
|
||||
+ <&cru ACLK_USB3OTG0>;
|
||||
+ clock-names = "ref_clk", "suspend_clk",
|
||||
+ "bus_clk";
|
||||
+ dr_mode = "host";
|
||||
+ phy_type = "utmi_wide";
|
||||
+ power-domains = <&power RK3568_PD_PIPE>;
|
||||
+ resets = <&cru SRST_USB3OTG0>;
|
||||
+ snps,dis_u2_susphy_quirk;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ usb_host1_xhci: usb@fd000000 {
|
||||
+ compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
|
||||
+ reg = <0x0 0xfd000000 0x0 0x400000>;
|
||||
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
|
||||
+ <&cru ACLK_USB3OTG1>;
|
||||
+ clock-names = "ref_clk", "suspend_clk",
|
||||
+ "bus_clk";
|
||||
+ dr_mode = "host";
|
||||
+ phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>;
|
||||
+ phy-names = "usb2-phy", "usb3-phy";
|
||||
+ phy_type = "utmi_wide";
|
||||
+ power-domains = <&power RK3568_PD_PIPE>;
|
||||
+ resets = <&cru SRST_USB3OTG1>;
|
||||
+ snps,dis_u2_susphy_quirk;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
gic: interrupt-controller@fd400000 {
|
||||
compatible = "arm,gic-v3";
|
||||
reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
|
||||
@@ -291,7 +325,6 @@
|
||||
};
|
||||
|
||||
pipegrf: syscon@fdc50000 {
|
||||
- compatible = "rockchip,rk3568-pipe-grf", "syscon";
|
||||
reg = <0x0 0xfdc50000 0x0 0x1000>;
|
||||
};
|
||||
|
||||
|
|
@ -1,72 +0,0 @@
|
|||
From 431e7d2eece5b906578926d15ee22a70504c364d Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Fri, 29 Apr 2022 08:38:28 -0400
|
||||
Subject: [PATCH] PCI: rockchip-dwc: Reset core at driver probe
|
||||
|
||||
The PCIe controller is in an unknown state at driver probe. This can
|
||||
lead to undesireable effects when the driver attempts to configure the
|
||||
controller.
|
||||
|
||||
Prevent issues in the future by resetting the core during probe.
|
||||
|
||||
Link: https://lore.kernel.org/r/20220429123832.2376381-3-pgwipeout@gmail.com
|
||||
Tested-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
|
||||
---
|
||||
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 23 ++++++++-----------
|
||||
1 file changed, 10 insertions(+), 13 deletions(-)
|
||||
|
||||
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
|
||||
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
|
||||
@@ -152,6 +152,11 @@ static int rockchip_pcie_resource_get(st
|
||||
if (IS_ERR(rockchip->rst_gpio))
|
||||
return PTR_ERR(rockchip->rst_gpio);
|
||||
|
||||
+ rockchip->rst = devm_reset_control_array_get_exclusive(&pdev->dev);
|
||||
+ if (IS_ERR(rockchip->rst))
|
||||
+ return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->rst),
|
||||
+ "failed to get reset lines\n");
|
||||
+
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -182,18 +187,6 @@ static void rockchip_pcie_phy_deinit(str
|
||||
phy_power_off(rockchip->phy);
|
||||
}
|
||||
|
||||
-static int rockchip_pcie_reset_control_release(struct rockchip_pcie *rockchip)
|
||||
-{
|
||||
- struct device *dev = rockchip->pci.dev;
|
||||
-
|
||||
- rockchip->rst = devm_reset_control_array_get_exclusive(dev);
|
||||
- if (IS_ERR(rockchip->rst))
|
||||
- return dev_err_probe(dev, PTR_ERR(rockchip->rst),
|
||||
- "failed to get reset lines\n");
|
||||
-
|
||||
- return reset_control_deassert(rockchip->rst);
|
||||
-}
|
||||
-
|
||||
static const struct dw_pcie_ops dw_pcie_ops = {
|
||||
.link_up = rockchip_pcie_link_up,
|
||||
.start_link = rockchip_pcie_start_link,
|
||||
@@ -222,6 +215,10 @@ static int rockchip_pcie_probe(struct pl
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
+ ret = reset_control_assert(rockchip->rst);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
/* DON'T MOVE ME: must be enable before PHY init */
|
||||
rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
|
||||
if (IS_ERR(rockchip->vpcie3v3)) {
|
||||
@@ -241,7 +238,7 @@ static int rockchip_pcie_probe(struct pl
|
||||
if (ret)
|
||||
goto disable_regulator;
|
||||
|
||||
- ret = rockchip_pcie_reset_control_release(rockchip);
|
||||
+ ret = reset_control_deassert(rockchip->rst);
|
||||
if (ret)
|
||||
goto deinit_phy;
|
||||
|
||||
|
|
@ -1,163 +0,0 @@
|
|||
From e8aae154df6121167e5b4f156cfc2402e651d2b1 Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Fri, 29 Apr 2022 08:38:29 -0400
|
||||
Subject: [PATCH] PCI: rockchip-dwc: Add legacy interrupt support
|
||||
|
||||
The legacy interrupts on the rk356x PCIe controller are handled by a
|
||||
single muxed interrupt. Add IRQ domain support to the pcie-dw-rockchip
|
||||
driver to support the virtual domain.
|
||||
|
||||
Link: https://lore.kernel.org/r/20220429123832.2376381-4-pgwipeout@gmail.com
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
|
||||
Reviewed-by: Marc Zyngier <maz@kernel.org>
|
||||
---
|
||||
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 96 ++++++++++++++++++-
|
||||
1 file changed, 94 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
|
||||
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
|
||||
@@ -10,9 +10,12 @@
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/gpio/consumer.h>
|
||||
+#include <linux/irqchip/chained_irq.h>
|
||||
+#include <linux/irqdomain.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
+#include <linux/of_irq.h>
|
||||
#include <linux/phy/phy.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
@@ -26,6 +29,7 @@
|
||||
*/
|
||||
#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
|
||||
#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
|
||||
+#define HIWORD_DISABLE_BIT(val) HIWORD_UPDATE(val, ~val)
|
||||
|
||||
#define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)
|
||||
|
||||
@@ -36,10 +40,12 @@
|
||||
#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP)
|
||||
#define PCIE_L0S_ENTRY 0x11
|
||||
#define PCIE_CLIENT_GENERAL_CONTROL 0x0
|
||||
+#define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8
|
||||
+#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c
|
||||
#define PCIE_CLIENT_GENERAL_DEBUG 0x104
|
||||
-#define PCIE_CLIENT_HOT_RESET_CTRL 0x180
|
||||
+#define PCIE_CLIENT_HOT_RESET_CTRL 0x180
|
||||
#define PCIE_CLIENT_LTSSM_STATUS 0x300
|
||||
-#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
|
||||
+#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
|
||||
#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0)
|
||||
|
||||
struct rockchip_pcie {
|
||||
@@ -51,6 +57,7 @@ struct rockchip_pcie {
|
||||
struct reset_control *rst;
|
||||
struct gpio_desc *rst_gpio;
|
||||
struct regulator *vpcie3v3;
|
||||
+ struct irq_domain *irq_domain;
|
||||
};
|
||||
|
||||
static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip,
|
||||
@@ -65,6 +72,78 @@ static void rockchip_pcie_writel_apb(str
|
||||
writel_relaxed(val, rockchip->apb_base + reg);
|
||||
}
|
||||
|
||||
+static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
|
||||
+{
|
||||
+ struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
+ struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
|
||||
+ unsigned long reg, hwirq;
|
||||
+
|
||||
+ chained_irq_enter(chip, desc);
|
||||
+
|
||||
+ reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_LEGACY);
|
||||
+
|
||||
+ for_each_set_bit(hwirq, ®, 4)
|
||||
+ generic_handle_domain_irq(rockchip->irq_domain, hwirq);
|
||||
+
|
||||
+ chained_irq_exit(chip, desc);
|
||||
+}
|
||||
+
|
||||
+static void rockchip_intx_mask(struct irq_data *data)
|
||||
+{
|
||||
+ rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data),
|
||||
+ HIWORD_UPDATE_BIT(BIT(data->hwirq)),
|
||||
+ PCIE_CLIENT_INTR_MASK_LEGACY);
|
||||
+};
|
||||
+
|
||||
+static void rockchip_intx_unmask(struct irq_data *data)
|
||||
+{
|
||||
+ rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data),
|
||||
+ HIWORD_DISABLE_BIT(BIT(data->hwirq)),
|
||||
+ PCIE_CLIENT_INTR_MASK_LEGACY);
|
||||
+};
|
||||
+
|
||||
+static struct irq_chip rockchip_intx_irq_chip = {
|
||||
+ .name = "INTx",
|
||||
+ .irq_mask = rockchip_intx_mask,
|
||||
+ .irq_unmask = rockchip_intx_unmask,
|
||||
+ .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
|
||||
+};
|
||||
+
|
||||
+static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
|
||||
+ irq_hw_number_t hwirq)
|
||||
+{
|
||||
+ irq_set_chip_and_handler(irq, &rockchip_intx_irq_chip, handle_level_irq);
|
||||
+ irq_set_chip_data(irq, domain->host_data);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct irq_domain_ops intx_domain_ops = {
|
||||
+ .map = rockchip_pcie_intx_map,
|
||||
+};
|
||||
+
|
||||
+static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
|
||||
+{
|
||||
+ struct device *dev = rockchip->pci.dev;
|
||||
+ struct device_node *intc;
|
||||
+
|
||||
+ intc = of_get_child_by_name(dev->of_node, "legacy-interrupt-controller");
|
||||
+ if (!intc) {
|
||||
+ dev_err(dev, "missing child interrupt-controller node\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX,
|
||||
+ &intx_domain_ops, rockchip);
|
||||
+ of_node_put(intc);
|
||||
+ if (!rockchip->irq_domain) {
|
||||
+ dev_err(dev, "failed to get a INTx IRQ domain\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip)
|
||||
{
|
||||
rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM,
|
||||
@@ -111,7 +190,20 @@ static int rockchip_pcie_host_init(struc
|
||||
{
|
||||
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
||||
struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
|
||||
+ struct device *dev = rockchip->pci.dev;
|
||||
u32 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);
|
||||
+ int irq, ret;
|
||||
+
|
||||
+ irq = of_irq_get_byname(dev->of_node, "legacy");
|
||||
+ if (irq < 0)
|
||||
+ return irq;
|
||||
+
|
||||
+ ret = rockchip_pcie_init_irq_domain(rockchip);
|
||||
+ if (ret < 0)
|
||||
+ dev_err(dev, "failed to init irq domain\n");
|
||||
+
|
||||
+ irq_set_chained_handler_and_data(irq, rockchip_pcie_legacy_int_handler,
|
||||
+ rockchip);
|
||||
|
||||
/* LTSSM enable control mode */
|
||||
rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
|
||||
|
|
@ -1,35 +0,0 @@
|
|||
From 13e0ee34f39c01948a7bbaab0b3c225d9b00a5bb Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Fri, 29 Apr 2022 07:52:49 -0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: add rk356x sfc support
|
||||
|
||||
Add the sfc node to the rk356x device tree. This enables spi flash
|
||||
support for this soc.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20220429115252.2360496-5-pgwipeout@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 11 +++++++++++
|
||||
1 file changed, 11 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -729,6 +729,17 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ sfc: spi@fe300000 {
|
||||
+ compatible = "rockchip,sfc";
|
||||
+ reg = <0x0 0xfe300000 0x0 0x4000>;
|
||||
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
|
||||
+ clock-names = "clk_sfc", "hclk_sfc";
|
||||
+ pinctrl-0 = <&fspi_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
sdhci: mmc@fe310000 {
|
||||
compatible = "rockchip,rk3568-dwcmshc";
|
||||
reg = <0x0 0xfe310000 0x0 0x10000>;
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
From cd2d081d18de396cb45636c215dc589a330b3f4e Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Wed, 11 May 2022 11:01:13 -0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: add clocks to rk356x cru
|
||||
|
||||
The rk356x cru requires a 24m clock input to function. Add the clocks
|
||||
properties to the cru to clear some dtbs_check warnings.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20220511150117.113070-3-pgwipeout@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -363,6 +363,8 @@
|
||||
cru: clock-controller@fdd20000 {
|
||||
compatible = "rockchip,rk3568-cru";
|
||||
reg = <0x0 0xfdd20000 0x0 0x1000>;
|
||||
+ clocks = <&xin24m>;
|
||||
+ clock-names = "xin24m";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
|
||||
|
|
@ -1,74 +0,0 @@
|
|||
From 66b51ea7d70fcc2ede87161c413fe1db4422bdac Mon Sep 17 00:00:00 2001
|
||||
From: Peter Geis <pgwipeout@gmail.com>
|
||||
Date: Fri, 29 Apr 2022 08:38:30 -0400
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add rk3568 PCIe2x1 controller
|
||||
|
||||
The PCIe2x1 controller is common between the rk3568 and rk3566. It is a
|
||||
single lane PCIe2 compliant controller.
|
||||
|
||||
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20220429123832.2376381-5-pgwipeout@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 50 ++++++++++++++++++++++++
|
||||
1 file changed, 50 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -703,6 +703,56 @@
|
||||
reg = <0x0 0xfe1a8100 0x0 0x20>;
|
||||
};
|
||||
|
||||
+ pcie2x1: pcie@fe260000 {
|
||||
+ compatible = "rockchip,rk3568-pcie";
|
||||
+ reg = <0x3 0xc0000000 0x0 0x00400000>,
|
||||
+ <0x0 0xfe260000 0x0 0x00010000>,
|
||||
+ <0x3 0x3f000000 0x0 0x01000000>;
|
||||
+ reg-names = "dbi", "apb", "config";
|
||||
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "sys", "pmc", "msi", "legacy", "err";
|
||||
+ bus-range = <0x0 0xf>;
|
||||
+ clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
|
||||
+ <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
|
||||
+ <&cru CLK_PCIE20_AUX_NDFT>;
|
||||
+ clock-names = "aclk_mst", "aclk_slv",
|
||||
+ "aclk_dbi", "pclk", "aux";
|
||||
+ device_type = "pci";
|
||||
+ interrupt-map-mask = <0 0 0 7>;
|
||||
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
|
||||
+ <0 0 0 2 &pcie_intc 1>,
|
||||
+ <0 0 0 3 &pcie_intc 2>,
|
||||
+ <0 0 0 4 &pcie_intc 3>;
|
||||
+ linux,pci-domain = <0>;
|
||||
+ num-ib-windows = <6>;
|
||||
+ num-ob-windows = <2>;
|
||||
+ max-link-speed = <2>;
|
||||
+ msi-map = <0x0 &gic 0x0 0x1000>;
|
||||
+ num-lanes = <1>;
|
||||
+ phys = <&combphy2 PHY_TYPE_PCIE>;
|
||||
+ phy-names = "pcie-phy";
|
||||
+ power-domains = <&power RK3568_PD_PIPE>;
|
||||
+ ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000
|
||||
+ 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>;
|
||||
+ resets = <&cru SRST_PCIE20_POWERUP>;
|
||||
+ reset-names = "pipe";
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ pcie_intc: legacy-interrupt-controller {
|
||||
+ #address-cells = <0>;
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-controller;
|
||||
+ interrupt-parent = <&gic>;
|
||||
+ interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
sdmmc0: mmc@fe2b0000 {
|
||||
compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
reg = <0x0 0xfe2b0000 0x0 0x4000>;
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
From a323e6b5737bb6e3d3946369b97099abb7dde695 Mon Sep 17 00:00:00 2001
|
||||
From: Jensen Huang <jensenhuang@friendlyarm.com>
|
||||
Date: Fri, 13 Jan 2023 14:44:57 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: add missing #interrupt-cells to rk356x
|
||||
pcie2x1
|
||||
|
||||
This fixes the following issue:
|
||||
pcieport 0000:00:00.0: of_irq_parse_pci: failed with rc=-22
|
||||
|
||||
Signed-off-by: Jensen Huang <jensenhuang@friendlyarm.com>
|
||||
Link: https://lore.kernel.org/r/20230113064457.7105-1-jensenhuang@friendlyarm.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -722,6 +722,7 @@
|
||||
clock-names = "aclk_mst", "aclk_slv",
|
||||
"aclk_dbi", "pclk", "aux";
|
||||
device_type = "pci";
|
||||
+ #interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc 0>,
|
||||
<0 0 0 2 &pcie_intc 1>,
|
||||
|
|
@ -1,32 +0,0 @@
|
|||
From 64b69474edf3b885c19a89bb165f978ba1b4be00 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Tue, 10 Jan 2023 22:55:50 +0000
|
||||
Subject: [PATCH] arm64: dts: rockchip: assign rate to clk_rtc_32k on rk356x
|
||||
|
||||
clk_rtc_32k and its child clock clk_hdmi_cec detauls to a rate of 24 MHz
|
||||
and not to 32 kHz on RK356x.
|
||||
|
||||
Fix this by assigning clk_rtc_32k a rate of 32768, also assign the parent
|
||||
to clk_rtc32k_frac.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
Link: https://lore.kernel.org/r/20230110225547.1563119-2-jonas@kwiboo.se
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 5 +++--
|
||||
1 file changed, 3 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -367,8 +367,9 @@
|
||||
clock-names = "xin24m";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
- assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
|
||||
- assigned-clock-rates = <1200000000>, <200000000>;
|
||||
+ assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
|
||||
+ assigned-clock-rates = <32768>, <1200000000>, <200000000>;
|
||||
+ assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
|
||||
rockchip,grf = <&grf>;
|
||||
};
|
||||
|
||||
|
|
@ -1,67 +0,0 @@
|
|||
From 604be85547ce4d61b89292d2f9a78c721b778c16 Mon Sep 17 00:00:00 2001
|
||||
From: Andy Yan <andy.yan@rock-chips.com>
|
||||
Date: Fri, 22 Apr 2022 09:28:39 +0200
|
||||
Subject: [PATCH] drm/rockchip: Add VOP2 driver
|
||||
|
||||
The VOP2 unit is found on Rockchip SoCs beginning with rk3566/rk3568.
|
||||
It replaces the VOP unit found in the older Rockchip SoCs.
|
||||
|
||||
This driver has been derived from the downstream Rockchip Kernel and
|
||||
heavily modified:
|
||||
|
||||
- All nonstandard DRM properties have been removed
|
||||
- dropped struct vop2_plane_state and pass around less data between
|
||||
functions
|
||||
- Dropped all DRM_FORMAT_* not known on upstream
|
||||
- rework register access to get rid of excessively used macros
|
||||
- Drop all waiting for framesyncs
|
||||
|
||||
The driver is tested with HDMI and MIPI-DSI display on a RK3568-EVB
|
||||
board. Overlay support is tested with the modetest utility. AFBC support
|
||||
on the cluster windows is tested with weston-simple-dmabuf-egl on
|
||||
weston using the (yet to be upstreamed) panfrost driver support.
|
||||
|
||||
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
|
||||
Co-Developed-by: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
[dt-binding-header:]
|
||||
Acked-by: Rob Herring <robh@kernel.org>
|
||||
[moved dt-binding header from dt-nodes patch to here
|
||||
and made checkpatch --strict happier]
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Link: https://patchwork.freedesktop.org/patch/msgid/20220422072841.2206452-23-s.hauer@pengutronix.de
|
||||
---
|
||||
drivers/gpu/drm/rockchip/Kconfig | 6 +
|
||||
drivers/gpu/drm/rockchip/Makefile | 1 +
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 1 +
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 6 +-
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_fb.c | 2 +
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 14 +
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 2706 ++++++++++++++++++
|
||||
drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 477 +++
|
||||
drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 281 ++
|
||||
include/dt-bindings/soc/rockchip,vop2.h | 14 +
|
||||
10 files changed, 3507 insertions(+), 1 deletion(-)
|
||||
create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
|
||||
create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
|
||||
create mode 100644 drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
|
||||
create mode 100644 include/dt-bindings/soc/rockchip,vop2.h
|
||||
|
||||
--- /dev/null
|
||||
+++ b/include/dt-bindings/soc/rockchip,vop2.h
|
||||
@@ -0,0 +1,14 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
|
||||
+
|
||||
+#ifndef __DT_BINDINGS_ROCKCHIP_VOP2_H
|
||||
+#define __DT_BINDINGS_ROCKCHIP_VOP2_H
|
||||
+
|
||||
+#define ROCKCHIP_VOP2_EP_RGB0 1
|
||||
+#define ROCKCHIP_VOP2_EP_HDMI0 2
|
||||
+#define ROCKCHIP_VOP2_EP_EDP0 3
|
||||
+#define ROCKCHIP_VOP2_EP_MIPI0 4
|
||||
+#define ROCKCHIP_VOP2_EP_LVDS0 5
|
||||
+#define ROCKCHIP_VOP2_EP_MIPI1 6
|
||||
+#define ROCKCHIP_VOP2_EP_LVDS1 7
|
||||
+
|
||||
+#endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */
|
||||
|
|
@ -1,394 +0,0 @@
|
|||
From 2e9bffc4f713db465177238f6033f7d367d6f151 Mon Sep 17 00:00:00 2001
|
||||
From: Shawn Lin <shawn.lin@rock-chips.com>
|
||||
Date: Thu, 25 Aug 2022 21:38:34 +0200
|
||||
Subject: [PATCH] phy: rockchip: Support PCIe v3
|
||||
|
||||
RK3568 supports PCIe v3 using not Combphy like PCIe v2 on rk3566.
|
||||
It use a dedicated PCIe-phy. Add support for this.
|
||||
|
||||
Initial support by Shawn Lin, modifications by Peter Geis and Frank
|
||||
Wunderlich.
|
||||
|
||||
Add data-lanes property for splitting pcie-lanes across controllers.
|
||||
|
||||
The data-lanes is an array where x=0 means lane is disabled and x > 0
|
||||
means controller x is assigned to phy lane.
|
||||
|
||||
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
|
||||
Suggested-by: Peter Geis <pgwipeout@gmail.com>
|
||||
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
|
||||
Link: https://lore.kernel.org/r/20220825193836.54262-4-linux@fw-web.de
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/Kconfig | 9 +
|
||||
drivers/phy/rockchip/Makefile | 1 +
|
||||
.../phy/rockchip/phy-rockchip-snps-pcie3.c | 319 ++++++++++++++++++
|
||||
include/linux/phy/pcie.h | 12 +
|
||||
4 files changed, 341 insertions(+)
|
||||
create mode 100644 drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
|
||||
create mode 100644 include/linux/phy/pcie.h
|
||||
|
||||
--- a/drivers/phy/rockchip/Kconfig
|
||||
+++ b/drivers/phy/rockchip/Kconfig
|
||||
@@ -83,6 +83,15 @@ config PHY_ROCKCHIP_PCIE
|
||||
help
|
||||
Enable this to support the Rockchip PCIe PHY.
|
||||
|
||||
+config PHY_ROCKCHIP_SNPS_PCIE3
|
||||
+ tristate "Rockchip Snps PCIe3 PHY Driver"
|
||||
+ depends on (ARCH_ROCKCHIP && OF) || COMPILE_TEST
|
||||
+ depends on HAS_IOMEM
|
||||
+ select GENERIC_PHY
|
||||
+ select MFD_SYSCON
|
||||
+ help
|
||||
+ Enable this to support the Rockchip snps PCIe3 PHY.
|
||||
+
|
||||
config PHY_ROCKCHIP_TYPEC
|
||||
tristate "Rockchip TYPEC PHY Driver"
|
||||
depends on OF && (ARCH_ROCKCHIP || COMPILE_TEST)
|
||||
--- a/drivers/phy/rockchip/Makefile
|
||||
+++ b/drivers/phy/rockchip/Makefile
|
||||
@@ -8,5 +8,6 @@ obj-$(CONFIG_PHY_ROCKCHIP_INNO_HDMI) +=
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY) += phy-rockchip-naneng-combphy.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
|
||||
+obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
|
||||
obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
|
||||
@@ -0,0 +1,319 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0
|
||||
+/*
|
||||
+ * Rockchip PCIE3.0 phy driver
|
||||
+ *
|
||||
+ * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/clk.h>
|
||||
+#include <linux/delay.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/iopoll.h>
|
||||
+#include <linux/kernel.h>
|
||||
+#include <linux/mfd/syscon.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/of_device.h>
|
||||
+#include <linux/phy/pcie.h>
|
||||
+#include <linux/phy/phy.h>
|
||||
+#include <linux/regmap.h>
|
||||
+#include <linux/reset.h>
|
||||
+
|
||||
+/* Register for RK3568 */
|
||||
+#define GRF_PCIE30PHY_CON1 0x4
|
||||
+#define GRF_PCIE30PHY_CON6 0x18
|
||||
+#define GRF_PCIE30PHY_CON9 0x24
|
||||
+#define GRF_PCIE30PHY_DA_OCM (BIT(15) | BIT(31))
|
||||
+#define GRF_PCIE30PHY_STATUS0 0x80
|
||||
+#define GRF_PCIE30PHY_WR_EN (0xf << 16)
|
||||
+#define SRAM_INIT_DONE(reg) (reg & BIT(14))
|
||||
+
|
||||
+#define RK3568_BIFURCATION_LANE_0_1 BIT(0)
|
||||
+
|
||||
+/* Register for RK3588 */
|
||||
+#define PHP_GRF_PCIESEL_CON 0x100
|
||||
+#define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0
|
||||
+#define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904
|
||||
+#define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04
|
||||
+#define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0))
|
||||
+
|
||||
+#define RK3588_BIFURCATION_LANE_0_1 BIT(0)
|
||||
+#define RK3588_BIFURCATION_LANE_2_3 BIT(1)
|
||||
+#define RK3588_LANE_AGGREGATION BIT(2)
|
||||
+
|
||||
+struct rockchip_p3phy_ops;
|
||||
+
|
||||
+struct rockchip_p3phy_priv {
|
||||
+ const struct rockchip_p3phy_ops *ops;
|
||||
+ void __iomem *mmio;
|
||||
+ /* mode: RC, EP */
|
||||
+ int mode;
|
||||
+ /* pcie30_phymode: Aggregation, Bifurcation */
|
||||
+ int pcie30_phymode;
|
||||
+ struct regmap *phy_grf;
|
||||
+ struct regmap *pipe_grf;
|
||||
+ struct reset_control *p30phy;
|
||||
+ struct phy *phy;
|
||||
+ struct clk_bulk_data *clks;
|
||||
+ int num_clks;
|
||||
+ int num_lanes;
|
||||
+ u32 lanes[4];
|
||||
+};
|
||||
+
|
||||
+struct rockchip_p3phy_ops {
|
||||
+ int (*phy_init)(struct rockchip_p3phy_priv *priv);
|
||||
+};
|
||||
+
|
||||
+static int rockchip_p3phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
|
||||
+{
|
||||
+ struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
|
||||
+
|
||||
+ /* Actually We don't care EP/RC mode, but just record it */
|
||||
+ switch (submode) {
|
||||
+ case PHY_MODE_PCIE_RC:
|
||||
+ priv->mode = PHY_MODE_PCIE_RC;
|
||||
+ break;
|
||||
+ case PHY_MODE_PCIE_EP:
|
||||
+ priv->mode = PHY_MODE_PCIE_EP;
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_err(&phy->dev, "%s, invalid mode\n", __func__);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rockchip_p3phy_rk3568_init(struct rockchip_p3phy_priv *priv)
|
||||
+{
|
||||
+ struct phy *phy = priv->phy;
|
||||
+ bool bifurcation = false;
|
||||
+ int ret, i;
|
||||
+ u32 reg;
|
||||
+
|
||||
+ /* Deassert PCIe PMA output clamp mode */
|
||||
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, GRF_PCIE30PHY_DA_OCM);
|
||||
+
|
||||
+ for (i = 0; i < priv->num_lanes; i++) {
|
||||
+ dev_info(&phy->dev, "lane number %d, val %d\n", i, priv->lanes[i]);
|
||||
+ if (priv->lanes[i] > 1)
|
||||
+ bifurcation = true;
|
||||
+ }
|
||||
+
|
||||
+ /* Set bifurcation if needed, and it doesn't care RC/EP */
|
||||
+ if (bifurcation) {
|
||||
+ dev_info(&phy->dev, "bifurcation enabled\n");
|
||||
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,
|
||||
+ GRF_PCIE30PHY_WR_EN | RK3568_BIFURCATION_LANE_0_1);
|
||||
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1,
|
||||
+ GRF_PCIE30PHY_DA_OCM);
|
||||
+ } else {
|
||||
+ dev_dbg(&phy->dev, "bifurcation disabled\n");
|
||||
+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,
|
||||
+ GRF_PCIE30PHY_WR_EN & ~RK3568_BIFURCATION_LANE_0_1);
|
||||
+ }
|
||||
+
|
||||
+ reset_control_deassert(priv->p30phy);
|
||||
+
|
||||
+ ret = regmap_read_poll_timeout(priv->phy_grf,
|
||||
+ GRF_PCIE30PHY_STATUS0,
|
||||
+ reg, SRAM_INIT_DONE(reg),
|
||||
+ 0, 500);
|
||||
+ if (ret)
|
||||
+ dev_err(&priv->phy->dev, "%s: lock failed 0x%x, check input refclk and power supply\n",
|
||||
+ __func__, reg);
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static const struct rockchip_p3phy_ops rk3568_ops = {
|
||||
+ .phy_init = rockchip_p3phy_rk3568_init,
|
||||
+};
|
||||
+
|
||||
+static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv)
|
||||
+{
|
||||
+ u32 reg = 0;
|
||||
+ u8 mode = 0;
|
||||
+ int i, ret;
|
||||
+
|
||||
+ /* Deassert PCIe PMA output clamp mode */
|
||||
+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, BIT(8) | BIT(24));
|
||||
+
|
||||
+ /* Set bifurcation if needed */
|
||||
+ for (i = 0; i < priv->num_lanes; i++) {
|
||||
+ if (!priv->lanes[i])
|
||||
+ mode |= (BIT(i) << 3);
|
||||
+
|
||||
+ if (priv->lanes[i] > 1)
|
||||
+ mode |= (BIT(i) >> 1);
|
||||
+ }
|
||||
+
|
||||
+ if (!mode)
|
||||
+ reg = RK3588_LANE_AGGREGATION;
|
||||
+ else {
|
||||
+ if (mode & (BIT(0) | BIT(1)))
|
||||
+ reg |= RK3588_BIFURCATION_LANE_0_1;
|
||||
+
|
||||
+ if (mode & (BIT(2) | BIT(3)))
|
||||
+ reg |= RK3588_BIFURCATION_LANE_2_3;
|
||||
+ }
|
||||
+
|
||||
+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, (0x7<<16) | reg);
|
||||
+
|
||||
+ /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
|
||||
+ if (!IS_ERR(priv->pipe_grf)) {
|
||||
+ reg = (mode & (BIT(6) | BIT(7))) >> 6;
|
||||
+ if (reg)
|
||||
+ regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON,
|
||||
+ (reg << 16) | reg);
|
||||
+ }
|
||||
+
|
||||
+ reset_control_deassert(priv->p30phy);
|
||||
+
|
||||
+ ret = regmap_read_poll_timeout(priv->phy_grf,
|
||||
+ RK3588_PCIE3PHY_GRF_PHY0_STATUS1,
|
||||
+ reg, RK3588_SRAM_INIT_DONE(reg),
|
||||
+ 0, 500);
|
||||
+ ret |= regmap_read_poll_timeout(priv->phy_grf,
|
||||
+ RK3588_PCIE3PHY_GRF_PHY1_STATUS1,
|
||||
+ reg, RK3588_SRAM_INIT_DONE(reg),
|
||||
+ 0, 500);
|
||||
+ if (ret)
|
||||
+ dev_err(&priv->phy->dev, "lock failed 0x%x, check input refclk and power supply\n",
|
||||
+ reg);
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static const struct rockchip_p3phy_ops rk3588_ops = {
|
||||
+ .phy_init = rockchip_p3phy_rk3588_init,
|
||||
+};
|
||||
+
|
||||
+static int rochchip_p3phy_init(struct phy *phy)
|
||||
+{
|
||||
+ struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
|
||||
+ if (ret) {
|
||||
+ dev_err(&priv->phy->dev, "failed to enable PCIe bulk clks %d\n", ret);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ reset_control_assert(priv->p30phy);
|
||||
+ udelay(1);
|
||||
+
|
||||
+ if (priv->ops->phy_init) {
|
||||
+ ret = priv->ops->phy_init(priv);
|
||||
+ if (ret)
|
||||
+ clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
|
||||
+ }
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int rochchip_p3phy_exit(struct phy *phy)
|
||||
+{
|
||||
+ struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
|
||||
+
|
||||
+ clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
|
||||
+ reset_control_assert(priv->p30phy);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct phy_ops rochchip_p3phy_ops = {
|
||||
+ .init = rochchip_p3phy_init,
|
||||
+ .exit = rochchip_p3phy_exit,
|
||||
+ .set_mode = rockchip_p3phy_set_mode,
|
||||
+ .owner = THIS_MODULE,
|
||||
+};
|
||||
+
|
||||
+static int rockchip_p3phy_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct phy_provider *phy_provider;
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ struct rockchip_p3phy_priv *priv;
|
||||
+ struct device_node *np = dev->of_node;
|
||||
+ struct resource *res;
|
||||
+ int ret;
|
||||
+
|
||||
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
+ if (!priv)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
+ priv->mmio = devm_ioremap_resource(dev, res);
|
||||
+ if (IS_ERR(priv->mmio)) {
|
||||
+ ret = PTR_ERR(priv->mmio);
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ priv->ops = of_device_get_match_data(&pdev->dev);
|
||||
+ if (!priv->ops) {
|
||||
+ dev_err(dev, "no of match data provided\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ priv->phy_grf = syscon_regmap_lookup_by_phandle(np, "rockchip,phy-grf");
|
||||
+ if (IS_ERR(priv->phy_grf)) {
|
||||
+ dev_err(dev, "failed to find rockchip,phy_grf regmap\n");
|
||||
+ return PTR_ERR(priv->phy_grf);
|
||||
+ }
|
||||
+
|
||||
+ priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node,
|
||||
+ "rockchip,pipe-grf");
|
||||
+ if (IS_ERR(priv->pipe_grf))
|
||||
+ dev_info(dev, "failed to find rockchip,pipe_grf regmap\n");
|
||||
+
|
||||
+ priv->num_lanes = of_property_read_variable_u32_array(dev->of_node, "data-lanes",
|
||||
+ priv->lanes, 2,
|
||||
+ ARRAY_SIZE(priv->lanes));
|
||||
+
|
||||
+ /* if no data-lanes assume aggregation */
|
||||
+ if (priv->num_lanes == -EINVAL) {
|
||||
+ dev_dbg(dev, "no data-lanes property found\n");
|
||||
+ priv->num_lanes = 1;
|
||||
+ priv->lanes[0] = 1;
|
||||
+ } else if (priv->num_lanes < 0) {
|
||||
+ dev_err(dev, "failed to read data-lanes property %d\n", priv->num_lanes);
|
||||
+ return priv->num_lanes;
|
||||
+ }
|
||||
+
|
||||
+ priv->phy = devm_phy_create(dev, NULL, &rochchip_p3phy_ops);
|
||||
+ if (IS_ERR(priv->phy)) {
|
||||
+ dev_err(dev, "failed to create combphy\n");
|
||||
+ return PTR_ERR(priv->phy);
|
||||
+ }
|
||||
+
|
||||
+ priv->p30phy = devm_reset_control_get_optional_exclusive(dev, "phy");
|
||||
+ if (IS_ERR(priv->p30phy)) {
|
||||
+ return dev_err_probe(dev, PTR_ERR(priv->p30phy),
|
||||
+ "failed to get phy reset control\n");
|
||||
+ }
|
||||
+ if (!priv->p30phy)
|
||||
+ dev_info(dev, "no phy reset control specified\n");
|
||||
+
|
||||
+ priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
|
||||
+ if (priv->num_clks < 1)
|
||||
+ return -ENODEV;
|
||||
+
|
||||
+ dev_set_drvdata(dev, priv);
|
||||
+ phy_set_drvdata(priv->phy, priv);
|
||||
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
||||
+ return PTR_ERR_OR_ZERO(phy_provider);
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id rockchip_p3phy_of_match[] = {
|
||||
+ { .compatible = "rockchip,rk3568-pcie3-phy", .data = &rk3568_ops },
|
||||
+ { .compatible = "rockchip,rk3588-pcie3-phy", .data = &rk3588_ops },
|
||||
+ { },
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, rockchip_p3phy_of_match);
|
||||
+
|
||||
+static struct platform_driver rockchip_p3phy_driver = {
|
||||
+ .probe = rockchip_p3phy_probe,
|
||||
+ .driver = {
|
||||
+ .name = "rockchip-snps-pcie3-phy",
|
||||
+ .of_match_table = rockchip_p3phy_of_match,
|
||||
+ },
|
||||
+};
|
||||
+module_platform_driver(rockchip_p3phy_driver);
|
||||
+MODULE_DESCRIPTION("Rockchip Synopsys PCIe 3.0 PHY driver");
|
||||
+MODULE_LICENSE("GPL");
|
||||
--- /dev/null
|
||||
+++ b/include/linux/phy/pcie.h
|
||||
@@ -0,0 +1,12 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0 */
|
||||
+/*
|
||||
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
+ */
|
||||
+#ifndef __PHY_PCIE_H
|
||||
+#define __PHY_PCIE_H
|
||||
+
|
||||
+#define PHY_MODE_PCIE_RC 20
|
||||
+#define PHY_MODE_PCIE_EP 21
|
||||
+#define PHY_MODE_PCIE_BIFURCATION 22
|
||||
+
|
||||
+#endif
|
||||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Add table
Add a link
Reference in a new issue