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Test for RUTX 6.1 compilation
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Ycarus (Yannick Chabanois)
parent
ca1b5e5ab0
commit
fb024bdfd3
7 changed files with 567 additions and 86 deletions
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "qcom-ipq4019-ap.dk01.1.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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memory {
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device_type = "memory";
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reg = <0x80000000 0x10000000>;
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};
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soc {
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pinctrl@1000000 {
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mdio_pins: mdio_pinmux {
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mux_1 {
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pins = "gpio53";
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function = "mdio";
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bias-pull-up;
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};
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mux_2 {
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pins = "gpio52";
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function = "mdc";
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bias-pull-up;
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};
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};
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i2c_0_pins: i2c_0_pinmux {
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mux {
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pins = "gpio58", "gpio59";
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function = "blsp_i2c0";
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bias-disable;
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};
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};
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&tlmm 4 1>;
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linux,code = <KEY_RESTART>;
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};
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};
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gpio_export {
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compatible = "gpio-export";
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#size-cells = <0>;
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gpio_out {
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gpio-export,name = "gpio_out";
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gpio-export,output = <0>;
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gpio-export,direction_may_change = <0>;
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gpios = <&stm32_io 23 GPIO_ACTIVE_HIGH>;
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};
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gpio_in {
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gpio-export,name = "gpio_in";
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gpio-export,input = <0>;
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gpio-export,direction_may_change = <0>;
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gpios = <&stm32_io 24 GPIO_ACTIVE_LOW>;
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};
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};
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};
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};
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&blsp1_i2c3 {
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status = "okay";
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pinctrl-0 = <&i2c_0_pins>;
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pinctrl-names = "default";
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clock-frequency = <400000>;
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stm32_io: stm32@74 {
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compatible = "tlt,stm32v1";
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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gpio-controller;
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interrupt-controller;
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interrupt-parent = <&tlmm>;
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interrupts = <5 2>;
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reg = <0x74>;
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};
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};
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&blsp1_spi1 {
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cs-gpios = <&tlmm 54 0>, <&tlmm 63 0>;
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num-cs = <2>;
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xt25f128b@0 {
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/*
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* Factory U-boot looks in 0:BOOTCONFIG partition for active
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* partitions settings and mangles the partition config so
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* 0:QSEE/0:QSEE_1, 0:CDT/0:CDT_1 and 0:APPSBL/0:APPSBL_1 pairs
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* can be swaped. It isn't a problem but we never can be sure where
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* OFW put factory images. "n25q128a11" is required for proper nor
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* recognition in u-boot.
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*/
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compatible = "jedec,spi-nor", "n25q128a11";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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spi-max-frequency = <24000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "0:SBL1";
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reg = <0x0 0x40000>;
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read-only;
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};
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partition@40000 {
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label = "0:MIBIB";
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reg = <0x40000 0x20000>;
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read-only;
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};
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partition@60000 {
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label = "0:BOOTCONFIG";
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reg = <0x60000 0x20000>;
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read-only;
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};
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partition@80000 {
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label = "0:BOOTCONFIG1";
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reg = <0x80000 0x20000>;
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read-only;
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};
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partition@a0000 {
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label = "0:QSEE";
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reg = <0xa0000 0x60000>;
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read-only;
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};
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partition@100000 {
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label = "0:QSEE_1";
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reg = <0x100000 0x60000>;
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read-only;
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};
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partition@160000 {
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label = "0:CDT";
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reg = <0x160000 0x10000>;
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read-only;
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};
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partition@170000 {
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label = "0:CDT_1";
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reg = <0x170000 0x10000>;
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read-only;
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};
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partition@180000 {
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label = "0:DDRPARAMS";
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reg = <0x180000 0x10000>;
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read-only;
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};
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partition@190000 {
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label = "0:APPSBLENV";
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reg = <0x190000 0x10000>;
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read-only;
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};
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partition@1a0000 {
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label = "0:APPSBL";
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reg = <0x1a0000 0xa0000>;
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read-only;
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};
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partition@240000 {
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label = "0:APPSBL_1";
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reg = <0x240000 0xa0000>;
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read-only;
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};
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partition@2e0000 {
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label = "0:ART";
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reg = <0x2e0000 0x10000>;
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read-only;
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};
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config: partition@2f0000 {
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label = "0:CONFIG";
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reg = <0x2f0000 0x10000>;
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read-only;
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};
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partition@300000 {
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label = "0:CONFIG_RW";
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reg = <0x300000 0x10000>;
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read-only;
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};
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partition@310000 {
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label = "0:EVENTSLOG";
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reg = <0x310000 0x90000>;
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read-only;
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};
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};
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};
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xt26g02a@1 {
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/*
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* Factory U-boot looks in 0:BOOTCONFIG partition for active
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* partitions settings and mangles the partition config so
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* rootfs/rootfs_1 pairs can be swaped.
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* It isn't a problem but we never can be sure where OFW put
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* factory images. "spinand,mt29f" value is required for proper
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* nand recognition in u-boot.
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*/
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compatible = "spi-nand", "spinand,mt29f";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <1>;
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spi-max-frequency = <24000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "rootfs_1";
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reg = <0x00000000 0x08000000>;
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};
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partition@8000000 {
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label = "rootfs";
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reg = <0x08000000 0x08000000>;
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};
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};
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};
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};
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&mdio {
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status = "okay";
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pinctrl-0 = <&mdio_pins>;
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pinctrl-names = "default";
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phy-reset-gpio = <&tlmm 62 0>;
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};
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&wifi0 {
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nvmem-cell-names = "pre-calibration", "mac-address";
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nvmem-cells = <&precal_art_1000>, <&macaddr_config_0>;
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mac-address-increment = <2>;
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};
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&wifi1 {
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nvmem-cell-names = "pre-calibration", "mac-address";
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nvmem-cells = <&precal_art_5000>, <&macaddr_config_0>;
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mac-address-increment = <3>;
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};
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&gmac {
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status = "okay";
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};
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&switch {
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status = "okay";
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};
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&swport2 {
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status = "okay";
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label = "lan1";
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};
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&swport3 {
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status = "okay";
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label = "lan2";
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};
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&swport4 {
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status = "okay";
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label = "lan3";
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};
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&swport5 {
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status = "okay";
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label = "wan";
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};
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@ -0,0 +1,36 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "qcom-ipq4018-rutx.dtsi"
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/ {
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model = "Teltonika RUTX12";
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compatible = "teltonika,rutx12";
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soc {
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leds {
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compatible = "gpio-leds";
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wifi2g {
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label = "green:wifi2g";
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gpios = <&stm32_io 19 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "phy0tpt";
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};
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wifi5g {
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label = "green:wifi5g";
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gpios = <&stm32_io 18 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "phy1tpt";
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};
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};
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};
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};
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&wifi0 {
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status = "okay";
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qcom,ath10k-calibration-variant = "Teltonika-RUTX12";
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};
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&wifi1 {
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status = "okay";
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qcom,ath10k-calibration-variant = "Teltonika-RUTX12";
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};
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