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Revert "Revert "add ipq40xx 5.15""

Browse source 
This reverts commit 4be8e19039.
This commit is contained in:
suyuan168 2021-12-29 01:43:50 +08:00
parent 549356ee91
commit ff2db31eab
163 changed files with 31248 additions and 133 deletions
Download patch file Download diff file Expand all files Collapse all files

24
root/target/linux/ipq40xx/Makefile Normal file
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include $(TOPDIR)/rules.mk
ARCH:=arm
BOARD:=ipq40xx
BOARDNAME:=Qualcomm Atheros IPQ40XX
FEATURES:=squashfs fpu ramdisk nand
CPU_TYPE:=cortex-a7
CPU_SUBTYPE:=neon-vfpv4
SUBTARGETS:=generic mikrotik
KERNEL_PATCHVER:=5.10
KERNEL_TESTING_PATCHVER:=5.10
KERNELNAME:=zImage Image dtbs
include $(INCLUDE_DIR)/target.mk
DEFAULT_PACKAGES += \
kmod-usb-dwc3-qcom \
kmod-leds-gpio kmod-gpio-button-hotplug swconfig \
kmod-ath10k-ct wpad-basic-wolfssl \
kmod-usb3 kmod-usb-dwc3 ath10k-firmware-qca4019-ct \
ath10k-board-qca4019 uboot-envtools
$(eval $(call BuildTarget))

493
root/target/linux/ipq40xx/config-5.10 Normal file
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CONFIG_ALIGNMENT_TRAP=y
# CONFIG_APQ_GCC_8084 is not set
# CONFIG_APQ_MMCC_8084 is not set
CONFIG_AR40XX_PHY=y
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_IPQ40XX=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
# CONFIG_ARCH_MDM9615 is not set
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
# CONFIG_ARCH_MSM8960 is not set
# CONFIG_ARCH_MSM8974 is not set
# CONFIG_ARCH_MSM8X60 is not set
CONFIG_ARCH_MULTIPLATFORM=y
CONFIG_ARCH_MULTI_V6_V7=y
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_NR_GPIO=0
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
CONFIG_ARCH_QCOM=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM=y
CONFIG_ARM_AMBA=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
# CONFIG_ARM_ATAG_DTB_COMPAT is not set
CONFIG_ARM_CPUIDLE=y
# CONFIG_ARM_CPU_TOPOLOGY is not set
CONFIG_ARM_CRYPTO=y
CONFIG_ARM_GIC=y
CONFIG_ARM_HAS_SG_CHAIN=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_L1_CACHE_SHIFT_6=y
CONFIG_ARM_PATCH_IDIV=y
CONFIG_ARM_PATCH_PHYS_VIRT=y
# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
# CONFIG_ARM_QCOM_CPUFREQ_NVMEM is not set
# CONFIG_ARM_QCOM_SPM_CPUIDLE is not set
# CONFIG_ARM_SMMU is not set
CONFIG_ARM_THUMB=y
CONFIG_ARM_UNWIND=y
CONFIG_ARM_VIRT_EXT=y
CONFIG_AT803X_PHY=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_BCH=y
CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
CONFIG_BLK_CMDLINE_PARSER=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BOUNCE=y
# CONFIG_CACHE_L2X0 is not set
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLKSRC_QCOM=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE_PARTITION=y
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_QCOM=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_SPECTRE=y
CONFIG_CPU_THERMAL=y
CONFIG_CPU_THUMB_CAPABLE=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_V7=y
CONFIG_CRC16=y
# CONFIG_CRC32_SARWATE is not set
CONFIG_CRC32_SLICEBY8=y
CONFIG_CRYPTO_AES_ARM=y
CONFIG_CRYPTO_AES_ARM_BS=y
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_DEV_QCE=y
# CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL is not set
# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER=y
CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
CONFIG_CRYPTO_DEV_QCOM_RNG=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA256_ARM=y
CONFIG_CRYPTO_SIMD=y
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
CONFIG_DEBUG_MISC=y
CONFIG_DMADEVICES=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
CONFIG_DMA_OPS=y
CONFIG_DMA_REMAP=y
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DTC=y
CONFIG_DT_IDLE_STATES=y
CONFIG_DYNAMIC_DEBUG=y
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EEPROM_AT24=y
CONFIG_ESSEDMA=y
CONFIG_EXTCON=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_VDSO_32=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_74X164=y
CONFIG_GPIO_WATCHDOG=y
CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDEN_BRANCH_PREDICTOR=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAVE_SMP=y
CONFIG_HIGHMEM=y
# CONFIG_HIGHPTE is not set
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_QCOM=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_OPTEE=y
CONFIG_HZ_FIXED=0
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_HELPER_AUTO=y
# CONFIG_I2C_QCOM_CCI is not set
CONFIG_I2C_QUP=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
CONFIG_IOMMU_SUPPORT=y
CONFIG_IO_URING=y
# CONFIG_IPQ_APSS_PLL is not set
CONFIG_IPQ_GCC_4019=y
# CONFIG_IPQ_GCC_6018 is not set
# CONFIG_IPQ_GCC_806X is not set
# CONFIG_IPQ_GCC_8074 is not set
# CONFIG_IPQ_LCC_806X is not set
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
# CONFIG_KPSS_XCC is not set
# CONFIG_KRAITCC is not set
CONFIG_LEDS_LP5523=y
CONFIG_LEDS_LP5562=y
CONFIG_LEDS_LP55XX_COMMON=y
CONFIG_LEDS_TLC591XX=y
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MDIO_GPIO=y
CONFIG_MDIO_IPQ4019=y
# CONFIG_MDM_GCC_9615 is not set
# CONFIG_MDM_LCC_9615 is not set
CONFIG_MEMFD_CREATE=y
# CONFIG_MFD_HI6421_SPMI is not set
# CONFIG_MFD_QCOM_RPM is not set
# CONFIG_MFD_SPMI_PMIC is not set
CONFIG_MFD_SYSCON=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_MIGRATION=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_CQHCI=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
CONFIG_MMC_SDHCI_MSM=y
# CONFIG_MMC_SDHCI_PCI is not set
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MODULES_USE_ELF_REL=y
# CONFIG_MSM_GCC_8660 is not set
# CONFIG_MSM_GCC_8916 is not set
# CONFIG_MSM_GCC_8939 is not set
# CONFIG_MSM_GCC_8960 is not set
# CONFIG_MSM_GCC_8974 is not set
# CONFIG_MSM_GCC_8994 is not set
# CONFIG_MSM_GCC_8996 is not set
# CONFIG_MSM_GCC_8998 is not set
# CONFIG_MSM_GPUCC_8998 is not set
# CONFIG_MSM_LCC_8960 is not set
# CONFIG_MSM_MMCC_8960 is not set
# CONFIG_MSM_MMCC_8974 is not set
# CONFIG_MSM_MMCC_8996 is not set
# CONFIG_MSM_MMCC_8998 is not set
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_SW_BCH=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_NAND_QCOM=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_SPLIT_FIT_FW=y
CONFIG_MTD_SPLIT_WRGG_FW=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEON=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NLS=y
CONFIG_NO_HZ=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=4
CONFIG_NVMEM=y
# CONFIG_NVMEM_SPMI_SDAM is not set
CONFIG_NVMEM_SYSFS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OF_NET=y
CONFIG_OLD_SIGACTION=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_OPTEE=y
CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1
CONFIG_PADATA=y
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_QCOM=y
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
# CONFIG_PHY_QCOM_APQ8064_SATA is not set
CONFIG_PHY_QCOM_IPQ4019_USB=y
# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
# CONFIG_PHY_QCOM_IPQ806X_USB is not set
# CONFIG_PHY_QCOM_PCIE2 is not set
# CONFIG_PHY_QCOM_QMP is not set
# CONFIG_PHY_QCOM_QUSB2 is not set
# CONFIG_PHY_QCOM_USB_HS_28NM is not set
# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
# CONFIG_PHY_QCOM_USB_SS is not set
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_APQ8064 is not set
# CONFIG_PINCTRL_APQ8084 is not set
CONFIG_PINCTRL_IPQ4019=y
# CONFIG_PINCTRL_IPQ6018 is not set
# CONFIG_PINCTRL_IPQ8064 is not set
# CONFIG_PINCTRL_IPQ8074 is not set
# CONFIG_PINCTRL_MDM9615 is not set
CONFIG_PINCTRL_MSM=y
# CONFIG_PINCTRL_MSM8226 is not set
# CONFIG_PINCTRL_MSM8660 is not set
# CONFIG_PINCTRL_MSM8916 is not set
# CONFIG_PINCTRL_MSM8960 is not set
# CONFIG_PINCTRL_MSM8976 is not set
# CONFIG_PINCTRL_MSM8994 is not set
# CONFIG_PINCTRL_MSM8996 is not set
# CONFIG_PINCTRL_MSM8998 is not set
# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
# CONFIG_PINCTRL_QCS404 is not set
# CONFIG_PINCTRL_SC7180 is not set
# CONFIG_PINCTRL_SDM660 is not set
# CONFIG_PINCTRL_SDM845 is not set
# CONFIG_PINCTRL_SM8150 is not set
# CONFIG_PINCTRL_SM8250 is not set
CONFIG_PM_OPP=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_MSM=y
CONFIG_POWER_SUPPLY=y
CONFIG_PPS=y
CONFIG_PRINTK_TIME=y
CONFIG_PTP_1588_CLOCK=y
CONFIG_QCA807X_PHY=y
CONFIG_QCOM_A53PLL=y
CONFIG_QCOM_BAM_DMA=y
# CONFIG_QCOM_COMMAND_DB is not set
# CONFIG_QCOM_CPR is not set
# CONFIG_QCOM_EBI2 is not set
# CONFIG_QCOM_GENI_SE is not set
# CONFIG_QCOM_GSBI is not set
# CONFIG_QCOM_HFPLL is not set
# CONFIG_QCOM_IOMMU is not set
# CONFIG_QCOM_LLCC is not set
# CONFIG_QCOM_OCMEM is not set
# CONFIG_QCOM_PDC is not set
CONFIG_QCOM_QFPROM=y
# CONFIG_QCOM_RMTFS_MEM is not set
# CONFIG_QCOM_RPMH is not set
CONFIG_QCOM_SCM=y
# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
CONFIG_QCOM_SMEM=y
# CONFIG_QCOM_SMSM is not set
# CONFIG_QCOM_SOCINFO is not set
CONFIG_QCOM_TCSR=y
# CONFIG_QCOM_TSENS is not set
CONFIG_QCOM_WDT=y
# CONFIG_QCS_GCC_404 is not set
# CONFIG_QCS_Q6SSTOP_404 is not set
# CONFIG_QCS_TURING_404 is not set
CONFIG_RAS=y
CONFIG_RATIONAL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_REGULATOR_QCOM_LABIBB is not set
# CONFIG_REGULATOR_QCOM_SPMI is not set
# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
CONFIG_REGULATOR_VCTRL=y
CONFIG_REGULATOR_VQMMC_IPQ4019=y
CONFIG_RESET_CONTROLLER=y
# CONFIG_RESET_QCOM_AOSS is not set
# CONFIG_RESET_QCOM_PDC is not set
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RTC_MC146818_LIB=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
# CONFIG_SC_DISPCC_7180 is not set
# CONFIG_SC_GCC_7180 is not set
# CONFIG_SC_GPUCC_7180 is not set
# CONFIG_SC_LPASS_CORECC_7180 is not set
# CONFIG_SC_MSS_7180 is not set
# CONFIG_SC_VIDEOCC_7180 is not set
# CONFIG_SDM_CAMCC_845 is not set
# CONFIG_SDM_DISPCC_845 is not set
# CONFIG_SDM_GCC_660 is not set
# CONFIG_SDM_GCC_845 is not set
# CONFIG_SDM_GPUCC_845 is not set
# CONFIG_SDM_LPASSCC_845 is not set
# CONFIG_SDM_VIDEOCC_845 is not set
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_MSM=y
CONFIG_SERIAL_MSM_CONSOLE=y
CONFIG_SGL_ALLOC=y
CONFIG_SMP=y
CONFIG_SMP_ON_UP=y
# CONFIG_SM_GCC_8150 is not set
# CONFIG_SM_GCC_8250 is not set
# CONFIG_SM_GPUCC_8150 is not set
# CONFIG_SM_GPUCC_8250 is not set
# CONFIG_SM_VIDEOCC_8150 is not set
# CONFIG_SM_VIDEOCC_8250 is not set
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_GPIO=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_QUP=y
CONFIG_SPMI=y
# CONFIG_SPMI_HISI3670 is not set
CONFIG_SPMI_MSM_PMIC_ARB=y
# CONFIG_SPMI_PMIC_CLKDIV is not set
CONFIG_SRCU=y
CONFIG_SWCONFIG=y
CONFIG_SWCONFIG_LEDS=y
CONFIG_SWPHY=y
CONFIG_SWP_EMULATE=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_TEE=y
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_OF=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UBIFS_FS=y
CONFIG_UEVENT_HELPER_PATH=""
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_UNWINDER_ARM=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_SUPPORT=y
CONFIG_USE_OF=y
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_WATCHDOG_CORE=y
CONFIG_XPS=y
CONFIG_XXHASH=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y

515
root/target/linux/ipq40xx/config-5.15 Normal file
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CONFIG_AF_UNIX_OOB=y
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_APQ_GCC_8084 is not set
# CONFIG_APQ_MMCC_8084 is not set
CONFIG_AR40XX_PHY=y
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_IPQ40XX=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
# CONFIG_ARCH_MDM9615 is not set
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
# CONFIG_ARCH_MSM8960 is not set
# CONFIG_ARCH_MSM8974 is not set
# CONFIG_ARCH_MSM8X60 is not set
CONFIG_ARCH_MULTIPLATFORM=y
CONFIG_ARCH_MULTI_V6_V7=y
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_NR_GPIO=0
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
CONFIG_ARCH_QCOM=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM=y
CONFIG_ARM_AMBA=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
# CONFIG_ARM_ATAG_DTB_COMPAT is not set
CONFIG_ARM_CPUIDLE=y
# CONFIG_ARM_CPU_TOPOLOGY is not set
CONFIG_ARM_CRYPTO=y
CONFIG_ARM_GIC=y
CONFIG_ARM_HAS_SG_CHAIN=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_L1_CACHE_SHIFT_6=y
CONFIG_ARM_PATCH_IDIV=y
CONFIG_ARM_PATCH_PHYS_VIRT=y
# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
# CONFIG_ARM_QCOM_CPUFREQ_NVMEM is not set
# CONFIG_ARM_QCOM_SPM_CPUIDLE is not set
# CONFIG_ARM_SMMU is not set
CONFIG_ARM_THUMB=y
CONFIG_ARM_UNWIND=y
CONFIG_ARM_VIRT_EXT=y
CONFIG_AT803X_PHY=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_BCH=y
CONFIG_BINARY_PRINTF=y
CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BOUNCE=y
# CONFIG_CACHE_L2X0 is not set
CONFIG_CLKSRC_QCOM=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE_PARTITION=y
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_QCOM=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_SPECTRE=y
CONFIG_CPU_THERMAL=y
CONFIG_CPU_THUMB_CAPABLE=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_V7=y
CONFIG_CRC16=y
# CONFIG_CRC32_SARWATE is not set
CONFIG_CRC32_SLICEBY8=y
CONFIG_CRC8=y
CONFIG_CRYPTO_AES_ARM=y
CONFIG_CRYPTO_AES_ARM_BS=y
# CONFIG_CRYPTO_BLAKE2B_NEON is not set
# CONFIG_CRYPTO_BLAKE2S_ARM is not set
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CRYPTD=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_DEV_QCE=y
# CONFIG_CRYPTO_DEV_QCE_ENABLE_AEAD is not set
# CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL is not set
# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER=y
CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
CONFIG_CRYPTO_DEV_QCOM_RNG=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_GF128MUL=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_LIB_DES=y
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_NULL2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_RNG_DEFAULT=y
CONFIG_CRYPTO_SEQIV=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA256_ARM=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SIMD=y
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
CONFIG_DEBUG_MISC=y
# CONFIG_DMABUF_DEBUG is not set
# CONFIG_DMABUF_SYSFS_STATS is not set
CONFIG_DMADEVICES=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
CONFIG_DMA_OPS=y
CONFIG_DMA_REMAP=y
CONFIG_DMA_SHARED_BUFFER=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DTC=y
CONFIG_DT_IDLE_STATES=y
CONFIG_DYNAMIC_DEBUG=y
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EEPROM_AT24=y
CONFIG_ESSEDMA=y
CONFIG_EXTCON=y
# CONFIG_EXTCON_USBC_TUSB320 is not set
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_VDSO_32=y
CONFIG_GPIOLIB=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_74X164=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_WATCHDOG=y
CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDEN_BRANCH_PREDICTOR=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAVE_SMP=y
CONFIG_HIGHMEM=y
# CONFIG_HIGHPTE is not set
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_QCOM=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_OPTEE=y
CONFIG_HZ_FIXED=0
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_HELPER_AUTO=y
# CONFIG_I2C_QCOM_CCI is not set
CONFIG_I2C_QUP=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
CONFIG_IOMMU_SUPPORT=y
CONFIG_IO_URING=y
# CONFIG_IPQ_APSS_PLL is not set
CONFIG_IPQ_GCC_4019=y
# CONFIG_IPQ_GCC_6018 is not set
# CONFIG_IPQ_GCC_806X is not set
# CONFIG_IPQ_GCC_8074 is not set
# CONFIG_IPQ_LCC_806X is not set
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
CONFIG_KMAP_LOCAL=y
# CONFIG_KPSS_XCC is not set
# CONFIG_KRAITCC is not set
CONFIG_LEDS_LP5523=y
CONFIG_LEDS_LP5562=y
CONFIG_LEDS_LP55XX_COMMON=y
CONFIG_LEDS_TLC591XX=y
CONFIG_LIBFDT=y
CONFIG_LLD_VERSION=0
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LTO_NONE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MDIO_GPIO=y
CONFIG_MDIO_IPQ4019=y
# CONFIG_MDM_GCC_9615 is not set
# CONFIG_MDM_LCC_9615 is not set
CONFIG_MEMFD_CREATE=y
# CONFIG_MFD_HI6421_SPMI is not set
# CONFIG_MFD_QCOM_RPM is not set
# CONFIG_MFD_SPMI_PMIC is not set
CONFIG_MFD_SYSCON=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_MIGRATION=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_CQHCI=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
CONFIG_MMC_SDHCI_MSM=y
# CONFIG_MMC_SDHCI_PCI is not set
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MODULES_USE_ELF_REL=y
# CONFIG_MSM_GCC_8660 is not set
# CONFIG_MSM_GCC_8916 is not set
# CONFIG_MSM_GCC_8939 is not set
# CONFIG_MSM_GCC_8960 is not set
# CONFIG_MSM_GCC_8974 is not set
# CONFIG_MSM_GCC_8994 is not set
# CONFIG_MSM_GCC_8996 is not set
# CONFIG_MSM_GCC_8998 is not set
# CONFIG_MSM_GPUCC_8998 is not set
# CONFIG_MSM_LCC_8960 is not set
# CONFIG_MSM_MMCC_8960 is not set
# CONFIG_MSM_MMCC_8974 is not set
# CONFIG_MSM_MMCC_8996 is not set
# CONFIG_MSM_MMCC_8998 is not set
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_SW_BCH=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_NAND_QCOM=y
# CONFIG_MTD_QCOMSMEM_PARTS is not set
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_SPLIT_FIT_FW=y
CONFIG_MTD_SPLIT_WRGG_FW=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEON=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_SOCK_MSG=y
CONFIG_NLS=y
CONFIG_NO_HZ=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=4
CONFIG_NVMEM=y
# CONFIG_NVMEM_SPMI_SDAM is not set
CONFIG_NVMEM_SYSFS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OF_NET=y
CONFIG_OLD_SIGACTION=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_OPTEE=y
CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1
CONFIG_PADATA=y
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_QCOM=y
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
# CONFIG_PHY_QCOM_APQ8064_SATA is not set
CONFIG_PHY_QCOM_IPQ4019_USB=y
# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
# CONFIG_PHY_QCOM_IPQ806X_USB is not set
# CONFIG_PHY_QCOM_PCIE2 is not set
# CONFIG_PHY_QCOM_QMP is not set
# CONFIG_PHY_QCOM_QUSB2 is not set
# CONFIG_PHY_QCOM_USB_HS_28NM is not set
# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
# CONFIG_PHY_QCOM_USB_SS is not set
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_APQ8064 is not set
# CONFIG_PINCTRL_APQ8084 is not set
CONFIG_PINCTRL_IPQ4019=y
# CONFIG_PINCTRL_IPQ6018 is not set
# CONFIG_PINCTRL_IPQ8064 is not set
# CONFIG_PINCTRL_IPQ8074 is not set
# CONFIG_PINCTRL_MDM9615 is not set
CONFIG_PINCTRL_MSM=y
# CONFIG_PINCTRL_MSM8226 is not set
# CONFIG_PINCTRL_MSM8660 is not set
# CONFIG_PINCTRL_MSM8916 is not set
# CONFIG_PINCTRL_MSM8960 is not set
# CONFIG_PINCTRL_MSM8976 is not set
# CONFIG_PINCTRL_MSM8994 is not set
# CONFIG_PINCTRL_MSM8996 is not set
# CONFIG_PINCTRL_MSM8998 is not set
# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
# CONFIG_PINCTRL_QCS404 is not set
# CONFIG_PINCTRL_SC7180 is not set
# CONFIG_PINCTRL_SDM660 is not set
# CONFIG_PINCTRL_SDM845 is not set
# CONFIG_PINCTRL_SM8150 is not set
# CONFIG_PINCTRL_SM8250 is not set
CONFIG_PM_OPP=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_MSM=y
CONFIG_POWER_SUPPLY=y
CONFIG_PPS=y
CONFIG_PRINTK_TIME=y
CONFIG_PTP_1588_CLOCK=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_QCA807X_PHY=y
CONFIG_QCOM_A53PLL=y
# CONFIG_QCOM_ADM is not set
CONFIG_QCOM_BAM_DMA=y
# CONFIG_QCOM_COMMAND_DB is not set
# CONFIG_QCOM_CPR is not set
# CONFIG_QCOM_EBI2 is not set
# CONFIG_QCOM_GENI_SE is not set
# CONFIG_QCOM_GSBI is not set
# CONFIG_QCOM_HFPLL is not set
# CONFIG_QCOM_IOMMU is not set
# CONFIG_QCOM_LLCC is not set
# CONFIG_QCOM_OCMEM is not set
# CONFIG_QCOM_PDC is not set
CONFIG_QCOM_QFPROM=y
# CONFIG_QCOM_RMTFS_MEM is not set
# CONFIG_QCOM_RPMH is not set
CONFIG_QCOM_SCM=y
# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
CONFIG_QCOM_SMEM=y
# CONFIG_QCOM_SMSM is not set
# CONFIG_QCOM_SOCINFO is not set
CONFIG_QCOM_TCSR=y
# CONFIG_QCOM_TSENS is not set
CONFIG_QCOM_WDT=y
# CONFIG_QCS_GCC_404 is not set
# CONFIG_QCS_Q6SSTOP_404 is not set
# CONFIG_QCS_TURING_404 is not set
CONFIG_RAS=y
CONFIG_RATIONAL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_REGULATOR_QCOM_LABIBB is not set
# CONFIG_REGULATOR_QCOM_SPMI is not set
# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
CONFIG_REGULATOR_VCTRL=y
CONFIG_REGULATOR_VQMMC_IPQ4019=y
CONFIG_RESET_CONTROLLER=y
# CONFIG_RESET_QCOM_AOSS is not set
# CONFIG_RESET_QCOM_PDC is not set
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RTC_MC146818_LIB=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
# CONFIG_SC_DISPCC_7180 is not set
# CONFIG_SC_GCC_7180 is not set
# CONFIG_SC_GPUCC_7180 is not set
# CONFIG_SC_LPASS_CORECC_7180 is not set
# CONFIG_SC_MSS_7180 is not set
# CONFIG_SC_VIDEOCC_7180 is not set
# CONFIG_SDM_CAMCC_845 is not set
# CONFIG_SDM_DISPCC_845 is not set
# CONFIG_SDM_GCC_660 is not set
# CONFIG_SDM_GCC_845 is not set
# CONFIG_SDM_GPUCC_845 is not set
# CONFIG_SDM_LPASSCC_845 is not set
# CONFIG_SDM_VIDEOCC_845 is not set
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_MSM=y
CONFIG_SERIAL_MSM_CONSOLE=y
CONFIG_SGL_ALLOC=y
CONFIG_SMP=y
CONFIG_SMP_ON_UP=y
# CONFIG_SM_GCC_8150 is not set
# CONFIG_SM_GCC_8250 is not set
# CONFIG_SM_GPUCC_8150 is not set
# CONFIG_SM_GPUCC_8250 is not set
# CONFIG_SM_VIDEOCC_8150 is not set
# CONFIG_SM_VIDEOCC_8250 is not set
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_GPIO=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SPI_QUP=y
CONFIG_SPMI=y
# CONFIG_SPMI_HISI3670 is not set
CONFIG_SPMI_MSM_PMIC_ARB=y
# CONFIG_SPMI_PMIC_CLKDIV is not set
CONFIG_SRCU=y
CONFIG_SWCONFIG=y
CONFIG_SWCONFIG_LEDS=y
CONFIG_SWPHY=y
CONFIG_SWP_EMULATE=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_TEE=y
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_OF=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UBIFS_FS=y
CONFIG_UEVENT_HELPER_PATH=""
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_UNWINDER_ARM=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_SUPPORT=y
CONFIG_USE_OF=y
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_WATCHDOG_CORE=y
CONFIG_XPS=y
CONFIG_XXHASH=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y

15
root/target/linux/ipq40xx/config-5.4
View file

@ -1,6 +1,4 @@
CONFIG_ALIGNMENT_TRAP=y
CONFIG_ARM_MODULE_PLTS=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
# CONFIG_APQ_GCC_8084 is not set
# CONFIG_APQ_MMCC_8084 is not set
CONFIG_AR40XX_PHY=y
@ -54,6 +52,7 @@ CONFIG_BOUNCE=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_CLKSRC_QCOM=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE_PARTITION=y
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_QCOM=y
CONFIG_COMPAT_32BIT_TIME=y
@ -198,8 +197,6 @@ CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_QCOM=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_OPTEE=y
CONFIG_HZ=100
CONFIG_HZ_100=y
CONFIG_HZ_FIXED=0
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
@ -226,6 +223,7 @@ CONFIG_IRQ_WORK=y
CONFIG_LEDS_LP5523=y
CONFIG_LEDS_LP5562=y
CONFIG_LEDS_LP55XX_COMMON=y
CONFIG_LEDS_TLC591XX=y
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
@ -382,9 +380,6 @@ CONFIG_QCOM_WDT=y
# CONFIG_QRTR is not set
CONFIG_RAS=y
CONFIG_RATIONAL=y
CONFIG_RCU_CPU_STALL_TIMEOUT=21
CONFIG_RCU_NEED_SEGCBLIST=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_REFCOUNT_FULL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
@ -446,10 +441,6 @@ CONFIG_TIMER_PROBE=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_UBIFS_FS_LZO=y
CONFIG_UBIFS_FS_ZLIB=y
CONFIG_UBIFS_FS_ZSTD=y
CONFIG_UEVENT_HELPER_PATH=""
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_UNWINDER_ARM=y
@ -469,4 +460,4 @@ CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y

1890
root/target/linux/ipq40xx/files-5.10/drivers/net/mdio/ar40xx.c Normal file
View file

File diff suppressed because it is too large Load diff

342
root/target/linux/ipq40xx/files-5.10/drivers/net/mdio/ar40xx.h Normal file
View file

@ -0,0 +1,342 @@
/*
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __AR40XX_H
#define __AR40XX_H
#define AR40XX_MAX_VLANS 128
#define AR40XX_NUM_PORTS 6
#define AR40XX_NUM_PHYS 5
#define BITS(_s, _n) (((1UL << (_n)) - 1) << _s)
struct ar40xx_priv {
struct switch_dev dev;
u8 __iomem *hw_addr;
u8 __iomem *psgmii_hw_addr;
u32 mac_mode;
struct reset_control *ess_rst;
u32 cpu_bmp;
u32 lan_bmp;
u32 wan_bmp;
struct mii_bus *mii_bus;
struct phy_device *phy;
/* mutex for qm task */
struct mutex qm_lock;
struct delayed_work qm_dwork;
u32 port_link_up[AR40XX_NUM_PORTS];
u32 ar40xx_port_old_link[AR40XX_NUM_PORTS];
u32 ar40xx_port_qm_buf[AR40XX_NUM_PORTS];
u32 phy_t_status;
/* mutex for switch reg access */
struct mutex reg_mutex;
/* mutex for mib task */
struct mutex mib_lock;
struct delayed_work mib_work;
int mib_next_port;
u64 *mib_stats;
char buf[2048];
/* all fields below will be cleared on reset */
bool vlan;
u16 vlan_id[AR40XX_MAX_VLANS];
u8 vlan_table[AR40XX_MAX_VLANS];
u8 vlan_tagged;
u16 pvid[AR40XX_NUM_PORTS];
/* mirror */
bool mirror_rx;
bool mirror_tx;
int source_port;
int monitor_port;
};
#define AR40XX_PORT_LINK_UP 1
#define AR40XX_PORT_LINK_DOWN 0
#define AR40XX_QM_NOT_EMPTY 1
#define AR40XX_QM_EMPTY 0
#define AR40XX_LAN_VLAN 1
#define AR40XX_WAN_VLAN 2
enum ar40xx_port_wrapper_cfg {
PORT_WRAPPER_PSGMII = 0,
};
struct ar40xx_mib_desc {
u32 size;
u32 offset;
const char *name;
};
#define AR40XX_PORT_CPU 0
#define AR40XX_PSGMII_MODE_CONTROL 0x1b4
#define AR40XX_PSGMII_ATHR_CSCO_MODE_25M BIT(0)
#define AR40XX_PSGMIIPHY_TX_CONTROL 0x288
#define AR40XX_MII_ATH_MMD_ADDR 0x0d
#define AR40XX_MII_ATH_MMD_DATA 0x0e
#define AR40XX_MII_ATH_DBG_ADDR 0x1d
#define AR40XX_MII_ATH_DBG_DATA 0x1e
#define AR40XX_STATS_RXBROAD 0x00
#define AR40XX_STATS_RXPAUSE 0x04
#define AR40XX_STATS_RXMULTI 0x08
#define AR40XX_STATS_RXFCSERR 0x0c
#define AR40XX_STATS_RXALIGNERR 0x10
#define AR40XX_STATS_RXRUNT 0x14
#define AR40XX_STATS_RXFRAGMENT 0x18
#define AR40XX_STATS_RX64BYTE 0x1c
#define AR40XX_STATS_RX128BYTE 0x20
#define AR40XX_STATS_RX256BYTE 0x24
#define AR40XX_STATS_RX512BYTE 0x28
#define AR40XX_STATS_RX1024BYTE 0x2c
#define AR40XX_STATS_RX1518BYTE 0x30
#define AR40XX_STATS_RXMAXBYTE 0x34
#define AR40XX_STATS_RXTOOLONG 0x38
#define AR40XX_STATS_RXGOODBYTE 0x3c
#define AR40XX_STATS_RXBADBYTE 0x44
#define AR40XX_STATS_RXOVERFLOW 0x4c
#define AR40XX_STATS_FILTERED 0x50
#define AR40XX_STATS_TXBROAD 0x54
#define AR40XX_STATS_TXPAUSE 0x58
#define AR40XX_STATS_TXMULTI 0x5c
#define AR40XX_STATS_TXUNDERRUN 0x60
#define AR40XX_STATS_TX64BYTE 0x64
#define AR40XX_STATS_TX128BYTE 0x68
#define AR40XX_STATS_TX256BYTE 0x6c
#define AR40XX_STATS_TX512BYTE 0x70
#define AR40XX_STATS_TX1024BYTE 0x74
#define AR40XX_STATS_TX1518BYTE 0x78
#define AR40XX_STATS_TXMAXBYTE 0x7c
#define AR40XX_STATS_TXOVERSIZE 0x80
#define AR40XX_STATS_TXBYTE 0x84
#define AR40XX_STATS_TXCOLLISION 0x8c
#define AR40XX_STATS_TXABORTCOL 0x90
#define AR40XX_STATS_TXMULTICOL 0x94
#define AR40XX_STATS_TXSINGLECOL 0x98
#define AR40XX_STATS_TXEXCDEFER 0x9c
#define AR40XX_STATS_TXDEFER 0xa0
#define AR40XX_STATS_TXLATECOL 0xa4
#define AR40XX_REG_MODULE_EN 0x030
#define AR40XX_MODULE_EN_MIB BIT(0)
#define AR40XX_REG_MIB_FUNC 0x034
#define AR40XX_MIB_BUSY BIT(17)
#define AR40XX_MIB_CPU_KEEP BIT(20)
#define AR40XX_MIB_FUNC BITS(24, 3)
#define AR40XX_MIB_FUNC_S 24
#define AR40XX_MIB_FUNC_NO_OP 0x0
#define AR40XX_MIB_FUNC_FLUSH 0x1
#define AR40XX_ESS_SERVICE_TAG 0x48
#define AR40XX_ESS_SERVICE_TAG_STAG BIT(17)
#define AR40XX_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
#define AR40XX_PORT_SPEED BITS(0, 2)
#define AR40XX_PORT_STATUS_SPEED_S 0
#define AR40XX_PORT_TX_EN BIT(2)
#define AR40XX_PORT_RX_EN BIT(3)
#define AR40XX_PORT_STATUS_TXFLOW BIT(4)
#define AR40XX_PORT_STATUS_RXFLOW BIT(5)
#define AR40XX_PORT_DUPLEX BIT(6)
#define AR40XX_PORT_TXHALF_FLOW BIT(7)
#define AR40XX_PORT_STATUS_LINK_UP BIT(8)
#define AR40XX_PORT_AUTO_LINK_EN BIT(9)
#define AR40XX_PORT_STATUS_FLOW_CONTROL BIT(12)
#define AR40XX_REG_MAX_FRAME_SIZE 0x078
#define AR40XX_MAX_FRAME_SIZE_MTU BITS(0, 14)
#define AR40XX_REG_PORT_HEADER(_i) (0x09c + (_i) * 4)
#define AR40XX_REG_EEE_CTRL 0x100
#define AR40XX_EEE_CTRL_DISABLE_PHY(_i) BIT(4 + (_i) * 2)
#define AR40XX_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8)
#define AR40XX_PORT_VLAN0_DEF_SVID BITS(0, 12)
#define AR40XX_PORT_VLAN0_DEF_SVID_S 0
#define AR40XX_PORT_VLAN0_DEF_CVID BITS(16, 12)
#define AR40XX_PORT_VLAN0_DEF_CVID_S 16
#define AR40XX_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8)
#define AR40XX_PORT_VLAN1_CORE_PORT BIT(9)
#define AR40XX_PORT_VLAN1_PORT_TLS_MODE BIT(7)
#define AR40XX_PORT_VLAN1_PORT_VLAN_PROP BIT(6)
#define AR40XX_PORT_VLAN1_OUT_MODE BITS(12, 2)
#define AR40XX_PORT_VLAN1_OUT_MODE_S 12
#define AR40XX_PORT_VLAN1_OUT_MODE_UNMOD 0
#define AR40XX_PORT_VLAN1_OUT_MODE_UNTAG 1
#define AR40XX_PORT_VLAN1_OUT_MODE_TAG 2
#define AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH 3
#define AR40XX_REG_VTU_FUNC0 0x0610
#define AR40XX_VTU_FUNC0_EG_MODE BITS(4, 14)
#define AR40XX_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2)
#define AR40XX_VTU_FUNC0_EG_MODE_KEEP 0
#define AR40XX_VTU_FUNC0_EG_MODE_UNTAG 1
#define AR40XX_VTU_FUNC0_EG_MODE_TAG 2
#define AR40XX_VTU_FUNC0_EG_MODE_NOT 3
#define AR40XX_VTU_FUNC0_IVL BIT(19)
#define AR40XX_VTU_FUNC0_VALID BIT(20)
#define AR40XX_REG_VTU_FUNC1 0x0614
#define AR40XX_VTU_FUNC1_OP BITS(0, 3)
#define AR40XX_VTU_FUNC1_OP_NOOP 0
#define AR40XX_VTU_FUNC1_OP_FLUSH 1
#define AR40XX_VTU_FUNC1_OP_LOAD 2
#define AR40XX_VTU_FUNC1_OP_PURGE 3
#define AR40XX_VTU_FUNC1_OP_REMOVE_PORT 4
#define AR40XX_VTU_FUNC1_OP_GET_NEXT 5
#define AR40XX7_VTU_FUNC1_OP_GET_ONE 6
#define AR40XX_VTU_FUNC1_FULL BIT(4)
#define AR40XX_VTU_FUNC1_PORT BIT(8, 4)
#define AR40XX_VTU_FUNC1_PORT_S 8
#define AR40XX_VTU_FUNC1_VID BIT(16, 12)
#define AR40XX_VTU_FUNC1_VID_S 16
#define AR40XX_VTU_FUNC1_BUSY BIT(31)
#define AR40XX_REG_FWD_CTRL0 0x620
#define AR40XX_FWD_CTRL0_CPU_PORT_EN BIT(10)
#define AR40XX_FWD_CTRL0_MIRROR_PORT BITS(4, 4)
#define AR40XX_FWD_CTRL0_MIRROR_PORT_S 4
#define AR40XX_REG_FWD_CTRL1 0x624
#define AR40XX_FWD_CTRL1_UC_FLOOD BITS(0, 7)
#define AR40XX_FWD_CTRL1_UC_FLOOD_S 0
#define AR40XX_FWD_CTRL1_MC_FLOOD BITS(8, 7)
#define AR40XX_FWD_CTRL1_MC_FLOOD_S 8
#define AR40XX_FWD_CTRL1_BC_FLOOD BITS(16, 7)
#define AR40XX_FWD_CTRL1_BC_FLOOD_S 16
#define AR40XX_FWD_CTRL1_IGMP BITS(24, 7)
#define AR40XX_FWD_CTRL1_IGMP_S 24
#define AR40XX_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc)
#define AR40XX_PORT_LOOKUP_MEMBER BITS(0, 7)
#define AR40XX_PORT_LOOKUP_IN_MODE BITS(8, 2)
#define AR40XX_PORT_LOOKUP_IN_MODE_S 8
#define AR40XX_PORT_LOOKUP_STATE BITS(16, 3)
#define AR40XX_PORT_LOOKUP_STATE_S 16
#define AR40XX_PORT_LOOKUP_LEARN BIT(20)
#define AR40XX_PORT_LOOKUP_LOOPBACK BIT(21)
#define AR40XX_PORT_LOOKUP_ING_MIRROR_EN BIT(25)
#define AR40XX_REG_ATU_FUNC 0x60c
#define AR40XX_ATU_FUNC_OP BITS(0, 4)
#define AR40XX_ATU_FUNC_OP_NOOP 0x0
#define AR40XX_ATU_FUNC_OP_FLUSH 0x1
#define AR40XX_ATU_FUNC_OP_LOAD 0x2
#define AR40XX_ATU_FUNC_OP_PURGE 0x3
#define AR40XX_ATU_FUNC_OP_FLUSH_LOCKED 0x4
#define AR40XX_ATU_FUNC_OP_FLUSH_UNICAST 0x5
#define AR40XX_ATU_FUNC_OP_GET_NEXT 0x6
#define AR40XX_ATU_FUNC_OP_SEARCH_MAC 0x7
#define AR40XX_ATU_FUNC_OP_CHANGE_TRUNK 0x8
#define AR40XX_ATU_FUNC_BUSY BIT(31)
#define AR40XX_REG_QM_DEBUG_ADDR 0x820
#define AR40XX_REG_QM_DEBUG_VALUE 0x824
#define AR40XX_REG_QM_PORT0_3_QNUM 0x1d
#define AR40XX_REG_QM_PORT4_6_QNUM 0x1e
#define AR40XX_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
#define AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16)
#define AR40XX_REG_PORT_FLOWCTRL_THRESH(_i) (0x9b0 + (_i) * 0x4)
#define AR40XX_PORT0_FC_THRESH_ON_DFLT 0x60
#define AR40XX_PORT0_FC_THRESH_OFF_DFLT 0x90
#define AR40XX_PHY_DEBUG_0 0
#define AR40XX_PHY_MANU_CTRL_EN BIT(12)
#define AR40XX_PHY_DEBUG_2 2
#define AR40XX_PHY_SPEC_STATUS 0x11
#define AR40XX_PHY_SPEC_STATUS_LINK BIT(10)
#define AR40XX_PHY_SPEC_STATUS_DUPLEX BIT(13)
#define AR40XX_PHY_SPEC_STATUS_SPEED BITS(14, 2)
/* port forwarding state */
enum {
AR40XX_PORT_STATE_DISABLED = 0,
AR40XX_PORT_STATE_BLOCK = 1,
AR40XX_PORT_STATE_LISTEN = 2,
AR40XX_PORT_STATE_LEARN = 3,
AR40XX_PORT_STATE_FORWARD = 4
};
/* ingress 802.1q mode */
enum {
AR40XX_IN_PORT_ONLY = 0,
AR40XX_IN_PORT_FALLBACK = 1,
AR40XX_IN_VLAN_ONLY = 2,
AR40XX_IN_SECURE = 3
};
/* egress 802.1q mode */
enum {
AR40XX_OUT_KEEP = 0,
AR40XX_OUT_STRIP_VLAN = 1,
AR40XX_OUT_ADD_VLAN = 2
};
/* port speed */
enum {
AR40XX_PORT_SPEED_10M = 0,
AR40XX_PORT_SPEED_100M = 1,
AR40XX_PORT_SPEED_1000M = 2,
AR40XX_PORT_SPEED_ERR = 3,
};
#define AR40XX_MIB_WORK_DELAY 2000 /* msecs */
#define AR40XX_QM_WORK_DELAY 100
#define AR40XX_MIB_FUNC_CAPTURE 0x3
#define AR40XX_REG_PORT_STATS_START 0x1000
#define AR40XX_REG_PORT_STATS_LEN 0x100
#define AR40XX_PORTS_ALL 0x3f
#define AR40XX_PSGMII_ID 5
#define AR40XX_PSGMII_CALB_NUM 100
#define AR40XX_MALIBU_PSGMII_MODE_CTRL 0x6d
#define AR40XX_MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VAL 0x220c
#define AR40XX_MALIBU_PHY_MMD7_DAC_CTRL 0x801a
#define AR40XX_MALIBU_DAC_CTRL_MASK 0x380
#define AR40XX_MALIBU_DAC_CTRL_VALUE 0x280
#define AR40XX_MALIBU_PHY_RLP_CTRL 0x805a
#define AR40XX_PSGMII_TX_DRIVER_1_CTRL 0xb
#define AR40XX_MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP 0x8a
#define AR40XX_MALIBU_PHY_LAST_ADDR 4
static inline struct ar40xx_priv *
swdev_to_ar40xx(struct switch_dev *swdev)
{
return container_of(swdev, struct ar40xx_priv, dev);
}
#endif

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/*
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __AR40XX_H
#define __AR40XX_H
#define AR40XX_MAX_VLANS 128
#define AR40XX_NUM_PORTS 6
#define AR40XX_NUM_PHYS 5
#define BITS(_s, _n) (((1UL << (_n)) - 1) << _s)
struct ar40xx_priv {
struct switch_dev dev;
u8 __iomem *hw_addr;
u8 __iomem *psgmii_hw_addr;
u32 mac_mode;
struct reset_control *ess_rst;
u32 cpu_bmp;
u32 lan_bmp;
u32 wan_bmp;
struct mii_bus *mii_bus;
struct phy_device *phy;
/* mutex for qm task */
struct mutex qm_lock;
struct delayed_work qm_dwork;
u32 port_link_up[AR40XX_NUM_PORTS];
u32 ar40xx_port_old_link[AR40XX_NUM_PORTS];
u32 ar40xx_port_qm_buf[AR40XX_NUM_PORTS];
u32 phy_t_status;
/* mutex for switch reg access */
struct mutex reg_mutex;
/* mutex for mib task */
struct mutex mib_lock;
struct delayed_work mib_work;
int mib_next_port;
u64 *mib_stats;
char buf[2048];
/* all fields below will be cleared on reset */
bool vlan;
u16 vlan_id[AR40XX_MAX_VLANS];
u8 vlan_table[AR40XX_MAX_VLANS];
u8 vlan_tagged;
u16 pvid[AR40XX_NUM_PORTS];
/* mirror */
bool mirror_rx;
bool mirror_tx;
int source_port;
int monitor_port;
};
#define AR40XX_PORT_LINK_UP 1
#define AR40XX_PORT_LINK_DOWN 0
#define AR40XX_QM_NOT_EMPTY 1
#define AR40XX_QM_EMPTY 0
#define AR40XX_LAN_VLAN 1
#define AR40XX_WAN_VLAN 2
enum ar40xx_port_wrapper_cfg {
PORT_WRAPPER_PSGMII = 0,
};
struct ar40xx_mib_desc {
u32 size;
u32 offset;
const char *name;
};
#define AR40XX_PORT_CPU 0
#define AR40XX_PSGMII_MODE_CONTROL 0x1b4
#define AR40XX_PSGMII_ATHR_CSCO_MODE_25M BIT(0)
#define AR40XX_PSGMIIPHY_TX_CONTROL 0x288
#define AR40XX_MII_ATH_MMD_ADDR 0x0d
#define AR40XX_MII_ATH_MMD_DATA 0x0e
#define AR40XX_MII_ATH_DBG_ADDR 0x1d
#define AR40XX_MII_ATH_DBG_DATA 0x1e
#define AR40XX_STATS_RXBROAD 0x00
#define AR40XX_STATS_RXPAUSE 0x04
#define AR40XX_STATS_RXMULTI 0x08
#define AR40XX_STATS_RXFCSERR 0x0c
#define AR40XX_STATS_RXALIGNERR 0x10
#define AR40XX_STATS_RXRUNT 0x14
#define AR40XX_STATS_RXFRAGMENT 0x18
#define AR40XX_STATS_RX64BYTE 0x1c
#define AR40XX_STATS_RX128BYTE 0x20
#define AR40XX_STATS_RX256BYTE 0x24
#define AR40XX_STATS_RX512BYTE 0x28
#define AR40XX_STATS_RX1024BYTE 0x2c
#define AR40XX_STATS_RX1518BYTE 0x30
#define AR40XX_STATS_RXMAXBYTE 0x34
#define AR40XX_STATS_RXTOOLONG 0x38
#define AR40XX_STATS_RXGOODBYTE 0x3c
#define AR40XX_STATS_RXBADBYTE 0x44
#define AR40XX_STATS_RXOVERFLOW 0x4c
#define AR40XX_STATS_FILTERED 0x50
#define AR40XX_STATS_TXBROAD 0x54
#define AR40XX_STATS_TXPAUSE 0x58
#define AR40XX_STATS_TXMULTI 0x5c
#define AR40XX_STATS_TXUNDERRUN 0x60
#define AR40XX_STATS_TX64BYTE 0x64
#define AR40XX_STATS_TX128BYTE 0x68
#define AR40XX_STATS_TX256BYTE 0x6c
#define AR40XX_STATS_TX512BYTE 0x70
#define AR40XX_STATS_TX1024BYTE 0x74
#define AR40XX_STATS_TX1518BYTE 0x78
#define AR40XX_STATS_TXMAXBYTE 0x7c
#define AR40XX_STATS_TXOVERSIZE 0x80
#define AR40XX_STATS_TXBYTE 0x84
#define AR40XX_STATS_TXCOLLISION 0x8c
#define AR40XX_STATS_TXABORTCOL 0x90
#define AR40XX_STATS_TXMULTICOL 0x94
#define AR40XX_STATS_TXSINGLECOL 0x98
#define AR40XX_STATS_TXEXCDEFER 0x9c
#define AR40XX_STATS_TXDEFER 0xa0
#define AR40XX_STATS_TXLATECOL 0xa4
#define AR40XX_REG_MODULE_EN 0x030
#define AR40XX_MODULE_EN_MIB BIT(0)
#define AR40XX_REG_MIB_FUNC 0x034
#define AR40XX_MIB_BUSY BIT(17)
#define AR40XX_MIB_CPU_KEEP BIT(20)
#define AR40XX_MIB_FUNC BITS(24, 3)
#define AR40XX_MIB_FUNC_S 24
#define AR40XX_MIB_FUNC_NO_OP 0x0
#define AR40XX_MIB_FUNC_FLUSH 0x1
#define AR40XX_ESS_SERVICE_TAG 0x48
#define AR40XX_ESS_SERVICE_TAG_STAG BIT(17)
#define AR40XX_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
#define AR40XX_PORT_SPEED BITS(0, 2)
#define AR40XX_PORT_STATUS_SPEED_S 0
#define AR40XX_PORT_TX_EN BIT(2)
#define AR40XX_PORT_RX_EN BIT(3)
#define AR40XX_PORT_STATUS_TXFLOW BIT(4)
#define AR40XX_PORT_STATUS_RXFLOW BIT(5)
#define AR40XX_PORT_DUPLEX BIT(6)
#define AR40XX_PORT_TXHALF_FLOW BIT(7)
#define AR40XX_PORT_STATUS_LINK_UP BIT(8)
#define AR40XX_PORT_AUTO_LINK_EN BIT(9)
#define AR40XX_PORT_STATUS_FLOW_CONTROL BIT(12)
#define AR40XX_REG_MAX_FRAME_SIZE 0x078
#define AR40XX_MAX_FRAME_SIZE_MTU BITS(0, 14)
#define AR40XX_REG_PORT_HEADER(_i) (0x09c + (_i) * 4)
#define AR40XX_REG_EEE_CTRL 0x100
#define AR40XX_EEE_CTRL_DISABLE_PHY(_i) BIT(4 + (_i) * 2)
#define AR40XX_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8)
#define AR40XX_PORT_VLAN0_DEF_SVID BITS(0, 12)
#define AR40XX_PORT_VLAN0_DEF_SVID_S 0
#define AR40XX_PORT_VLAN0_DEF_CVID BITS(16, 12)
#define AR40XX_PORT_VLAN0_DEF_CVID_S 16
#define AR40XX_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8)
#define AR40XX_PORT_VLAN1_CORE_PORT BIT(9)
#define AR40XX_PORT_VLAN1_PORT_TLS_MODE BIT(7)
#define AR40XX_PORT_VLAN1_PORT_VLAN_PROP BIT(6)
#define AR40XX_PORT_VLAN1_OUT_MODE BITS(12, 2)
#define AR40XX_PORT_VLAN1_OUT_MODE_S 12
#define AR40XX_PORT_VLAN1_OUT_MODE_UNMOD 0
#define AR40XX_PORT_VLAN1_OUT_MODE_UNTAG 1
#define AR40XX_PORT_VLAN1_OUT_MODE_TAG 2
#define AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH 3
#define AR40XX_REG_VTU_FUNC0 0x0610
#define AR40XX_VTU_FUNC0_EG_MODE BITS(4, 14)
#define AR40XX_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2)
#define AR40XX_VTU_FUNC0_EG_MODE_KEEP 0
#define AR40XX_VTU_FUNC0_EG_MODE_UNTAG 1
#define AR40XX_VTU_FUNC0_EG_MODE_TAG 2
#define AR40XX_VTU_FUNC0_EG_MODE_NOT 3
#define AR40XX_VTU_FUNC0_IVL BIT(19)
#define AR40XX_VTU_FUNC0_VALID BIT(20)
#define AR40XX_REG_VTU_FUNC1 0x0614
#define AR40XX_VTU_FUNC1_OP BITS(0, 3)
#define AR40XX_VTU_FUNC1_OP_NOOP 0
#define AR40XX_VTU_FUNC1_OP_FLUSH 1
#define AR40XX_VTU_FUNC1_OP_LOAD 2
#define AR40XX_VTU_FUNC1_OP_PURGE 3
#define AR40XX_VTU_FUNC1_OP_REMOVE_PORT 4
#define AR40XX_VTU_FUNC1_OP_GET_NEXT 5
#define AR40XX7_VTU_FUNC1_OP_GET_ONE 6
#define AR40XX_VTU_FUNC1_FULL BIT(4)
#define AR40XX_VTU_FUNC1_PORT BIT(8, 4)
#define AR40XX_VTU_FUNC1_PORT_S 8
#define AR40XX_VTU_FUNC1_VID BIT(16, 12)
#define AR40XX_VTU_FUNC1_VID_S 16
#define AR40XX_VTU_FUNC1_BUSY BIT(31)
#define AR40XX_REG_FWD_CTRL0 0x620
#define AR40XX_FWD_CTRL0_CPU_PORT_EN BIT(10)
#define AR40XX_FWD_CTRL0_MIRROR_PORT BITS(4, 4)
#define AR40XX_FWD_CTRL0_MIRROR_PORT_S 4
#define AR40XX_REG_FWD_CTRL1 0x624
#define AR40XX_FWD_CTRL1_UC_FLOOD BITS(0, 7)
#define AR40XX_FWD_CTRL1_UC_FLOOD_S 0
#define AR40XX_FWD_CTRL1_MC_FLOOD BITS(8, 7)
#define AR40XX_FWD_CTRL1_MC_FLOOD_S 8
#define AR40XX_FWD_CTRL1_BC_FLOOD BITS(16, 7)
#define AR40XX_FWD_CTRL1_BC_FLOOD_S 16
#define AR40XX_FWD_CTRL1_IGMP BITS(24, 7)
#define AR40XX_FWD_CTRL1_IGMP_S 24
#define AR40XX_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc)
#define AR40XX_PORT_LOOKUP_MEMBER BITS(0, 7)
#define AR40XX_PORT_LOOKUP_IN_MODE BITS(8, 2)
#define AR40XX_PORT_LOOKUP_IN_MODE_S 8
#define AR40XX_PORT_LOOKUP_STATE BITS(16, 3)
#define AR40XX_PORT_LOOKUP_STATE_S 16
#define AR40XX_PORT_LOOKUP_LEARN BIT(20)
#define AR40XX_PORT_LOOKUP_LOOPBACK BIT(21)
#define AR40XX_PORT_LOOKUP_ING_MIRROR_EN BIT(25)
#define AR40XX_REG_ATU_FUNC 0x60c
#define AR40XX_ATU_FUNC_OP BITS(0, 4)
#define AR40XX_ATU_FUNC_OP_NOOP 0x0
#define AR40XX_ATU_FUNC_OP_FLUSH 0x1
#define AR40XX_ATU_FUNC_OP_LOAD 0x2
#define AR40XX_ATU_FUNC_OP_PURGE 0x3
#define AR40XX_ATU_FUNC_OP_FLUSH_LOCKED 0x4
#define AR40XX_ATU_FUNC_OP_FLUSH_UNICAST 0x5
#define AR40XX_ATU_FUNC_OP_GET_NEXT 0x6
#define AR40XX_ATU_FUNC_OP_SEARCH_MAC 0x7
#define AR40XX_ATU_FUNC_OP_CHANGE_TRUNK 0x8
#define AR40XX_ATU_FUNC_BUSY BIT(31)
#define AR40XX_REG_QM_DEBUG_ADDR 0x820
#define AR40XX_REG_QM_DEBUG_VALUE 0x824
#define AR40XX_REG_QM_PORT0_3_QNUM 0x1d
#define AR40XX_REG_QM_PORT4_6_QNUM 0x1e
#define AR40XX_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
#define AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16)
#define AR40XX_REG_PORT_FLOWCTRL_THRESH(_i) (0x9b0 + (_i) * 0x4)
#define AR40XX_PORT0_FC_THRESH_ON_DFLT 0x60
#define AR40XX_PORT0_FC_THRESH_OFF_DFLT 0x90
#define AR40XX_PHY_DEBUG_0 0
#define AR40XX_PHY_MANU_CTRL_EN BIT(12)
#define AR40XX_PHY_DEBUG_2 2
#define AR40XX_PHY_SPEC_STATUS 0x11
#define AR40XX_PHY_SPEC_STATUS_LINK BIT(10)
#define AR40XX_PHY_SPEC_STATUS_DUPLEX BIT(13)
#define AR40XX_PHY_SPEC_STATUS_SPEED BITS(14, 2)
/* port forwarding state */
enum {
AR40XX_PORT_STATE_DISABLED = 0,
AR40XX_PORT_STATE_BLOCK = 1,
AR40XX_PORT_STATE_LISTEN = 2,
AR40XX_PORT_STATE_LEARN = 3,
AR40XX_PORT_STATE_FORWARD = 4
};
/* ingress 802.1q mode */
enum {
AR40XX_IN_PORT_ONLY = 0,
AR40XX_IN_PORT_FALLBACK = 1,
AR40XX_IN_VLAN_ONLY = 2,
AR40XX_IN_SECURE = 3
};
/* egress 802.1q mode */
enum {
AR40XX_OUT_KEEP = 0,
AR40XX_OUT_STRIP_VLAN = 1,
AR40XX_OUT_ADD_VLAN = 2
};
/* port speed */
enum {
AR40XX_PORT_SPEED_10M = 0,
AR40XX_PORT_SPEED_100M = 1,
AR40XX_PORT_SPEED_1000M = 2,
AR40XX_PORT_SPEED_ERR = 3,
};
#define AR40XX_MIB_WORK_DELAY 2000 /* msecs */
#define AR40XX_QM_WORK_DELAY 100
#define AR40XX_MIB_FUNC_CAPTURE 0x3
#define AR40XX_REG_PORT_STATS_START 0x1000
#define AR40XX_REG_PORT_STATS_LEN 0x100
#define AR40XX_PORTS_ALL 0x3f
#define AR40XX_PSGMII_ID 5
#define AR40XX_PSGMII_CALB_NUM 100
#define AR40XX_MALIBU_PSGMII_MODE_CTRL 0x6d
#define AR40XX_MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VAL 0x220c
#define AR40XX_MALIBU_PHY_MMD7_DAC_CTRL 0x801a
#define AR40XX_MALIBU_DAC_CTRL_MASK 0x380
#define AR40XX_MALIBU_DAC_CTRL_VALUE 0x280
#define AR40XX_MALIBU_PHY_RLP_CTRL 0x805a
#define AR40XX_PSGMII_TX_DRIVER_1_CTRL 0xb
#define AR40XX_MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP 0x8a
#define AR40XX_MALIBU_PHY_LAST_ADDR 4
static inline struct ar40xx_priv *
swdev_to_ar40xx(struct switch_dev *swdev)
{
return container_of(swdev, struct ar40xx_priv, dev);
}
#endif

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/*
* Copyright (c) 2016, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all copies.
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __AR40XX_H
#define __AR40XX_H
#define AR40XX_MAX_VLANS 128
#define AR40XX_NUM_PORTS 6
#define AR40XX_NUM_PHYS 5
#define BITS(_s, _n) (((1UL << (_n)) - 1) << _s)
struct ar40xx_priv {
struct switch_dev dev;
u8 __iomem *hw_addr;
u8 __iomem *psgmii_hw_addr;
u32 mac_mode;
struct reset_control *ess_rst;
u32 cpu_bmp;
u32 lan_bmp;
u32 wan_bmp;
struct mii_bus *mii_bus;
struct phy_device *phy;
/* mutex for qm task */
struct mutex qm_lock;
struct delayed_work qm_dwork;
u32 port_link_up[AR40XX_NUM_PORTS];
u32 ar40xx_port_old_link[AR40XX_NUM_PORTS];
u32 ar40xx_port_qm_buf[AR40XX_NUM_PORTS];
u32 phy_t_status;
/* mutex for switch reg access */
struct mutex reg_mutex;
/* mutex for mib task */
struct mutex mib_lock;
struct delayed_work mib_work;
int mib_next_port;
u64 *mib_stats;
char buf[2048];
/* all fields below will be cleared on reset */
bool vlan;
u16 vlan_id[AR40XX_MAX_VLANS];
u8 vlan_table[AR40XX_MAX_VLANS];
u8 vlan_tagged;
u16 pvid[AR40XX_NUM_PORTS];
/* mirror */
bool mirror_rx;
bool mirror_tx;
int source_port;
int monitor_port;
};
#define AR40XX_PORT_LINK_UP 1
#define AR40XX_PORT_LINK_DOWN 0
#define AR40XX_QM_NOT_EMPTY 1
#define AR40XX_QM_EMPTY 0
#define AR40XX_LAN_VLAN 1
#define AR40XX_WAN_VLAN 2
enum ar40xx_port_wrapper_cfg {
PORT_WRAPPER_PSGMII = 0,
};
struct ar40xx_mib_desc {
u32 size;
u32 offset;
const char *name;
};
#define AR40XX_PORT_CPU 0
#define AR40XX_PSGMII_MODE_CONTROL 0x1b4
#define AR40XX_PSGMII_ATHR_CSCO_MODE_25M BIT(0)
#define AR40XX_PSGMIIPHY_TX_CONTROL 0x288
#define AR40XX_MII_ATH_MMD_ADDR 0x0d
#define AR40XX_MII_ATH_MMD_DATA 0x0e
#define AR40XX_MII_ATH_DBG_ADDR 0x1d
#define AR40XX_MII_ATH_DBG_DATA 0x1e
#define AR40XX_STATS_RXBROAD 0x00
#define AR40XX_STATS_RXPAUSE 0x04
#define AR40XX_STATS_RXMULTI 0x08
#define AR40XX_STATS_RXFCSERR 0x0c
#define AR40XX_STATS_RXALIGNERR 0x10
#define AR40XX_STATS_RXRUNT 0x14
#define AR40XX_STATS_RXFRAGMENT 0x18
#define AR40XX_STATS_RX64BYTE 0x1c
#define AR40XX_STATS_RX128BYTE 0x20
#define AR40XX_STATS_RX256BYTE 0x24
#define AR40XX_STATS_RX512BYTE 0x28
#define AR40XX_STATS_RX1024BYTE 0x2c
#define AR40XX_STATS_RX1518BYTE 0x30
#define AR40XX_STATS_RXMAXBYTE 0x34
#define AR40XX_STATS_RXTOOLONG 0x38
#define AR40XX_STATS_RXGOODBYTE 0x3c
#define AR40XX_STATS_RXBADBYTE 0x44
#define AR40XX_STATS_RXOVERFLOW 0x4c
#define AR40XX_STATS_FILTERED 0x50
#define AR40XX_STATS_TXBROAD 0x54
#define AR40XX_STATS_TXPAUSE 0x58
#define AR40XX_STATS_TXMULTI 0x5c
#define AR40XX_STATS_TXUNDERRUN 0x60
#define AR40XX_STATS_TX64BYTE 0x64
#define AR40XX_STATS_TX128BYTE 0x68
#define AR40XX_STATS_TX256BYTE 0x6c
#define AR40XX_STATS_TX512BYTE 0x70
#define AR40XX_STATS_TX1024BYTE 0x74
#define AR40XX_STATS_TX1518BYTE 0x78
#define AR40XX_STATS_TXMAXBYTE 0x7c
#define AR40XX_STATS_TXOVERSIZE 0x80
#define AR40XX_STATS_TXBYTE 0x84
#define AR40XX_STATS_TXCOLLISION 0x8c
#define AR40XX_STATS_TXABORTCOL 0x90
#define AR40XX_STATS_TXMULTICOL 0x94
#define AR40XX_STATS_TXSINGLECOL 0x98
#define AR40XX_STATS_TXEXCDEFER 0x9c
#define AR40XX_STATS_TXDEFER 0xa0
#define AR40XX_STATS_TXLATECOL 0xa4
#define AR40XX_REG_MODULE_EN 0x030
#define AR40XX_MODULE_EN_MIB BIT(0)
#define AR40XX_REG_MIB_FUNC 0x034
#define AR40XX_MIB_BUSY BIT(17)
#define AR40XX_MIB_CPU_KEEP BIT(20)
#define AR40XX_MIB_FUNC BITS(24, 3)
#define AR40XX_MIB_FUNC_S 24
#define AR40XX_MIB_FUNC_NO_OP 0x0
#define AR40XX_MIB_FUNC_FLUSH 0x1
#define AR40XX_ESS_SERVICE_TAG 0x48
#define AR40XX_ESS_SERVICE_TAG_STAG BIT(17)
#define AR40XX_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
#define AR40XX_PORT_SPEED BITS(0, 2)
#define AR40XX_PORT_STATUS_SPEED_S 0
#define AR40XX_PORT_TX_EN BIT(2)
#define AR40XX_PORT_RX_EN BIT(3)
#define AR40XX_PORT_STATUS_TXFLOW BIT(4)
#define AR40XX_PORT_STATUS_RXFLOW BIT(5)
#define AR40XX_PORT_DUPLEX BIT(6)
#define AR40XX_PORT_TXHALF_FLOW BIT(7)
#define AR40XX_PORT_STATUS_LINK_UP BIT(8)
#define AR40XX_PORT_AUTO_LINK_EN BIT(9)
#define AR40XX_PORT_STATUS_FLOW_CONTROL BIT(12)
#define AR40XX_REG_MAX_FRAME_SIZE 0x078
#define AR40XX_MAX_FRAME_SIZE_MTU BITS(0, 14)
#define AR40XX_REG_PORT_HEADER(_i) (0x09c + (_i) * 4)
#define AR40XX_REG_EEE_CTRL 0x100
#define AR40XX_EEE_CTRL_DISABLE_PHY(_i) BIT(4 + (_i) * 2)
#define AR40XX_REG_PORT_VLAN0(_i) (0x420 + (_i) * 0x8)
#define AR40XX_PORT_VLAN0_DEF_SVID BITS(0, 12)
#define AR40XX_PORT_VLAN0_DEF_SVID_S 0
#define AR40XX_PORT_VLAN0_DEF_CVID BITS(16, 12)
#define AR40XX_PORT_VLAN0_DEF_CVID_S 16
#define AR40XX_REG_PORT_VLAN1(_i) (0x424 + (_i) * 0x8)
#define AR40XX_PORT_VLAN1_CORE_PORT BIT(9)
#define AR40XX_PORT_VLAN1_PORT_TLS_MODE BIT(7)
#define AR40XX_PORT_VLAN1_PORT_VLAN_PROP BIT(6)
#define AR40XX_PORT_VLAN1_OUT_MODE BITS(12, 2)
#define AR40XX_PORT_VLAN1_OUT_MODE_S 12
#define AR40XX_PORT_VLAN1_OUT_MODE_UNMOD 0
#define AR40XX_PORT_VLAN1_OUT_MODE_UNTAG 1
#define AR40XX_PORT_VLAN1_OUT_MODE_TAG 2
#define AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH 3
#define AR40XX_REG_VTU_FUNC0 0x0610
#define AR40XX_VTU_FUNC0_EG_MODE BITS(4, 14)
#define AR40XX_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2)
#define AR40XX_VTU_FUNC0_EG_MODE_KEEP 0
#define AR40XX_VTU_FUNC0_EG_MODE_UNTAG 1
#define AR40XX_VTU_FUNC0_EG_MODE_TAG 2
#define AR40XX_VTU_FUNC0_EG_MODE_NOT 3
#define AR40XX_VTU_FUNC0_IVL BIT(19)
#define AR40XX_VTU_FUNC0_VALID BIT(20)
#define AR40XX_REG_VTU_FUNC1 0x0614
#define AR40XX_VTU_FUNC1_OP BITS(0, 3)
#define AR40XX_VTU_FUNC1_OP_NOOP 0
#define AR40XX_VTU_FUNC1_OP_FLUSH 1
#define AR40XX_VTU_FUNC1_OP_LOAD 2
#define AR40XX_VTU_FUNC1_OP_PURGE 3
#define AR40XX_VTU_FUNC1_OP_REMOVE_PORT 4
#define AR40XX_VTU_FUNC1_OP_GET_NEXT 5
#define AR40XX7_VTU_FUNC1_OP_GET_ONE 6
#define AR40XX_VTU_FUNC1_FULL BIT(4)
#define AR40XX_VTU_FUNC1_PORT BIT(8, 4)
#define AR40XX_VTU_FUNC1_PORT_S 8
#define AR40XX_VTU_FUNC1_VID BIT(16, 12)
#define AR40XX_VTU_FUNC1_VID_S 16
#define AR40XX_VTU_FUNC1_BUSY BIT(31)
#define AR40XX_REG_FWD_CTRL0 0x620
#define AR40XX_FWD_CTRL0_CPU_PORT_EN BIT(10)
#define AR40XX_FWD_CTRL0_MIRROR_PORT BITS(4, 4)
#define AR40XX_FWD_CTRL0_MIRROR_PORT_S 4
#define AR40XX_REG_FWD_CTRL1 0x624
#define AR40XX_FWD_CTRL1_UC_FLOOD BITS(0, 7)
#define AR40XX_FWD_CTRL1_UC_FLOOD_S 0
#define AR40XX_FWD_CTRL1_MC_FLOOD BITS(8, 7)
#define AR40XX_FWD_CTRL1_MC_FLOOD_S 8
#define AR40XX_FWD_CTRL1_BC_FLOOD BITS(16, 7)
#define AR40XX_FWD_CTRL1_BC_FLOOD_S 16
#define AR40XX_FWD_CTRL1_IGMP BITS(24, 7)
#define AR40XX_FWD_CTRL1_IGMP_S 24
#define AR40XX_REG_PORT_LOOKUP(_i) (0x660 + (_i) * 0xc)
#define AR40XX_PORT_LOOKUP_MEMBER BITS(0, 7)
#define AR40XX_PORT_LOOKUP_IN_MODE BITS(8, 2)
#define AR40XX_PORT_LOOKUP_IN_MODE_S 8
#define AR40XX_PORT_LOOKUP_STATE BITS(16, 3)
#define AR40XX_PORT_LOOKUP_STATE_S 16
#define AR40XX_PORT_LOOKUP_LEARN BIT(20)
#define AR40XX_PORT_LOOKUP_LOOPBACK BIT(21)
#define AR40XX_PORT_LOOKUP_ING_MIRROR_EN BIT(25)
#define AR40XX_REG_ATU_FUNC 0x60c
#define AR40XX_ATU_FUNC_OP BITS(0, 4)
#define AR40XX_ATU_FUNC_OP_NOOP 0x0
#define AR40XX_ATU_FUNC_OP_FLUSH 0x1
#define AR40XX_ATU_FUNC_OP_LOAD 0x2
#define AR40XX_ATU_FUNC_OP_PURGE 0x3
#define AR40XX_ATU_FUNC_OP_FLUSH_LOCKED 0x4
#define AR40XX_ATU_FUNC_OP_FLUSH_UNICAST 0x5
#define AR40XX_ATU_FUNC_OP_GET_NEXT 0x6
#define AR40XX_ATU_FUNC_OP_SEARCH_MAC 0x7
#define AR40XX_ATU_FUNC_OP_CHANGE_TRUNK 0x8
#define AR40XX_ATU_FUNC_BUSY BIT(31)
#define AR40XX_REG_QM_DEBUG_ADDR 0x820
#define AR40XX_REG_QM_DEBUG_VALUE 0x824
#define AR40XX_REG_QM_PORT0_3_QNUM 0x1d
#define AR40XX_REG_QM_PORT4_6_QNUM 0x1e
#define AR40XX_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
#define AR40XX_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16)
#define AR40XX_REG_PORT_FLOWCTRL_THRESH(_i) (0x9b0 + (_i) * 0x4)
#define AR40XX_PORT0_FC_THRESH_ON_DFLT 0x60
#define AR40XX_PORT0_FC_THRESH_OFF_DFLT 0x90
#define AR40XX_PHY_DEBUG_0 0
#define AR40XX_PHY_MANU_CTRL_EN BIT(12)
#define AR40XX_PHY_DEBUG_2 2
#define AR40XX_PHY_SPEC_STATUS 0x11
#define AR40XX_PHY_SPEC_STATUS_LINK BIT(10)
#define AR40XX_PHY_SPEC_STATUS_DUPLEX BIT(13)
#define AR40XX_PHY_SPEC_STATUS_SPEED BITS(14, 2)
/* port forwarding state */
enum {
AR40XX_PORT_STATE_DISABLED = 0,
AR40XX_PORT_STATE_BLOCK = 1,
AR40XX_PORT_STATE_LISTEN = 2,
AR40XX_PORT_STATE_LEARN = 3,
AR40XX_PORT_STATE_FORWARD = 4
};
/* ingress 802.1q mode */
enum {
AR40XX_IN_PORT_ONLY = 0,
AR40XX_IN_PORT_FALLBACK = 1,
AR40XX_IN_VLAN_ONLY = 2,
AR40XX_IN_SECURE = 3
};
/* egress 802.1q mode */
enum {
AR40XX_OUT_KEEP = 0,
AR40XX_OUT_STRIP_VLAN = 1,
AR40XX_OUT_ADD_VLAN = 2
};
/* port speed */
enum {
AR40XX_PORT_SPEED_10M = 0,
AR40XX_PORT_SPEED_100M = 1,
AR40XX_PORT_SPEED_1000M = 2,
AR40XX_PORT_SPEED_ERR = 3,
};
#define AR40XX_MIB_WORK_DELAY 2000 /* msecs */
#define AR40XX_QM_WORK_DELAY 100
#define AR40XX_MIB_FUNC_CAPTURE 0x3
#define AR40XX_REG_PORT_STATS_START 0x1000
#define AR40XX_REG_PORT_STATS_LEN 0x100
#define AR40XX_PORTS_ALL 0x3f
#define AR40XX_PSGMII_ID 5
#define AR40XX_PSGMII_CALB_NUM 100
#define AR40XX_MALIBU_PSGMII_MODE_CTRL 0x6d
#define AR40XX_MALIBU_PHY_PSGMII_MODE_CTRL_ADJUST_VAL 0x220c
#define AR40XX_MALIBU_PHY_MMD7_DAC_CTRL 0x801a
#define AR40XX_MALIBU_DAC_CTRL_MASK 0x380
#define AR40XX_MALIBU_DAC_CTRL_VALUE 0x280
#define AR40XX_MALIBU_PHY_RLP_CTRL 0x805a
#define AR40XX_PSGMII_TX_DRIVER_1_CTRL 0xb
#define AR40XX_MALIBU_PHY_PSGMII_REDUCE_SERDES_TX_AMP 0x8a
#define AR40XX_MALIBU_PHY_LAST_ADDR 4
static inline struct ar40xx_priv *
swdev_to_ar40xx(struct switch_dev *swdev)
{
return container_of(swdev, struct ar40xx_priv, dev);
}
#endif

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// SPDX-License-Identifier: ISC
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
* Copyright (c) 2017, Sven Eckelmann <sven.eckelmann@openmesh.com>
*/
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "OpenMesh A42";
compatible = "openmesh,a42";
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2: usb2@60f8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
aliases {
led-boot = &led_status_green;
led-failsafe = &led_status_green;
led-running = &led_status_green;
led-upgrade = &led_status_green;
};
leds {
compatible = "gpio-leds";
status_red {
label = "red:status";
gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
};
led_status_green: status_green {
label = "green:status";
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
};
status_blue {
label = "blue:status";
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
};
};
watchdog {
compatible = "linux,wdt-gpio";
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
hw_algo = "toggle";
/* hw_margin_ms is actually 300s but driver limits it to 60s */
hw_margin_ms = <60000>;
always-running;
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
/* partitions are passed via bootloader */
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&gmac0 {
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <2 0x20>;
};
&gmac1 {
qcom,phy_mdio_addr = <3>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <1 0x10>;
};
&usb2_hs_phy {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "OM-A42";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "OM-A42";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "ALFA Network AP120C-AC";
compatible = "alfa-network,ap120c-ac";
aliases {
led-boot = &status;
led-failsafe = &status;
led-running = &status;
led-upgrade = &status;
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
status: status {
label = "blue:status";
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
default-state = "keep";
};
wan {
label = "amber:wan";
gpios = <&ethphy4 1 GPIO_ACTIVE_HIGH>;
};
wlan2g {
label = "green:wlan2g";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tpt";
};
wlan5g {
label = "red:wlan5g";
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy1tpt";
};
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
};
ess-psgmii@98000 {
status = "okay";
};
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
};
usb3@8af8800 {
status = "okay";
dwc3@8a00000 {
phys = <&usb3_hs_phy>;
phy-names = "usb2-phy";
};
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_lan_bmp = <0x10>;
switch_wan_bmp = <0x20>;
};
edma@c080000 {
status = "okay";
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_i2c3 {
status = "okay";
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
tpm@29 {
compatible = "atmel,at97sc3204t";
reg = <0x29>;
};
};
&blsp1_spi1 {
status = "okay";
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
<&tlmm 4 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition@d0000 {
label = "DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition@e0000 {
label = "APPSBLENV";
reg = <0x000e0000 0x00010000>;
};
partition@f0000 {
label = "APPSBL";
reg = <0x000f0000 0x00080000>;
read-only;
};
partition@170000 {
label = "ART";
reg = <0x00170000 0x00010000>;
read-only;
};
partition@180000 {
label = "priv_data1";
reg = <0x00180000 0x00010000>;
read-only;
};
partition@190000 {
label = "priv_data2";
reg = <0x00190000 0x00010000>;
read-only;
};
};
};
nand@1 {
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "rootfs1";
reg = <0x00000000 0x04000000>;
};
partition@4000000 {
label = "rootfs2";
reg = <0x04000000 0x04000000>;
};
};
};
};
&blsp1_uart1 {
status = "okay";
pinctrl-0 = <&serial0_pins>;
pinctrl-names = "default";
};
&cryptobam {
status = "okay";
};
&ethphy4 {
gpio-controller;
#gpio-cells = <2>;
};
&gmac0 {
qcom,forced_duplex = <1>;
qcom,forced_speed = <1000>;
qcom,phy_mdio_addr = <3>;
qcom,poll_required = <1>;
vlan_tag = <1 0x10>;
};
&gmac1 {
qcom,forced_duplex = <1>;
qcom,forced_speed = <1000>;
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <1>;
vlan_tag = <2 0x20>;
};
&tlmm {
i2c0_pins: i2c0_pinmux {
mux_i2c {
function = "blsp_i2c0";
pins = "gpio58", "gpio59";
drive-strength = <16>;
bias-disable;
};
};
mdio_pins: mdio_pinmux {
mux_mdio {
pins = "gpio53";
function = "mdio";
bias-pull-up;
};
mux_mdc {
pins = "gpio52";
function = "mdc";
bias-pull-up;
};
};
serial0_pins: serial0_pinmux {
mux_uart {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi0_pins: spi0_pinmux {
mux_spi {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
mux_cs {
function = "gpio";
pins = "gpio54", "gpio4";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&usb2_hs_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&wifi0 {
status = "okay";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC";
};

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// SPDX-License-Identifier: GPL-2.0-only OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "EZVIZ CS-W3-WD1200G EUP";
compatible = "ezviz,cs-w3-wd1200g-eup";
aliases {
led-boot = &led_status_green;
led-failsafe = &led_status_red;
led-running = &led_status_blue;
led-upgrade = &led_status_green;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
reset-delay-us = <5000>;
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
leds {
compatible = "gpio-leds";
led_status_red: status_red {
label = "red:status";
gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
};
led_status_green: status_green {
label = "green:status";
gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
};
led_status_blue: status_blue {
label = "blue:status";
gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio53";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio52";
function = "mdc";
bias-pull-up;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition0@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition1@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition2@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition3@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition4@d0000 {
label = "DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition5@E0000 {
label = "APPSBLENV";
reg = <0x000e0000 0x00010000>;
read-only;
};
partition6@F0000 {
label = "APPSBL";
reg = <0x000f0000 0x00080000>;
read-only;
};
partition7@170000 {
label = "ART";
reg = <0x00170000 0x00010000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
precal_art_1000: precal@1000 {
reg = <0x1000 0x2f20>;
};
precal_art_5000: precal@5000 {
reg = <0x5000 0x2f20>;
};
};
partition9@580000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x00180000 0x00e80000>;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "ezviz-cs-w3-wd1200g-eup";
nvmem-cell-names = "pre-calibration";
nvmem-cells = <&precal_art_1000>;
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "ezviz-cs-w3-wd1200g-eup";
nvmem-cell-names = "pre-calibration";
nvmem-cells = <&precal_art_5000>;
};
&gmac0 {
nvmem-cell-names = "mac-address";
nvmem-cells = <&macaddr_art_6>;
};
&gmac1 {
nvmem-cell-names = "mac-address";
nvmem-cells = <&macaddr_art_0>;
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "D-Link DAP 2610";
compatible = "dlink,dap-2610";
aliases {
led-boot = &led_red;
led-failsafe = &led_red;
led-running = &led_green;
led-upgrade = &led_red;
};
soc {
edma@c080000 {
qcom,num_gmac = <1>;
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
rng@22000 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_lan_bmp = <0x20>;
switch_wan_bmp = <0x00>;
};
ess-psgmii@98000 {
status = "okay";
};
};
leds {
compatible = "gpio-leds";
led_red: red {
label = "red:power";
gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
};
led_green: green {
label = "green:power";
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fixed-partitions";
partition@0 {
label = "SBL1";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "MIBIB";
reg = <0x40000 0x20000>;
read-only;
};
partition@60000 {
label = "QSEE";
reg = <0x60000 0x60000>;
read-only;
};
partition@c0000 {
label = "CDT";
reg = <0xc0000 0x10000>;
read-only;
};
partition@d0000 {
label = "DDRPARAMS";
reg = <0xd0000 0x10000>;
read-only;
};
partition@e0000 {
label = "APPSBLENV";
reg = <0xe0000 0x10000>;
read-only;
};
partition@f0000 {
label = "APPSBL";
reg = <0xf0000 0x80000>;
read-only;
};
partition@170000 {
label = "ART";
reg = <0x170000 0x10000>;
read-only;
};
partition@180000 {
compatible = "wrg";
label = "firmware";
reg = <0x180000 0xdc0000>;
};
partition@fb0000 {
label = "rgbd";
reg = <0xfb0000 0x10000>;
read-only;
};
partition@fc0000 {
label = "bdcfg";
reg = <0xfc0000 0x10000>;
read-only;
};
partition@fd0000 {
label = "langpack";
reg = <0xfd0000 0x20000>;
read-only;
};
partition@ff0000 {
label = "certificate";
reg = <0xff0000 0x10000>;
read-only;
};
partition@f40000 {
label = "captival";
reg = <0xf40000 0x70000>;
read-only;
};
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&gmac0 {
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <1 0x20>;
};
&mdio {
status = "okay";
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
mux {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
mux_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "dlink,dap-2610";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "dlink,dap-2610";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Linksys EA6350v3";
compatible = "linksys,ea6350v3";
aliases {
led-boot = &power;
led-failsafe = &power;
led-running = &power;
led-upgrade = &power;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
};
usb3@8af8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
wps {
label = "wps";
gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
leds {
compatible = "gpio-leds";
power: status {
label = "green:status";
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "linksys-ea6350v3";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "linksys-ea6350v3";
};
&blsp_dma {
status = "okay";
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
mux {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
mux_cs {
function = "gpio";
pins = "gpio54", "gpio59";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp1_spi1 { /* BLSP1 QUP1 */
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
<&tlmm 59 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
SBL1@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
MBIB@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
QSEE@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
CDT@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
APPSBLENV@d0000 {
label = "APPSBLENV";
reg = <0x000d0000 0x00010000>;
read-only;
};
APPSBL@e0000 {
label = "APPSBL"; /* uboot */
reg = <0x000e0000 0x00080000>;
read-only;
};
ART@160000 {
label = "ART";
reg = <0x00160000 0x00010000>;
read-only;
};
u_env@170000 {
label = "u_env";
reg = <0x00170000 0x00020000>;
};
s_env@190000 {
label = "s_env";
reg = <0x00190000 0x00020000>;
};
devinfo@1b0000 {
label = "devinfo";
reg = <0x001b0000 0x00010000>;
};
/* 0x001c0000 - 0x00200000 unused */
};
};
flash@1 {
status = "okay";
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
kernel@0 {
label = "kernel";
reg = <0x00000000 0x02800000>;
};
rootfs@300000 {
label = "rootfs";
reg = <0x00300000 0x02500000>;
};
alt_kernel@2800000 {
label = "alt_kernel";
reg = <0x02800000 0x02800000>;
};
alt_rootfs@2b00000 {
label = "alt_rootfs";
reg = <0x02b00000 0x02500000>;
};
sysdiag@5000000 {
label = "sysdiag";
reg = <0x05000000 0x00100000>;
};
syscfg@5100000 {
label = "syscfg";
reg = <0x05100000 0x02F00000>;
};
/* 0x00000000 - 0x08000000: 128 MiB */
};
};
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0-or-later
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "EnGenius EAP1300";
compatible = "engenius,eap1300";
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_RESTART>;
};
};
aliases {
led-boot = &power;
led-failsafe = &power;
led-running = &power;
led-upgrade = &power;
};
leds {
compatible = "gpio-leds";
power: orange {
label = "orange:power";
gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
};
lan {
label = "blue:lan";
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
};
mesh {
label = "blue:mesh";
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
};
wlan2g {
label = "blue:wlan2g";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
};
wlan5g {
label = "yellow:wlan5g";
gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
};
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio54", "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
m25p80@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition1@40000 {
label = "0:MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition2@60000 {
label = "0:QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition3@c0000 {
label = "0:CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition4@d0000 {
label = "0:DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition5@e0000 {
label = "0:APPSBLENV";
reg = <0x000e0000 0x00010000>;
read-only;
};
partition6@f0000 {
label = "0:APPSBL";
reg = <0x000f0000 0x00090000>;
read-only;
};
partition7@180000 {
label = "0:ART";
reg = <0x00180000 0x00010000>;
read-only;
};
partition8@190000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x190000 0x1dc0000>;
};
partition9@1f50000 {
label = "u-boot-env";
reg = <0x01f50000 0x00010000>;
};
partition10@1f60000 {
label = "userconfig";
reg = <0x01f60000 0x000a0000>;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&gmac0 {
vlan_tag = <2 0x20>;
};
&gmac1 {
vlan_tag = <1 0x10>;
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "EnGenius-EAP1300";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "EnGenius-EAP1300";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Edgecore ECW5211";
compatible = "edgecore,ecw5211";
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
label-mac-device = &gmac0;
};
chosen {
bootargs-append = " root=/dev/ubiblock0_1";
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
led_power: power {
label = "yellow:power";
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
};
wlan2g {
label = "green:wlan2g";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tpt";
};
wlan5g {
label = "green:wlan5g";
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy1tpt";
};
};
soc {
rng@22000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
};
usb3@8af8800 {
status = "okay";
dwc3@8a00000 {
phys = <&usb3_hs_phy>;
phy-names = "usb2-phy";
};
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_lan_bmp = <0x10>;
switch_wan_bmp = <0x20>;
};
edma@c080000 {
status = "okay";
};
};
};
&tlmm {
mdio_pins: mdio_pinmux {
mux_mdio {
pins = "gpio53";
function = "mdio";
bias-pull-up;
};
mux_mdc {
pins = "gpio52";
function = "mdc";
bias-pull-up;
};
};
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi0_pins: spi0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <2>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio54", "gpio4";
drive-strength = <2>;
bias-disable;
output-high;
};
};
i2c0_pins: i2c0_pinmux {
mux_i2c {
function = "blsp_i2c0";
pins = "gpio58", "gpio59";
drive-strength = <16>;
bias-disable;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
status = "okay";
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 4 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition@40000 {
label = "0:MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition@60000 {
label = "0:QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition@c0000 {
label = "0:CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition@d0000 {
label = "0:DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition@e0000 {
label = "0:APPSBLENV"; /* uboot env */
reg = <0x000e0000 0x00010000>;
};
partition@f0000 {
label = "0:APPSBL"; /* uboot */
reg = <0x000f0000 0x00080000>;
read-only;
};
partition@170000 {
label = "0:ART";
reg = <0x00170000 0x00010000>;
read-only;
};
};
};
flash@1 {
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "rootfs";
reg = <0x00000000 0x04000000>;
};
};
};
};
&blsp1_i2c3 {
status = "okay";
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
tpm@29 {
compatible = "atmel,at97sc3204t";
reg = <0x29>;
};
};
&blsp1_uart1 {
status = "okay";
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
};
&cryptobam {
status = "okay";
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
};
&gmac0 {
qcom,poll_required = <1>;
qcom,phy_mdio_addr = <4>;
vlan_tag = <2 0x20>;
};
&gmac1 {
qcom,poll_required = <1>;
qcom,phy_mdio_addr = <3>;
vlan_tag = <1 0x10>;
};
&wifi0 {
status = "okay";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC";
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0-or-later
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "EnGenius EMD1";
compatible = "engenius,emd1";
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_lan_bmp = <0x20>;
switch_wan_bmp = <0x00>;
};
edma@c080000 {
status = "okay";
qcom,num_gmac = <1>;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
led_power: power {
label = "white:power";
gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
};
wlan2g {
label = "red:wlan2g";
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tpt";
};
wlan5g {
label = "blue:wlan5g";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy1tpt";
};
mesh {
label = "orange:mesh";
gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
};
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio54", "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition0@0 {
label = "0:SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition1@40000 {
label = "0:MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition2@60000 {
label = "0:QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition3@c0000 {
label = "0:CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition4@d0000 {
label = "0:DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition5@e0000 {
label = "0:APPSBLENV";
reg = <0x000e0000 0x00010000>;
read-only;
};
partition6@f0000 {
label = "0:APPSBL";
reg = <0x000f0000 0x00080000>;
read-only;
};
partition7@170000 {
label = "0:ART";
reg = <0x00170000 0x00010000>;
read-only;
};
partition8@180000 {
label = "userconfig";
reg = <0x00180000 0x00080000>;
read-only;
};
partition9@200000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x200000 0x01e00000>;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&gmac0 {
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <1 0x20>;
};
&cryptobam {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "EnGenius-EMD1";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "EnGenius-EMD1";
};

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// SPDX-License-Identifier: GPL-2.0-or-later
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "EnGenius EMR3500";
compatible = "engenius,emr3500";
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2_hs_phy: hsphy@a8000 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
aliases {
led-boot = &power;
led-failsafe = &power;
led-running = &power;
led-upgrade = &power;
};
leds {
compatible = "gpio-leds";
power: white {
label = "white:power";
gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
};
blue {
label = "blue";
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
};
red {
label = "red";
gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
};
orange {
label = "orange";
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
};
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio54", "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
m25p80@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition@40000 {
label = "0:MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition@60000 {
label = "0:QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition@c0000 {
label = "0:CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition@d0000 {
label = "0:DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition@e0000 {
label = "0:APPSBLENV";
reg = <0x000e0000 0x00010000>;
read-only;
};
partition@f0000 {
label = "0:APPSBL";
reg = <0x000f0000 0x00080000>;
read-only;
};
partition@170000 {
label = "0:ART";
reg = <0x00170000 0x00010000>;
read-only;
};
partition@180000 {
label = "userconfig";
reg = <0x00180000 0x00080000>;
read-only;
};
partition@200000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x200000 0x1e00000>;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&gmac0 {
vlan_tag = <1 0x10>;
};
&gmac1 {
vlan_tag = <2 0x20>;
};
&usb2_hs_phy {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "EnGenius-EMR3500";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "EnGenius-EMR3500";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "EnGenius ENS620EXT";
compatible = "engenius,ens620ext";
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
aliases {
led-boot = &power;
led-failsafe = &power;
led-running = &power;
led-upgrade = &power;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
/*
* Disable the broken restart as a workaround for the buggy
* 3.0.0/3.0.1 U-boots that ship with the device.
* Note: The watchdog is now used to restart this device.
*/
restart@4ab000 {
status = "disabled";
};
};
buttons {
compatible = "gpio-keys";
wps {
label = "wps";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
leds {
compatible = "gpio-leds";
power: power {
label = "amber:power";
gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
};
lan1 {
label = "green:lan1";
gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
};
lan2 {
label = "green:lan2";
gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
};
wlan2g {
label = "green:wlan2g";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
};
wlan5g {
label = "green:wlan5g";
gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
};
};
};
&cryptobam {
status = "okay";
};
&blsp_dma {
status = "okay";
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
mux {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
mux_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp1_spi1 { /* BLSP1 QUP1 */
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
flash@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition@d0000 {
label = "DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition@e0000 {
label = "APPSBLENV"; /* uboot env*/
reg = <0x000e0000 0x00010000>;
read-only;
};
partition@f0000 {
label = "APPSBL"; /* uboot */
reg = <0x000f0000 0x00090000>;
read-only;
};
partition@180000 {
label = "ART";
reg = <0x00180000 0x00010000>;
read-only;
};
partition@190000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x00190000 0x14d0000>;
};
partition@1660000 {
label = "failsafe";
reg = <0x01660000 0x008F0000>;
read-only;
};
partition@1f50000 {
label = "u-boot-env";
reg = <0x01f50000 0x00010000>;
read-only;
};
partition@1f60000 {
label = "userconfig";
reg = <0x01f60000 0x000a0000>;
read-only;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "EnGenius-ENS620EXT";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "EnGenius-ENS620EXT";
};

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/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
* Copyright (c) 2018, David Bauer <mail@david-bauer.net>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "qcom-ipq4018-ex61x0v2.dtsi"
/ {
model = "Netgear EX6100v2";
compatible = "netgear,ex6100v2";
};
&wifi0 {
qcom,ath10k-calibration-variant = "Netgear-EX6100v2";
};
&wifi1 {
qcom,ath10k-calibration-variant = "Netgear-EX6100v2";
};

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/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
* Copyright (c) 2018, David Bauer <mail@david-bauer.net>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "qcom-ipq4018-ex61x0v2.dtsi"
/ {
model = "Netgear EX6150v2";
compatible = "netgear,ex6150v2";
};
&wifi0 {
qcom,ath10k-calibration-variant = "Netgear-EX6150v2";
};
&wifi1 {
qcom,ath10k-calibration-variant = "Netgear-EX6150v2";
};

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/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
* Copyright (c) 2018, David Bauer <mail@david-bauer.net>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Netgear EX61X0v2";
compatible = "netgear,ex61x0v2";
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
qcom,num_gmac = <1>;
};
};
aliases {
led-boot = &power_amber;
led-failsafe = &power_amber;
led-running = &power_green;
led-upgrade = &power_amber;
label-mac-device = &gmac0;
};
keys {
compatible = "gpio-keys";
wps {
label = "wps";
gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
led_spi {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
sck-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
num-chipselects = <0>;
led_gpio: led_gpio@0 {
compatible = "fairchild,74hc595";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
registers-number = <1>;
spi-max-frequency = <1000000>;
};
};
leds {
compatible = "gpio-leds";
power_amber: power_amber {
label = "amber:power";
gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
};
power_green: power_green {
label = "green:power";
gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
};
right {
label = "blue:right";
gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
};
left {
label = "blue:left";
gpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;
};
client_green {
label = "green:client";
gpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;
};
client_red {
label = "red:client";
gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
};
router_green {
label = "green:router";
gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
};
router_red {
label = "red:router";
gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
};
wps {
label = "green:wps";
gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
};
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
mx25l12805d@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <45000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition0@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition1@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition2@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition3@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition4@d0000 {
label = "DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition5@E0000 {
label = "APPSBLENV";
reg = <0x000e0000 0x00010000>;
read-only;
};
partition6@F0000 {
label = "APPSBL";
reg = <0x000f0000 0x00080000>;
read-only;
};
partition7@170000 {
label = "ART";
reg = <0x00170000 0x00010000>;
compatible = "nvmem-cells";
read-only;
#address-cells = <1>;
#size-cells = <1>;
precal_art_1000: precal@1000 {
reg = <0x1000 0x2f20>;
};
precal_art_5000: precal@5000 {
reg = <0x5000 0x2f20>;
};
};
partition8@180000 {
label = "config";
reg = <0x00180000 0x00010000>;
read-only;
};
partition9@190000 {
label = "pot";
reg = <0x00190000 0x00010000>;
read-only;
};
partition10@1a0000 {
compatible = "nvmem-cells";
label = "dnidata";
reg = <0x001a0000 0x00010000>;
read-only;
#address-cells = <1>;
#size-cells = <1>;
macaddr_dnidata_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_dnidata_c: macaddr@c {
reg = <0xc 0x6>;
};
};
partition11@1b0000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x001b0000 0x00e10000>;
};
partition12@fc0000 {
label = "language";
reg = <0x00fc0000 0x00040000>;
read-only;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&blsp_dma {
status = "okay";
};
&cryptobam {
status = "okay";
};
&wifi0 {
status = "okay";
nvmem-cell-names = "pre-calibration", "mac-address";
nvmem-cells = <&precal_art_1000>, <&macaddr_dnidata_0>;
};
&wifi1 {
status = "okay";
nvmem-cell-names = "pre-calibration", "mac-address";
nvmem-cells = <&precal_art_5000>, <&macaddr_dnidata_c>;
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "AVM FRITZ!Box 4040";
compatible = "avm,fritzbox-4040";
aliases {
led-boot = &power;
led-failsafe = &flash;
led-running = &power;
led-upgrade = &flash;
label-mac-device = &gmac0;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
};
usb3@8af8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
wlan {
label = "wlan";
gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
};
wps {
label = "wps";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
switch-leds {
compatible = "gpio-leds";
wlan {
label = "green:wlan";
gpios = <&ethphy0 0 GPIO_ACTIVE_HIGH>;
};
panic: info_red {
label = "red:info";
gpios = <&ethphy0 1 GPIO_ACTIVE_HIGH>;
panic-indicator;
};
wan {
label = "green:wan";
gpios = <&ethphy1 0 GPIO_ACTIVE_HIGH>;
};
power: power {
label = "green:power";
gpios = <&ethphy2 1 GPIO_ACTIVE_HIGH>;
};
lan {
label = "green:lan";
gpios = <&ethphy3 0 GPIO_ACTIVE_HIGH>;
};
flash: info_amber {
label = "amber:info";
gpios = <&ethphy3 1 GPIO_ACTIVE_HIGH>;
};
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
mux {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
mux_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&cryptobam {
status = "okay";
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 { /* BLSP1 QUP1 */
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
status = "okay";
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition0@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition1@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition2@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition3@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition4@d0000 {
label = "DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition5@e0000 {
label = "APPSBLENV"; /* uboot env - empty */
reg = <0x000e0000 0x00010000>;
read-only;
};
partition6@f0000 {
label = "urlader"; /* APPSBL */
reg = <0x000f0000 0x0002dc000>;
read-only;
};
partition7@11dc00 {
/* make a backup of this partition! */
label = "urlader_config";
reg = <0x0011dc00 0x00002400>;
read-only;
};
partition8@120000 {
label = "tffs1";
reg = <0x00120000 0x00080000>;
read-only;
};
partition9@1a0000 {
label = "tffs2";
reg = <0x001a0000 0x00080000>;
read-only;
};
partition10@220000 {
label = "uboot";
reg = <0x00220000 0x00080000>;
read-only;
};
partition11@2A0000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x002a0000 0x01c60000>;
};
partition12@1f00000 {
label = "jffs2";
reg = <0x01f00000 0x00100000>;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&ethphy0 {
gpio-controller;
#gpio-cells = <2>;
};
&ethphy1 {
gpio-controller;
#gpio-cells = <2>;
enable-usb-power {
gpio-hog;
line-name = "enable USB3 power";
gpios = <1 GPIO_ACTIVE_HIGH>;
output-high;
};
};
&ethphy2 {
gpio-controller;
#gpio-cells = <2>;
};
&ethphy3 {
gpio-controller;
#gpio-cells = <2>;
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "AVM-FRITZBox-4040";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "AVM-FRITZBox-4040";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "GL.iNet GL-AP1300";
compatible = "glinet,gl-ap1300";
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
chosen {
bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
};
usb3@8af8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_lan_bmp = <0x18>;
switch_wan_bmp = <0x20>;
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
led_power: power {
label = "green:power";
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
wan {
label = "green:wan";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
};
};
};
&blsp_dma {
status = "okay";
};
&cryptobam {
status = "okay";
};
&blsp1_spi1 {
status = "okay";
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 5 GPIO_ACTIVE_HIGH>;
flash@0 {
status = "okay";
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition@d0000 {
label = "DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition@e0000 {
label = "APPSBLENV"; /* uboot env*/
reg = <0x000e0000 0x00010000>;
};
partition@f0000 {
label = "APPSBL"; /* uboot */
reg = <0x000f0000 0x00080000>;
read-only;
};
partition@170000 {
label = "ART";
reg = <0x00170000 0x00010000>;
read-only;
};
};
};
spi-nand@1 {
status = "okay";
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "ubi";
reg = <0x00000000 0x08000000>;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi0_pins: spi0_pinmux {
mux_spi {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
mux_cs {
function = "gpio";
pins = "gpio54", "gpio5";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&usb2_hs_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb3_ss_phy {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "GL-AP1300";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "GL-AP1300";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2020, Robert Marko <robimarko@gmail.com> */
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "MikroTik hAP ac2";
compatible = "mikrotik,hap-ac2";
memory {
device_type = "memory";
reg = <0x80000000 0x08000000>;
};
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
led-boot = &led_user;
led-failsafe = &led_user;
led-running = &led_user;
led-upgrade = &led_user;
};
soc {
rng@22000 {
status = "okay";
};
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb3@8af8800 {
status = "okay";
dwc3@8a00000 {
phys = <&usb3_hs_phy>;
phy-names = "usb2-phy";
};
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
mode {
label = "mode";
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
};
};
leds {
compatible = "gpio-leds";
power {
label = "green:power";
gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
default-state = "keep";
panic-indicator;
};
led_user: user {
label = "green:user";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
};
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <2>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
enable-usb-power {
gpio-hog;
gpios = <2 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "enable USB power";
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
status = "okay";
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
flash@0 {
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <40000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Qualcomm";
reg = <0x0 0x80000>;
read-only;
};
partition@80000 {
compatible = "mikrotik,routerboot-partitions";
#address-cells = <1>;
#size-cells = <1>;
label = "RouterBoot";
reg = <0x80000 0x80000>;
read-only;
hard_config {
read-only;
size = <0x2000>;
};
dtb_config {
read-only;
};
soft_config {
};
};
partition@100000 {
compatible = "mikrotik,minor";
label = "firmware";
reg = <0x100000 0xf00000>;
};
};
};
};
&blsp1_uart1 {
status = "okay";
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
};
&cryptobam {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&mdio {
status = "okay";
};
&ethphy0 {
qcom,single-led-1000;
qcom,single-led-100;
qcom,single-led-10;
};
&ethphy1 {
qcom,single-led-1000;
qcom,single-led-100;
qcom,single-led-10;
};
&ethphy2 {
qcom,single-led-1000;
qcom,single-led-100;
qcom,single-led-10;
};
&ethphy3 {
qcom,single-led-1000;
qcom,single-led-100;
qcom,single-led-10;
};
&ethphy4 {
qcom,single-led-1000;
qcom,single-led-100;
qcom,single-led-10;
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "MikroTik-hAP-ac2";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "MikroTik-hAP-ac2";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
// Copyright (c) 2018, Robert Marko <robimarko@gmail.com>
#include "qcom-ipq4018-jalapeno.dtsi"
/ {
model = "8devices Jalapeno";
compatible = "8dev,jalapeno";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
// Copyright (c) 2018, Robert Marko <robimarko@gmail.com>
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
};
ess-psgmii@98000 {
status = "okay";
};
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
status = "okay";
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2: usb2@60f8800 {
status = "okay";
};
usb3: usb3@8af8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_lan_bmp = <0x10>; /* lan port bitmap */
};
edma@c080000 {
status = "okay";
};
};
};
&tlmm {
mdio_pins: mdio_pinmux {
pinmux_1 {
pins = "gpio53";
function = "mdio";
};
pinmux_2 {
pins = "gpio52";
function = "mdc";
};
pinconf {
pins = "gpio52", "gpio53";
bias-pull-up;
};
};
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <2>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio54", "gpio59";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
status = "okay";
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
flash@0 {
status = "okay";
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition@d0000 {
label = "DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition@e0000 {
label = "APPSBLENV"; /* uboot env*/
reg = <0x000e0000 0x00010000>;
read-only;
};
partition@f0000 {
label = "APPSBL"; /* uboot */
reg = <0x000f0000 0x00080000>;
read-only;
};
partition@170000 {
label = "ART";
reg = <0x00170000 0x00010000>;
read-only;
};
};
};
spi-nand@1 {
status = "okay";
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "ubi";
reg = <0x00000000 0x08000000>;
};
};
};
};
&blsp1_uart1 {
status = "okay";
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
};
&cryptobam {
status = "okay";
};
&gmac0 {
qcom,poll_required = <1>;
qcom,poll_required_dynamic = <1>;
qcom,phy_mdio_addr = <3>;
vlan_tag = <1 0x10>;
};
&gmac1 {
qcom,poll_required = <1>;
qcom,poll_required_dynamic = <1>;
qcom,phy_mdio_addr = <4>;
vlan_tag = <2 0x20>;
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "8devices-Jalapeno";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "8devices-Jalapeno";
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "devolo Magic 2 WiFi next";
compatible = "devolo,magic-2-wifi-next";
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
reset-delay-us = <2000>;
/delete-node/ ethernet-phy@0;
/delete-node/ ethernet-phy@1;
};
ess-psgmii@98000 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_lan_bmp = <0x3e>;
switch_wan_bmp = <0x0>;
};
edma@c080000 {
status = "okay";
qcom,num_gmac = <3>;
gmac0 {
qcom,phy_mdio_addr = <3>;
qcom,poll_required = <1>;
/delete-property/ qcom,forced_speed;
/delete-property/ qcom,forced_duplex;
vlan_tag = <1 0x10>;
};
gmac1 {
qcom,phy_mdio_addr = <2>;
qcom,poll_required = <1>;
/delete-property/ qcom,forced_speed;
/delete-property/ qcom,forced_duplex;
vlan_tag = <1 0x08>;
};
gmac2 {
local-mac-address = [00 00 00 00 00 00];
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <1>;
/delete-property/ qcom,forced_speed;
/delete-property/ qcom,forced_duplex;
vlan_tag = <1 0x20>;
};
};
gpio_export {
compatible = "gpio-export";
#size-cells = <0>;
plc {
gpio-export,name = "plc-enable";
gpio-export,output = <1>;
gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
};
};
};
keys {
compatible = "gpio-keys";
wlan {
label = "WLAN";
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
reset {
label = "Reset";
gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
status_dlan {
label = "white:dlan";
gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
default-state = "keep";
};
status_wlan {
label = "white:wlan";
gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
default-state = "keep";
};
error_dlan {
label = "red:dlan";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
};
};
&tlmm {
spi_0_pins: spi_0_pinmux {
mux {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
mux_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio53";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio52";
function = "mdc";
bias-pull-up;
};
};
serial_pins: serial_pinmux {
mux {
pins = "gpio61", "gpio60";
function = "blsp_uart0";
bias-disable;
};
};
button_pins: button_pinmux {
mux {
function = "gpio";
pins = "gpio0", "gpio5";
bias-disable;
input;
};
};
};
&cryptobam {
status = "okay";
};
&blsp_dma {
status = "okay";
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "devolo,magic-2-wifi-next";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "devolo,magic-2-wifi-next";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
linux,modalias = "n25q128a11";
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition@d0000 {
label = "DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition@e0000 {
label = "APPSBLENV"; /* uboot env*/
reg = <0x000e0000 0x00010000>;
};
partition@f0000 {
label = "APPSBL"; /* uboot */
reg = <0x000f0000 0x00080000>;
read-only;
};
partition@170000 {
label = "ART";
reg = <0x00170000 0x00010000>;
read-only;
};
firmware@180000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x00180000 0x01a80000>;
};
};
};
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2019, CRISIS INNOVATION LAB d.o.o.
* Author: Robert Marko <robert@meshpoint.me>
*/
#include "qcom-ipq4018-jalapeno.dtsi"
/ {
model = "Crisis Innovation Lab MeshPoint.One";
compatible = "cilab,meshpoint-one";
aliases {
led-boot = &led_status;
led-failsafe = &led_status;
led-running = &led_status;
led-upgrade = &led_status;
};
soc {
i2c-gpio {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
compatible = "i2c-gpio";
gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* sda */
&tlmm 4 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* scl */
>;
bme280@76 {
status = "okay";
compatible = "bosch,bme280";
reg = <0x76>;
};
pcf2129@51 {
status = "okay";
compatible = "nxp,pcf2129";
reg = <0x51>;
};
ina230@40 {
status = "okay";
compatible = "ti,ina230";
reg = <0x40>;
shunt-resistor = <2000>;
};
ina230@44 {
status = "okay";
compatible = "ti,ina230";
reg = <0x44>;
shunt-resistor = <2000>;
};
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART >;
};
};
leds {
compatible = "gpio-leds";
led_status: status {
label = "blue:status";
gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
};
};
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "ZyXEL NBG6617";
compatible = "zyxel,nbg6617";
chosen {
/*
* the vendor u-boot adds root and mtdparts cmdline parameters
* which we don't want... but we have to overwrite them or else
* the kernel will take them at face value.
*/
bootargs-append = " mtdparts= root=31:13";
};
aliases {
led-boot = &power;
led-failsafe = &power;
led-running = &power;
led-upgrade = &power;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
dwc3@6000000 {
#address-cells = <1>;
#size-cells = <0>;
usb2_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
};
};
usb3@8af8800 {
status = "okay";
dwc3@8a00000 {
#address-cells = <1>;
#size-cells = <0>;
usb3_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
usb3_port2: port@2 {
reg = <2>;
#trigger-source-cells = <0>;
};
};
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
wlan {
label = "wlan";
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_RFKILL>;
linux,input-type = <EV_SW>;
};
wps {
label = "wps";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
reset {
label = "reset";
gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
power: power {
label = "green:power";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
};
usb {
label = "green:usb";
gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
trigger-sources = <&usb2_port1>, <&usb3_port1>, <&usb3_port2>;
linux,default-trigger = "usbport";
};
wlan2g {
label = "green:wlan2g";
gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
};
wlan5g {
label = "green:wlan5g";
gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
};
wps {
label = "green:wps";
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
};
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
mux {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
mux_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-low;
};
};
led_pins: led_pinmux {
mux {
pins = "gpio0", "gpio1", "gpio3", "gpio5", "gpio58";
drive-strength = <0x8>;
bias-disable;
output-low;
};
};
};
&blsp1_spi1 { /* BLSP1 QUP1 */
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
status = "okay";
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition0@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition1@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition2@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition3@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition4@d0000 {
label = "DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition5@e0000 {
label = "APPSBL"; /* u-boot */
reg = <0x000e0000 0x00080000>;
/* U-Boot Standalone App "zloader" is located at 0x64000 */
read-only;
};
partition6@160000 {
label = "APPSBLENV"; /* u-boot env */
reg = <0x00160000 0x00010000>;
};
partition7@170000 {
/* make a backup of this partition! */
label = "ART";
reg = <0x00170000 0x00010000>;
read-only;
};
partition8@180000 {
label = "kernel";
reg = <0x00180000 0x00400000>;
};
partition9@580000 {
label = "dualflag";
reg = <0x00580000 0x00010000>;
read-only;
};
partition10@590000 {
label = "header";
reg = <0x00590000 0x00010000>;
};
partition11@5a0000 {
label = "romd";
reg = <0x005a0000 0x00100000>;
read-only;
};
partition12@6a0000 {
label = "not_root_data";
/*
* for some strange reason, someone at ZyXEL
* had the "great" idea to put the rootfs_data
* in front of rootfs... Don't do that!
* As a result this one, full MebiByte remains
* unused.
*/
reg = <0x006a0000 0x00100000>;
};
partition13@7a0000 {
label = "rootfs";
reg = <0x007a0000 0x01860000>;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&blsp_dma {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "ZyXEL-NBG6617";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "ZyXEL-NBG6617";
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2017-2020, Sven Eckelmann <sven@narfation.org>
* Copyright (c) 2018, Marek Lindner <marek.lindner@kaiwoo.ai>
*/
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Plasma Cloud PA1200";
compatible = "plasmacloud,pa1200";
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2: usb2@60f8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
aliases {
led-boot = &led_status_purple;
led-failsafe = &led_status_yellow;
led-running = &led_status_cyan;
led-upgrade = &led_status_yellow;
};
leds {
compatible = "gpio-leds";
led_status_cyan: status_cyan {
label = "cyan:status";
gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
};
led_status_purple: status_purple {
label = "purple:status";
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
};
led_status_yellow: status_yellow {
label = "yellow:status";
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
};
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
/* partitions are passed via bootloader */
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&gmac0 {
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <2 0x20>;
};
&gmac1 {
qcom,phy_mdio_addr = <3>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <1 0x10>;
};
&usb2_hs_phy {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "PlasmaCloud-PA1200";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "PlasmaCloud-PA1200";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "ASUS RT-AC58U";
compatible = "asus,rt-ac58u";
memory {
device_type = "memory";
reg = <0x80000000 0x8000000>;
};
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
chosen {
bootargs-append = " ubi.mtd=UBI_DEV";
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb3@8af8800 {
status = "okay";
dwc3@8a00000 {
#address-cells = <1>;
#size-cells = <0>;
usb3_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
usb3_port2: port@2 {
reg = <2>;
#trigger-source-cells = <0>;
};
};
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
wps {
label = "wps";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
leds {
compatible = "gpio-leds";
led_power: status {
label = "blue:status";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
};
wan {
label = "blue:wan";
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
};
wlan2G {
label = "blue:wlan2G";
gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tpt";
};
wlan5G {
label = "blue:wlan5G";
gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy1tpt";
};
usb {
label = "blue:usb";
gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
trigger-sources = <&usb3_port1>, <&usb3_port2>;
linux,default-trigger = "usbport";
};
lan {
label = "blue:lan";
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
};
};
};
&cryptobam {
status = "okay";
};
&blsp_dma {
status = "okay";
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
mux {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
mux_cs {
function = "gpio";
pins = "gpio54", "gpio59";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp1_spi1 { /* BLSP1 QUP1 */
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
<&tlmm 59 GPIO_ACTIVE_HIGH>;
flash@0 {
/*
* U-boot looks for "n25q128a11" node,
* if we don't have it, it will spit out the following warning:
* "ipq: fdt fixup unable to find compatible node".
*/
compatible = "jedec,spi-nor";
reg = <0>;
linux,modalias = "m25p80", "mx25l1606e", "n25q128a11";
spi-max-frequency = <30000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition@d0000 {
label = "DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition@e0000 {
label = "APPSBLENV"; /* uboot env*/
reg = <0x000e0000 0x00010000>;
read-only;
};
partition@f0000 {
label = "APPSBL"; /* uboot */
reg = <0x000f0000 0x00080000>;
read-only;
};
partition@170000 {
label = "ART";
reg = <0x00170000 0x00010000>;
read-only;
};
/* 0x00180000 - 0x00200000 unused */
};
};
spi-nand@1 {
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <30000000>;
/*
* U-boot looks for "spinand,mt29f" node,
* if we don't have it, it will spit out the following warning:
* "ipq: fdt fixup unable to find compatible node".
*/
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
/*
* TODO: change to label = "ubi" once we drop 4.14.
* also drop the bootargs-append and all the
* userspace CI_UBIPART="UBI_DEV" remains.
*/
label = "UBI_DEV";
reg = <0x00000000 0x08000000>;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "RT-AC58U";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "RT-AC58U";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019-ap.dk01.1.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
aliases {
label-mac-device = &gmac0;
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
soc {
pinctrl@1000000 {
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio53";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio52";
function = "mdc";
bias-pull-up;
};
};
i2c_0_pins: i2c_0_pinmux {
mux {
pins = "gpio58", "gpio59";
function = "blsp_i2c0";
bias-disable;
};
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 4 1>;
linux,code = <KEY_RESTART>;
};
};
gpio_export {
compatible = "gpio-export";
#size-cells = <0>;
gpio_out {
gpio-export,name = "gpio_out";
gpio-export,output = <0>;
gpio-export,direction_may_change = <0>;
gpios = <&stm32_io 23 GPIO_ACTIVE_HIGH>;
};
gpio_in {
gpio-export,name = "gpio_in";
gpio-export,input = <0>;
gpio-export,direction_may_change = <0>;
gpios = <&stm32_io 24 GPIO_ACTIVE_LOW>;
};
};
};
};
&blsp1_i2c3 {
status = "okay";
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
clock-frequency = <400000>;
stm32_io: stm32@74 {
compatible = "tlt,stm32v1";
#gpio-cells = <2>;
#interrupt-cells = <2>;
gpio-controller;
interrupt-controller;
interrupt-parent = <&tlmm>;
interrupts = <5 2>;
reg = <0x74>;
};
};
&blsp1_spi1 {
cs-gpios = <&tlmm 54 0>, <&tlmm 63 0>;
num-cs = <2>;
xt25f128b@0 {
/*
* Factory U-boot looks in 0:BOOTCONFIG partition for active
* partitions settings and mangles the partition config so
* 0:QSEE/0:QSEE_1, 0:CDT/0:CDT_1 and 0:APPSBL/0:APPSBL_1 pairs
* can be swaped. It isn't a problem but we never can be sure where
* OFW put factory images. "n25q128a11" is required for proper nor
* recognition in u-boot.
*/
compatible = "jedec,spi-nor", "n25q128a11";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:SBL1";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "0:MIBIB";
reg = <0x40000 0x20000>;
read-only;
};
partition@60000 {
label = "0:BOOTCONFIG";
reg = <0x60000 0x20000>;
read-only;
};
partition@80000 {
label = "0:BOOTCONFIG1";
reg = <0x80000 0x20000>;
read-only;
};
partition@a0000 {
label = "0:QSEE";
reg = <0xa0000 0x60000>;
read-only;
};
partition@100000 {
label = "0:QSEE_1";
reg = <0x100000 0x60000>;
read-only;
};
partition@160000 {
label = "0:CDT";
reg = <0x160000 0x10000>;
read-only;
};
partition@170000 {
label = "0:CDT_1";
reg = <0x170000 0x10000>;
read-only;
};
partition@180000 {
label = "0:DDRPARAMS";
reg = <0x180000 0x10000>;
read-only;
};
partition@190000 {
label = "0:APPSBLENV";
reg = <0x190000 0x10000>;
read-only;
};
partition@1a0000 {
label = "0:APPSBL";
reg = <0x1a0000 0xa0000>;
read-only;
};
partition@240000 {
label = "0:APPSBL_1";
reg = <0x240000 0xa0000>;
read-only;
};
partition@2e0000 {
label = "0:ART";
reg = <0x2e0000 0x10000>;
read-only;
};
config: partition@2f0000 {
label = "0:CONFIG";
reg = <0x2f0000 0x10000>;
read-only;
};
partition@300000 {
label = "0:CONFIG_RW";
reg = <0x300000 0x10000>;
read-only;
};
partition@310000 {
label = "0:EVENTSLOG";
reg = <0x310000 0x90000>;
read-only;
};
};
};
xt26g02a@1 {
/*
* Factory U-boot looks in 0:BOOTCONFIG partition for active
* partitions settings and mangles the partition config so
* rootfs/rootfs_1 pairs can be swaped.
* It isn't a problem but we never can be sure where OFW put
* factory images. "spinand,mt29f" value is required for proper
* nand recognition in u-boot.
*/
compatible = "spi-nand", "spinand,mt29f";
#address-cells = <1>;
#size-cells = <1>;
reg = <1>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "rootfs_1";
reg = <0x00000000 0x08000000>;
};
partition@8000000 {
label = "rootfs";
reg = <0x08000000 0x08000000>;
};
};
};
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
phy-reset-gpio = <&tlmm 62 0>;
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4018-rutx.dtsi"
/ {
model = "Teltonika RUTX10";
compatible = "teltonika,rutx10";
soc {
leds {
compatible = "gpio-leds";
wifi2g {
label = "green:wifi2g";
gpios = <&stm32_io 19 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tpt";
};
wifi5g {
label = "green:wifi5g";
gpios = <&stm32_io 18 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy1tpt";
};
};
};
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2020, Robert Marko <robimarko@gmail.com> */
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "MikroTik SXTsq 5 ac (RBSXTsqG-5acD)";
compatible = "mikrotik,sxtsq-5-ac";
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
led-boot = &led_user;
led-failsafe = &led_user;
led-running = &led_user;
led-upgrade = &led_user;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
edma@c080000 {
status = "okay";
phy-mode = "rgmii";
qcom,num_gmac = <1>;
qcom,single-phy;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
power {
label = "blue:power";
gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
default-state = "keep";
panic-indicator;
};
led_user: user {
label = "green:user";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
};
rssilow {
label = "green:rssilow";
gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
};
rssimediumlow {
label = "green:rssimediumlow";
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
};
rssimedium {
label = "green:rssimedium";
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
};
rssimediumhigh {
label = "green:rssimediumhigh";
gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
};
rssihigh {
label = "green:rssihigh";
gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
};
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <2>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
status = "okay";
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
flash@0 {
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <40000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Qualcomm";
reg = <0x0 0x80000>;
read-only;
};
partition@80000 {
compatible = "mikrotik,routerboot-partitions";
#address-cells = <1>;
#size-cells = <1>;
label = "RouterBoot";
reg = <0x80000 0x80000>;
read-only;
hard_config {
read-only;
};
dtb_config {
read-only;
};
soft_config {
};
};
partition@100000 {
compatible = "mikrotik,minor";
label = "firmware";
reg = <0x100000 0xf00000>;
};
};
};
};
&blsp1_uart1 {
status = "okay";
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
};
&cryptobam {
status = "okay";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "MikroTik-SXTsq-5-ac";
};
&gmac0 {
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <1 0x20>;
};
&mdio {
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2020, Robert Marko <robimarko@gmail.com> */
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Netgear WAC510";
compatible = "netgear,wac510";
aliases {
led-boot = &led_power_amber;
led-failsafe = &led_power_amber;
led-running = &led_power_green;
led-upgrade = &led_power_amber;
label-mac-device = &gmac0;
};
chosen {
bootargs-append = " root=/dev/ubiblock0_1";
};
soc {
rng@22000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
status = "okay";
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2: usb2@60f8800 {
status = "okay";
};
usb3: usb3@8af8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
led_spi {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
sck-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
num-chipselects = <0>;
ssr: ssr@0 {
compatible = "fairchild,74hc595";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
registers-number = <1>;
spi-max-frequency = <1000000>;
};
};
leds {
compatible = "gpio-leds";
led_power_amber: power_amber {
label = "amber:power";
gpios = <&ssr 6 GPIO_ACTIVE_LOW>;
panic-indicator;
};
led_power_green: power_green {
label = "green:power";
gpios = <&ssr 5 GPIO_ACTIVE_LOW>;
};
wlan2g_blue {
label = "blue:wlan2g";
gpios = <&ssr 4 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
wlan2g_green {
label = "green:wlan2g";
gpios = <&ssr 3 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0radio";
};
wlan5g_blue {
label = "blue:wlan5g";
gpios = <&ssr 2 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
wlan5g_green {
label = "green:wlan5g";
gpios = <&ssr 1 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1radio";
};
act_green {
label = "green:act";
gpios = <&ssr 0 GPIO_ACTIVE_LOW>;
};
};
};
&qpic_bam {
status = "okay";
};
&tlmm {
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio53";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio52";
function = "mdc";
bias-pull-up;
};
};
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pinmux_cs {
function = "gpio";
pins = "gpio54", "gpio59";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
status = "okay";
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
<&tlmm 59 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition@40000 {
label = "0:MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition@60000 {
label = "0:QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition@c0000 {
label = "0:CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition@d0000 {
label = "0:DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition@e0000 {
label = "0:APPSBLENV";
reg = <0x000e0000 0x00010000>;
};
partition@f0000 {
label = "0:APPSBL";
reg = <0x000f0000 0x000f0000>;
read-only;
};
partition@1e0000 {
label = "0:MANUDATA";
reg = <0x001e0000 0x00010000>;
read-only;
};
partition@1f0000 {
label = "0:ART";
reg = <0x001f0000 0x00010000>;
read-only;
};
};
};
nand@1 {
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <48000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "rootfs";
reg = <0x00000000 0x03800000>;
};
partition@3800000 {
label = "rootfs_1";
reg = <0x03800000 0x03800000>;
};
partition@7000000 {
label = "var_config";
reg = <0x07000000 0x00f00000>;
read-only;
};
partition@7f00000 {
label = "Oops_log";
reg = <0x07f00000 0x000c0000>;
read-only;
};
};
};
};
&blsp1_uart1 {
status = "okay";
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
};
&cryptobam {
status = "okay";
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>;
reset-delay-us = <2000>;
};
&gmac0 {
qcom,forced_duplex = <1>;
qcom,forced_speed = <1000>;
qcom,phy_mdio_addr = <3>;
qcom,poll_required = <1>;
vlan_tag = <1 0x10>;
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "Netgear-WAC510";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "Netgear-WAC510";
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};

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/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
* Copyright (c) 2018, David Bauer <mail@david-bauer.net>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "ZyXEL WRE6606";
compatible = "zyxel,wre6606";
aliases {
led-boot = &power;
led-failsafe = &power;
led-running = &power;
led-upgrade = &power;
};
chosen {
bootargs-append = " mtdparts=";
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
qcom,num_gmac = <1>;
};
};
leds {
compatible = "gpio-leds";
wps {
label = "green:wps";
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
};
wlan5g_green {
label = "green:wlan5g";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
};
power: power {
label = "green:power";
gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
};
wlan5g_red {
label = "red:wlan5g";
gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
};
wlan2g_red {
label = "red:wlan2g";
gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
};
wlan2g_green {
label = "green:wlan2g";
gpios = <&tlmm 59 GPIO_ACTIVE_HIGH>;
};
};
keys {
compatible = "gpio-keys";
wps {
label = "wps";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
mx25l12805d@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition0@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition1@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition2@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition3@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition4@d0000 {
label = "DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition5@E0000 {
label = "APPSBLENV";
reg = <0x000e0000 0x00010000>;
read-only;
};
partition6@F0000 {
label = "APPSBL";
reg = <0x000f0000 0x00080000>;
read-only;
};
partition7@170000 {
label = "ART";
reg = <0x00170000 0x00010000>;
read-only;
};
partition8@180000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x00180000 0x00ce0000>;
};
partition9@e60000 {
label = "manufacture";
reg = <0x00e60000 0x00050000>;
read-only;
};
partition10@eb0000 {
label = "storage";
reg = <0x00eb0000 0x00150000>;
read-only;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "ZyXEL-WRE6606";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "ZyXEL-WRE6606";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Luma Home WRTQ-329ACN";
compatible = "luma,wrtq-329acn";
i2c-gpio {
compatible = "i2c-gpio";
sda-gpios = <&tlmm 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
#address-cells = <1>;
#size-cells = <0>;
/* No driver exists */
led_ring@48 {
compatible = "ti,msp430";
reg = <0x48>;
};
eeprom@50 {
compatible = "atmel,24c16";
reg = <0x50>;
pagesize = <16>;
read-only;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
/delete-node/ ethernet-phy@0;
/delete-node/ ethernet-phy@1;
/delete-node/ ethernet-phy@3;
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
};
usb3@8af8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_lan_bmp = <0x1e>;
switch_wan_bmp = <0x20>;
};
edma@c080000 {
status = "okay";
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
<&tlmm 59 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&spi0_pins>;
pinctrl-names = "default";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:SBL1";
reg = <0x000000 0x040000>;
read-only;
};
partition@40000 {
label = "0:MIBIB";
reg = <0x040000 0x020000>;
read-only;
};
partition@60000 {
label = "0:QSEE";
reg = <0x060000 0x060000>;
read-only;
};
partition@c0000 {
label = "0:CDT";
reg = <0x0c0000 0x010000>;
read-only;
};
partition@d0000 {
label = "0:DDRPARAMS";
reg = <0x0d0000 0x010000>;
read-only;
};
partition@e0000 {
label = "0:APPSBLENV";
reg = <0x0e0000 0x010000>;
};
partition@f0000 {
label = "0:APPSBL";
reg = <0x0f0000 0x080000>;
read-only;
};
partition@170000 {
label = "0:ART";
reg = <0x170000 0x010000>;
read-only;
};
};
};
flash@1 {
status = "okay";
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "ubi";
reg = <0x0000000 0x8000000>;
};
};
};
};
&blsp1_uart1 {
status = "okay";
pinctrl-0 = <&serial0_pins>;
pinctrl-names = "default";
};
&cryptobam {
status = "okay";
};
&gmac0 {
qcom,phy_mdio_addr = <2>;
qcom,poll_required = <1>;
};
&gmac1 {
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <1>;
};
&tlmm {
serial0_pins: serial0_pinmux {
mux {
function = "blsp_uart0";
pins = "gpio60", "gpio61";
bias-disable;
};
};
spi0_pins: spi0_pinmux {
mux {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
bias-disable;
drive-strength = <12>;
};
mux_cs {
function = "gpio";
pins = "gpio54", "gpio59";
bias-disable;
drive-strength = <2>;
output-high;
};
};
};
&usb2_hs_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb3_ss_phy {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "Luma-WRTQ-329ACN";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "Luma-WRTQ-329ACN";
};

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// SPDX-License-Identifier: ISC
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
* Copyright (c) 2017-2018, Sven Eckelmann <sven.eckelmann@openmesh.com>
*/
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "OpenMesh A62";
compatible = "openmesh,a62";
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2: usb2@60f8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
switch_lan_bmp = <0x10>;
switch_wan_bmp = <0x20>;
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART >;
};
};
aliases {
led-boot = &led_status_green;
led-failsafe = &led_status_green;
led-running = &led_status_green;
led-upgrade = &led_status_green;
};
leds {
compatible = "gpio-leds";
status_red {
label = "red:status";
gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
};
led_status_green: status_green {
label = "green:status";
gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
};
status_blue {
label = "blue:status";
gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
};
};
watchdog {
compatible = "linux,wdt-gpio";
gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
hw_algo = "toggle";
/* hw_margin_ms is actually 300s but driver limits it to 60s */
hw_margin_ms = <60000>;
always-running;
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio12";
drive-strength = <2>;
bias-disable;
output-high;
};
};
enable-usb-power {
gpio-hog;
gpios = <58 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "enable USB2 power";
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
/* partitions are passed via bootloader */
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&gmac0 {
qcom,phy_mdio_addr = <3>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <1 0x10>;
};
&usb2_hs_phy {
status = "okay";
};
&pcie0 {
status = "okay";
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi2: wifi@1,0 {
compatible = "qcom,ath10k";
status = "okay";
reg = <0x00010000 0 0 0 0>;
qcom,ath10k-calibration-variant = "OM-A62";
ieee80211-freq-limit = <5170000 5350000>;
};
};
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "OM-A62";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "OM-A62";
ieee80211-freq-limit = <5470000 5875000>;
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "MobiPromo CM520-79F";
compatible = "mobipromo,cm520-79f";
aliases {
led-boot = &led_sys;
led-failsafe = &led_sys;
led-running = &led_sys;
led-upgrade = &led_sys;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
reset-delay-us = <1000>;
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
dwc3@6000000 {
#address-cells = <1>;
#size-cells = <0>;
usb2_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
};
};
usb3@8af8800 {
status = "okay";
dwc3@8a00000 {
#address-cells = <1>;
#size-cells = <0>;
usb3_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
usb3_port2: port@2 {
reg = <2>;
#trigger-source-cells = <0>;
};
};
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
led_spi {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
sck-gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>;
num-chipselects = <0>;
led_gpio: led_gpio@0 {
compatible = "fairchild,74hc595";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
registers-number = <1>;
spi-max-frequency = <1000000>;
};
};
leds {
compatible = "gpio-leds";
usb {
label = "blue:usb";
gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "usbport";
trigger-sources = <&usb3_port1>, <&usb3_port2>, <&usb2_port1>;
};
led_sys: can {
label = "blue:can";
gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
};
wan {
label = "blue:wan";
gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
};
lan1 {
label = "blue:lan1";
gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
};
lan2 {
label = "blue:lan2";
gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
};
wlan2g {
label = "blue:wlan2g";
gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
wlan5g {
label = "blue:wlan5g";
gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_uart1 {
status = "okay";
};
&blsp1_uart2 {
status = "okay";
};
&cryptobam {
status = "okay";
};
&gmac0 {
nvmem-cells = <&macaddr_art_1006>;
nvmem-cell-names = "mac-address";
};
&gmac1 {
nvmem-cells = <&macaddr_art_5006>;
nvmem-cell-names = "mac-address";
};
&nand {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x0 0x100000>;
read-only;
};
partition@100000 {
label = "MIBIB";
reg = <0x100000 0x100000>;
read-only;
};
partition@200000 {
label = "BOOTCONFIG";
reg = <0x200000 0x100000>;
};
partition@300000 {
label = "QSEE";
reg = <0x300000 0x100000>;
read-only;
};
partition@400000 {
label = "QSEE_1";
reg = <0x400000 0x100000>;
read-only;
};
partition@500000 {
label = "CDT";
reg = <0x500000 0x80000>;
read-only;
};
partition@580000 {
label = "CDT_1";
reg = <0x580000 0x80000>;
read-only;
};
partition@600000 {
label = "BOOTCONFIG1";
reg = <0x600000 0x80000>;
};
partition@680000 {
label = "APPSBLENV";
reg = <0x680000 0x80000>;
};
partition@700000 {
label = "APPSBL";
reg = <0x700000 0x200000>;
read-only;
};
partition@900000 {
label = "APPSBL_1";
reg = <0x900000 0x200000>;
read-only;
};
art: partition@b00000 {
label = "ART";
reg = <0xb00000 0x80000>;
read-only;
};
partition@b80000 {
label = "ubi";
reg = <0xb80000 0x7480000>;
};
};
};
};
&qpic_bam {
status = "okay";
};
&tlmm {
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio6";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio7";
function = "mdc";
bias-pull-up;
};
};
nand_pins: nand_pins {
pullups {
pins = "gpio52", "gpio53", "gpio58",
"gpio59";
function = "qpic";
bias-pull-up;
};
pulldowns {
pins = "gpio54", "gpio55", "gpio56",
"gpio57", "gpio60", "gpio61",
"gpio62", "gpio63", "gpio64",
"gpio65", "gpio66", "gpio67",
"gpio68", "gpio69";
function = "qpic";
bias-pull-down;
};
};
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "CM520-79F";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "CM520-79F";
};
&art {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_1006: macaddr@1006 {
reg = <0x1006 0x6>;
};
macaddr_art_5006: macaddr@5006 {
reg = <0x5006 0x6>;
};
};

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/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT
*
* Copyright (c) 2018 Peng Zhang <sd20@qxwlan.com>
*
*/
#include "qcom-ipq4019-e2600ac.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Qxwlan E2600AC c1";
compatible = "qxwlan,e2600ac-c1";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
flash@0 {
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:SBL1";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "0:MIBIB";
reg = <0x40000 0x20000>;
read-only;
};
partition@60000 {
label = "0:QSEE";
reg = <0x60000 0x60000>;
read-only;
};
partition@c0000 {
label = "0:CDT";
reg = <0xc0000 0x10000>;
read-only;
};
partition@d0000 {
label = "0:DDRPARAMS";
reg = <0xd0000 0x10000>;
read-only;
};
partition@e0000 {
label = "0:APPSBLENV";
reg = <0xe0000 0x10000>;
read-only;
};
partition@f0000 {
label = "0:APPSBL";
reg = <0xf0000 0x80000>;
read-only;
};
partition@170000 {
label = "0:ART";
reg = <0x170000 0x10000>;
read-only;
};
partition@180000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x180000 0x1e80000>;
};
};
};
};

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/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT
*
* Copyright (c) 2018 Peng Zhang <sd20@qxwlan.com>
*
*/
#include "qcom-ipq4019-e2600ac.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Qxwlan E2600AC c2";
compatible = "qxwlan,e2600ac-c2";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
flash@0 {
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:SBL1";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "0:MIBIB";
reg = <0x40000 0x20000>;
read-only;
};
partition@60000 {
label = "0:QSEE";
reg = <0x60000 0x60000>;
read-only;
};
partition@c0000 {
label = "0:CDT";
reg = <0xc0000 0x10000>;
read-only;
};
partition@d0000 {
label = "0:DDRPARAMS";
reg = <0xd0000 0x10000>;
read-only;
};
partition@e0000 {
label = "0:APPSBLENV";
reg = <0xe0000 0x10000>;
read-only;
};
partition@f0000 {
label = "0:APPSBL";
reg = <0xf0000 0x80000>;
read-only;
};
partition@170000 {
label = "0:ART";
reg = <0x170000 0x10000>;
read-only;
};
};
};
};
&nand {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "ubi";
reg = <0x00000000 0x04000000>;
};
};
};
};
&tlmm {
nand_pins: nand-pins {
pullups {
pins = "gpio53", "gpio58", "gpio59";
function = "qpic";
bias-pull-up;
};
pulldowns {
pins = "gpio54", "gpio55", "gpio56",
"gpio57", "gpio60", "gpio61",
"gpio62", "gpio63", "gpio64",
"gpio65", "gpio66", "gpio67",
"gpio68", "gpio69";
function = "qpic";
bias-pull-down;
};
};
};

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/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT
*
* Copyright (c) 2018 Peng Zhang <sd20@qxwlan.com>
*
*/
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Qxwlan E2600AC";
compatible = "qcom,ipq4019";
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>; /* 256MB */
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2: usb2@60f8800 {
status = "okay";
dwc3@6000000 {
#address-cells = <1>;
#size-cells = <0>;
usb2_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
};
};
serial@78af000 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
serial@78b0000 {
pinctrl-0 = <&serial_1_pins>;
pinctrl-names = "default";
status = "okay";
};
i2c@78b7000 { /* BLSP1 QUP2 */
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
status = "okay";
};
usb3: usb3@8af8800 {
status = "okay";
dwc3@8a00000 {
#address-cells = <1>;
#size-cells = <0>;
usb3_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
usb3_port2: port@2 {
reg = <2>;
#trigger-source-cells = <0>;
};
};
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
leds {
compatible = "gpio-leds";
led1 {
label = "green:wlan0";
gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
};
led2 {
label = "green:wlan1";
gpios = <&tlmm 36 GPIO_ACTIVE_LOW>;
};
led3 {
label = "green:usb";
gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
trigger-sources = <&usb2_port1>, <&usb3_port1>, <&usb3_port2>;
linux,default-trigger = "usbport";
};
led4 {
label = "green:ctrl1";
gpios = <&tlmm 51 GPIO_ACTIVE_LOW>;
};
led5 {
label = "green:ctrl2";
gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
};
led6 {
label = "green:ctrl3";
gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
};
&blsp_dma {
status = "okay";
};
&cryptobam {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&tlmm {
i2c_0_pins: i2c-0-pinmux {
mux {
pins = "gpio20", "gpio21";
function = "blsp_i2c0";
bias-disable;
};
};
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio6";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio7";
function = "mdc";
bias-pull-up;
};
};
serial_0_pins: serial0-pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
serial_1_pins: serial1_pinmux {
mux {
pins = "gpio8", "gpio9";
function = "blsp_uart1";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
drive-strength = <12>;
bias-disable;
};
pinmux_cs {
function = "gpio";
pins = "gpio12";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "Qxwlan-E2600AC";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "Qxwlan-E2600AC";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019-xx8300.dtsi"
/ {
model = "Linksys EA8300 (Dallas)";
compatible = "linksys,ea8300", "qcom,ipq4019";
aliases {
led-boot = &led_wps_amber;
led-failsafe = &led_wps;
led-running = &led_linksys;
led-upgrade = &led_world;
serial0 = &blsp1_uart1;
};
leds {
compatible = "gpio-leds";
// Retain node names from running OEM on EA8300
// Front panel LEDs, top to bottom
led_plug: diag {
label = "amber:plug";
gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
};
led_world: internet {
label = "amber:world";
gpios = <&tlmm 49 GPIO_ACTIVE_HIGH>;
};
led_wps: wps {
label = "white:wps";
gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
};
led_wps_amber: wps_amber {
label = "amber:wps";
gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
panic-indicator;
};
led_linksys: pwr {
label = "white:linksys";
gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
};
// On back panel, above USB socket
led_usb: usb {
label = "green:usb";
gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
trigger-sources = <&usb3_port1>, <&usb3_port2>,
<&usb2_port1>;
linux,default-trigger = "usbport";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
};
wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
};
};
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "linksys-ea8300-fcc";
};
&wifi1 {
status = "okay";
ieee80211-freq-limit = <5170000 5330000>;
qcom,ath10k-calibration-variant = "linksys-ea8300-fcc";
};
&wifi2 {
status = "okay";
ieee80211-freq-limit = <5490000 5835000>;
qcom,ath10k-calibration-variant = "linksys-ea8300-fcc";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "EnGenius EAP2200";
compatible = "engenius,eap2200";
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
keys {
compatible = "gpio-keys";
wps {
label = "wps";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
leds {
compatible = "gpio-leds";
led_power: power {
label = "amber:power";
gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
};
lan1 {
label = "blue:lan1";
gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
};
lan2 {
label = "blue:lan2";
gpios = <&tlmm 45 GPIO_ACTIVE_LOW>;
};
wlan2g {
label = "blue:wlan2g";
gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
wlan5g {
label = "yellow:wlan5g";
gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
wlan5g2 {
label = "yellow:wlan5g2";
gpios = <&tlmm 48 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy2tpt";
};
mode {
label = "blue:mode";
gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
};
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_lan_bmp = <0x10>;
};
edma@c080000 {
status = "okay";
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition0@0 {
label = "0:SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition1@40000 {
label = "0:MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition2@60000 {
label = "0:QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition3@c0000 {
label = "0:CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition4@d0000 {
label = "0:DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition5@e0000 {
label = "0:APPSBLENV";
reg = <0x000e0000 0x00010000>;
read-only;
};
partition6@f0000 {
label = "0:APPSBL";
reg = <0x000f0000 0x00080000>;
read-only;
};
partition7@170000 {
label = "0:ART";
reg = <0x00170000 0x00010000>;
read-only;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&gmac0 {
vlan_tag = <1 0x10>;
};
&nand {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "rootfs1";
reg = <0x00000000 0x04000000>;
};
partition@40000000 {
label = "ubi";
reg = <0x04000000 0x04000000>;
};
};
};
};
&pcie0 {
status = "okay";
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi2: wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
ieee80211-freq-limit = <5470000 5875000>;
qcom,ath10k-calibration-variant = "EnGenius-EAP2200";
};
};
};
&qpic_bam {
status = "okay";
};
&tlmm {
nand_pins: nand_pins {
pullups {
pins = "gpio53", "gpio58", "gpio59";
function = "qpic";
bias-pull-up;
};
pulldowns {
pins = "gpio54", "gpio55", "gpio56",
"gpio57", "gpio60", "gpio61",
"gpio62", "gpio63", "gpio64",
"gpio65", "gpio66", "gpio67",
"gpio68", "gpio69";
function = "qpic";
bias-pull-down;
};
};
serial_0_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
drive-strength = <12>;
bias-disable;
};
pinmux_cs {
function = "gpio";
pins = "gpio12";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "EnGenius-EAP2200";
};
&wifi1 {
status = "okay";
ieee80211-freq-limit = <5170000 5350000>;
qcom,ath10k-calibration-variant = "EnGenius-EAP2200";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "AVM FRITZ!Box 7530";
compatible = "avm,fritzbox-7530";
aliases {
led-boot = &power_green;
led-failsafe = &info_red;
led-running = &power_green;
led-upgrade = &info_green;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb3@8af8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
qcom,num_gmac = <1>;
};
};
keys {
compatible = "gpio-keys";
wlan {
label = "wlan";
gpios = <&tlmm 42 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
};
wps {
label = "wps";
gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
dect {
label = "dect";
gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PHONE>;
};
};
leds {
compatible = "gpio-leds";
info_red: info_red {
label = "red:info";
gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
};
info_green: info {
label = "green:info";
gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
};
wlan {
label = "green:wlan";
gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
};
fon {
label = "green:fon";
gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
};
power_green: power {
label = "green:power";
gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
};
wps {
label = "green:wps";
gpios = <&tlmm 45 GPIO_ACTIVE_LOW>;
};
};
};
&tlmm {
serial_0_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
nand_pins: nand_pins {
pullups {
pins = "gpio53", "gpio58", "gpio59";
function = "qpic";
bias-pull-up;
};
pulldowns {
pins = "gpio54", "gpio55", "gpio56",
"gpio57", "gpio60", "gpio61",
"gpio62", "gpio63", "gpio64",
"gpio65", "gpio66", "gpio67",
"gpio68", "gpio69";
function = "qpic";
bias-pull-down;
};
};
usb-power {
line-name = "enable USB3 power";
gpios = <49 GPIO_ACTIVE_HIGH>;
gpio-hog;
output-high;
};
};
&nand {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x000000 0x80000>;
read-only;
};
partition@80000 {
label = "MIBIB";
reg = <0x080000 0x80000>;
read-only;
};
partition@100000 {
label = "QSEE";
reg = <0x100000 0x80000>;
read-only;
};
partition@180000 {
label = "CDT";
reg = <0x180000 0x40000>;
read-only;
};
partition@1c0000 {
label = "QSEE_B";
reg = <0x1c0000 0x80000>;
read-only;
};
partition@240000 {
label = "urlader0";
reg = <0x240000 0x40000>;
read-only;
};
partition@280000 {
label = "urlader1";
reg = <0x280000 0x40000>;
read-only;
};
partition@2c0000 {
label = "nand-tffs";
reg = <0x2c0000 0x840000>;
read-only;
};
partition@b00000 {
/* 'kernel1' in AVM firmware */
label = "uboot0";
reg = <0xb00000 0x400000>;
};
partition@f00000 {
/* 'kernel2' in AVM firmware */
label = "uboot1";
reg = <0xf00000 0x400000>;
};
partition@1300000 {
label = "ubi";
reg = <0x1300000 0x6d00000>;
};
};
};
};
&cryptobam {
status = "okay";
};
&blsp_dma {
status = "okay";
};
&blsp1_uart1 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "AVM-FRITZBox-7530";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "AVM-FRITZBox-7530";
};
&pcie0 {
status = "okay";
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
dsl@1,0 {
compatible = "intel,vrx518";
status = "okay";
reg = <0x00010000 0 0 0 0>;
};
};
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "AVM FRITZ!Repeater 1200";
compatible = "avm,fritzrepeater-1200";
aliases {
led-boot = &power_green;
led-failsafe = &power_red;
led-running = &power_green;
led-upgrade = &power_red;
label-mac-device = &wifi0;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
/delete-node/ ethernet-phy@1;
/delete-node/ ethernet-phy@2;
/delete-node/ ethernet-phy@3;
/delete-node/ ethernet-phy@4;
/delete-node/ psgmii-phy@5;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
switch_mac_mode = <0x3>; /* mac mode for RGMII RMII */
switch_lan_bmp = <0x0>; /* lan port bitmap */
switch_wan_bmp = <0x10>; /* wan port bitmap */
};
edma@c080000 {
status = "okay";
phy-mode = "rgmii-id";
qcom,num_gmac = <1>;
qcom,single-phy;
};
};
key {
compatible = "gpio-keys";
wps {
label = "WPS button";
gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
leds {
compatible = "gpio-leds";
power_red: power_red {
label = "red:power";
gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
};
power_green: power_green {
label = "green:power";
gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
};
power_yellow {
label = "yellow:power";
gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
};
};
};
&tlmm {
serial_0_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
nand_pins: nand_pins {
pullups {
pins = "gpio53", "gpio58", "gpio59";
function = "qpic";
bias-pull-up;
};
pulldowns {
pins = "gpio54", "gpio55", "gpio56",
"gpio57", "gpio60", "gpio61",
"gpio62", "gpio63", "gpio64",
"gpio65", "gpio66", "gpio67",
"gpio68", "gpio69";
function = "qpic";
bias-pull-down;
};
};
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio6";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio7";
function = "mdc";
bias-pull-up;
};
};
phy-reset {
line-name = "PHY-reset";
gpios = <19 GPIO_ACTIVE_HIGH>;
gpio-hog;
output-high;
};
phy-reset-2 {
line-name = "PHY-reset-2";
gpios = <47 GPIO_ACTIVE_HIGH>;
gpio-hog;
output-high;
};
};
&nand {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x0 0x80000>;
read-only;
};
partition@80000 {
label = "MIBIB";
reg = <0x80000 0x80000>;
read-only;
};
partition@100000 {
label = "QSEE";
reg = <0x100000 0x80000>;
read-only;
};
partition@180000 {
label = "CDT";
reg = <0x180000 0x40000>;
read-only;
};
partition@1c0000 {
label = "QSEE_B";
reg = <0x1c0000 0x80000>;
read-only;
};
partition@240000 {
label = "urlader0";
reg = <0x240000 0x40000>;
read-only;
};
partition@280000 {
label = "urlader1";
reg = <0x280000 0x40000>;
read-only;
};
partition@2c0000 {
label = "nand-tffs";
reg = <0x2c0000 0x840000>;
read-only;
};
partition@b00000 {
/* 'kernel1' in AVM firmware */
label = "uboot0";
reg = <0xb00000 0x400000>;
};
partition@f00000 {
/* 'kernel2' in AVM firmware */
label = "uboot1";
reg = <0xf00000 0x400000>;
};
partition@1300000 {
label = "ubi";
reg = <0x1300000 0x6d00000>;
};
};
};
};
&cryptobam {
status = "okay";
};
&blsp_dma {
status = "okay";
};
&blsp1_uart1 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&qpic_bam {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-1200";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-1200";
};
&gmac0 {
qcom,phy_mdio_addr = <0>;
qcom,poll_required = <1>;
vlan_tag = <0 0x20>;
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "AVM FRITZ!Repeater 3000";
compatible = "avm,fritzrepeater-3000";
aliases {
led-boot = &power_led;
led-failsafe = &power_led;
led-running = &power_led;
led-upgrade = &power_led;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_lan_bmp = <0x30>;
switch_wan_bmp = <0x02>;
};
edma@c080000 {
status = "okay";
qcom,num_gmac = <1>;
};
};
key {
compatible = "gpio-keys";
connect {
label = "Connect";
gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
leds {
compatible = "gpio-leds";
connect_red {
label = "red:connect";
gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
};
connect_green {
label = "green:connect";
gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
};
connect_blue {
label = "blue:connect";
gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
};
power_led: power {
label = "green:power";
gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
};
};
};
&tlmm {
serial_0_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
nand_pins: nand_pins {
pullups {
pins = "gpio53", "gpio58", "gpio59";
function = "qpic";
bias-pull-up;
};
pulldowns {
pins = "gpio54", "gpio55", "gpio56",
"gpio57", "gpio60", "gpio61",
"gpio62", "gpio63", "gpio64",
"gpio65", "gpio66", "gpio67",
"gpio68", "gpio69";
function = "qpic";
bias-pull-down;
};
};
};
&nand {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x000000 0x80000>;
read-only;
};
partition@80000 {
label = "MIBIB";
reg = <0x080000 0x80000>;
read-only;
};
partition@100000 {
label = "QSEE";
reg = <0x100000 0x80000>;
read-only;
};
partition@180000 {
label = "CDT";
reg = <0x180000 0x40000>;
read-only;
};
partition@1c0000 {
label = "QSEE_B";
reg = <0x1c0000 0x80000>;
read-only;
};
partition@240000 {
label = "urlader0";
reg = <0x240000 0x40000>;
read-only;
};
partition@280000 {
label = "urlader1";
reg = <0x280000 0x40000>;
read-only;
};
partition@2c0000 {
label = "nand-tffs";
reg = <0x2c0000 0x840000>;
read-only;
};
partition@b00000 {
/* 'kernel1' in AVM firmware */
label = "uboot0";
reg = <0xb00000 0x400000>;
};
partition@f00000 {
/* 'kernel2' in AVM firmware */
label = "uboot1";
reg = <0xf00000 0x400000>;
};
partition@1300000 {
label = "ubi";
reg = <0x1300000 0x6d00000>;
};
};
};
};
&gmac0 {
vlan_tag = <1 0x30>;
};
&cryptobam {
status = "okay";
};
&blsp_dma {
status = "okay";
};
&blsp1_uart1 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&qpic_bam {
status = "okay";
};
&wifi0 {
status = "okay";
/* BDFs are identical for the FRITZ!Box 7530 and the FRITZ!Repeater 3000 */
qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-3000";
};
&wifi1 {
status = "okay";
ieee80211-freq-limit = <5170000 5350000>;
/* BDFs are identical for the FRITZ!Box 7530 and the FRITZ!Repeater 3000 */
qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-3000";
};
&pcie0 {
status = "okay";
perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
/* QCA9984 */
compatible = "qcom,ath10k";
status = "okay";
reg = <0x00010000 0 0 0 0>;
ieee80211-freq-limit = <5470000 5875000>;
/* Uses the reference BDF */
};
};
};

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// SPDX-License-Identifier: GPL-2.0-only OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "GL.iNet GL-B2200";
compatible = "glinet,gl-b2200", "qcom,ipq4019";
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
chosen {
bootargs-append = " root=/dev/mmcblk0p2 rw rootwait clk_ignore_unused";
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_lan_bmp = <0x2e>;
switch_wan_bmp = <0x10>;
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
wps {
label = "wps";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
linux,input-type = <1>;
};
reset {
label = "reset";
gpios = <&tlmm 40 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
linux,input-type = <1>;
};
};
leds {
compatible = "gpio-leds";
power_blue {
label = "blue:power";
gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
internet_blue {
label = "blue:internet";
gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
};
power_white {
label = "white:power";
gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
};
internet_white {
label = "white:internet";
gpios = <&tlmm 66 GPIO_ACTIVE_LOW>;
};
};
};
&gmac1 {
qcom,phy_mdio_addr = <3>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <2 0x10>;
};
&gmac0 {
vlan_tag = <1 0x2e>;
};
&vqmmc {
status = "okay";
};
&sdhci {
status = "okay";
pinctrl-0 = <&sd_pins>;
pinctrl-names = "default";
cd-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
vqmmc-supply = <&vqmmc>;
};
&blsp_dma {
status = "okay";
};
&cryptobam {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "MIBIB";
reg = <0x40000 0x20000>;
read-only;
};
partition@60000 {
label = "QSEE";
reg = <0x60000 0x60000>;
read-only;
};
partition@c0000 {
label = "CDT";
reg = <0xc0000 0x10000>;
read-only;
};
partition@d0000 {
label = "DDRPARAMS";
reg = <0xd0000 0x10000>;
read-only;
};
partition@e0000 {
label = "APPSBLENV";
reg = <0xe0000 0x10000>;
read-only;
};
partition@f0000 {
label = "APPSBL";
reg = <0xf0000 0x80000>;
read-only;
};
partition@170000 {
label = "ART";
reg = <0x170000 0x10000>;
read-only;
};
};
};
};
&blsp1_spi2 {
pinctrl-0 = <&spi_1_pins>;
pinctrl-names = "default";
status = "okay";
spidev1: spi@0 {
compatible = "siliconlabs,si3210";
reg = <0>;
spi-max-frequency = <24000000>;
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&blsp1_uart2 {
pinctrl-0 = <&serial_1_pins>;
pinctrl-names = "default";
status = "okay";
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
serial_1_pins: serial1_pinmux {
mux {
pins = "gpio8", "gpio9",
"gpio10", "gpio11";
function = "blsp_uart1";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
};
pinmux_cs {
function = "gpio";
pins = "gpio12";
};
pinconf {
pins = "gpio13", "gpio14", "gpio15";
drive-strength = <12>;
bias-disable;
};
pinconf_cs {
pins = "gpio12";
drive-strength = <2>;
bias-disable;
output-high;
};
};
spi_1_pins: spi_1_pinmux {
mux {
pins = "gpio44", "gpio46", "gpio47";
function = "blsp_spi1";
bias-disable;
};
cs {
pins = "gpio45";
function = "gpio";
bias-pull-up;
};
reset {
pins = "gpio43";
function = "gpio";
output-high;
};
mux_2 {
pins = "gpio35";
function = "gpio";
output-high;
};
host_int {
pins = "gpio2";
function = "gpio";
input;
};
wake {
pins = "gpio48";
function = "gpio";
output-high;
};
};
sd_pins: sd_pins {
pinmux {
function = "sdio";
pins = "gpio23", "gpio24", "gpio25", "gpio26",
"gpio29", "gpio30", "gpio31", "gpio32";
drive-strength = <10>;
};
pinmux_sd_clk {
function = "sdio";
pins = "gpio27";
drive-strength = <16>;
};
pinmux_sd7 {
function = "sdio";
pins = "gpio28";
drive-strength = <10>;
bias-disable;
};
};
};
&pcie0 {
status = "okay";
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi2: wifi@1,0 {
status = "okay";
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
qcom,ath10k-calibration-variant = "GL-B2200";
};
};
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "GL-B2200";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "GL-B2200";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2019, Robert Marko <robimarko@gmail.com> */
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "8devices Habanero DVK";
compatible = "8dev,habanero-dvk";
aliases {
led-boot = &led_status;
led-failsafe = &led_status;
led-running = &led_status;
led-upgrade = &led_upgrade;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
};
ess-psgmii@98000 {
status = "okay";
};
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
status = "okay";
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2: usb2@60f8800 {
status = "okay";
};
usb3: usb3@8af8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 8 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
led_status: status {
label = "green:status";
gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
panic-indicator;
};
led_upgrade: upgrade {
label = "green:upgrade";
gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
};
wlan2g {
label = "green:wlan2g";
gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tpt";
};
wlan5g {
label = "green:wlan5g";
gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy1tpt";
};
};
};
&vqmmc {
status = "okay";
};
&sdhci {
status = "okay";
pinctrl-0 = <&sd_pins>;
pinctrl-names = "default";
cd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
vqmmc-supply = <&vqmmc>;
};
&qpic_bam {
status = "okay";
};
&tlmm {
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio6";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio7";
function = "mdc";
bias-pull-up;
};
};
serial_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
drive-strength = <12>;
bias-disable;
};
pinmux_cs {
function = "gpio";
pins = "gpio12";
drive-strength = <2>;
bias-disable;
output-high;
};
};
nand_pins: nand_pins {
pullups {
pins = "gpio52", "gpio53", "gpio58", "gpio59";
function = "qpic";
bias-pull-up;
};
pulldowns {
pins = "gpio54", "gpio55", "gpio56", "gpio57",
"gpio60", "gpio62", "gpio63", "gpio64",
"gpio65", "gpio66", "gpio67", "gpio68",
"gpio69";
function = "qpic";
bias-pull-down;
};
};
sd_pins: sd_pins {
pinmux {
function = "sdio";
pins = "gpio23", "gpio24", "gpio25", "gpio26",
"gpio28", "gpio29", "gpio30", "gpio31";
drive-strength = <10>;
};
pinmux_sd_clk {
function = "sdio";
pins = "gpio27";
drive-strength = <16>;
};
pinmux_sd7 {
function = "sdio";
pins = "gpio32";
drive-strength = <10>;
bias-disable;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
status = "okay";
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <24000000>;
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition@40000 {
label = "MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition@60000 {
label = "QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition@c0000 {
label = "CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition@d0000 {
label = "DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition@e0000 {
label = "APPSBLENV"; /* uboot env */
reg = <0x000e0000 0x00010000>;
read-only;
};
partition@f0000 {
label = "APPSBL"; /* uboot */
reg = <0x000f0000 0x00080000>;
read-only;
};
partition@170000 {
label = "ART";
reg = <0x00170000 0x00010000>;
read-only;
};
partition@180000 {
label = "cfg";
reg = <0x00180000 0x00040000>;
};
partition@1c0000 {
label = "firmware";
compatible = "denx,fit";
reg = <0x001c0000 0x01e40000>;
};
};
};
};
/* Some DVK boards ship without NAND */
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
};
&blsp1_uart1 {
status = "okay";
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
};
&cryptobam {
status = "okay";
};
&pcie0 {
status = "okay";
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
/* Free slot for use */
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "8devices-Habanero";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "8devices-Habanero";
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "MikroTik hAP ac3";
compatible = "mikrotik,hap-ac3";
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
led-boot = &led_status_blue;
led-failsafe = &led_status_red;
led-running = &led_status_blue;
led-upgrade = &led_status_red;
};
soc {
rng@22000 {
status = "okay";
};
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2: usb2@60f8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
mode {
label = "mode";
gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
};
led {
label = "led";
gpios = <&tlmm 42 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
leds {
compatible = "gpio-leds";
led_status_blue: status-blue {
label = "blue:status";
gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
};
led_status_red: status-red {
label = "red:status";
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
panic-indicator;
};
led_status_green: status-green {
label = "green:status";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
};
wlan {
label = "green:wlan";
gpios = <&tlmm 23 GPIO_ACTIVE_HIGH>;
};
ethernet {
label = "green:ethernet";
gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
};
wan {
label = "green:wan";
gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
};
lan1 {
label = "green:lan1";
gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>;
};
lan2 {
label = "green:lan2";
gpios = <&tlmm 30 GPIO_ACTIVE_HIGH>;
};
lan3 {
label = "green:lan3";
gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;
};
lan4 {
label = "green:lan4";
gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
};
poe {
label = "red:poe";
gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>;
};
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio12";
drive-strength = <2>;
bias-disable;
output-high;
};
};
nand_pins: nand_pins {
pullups {
pins = "gpio53", "gpio58", "gpio59";
function = "qpic";
bias-pull-up;
};
pulldowns {
pins = "gpio55", "gpio56", "gpio57", "gpio60",
"gpio62", "gpio63", "gpio64", "gpio65",
"gpio66", "gpio67", "gpio68", "gpio69";
function = "qpic";
bias-pull-down;
};
};
enable-usb-power {
gpio-hog;
gpios = <44 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "enable USB power";
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
status = "okay";
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
flash@0 {
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <40000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Qualcomm";
reg = <0x0 0x80000>;
read-only;
};
partition@80000 {
compatible = "mikrotik,routerboot-partitions";
#address-cells = <1>;
#size-cells = <1>;
label = "RouterBoot";
reg = <0x80000 0x80000>;
read-only;
hard_config {
read-only;
size = <0x2000>;
};
dtb_config {
read-only;
};
soft_config {
};
};
};
};
};
&qpic_bam {
status = "okay";
};
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "kernel";
reg = <0x0 0xa00000>;
};
partition@a00000 {
label = "ubi";
reg = <0xa00000 0x7600000>;
};
};
};
};
&blsp1_uart1 {
status = "okay";
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
};
&cryptobam {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};
&mdio {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "MikroTik-hAP-ac3";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "MikroTik-hAP-ac3";
};

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/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
* Copyright (c) 2019, Robert Marko <robimarko@gmail.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Mikrotik Wireless Wire Dish LHGG-60ad";
compatible = "mikrotik,lhgg-60ad";
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
led-boot = &user;
led-failsafe = &user;
led-running = &user;
led-upgrade = &user;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
/delete-node/ ethernet-phy@1;
/delete-node/ ethernet-phy@2;
/delete-node/ ethernet-phy@3;
/delete-node/ ethernet-phy@4;
/delete-node/ psgmii-phy@5;
};
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
switch_mac_mode = <0x3>; /* mac mode for RGMII RMII */
switch_lan_bmp = <0x0>; /* lan port bitmap */
switch_wan_bmp = <0x10>; /* wan port bitmap */
};
edma@c080000 {
status = "okay";
phy-mode = "rgmii-id";
qcom,num_gmac = <1>;
qcom,single-phy;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
power: power {
label = "blue:power";
gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
default-state = "keep";
panic-indicator;
};
user: user {
label = "yellow:user";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
};
wlan {
label = "green:wlan";
gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
};
align-left {
label = "green:align-left";
gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
};
align-right {
label = "green:align-right";
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
};
wlan-rx {
label = "green:align-down";
gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
};
wlan-tx {
label = "green:align-up";
gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
};
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi-0-pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
bias-disable;
};
pinmux_cs {
function = "gpio";
pins = "gpio12";
bias-disable;
output-high;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
status = "okay";
m25p80@0 {
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "Qualcomm";
reg = <0x0 0x80000>;
read-only;
};
partition@80000 {
compatible = "mikrotik,routerboot-partitions";
#address-cells = <1>;
#size-cells = <1>;
label = "RouterBoot";
reg = <0x80000 0x80000>;
read-only;
hard_config {
read-only;
size = <0x2000>;
};
dtb_config {
read-only;
};
soft_config {
};
};
partition@100000 {
compatible = "mikrotik,minor";
label = "firmware";
reg = <0x100000 0xf00000>;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&pcie0 {
status = "okay";
perst-gpio = <&tlmm 42 GPIO_ACTIVE_HIGH>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
/* wil6210 802.11ad card */
wifi: wifi@1,0 {
status = "okay";
/* wil6210 driver has no compatible */
reg = <0x00010000 0 0 0 0>;
};
};
};
&gmac0 {
qcom,phy_mdio_addr = <0>;
qcom,poll_required = <1>;
vlan_tag = <0 0x20>;
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "ASUS Lyra MAP-AC2200";
compatible = "asus,map-ac2200";
aliases {
led-boot = &led_blue0;
led-failsafe = &led_red0;
led-running = &led_blue0;
led-upgrade = &led_red0;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
wps {
label = "wps";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
};
&nand {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x0 0x80000>;
read-only;
};
partition@80000 {
label = "MIBIB";
reg = <0x80000 0x80000>;
read-only;
};
partition@100000 {
label = "QSEE";
reg = <0x100000 0x100000>;
read-only;
};
partition@200000 {
label = "CDT";
reg = <0x200000 0x80000>;
read-only;
};
partition@280000 {
label = "APPSBL";
reg = <0x280000 0x140000>;
read-only;
};
partition@3c0000 {
label = "APPSBLENV";
reg = <0x3c0000 0x40000>;
read-only;
};
partition@400000 {
label = "ubi";
reg = <0x400000 0x7c00000>;
};
};
};
};
&tlmm {
i2c_0_pins: i2c_0_pinmux {
pinmux {
function = "blsp_i2c0";
pins = "gpio20", "gpio21";
drive-strength = <16>;
bias-disable;
};
};
serial_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
nand_pins: nand_pins {
pullups {
pins = "gpio52", "gpio53", "gpio58",
"gpio59";
function = "qpic";
bias-pull-up;
};
pulldowns {
pins = "gpio54", "gpio55", "gpio56",
"gpio57", "gpio60", "gpio61",
"gpio62", "gpio63", "gpio64",
"gpio65", "gpio66", "gpio67",
"gpio68", "gpio69";
function = "qpic";
bias-pull-down;
};
};
enable_ext_pa_high {
gpio-hog;
gpios = <44 GPIO_ACTIVE_HIGH>,
<46 GPIO_ACTIVE_HIGH>;
output-high;
bias-pull-down;
line-name = "enable external PA output-high";
};
enable_ext_pa_low {
gpio-hog;
gpios = <45 GPIO_ACTIVE_HIGH>,
<47 GPIO_ACTIVE_HIGH>;
output-low;
bias-pull-down;
line-name = "enable external PA output-low";
};
};
&cryptobam {
status = "okay";
};
&blsp_dma {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "ASUS-MAP-AC2200";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "ASUS-MAP-AC2200";
ieee80211-freq-limit = <5470000 5875000>;
};
&pcie0 {
status = "okay";
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi2: wifi@1,0 {
compatible = "qcom,ath10k";
status = "okay";
reg = <0x00010000 0 0 0 0>;
qcom,ath10k-calibration-variant = "ASUS-MAP-AC2200";
ieee80211-freq-limit = <5170000 5350000>;
};
};
};
&usb2_hs_phy {
/* Bluetooth module attached via USB */
status = "okay";
};
&blsp1_i2c3 {
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
status = "okay";
led-controller@32 {
/* 9-channel RGB LED controller */
compatible = "national,lp5523";
reg = <0x32>;
clock-mode = [01];
led_blue0: blue0 {
chan-name = "blue0";
label = "blue:chan0";
led-cur = [fa];
max-cur = [ff];
};
blue1 {
chan-name = "blue1";
label = "blue:chan1";
led-cur = [fa];
max-cur = [ff];
};
blue2 {
chan-name = "blue2";
label = "blue:chan2";
led-cur = [fa];
max-cur = [ff];
};
led_green0: green0 {
chan-name = "green0";
label = "green:chan0";
led-cur = [fa];
max-cur = [ff];
};
green1 {
chan-name = "green1";
label = "green:chan1";
led-cur = [fa];
max-cur = [ff];
};
green2 {
chan-name = "green2";
label = "green:chan2";
led-cur = [fa];
max-cur = [ff];
};
led_red0: red0 {
chan-name = "red0";
label = "red:chan0";
led-cur = [fa];
max-cur = [ff];
};
red1 {
chan-name = "red1";
label = "red:chan1";
led-cur = [fa];
max-cur = [ff];
};
red2 {
chan-name = "red2";
label = "red:chan2";
led-cur = [fa];
max-cur = [ff];
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019-xx8300.dtsi"
/ {
model = "Linksys MR8300 (Dallas)";
compatible = "linksys,mr8300", "qcom,ipq4019";
aliases {
led-boot = &led_blue;
led-failsafe = &led_red;
led-running = &led_blue;
led-upgrade = &led_amber;
serial0 = &blsp1_uart1;
};
// Top panel LEDs, above Linksys logo
leds {
compatible = "gpio-leds";
led_red: red {
label = "red:alarm";
gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
};
led_amber: amber {
label = "amber:programming";
gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
panic-indicator;
};
led_blue: blue {
label = "blue:power";
gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
};
// On back panel, above USB socket
led_usb: usb {
label = "green:usb";
gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
trigger-sources = <&usb3_port1>, <&usb3_port2>,
<&usb2_port1>;
linux,default-trigger = "usbport";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
};
wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
};
};
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "linksys-mr8300-v0-fcc";
};
&wifi1 {
status = "okay";
ieee80211-freq-limit = <5170000 5330000>;
qcom,ath10k-calibration-variant = "linksys-mr8300-v0-fcc";
};
&wifi2 {
status = "okay";
ieee80211-freq-limit = <5490000 5835000>;
qcom,ath10k-calibration-variant = "linksys-mr8300-v0-fcc";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "EdgeCore OAP-100";
compatible = "edgecore,oap100";
aliases {
led-boot = &led_system;
led-failsafe = &led_system;
led-running = &led_system;
led-upgrade = &led_system;
};
chosen {
bootargs-append = " root=/dev/ubiblock0_1";
};
soc {
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
usb2@60f8800 {
status = "okay";
dwc3@6000000 {
#address-cells = <1>;
#size-cells = <0>;
usb2_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
};
};
usb3@8af8800 {
status = "okay";
dwc3@8a00000 {
#address-cells = <1>;
#size-cells = <0>;
usb3_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
usb3_port2: port@2 {
reg = <2>;
#trigger-source-cells = <0>;
};
};
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_mac_mode = <0x0>; /* mac mode for RGMII RMII */
switch_initvlas = <0x0007c 0x54>; /* port0 status */
switch_lan_bmp = <0x10>;
};
edma@c080000 {
status = "okay";
};
};
key {
compatible = "gpio-keys";
button@1 {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
};
};
leds {
compatible = "gpio-leds";
led_system: led_system {
label = "green:system";
gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
};
led_2g {
label = "blue:wlan2g";
gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>;
};
led_5g {
label = "blue:wlan5g";
gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
};
};
gpio_export {
compatible = "gpio-export";
#size-cells = <0>;
usb {
gpio-export,name = "usb-power";
gpio-export,output = <1>;
gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>;
};
poe {
gpio-export,name = "poe-power";
gpio-export,output = <0>;
gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
};
};
};
&tlmm {
serial_0_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
drive-strength = <12>;
bias-disable;
};
pinmux_cs {
function = "gpio";
pins = "gpio12";
drive-strength = <2>;
bias-disable;
output-high;
};
};
nand_pins: nand_pins {
pullups {
pins = "gpio53", "gpio58", "gpio59";
function = "qpic";
bias-pull-up;
};
pulldowns {
pins = "gpio54", "gpio55", "gpio56",
"gpio57", "gpio60", "gpio61",
"gpio62", "gpio63", "gpio64",
"gpio65", "gpio66", "gpio67",
"gpio68", "gpio69";
function = "qpic";
bias-pull-down;
};
};
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio6";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio7";
function = "mdc";
bias-pull-up;
};
};
};
&cryptobam {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
linux,modalias = "m25p80", "gd25q256";
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition0@0 {
label = "0:SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition1@40000 {
label = "0:MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition2@60000 {
label = "0:QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition3@c0000 {
label = "0:CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition4@d0000 {
label = "0:DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition5@e0000 {
label = "0:APPSBLENV";
reg = <0x000e0000 0x00010000>;
read-only;
};
partition6@f0000 {
label = "0:APPSBL";
reg = <0x000f0000 0x00080000>;
read-only;
};
partition7@170000 {
label = "0:ART";
reg = <0x00170000 0x00010000>;
read-only;
};
};
};
};
&nand {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "rootfs";
reg = <0x00000000 0x4000000>;
};
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_uart1 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&qpic_bam {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "Edgecore OAP100";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "Edgecore OAP100";
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
aliases {
led-boot = &led_status_white;
led-failsafe = &led_status_red;
led-running = &led_status_green;
led-upgrade = &led_status_blue;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
};
ess-psgmii@98000 {
status = "okay";
};
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
status = "okay";
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_lan_bmp = <0x1c>;
switch_wan_bmp = <0x02>;
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
wps {
label = "wps";
gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
leds {
compatible = "gpio-leds";
led-0 {
label = "green:power";
gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
led-1 {
label = "red:power";
gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
panic-indicator;
};
led_status_green: led-2 {
label = "green:status";
gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>;
};
led_status_red: led-3 {
label = "red:status";
gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
};
led_status_blue: led-4 {
label = "blue:status";
gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
};
led_status_white: led-5 {
label = "white:status";
gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
};
};
};
&vqmmc {
status = "okay";
};
&sdhci {
status = "okay";
pinctrl-0 = <&sd_pins>;
pinctrl-names = "default";
cd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
vqmmc-supply = <&vqmmc>;
};
&qpic_bam {
status = "okay";
};
&tlmm {
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio6";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio7";
function = "mdc";
bias-pull-up;
};
};
serial_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
i2c_0_pins: i2c_0_pinmux {
pinmux {
function = "blsp_i2c0";
pins = "gpio58", "gpio59";
bias-disable;
};
};
sd_pins: sd_pins {
pinmux {
function = "sdio";
pins = "gpio23", "gpio24", "gpio25", "gpio26",
"gpio28", "gpio29", "gpio30", "gpio31";
drive-strength = <10>;
};
pinmux_sd_clk {
function = "sdio";
pins = "gpio27";
drive-strength = <16>;
};
pinmux_sd7 {
function = "sdio";
pins = "gpio32";
drive-strength = <10>;
bias-disable;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_i2c3 {
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
status = "okay";
led-controller@27 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "ti,tlc59108"; /* really is tlc59208f */
reg = <0x27>;
led0@0 {
label = "rgb:led0";
reg = <0x0>;
linux,default-trigger = "default-on";
};
led1@1 {
label = "rgb:led1";
reg = <0x1>;
linux,default-trigger = "default-on";
};
led2@2 {
label = "rgb:led2";
reg = <0x2>;
linux,default-trigger = "default-on";
};
led3@3 {
label = "rgb:led3";
reg = <0x3>;
linux,default-trigger = "default-on";
};
led4@4 {
label = "rgb:led4";
reg = <0x4>;
linux,default-trigger = "default-on";
};
led5@5 {
label = "rgb:led5";
reg = <0x5>;
linux,default-trigger = "default-on";
};
led6@6 {
label = "rgb:led6";
reg = <0x6>;
linux,default-trigger = "default-on";
};
led7@7 {
label = "rgb:led7";
reg = <0x7>;
linux,default-trigger = "default-on";
};
};
};
&blsp1_uart1 {
status = "okay";
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
};
&cryptobam {
status = "okay";
};
&gmac0 {
vlan_tag = <1 0x1c>;
};
&gmac1 {
qcom,phy_mdio_addr = <0>;
vlan_tag = <2 0x02>;
};
&pcie0 {
status = "okay";
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "qcom,ath10k";
status = "okay";
reg = <0x00010000 0 0 0 0>;
ieee80211-freq-limit = <5470000 5875000>;
qcom,ath10k-calibration-variant = "Netgear-Orbi-Pro-SRK60";
};
};
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "Netgear-Orbi-Pro-SRK60";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "Netgear-Orbi-Pro-SRK60";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/* Copyright (c) 2017-2020, Sven Eckelmann <sven@narfation.org>
* Copyright (c) 2018, Marek Lindner <marek.lindner@kaiwoo.ai>
*/
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Plasma Cloud PA2200";
compatible = "plasmacloud,pa2200";
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
switch_lan_bmp = <0x10>;
switch_wan_bmp = <0x20>;
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART >;
};
};
aliases {
led-boot = &led_power_orange;
led-failsafe = &led_status_blue;
led-running = &led_power_orange;
led-upgrade = &led_status_blue;
};
leds {
compatible = "gpio-leds";
led_power_orange: power_orange {
label = "orange:power";
gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
};
2g_blue {
label = "blue:2g";
gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
2g_green {
label = "green:5g1";
gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
5g2_green {
label = "green:5g2";
gpios = <&tlmm 48 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy2tpt";
};
led_status_blue: status_blue {
label = "blue:status";
gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
};
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio12";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
/* partitions are passed via bootloader */
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&gmac0 {
qcom,phy_mdio_addr = <3>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <1 0x10>;
};
&pcie0 {
status = "okay";
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi2: wifi@1,0 {
compatible = "qcom,ath10k";
status = "okay";
reg = <0x00010000 0 0 0 0>;
qcom,ath10k-calibration-variant = "PlasmaCloud-PA2200";
ieee80211-freq-limit = <5170000 5350000>;
};
};
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "PlasmaCloud-PA2200";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "PlasmaCloud-PA2200";
ieee80211-freq-limit = <5470000 5875000>;
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019-r619ac.dtsi"
/ {
model = "P&W R619AC 128M";
compatible = "p2w,r619ac-128m";
};
&nand_rootfs {
/*
* Watch out: stock MIBIB is set up for a 64MiB chip.
* If a 128MiB flash chip is used, make sure to have
* the right values in MIBIB or the device might not
* boot.
*/
reg = <0x0 0x8000000>;
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019-r619ac.dtsi"
/ {
model = "P&W R619AC 64M";
compatible = "p2w,r619ac-64m";
};
&nand_rootfs {
reg = <0x0 0x4000000>;
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
#include <dt-bindings/leds/common.h>
/ {
chosen {
bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
};
aliases {
led-boot = &led_sys;
led-failsafe = &led_sys;
led-running = &led_sys;
led-upgrade = &led_sys;
label-mac-device = &gmac0;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
};
usb3@8af8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
leds {
compatible = "gpio-leds";
led_sys: led-0 {
label = "blue:sys";
gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_POWER;
};
led-1 {
label = "blue:wlan2g";
gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tpt";
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_WLAN;
function-enumerator = <0>;
};
led-2 {
label = "blue:wlan5g";
gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy1tpt";
color = <LED_COLOR_ID_BLUE>;
function = LED_FUNCTION_WLAN;
function-enumerator = <1>;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
status = "okay";
flash@0 {
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "MIBIB";
reg = <0x40000 0x20000>;
read-only;
};
partition@60000 {
label = "QSEE";
reg = <0x60000 0x60000>;
read-only;
};
partition@c0000 {
label = "CDT";
reg = <0xc0000 0x10000>;
read-only;
};
partition@d0000 {
label = "DDRPARAMS";
reg = <0xd0000 0x10000>;
read-only;
};
partition@e0000 {
label = "APPSBLENV";
reg = <0xe0000 0x10000>;
read-only;
};
partition@f0000 {
label = "APPSBL";
reg = <0xf0000 0x80000>;
read-only;
};
partition@170000 {
label = "ART";
reg = <0x170000 0x10000>;
read-only;
};
};
};
};
&nand {
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
nand_rootfs: partition@0 {
label = "ubi";
/* reg defined in 64M/128M variant dts. */
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&pcie0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pcie_pins>;
perst-gpio = <&tlmm 4 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 40 GPIO_ACTIVE_HIGH>;
/* Free slot for use */
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
&qpic_bam {
status = "okay";
};
&sdhci {
pinctrl-0 = <&sd_0_pins>;
pinctrl-names = "default";
vqmmc-supply = <&vqmmc>;
status = "okay";
};
&tlmm {
pcie_pins: pcie_pinmux {
mux {
pins = "gpio2";
function = "gpio";
output-low;
bias-pull-down;
};
};
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio6";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio7";
function = "mdc";
bias-pull-up;
};
};
sd_0_pins: sd_0_pinmux {
mux_1 {
pins = "gpio23", "gpio24", "gpio25", "gpio26", "gpio28";
function = "sdio";
drive-strength = <10>;
};
mux_2 {
pins = "gpio27";
function = "sdio";
drive-strength = <16>;
};
};
serial_0_pins: serial0-pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
};
&ethphy0 {
qcom,single-led-1000;
qcom,single-led-100;
qcom,single-led-10;
};
&ethphy1 {
qcom,single-led-1000;
qcom,single-led-100;
qcom,single-led-10;
};
&ethphy2 {
qcom,single-led-1000;
qcom,single-led-100;
qcom,single-led-10;
};
&ethphy3 {
qcom,single-led-1000;
qcom,single-led-100;
qcom,single-led-10;
};
&ethphy4 {
qcom,single-led-1000;
qcom,single-led-100;
qcom,single-led-10;
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};
&vqmmc {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "P&W R619AC";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "P&W R619AC";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019-orbi.dtsi"
/ {
model = "NETGEAR RBR50";
compatible = "netgear,rbr50";
chosen {
bootargs = "root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_ALT)ro,256K(0:CDT)ro,256K(0:CDT_ALT)ro,256K(0:DDRPARAMS)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_ALT)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,1457651200(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait";
};
soc {
usb2@60f8800 {
status = "okay";
};
usb3@8af8800 {
status = "okay";
};
};
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019-orbi.dtsi"
/ {
model = "NETGEAR RBS50";
compatible = "netgear,rbs50";
chosen {
bootargs = "root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_ALT)ro,256K(0:CDT)ro,256K(0:CDT_ALT)ro,256K(0:DDRPARAMS)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_ALT)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,1457651200(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait";
};
soc {
usb2@60f8800 {
status = "okay";
};
usb3@8af8800 {
status = "okay";
};
};
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};

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// SPDX-License-Identifier: ISC
// Copyright (c) 2015, The Linux Foundation. All rights reserved.
// Copyright (c) 2019, Cezary Jackiewicz <cezary@eko.one.pl>.
// Copyright (c) 2020, Pawel Dembicki <paweldembicki@gmail.com>.
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/soc/qcom,tcsr.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Cell C RTL30VW";
compatible = "cellc,rtl30vw";
aliases {
led-boot = &led_power_blue;
led-failsafe = &led_power_red;
led-running = &led_power_blue;
led-upgrade = &led_power_red;
};
chosen {
bootargs-append = "ubi.mtd=ubifs root=/dev/ubiblock0_0 rootfstype=squashfs ro";
};
led_spi {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
num-chipselects = <1>;
mosi-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
cs-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
sck-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
led_gpio: led_gpio@0 {
compatible = "fairchild,74hc595";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
registers-number = <2>;
spi-max-frequency = <1000000>;
};
};
leds {
compatible = "gpio-leds";
led_power_blue: power_blue {
gpios = <&led_gpio 0 GPIO_ACTIVE_HIGH>;
label = "blue:power";
default-state = "on";
};
led_power_red: power_red {
gpios = <&led_gpio 1 GPIO_ACTIVE_HIGH>;
label = "red:power";
};
tp28 {
gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
label = "ext:tp28";
default-state = "keep";
};
tp27 {
gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
label = "ext:tp27";
default-state = "keep";
};
wlan2g {
gpios = <&led_gpio 8 GPIO_ACTIVE_HIGH>;
label = "blue:wlan2g";
linux,default-trigger = "phy0tpt";
};
wlan5g {
gpios = <&led_gpio 9 GPIO_ACTIVE_HIGH>;
label = "blue:wlan5g";
linux,default-trigger = "phy1tpt";
};
wps {
gpios = <&led_gpio 10 GPIO_ACTIVE_HIGH>;
label = "blue:wps";
};
voip {
gpios = <&led_gpio 11 GPIO_ACTIVE_HIGH>;
label = "blue:voip";
};
s1 {
gpios = <&led_gpio 12 GPIO_ACTIVE_HIGH>;
label = "blue:s1";
};
s2 {
gpios = <&led_gpio 13 GPIO_ACTIVE_HIGH>;
label = "blue:s2";
};
s3 {
gpios = <&led_gpio 14 GPIO_ACTIVE_HIGH>;
label = "blue:s3";
};
s4 {
gpios = <&led_gpio 15 GPIO_ACTIVE_HIGH>;
label = "blue:s4";
};
signal {
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
label = "red:signal";
};
};
keys {
compatible = "gpio-keys";
wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
};
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
};
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
};
usb3@8af8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
flash@0 {
/*"n25q128a11" is required for proper nand recognition in u-boot. */
compatible = "jedec,spi-nor", "n25q128a11";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:SBL1";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "0:MIBIB";
reg = <0x40000 0x20000>;
read-only;
};
partition@60000 {
label = "0:QSEE";
reg = <0x60000 0x60000>;
read-only;
};
partition@c0000 {
label = "0:CDT";
reg = <0xc0000 0x10000>;
read-only;
};
partition@d0000 {
label = "0:DDRPARAMS";
reg = <0xd0000 0x10000>;
read-only;
};
partition@e0000 {
label = "0:APPSBLENV";
reg = <0xe0000 0x10000>;
read-only;
};
partition@f0000 {
label = "0:APPSBL";
reg = <0xf0000 0x80000>;
read-only;
};
partition@170000 {
label = "0:ART";
reg = <0x170000 0x10000>;
read-only;
};
partition@180000 {
label = "0:BOOTCONFIG";
reg = <0x180000 0x10000>;
read-only;
};
};
};
flash@1 {
/*
* Factory U-boot looks in 0:BOOTCONFIG partition for active
* partitions settings and mangle partition config. So kernel
* /kernel_1 and rootfs/rootfs_1 pairs can be swaped.
* It isn't a problem but we never can be sure where OFW put
* factory images. "spinand,mt29f" value is required for proper
* nand recognition in u-boot.
*/
compatible = "spi-nand","spinand,mt29f";
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "kernel";
reg = <0x0 0x400000>;
};
partition@400000 {
label = "rootfs";
reg = <0x400000 0x2000000>;
};
partition@2400000 {
label = "kernel_1";
reg = <0x2400000 0x400000>;
};
partition@2800000 {
label = "rootfs_1";
reg = <0x2800000 0x2000000>;
};
partition@4800000 {
label = "ubifs";
reg = <0x4800000 0x3800000>;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pinmux_cs {
function = "gpio";
pins = "gpio54", "gpio59";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&usb2_hs_phy {
status = "okay";
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "cellc,rtl30vw";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "cellc,rtl30vw";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019-orbi.dtsi"
/ {
model = "NETGEAR SRR60";
compatible = "netgear,srr60";
chosen {
bootargs = "root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_1)ro,256K(0:CDT)ro,256K(0:CDT_1)ro,512K(0:BOOTCONFIG1)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_1)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,64K(cert)ro,3840K(kernel-2)ro,31488K(rootfs-2)ro,35328K@44881K(firmware-2)ro,5M(device_table)ro,17M(cp_file)ro,102737K(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait";
};
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019-orbi.dtsi"
/ {
model = "NETGEAR SRS60";
compatible = "netgear,srs60";
chosen {
bootargs = "root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_1)ro,256K(0:CDT)ro,256K(0:CDT_1)ro,512K(0:BOOTCONFIG1)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_1)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,64K(cert)ro,3840K(kernel-2)ro,31488K(rootfs-2)ro,35328K@44881K(firmware-2)ro,5M(device_table)ro,17M(cp_file)ro,102737K(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait";
};
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019-u4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Unielec U4019 (32M)";
compatible = "unielec,u4019-32m","unielec,u4019","qcom,ipq4019";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
flash@0 {
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <24000000>;
broken-flash-reset;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:SBL1";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "0:MIBIB";
reg = <0x40000 0x20000>;
read-only;
};
partition@60000 {
label = "0:QSEE";
reg = <0x60000 0x60000>;
read-only;
};
partition@c0000 {
label = "0:CDT";
reg = <0xc0000 0x10000>;
read-only;
};
partition@d0000 {
label = "0:DDRPARAMS";
reg = <0xd0000 0x10000>;
read-only;
};
partition@e0000 {
label = "0:APPSBLENV";
reg = <0xe0000 0x10000>;
read-only;
};
partition@f0000 {
label = "0:APPSBL";
reg = <0xf0000 0x80000>;
read-only;
};
partition@170000 {
label = "0:ART";
reg = <0x170000 0x10000>;
read-only;
};
partition@180000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x180000 0x1e80000>;
};
};
};
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
compatible = "unielec,u4019","qcom,ipq4019";
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
reset-delay-us = <2000>;
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
dwc3@6000000 {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
};
};
usb3@8af8800 {
status = "okay";
dwc3@8a00000 {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
port@2 {
reg = <2>;
#trigger-source-cells = <0>;
};
};
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
aliases {
led-boot = &led_status;
led-failsafe = &led_status;
led-running = &led_status;
led-upgrade = &led_status;
serial0 = &blsp1_uart1;
serial1 = &blsp1_uart2;
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
led_status: led2 {
label = "green:led2";
gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_uart1 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&blsp1_uart2 {
pinctrl-0 = <&serial_1_pins>;
pinctrl-names = "default";
status = "okay";
};
&qpic_bam {
status = "okay";
};
&tlmm {
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio6";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio7";
function = "mdc";
bias-pull-up;
};
};
serial_0_pins: serial0-pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
serial_1_pins: serial1_pinmux {
mux {
pins = "gpio8", "gpio9";
function = "blsp_uart1";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
drive-strength = <12>;
bias-disable;
};
pinmux_cs {
function = "gpio";
pins = "gpio12";
drive-strength = <2>;
bias-disable;
output-high;
};
};
led_pins: led_pinmux {
mux {
function = "gpio";
pins = "gpio68";
bias-disabled;
output-low;
};
};
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};
&wifi0 {
status = "okay";
};
&wifi1 {
status = "okay";
};

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/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
* Copyright (c) 2019, Nguyen Dinh Phi <phi_nguyen@compex.com.sg>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Compex WPJ419";
compatible = "compex,wpj419", "qcom,ipq4019";
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
reserved-memory {
ranges;
rsvd1@87000000 {
/* Reserved for other subsystem */
reg = <0x87000000 0x500000>;
no-map;
};
wifi_dump@87500000 {
reg = <0x87500000 0x600000>;
no-map;
};
rsvd2@87B00000 {
/* Reserved for other subsystem */
reg = <0x87B00000 0x500000>;
no-map;
};
};
chosen {
bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
};
soc {
pinctrl@1000000 {
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio6";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio7";
function = "mdc";
bias-pull-up;
};
};
serial_0_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
serial_1_pins: serial1_pinmux {
mux {
pins = "gpio8", "gpio9", "gpio10", "gpio11";
function = "blsp_uart1";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
bias-disable;
};
pinmux_cs {
function = "gpio";
pins = "gpio12";
bias-disable;
output-high;
};
};
i2c_0_pins: i2c_0_pinmux {
mux {
pins = "gpio20", "gpio21";
function = "blsp_i2c0";
bias-disable;
};
};
nand_pins: nand_pins {
pullups {
pins = "gpio52", "gpio53", "gpio58", "gpio59";
function = "qpic";
bias-pull-up;
};
pulldowns {
pins = "gpio54", "gpio55", "gpio56",
"gpio57", "gpio60", "gpio61",
"gpio62", "gpio63", "gpio64",
"gpio65", "gpio66", "gpio67",
"gpio68", "gpio69";
function = "qpic";
bias-pull-down;
};
};
led_0_pins: led0_pinmux {
mux_1 {
pins = "gpio36";
function = "led0";
bias-pull-down;
};
mux_2 {
pins = "gpio40";
function = "led4";
bias-pull-down;
};
};
};
blsp_dma: dma@7884000 {
status = "okay";
};
spi_0: spi@78b5000 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>, <&tlmm 41 GPIO_ACTIVE_HIGH>;
num-cs = <2>;
flash0@0 {
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <24000000>;
broken-flash-reset;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:SBL1";
reg = <0x000000 0x040000>;
read-only;
};
partition@40000 {
label = "0:MIBIB";
reg = <0x040000 0x020000>;
read-only;
};
partition@60000 {
label = "0:QSEE";
reg = <0x060000 0x060000>;
read-only;
};
partition@c0000 {
label = "0:CDT";
reg = <0x0c0000 0x010000>;
read-only;
};
partition@d0000 {
label = "0:DDRPARAMS";
reg = <0x0d0000 0x010000>;
read-only;
};
partition@e0000 {
label = "u-boot-env";
reg = <0x0e0000 0x010000>;
};
partition@f0000 {
label = "u-boot";
reg = <0x0f0000 0x080000>;
read-only;
};
partition@170000 {
label = "0:ART";
reg = <0x170000 0x010000>;
read-only;
};
};
};
nand@1 {
reg = <1>;
status = "okay";
compatible = "spi-nand";
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* The device has 128MB, but we can only address
* 64MB because of the bootloader's default settings.
* This is due to the old mt29f driver,
* which detected the deivce with only 64MB
*/
partition@0 {
label = "ubi";
reg = <0x0000000 0x4000000>;
};
};
};
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
reset-delay-us = <5000>;
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
i2c_0: i2c@78b7000 {
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
status = "okay";
};
serial@78af000 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
serial@78b0000 {
pinctrl-0 = <&serial_1_pins>;
pinctrl-names = "default";
status = "okay";
};
usb3_ss_phy: ssphy@9a000 {
status = "okay";
};
usb3_hs_phy: hsphy@a6000 {
status = "okay";
};
usb3: usb3@8af8800 {
status = "okay";
};
usb2_hs_phy: hsphy@a8000 {
status = "okay";
};
usb2: usb2@60f8800 {
status = "okay";
};
cryptobam: dma@8e04000 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
switch_lan_bmp = <0x1e>;
switch_wan_bmp = <0x20>;
status = "okay";
};
edma@c080000 {
status = "okay";
};
qpic_bam: dma@7984000 {
status = "okay";
};
pcie0: pci@40000000 {
status = "okay";
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
};
nand: nand-controller@79b0000 {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
&gmac0 {
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <2 0x20>;
};
&gmac1 {
qcom,phy_mdio_addr = <3>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <1 0x10>;
};
&wifi0 {
status = "okay";
};
&wifi1 {
status = "okay";
};

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// SPDX-License-Identifier: ISC
/*
* Copyright (c) 2015 - 2016, The Linux Foundation. All rights reserved.
* Copyright (c) 2020 Yanase Yuki <dev@zpc.sakura.ne.jp>
*/
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Buffalo WTR-M2133HP";
compatible = "buffalo,wtr-m2133hp", "qcom,ipq4019";
memory {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
chosen {
/*
* U-Boot adds "ubi.mtd=rootfs root=mtd:ubi_rootfs" to
* kernel command line. But we use different partition names,
* so we have to set correct parameters.
*/
bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
};
aliases {
led-boot = &led_power_blue;
led-failsafe = &led_power_orange;
led-running = &led_power_white;
led-upgrade = &led_power_blue;
label-mac-device = &gmac0;
};
soc {
rng@22000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_lan_bmp = <0x1c>;
};
ess-psgmii@98000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
usb3@8af8800 {
status = "okay";
};
};
leds {
compatible = "gpio-leds";
led_power_white: power_white {
label = "white:power";
gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
};
led_power_orange: power_orange {
label = "orange:power";
gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
};
led_power_blue: power_blue {
label = "blue:power";
gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
};
router_white {
label = "white:router";
gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
};
router_orange {
label = "orange:router";
gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
};
internet_white {
label = "white:internet";
gpios = <&tlmm 27 GPIO_ACTIVE_HIGH>;
};
internet_orange {
label = "orange:internet";
gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
};
wireless_white {
label = "white:wireless";
gpios = <&tlmm 24 GPIO_ACTIVE_HIGH>;
};
wireless_orange {
label = "orange:wireless";
gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>;
};
};
keys {
compatible = "gpio-keys";
auto_mode {
label = "auto_mode";
gpios = <&tlmm 9 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
linux,input-type = <EV_SW>;
};
router_mode {
label = "router_mode";
gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
linux,code = <BTN_1>;
linux,input-type = <EV_SW>;
};
ap_mode {
label = "ap_mode";
gpios = <&tlmm 11 GPIO_ACTIVE_LOW>;
linux,code = <BTN_2>;
linux,input-type = <EV_SW>;
};
reset {
label = "reset";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
wps {
label = "AOSS Button";
gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
};
};
&tlmm {
serial_0_pins: serial0_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio6";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio7";
function = "mdc";
bias-pull-up;
};
};
nand_pins: nand_pins {
pullups {
pins = "gpio52", "gpio53", "gpio58",
"gpio59";
function = "qpic";
bias-pull-up;
};
pulldowns {
pins = "gpio54", "gpio55", "gpio56",
"gpio57", "gpio60", "gpio61",
"gpio62", "gpio63", "gpio64",
"gpio65", "gpio66", "gpio67",
"gpio68", "gpio69";
function = "qpic";
bias-pull-down;
};
};
usb_power {
line-name = "USB power";
gpios = <34 GPIO_ACTIVE_HIGH>;
gpio-hog;
output-high;
};
};
&blsp_dma {
status = "okay";
};
&blsp1_uart1 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&pcie0 {
status = "okay";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@0,0 {
compatible = "qcom,ath10k";
reg = <0 0 0 0 0>;
qcom,ath10k-calibration-variant = "Buffalo-WTR-M2133HP";
};
};
};
&qpic_bam {
status = "okay";
};
&nand {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x0000000 0x0100000>;
read-only;
};
partition@100000 {
label = "MIBIB";
reg = <0x0100000 0x0100000>;
read-only;
};
partition@200000 {
label = "BOOTCONFIG";
reg = <0x0200000 0x0100000>;
read-only;
};
partition@300000 {
label = "QSEE";
reg = <0x0300000 0x0100000>;
read-only;
};
partition@400000 {
label = "QSEE_1";
reg = <0x0400000 0x0100000>;
read-only;
};
partition@500000 {
label = "CDT";
reg = <0x0500000 0x0080000>;
read-only;
};
partition@580000 {
label = "CDT_1";
reg = <0x0580000 0x0080000>;
read-only;
};
partition@600000 {
label = "BOOTCONFIG1";
reg = <0x0600000 0x0080000>;
read-only;
};
partition@680000 {
label = "APPSBLENV";
reg = <0x0680000 0x0080000>;
};
partition@700000 {
label = "APPSBL";
reg = <0x0700000 0x0200000>;
read-only;
};
partition@900000 {
label = "APPSBL_1";
reg = <0x0900000 0x0200000>;
read-only;
};
art: partition@b00000 {
label = "ART";
reg = <0x0b00000 0x0080000>;
read-only;
};
partition@b80000 {
label = "ART_1";
reg = <0x0b80000 0x0080000>;
read-only;
};
orgdata: partition@c00000 {
label = "ORGDATA";
reg = <0x0c00000 0x0080000>;
read-only;
};
partition@c80000 {
label = "ORGDATA_1";
reg = <0x0c80000 0x0080000>;
read-only;
};
partition@d00000 {
label = "ubi";
reg = <0x0d00000 0x2900000>;
};
partition@3600000 {
label = "rootfs_recover";
reg = <0x3600000 0x2900000>;
read-only;
};
partition@5f00000 {
label = "user_property";
reg = <0x5f00000 0x1a20000>;
read-only;
};
};
};
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "Buffalo-WTR-M2133HP";
ieee80211-freq-limit = <2400000 2483000>;
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "Buffalo-WTR-M2133HP";
};
&mdio {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
};
&gmac0 {
nvmem-cells = <&macaddr_orgdata_20>;
nvmem-cell-names = "mac-address";
};
&gmac1 {
nvmem-cells = <&macaddr_orgdata_20>;
nvmem-cell-names = "mac-address";
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&orgdata {
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
macaddr_orgdata_20: macaddr@20 {
reg = <0x20 0x6>;
};
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Device Tree Source for Linksys xx8300 (Dallas)
*
* Copyright (C) 2019 Jeff Kletsky
* Updated 2020 Hans Geiblinger
*
*/
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
//
// OEM U-Boot provides either
// init=/sbin/init rootfstype=ubifs ubi.mtd=11,2048 \
// root=ubi0:ubifs rootwait rw
// or the same with ubi.mtd=13,2048
//
/ {
chosen {
bootargs-append = " root=/dev/ubiblock0_0 rootfstype=squashfs ro";
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
dwc3@6000000 {
#address-cells = <1>;
#size-cells = <0>;
usb2_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
};
};
usb3@8af8800 {
status = "okay";
dwc3@8a00000 {
#address-cells = <1>;
#size-cells = <0>;
usb3_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
usb3_port2: port@2 {
reg = <2>;
#trigger-source-cells = <0>;
};
};
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_uart1 {
status = "okay";
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
};
&cryptobam {
status = "okay";
};
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "sbl1";
reg = <0x0 0x100000>;
read-only;
};
partition@100000 {
label = "mibib";
reg = <0x100000 0x100000>;
read-only;
};
partition@200000 {
label = "qsee";
reg = <0x200000 0x100000>;
read-only;
};
partition@300000 {
label = "cdt";
reg = <0x300000 0x80000>;
read-only;
};
partition@380000 {
label = "appsblenv";
reg = <0x380000 0x80000>;
read-only;
};
partition@400000 {
label = "ART";
reg = <0x400000 0x80000>;
read-only;
};
partition@480000 {
label = "appsbl";
reg = <0x480000 0x200000>;
read-only;
};
partition@680000 {
label = "u_env";
reg = <0x680000 0x80000>;
// writable -- U-Boot environment
};
partition@700000 {
label = "s_env";
reg = <0x700000 0x40000>;
// writable -- Boot counter records
};
partition@740000 {
label = "devinfo";
reg = <0x740000 0x40000>;
read-only;
};
partition@780000 {
label = "kernel";
reg = <0x780000 0x5800000>;
};
partition@a80000 {
label = "rootfs";
reg = <0xa80000 0x5500000>;
};
partition@5f80000 {
label = "alt_kernel";
reg = <0x5f80000 0x5800000>;
};
partition@6280000 {
label = "alt_rootfs";
reg = <0x6280000 0x5500000>;
};
partition@b780000 {
label = "sysdiag";
reg = <0xb780000 0x100000>;
read-only;
};
partition@b880000 {
label = "syscfg";
reg = <0xb880000 0x4680000>;
read-only;
};
};
};
};
&pcie0 {
status = "okay";
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi2: wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
};
};
};
&qpic_bam {
status = "okay";
};
&tlmm {
serial_0_pins: serial0-pinmux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
nand_pins: nand_pins {
pullups {
pins = "gpio53", "gpio58", "gpio59";
function = "qpic";
bias-pull-up;
};
// gpio61 controls led_usb
pulldowns {
pins = "gpio55", "gpio56", "gpio57",
"gpio60", "gpio62", "gpio63",
"gpio64", "gpio65", "gpio66",
"gpio67", "gpio68", "gpio69";
function = "qpic";
bias-pull-down;
};
};
};
&usb2_hs_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb3_ss_phy {
status = "okay";
};

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/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
* Copyright (c) 2017, Christian Mehlis <christian@m3hlis.de>
* Copyright (c) 2017-2018, Sven Eckelmann <sven.eckelmann@openmesh.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Compex WPJ428";
compatible = "compex,wpj428";
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
reset-delay-us = <2000>;
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2: usb2@60f8800 {
status = "okay";
};
usb3: usb3@8af8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
switch_lan_bmp = <0x10>;
switch_wan_bmp = <0x20>;
status = "okay";
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
aliases {
led-boot = &status;
led-failsafe = &status;
led-upgrade = &status;
};
leds {
compatible = "gpio-leds";
status: rss4 {
label = "green:rss4";
gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
};
rss3 {
label = "green:rss3";
gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
};
};
beeper: beeper {
compatible = "gpio-beeper";
gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
};
};
&tlmm {
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio53";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio52";
function = "mdc";
bias-pull-up;
};
};
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
m25p80@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition0@0 {
label = "0:SBL1";
reg = <0x00000000 0x00040000>;
read-only;
};
partition1@40000 {
label = "0:MIBIB";
reg = <0x00040000 0x00020000>;
read-only;
};
partition2@60000 {
label = "0:QSEE";
reg = <0x00060000 0x00060000>;
read-only;
};
partition3@c0000 {
label = "0:CDT";
reg = <0x000c0000 0x00010000>;
read-only;
};
partition4@d0000 {
label = "0:DDRPARAMS";
reg = <0x000d0000 0x00010000>;
read-only;
};
partition5@e0000 {
label = "0:APPSBLENV"; /* uboot env*/
reg = <0x000e0000 0x00010000>;
read-only;
};
partition5@f0000 {
label = "0:APPSBL"; /* uboot */
reg = <0x000f0000 0x00080000>;
read-only;
};
partition5@170000 {
label = "0:ART";
reg = <0x00170000 0x00010000>;
read-only;
};
partition6@180000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x00180000 0x01e80000>;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&gmac0 {
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <2 0x20>;
};
&gmac1 {
qcom,phy_mdio_addr = <3>;
qcom,poll_required = <1>;
qcom,forced_speed = <1000>;
qcom,forced_duplex = <1>;
vlan_tag = <1 0x10>;
};
&usb3_ss_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb2_hs_phy {
status = "okay";
};
&wifi0 {
status = "okay";
};
&wifi1 {
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0-only OR MIT
#include "qcom-ipq4029-aruba-glenmorangie.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Aruba AP-303";
compatible = "aruba,ap-303";
aliases {
led-boot = &led_system_green;
led-failsafe = &led_system_red;
led-running = &led_system_green;
led-upgrade = &led_system_red;
};
leds {
compatible = "gpio-leds";
wifi_green {
label = "green:wifi";
gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tpt";
};
wifi_amber {
label = "amber:wifi";
gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy1tpt";
};
led_system_red: system_red {
label = "red:system";
gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
};
led_system_green: system_green {
label = "green:system";
gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
};
};
};
&tlmm {
/*
* In addition to the Pins listed below,
* the following GPIOs have "features":
* 54 - out - active low to force HW reset
* 41 - out - active low to reset TPM
* 43 - out - active low to reset BLE radio
* 19 - in - active high when DC powered
*/
phy-reset {
line-name = "PHY-reset";
gpios = <42 GPIO_ACTIVE_HIGH>;
gpio-hog;
output-high;
};
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/*
* There is no partition map for the NOR flash
* in the stock firmware.
*
* All partitions here are based on offsets
* found in the U-Boot GPL code and information
* from smem.
*/
partition@0 {
label = "sbl1";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "mibib";
reg = <0x40000 0x20000>;
read-only;
};
partition@60000 {
label = "qsee";
reg = <0x60000 0x60000>;
read-only;
};
partition@c0000 {
label = "cdt";
reg = <0xc0000 0x10000>;
read-only;
};
partition@d0000 {
label = "ddrparams";
reg = <0xd0000 0x10000>;
read-only;
};
partition@e0000 {
label = "ART";
reg = <0xe0000 0x10000>;
read-only;
};
partition@f0000 {
label = "appsbl";
reg = <0xf0000 0xf0000>;
read-only;
};
partition@1e0000 {
label = "mfginfo";
reg = <0x1e0000 0x10000>;
read-only;
};
partition@1f0000 {
label = "apcd";
reg = <0x1f0000 0x10000>;
read-only;
};
partition@200000 {
label = "osss";
reg = <0x200000 0x180000>;
read-only;
};
partition@380000 {
label = "appsblenv";
reg = <0x380000 0x10000>;
};
partition@390000 {
label = "pds";
reg = <0x390000 0x10000>;
read-only;
};
partition@3a0000 {
label = "fcache";
reg = <0x3a0000 0x10000>;
read-only;
};
partition@3b0000 {
/* Called osss1 in smem */
label = "u-boot-env-bak";
reg = <0x3b0000 0x10000>;
read-only;
};
partition@3f0000 {
label = "u-boot-env";
reg = <0x3f0000 0x10000>;
read-only;
};
};
};
};

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// SPDX-License-Identifier: GPL-2.0-only OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Aruba AP-303H";
compatible = "aruba,ap-303h";
aliases {
led-boot = &led_system_green;
led-failsafe = &led_system_red;
led-running = &led_system_green;
led-upgrade = &led_system_amber;
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
reset-delay-us = <2000>;
};
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
i2c_0: i2c@78b7000 {
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
status = "okay";
tpm@29 {
/* No Driver */
compatible = "atmel,at97sc3203";
reg = <0x29>;
read-only;
};
power-monitor@40 {
/* No driver */
compatible = "isl,isl28022";
reg = <0x40>;
};
};
};
leds {
compatible = "gpio-leds";
wifi_green {
label = "green:wifi";
gpios = <&tlmm 27 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tpt";
};
wifi_amber {
label = "amber:wifi";
gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy1tpt";
};
pse {
label = "green:pse";
gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
};
led_system_red: system_red {
label = "red:system";
gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
};
led_system_green: system_green {
label = "green:system";
gpios = <&tlmm 24 GPIO_ACTIVE_HIGH>;
};
led_system_amber: system_amber {
label = "amber:system";
gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "Reset button";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_uart1 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&blsp1_uart2 {
/* Texas Instruments CC2540T BLE radio */
pinctrl-0 = <&serial_1_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&qpic_bam {
status = "okay";
};
&tlmm {
/*
* In addition to the Pins listed below,
* the following GPIOs have "features":
* 39 - out - active low to force HW reset
* 32 - out - active low to reset TPM
* 43 - out - active low to reset BLE radio
* 41 - out - pulse to set warm reset status
* 34 - out - active low to enable PSE port
* 22 - in - active low when 802.3at powered
* 29 - in - active high when DC powered
* 40 - in - active low when reset due to cold HW reset
* 30 - in - active low when USB overcurrent detected
* 35 - in - interrupt line for power monitor chip
* 31 - in - active low when PSE port active
*/
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio6";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio7";
function = "mdc";
bias-pull-up;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio12", "gpio59";
drive-strength = <2>;
bias-disable;
output-high;
};
};
i2c_0_pins: i2c_0_pinmux {
mux {
pins = "gpio20", "gpio21";
function = "blsp_i2c0";
drive-strength = <4>;
bias-disable;
};
};
serial_0_pins: serial_0_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
serial_1_pins: serial_1_pinmux {
mux {
pins = "gpio8", "gpio9";
function = "blsp_uart1";
bias-disable;
};
};
usb-power {
line-name = "USB-power";
gpios = <23 GPIO_ACTIVE_HIGH>;
gpio-hog;
output-high;
};
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/*
* There is no partition map for the NOR flash
* in the stock firmware.
*
* All partitions here are based on offsets
* found in the U-Boot GPL code and information
* from smem.
*/
partition@0 {
label = "sbl1";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "mibib";
reg = <0x40000 0x20000>;
read-only;
};
partition@60000 {
label = "qsee";
reg = <0x60000 0x60000>;
read-only;
};
partition@c0000 {
label = "cdt";
reg = <0xc0000 0x10000>;
read-only;
};
partition@d0000 {
label = "ddrparams";
reg = <0xd0000 0x10000>;
read-only;
};
partition@e0000 {
label = "appsblenv";
reg = <0xe0000 0x10000>;
read-only;
};
partition@f0000 {
label = "appsbl";
reg = <0xf0000 0x100000>;
read-only;
};
partition@1e0000 {
label = "ART";
reg = <0x1f0000 0x10000>;
read-only;
};
partition@1f0000 {
label = "osss";
reg = <0x200000 0x170000>;
read-only;
};
partition@200000 {
label = "pds";
reg = <0x370000 0x10000>;
read-only;
};
partition@380000 {
label = "apcd";
reg = <0x380000 0x10000>;
read-only;
};
partition@390000 {
label = "mfginfo";
reg = <0x390000 0x10000>;
read-only;
};
partition@3a0000 {
label = "fcache";
reg = <0x3a0000 0x10000>;
read-only;
};
partition@3b0000 {
/* Called osss1 in smem */
label = "u-boot-env-bak";
reg = <0x3b0000 0x10000>;
read-only;
};
partition@3f0000 {
label = "u-boot-env";
reg = <0x3c0000 0x40000>;
read-only;
};
};
};
flash@1 {
status = "okay";
compatible = "spi-nand";
reg = <1>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
/* 'aos0' in Aruba firmware */
label = "aos0";
reg = <0x0 0x2000000>;
read-only;
};
partition@2000000 {
/* 'aos1' in Aruba firmware */
label = "ubi";
reg = <0x2000000 0x2000000>;
};
partition@4000000 {
label = "aruba-ubifs";
reg = <0x4000000 0x4000000>;
read-only;
};
};
};
};
&usb2_hs_phy {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "Aruba-AP-303";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "Aruba-AP-303";
};

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// SPDX-License-Identifier: GPL-2.0-only OR MIT
#include "qcom-ipq4029-aruba-glenmorangie.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Aruba AP-365";
compatible = "aruba,ap-365";
aliases {
led-boot = &led_system_green;
led-failsafe = &led_system_red;
led-running = &led_system_green;
led-upgrade = &led_system_red;
};
leds {
compatible = "gpio-leds";
led_system_red: system_red {
label = "red:system";
gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
};
led_system_green: system_green {
label = "green:system";
gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
};
system_amber {
label = "amber:system";
gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
};
};
watchdog {
compatible = "linux,wdt-gpio";
gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
hw_algo = "toggle";
hw_margin_ms = <1000>;
always-running;
};
};
&tlmm {
/*
* In addition to the Pins listed below,
* the following GPIOs have "features":
* 39 - out - pulse low to reset watchdog status flipflop
* 40 - out - active high to enable watchdog
* 41 - out - watchdog poke
* 42 - out - active low to reset BLE radio
* 43 - out - active low to reset TPM
* 47 - out - pulse low to reset warm reset status
* 54 - out - active low to force HW reset
* 18 - in - PHY interrupt line
* 45 - in - power monitor interrupt
* 48 - in - active low when cold reset
* 52 - in - active high when watchdog reset
*/
phy-reset {
line-name = "PHY-reset";
gpios = <42 GPIO_ACTIVE_HIGH>;
gpio-hog;
output-high;
};
};
&i2c_0 {
power-monitor@40 {
/* No driver */
compatible = "isl,isl28022";
reg = <0x40>;
};
temperature-sensor@48 {
compatible = "adi,ad7416";
reg = <0x48>;
};
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/*
* There is no partition map for the NOR flash
* in the stock firmware.
*
* All partitions here are based on offsets
* found in the U-Boot GPL code and information
* from smem.
*/
partition@0 {
label = "sbl1";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "mibib";
reg = <0x40000 0x20000>;
read-only;
};
partition@60000 {
label = "qsee";
reg = <0x60000 0x60000>;
read-only;
};
partition@c0000 {
label = "cdt";
reg = <0xc0000 0x10000>;
read-only;
};
partition@d0000 {
label = "ddrparams";
reg = <0xd0000 0x10000>;
read-only;
};
partition@e0000 {
label = "u-boot-env";
reg = <0xe0000 0x10000>;
};
partition@f0000 {
label = "appsbl";
reg = <0xf0000 0x100000>;
read-only;
};
partition@1f0000 {
label = "ART";
reg = <0x1f0000 0x10000>;
read-only;
};
partition@200000 {
label = "osss";
reg = <0x200000 0x170000>;
read-only;
};
partition@370000 {
label = "pds";
reg = <0x370000 0x10000>;
read-only;
};
partition@380000 {
label = "apcd";
reg = <0x380000 0x10000>;
read-only;
};
partition@390000 {
label = "mfginfo";
reg = <0x390000 0x10000>;
read-only;
};
partition@3a0000 {
label = "fcache";
reg = <0x3a0000 0x10000>;
read-only;
};
partition@3b0000 {
label = "osss1";
reg = <0x3b0000 0x50000>;
read-only;
};
};
};
};

251
root/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-aruba-glenmorangie.dtsi Normal file
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@ -0,0 +1,251 @@
// SPDX-License-Identifier: GPL-2.0-only OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
/delete-node/ ethernet-phy@0;
/delete-node/ ethernet-phy@1;
/delete-node/ ethernet-phy@2;
/delete-node/ ethernet-phy@3;
/delete-node/ ethernet-phy@4;
/delete-node/ psgmii-phy@5;
ethernet-phy@5 {
reg = <0x5>;
};
};
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
switch_mac_mode = <0x3>; /* mac mode for RGMII RMII */
switch_lan_bmp = <0x0>; /* lan port bitmap */
switch_wan_bmp = <0x10>; /* wan port bitmap */
};
edma@c080000 {
qcom,single-phy;
qcom,num_gmac = <1>;
phy-mode = "rgmii-id";
status = "okay";
};
i2c_0: i2c@78b7000 {
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
status = "okay";
tpm@29 {
/* No Driver */
compatible = "atmel,at97sc3203";
reg = <0x29>;
read-only;
};
};
};
keys {
compatible = "gpio-keys";
reset {
label = "Reset button";
gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_uart1 {
/* Texas Instruments CC2540T BLE radio */
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&blsp1_uart2 {
pinctrl-0 = <&serial_1_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&gmac0 {
qcom,phy_mdio_addr = <5>;
qcom,poll_required = <1>;
vlan_tag = <0 0x20>;
};
&qpic_bam {
status = "okay";
};
&tlmm {
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio6";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio7";
function = "mdc";
bias-pull-up;
};
};
nand_pins: nand_pins {
pullups {
pins = "gpio53", "gpio58", "gpio59";
function = "qpic";
bias-pull-up;
};
pulldowns {
pins = "gpio54", "gpio55", "gpio56",
"gpio57", "gpio60", "gpio61",
"gpio62", "gpio63", "gpio64",
"gpio65", "gpio66", "gpio67",
"gpio68", "gpio69";
function = "qpic";
bias-pull-down;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio12";
drive-strength = <2>;
bias-disable;
output-high;
};
};
i2c_0_pins: i2c_0_pinmux {
mux {
pins = "gpio10", "gpio11";
function = "blsp_i2c0";
drive-strength = <4>;
bias-disable;
};
};
serial_0_pins: serial_0_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
serial_1_pins: serial_1_pinmux {
mux {
pins = "gpio8", "gpio9";
function = "blsp_uart1";
bias-disable;
};
};
};
&nand {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
/* 'aos0' in Aruba firmware */
label = "aos0";
reg = <0x0 0x2000000>;
read-only;
};
partition@2000000 {
/* 'aos1' in Aruba firmware */
label = "ubi";
reg = <0x2000000 0x2000000>;
};
partition@4000000 {
label = "aruba-ubifs";
reg = <0x4000000 0x4000000>;
read-only;
};
};
};
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "Aruba-AP-303";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "Aruba-AP-303";
};

280
root/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-gl-b1300.dts Normal file
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@ -0,0 +1,280 @@
/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "GL.iNet GL-B1300";
compatible = "glinet,gl-b1300";
aliases {
led-boot = &power;
led-failsafe = &power;
led-running = &power;
led-upgrade = &power;
};
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
reg = <0x194b000 0x100>;
qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
status = "okay";
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
usb2@60f8800 {
status = "okay";
};
usb3@8af8800 {
status = "okay";
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
switch_lan_bmp = <0x18>;
switch_wan_bmp = <0x20>;
};
edma@c080000 {
status = "okay";
};
};
keys {
compatible = "gpio-keys";
wps {
label = "wps";
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
reset {
label = "reset";
gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
power: power {
label = "green:power";
gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
mesh {
label = "green:mesh";
gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
};
wlan {
label = "green:wlan";
gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
};
};
};
&blsp_dma {
status = "okay";
};
&cryptobam {
status = "okay";
};
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
mx25l25635f@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
SBL1@0 {
label = "SBL1";
reg = <0x0 0x40000>;
read-only;
};
MIBIB@40000 {
label = "MIBIB";
reg = <0x40000 0x20000>;
read-only;
};
QSEE@60000 {
label = "QSEE";
reg = <0x60000 0x60000>;
read-only;
};
CDT@c0000 {
label = "CDT";
reg = <0xc0000 0x10000>;
read-only;
};
DDRPARAMS@d0000 {
label = "DDRPARAMS";
reg = <0xd0000 0x10000>;
read-only;
};
APPSBLENV@e0000 {
label = "APPSBLENV";
reg = <0xe0000 0x10000>;
read-only;
};
APPSBL@f0000 {
label = "APPSBL";
reg = <0xf0000 0x80000>;
read-only;
};
ART@170000 {
label = "ART";
reg = <0x170000 0x10000>;
read-only;
};
firmware@180000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x180000 0x1e80000>;
};
};
};
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "okay";
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
};
pinmux_cs {
function = "gpio";
pins = "gpio54";
};
pinconf {
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pinconf_cs {
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&usb2_hs_phy {
status = "okay";
};
&usb3_hs_phy {
status = "okay";
};
&usb3_ss_phy {
status = "okay";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "GL-B1300";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "GL-B1300";
};

189
root/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4019-l1000.dts → root/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-gl-s1300.dts Executable file → Normal file
View file

@ -1,8 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT
*
* Copyright (c) 2018 Peng Zhang <sd20@qxwlan.com>
*
*/
// SPDX-License-Identifier: GPL-2.0-only OR MIT
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
@ -10,31 +6,21 @@
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "GL.iNet GL-S1300";
compatible = "glinet,gl-s1300";
model = "GZ419";
compatible = "pangu,l1000", "qcom,ipq4019";
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
memory {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512MB */
reg = <0x80000000 0x10000000>;
};
aliases {
sdhc1 = &sdhci;
led-boot = &power;
led-failsafe = &power;
led-running = &power;
led-upgrade = &power;
serial0 = &blsp1_uart1;
serial1 = &blsp1_uart2;
};
chosen {
bootargs-append = " root=/dev/ubiblock0_1 rootfstype=squashfs";
linux,stdout-path = "serial0:115200n8";
};
soc {
rng@22000 {
status = "okay";
@ -42,10 +28,6 @@
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
reset-delay-us = <2000>;
};
ess-psgmii@98000 {
@ -100,13 +82,6 @@
switch_wan_bmp = <0x20>;
};
i2c@78b7000 { /* BLSP1 QUP2 */
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
status = "okay";
};
edma@c080000 {
status = "okay";
};
@ -115,6 +90,12 @@
keys {
compatible = "gpio-keys";
wps {
label = "wps";
gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
reset {
label = "reset";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
@ -125,43 +106,22 @@
leds {
compatible = "gpio-leds";
power: status {
label = "blue:status";
gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
led_power: power {
label = "green:power";
gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
wlan2g {
label = "blue:wlan2g";
gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
mesh {
label = "green:mesh";
gpios = <&tlmm 59 GPIO_ACTIVE_HIGH>;
};
wlan5g {
label = "bule:wlan5g";
gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
wlan {
label = "green:wlan";
gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tpt";
};
wan {
label = "bule:wan";
gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
};
4g1 {
label = "bule:4g1";
gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
};
4g2 {
label = "bule:4g2";
gpios = <&tlmm 45 GPIO_ACTIVE_LOW>;
};
4g3 {
label = "bule:4g3";
gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
};
usb {
label = "bule:usb";
gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
trigger-sources = <&usb2>, <&usb3>;
linux,default-trigger = "usbport";
};
};
};
@ -210,6 +170,7 @@
MIBIB@40000 {
label = "MIBIB";
reg = <0x40000 0x20000>;
read-only;
};
QSEE@60000 {
@ -233,44 +194,42 @@
APPSBLENV@e0000 {
label = "APPSBLENV";
reg = <0xe0000 0x10000>;
read-only;
};
APPSBL@f0000 {
label = "APPSBL";
reg = <0xf0000 0x80000>;
read-only;
};
ART@170000 {
label = "ART";
reg = <0x170000 0x10000>;
read-only;
};
firmware@180000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x180000 0xe80000>;
};
};
};
};
&nand {
pinctrl-0 = <&nand_pins>;
&blsp1_spi2 {
pinctrl-0 = <&spi_1_pins>;
pinctrl-names = "default";
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
rootfs@0 {
label = "rootfs";
reg = <0x0 0x8000000>;
};
};
spidev1: spi@0 {
compatible = "siliconlabs,si3210";
reg = <0>;
spi-max-frequency = <24000000>;
};
};
&qpic_bam {
status = "okay";
};
&blsp1_uart1 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
@ -292,19 +251,6 @@
};
};
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio6";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio7";
function = "mdc";
bias-pull-up;
};
};
serial_1_pins: serial1_pinmux {
mux {
pins = "gpio8", "gpio9",
@ -314,14 +260,6 @@
};
};
i2c_0_pins: i2c-0-pinmux {
mux {
pins = "gpio20", "gpio21";
function = "blsp_i2c0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pinmux {
function = "blsp_spi0";
@ -344,22 +282,31 @@
};
};
nand_pins: nand_pins {
pullups {
pins = "gpio52", "gpio53", "gpio58",
"gpio59";
function = "qpic";
spi_1_pins: spi_1_pinmux {
mux {
pins = "gpio44", "gpio46", "gpio47";
function = "blsp_spi1";
bias-disable;
};
host_int {
pins = "gpio42";
function = "gpio";
input;
};
cs {
pins = "gpio45";
function = "gpio";
bias-pull-up;
};
pulldowns {
pins = "gpio54", "gpio55", "gpio56",
"gpio57", "gpio60", "gpio61",
"gpio62", "gpio63", "gpio64",
"gpio65", "gpio66", "gpio67",
"gpio68", "gpio69";
function = "qpic";
bias-pull-down;
wake {
pins = "gpio40";
function = "gpio";
output-high;
};
reset {
pins = "gpio49";
function = "gpio";
output-high;
};
};
@ -400,10 +347,10 @@
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "PANGU-L1000";
qcom,ath10k-calibration-variant = "GL-S1300";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "PANGU-L1000";
qcom,ath10k-calibration-variant = "GL-S1300";
};

411
root/target/linux/ipq40xx/files/arch/arm/boot/dts/qcom-ipq4029-mr33.dts Normal file
View file

@ -0,0 +1,411 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree Source for Meraki MR33 (Stinkbug)
*
* Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
* Copyright (C) 2017 Christian Lamparter <chunkeey@googlemail.com>
*
* Based on Cisco Meraki DTS from GPL release r25-linux-3.14-20170427
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*/
#include "qcom-ipq4019.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
#include <dt-bindings/leds/common.h>
/ {
model = "Meraki MR33 Access Point";
compatible = "meraki,mr33";
aliases {
led-boot = &status_green;
led-failsafe = &status_red;
led-running = &status_green;
led-upgrade = &power_orange;
};
/* Do we really need this defined? */
memory {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
soc {
rng@22000 {
status = "okay";
};
mdio@90000 {
status = "okay";
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
};
/* It is a 56-bit counter that supplies the count to the ARM arch
timers and without upstream driver */
counter@4a1000 {
compatible = "qcom,qca-gcnt";
reg = <0x4a1000 0x4>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
serial@78b0000 {
pinctrl-0 = <&serial_1_pins>;
pinctrl-names = "default";
status = "okay";
bluetooth {
compatible = "ti,cc2650";
enable-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
};
};
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
ess-switch@c000000 {
switch_mac_mode = <0x3>; /* mac mode for RGMII RMII */
switch_lan_bmp = <0x0>; /* lan port bitmap */
switch_wan_bmp = <0x10>; /* wan port bitmap */
};
edma@c080000 {
qcom,single-phy;
qcom,num_gmac = <1>;
phy-mode = "rgmii-rxid";
status = "okay";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
power_orange: power {
label = "orange:power";
gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
panic-indicator;
};
};
};
&blsp_dma {
status = "okay";
};
&blsp1_uart1 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&cryptobam {
status = "okay";
};
&gmac0 {
qcom,phy_mdio_addr = <1>;
qcom,poll_required = <1>;
vlan_tag = <0 0x20>;
};
&blsp1_i2c3 {
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
status = "okay";
at24@50 {
compatible = "atmel,24c64";
pagesize = <32>;
reg = <0x50>;
read-only; /* This holds our MAC & Meraki board-data */
};
};
&blsp1_i2c4 {
pinctrl-0 = <&i2c_1_pins>;
pinctrl-names = "default";
status = "okay";
led-controller@30 {
compatible = "ti,lp5562";
reg = <0x30>;
clock-mode = /bits/8 <2>;
enable-gpio = <&tlmm 48 GPIO_ACTIVE_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
/* RGB led */
status_red: chan@0 {
chan-name = "red:status";
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;
reg = <0>;
color = <LED_COLOR_ID_RED>;
};
status_green: chan@1 {
chan-name = "green:status";
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
};
chan@2 {
chan-name = "blue:status";
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;
reg = <2>;
color = <LED_COLOR_ID_BLUE>;
};
chan@3 {
chan-name = "white:status";
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;
reg = <3>;
color = <LED_COLOR_ID_WHITE>;
};
};
};
&nand {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
status = "okay";
nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "sbl1";
reg = <0x00000000 0x00100000>;
read-only;
};
partition@100000 {
label = "mibib";
reg = <0x00100000 0x00100000>;
read-only;
};
partition@200000 {
label = "bootconfig";
reg = <0x00200000 0x00100000>;
read-only;
};
partition@300000 {
label = "qsee";
reg = <0x00300000 0x00100000>;
read-only;
};
partition@400000 {
label = "qsee_alt";
reg = <0x00400000 0x00100000>;
read-only;
};
partition@500000 {
label = "cdt";
reg = <0x00500000 0x00080000>;
read-only;
};
partition@580000 {
label = "cdt_alt";
reg = <0x00580000 0x00080000>;
read-only;
};
partition@600000 {
label = "ddrparams";
reg = <0x00600000 0x00080000>;
read-only;
};
partition@700000 {
label = "u-boot";
reg = <0x00700000 0x00200000>;
read-only;
};
partition@900000 {
label = "u-boot-backup";
reg = <0x00900000 0x00200000>;
read-only;
};
partition@b00000 {
label = "ART";
reg = <0x00b00000 0x00080000>;
read-only;
};
partition@c00000 {
label = "ubi";
reg = <0x00c00000 0x07000000>;
/*
* Do not try to allocate the remaining
* 4 MiB to this ubi partition. It will
* confuse the u-boot and it might not
* find the kernel partition anymore.
*/
};
};
};
};
&pcie0 {
status = "okay";
perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi2: wifi@1,0 {
compatible = "qcom,ath10k";
status = "okay";
reg = <0x00010000 0 0 0 0>;
};
};
};
&qpic_bam {
status = "okay";
};
&tlmm {
/*
* GPIO43 should be 0/1 whenever the unit is
* powered through PoE or AC-Adapter.
* That said, playing with this seems to
* reset the AP.
*/
mdio_pins: mdio_pinmux {
mux_1 {
pins = "gpio6";
function = "mdio";
bias-pull-up;
};
mux_2 {
pins = "gpio7";
function = "mdc";
bias-pull-up;
};
};
serial_0_pins: serial_pinmux {
mux {
pins = "gpio16", "gpio17";
function = "blsp_uart0";
bias-disable;
};
};
serial_1_pins: serial1_pinmux {
mux {
/* We use the i2c-0 pins for serial_1 */
pins = "gpio8", "gpio9";
function = "blsp_uart1";
bias-disable;
};
};
i2c_0_pins: i2c_0_pinmux {
pinmux {
function = "blsp_i2c0";
pins = "gpio20", "gpio21";
};
pinconf {
pins = "gpio20", "gpio21";
drive-strength = <16>;
bias-disable;
};
};
i2c_1_pins: i2c_1_pinmux {
pinmux {
function = "blsp_i2c1";
pins = "gpio34", "gpio35";
};
pinconf {
pins = "gpio34", "gpio35";
drive-strength = <16>;
bias-disable;
};
};
nand_pins: nand_pins {
/*
* There are 18 pins. 15 pins are common between LCD and NAND.
* The QPIC controller arbitrates between LCD and NAND. Of the
* remaining 4, 2 are for NAND and 2 are for LCD exclusively.
*
* The meraki source hints that the bluetooth module claims
* pin 52 as well. But sadly, there's no data whenever this
* is a NAND or LCD exclusive pin or not.
*/
pullups {
pins = "gpio52", "gpio53", "gpio58",
"gpio59";
function = "qpic";
bias-pull-up;
};
pulldowns {
pins = "gpio54", "gpio55", "gpio56",
"gpio57", "gpio60", "gpio61",
"gpio62", "gpio63", "gpio64",
"gpio65", "gpio66", "gpio67",
"gpio68", "gpio69";
function = "qpic";
bias-pull-down;
};
};
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "Meraki-MR33";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "Meraki-MR33";
};

99
root/target/linux/ipq40xx/patches-5.10/0001-v5.12-ARM-dts-qcom-ipq4019-add-USB-devicetree-nodes.patch Normal file
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From b8afc254b40167fd37b4d4263e750dab1f9ef157 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Wed, 9 Sep 2020 18:38:31 +0200
Subject: [PATCH] ARM: dts: qcom: ipq4019: add USB devicetree nodes
Since we now have driver for the USB PHY, and USB controller is already supported by the DWC3 driver lets add the necessary nodes to DTSI.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20200909163831.1894142-1-robert.marko@sartura.hr
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -605,5 +605,79 @@
reg = <4>;
};
};
+
+ usb3_ss_phy: ssphy@9a000 {
+ compatible = "qcom,usb-ss-ipq4019-phy";
+ #phy-cells = <0>;
+ reg = <0x9a000 0x800>;
+ reg-names = "phy_base";
+ resets = <&gcc USB3_UNIPHY_PHY_ARES>;
+ reset-names = "por_rst";
+ status = "disabled";
+ };
+
+ usb3_hs_phy: hsphy@a6000 {
+ compatible = "qcom,usb-hs-ipq4019-phy";
+ #phy-cells = <0>;
+ reg = <0xa6000 0x40>;
+ reg-names = "phy_base";
+ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
+ reset-names = "por_rst", "srif_rst";
+ status = "disabled";
+ };
+
+ usb3: usb3@8af8800 {
+ compatible = "qcom,dwc3";
+ reg = <0x8af8800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&gcc GCC_USB3_MASTER_CLK>,
+ <&gcc GCC_USB3_SLEEP_CLK>,
+ <&gcc GCC_USB3_MOCK_UTMI_CLK>;
+ clock-names = "master", "sleep", "mock_utmi";
+ ranges;
+ status = "disabled";
+
+ dwc3@8a00000 {
+ compatible = "snps,dwc3";
+ reg = <0x8a00000 0xf8000>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ dr_mode = "host";
+ };
+ };
+
+ usb2_hs_phy: hsphy@a8000 {
+ compatible = "qcom,usb-hs-ipq4019-phy";
+ #phy-cells = <0>;
+ reg = <0xa8000 0x40>;
+ reg-names = "phy_base";
+ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
+ reset-names = "por_rst", "srif_rst";
+ status = "disabled";
+ };
+
+ usb2: usb2@60f8800 {
+ compatible = "qcom,dwc3";
+ reg = <0x60f8800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&gcc GCC_USB2_MASTER_CLK>,
+ <&gcc GCC_USB2_SLEEP_CLK>,
+ <&gcc GCC_USB2_MOCK_UTMI_CLK>;
+ clock-names = "master", "sleep", "mock_utmi";
+ ranges;
+ status = "disabled";
+
+ dwc3@6000000 {
+ compatible = "snps,dwc3";
+ reg = <0x6000000 0xf8000>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb2_hs_phy>;
+ phy-names = "usb2-phy";
+ dr_mode = "host";
+ };
+ };
};
};

44
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From d1ae4c808e7802008225078d93fbadd4aeea1e2d Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Wed, 9 Sep 2020 21:56:37 +0200
Subject: [PATCH] ARM: dts: qcom: ipq4019: add more labels
Lets add labels to more commonly used nodes for easier modification in board DTS files.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Link: https://lore.kernel.org/r/20200909195640.3127341-2-robert.marko@sartura.hr
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -190,7 +190,7 @@
reg = <0x1800000 0x60000>;
};
- rng@22000 {
+ prng: rng@22000 {
compatible = "qcom,prng";
reg = <0x22000 0x140>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
@@ -300,7 +300,7 @@
status = "disabled";
};
- crypto@8e3a000 {
+ crypto: crypto@8e3a000 {
compatible = "qcom,crypto-v5.1";
reg = <0x08e3a000 0x6000>;
clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
@@ -386,7 +386,7 @@
dma-names = "rx", "tx";
};
- watchdog@b017000 {
+ watchdog: watchdog@b017000 {
compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
reg = <0xb017000 0x40>;
clocks = <&sleep_clk>;

35
root/target/linux/ipq40xx/patches-5.10/0003-v5.12-ARM-dts-qcom-ipq4019-add-SDHCI-VQMMC-LDO-node.patch Normal file
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@ -0,0 +1,35 @@
From e14775aa2feac18e7378cb8009b55c13d4236b50 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Mon, 7 Sep 2020 12:19:37 +0200
Subject: [PATCH] ARM: dts: qcom: ipq4019: add SDHCI VQMMC LDO node
Since we now have driver for the SDHCI VQMMC LDO needed
for I/0 voltage levels lets introduce the necessary node for it.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Link: https://lore.kernel.org/r/20200907101937.10155-1-robert.marko@sartura.hr
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -209,6 +209,16 @@
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
};
+ vqmmc: regulator@1948000 {
+ compatible = "qcom,vqmmc-ipq4019-regulator";
+ reg = <0x01948000 0x4>;
+ regulator-name = "vqmmc";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-always-on;
+ status = "disabled";
+ };
+
sdhci: sdhci@7824900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x7824900 0x11c>, <0x7824000 0x800>;

115
root/target/linux/ipq40xx/patches-5.10/104-clk-fix-apss-cpu-overclocking.patch Normal file
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From f2b87dc1028b710ec8ce25808b9d21f92b376184 Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@googlemail.com>
Date: Sun, 11 Mar 2018 14:41:31 +0100
Subject: [PATCH 2/2] clk: fix apss cpu overclocking
There's an interaction issue between the clk changes:"
clk: qcom: ipq4019: Add the apss cpu pll divider clock node
clk: qcom: ipq4019: remove fixed clocks and add pll clocks
" and the cpufreq-dt.
cpufreq-dt is now spamming the kernel-log with the following:
[ 1099.190658] cpu cpu0: dev_pm_opp_set_rate: failed to find current OPP
for freq 761142857 (-34)
This only happens on certain devices like the Compex WPJ428
and AVM FritzBox!4040. However, other devices like the Asus
RT-AC58U and Meraki MR33 work just fine.
The issue stem from the fact that all higher CPU-Clocks
are achieved by switching the clock-parent to the P_DDRPLLAPSS
(ddrpllapss). Which is set by Qualcomm's proprietary bootcode
as part of the DDR calibration.
For example, the FB4040 uses 256 MiB Nanya NT5CC128M16IP clocked
at round 533 MHz (ddrpllsdcc = 190285714 Hz).
whereas the 128 MiB Nanya NT5CC64M16GP-DI in the ASUS RT-AC58U is
clocked at a slightly higher 537 MHz ( ddrpllsdcc = 192000000 Hz).
This patch attempts to fix the issue by modifying
clk_cpu_div_round_rate(), clk_cpu_div_set_rate(), clk_cpu_div_recalc_rate()
to use a new qcom_find_freq_close() function, which returns the closest
matching frequency, instead of the next higher. This way, the SoC in
the FB4040 (with its max clock speed of 710.4 MHz) will no longer
try to overclock to 761 MHz.
Fixes: d83dcacea18 ("clk: qcom: ipq4019: Add the apss cpu pll divider clock node")
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/clk/qcom/gcc-ipq4019.c | 34 +++++++++++++++++++++++++++++++---
1 file changed, 31 insertions(+), 3 deletions(-)
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -1243,6 +1243,29 @@ static const struct clk_fepll_vco gcc_fe
.reg = 0x2f020,
};
+
+const struct freq_tbl *qcom_find_freq_close(const struct freq_tbl *f,
+ unsigned long rate)
+{
+ const struct freq_tbl *last = NULL;
+
+ for ( ; f->freq; f++) {
+ if (rate == f->freq)
+ return f;
+
+ if (f->freq > rate) {
+ if (!last ||
+ (f->freq - rate) < (rate - last->freq))
+ return f;
+ else
+ return last;
+ }
+ last = f;
+ }
+
+ return last;
+}
+
/*
* Round rate function for APSS CPU PLL Clock divider.
* It looks up the frequency table and returns the next higher frequency
@@ -1255,7 +1278,7 @@ static long clk_cpu_div_round_rate(struc
struct clk_hw *p_hw;
const struct freq_tbl *f;
- f = qcom_find_freq(pll->freq_tbl, rate);
+ f = qcom_find_freq_close(pll->freq_tbl, rate);
if (!f)
return -EINVAL;
@@ -1278,7 +1301,7 @@ static int clk_cpu_div_set_rate(struct c
u32 mask;
int ret;
- f = qcom_find_freq(pll->freq_tbl, rate);
+ f = qcom_find_freq_close(pll->freq_tbl, rate);
if (!f)
return -EINVAL;
@@ -1305,6 +1328,7 @@ static unsigned long
clk_cpu_div_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
+ const struct freq_tbl *f;
struct clk_fepll *pll = to_clk_fepll(hw);
u32 cdiv, pre_div;
u64 rate;
@@ -1325,7 +1349,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h
rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2;
do_div(rate, pre_div);
- return rate;
+ f = qcom_find_freq_close(pll->freq_tbl, rate);
+ if (!f)
+ return rate;
+
+ return f->freq;
};
static const struct clk_ops clk_regmap_cpu_div_ops = {

26
root/target/linux/ipq40xx/patches-5.10/105-ipq40xx-fix-sleep-clock.patch Normal file
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@ -0,0 +1,26 @@
From a63c7162a1dae9f1185897641dc3e47e295563d6 Mon Sep 17 00:00:00 2001
From: Pavel Kubelun <be.dissent@gmail.com>
Date: Mon, 6 May 2019 20:55:16 +0300
Subject: [PATCH] ARM: dts: qcom: ipq4019: fix sleep clock
It seems like sleep_clk was copied from ipq806x.
Fix ipq40xx sleep_clk to the value QSDK defines.
Link: https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-msm/commit/?id=d92ec59973484acc86dd24b67f10f8911b4b4b7d
Link: https://patchwork.kernel.org/comment/22721613/
Suggested-by: Bjorn Andersson <bjorn.andersson@linaro.org> [clock-output-names]
Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com> [just fixed the value]
---
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -142,7 +142,8 @@
clocks {
sleep_clk: sleep_clk {
compatible = "fixed-clock";
- clock-frequency = <32768>;
+ clock-frequency = <32000>;
+ clock-output-names = "gcc_sleep_clk_src";
#clock-cells = <0>;
};

52
root/target/linux/ipq40xx/patches-5.10/300-clk-qcom-ipq4019-add-ess-reset.patch Normal file
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@ -0,0 +1,52 @@
From 480c1f7648fc586db12d6003c717c23667a4fcf0 Mon Sep 17 00:00:00 2001
From: Ram Chandra Jangir <rjangir@codeaurora.org>
Date: Tue, 28 Mar 2017 22:35:33 +0530
Subject: [PATCH] clk: qcom: ipq4019: add ess reset
Added the ESS reset in IPQ4019 GCC.
Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
---
drivers/clk/qcom/gcc-ipq4019.c | 11 +++++++++++
include/dt-bindings/clock/qcom,gcc-ipq4019.h | 11 +++++++++++
2 files changed, 22 insertions(+)
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -1736,6 +1736,17 @@ static const struct qcom_reset_map gcc_i
[GCC_TCSR_BCR] = {0x22000, 0},
[GCC_MPM_BCR] = {0x24000, 0},
[GCC_SPDM_BCR] = {0x25000, 0},
+ [ESS_MAC1_ARES] = {0x1200C, 0},
+ [ESS_MAC2_ARES] = {0x1200C, 1},
+ [ESS_MAC3_ARES] = {0x1200C, 2},
+ [ESS_MAC4_ARES] = {0x1200C, 3},
+ [ESS_MAC5_ARES] = {0x1200C, 4},
+ [ESS_PSGMII_ARES] = {0x1200C, 5},
+ [ESS_MAC1_CLK_DIS] = {0x1200C, 8},
+ [ESS_MAC2_CLK_DIS] = {0x1200C, 9},
+ [ESS_MAC3_CLK_DIS] = {0x1200C, 10},
+ [ESS_MAC4_CLK_DIS] = {0x1200C, 11},
+ [ESS_MAC5_CLK_DIS] = {0x1200C, 12},
};
static const struct regmap_config gcc_ipq4019_regmap_config = {
--- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h
+++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h
@@ -165,5 +165,16 @@
#define GCC_QDSS_BCR 69
#define GCC_MPM_BCR 70
#define GCC_SPDM_BCR 71
+#define ESS_MAC1_ARES 72
+#define ESS_MAC2_ARES 73
+#define ESS_MAC3_ARES 74
+#define ESS_MAC4_ARES 75
+#define ESS_MAC5_ARES 76
+#define ESS_PSGMII_ARES 77
+#define ESS_MAC1_CLK_DIS 78
+#define ESS_MAC2_CLK_DIS 79
+#define ESS_MAC3_CLK_DIS 80
+#define ESS_MAC4_CLK_DIS 81
+#define ESS_MAC5_CLK_DIS 82
#endif

48
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@ -0,0 +1,48 @@
From 0843a61d6913bdac8889eb048ed89f7903059787 Mon Sep 17 00:00:00 2001
From: Robert Marko <robimarko@gmail.com>
Date: Fri, 30 Oct 2020 13:36:31 +0100
Subject: [PATCH] arm: compressed: add appended DTB section
This adds a appended_dtb section to the ARM decompressor
linker script.
This allows using the existing ARM zImage appended DTB support for
appending a DTB to the raw ELF kernel.
Its size is set to 1MB max to match the zImage appended DTB size limit.
To use it to pass the DTB to the kernel, objcopy is used:
objcopy --set-section-flags=.appended_dtb=alloc,contents \
--update-section=.appended_dtb=<target>.dtb vmlinux
This is based off the following patch:
https://github.com/openwrt/openwrt/commit/c063e27e02a9dcac0e7f5877fb154e58fa3e1a69
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
arch/arm/boot/compressed/vmlinux.lds.S | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
--- a/arch/arm/boot/compressed/vmlinux.lds.S
+++ b/arch/arm/boot/compressed/vmlinux.lds.S
@@ -101,6 +101,13 @@ SECTIONS
_edata = .;
+ .appended_dtb : {
+ /* leave space for appended DTB */
+ . += 0x100000;
+ }
+
+ _edata_dtb = .;
+
/*
* The image_end section appears after any additional loadable sections
* that the linker may decide to insert in the binary image. Having
@@ -138,4 +145,4 @@ SECTIONS
ARM_ASSERTS
}
-ASSERT(_edata_real == _edata, "error: zImage file size is incorrect");
+ASSERT(_edata_real == _edata_dtb, "error: zImage file size is incorrect");

66
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From 11d6a6128a5a07c429941afc202b6e62a19771be Mon Sep 17 00:00:00 2001
From: John Thomson <git@johnthomson.fastmail.com.au>
Date: Fri, 23 Oct 2020 19:42:36 +1000
Subject: [PATCH 2/2] arm: compressed: set ipq40xx watchdog to allow boot
For IPQ40XX systems where the SoC watchdog is activated before linux,
the watchdog timer may be too small for linux to finish uncompress,
boot, and watchdog management start.
If the watchdog is enabled, set the timeout for it to 30 seconds.
The functionality and offsets were copied from:
drivers/watchdog/qcom-wdt.c qcom_wdt_set_timeout & qcom_wdt_start
The watchdog memory address was taken from:
arch/arm/boot/dts/qcom-ipq4019.dtsi
This was required on Mikrotik IPQ40XX consumer hardware using Mikrotik's
RouterBoot bootloader.
Signed-off-by: John Thomson <git@johnthomson.fastmail.com.au>
---
arch/arm/boot/compressed/head.S | 35 +++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -601,6 +601,41 @@ not_relocated: mov r0, #0
bic r4, r4, #1
blne cache_on
+/* Set the Qualcom IPQ40xx watchdog timeout to 30 seconds
+ * if it is enabled, so that there is time for kernel
+ * to decompress, boot, and take over the watchdog.
+ * data and functionality from drivers/watchdog/qcom-wdt.c
+ * address from arch/arm/boot/dts/qcom-ipq4019.dtsi
+ */
+#ifdef CONFIG_ARCH_IPQ40XX
+watchdog_set:
+ /* offsets:
+ * 0x04 reset (=1 resets countdown)
+ * 0x08 enable (=0 disables)
+ * 0x0c status (=1 when SoC was reset by watchdog)
+ * 0x10 bark (=timeout warning in ticks)
+ * 0x14 bite (=timeout reset in ticks)
+ * clock rate is 1<<15 hertz
+ */
+ .equ watchdog, 0x0b017000 @Store watchdog base address
+ movw r0, #:lower16:watchdog
+ movt r0, #:upper16:watchdog
+ ldr r1, [r0, #0x08] @Get enabled?
+ cmp r1, #1 @If not enabled, do not change
+ bne watchdog_finished
+ mov r1, #0
+ str r1, [r0, #0x08] @Disable the watchdog
+ mov r1, #1
+ str r1, [r0, #0x04] @Pet the watchdog
+ mov r1, #30 @30 seconds timeout
+ lsl r1, r1, #15 @converted to ticks
+ str r1, [r0, #0x10] @Set the bark timeout
+ str r1, [r0, #0x14] @Set the bite timeout
+ mov r1, #1
+ str r1, [r0, #0x08] @Enable the watchdog
+watchdog_finished:
+#endif /* CONFIG_ARCH_IPQ40XX */
+
/*
* The C runtime environment should now be setup sufficiently.
* Set up some pointers, and start decompressing.

24
root/target/linux/ipq40xx/patches-5.10/400-mmc-sdhci-sdhci-msm-use-sdhci_set_clock-instead-of-s.patch Normal file
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@ -0,0 +1,24 @@
From f63ea127643a605da97090ce585fdd7c2d17fa42 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Mon, 14 Dec 2020 13:35:35 +0100
Subject: [PATCH] mmc: sdhci-msm: use sdhci_set_clock
When using sdhci_msm_set_clock clock setting will fail, so lets
use the generic sdhci_set_clock.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
drivers/mmc/host/sdhci-msm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -2191,7 +2191,7 @@ MODULE_DEVICE_TABLE(of, sdhci_msm_dt_mat
static const struct sdhci_ops sdhci_msm_ops = {
.reset = sdhci_msm_reset,
- .set_clock = sdhci_msm_set_clock,
+ .set_clock = sdhci_set_clock,
.get_min_clock = sdhci_msm_get_min_clock,
.get_max_clock = sdhci_msm_get_max_clock,
.set_bus_width = sdhci_set_bus_width,

46
root/target/linux/ipq40xx/patches-5.10/702-dts-ipq4019-add-PHY-switch-nodes.patch Normal file
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@ -0,0 +1,46 @@
From 9deeec35dd3b628b95624e41d4e04acf728991ba Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@gmail.com>
Date: Sun, 20 Nov 2016 02:20:54 +0100
Subject: [PATCH] dts: ipq4019: add PHY/switch nodes
This patch adds both the "qcom,ess-switch" and "qcom,ess-psgmii"
nodes which are needed for the ar40xx.c driver to initialize the
switch.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -617,6 +617,29 @@
};
};
+ ess-switch@c000000 {
+ compatible = "qcom,ess-switch";
+ reg = <0xc000000 0x80000>;
+ switch_access_mode = "local bus";
+ resets = <&gcc ESS_RESET>;
+ reset-names = "ess_rst";
+ clocks = <&gcc GCC_ESS_CLK>;
+ clock-names = "ess_clk";
+ switch_cpu_bmp = <0x1>;
+ switch_lan_bmp = <0x1e>;
+ switch_wan_bmp = <0x20>;
+ switch_mac_mode = <0>; /* PORT_WRAPPER_PSGMII */
+ switch_initvlas = <0x7c 0x54>;
+ status = "disabled";
+ };
+
+ ess-psgmii@98000 {
+ compatible = "qcom,ess-psgmii";
+ reg = <0x98000 0x800>;
+ psgmii_access_mode = "local bus";
+ status = "disabled";
+ };
+
usb3_ss_phy: ssphy@9a000 {
compatible = "qcom,usb-ss-ipq4019-phy";
#phy-cells = <0>;

53
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@ -0,0 +1,53 @@
From 7c129254adb1093d10a62ed7bf7b956fcc6ffe34 Mon Sep 17 00:00:00 2001
From: Rakesh Nair <ranair@codeaurora.org>
Date: Wed, 20 Jul 2016 15:02:01 +0530
Subject: [PATCH] net: IPQ4019 needs rfs/vlan_tag callbacks in
netdev_ops
Add callback support to get default vlan tag and register
receive flow steering filter.
Used by IPQ4019 ess-edma driver.
BUG=chrome-os-partner:33096
TEST=none
Change-Id: I266070e4a0fbe4a0d9966fe79a71e50ec4f26c75
Signed-off-by: Rakesh Nair <ranair@codeaurora.org>
Reviewed-on: https://chromium-review.googlesource.com/362203
Commit-Ready: Grant Grundler <grundler@chromium.org>
Tested-by: Grant Grundler <grundler@chromium.org>
Reviewed-by: Grant Grundler <grundler@chromium.org>
---
include/linux/netdevice.h | 13 +++++++++++++
1 file changed, 13 insertions(+)
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -765,6 +765,16 @@ struct xps_map {
#define XPS_MIN_MAP_ALLOC ((L1_CACHE_ALIGN(offsetof(struct xps_map, queues[1])) \
- sizeof(struct xps_map)) / sizeof(u16))
+#ifdef CONFIG_RFS_ACCEL
+typedef int (*set_rfs_filter_callback_t)(struct net_device *dev,
+ __be32 src,
+ __be32 dst,
+ __be16 sport,
+ __be16 dport,
+ u8 proto,
+ u16 rxq_index,
+ u32 action);
+#endif
/*
* This structure holds all XPS maps for device. Maps are indexed by CPU.
*/
@@ -1445,6 +1455,9 @@ struct net_device_ops {
const struct sk_buff *skb,
u16 rxq_index,
u32 flow_id);
+ int (*ndo_register_rfs_filter)(struct net_device *dev,
+ set_rfs_filter_callback_t set_filter);
+ int (*ndo_get_default_vlan_tag)(struct net_device *net);
#endif
int (*ndo_add_slave)(struct net_device *dev,
struct net_device *slave_dev,

27
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@ -0,0 +1,27 @@
--- a/drivers/net/mdio/Kconfig
+++ b/drivers/net/mdio/Kconfig
@@ -27,6 +27,13 @@ config OF_MDIO
help
OpenFirmware MDIO bus (Ethernet PHY) accessors
+config AR40XX_PHY
+ tristate "Driver for Qualcomm Atheros IPQ40XX switches"
+ depends on HAS_IOMEM && OF && OF_MDIO
+ select SWCONFIG
+ help
+ This is the driver for Qualcomm Atheros IPQ40XX ESS switches.
+
if MDIO_BUS
config MDIO_DEVRES
--- a/drivers/net/mdio/Makefile
+++ b/drivers/net/mdio/Makefile
@@ -21,6 +21,8 @@ obj-$(CONFIG_MDIO_SUN4I) += mdio-sun4i.
obj-$(CONFIG_MDIO_THUNDER) += mdio-thunder.o
obj-$(CONFIG_MDIO_XGENE) += mdio-xgene.o
+obj-$(CONFIG_AR40XX_PHY) += ar40xx.o
+
obj-$(CONFIG_MDIO_BUS_MUX) += mdio-mux.o
obj-$(CONFIG_MDIO_BUS_MUX_BCM_IPROC) += mdio-mux-bcm-iproc.o
obj-$(CONFIG_MDIO_BUS_MUX_GPIO) += mdio-mux-gpio.o

61
root/target/linux/ipq40xx/patches-5.10/706-dt-bindings-net-add-QCA807x-PHY.patch Normal file
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@ -0,0 +1,61 @@
From c66863c1ba8995b61e6d727d78a241c734f5bb57 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Thu, 1 Oct 2020 15:05:35 +0200
Subject: [PATCH] dt-bindings: net: add QCA807x PHY
Add DT bindings for Qualcomm QCA807x PHY series.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
include/dt-bindings/net/qcom-qca807x.h | 45 ++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
create mode 100644 include/dt-bindings/net/qcom-qca807x.h
--- /dev/null
+++ b/include/dt-bindings/net/qcom-qca807x.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Device Tree constants for the Qualcomm QCA807X PHYs
+ */
+
+#ifndef _DT_BINDINGS_QCOM_QCA807X_H
+#define _DT_BINDINGS_QCOM_QCA807X_H
+
+#define PSGMII_QSGMII_TX_DRIVER_140MV 0
+#define PSGMII_QSGMII_TX_DRIVER_160MV 1
+#define PSGMII_QSGMII_TX_DRIVER_180MV 2
+#define PSGMII_QSGMII_TX_DRIVER_200MV 3
+#define PSGMII_QSGMII_TX_DRIVER_220MV 4
+#define PSGMII_QSGMII_TX_DRIVER_240MV 5
+#define PSGMII_QSGMII_TX_DRIVER_260MV 6
+#define PSGMII_QSGMII_TX_DRIVER_280MV 7
+#define PSGMII_QSGMII_TX_DRIVER_300MV 8
+#define PSGMII_QSGMII_TX_DRIVER_320MV 9
+#define PSGMII_QSGMII_TX_DRIVER_400MV 10
+#define PSGMII_QSGMII_TX_DRIVER_500MV 11
+/* Default value */
+#define PSGMII_QSGMII_TX_DRIVER_600MV 12
+
+/* Full amplitude, full bias current */
+#define QCA807X_CONTROL_DAC_FULL_VOLT_BIAS 0
+/* Amplitude follow DSP (amplitude is adjusted based on cable length), half bias current */
+#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS 1
+/* Full amplitude, bias current follow DSP (bias current is adjusted based on cable length) */
+#define QCA807X_CONTROL_DAC_FULL_VOLT_DSP_BIAS 2
+/* Both amplitude and bias current follow DSP */
+#define QCA807X_CONTROL_DAC_DSP_VOLT_BIAS 3
+/* Full amplitude, half bias current */
+#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS 4
+/* Amplitude follow DSP setting; 1/4 bias current when cable<10m,
+ * otherwise half bias current
+ */
+#define QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS 5
+/* Full amplitude; same bias current setting with “010” and “011”,
+ * but half more bias is reduced when cable <10m
+ */
+#define QCA807X_CONTROL_DAC_FULL_VOLT_HALF_BIAS_SHORT 6
+/* Amplitude follow DSP; same bias current setting with “110”, default value */
+#define QCA807X_CONTROL_DAC_DSP_VOLT_HALF_BIAS_SHORT 7
+
+#endif

50
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@ -0,0 +1,50 @@
From f825cdc8bfde7616a14e2163f16303a8973031d2 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Wed, 7 Oct 2020 17:38:48 +0200
Subject: [PATCH] net: phy: Add Qualcom QCA807x driver
This adds driver for the Qualcomm QCA8072 and QCA8075 PHY-s.
They are 2 or 5 port IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and 1000BASE-T PHY-s.
They feature 2 SerDes, one for PSGMII or QSGMII connection with MAC, while second one is SGMII for connection to MAC or fiber.
Both models have a combo port that supports 1000BASE-X and 100BASE-FX fiber.
Each PHY inside of QCA807x series has 4 digitally controlled output only pins that natively drive LED-s.
But some vendors used these to driver generic LED-s controlled by userspace,
so lets enable registering each PHY as GPIO controller and add driver for it.
These are commonly used in Qualcomm IPQ40xx, IPQ60xx and IPQ807x boards.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
drivers/net/phy/Kconfig | 6 ++++++
drivers/net/phy/Makefile | 1 +
2 files changed, 7 insertions(+)
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -315,6 +315,12 @@ config AT803X_PHY
Currently supports the AR8030, AR8031, AR8033, AR8035 and internal
QCA8337(Internal qca8k PHY) model
+config QCA807X_PHY
+ tristate "Qualcomm QCA807X PHYs"
+ depends on OF_MDIO
+ help
+ Currently supports the QCA8072 and QCA8075 models.
+
config QSEMI_PHY
tristate "Quality Semiconductor PHYs"
help
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -85,6 +85,7 @@ obj-$(CONFIG_MICROSEMI_PHY) += mscc/
obj-$(CONFIG_NATIONAL_PHY) += national.o
obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o
obj-$(CONFIG_QSEMI_PHY) += qsemi.o
+obj-$(CONFIG_QCA807X_PHY) += qca807x.o
obj-$(CONFIG_REALTEK_PHY) += realtek.o
obj-$(CONFIG_RENESAS_PHY) += uPD60620.o
obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o

62
root/target/linux/ipq40xx/patches-5.10/708-arm-dts-ipq4019-QCA807x-properties.patch Normal file
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@ -0,0 +1,62 @@
From e0fa88eaa3c176b71e563da68949ac2ab45aaa61 Mon Sep 17 00:00:00 2001
From: Robert Marko <robert.marko@sartura.hr>
Date: Fri, 2 Oct 2020 10:43:26 +0200
Subject: [PATCH] arm: dts: ipq4019: QCA807x properties
This adds necessary DT properties for QCA807x PHY-s to IPQ4019 DTSI.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/net/qcom-qca807x.h>
/ {
#address-cells = <1>;
@@ -598,22 +599,39 @@
ethphy0: ethernet-phy@0 {
reg = <0>;
+
+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
};
ethphy1: ethernet-phy@1 {
reg = <1>;
+
+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
};
ethphy2: ethernet-phy@2 {
reg = <2>;
+
+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
};
ethphy3: ethernet-phy@3 {
reg = <3>;
+
+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
};
ethphy4: ethernet-phy@4 {
reg = <4>;
+
+ qcom,control-dac = <QCA807X_CONTROL_DAC_DSP_VOLT_QUARTER_BIAS>;
+ };
+
+ psgmiiphy: psgmii-phy@5 {
+ reg = <5>;
+
+ qcom,tx-driver-strength = <PSGMII_QSGMII_TX_DRIVER_300MV>;
+ qcom,psgmii-az;
};
};

37
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@ -0,0 +1,37 @@
From 12e9319da1adacac92930c899c99f0e1970cac11 Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@googlemail.com>
Date: Thu, 19 Jan 2017 02:01:31 +0100
Subject: [PATCH 33/38] NET: add qualcomm essedma ethernet driver
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
drivers/net/ethernet/qualcomm/Kconfig | 9 +++++++++
drivers/net/ethernet/qualcomm/Makefile | 1 +
2 files changed, 10 insertions(+)
--- a/drivers/net/ethernet/qualcomm/Kconfig
+++ b/drivers/net/ethernet/qualcomm/Kconfig
@@ -62,4 +62,14 @@ config QCOM_EMAC
source "drivers/net/ethernet/qualcomm/rmnet/Kconfig"
+config ESSEDMA
+ tristate "Qualcomm Atheros ESS Edma support"
+ depends on OF_MDIO
+ help
+ This driver supports ethernet edma adapter.
+ Say Y to build this driver.
+
+ To compile this driver as a module, choose M here. The module
+ will be called essedma.ko.
+
endif # NET_VENDOR_QUALCOMM
--- a/drivers/net/ethernet/qualcomm/Makefile
+++ b/drivers/net/ethernet/qualcomm/Makefile
@@ -10,5 +10,6 @@ obj-$(CONFIG_QCA7000_UART) += qcauart.o
qcauart-objs := qca_uart.o
obj-y += emac/
+obj-$(CONFIG_ESSEDMA) += essedma/
obj-$(CONFIG_RMNET) += rmnet/

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@ -0,0 +1,92 @@
From c611d3780fa101662a822d10acf8feb04ca97409 Mon Sep 17 00:00:00 2001
From: Christian Lamparter <chunkeey@gmail.com>
Date: Sun, 20 Nov 2016 01:01:10 +0100
Subject: [PATCH] dts: ipq4019: add ethernet essedma node
This patch adds the device-tree node for the ethernet
interfaces.
Note: The driver isn't anywhere close to be upstream,
so the info might change.
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 60 +++++++++++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -39,6 +39,8 @@
spi1 = &blsp1_spi2;
i2c0 = &blsp1_i2c3;
i2c1 = &blsp1_i2c4;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
};
cpus {
@@ -658,6 +660,64 @@
status = "disabled";
};
+ edma@c080000 {
+ compatible = "qcom,ess-edma";
+ reg = <0xc080000 0x8000>;
+ qcom,page-mode = <0>;
+ qcom,rx_head_buf_size = <1540>;
+ qcom,mdio_supported;
+ qcom,poll_required = <1>;
+ qcom,num_gmac = <2>;
+ interrupts = <0 65 IRQ_TYPE_EDGE_RISING
+ 0 66 IRQ_TYPE_EDGE_RISING
+ 0 67 IRQ_TYPE_EDGE_RISING
+ 0 68 IRQ_TYPE_EDGE_RISING
+ 0 69 IRQ_TYPE_EDGE_RISING
+ 0 70 IRQ_TYPE_EDGE_RISING
+ 0 71 IRQ_TYPE_EDGE_RISING
+ 0 72 IRQ_TYPE_EDGE_RISING
+ 0 73 IRQ_TYPE_EDGE_RISING
+ 0 74 IRQ_TYPE_EDGE_RISING
+ 0 75 IRQ_TYPE_EDGE_RISING
+ 0 76 IRQ_TYPE_EDGE_RISING
+ 0 77 IRQ_TYPE_EDGE_RISING
+ 0 78 IRQ_TYPE_EDGE_RISING
+ 0 79 IRQ_TYPE_EDGE_RISING
+ 0 80 IRQ_TYPE_EDGE_RISING
+ 0 240 IRQ_TYPE_EDGE_RISING
+ 0 241 IRQ_TYPE_EDGE_RISING
+ 0 242 IRQ_TYPE_EDGE_RISING
+ 0 243 IRQ_TYPE_EDGE_RISING
+ 0 244 IRQ_TYPE_EDGE_RISING
+ 0 245 IRQ_TYPE_EDGE_RISING
+ 0 246 IRQ_TYPE_EDGE_RISING
+ 0 247 IRQ_TYPE_EDGE_RISING
+ 0 248 IRQ_TYPE_EDGE_RISING
+ 0 249 IRQ_TYPE_EDGE_RISING
+ 0 250 IRQ_TYPE_EDGE_RISING
+ 0 251 IRQ_TYPE_EDGE_RISING
+ 0 252 IRQ_TYPE_EDGE_RISING
+ 0 253 IRQ_TYPE_EDGE_RISING
+ 0 254 IRQ_TYPE_EDGE_RISING
+ 0 255 IRQ_TYPE_EDGE_RISING>;
+
+ status = "disabled";
+
+ gmac0: gmac0 {
+ local-mac-address = [00 00 00 00 00 00];
+ vlan_tag = <1 0x1f>;
+ };
+
+ gmac1: gmac1 {
+ local-mac-address = [00 00 00 00 00 00];
+ qcom,phy_mdio_addr = <4>;
+ qcom,poll_required = <1>;
+ qcom,forced_speed = <1000>;
+ qcom,forced_duplex = <1>;
+ vlan_tag = <2 0x20>;
+ };
+ };
+
usb3_ss_phy: ssphy@9a000 {
compatible = "qcom,usb-ss-ipq4019-phy";
#phy-cells = <0>;

180
root/target/linux/ipq40xx/patches-5.10/850-soc-add-qualcomm-syscon.patch Normal file
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@ -0,0 +1,180 @@
From: Christian Lamparter <chunkeey@googlemail.com>
Subject: SoC: add qualcomm syscon
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_QCOM_SMP2P) += smp2p.o
obj-$(CONFIG_QCOM_SMSM) += smsm.o
obj-$(CONFIG_QCOM_SOCINFO) += socinfo.o
obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o
+obj-$(CONFIG_QCOM_TCSR) += qcom_tcsr.o
obj-$(CONFIG_QCOM_APR) += apr.o
obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -189,6 +189,13 @@ config QCOM_SOCINFO
Say yes here to support the Qualcomm socinfo driver, providing
information about the SoC to user space.
+config QCOM_TCSR
+ tristate "QCOM Top Control and Status Registers"
+ depends on ARCH_QCOM
+ help
+ Say y here to enable TCSR support. The TCSR provides control
+ functions for various peripherals.
+
config QCOM_WCNSS_CTRL
tristate "Qualcomm WCNSS control driver"
depends on ARCH_QCOM || COMPILE_TEST
--- /dev/null
+++ b/drivers/soc/qcom/qcom_tcsr.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2014, The Linux foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License rev 2 and
+ * only rev 2 as published by the free Software foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+
+#define TCSR_USB_PORT_SEL 0xb0
+#define TCSR_USB_HSPHY_CONFIG 0xC
+
+#define TCSR_ESS_INTERFACE_SEL_OFFSET 0x0
+#define TCSR_ESS_INTERFACE_SEL_MASK 0xf
+
+#define TCSR_WIFI0_GLB_CFG_OFFSET 0x0
+#define TCSR_WIFI1_GLB_CFG_OFFSET 0x4
+#define TCSR_PNOC_SNOC_MEMTYPE_M0_M2 0x4
+
+static int tcsr_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ const struct device_node *node = pdev->dev.of_node;
+ void __iomem *base;
+ u32 val;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) {
+ dev_err(&pdev->dev, "setting usb port select = %d\n", val);
+ writel(val, base + TCSR_USB_PORT_SEL);
+ }
+
+ if (!of_property_read_u32(node, "qcom,usb-hsphy-mode-select", &val)) {
+ dev_info(&pdev->dev, "setting usb hs phy mode select = %x\n", val);
+ writel(val, base + TCSR_USB_HSPHY_CONFIG);
+ }
+
+ if (!of_property_read_u32(node, "qcom,ess-interface-select", &val)) {
+ u32 tmp = 0;
+ dev_info(&pdev->dev, "setting ess interface select = %x\n", val);
+ tmp = readl(base + TCSR_ESS_INTERFACE_SEL_OFFSET);
+ tmp = tmp & (~TCSR_ESS_INTERFACE_SEL_MASK);
+ tmp = tmp | (val&TCSR_ESS_INTERFACE_SEL_MASK);
+ writel(tmp, base + TCSR_ESS_INTERFACE_SEL_OFFSET);
+ }
+
+ if (!of_property_read_u32(node, "qcom,wifi_glb_cfg", &val)) {
+ dev_info(&pdev->dev, "setting wifi_glb_cfg = %x\n", val);
+ writel(val, base + TCSR_WIFI0_GLB_CFG_OFFSET);
+ writel(val, base + TCSR_WIFI1_GLB_CFG_OFFSET);
+ }
+
+ if (!of_property_read_u32(node, "qcom,wifi_noc_memtype_m0_m2", &val)) {
+ dev_info(&pdev->dev,
+ "setting wifi_noc_memtype_m0_m2 = %x\n", val);
+ writel(val, base + TCSR_PNOC_SNOC_MEMTYPE_M0_M2);
+ }
+
+ return 0;
+}
+
+static const struct of_device_id tcsr_dt_match[] = {
+ { .compatible = "qcom,tcsr", },
+ { },
+};
+
+MODULE_DEVICE_TABLE(of, tcsr_dt_match);
+
+static struct platform_driver tcsr_driver = {
+ .driver = {
+ .name = "tcsr",
+ .owner = THIS_MODULE,
+ .of_match_table = tcsr_dt_match,
+ },
+ .probe = tcsr_probe,
+};
+
+module_platform_driver(tcsr_driver);
+
+MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
+MODULE_DESCRIPTION("QCOM TCSR driver");
+MODULE_LICENSE("GPL v2");
--- /dev/null
+++ b/include/dt-bindings/soc/qcom,tcsr.h
@@ -0,0 +1,48 @@
+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef __DT_BINDINGS_QCOM_TCSR_H
+#define __DT_BINDINGS_QCOM_TCSR_H
+
+#define TCSR_USB_SELECT_USB3_P0 0x1
+#define TCSR_USB_SELECT_USB3_P1 0x2
+#define TCSR_USB_SELECT_USB3_DUAL 0x3
+
+/* IPQ40xx HS PHY Mode Select */
+#define TCSR_USB_HSPHY_HOST_MODE 0x00E700E7
+#define TCSR_USB_HSPHY_DEVICE_MODE 0x00C700E7
+
+/* IPQ40xx ess interface mode select */
+#define TCSR_ESS_PSGMII 0
+#define TCSR_ESS_PSGMII_RGMII5 1
+#define TCSR_ESS_PSGMII_RMII0 2
+#define TCSR_ESS_PSGMII_RMII1 4
+#define TCSR_ESS_PSGMII_RMII0_RMII1 6
+#define TCSR_ESS_PSGMII_RGMII4 9
+
+/*
+ * IPQ40xx WiFi Global Config
+ * Bit 30:AXID_EN
+ * Enable AXI master bus Axid translating to confirm all txn submitted by order
+ * Bit 24: Use locally generated socslv_wxi_bvalid
+ * 1: use locally generate socslv_wxi_bvalid for performance.
+ * 0: use SNOC socslv_wxi_bvalid.
+ */
+#define TCSR_WIFI_GLB_CFG 0x41000000
+
+/* IPQ40xx MEM_TYPE_SEL_M0_M2 Select Bit 26:24 - 2 NORMAL */
+#define TCSR_WIFI_NOC_MEMTYPE_M0_M2 0x02222222
+
+/* TCSR A/B REG */
+#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL 0
+#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL 1
+
+#endif

176
root/target/linux/ipq40xx/patches-5.10/900-dts-ipq4019-ap-dk01.1.patch Normal file
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@ -0,0 +1,176 @@
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -15,6 +15,7 @@
*/
#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
@@ -29,6 +30,32 @@
};
soc {
+ tcsr@194b000 {
+ /* select hostmode */
+ compatible = "qcom,tcsr";
+ reg = <0x194b000 0x100>;
+ qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
+ status = "okay";
+ };
+
+ ess_tcsr@1953000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1953000 0x1000>;
+ qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
+ };
+
+ tcsr@1949000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1949000 0x100>;
+ qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
+ };
+
+ tcsr@1957000 {
+ compatible = "qcom,tcsr";
+ reg = <0x1957000 0x100>;
+ qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
+ };
+
rng@22000 {
status = "ok";
};
@@ -74,14 +101,6 @@
pinctrl-names = "default";
status = "ok";
cs-gpios = <&tlmm 54 0>;
-
- mx25l25635e@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- compatible = "mx25l25635e";
- spi-max-frequency = <24000000>;
- };
};
serial@78af000 {
@@ -109,5 +128,41 @@
wifi@a800000 {
status = "ok";
};
+
+ mdio@90000 {
+ status = "okay";
+ };
+
+ ess-switch@c000000 {
+ status = "okay";
+ };
+
+ ess-psgmii@98000 {
+ status = "okay";
+ };
+
+ edma@c080000 {
+ status = "okay";
+ };
+
+ usb3_ss_phy: ssphy@9a000 {
+ status = "okay";
+ };
+
+ usb3_hs_phy: hsphy@a6000 {
+ status = "okay";
+ };
+
+ usb3: usb3@8af8800 {
+ status = "okay";
+ };
+
+ usb2_hs_phy: hsphy@a8000 {
+ status = "okay";
+ };
+
+ usb2: usb2@60f8800 {
+ status = "okay";
+ };
};
};
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts
@@ -18,5 +18,73 @@
/ {
model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1";
+ compatible = "qcom,ap-dk01.1-c1", "qcom,ap-dk01.2-c1";
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>;
+ };
+};
+
+&blsp1_spi1 {
+ mx25l25635f@0 {
+ compatible = "mx25l25635f", "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+
+ SBL1@0 {
+ label = "SBL1";
+ reg = <0x0 0x40000>;
+ read-only;
+ };
+ MIBIB@40000 {
+ label = "MIBIB";
+ reg = <0x40000 0x20000>;
+ read-only;
+ };
+ QSEE@60000 {
+ label = "QSEE";
+ reg = <0x60000 0x60000>;
+ read-only;
+ };
+ CDT@c0000 {
+ label = "CDT";
+ reg = <0xc0000 0x10000>;
+ read-only;
+ };
+ DDRPARAMS@d0000 {
+ label = "DDRPARAMS";
+ reg = <0xd0000 0x10000>;
+ read-only;
+ };
+ APPSBLENV@e0000 {
+ label = "APPSBLENV";
+ reg = <0xe0000 0x10000>;
+ read-only;
+ };
+ APPSBL@f0000 {
+ label = "APPSBL";
+ reg = <0xf0000 0x80000>;
+ read-only;
+ };
+ ART@170000 {
+ label = "ART";
+ reg = <0x170000 0x10000>;
+ read-only;
+ };
+ kernel@180000 {
+ label = "kernel";
+ reg = <0x180000 0x400000>;
+ };
+ rootfs@580000 {
+ label = "rootfs";
+ reg = <0x580000 0x1600000>;
+ };
+ firmware@180000 {
+ label = "firmware";
+ reg = <0x180000 0x1a00000>;
+ };
+ };
};

84
root/target/linux/ipq40xx/patches-5.10/901-arm-boot-add-dts-files.patch Normal file
View file

@ -0,0 +1,84 @@
From a10fab12a927e60b7141a602e740d70cb4d09e4a Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Thu, 9 Mar 2017 11:03:18 +0100
Subject: [PATCH] arm: boot: add dts files
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/arm/boot/dts/Makefile | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -902,11 +902,71 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8074-dragonboard.dtb \
qcom-apq8084-ifc6540.dtb \
qcom-apq8084-mtp.dtb \
+ qcom-ipq4018-a42.dtb \
+ qcom-ipq4018-ap120c-ac.dtb \
+ qcom-ipq4018-dap-2610.dtb \
+ qcom-ipq4018-cs-w3-wd1200g-eup.dtb \
+ qcom-ipq4018-magic-2-wifi-next.dtb \
+ qcom-ipq4018-ea6350v3.dtb \
+ qcom-ipq4018-eap1300.dtb \
+ qcom-ipq4018-ecw5211.dtb \
+ qcom-ipq4018-emd1.dtb \
+ qcom-ipq4018-emr3500.dtb \
+ qcom-ipq4018-ens620ext.dtb \
+ qcom-ipq4018-ex6100v2.dtb \
+ qcom-ipq4018-ex6150v2.dtb \
+ qcom-ipq4018-fritzbox-4040.dtb \
+ qcom-ipq4018-gl-ap1300.dtb \
+ qcom-ipq4018-jalapeno.dtb \
+ qcom-ipq4018-meshpoint-one.dtb \
+ qcom-ipq4018-hap-ac2.dtb \
+ qcom-ipq4018-sxtsq-5-ac.dtb \
+ qcom-ipq4018-nbg6617.dtb \
+ qcom-ipq4019-oap100.dtb \
+ qcom-ipq4018-pa1200.dtb \
+ qcom-ipq4018-rt-ac58u.dtb \
+ qcom-ipq4018-rutx10.dtb \
+ qcom-ipq4018-wac510.dtb \
+ qcom-ipq4018-wre6606.dtb \
+ qcom-ipq4018-wrtq-329acn.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq4019-ap.dk07.1-c1.dtb \
qcom-ipq4019-ap.dk07.1-c2.dtb \
+ qcom-ipq4019-a62.dtb \
+ qcom-ipq4019-cm520-79f.dtb \
+ qcom-ipq4019-e2600ac-c1.dtb \
+ qcom-ipq4019-e2600ac-c2.dtb \
+ qcom-ipq4019-ea8300.dtb \
+ qcom-ipq4019-eap2200.dtb \
+ qcom-ipq4019-fritzbox-7530.dtb \
+ qcom-ipq4019-fritzrepeater-1200.dtb \
+ qcom-ipq4019-fritzrepeater-3000.dtb \
+ qcom-ipq4019-habanero-dvk.dtb \
+ qcom-ipq4019-hap-ac3.dtb \
+ qcom-ipq4019-map-ac2200.dtb \
+ qcom-ipq4019-lhgg-60ad.dtb \
+ qcom-ipq4019-mr8300.dtb \
+ qcom-ipq4019-pa2200.dtb \
+ qcom-ipq4019-r619ac-64m.dtb \
+ qcom-ipq4019-r619ac-128m.dtb \
+ qcom-ipq4019-rbr50.dtb \
+ qcom-ipq4019-rbs50.dtb \
+ qcom-ipq4019-rtl30vw.dtb \
+ qcom-ipq4019-srr60.dtb \
+ qcom-ipq4019-srs60.dtb \
+ qcom-ipq4019-u4019-32m.dtb \
+ qcom-ipq4019-wpj419.dtb \
+ qcom-ipq4019-wtr-m2133hp.dtb \
+ qcom-ipq4028-wpj428.dtb \
+ qcom-ipq4029-ap-303.dtb \
+ qcom-ipq4029-ap-303h.dtb \
+ qcom-ipq4029-ap-365.dtb \
+ qcom-ipq4029-gl-b1300.dtb \
+ qcom-ipq4019-gl-b2200.dtb \
+ qcom-ipq4029-gl-s1300.dtb \
+ qcom-ipq4029-mr33.dtb \
qcom-ipq8064-ap148.dtb \
qcom-ipq8064-rb3011.dtb \
qcom-msm8660-surf.dtb \

167
root/target/linux/ipq40xx/patches-5.10/902-dts-ipq4019-ap-dk04.1.patch Normal file
View file

@ -0,0 +1,167 @@
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
@@ -17,53 +17,79 @@
stdout-path = "serial0:115200n8";
};
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>; /* 256MB */
- };
-
soc {
+ rng@22000 {
+ status = "okay";
+ };
+
pinctrl@1000000 {
serial_0_pins: serial0-pinmux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
+ mux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
};
serial_1_pins: serial1-pinmux {
- pins = "gpio8", "gpio9",
- "gpio10", "gpio11";
- function = "blsp_uart1";
- bias-disable;
+ mux {
+ pins = "gpio8", "gpio9";
+ function = "blsp_uart1";
+ bias-disable;
+ };
};
spi_0_pins: spi-0-pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio13", "gpio14", "gpio15";
- bias-disable;
};
pinmux_cs {
function = "gpio";
pins = "gpio12";
+ };
+ pinconf {
+ pins = "gpio13", "gpio14", "gpio15";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ pinconf_cs {
+ pins = "gpio12";
+ drive-strength = <2>;
bias-disable;
output-high;
};
};
i2c_0_pins: i2c-0-pinmux {
- pins = "gpio20", "gpio21";
- function = "blsp_i2c0";
- bias-disable;
+ pinmux {
+ function = "blsp_i2c0";
+ pins = "gpio10", "gpio11";
+ };
+ pinconf {
+ pins = "gpio10", "gpio11";
+ drive-strength = <16>;
+ bias-disable;
+ };
};
nand_pins: nand-pins {
- pins = "gpio53", "gpio55", "gpio56",
- "gpio57", "gpio58", "gpio59",
- "gpio60", "gpio62", "gpio63",
- "gpio64", "gpio65", "gpio66",
- "gpio67", "gpio68", "gpio69";
- function = "qpic";
+ pullups {
+ pins = "gpio52", "gpio53", "gpio58",
+ "gpio59";
+ function = "qpic";
+ bias-pull-up;
+ };
+
+ pulldowns {
+ pins = "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio60", "gpio61",
+ "gpio62", "gpio63", "gpio64",
+ "gpio65", "gpio66", "gpio67",
+ "gpio68", "gpio69";
+ function = "qpic";
+ bias-pull-down;
+ };
};
};
@@ -89,11 +115,11 @@
status = "ok";
cs-gpios = <&tlmm 12 0>;
- m25p80@0 {
+ mx25l25635e@0 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
- compatible = "n25q128a11";
+ compatible = "mx25l25635e";
spi-max-frequency = <24000000>;
};
};
@@ -103,9 +129,48 @@
perst-gpio = <&tlmm 38 0x1>;
};
+ i2c0: i2c@78b7000 { /* BLSP1 QUP2 */
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ };
+
qpic-nand@79b0000 {
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
};
+
+ usb3_ss_phy: ssphy@9a000 {
+ status = "okay";
+ };
+
+ usb3_hs_phy: hsphy@a6000 {
+ status = "okay";
+ };
+
+ usb3: usb3@8af8800 {
+ status = "okay";
+ };
+
+ usb2_hs_phy: hsphy@a8000 {
+ status = "okay";
+ };
+
+ usb2: usb2@60f8800 {
+ status = "okay";
+ };
+
+ cryptobam: dma@8e04000 {
+ status = "okay";
+ };
+
+ crypto@8e3a000 {
+ status = "okay";
+ };
+
+ watchdog@b017000 {
+ status = "okay";
+ };
};
};

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