From 5688f668827f7afed32950b89b8763f23810adf6 Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Fri, 26 Apr 2024 17:05:39 +0100 Subject: [PATCH 033/697] clk-bcm2835: Use PLLD for DSI0 HS clock DSI0 can take the clock from either PLLA or PLLD. PLLA is the default muxing, but PLLD is considered the more stable. Switch to using PLLD. Signed-off-by: Dave Stevenson --- drivers/clk/bcm/clk-bcm2835.c | 4 ++++ 1 file changed, 4 insertions(+) --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -107,6 +107,7 @@ #define CM_UARTDIV 0x0f4 #define CM_VECCTL 0x0f8 #define CM_VECDIV 0x0fc +#define CM_DSI0HSCK 0x120 #define CM_PULSECTL 0x190 #define CM_PULSEDIV 0x194 #define CM_SDCCTL 0x1a8 @@ -2352,6 +2353,9 @@ static int bcm2835_clk_probe(struct plat if (IS_ERR(cprman->regs)) return PTR_ERR(cprman->regs); + /* Mux DSI0 clock to PLLD */ + cprman_write(cprman, CM_DSI0HSCK, 1); + fw_node = of_parse_phandle(dev->of_node, "firmware", 0); if (fw_node) { struct rpi_firmware *fw = rpi_firmware_get(fw_node);