--- a/drivers/rtc/rtc-mt6397.c 2020-03-05 23:43:52.000000000 +0800 +++ b/drivers/rtc/rtc-mt6397.c 2020-03-18 00:54:20.445907453 +0800 @@ -4,48 +4,18 @@ * Author: Tianping.Fang */ -#include -#include +#include +#include +#include #include +#include +#include #include #include -#include -#include -#include -#include -#include -#include - -#define RTC_BBPU 0x0000 -#define RTC_BBPU_CBUSY BIT(6) - -#define RTC_WRTGR 0x003c +#include +#include -#define RTC_IRQ_STA 0x0002 -#define RTC_IRQ_STA_AL BIT(0) -#define RTC_IRQ_STA_LP BIT(3) - -#define RTC_IRQ_EN 0x0004 -#define RTC_IRQ_EN_AL BIT(0) -#define RTC_IRQ_EN_ONESHOT BIT(2) -#define RTC_IRQ_EN_LP BIT(3) -#define RTC_IRQ_EN_ONESHOT_AL (RTC_IRQ_EN_ONESHOT | RTC_IRQ_EN_AL) - -#define RTC_AL_MASK 0x0008 -#define RTC_AL_MASK_DOW BIT(4) - -#define RTC_TC_SEC 0x000a -/* Min, Hour, Dom... register offset to RTC_TC_SEC */ -#define RTC_OFFSET_SEC 0 -#define RTC_OFFSET_MIN 1 -#define RTC_OFFSET_HOUR 2 -#define RTC_OFFSET_DOM 3 -#define RTC_OFFSET_DOW 4 -#define RTC_OFFSET_MTH 5 -#define RTC_OFFSET_YEAR 6 -#define RTC_OFFSET_COUNT 7 - -#define RTC_AL_SEC 0x0018 +#include #define RTC_AL_SEC_MASK 0x003f #define RTC_AL_MIN_MASK 0x003f @@ -55,26 +25,8 @@ #define RTC_AL_MTH_MASK 0x000f #define RTC_AL_YEA_MASK 0x007f -#define RTC_PDN2 0x002e -#define RTC_PDN2_PWRON_ALARM BIT(4) - -#define RTC_MIN_YEAR 1968 -#define RTC_BASE_YEAR 1900 -#define RTC_NUM_YEARS 128 -#define RTC_MIN_YEAR_OFFSET (RTC_MIN_YEAR - RTC_BASE_YEAR) - -struct mt6397_rtc { - struct device *dev; - struct rtc_device *rtc_dev; - struct mutex lock; - struct regmap *regmap; - int irq; - u32 addr_base; -}; - static int mtk_rtc_write_trigger(struct mt6397_rtc *rtc) { - unsigned long timeout = jiffies + HZ; int ret; u32 data; @@ -82,19 +34,13 @@ static int mtk_rtc_write_trigger(struct if (ret < 0) return ret; - while (1) { - ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_BBPU, - &data); - if (ret < 0) - break; - if (!(data & RTC_BBPU_CBUSY)) - break; - if (time_after(jiffies, timeout)) { - ret = -ETIMEDOUT; - break; - } - cpu_relax(); - } + ret = regmap_read_poll_timeout(rtc->regmap, + rtc->addr_base + RTC_BBPU, data, + !(data & RTC_BBPU_CBUSY), + MTK_RTC_POLL_DELAY_US, + MTK_RTC_POLL_TIMEOUT); + if (ret < 0) + dev_err(rtc->dev, "failed to write WRTGE: %d\n", ret); return ret; } @@ -338,19 +284,19 @@ static int mtk_rtc_probe(struct platform return rtc->irq; rtc->regmap = mt6397_chip->regmap; - rtc->dev = &pdev->dev; mutex_init(&rtc->lock); platform_set_drvdata(pdev, rtc); - rtc->rtc_dev = devm_rtc_allocate_device(rtc->dev); + rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev); if (IS_ERR(rtc->rtc_dev)) return PTR_ERR(rtc->rtc_dev); - ret = request_threaded_irq(rtc->irq, NULL, - mtk_rtc_irq_handler_thread, - IRQF_ONESHOT | IRQF_TRIGGER_HIGH, - "mt6397-rtc", rtc); + ret = devm_request_threaded_irq(&pdev->dev, rtc->irq, NULL, + mtk_rtc_irq_handler_thread, + IRQF_ONESHOT | IRQF_TRIGGER_HIGH, + "mt6397-rtc", rtc); + if (ret) { dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n", rtc->irq, ret); @@ -372,15 +318,6 @@ out_free_irq: return ret; } -static int mtk_rtc_remove(struct platform_device *pdev) -{ - struct mt6397_rtc *rtc = platform_get_drvdata(pdev); - - free_irq(rtc->irq, rtc); - - return 0; -} - #ifdef CONFIG_PM_SLEEP static int mt6397_rtc_suspend(struct device *dev) { @@ -407,6 +344,7 @@ static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_rtc_resume); static const struct of_device_id mt6397_rtc_of_match[] = { + { .compatible = "mediatek,mt6323-rtc", }, { .compatible = "mediatek,mt6397-rtc", }, { } }; @@ -419,7 +357,6 @@ static struct platform_driver mtk_rtc_dr .pm = &mt6397_pm_ops, }, .probe = mtk_rtc_probe, - .remove = mtk_rtc_remove, }; module_platform_driver(mtk_rtc_driver); diff --git a/include/linux/mfd/mt6397/rtc.h b/include/linux/mfd/mt6397/rtc.h new file mode 100644 index 000000000000..f84b9163c0ee --- /dev/null +++ b/include/linux/mfd/mt6397/rtc.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2014-2019 MediaTek Inc. + * + * Author: Tianping.Fang + * Sean Wang + */ + +#ifndef _LINUX_MFD_MT6397_RTC_H_ +#define _LINUX_MFD_MT6397_RTC_H_ + +#include +#include +#include +#include + +#define RTC_BBPU 0x0000 +#define RTC_BBPU_CBUSY BIT(6) +#define RTC_BBPU_KEY (0x43 << 8) + +#define RTC_WRTGR 0x003c + +#define RTC_IRQ_STA 0x0002 +#define RTC_IRQ_STA_AL BIT(0) +#define RTC_IRQ_STA_LP BIT(3) + +#define RTC_IRQ_EN 0x0004 +#define RTC_IRQ_EN_AL BIT(0) +#define RTC_IRQ_EN_ONESHOT BIT(2) +#define RTC_IRQ_EN_LP BIT(3) +#define RTC_IRQ_EN_ONESHOT_AL (RTC_IRQ_EN_ONESHOT | RTC_IRQ_EN_AL) + +#define RTC_AL_MASK 0x0008 +#define RTC_AL_MASK_DOW BIT(4) + +#define RTC_TC_SEC 0x000a +/* Min, Hour, Dom... register offset to RTC_TC_SEC */ +#define RTC_OFFSET_SEC 0 +#define RTC_OFFSET_MIN 1 +#define RTC_OFFSET_HOUR 2 +#define RTC_OFFSET_DOM 3 +#define RTC_OFFSET_DOW 4 +#define RTC_OFFSET_MTH 5 +#define RTC_OFFSET_YEAR 6 +#define RTC_OFFSET_COUNT 7 + +#define RTC_AL_SEC 0x0018 + +#define RTC_PDN2 0x002e +#define RTC_PDN2_PWRON_ALARM BIT(4) + +#define RTC_MIN_YEAR 1968 +#define RTC_BASE_YEAR 1900 +#define RTC_NUM_YEARS 128 +#define RTC_MIN_YEAR_OFFSET (RTC_MIN_YEAR - RTC_BASE_YEAR) + +#define MTK_RTC_POLL_DELAY_US 10 +#define MTK_RTC_POLL_TIMEOUT (jiffies_to_usecs(HZ)) + +struct mt6397_rtc { + struct device *dev; + struct rtc_device *rtc_dev; + + /* Protect register access from multiple tasks */ + struct mutex lock; + struct regmap *regmap; + int irq; + u32 addr_base; +}; + +#endif /* _LINUX_MFD_MT6397_RTC_H_ */