From 9f623c0e96fc7c3b5c9b7a81f0a3017c47033ec7 Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Sun, 19 Dec 2021 18:57:36 -0500 Subject: [PATCH 06/11] rockchip: rk356x: add quartz64-a board Signed-off-by: Peter Geis --- arch/arm/mach-rockchip/rk3568/Kconfig | 12 ++- board/pine64/quartz64-a-rk3566/Kconfig | 15 ++++ board/pine64/quartz64-a-rk3566/Makefile | 4 + .../quartz64-a-rk3566/quartz64-a-rk3566.c | 1 + configs/quartz64-a-rk3566_defconfig | 77 +++++++++++++++++++ include/configs/quartz64-a-rk3566.h | 14 ++++ include/dt-bindings/power/rk3568-power.h | 32 ++++++++ 7 files changed, 154 insertions(+), 1 deletion(-) create mode 100644 board/pine64/quartz64-a-rk3566/Kconfig create mode 100644 board/pine64/quartz64-a-rk3566/Makefile create mode 100644 board/pine64/quartz64-a-rk3566/quartz64-a-rk3566.c create mode 100644 configs/quartz64-a-rk3566_defconfig create mode 100644 include/configs/quartz64-a-rk3566.h create mode 100644 include/dt-bindings/power/rk3568-power.h --- a/arch/arm/mach-rockchip/rk3568/Kconfig +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -1,11 +1,20 @@ if ROCKCHIP_RK3568 +choice + prompt "RK3568/RK3566 board select" + config TARGET_EVB_RK3568 bool "RK3568 evaluation board" - select BOARD_LATE_INIT help RK3568 EVB is a evaluation board for Rockchp RK3568. +config TARGET_QUARTZ64_A_RK3566 + bool "Quartz64 Model A RK3566 development board" + help + Quartz64 Model A RK3566 is a development board from Pine64. + +endchoice + config ROCKCHIP_BOOT_MODE_REG default 0xfdc20200 @@ -19,5 +28,6 @@ config SYS_MALLOC_F_LEN default 0x2000 source "board/rockchip/evb_rk3568/Kconfig" +source "board/pine64/quartz64-a-rk3566/Kconfig" endif --- /dev/null +++ b/board/pine64/quartz64-a-rk3566/Kconfig @@ -0,0 +1,15 @@ +if TARGET_QUARTZ64_A_RK3566 + +config SYS_BOARD + default "quartz64-a-rk3566" + +config SYS_VENDOR + default "pine64" + +config SYS_CONFIG_NAME + default "quartz64-a-rk3566" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif --- /dev/null +++ b/board/pine64/quartz64-a-rk3566/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += quartz64-a-rk3566.o --- /dev/null +++ b/board/pine64/quartz64-a-rk3566/quartz64-a-rk3566.c @@ -0,0 +1 @@ +// SPDX-License-Identifier: GPL-2.0+ --- /dev/null +++ b/configs/quartz64-a-rk3566_defconfig @@ -0,0 +1,77 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00a00000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_DEFAULT_DEVICE_TREE="rk3566-quartz64-a" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_TARGET_QUARTZ64_A_RK3566=y +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_API=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-quartz64-a.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_LOAD_IMAGE_V2=y +CONFIG_CMD_BIND=y +CONFIG_CMD_CLK=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_POWER_DOMAIN=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_SPL_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_ERRNO_STR=y --- /dev/null +++ b/include/configs/quartz64-a-rk3566.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __QUARTZ64_A_RK3566_H +#define __QUARTZ64_A_RK3566_H + +#include + +#define CONFIG_SUPPORT_EMMC_RPMB + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#endif --- /dev/null +++ b/include/dt-bindings/power/rk3568-power.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__ +#define __DT_BINDINGS_POWER_RK3568_POWER_H__ + +/* VD_CORE */ +#define RK3568_PD_CPU_0 0 +#define RK3568_PD_CPU_1 1 +#define RK3568_PD_CPU_2 2 +#define RK3568_PD_CPU_3 3 +#define RK3568_PD_CORE_ALIVE 4 + +/* VD_PMU */ +#define RK3568_PD_PMU 5 + +/* VD_NPU */ +#define RK3568_PD_NPU 6 + +/* VD_GPU */ +#define RK3568_PD_GPU 7 + +/* VD_LOGIC */ +#define RK3568_PD_VI 8 +#define RK3568_PD_VO 9 +#define RK3568_PD_RGA 10 +#define RK3568_PD_VPU 11 +#define RK3568_PD_CENTER 12 +#define RK3568_PD_RKVDEC 13 +#define RK3568_PD_RKVENC 14 +#define RK3568_PD_PIPE 15 +#define RK3568_PD_LOGIC_ALIVE 16 + +#endif