From ff527efdd7a2d32b591f22178e9c4e221301efa2 Mon Sep 17 00:00:00 2001 From: Jonathan Bell Date: Tue, 5 Mar 2024 14:32:46 +0000 Subject: [PATCH 0928/1002] DT: rp1: add general-purpose clock source definitions GPCLKs have two parts - a clock divider and a clock input, routed out to and in from a GPIO pad respectively. It follows that the clksrc_gpN inputs can't be used unless the pad is also configured as a GPCLK, so leave them disabled. Signed-off-by: Jonathan Bell --- arch/arm/boot/dts/broadcom/rp1.dtsi | 90 +++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm/boot/dts/broadcom/rp1.dtsi b/arch/arm/boot/dts/broadcom/rp1.dtsi index 05e4f7a4e111..d5f61e74ea27 100644 --- a/arch/arm/boot/dts/broadcom/rp1.dtsi +++ b/arch/arm/boot/dts/broadcom/rp1.dtsi @@ -865,6 +865,36 @@ rp1_dpi_24bit_gpio0: rp1_dpi_24bit_gpio0 { /* Mode 7 -- All GPIOs used! */ bias-disable; }; + rp1_gpclksrc0_gpio4: rp1_gpclksrc0_gpio4 { + function = "gpclk0"; + pins = "gpio4"; + bias-disable; + }; + + rp1_gpclksrc0_gpio20: rp1_gpclksrc0_gpio20 { + function = "gpclk0"; + pins = "gpio20"; + bias-disable; + }; + + rp1_gpclksrc1_gpio5: rp1_gpclksrc1_gpio5 { + function = "gpclk1"; + pins = "gpio5"; + bias-disable; + }; + + rp1_gpclksrc1_gpio18: rp1_gpclksrc1_gpio18 { + function = "gpclk1"; + pins = "gpio18"; + bias-disable; + }; + + rp1_gpclksrc1_gpio21: rp1_gpclksrc1_gpio21 { + function = "gpclk1"; + pins = "gpio21"; + bias-disable; + }; + rp1_pwm1_gpio45: rp1_pwm1_gpio45 { function = "pwm1"; pins = "gpio45"; @@ -1210,6 +1240,66 @@ clksrc_mipi1_dsi_byteclk: clksrc_mipi1_dsi_byteclk { clock-output-names = "clksrc_mipi1_dsi_byteclk"; clock-frequency = <72000000>; }; + /* GPIO derived clock sources. Each GPIO with a GPCLK function + * can drive its output from the respective GPCLK + * generator, and provide a clock source to other internal + * dividers. Add dummy sources here so that they can be overridden + * with overlays. + */ + clksrc_gp0: clksrc_gp0 { + status = "disabled"; + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&rp1_clocks RP1_CLK_GP0>; + clock-output-names = "clksrc_gp0"; + }; + clksrc_gp1: clksrc_gp1 { + status = "disabled"; + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&rp1_clocks RP1_CLK_GP1>; + clock-output-names = "clksrc_gp1"; + }; + clksrc_gp2: clksrc_gp2 { + status = "disabled"; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + #clock-cells = <0>; + clocks = <&rp1_clocks RP1_CLK_GP2>; + clock-output-names = "clksrc_gp2"; + }; + clksrc_gp3: clksrc_gp3 { + status = "disabled"; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + #clock-cells = <0>; + clocks = <&rp1_clocks RP1_CLK_GP3>; + clock-output-names = "clksrc_gp3"; + }; + clksrc_gp4: clksrc_gp4 { + status = "disabled"; + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&rp1_clocks RP1_CLK_GP4>; + clock-output-names = "clksrc_gp4"; + }; + clksrc_gp5: clksrc_gp5 { + status = "disabled"; + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&rp1_clocks RP1_CLK_GP5>; + clock-output-names = "clksrc_gp5"; + }; }; / { -- 2.44.0