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41 lines
1.5 KiB
Diff
41 lines
1.5 KiB
Diff
From 52315bec6ed633b6a71f28b746029602f8bd70b9 Mon Sep 17 00:00:00 2001
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From: Balaji Prakash J <bjagadee@codeaurora.org>
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Date: Wed, 22 Apr 2020 20:35:30 +0530
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Subject: [PATCH] clk: ipq8074: fix gcc_blsp1_ahb_clk properties
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All the voting enabled clocks does not support the enable
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from CBCR register. So, updated gcc_blsp1_ahb_clk enable
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register and mask to enable bit in APCS_CLOCK_BRANCH_ENA_VOTE.
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Also, the voting controlled clocks are shared among multiple
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components like APSS, RPM, NSS, TZ, etc. So, turning the
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voting off from APSS does not make the clock off if it has
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been voted from another component. Added the flag
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BRANCH_HALT_VOTED in order to skip checking the clock
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disable status.
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This change is referred from the below commits,
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1. 246b4fb3af9bd65d8af794aac2f0e7b1ed9cc2dd
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2. c8374157d5ae91d3b3e0d513d62808a798b32d3a
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Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org>
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Change-Id: I505cb560b31ad27a02c165fbe13bb33a2fc7d230
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---
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drivers/clk/qcom/gcc-ipq8074.c | 5 +++--
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1 file changed, 3 insertions(+), 2 deletions(-)
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--- a/drivers/clk/qcom/gcc-ipq8074.c
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+++ b/drivers/clk/qcom/gcc-ipq8074.c
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@@ -2125,9 +2125,10 @@ struct clk_rcg2 adss_pwm_clk_src = {
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static struct clk_branch gcc_blsp1_ahb_clk = {
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.halt_reg = 0x01008,
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+ .halt_check = BRANCH_HALT_VOTED,
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.clkr = {
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- .enable_reg = 0x01008,
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- .enable_mask = BIT(0),
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+ .enable_reg = 0x0b004,
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+ .enable_mask = BIT(10),
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.hw.init = &(struct clk_init_data){
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.name = "gcc_blsp1_ahb_clk",
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.parent_hws = (const struct clk_hw *[]){
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