mptcp/openmptcprouter
1
0
Fork 0
mirror of https://github.com/Ysurac/openmptcprouter.git synced 2025-03-09 15:40:20 +00:00
Code Issues Releases Wiki Activity
openmptcprouter/6.12/target/linux/bcm27xx/patches-6.12/950-0694-dts-bcm2712-ds-Dedup-as-upstream-support-expands.patch
Ycarus (Yannick Chabanois) bdb9b0046f Add bcm27xx 6.12 test support
2024-12-20 14:17:26 +01:00

732 lines
20 KiB
Diff
Raw Permalink Blame History

From 006a12c20c6f1bd94734935bd3f4edfedb83715c Mon Sep 17 00:00:00 2001
From: Phil Elwell <phil@raspberrypi.com>
Date: Mon, 9 Dec 2024 12:03:17 +0000
Subject: [PATCH 694/697] dts: bcm2712-ds: Dedup as upstream support expands
Signed-off-by: Phil Elwell <phil@raspberrypi.com>
---
arch/arm64/boot/dts/broadcom/bcm2712-ds.dtsi | 667 +++++++++----------
1 file changed, 314 insertions(+), 353 deletions(-)
--- a/arch/arm64/boot/dts/broadcom/bcm2712-ds.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcm2712-ds.dtsi
@@ -188,22 +188,6 @@
};
};
- bsc_irq: intc@7d508380 {
- compatible = "brcm,bcm7271-l2-intc";
- reg = <0x7d508380 0x10>;
- interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <1>;
- };
-
- main_irq: intc@7d508400 {
- compatible = "brcm,bcm7271-l2-intc";
- reg = <0x7d508400 0x10>;
- interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <1>;
- };
-
gio: gpio@7d508500 {
compatible = "brcm,brcmstb-gpio";
reg = <0x7d508500 0x40>;
@@ -228,15 +212,6 @@
status = "disabled";
};
- aon_intr: interrupt-controller@7d510600 {
- compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
- reg = <0x7d510600 0x30>;
- interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <1>;
- status = "disabled";
- };
-
pinctrl_aon: pinctrl@7d510700 {
compatible = "brcm,bcm2712-aon-pinctrl";
reg = <0x7d510700 0x20>;
@@ -304,358 +279,344 @@
};
};
-/ {
- axi: axi {
- compatible = "simple-bus";
- #address-cells = <2>;
+&axi {
+ iommu2: iommu@5100 {
+ /* IOMMU2 for PISP-BE, HEVC; and (unused) H264 accelerators */
+ compatible = "brcm,bcm2712-iommu";
+ reg = <0x10 0x5100 0x0 0x80>;
+ cache = <&iommuc>;
+ #iommu-cells = <0>;
+ };
+
+ iommu4: iommu@5200 {
+ /* IOMMU4 for HVS, MPL/TXP; and (unused) Unicam, PISP-FE, MiniBVN */
+ compatible = "brcm,bcm2712-iommu";
+ reg = <0x10 0x5200 0x0 0x80>;
+ cache = <&iommuc>;
+ #iommu-cells = <0>;
+ #interconnect-cells = <0>;
+ };
+
+ iommu5: iommu@5280 {
+ /* IOMMU5 for PCIe2 (RP1); and (unused) BSTM */
+ compatible = "brcm,bcm2712-iommu";
+ reg = <0x10 0x5280 0x0 0x80>;
+ cache = <&iommuc>;
+ #iommu-cells = <0>;
+ dma-iova-offset = <0x10 0x00000000>; // HACK for RP1 masters over PCIe
+ };
+
+ iommuc: iommuc@5b00 {
+ compatible = "brcm,bcm2712-iommuc";
+ reg = <0x10 0x5b00 0x0 0x80>;
+ };
+
+ dma32: dma@10000 {
+ compatible = "brcm,bcm2712-dma";
+ reg = <0x10 0x00010000 0 0x600>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma0",
+ "dma1",
+ "dma2",
+ "dma3",
+ "dma4",
+ "dma5";
+ #dma-cells = <1>;
+ brcm,dma-channel-mask = <0x0035>;
+ };
+
+ dma40: dma@10600 {
+ compatible = "brcm,bcm2712-dma";
+ reg = <0x10 0x00010600 0 0x600>;
+ interrupts =
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, /* dma4 6 */
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, /* dma4 7 */
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, /* dma4 8 */
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, /* dma4 9 */
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, /* dma4 10 */
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; /* dma4 11 */
+ interrupt-names = "dma6",
+ "dma7",
+ "dma8",
+ "dma9",
+ "dma10",
+ "dma11";
+ #dma-cells = <1>;
+ brcm,dma-channel-mask = <0x0fc0>;
+ };
+
+ // Single-lane Gen3 PCIe
+ // Outbound window at 0x14_000000-0x17_ffffff
+ pcie0: pcie@100000 {
+ compatible = "brcm,bcm2712-pcie";
+ reg = <0x10 0x00100000 0x0 0x9310>;
+ device_type = "pci";
+ max-link-speed = <2>;
+ #address-cells = <3>;
+ #interrupt-cells = <1>;
#size-cells = <2>;
+ /*
+ * Unused interrupts:
+ * 208: AER
+ * 215: NMI
+ * 216: PME
+ */
+ interrupt-parent = <&gicv2>;
+ interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pcie", "msi";
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 209
+ IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gicv2 GIC_SPI 210
+ IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gicv2 GIC_SPI 211
+ IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gicv2 GIC_SPI 212
+ IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&bcm_reset 5>, <&bcm_reset 42>, <&pcie_rescal>;
+ reset-names = "swinit", "bridge", "rescal";
+ msi-controller;
+ msi-parent = <&pcie0>;
+
+ ranges = <0x02000000 0x00 0x00000000
+ 0x17 0x00000000
+ 0x0 0xfffffffc>,
+ <0x43000000 0x04 0x00000000
+ 0x14 0x00000000
+ 0x3 0x00000000>;
+
+ dma-ranges = <0x43000000 0x10 0x00000000
+ 0x00 0x00000000
+ 0x10 0x00000000>;
- ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>,
- <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>,
- <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>,
- <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>,
- <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>;
-
- dma-ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>,
- <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>,
- <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>,
- <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>,
- <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>;
-
- iommu2: iommu@5100 {
- /* IOMMU2 for PISP-BE, HEVC; and (unused) H264 accelerators */
- compatible = "brcm,bcm2712-iommu";
- reg = <0x10 0x5100 0x0 0x80>;
- cache = <&iommuc>;
- #iommu-cells = <0>;
- };
-
- iommu4: iommu@5200 {
- /* IOMMU4 for HVS, MPL/TXP; and (unused) Unicam, PISP-FE, MiniBVN */
- compatible = "brcm,bcm2712-iommu";
- reg = <0x10 0x5200 0x0 0x80>;
- cache = <&iommuc>;
- #iommu-cells = <0>;
- #interconnect-cells = <0>;
- };
-
- iommu5: iommu@5280 {
- /* IOMMU5 for PCIe2 (RP1); and (unused) BSTM */
- compatible = "brcm,bcm2712-iommu";
- reg = <0x10 0x5280 0x0 0x80>;
- cache = <&iommuc>;
- #iommu-cells = <0>;
- dma-iova-offset = <0x10 0x00000000>; // HACK for RP1 masters over PCIe
- };
-
- iommuc: iommuc@5b00 {
- compatible = "brcm,bcm2712-iommuc";
- reg = <0x10 0x5b00 0x0 0x80>;
- };
-
- dma32: dma@10000 {
- compatible = "brcm,bcm2712-dma";
- reg = <0x10 0x00010000 0 0x600>;
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "dma0",
- "dma1",
- "dma2",
- "dma3",
- "dma4",
- "dma5";
- #dma-cells = <1>;
- brcm,dma-channel-mask = <0x0035>;
- };
-
- dma40: dma@10600 {
- compatible = "brcm,bcm2712-dma";
- reg = <0x10 0x00010600 0 0x600>;
- interrupts =
- <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, /* dma4 6 */
- <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, /* dma4 7 */
- <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, /* dma4 8 */
- <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, /* dma4 9 */
- <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, /* dma4 10 */
- <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; /* dma4 11 */
- interrupt-names = "dma6",
- "dma7",
- "dma8",
- "dma9",
- "dma10",
- "dma11";
- #dma-cells = <1>;
- brcm,dma-channel-mask = <0x0fc0>;
- };
-
- // Single-lane Gen3 PCIe
- // Outbound window at 0x14_000000-0x17_ffffff
- pcie0: pcie@100000 {
- compatible = "brcm,bcm2712-pcie";
- reg = <0x10 0x00100000 0x0 0x9310>;
- device_type = "pci";
- max-link-speed = <2>;
- #address-cells = <3>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- /*
- * Unused interrupts:
- * 208: AER
- * 215: NMI
- * 216: PME
- */
- interrupt-parent = <&gicv2>;
- interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "pcie", "msi";
- interrupt-map-mask = <0x0 0x0 0x0 0x7>;
- interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 209
- IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 2 &gicv2 GIC_SPI 210
- IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 3 &gicv2 GIC_SPI 211
- IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 4 &gicv2 GIC_SPI 212
- IRQ_TYPE_LEVEL_HIGH>;
- resets = <&bcm_reset 5>, <&bcm_reset 42>, <&pcie_rescal>;
- reset-names = "swinit", "bridge", "rescal";
- msi-controller;
- msi-parent = <&pcie0>;
-
- ranges = <0x02000000 0x00 0x00000000
- 0x17 0x00000000
- 0x0 0xfffffffc>,
- <0x43000000 0x04 0x00000000
- 0x14 0x00000000
- 0x3 0x00000000>;
-
- dma-ranges = <0x43000000 0x10 0x00000000
- 0x00 0x00000000
- 0x10 0x00000000>;
-
- status = "disabled";
- };
-
- // Single-lane Gen3 PCIe
- // Outbound window at 0x18_000000-0x1b_ffffff
- pcie1: pcie@110000 {
- compatible = "brcm,bcm2712-pcie";
- reg = <0x10 0x00110000 0x0 0x9310>;
- device_type = "pci";
- max-link-speed = <2>;
- #address-cells = <3>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- /*
- * Unused interrupts:
- * 218: AER
- * 225: NMI
- * 226: PME
- */
- interrupt-parent = <&gicv2>;
- interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "pcie", "msi";
- interrupt-map-mask = <0x0 0x0 0x0 0x7>;
- interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 219
- IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 2 &gicv2 GIC_SPI 220
- IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 3 &gicv2 GIC_SPI 221
- IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 4 &gicv2 GIC_SPI 222
- IRQ_TYPE_LEVEL_HIGH>;
- resets = <&bcm_reset 7>, <&bcm_reset 43>, <&pcie_rescal>;
- reset-names = "swinit", "bridge", "rescal";
- msi-controller;
- msi-parent = <&mip1>;
-
- // 2GB, 32-bit, non-prefetchable at PCIe 00_80000000
- ranges = <0x02000000 0x00 0x80000000
- 0x1b 0x80000000
- 0x00 0x80000000>,
- // 14GB, 64-bit, prefetchable at PCIe 04_00000000
- <0x43000000 0x04 0x00000000
- 0x18 0x00000000
- 0x03 0x80000000>;
-
- dma-ranges = <0x03000000 0x10 0x00000000
- 0x00 0x00000000
- 0x10 0x00000000>;
-
- status = "disabled";
- };
-
- pcie_rescal: reset-controller@119500 {
- compatible = "brcm,bcm7216-pcie-sata-rescal";
- reg = <0x10 0x00119500 0x0 0x10>;
- #reset-cells = <0>;
- };
+ status = "disabled";
+ };
- // Quad-lane Gen3 PCIe
- // Outbound window at 0x1c_000000-0x1f_ffffff
- pcie2: pcie@120000 {
- compatible = "brcm,bcm2712-pcie";
- reg = <0x10 0x00120000 0x0 0x9310>;
- device_type = "pci";
- max-link-speed = <2>;
- #address-cells = <3>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- /*
- * Unused interrupts:
- * 228: AER
- * 235: NMI
- * 236: PME
- */
- interrupt-parent = <&gicv2>;
- interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "pcie", "msi";
- interrupt-map-mask = <0x0 0x0 0x0 0x7>;
- interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 229
- IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 2 &gicv2 GIC_SPI 230
- IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 3 &gicv2 GIC_SPI 231
- IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 4 &gicv2 GIC_SPI 232
- IRQ_TYPE_LEVEL_HIGH>;
- resets = <&bcm_reset 32>, <&bcm_reset 44>, <&pcie_rescal>;
- reset-names = "swinit", "bridge", "rescal";
- msi-controller;
- msi-parent = <&mip0>;
-
- // ~4GB, 32-bit, not-prefetchable at PCIe 00_00000000
- ranges = <0x02000000 0x00 0x00000000
- 0x1f 0x00000000
- 0x0 0xfffffffc>,
- // 12GB, 64-bit, prefetchable at PCIe 04_00000000
- <0x43000000 0x04 0x00000000
- 0x1c 0x00000000
- 0x03 0x00000000>;
-
- // 64GB system RAM space at PCIe 10_00000000
- dma-ranges = <0x02000000 0x00 0x00000000
- 0x1f 0x00000000
- 0x00 0x00400000>,
- <0x43000000 0x10 0x00000000
- 0x00 0x00000000
- 0x10 0x00000000>;
+ // Single-lane Gen3 PCIe
+ // Outbound window at 0x18_000000-0x1b_ffffff
+ pcie1: pcie@110000 {
+ compatible = "brcm,bcm2712-pcie";
+ reg = <0x10 0x00110000 0x0 0x9310>;
+ device_type = "pci";
+ max-link-speed = <2>;
+ #address-cells = <3>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ /*
+ * Unused interrupts:
+ * 218: AER
+ * 225: NMI
+ * 226: PME
+ */
+ interrupt-parent = <&gicv2>;
+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pcie", "msi";
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 219
+ IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gicv2 GIC_SPI 220
+ IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gicv2 GIC_SPI 221
+ IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gicv2 GIC_SPI 222
+ IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&bcm_reset 7>, <&bcm_reset 43>, <&pcie_rescal>;
+ reset-names = "swinit", "bridge", "rescal";
+ msi-controller;
+ msi-parent = <&mip1>;
+
+ // 2GB, 32-bit, non-prefetchable at PCIe 00_80000000
+ ranges = <0x02000000 0x00 0x80000000
+ 0x1b 0x80000000
+ 0x00 0x80000000>,
+ // 14GB, 64-bit, prefetchable at PCIe 04_00000000
+ <0x43000000 0x04 0x00000000
+ 0x18 0x00000000
+ 0x03 0x80000000>;
+
+ dma-ranges = <0x03000000 0x10 0x00000000
+ 0x00 0x00000000
+ 0x10 0x00000000>;
- status = "disabled";
- };
+ status = "disabled";
+ };
- mip0: msi-controller@130000 {
- compatible = "brcm,bcm2712-mip-intc";
- reg = <0x10 0x00130000 0x0 0xc0>;
- msi-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- brcm,msi-base-spi = <128>;
- brcm,msi-num-spis = <64>;
- brcm,msi-offset = <0>;
- brcm,msi-pci-addr = <0xff 0xfffff000>;
- };
+ pcie_rescal: reset-controller@119500 {
+ compatible = "brcm,bcm7216-pcie-sata-rescal";
+ reg = <0x10 0x00119500 0x0 0x10>;
+ #reset-cells = <0>;
+ };
- mip1: msi-controller@131000 {
- compatible = "brcm,bcm2712-mip-intc";
- reg = <0x10 0x00131000 0x0 0xc0>;
- msi-controller;
- interrupt-controller;
- #interrupt-cells = <2>;
- brcm,msi-base-spi = <247>;
- /* Actually 20 total, but the others are
- * both sparse and non-consecutive */
- brcm,msi-num-spis = <8>;
- brcm,msi-offset = <8>;
- brcm,msi-pci-addr = <0xff 0xffffe000>;
- };
+ // Quad-lane Gen3 PCIe
+ // Outbound window at 0x1c_000000-0x1f_ffffff
+ pcie2: pcie@120000 {
+ compatible = "brcm,bcm2712-pcie";
+ reg = <0x10 0x00120000 0x0 0x9310>;
+ device_type = "pci";
+ max-link-speed = <2>;
+ #address-cells = <3>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ /*
+ * Unused interrupts:
+ * 228: AER
+ * 235: NMI
+ * 236: PME
+ */
+ interrupt-parent = <&gicv2>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pcie", "msi";
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 229
+ IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gicv2 GIC_SPI 230
+ IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gicv2 GIC_SPI 231
+ IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gicv2 GIC_SPI 232
+ IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&bcm_reset 32>, <&bcm_reset 44>, <&pcie_rescal>;
+ reset-names = "swinit", "bridge", "rescal";
+ msi-controller;
+ msi-parent = <&mip0>;
+
+ // ~4GB, 32-bit, not-prefetchable at PCIe 00_00000000
+ ranges = <0x02000000 0x00 0x00000000
+ 0x1f 0x00000000
+ 0x0 0xfffffffc>,
+ // 12GB, 64-bit, prefetchable at PCIe 04_00000000
+ <0x43000000 0x04 0x00000000
+ 0x1c 0x00000000
+ 0x03 0x00000000>;
+
+ // 64GB system RAM space at PCIe 10_00000000
+ dma-ranges = <0x02000000 0x00 0x00000000
+ 0x1f 0x00000000
+ 0x00 0x00400000>,
+ <0x43000000 0x10 0x00000000
+ 0x00 0x00000000
+ 0x10 0x00000000>;
- syscon_piarbctl: syscon@400018 {
- compatible = "brcm,syscon-piarbctl", "syscon", "simple-mfd";
- reg = <0x10 0x00400018 0x0 0x18>;
- };
+ status = "disabled";
+ };
- usb: usb@480000 {
- compatible = "brcm,bcm2835-usb";
- reg = <0x10 0x00480000 0x0 0x10000>;
- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clk_usb>;
- clock-names = "otg";
- phys = <&usbphy>;
- phy-names = "usb2-phy";
- status = "disabled";
- };
+ mip0: msi-controller@130000 {
+ compatible = "brcm,bcm2712-mip-intc";
+ reg = <0x10 0x00130000 0x0 0xc0>;
+ msi-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ brcm,msi-base-spi = <128>;
+ brcm,msi-num-spis = <64>;
+ brcm,msi-offset = <0>;
+ brcm,msi-pci-addr = <0xff 0xfffff000>;
+ };
- rpivid: codec@800000 {
- compatible = "raspberrypi,rpivid-vid-decoder";
- reg = <0x10 0x00800000 0x0 0x10000>, /* HEVC */
- <0x10 0x00840000 0x0 0x1000>; /* INTC */
- reg-names = "hevc",
- "intc";
-
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
-
- clocks = <&firmware_clocks 11>;
- clock-names = "hevc";
- iommus = <&iommu2>;
- status = "disabled";
- };
+ mip1: msi-controller@131000 {
+ compatible = "brcm,bcm2712-mip-intc";
+ reg = <0x10 0x00131000 0x0 0xc0>;
+ msi-controller;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ brcm,msi-base-spi = <247>;
+ /* Actually 20 total, but the others are
+ * both sparse and non-consecutive */
+ brcm,msi-num-spis = <8>;
+ brcm,msi-offset = <8>;
+ brcm,msi-pci-addr = <0xff 0xffffe000>;
+ };
+
+ syscon_piarbctl: syscon@400018 {
+ compatible = "brcm,syscon-piarbctl", "syscon", "simple-mfd";
+ reg = <0x10 0x00400018 0x0 0x18>;
+ };
+
+ usb: usb@480000 {
+ compatible = "brcm,bcm2835-usb";
+ reg = <0x10 0x00480000 0x0 0x10000>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk_usb>;
+ clock-names = "otg";
+ phys = <&usbphy>;
+ phy-names = "usb2-phy";
+ status = "disabled";
+ };
- pisp_be: pisp_be@880000 {
- compatible = "raspberrypi,pispbe";
- reg = <0x10 0x00880000 0x0 0x4000>;
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&firmware_clocks 7>;
- clocks-names = "isp_be";
- status = "okay";
- iommus = <&iommu2>;
- };
+ rpivid: codec@800000 {
+ compatible = "raspberrypi,rpivid-vid-decoder";
+ reg = <0x10 0x00800000 0x0 0x10000>, /* HEVC */
+ <0x10 0x00840000 0x0 0x1000>; /* INTC */
+ reg-names = "hevc",
+ "intc";
+
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&firmware_clocks 11>;
+ clock-names = "hevc";
+ iommus = <&iommu2>;
+ status = "disabled";
+ };
- sdio2: mmc@1100000 {
- compatible = "brcm,bcm2712-sdhci";
- reg = <0x10 0x01100000 0x0 0x260>,
- <0x10 0x01100400 0x0 0x200>;
- reg-names = "host", "cfg";
- interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_emmc2>;
- sdhci-caps-mask = <0x0000C000 0x0>;
- sdhci-caps = <0x0 0x0>;
- supports-cqe;
- mmc-ddr-3_3v;
- status = "disabled";
- };
+ pisp_be: pisp_be@880000 {
+ compatible = "raspberrypi,pispbe";
+ reg = <0x10 0x00880000 0x0 0x4000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&firmware_clocks 7>;
+ clocks-names = "isp_be";
+ status = "okay";
+ iommus = <&iommu2>;
+ };
- bcm_reset: reset-controller@1504318 {
- compatible = "brcm,brcmstb-reset";
- reg = <0x10 0x01504318 0x0 0x30>;
- #reset-cells = <1>;
- };
+ sdio2: mmc@1100000 {
+ compatible = "brcm,bcm2712-sdhci";
+ reg = <0x10 0x01100000 0x0 0x260>,
+ <0x10 0x01100400 0x0 0x200>;
+ reg-names = "host", "cfg";
+ interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_emmc2>;
+ sdhci-caps-mask = <0x0000C000 0x0>;
+ sdhci-caps = <0x0 0x0>;
+ supports-cqe;
+ mmc-ddr-3_3v;
+ status = "disabled";
+ };
- v3d: v3d@2000000 {
- compatible = "brcm,2712-v3d";
- reg = <0x10 0x02000000 0x0 0x4000>,
- <0x10 0x02008000 0x0 0x6000>;
- reg-names = "hub", "core0";
-
- power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
- resets = <&pm BCM2835_RESET_V3D>;
- clocks = <&firmware_clocks 5>;
- clocks-names = "v3d";
- interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
+ bcm_reset: reset-controller@1504318 {
+ compatible = "brcm,brcmstb-reset";
+ reg = <0x10 0x01504318 0x0 0x30>;
+ #reset-cells = <1>;
+ };
+
+ v3d: v3d@2000000 {
+ compatible = "brcm,2712-v3d";
+ reg = <0x10 0x02000000 0x0 0x4000>,
+ <0x10 0x02008000 0x0 0x6000>;
+ reg-names = "hub", "core0";
+
+ power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
+ resets = <&pm BCM2835_RESET_V3D>;
+ clocks = <&firmware_clocks 5>;
+ clocks-names = "v3d";
+ interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
};
};
+&aon_intr {
+ status = "disabled";
+};
+
&gio_aon {
brcm,gpio-direct;
};
Reference in a new issue View git blame Copy permalink