mirror of
https://github.com/Ysurac/openmptcprouter.git
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46 lines
1.8 KiB
Diff
46 lines
1.8 KiB
Diff
From 62b20e6e0dde8d5633e3d94b028f86fb24b31d22 Mon Sep 17 00:00:00 2001
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From: Bin Yang <yangbin@rock-chips.com>
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Date: Mon, 28 Feb 2022 08:56:56 -0500
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Subject: [PATCH] usb: dwc3: core: do not use 3.0 clock when operating in 2.0
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mode
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In the 3.0 device core, if the core is programmed to operate in
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2.0 only, then setting the GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK makes
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the internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe)
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clock. Enabling this feature allows the pipe3 clock to be not-running
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when forcibly operating in 2.0 device mode.
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Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
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Signed-off-by: Bin Yang <yangbin@rock-chips.com>
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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Link: https://lore.kernel.org/r/20220228135700.1089526-6-pgwipeout@gmail.com
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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---
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drivers/usb/dwc3/core.c | 5 +++++
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drivers/usb/dwc3/core.h | 1 +
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2 files changed, 6 insertions(+)
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--- a/drivers/usb/dwc3/core.c
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+++ b/drivers/usb/dwc3/core.c
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@@ -1090,6 +1090,11 @@ static int dwc3_core_init(struct dwc3 *d
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if (dwc->parkmode_disable_ss_quirk)
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reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
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+ if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) &&
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+ (dwc->maximum_speed == USB_SPEED_HIGH ||
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+ dwc->maximum_speed == USB_SPEED_FULL))
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+ reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
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+
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dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
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}
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--- a/drivers/usb/dwc3/core.h
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+++ b/drivers/usb/dwc3/core.h
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@@ -258,6 +258,7 @@
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/* Global User Control 1 Register */
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#define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT BIT(31)
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#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
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+#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT(26)
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#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
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#define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
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#define DWC3_GUCTL1_RESUME_OPMODE_HS_HOST BIT(10)
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