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76 lines
1.9 KiB
Diff
76 lines
1.9 KiB
Diff
From 63b2249cb5ccf8ff0625cd707f243b3e882bc366 Mon Sep 17 00:00:00 2001
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From: Ryder Lee <ryder.lee@mediatek.com>
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Date: Wed, 5 Sep 2018 18:22:18 +0800
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Subject: [PATCH 40/77] arm: dts: mt7623: update subsystem clock controller
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device nodes
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Update MT7623 subsystem clock controllers, inlcuding mmsys, imgsys,
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vdecsys, g3dsys and bdpsys.
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Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
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---
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arch/arm/boot/dts/mt7623.dtsi | 41 +++++++++++++++++++++++++++++++++++
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1 file changed, 41 insertions(+)
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diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
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index d009b50f917e..35b0fa4112b0 100644
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--- a/arch/arm/boot/dts/mt7623.dtsi
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+++ b/arch/arm/boot/dts/mt7623.dtsi
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@@ -729,6 +729,39 @@
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clock-names = "wifi-dma";
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};
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+ g3dsys: syscon@13000000 {
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+ compatible = "mediatek,mt7623-g3dsys",
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+ "mediatek,mt2701-g3dsys",
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+ "syscon";
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+ reg = <0 0x13000000 0 0x200>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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+
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+ mmsys: syscon@14000000 {
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+ compatible = "mediatek,mt7623-mmsys",
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+ "mediatek,mt2701-mmsys",
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+ "syscon";
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+ reg = <0 0x14000000 0 0x1000>;
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+ #clock-cells = <1>;
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+ };
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+
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+ imgsys: syscon@15000000 {
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+ compatible = "mediatek,mt7623-imgsys",
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+ "mediatek,mt2701-imgsys",
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+ "syscon";
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+ reg = <0 0x15000000 0 0x1000>;
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+ #clock-cells = <1>;
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+ };
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+
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+ vdecsys: syscon@16000000 {
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+ compatible = "mediatek,mt7623-vdecsys",
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+ "mediatek,mt2701-vdecsys",
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+ "syscon";
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+ reg = <0 0x16000000 0 0x1000>;
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+ #clock-cells = <1>;
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+ };
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+
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hifsys: syscon@1a000000 {
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compatible = "mediatek,mt7623-hifsys",
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"mediatek,mt2701-hifsys",
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@@ -983,6 +1016,14 @@
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power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
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status = "disabled";
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};
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+
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+ bdpsys: syscon@1c000000 {
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+ compatible = "mediatek,mt7623-bdpsys",
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+ "mediatek,mt2701-bdpsys",
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+ "syscon";
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+ reg = <0 0x1c000000 0 0x1000>;
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+ #clock-cells = <1>;
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+ };
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};
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&pio {
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--
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2.19.1
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