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101 lines
3.3 KiB
Diff
101 lines
3.3 KiB
Diff
From 583c01b9c43f690293b6d7254634d4eef4406acd Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Thu, 11 Aug 2022 13:49:16 +0100
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Subject: [PATCH 054/726] drm/vc4: Configure the HVS COB allocations
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The HVS Composite Output Buffer (COB) is the memory used to
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generate the output pixel data.
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Until now the vc4 driver has been relying on the firmware to
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have set these to sensible values.
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In testing triple screen support it has been noted that only
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1 line was being assigned to HVS channel 2. Whilst that is fine
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for the transposer (TXP), and indeed needed as only some pixels
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have an alpha channel, it is insufficient to run a live display.
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Split the COB more evenly between the 3 HVS channels.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Revert vc4_regs change
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---
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drivers/gpu/drm/vc4/vc4_hvs.c | 56 ++++++++++++++++++++++++++++++++++-
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1 file changed, 55 insertions(+), 1 deletion(-)
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diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c
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index 67effc334715..23f8da10ea53 100644
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--- a/drivers/gpu/drm/vc4/vc4_hvs.c
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+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
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@@ -1013,7 +1013,7 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
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struct vc4_hvs *hvs = NULL;
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int ret;
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u32 dispctrl;
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- u32 reg;
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+ u32 reg, top;
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hvs = drmm_kzalloc(drm, sizeof(*hvs), GFP_KERNEL);
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if (!hvs)
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@@ -1151,6 +1151,60 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
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HVS_WRITE(SCALER_DISPCTRL, dispctrl);
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+ /* Recompute Composite Output Buffer (COB) allocations for the displays
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+ */
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+ if (!vc4->is_vc5) {
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+ /* The COB is 20736 pixels, or just over 10 lines at 2048 wide.
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+ * The bottom 2048 pixels are full 32bpp RGBA (intended for the
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+ * TXP composing RGBA to memory), whilst the remainder are only
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+ * 24bpp RGB.
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+ *
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+ * Assign 3 lines to channels 1 & 2, and just over 4 lines to
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+ * channel 0.
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+ */
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+ #define VC4_COB_SIZE 20736
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+ #define VC4_COB_LINE_WIDTH 2048
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+ #define VC4_COB_NUM_LINES 3
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+ reg = 0;
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+ top = VC4_COB_LINE_WIDTH * VC4_COB_NUM_LINES;
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+ reg |= (top - 1) << 16;
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+ HVS_WRITE(SCALER_DISPBASE2, reg);
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+ reg = top;
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+ top += VC4_COB_LINE_WIDTH * VC4_COB_NUM_LINES;
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+ reg |= (top - 1) << 16;
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+ HVS_WRITE(SCALER_DISPBASE1, reg);
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+ reg = top;
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+ top = VC4_COB_SIZE;
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+ reg |= (top - 1) << 16;
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+ HVS_WRITE(SCALER_DISPBASE0, reg);
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+ } else {
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+ /* The COB is 44416 pixels, or 10.8 lines at 4096 wide.
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+ * The bottom 4096 pixels are full RGBA (intended for the TXP
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+ * composing RGBA to memory), whilst the remainder are only
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+ * RGB. Addressing is always pixel wide.
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+ *
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+ * Assign 3 lines of 4096 to channels 1 & 2, and just over 4
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+ * lines. to channel 0.
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+ */
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+ #define VC5_COB_SIZE 44416
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+ #define VC5_COB_LINE_WIDTH 4096
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+ #define VC5_COB_NUM_LINES 3
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+ reg = 0;
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+ top = VC5_COB_LINE_WIDTH * VC5_COB_NUM_LINES;
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+ reg |= top << 16;
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+ HVS_WRITE(SCALER_DISPBASE2, reg);
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+ top += 16;
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+ reg = top;
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+ top += VC5_COB_LINE_WIDTH * VC5_COB_NUM_LINES;
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+ reg |= top << 16;
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+ HVS_WRITE(SCALER_DISPBASE1, reg);
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+ top += 16;
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+ reg = top;
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+ top = VC5_COB_SIZE;
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+ reg |= top << 16;
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+ HVS_WRITE(SCALER_DISPBASE0, reg);
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+ }
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+
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ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
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vc4_hvs_irq_handler, 0, "vc4 hvs", drm);
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if (ret)
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--
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2.33.1
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