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https://github.com/Ysurac/openmptcprouter.git
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71 lines
2.3 KiB
Diff
71 lines
2.3 KiB
Diff
From e6e6ef4275978823ec3a84133fc91f4ffbef5c84 Mon Sep 17 00:00:00 2001
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From: Paul Burton <paul.burton@imgtec.com>
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Date: Mon, 22 Feb 2016 18:09:44 +0000
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Subject: [PATCH] MIPS: Add barriers between dcache & icache flushes
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Index-based cache operations may be arbitrarily reordered by out of
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order CPUs. Thus code which writes back the dcache & then invalidates
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the icache using indexed cache ops must include a barrier between
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operating on the 2 caches in order to prevent the scenario in which:
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- icache invalidation occurs.
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- icache fetch occurs, due to speculation.
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- dcache writeback occurs.
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If the above were allowed to happen then the icache would contain stale
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data. Forcing the dcache writeback to complete before the icache
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invalidation avoids this.
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Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Cc: James Hogan <james.hogan@imgtec.com>
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---
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arch/mips/mm/c-r4k.c | 13 +++++++++++--
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1 file changed, 11 insertions(+), 2 deletions(-)
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--- a/arch/mips/mm/c-r4k.c
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+++ b/arch/mips/mm/c-r4k.c
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@@ -514,6 +514,7 @@ static inline void local_r4k___flush_cac
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default:
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r4k_blast_dcache();
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+ mb(); /* cache instructions may be reordered */
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r4k_blast_icache();
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break;
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}
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@@ -594,8 +595,10 @@ static inline void local_r4k_flush_cache
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if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
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r4k_blast_dcache();
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/* If executable, blast stale lines from icache */
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- if (exec)
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+ if (exec) {
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+ mb(); /* cache instructions may be reordered */
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r4k_blast_icache();
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+ }
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}
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static void r4k_flush_cache_range(struct vm_area_struct *vma,
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@@ -696,8 +699,13 @@ static inline void local_r4k_flush_cache
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if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
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vaddr ? r4k_blast_dcache_page(addr) :
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r4k_blast_dcache_user_page(addr);
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- if (exec && !cpu_icache_snoops_remote_store)
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+ if (exec)
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+ mb(); /* cache instructions may be reordered */
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+
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+ if (exec && !cpu_icache_snoops_remote_store) {
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r4k_blast_scache_page(addr);
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+ mb(); /* cache instructions may be reordered */
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+ }
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}
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if (exec) {
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if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
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@@ -764,6 +772,7 @@ static inline void __local_r4k_flush_ica
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else
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blast_dcache_range(start, end);
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}
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+ mb(); /* cache instructions may be reordered */
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}
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if (type == R4K_INDEX ||
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