mirror of
https://github.com/Ysurac/openmptcprouter.git
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152 lines
4.3 KiB
Diff
152 lines
4.3 KiB
Diff
From 68836b81f7d6328a1a5a6cce5a00bf4010f742e5 Mon Sep 17 00:00:00 2001
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From: baiywt <baiywt_gj@163.com>
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Date: Wed, 24 Nov 2021 19:59:38 +0800
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Subject: [PATCH] Add support for Orangepi R1 Plus LTS
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---
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arch/arm/dts/Makefile | 1 +
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arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts | 7 ++
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configs/orangepi-r1-plus-lts-rk3328_defconfig | 98 +++++++++++++++++++
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3 files changed, 106 insertions(+)
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create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
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create mode 100644 configs/orangepi-r1-plus-lts-rk3328_defconfig
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--- a/arch/arm/dts/Makefile
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+++ b/arch/arm/dts/Makefile
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@@ -110,6 +110,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
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rk3328-evb.dtb \
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rk3328-nanopi-r2s.dtb \
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rk3328-orangepi-r1-plus.dtb \
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+ rk3328-orangepi-r1-plus-lts.dtb \
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rk3328-roc-cc.dtb \
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rk3328-rock64.dtb \
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rk3328-rock-pi-e.dtb
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--- /dev/null
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+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
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@@ -0,0 +1,1 @@
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+#include "rk3328-nanopi-r2s-u-boot.dtsi"
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--- /dev/null
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+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts.dts
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@@ -0,0 +1,7 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+#include "rk3328-orangepi-r1-plus.dts"
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+
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+/ {
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+ model = "Xunlong Orange Pi R1 Plus LTS";
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+ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
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+};
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--- /dev/null
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+++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig
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@@ -0,0 +1,112 @@
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+CONFIG_ARM=y
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+CONFIG_SKIP_LOWLEVEL_INIT=y
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+CONFIG_COUNTER_FREQUENCY=24000000
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+CONFIG_ARCH_ROCKCHIP=y
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+CONFIG_TEXT_BASE=0x00200000
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+CONFIG_SPL_GPIO=y
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+CONFIG_NR_DRAM_BANKS=1
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+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000
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+CONFIG_ENV_OFFSET=0x3F8000
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+CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus-lts"
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+CONFIG_DM_RESET=y
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+CONFIG_ROCKCHIP_RK3328=y
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+CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
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+CONFIG_TPL_LIBCOMMON_SUPPORT=y
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+CONFIG_TPL_LIBGENERIC_SUPPORT=y
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+CONFIG_SPL_DRIVERS_MISC=y
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+CONFIG_SPL_STACK_R_ADDR=0x600000
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+CONFIG_SPL_STACK=0x400000
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+CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
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+CONFIG_DEBUG_UART_BASE=0xFF130000
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+CONFIG_DEBUG_UART_CLOCK=24000000
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+CONFIG_SYS_LOAD_ADDR=0x800800
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+CONFIG_DEBUG_UART=y
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+# CONFIG_ANDROID_BOOT_IMAGE is not set
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+CONFIG_FIT=y
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+CONFIG_FIT_VERBOSE=y
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+CONFIG_SPL_LOAD_FIT=y
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+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb"
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+# CONFIG_DISPLAY_CPUINFO is not set
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+CONFIG_DISPLAY_BOARDINFO_LATE=y
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+CONFIG_MISC_INIT_R=y
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+CONFIG_SPL_MAX_SIZE=0x40000
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+CONFIG_SPL_PAD_TO=0x7f8000
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+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
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+CONFIG_SPL_BSS_START_ADDR=0x2000000
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+CONFIG_SPL_BSS_MAX_SIZE=0x2000
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+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
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+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
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+CONFIG_SPL_STACK_R=y
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+CONFIG_SPL_I2C=y
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+CONFIG_SPL_POWER=y
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+CONFIG_SPL_ATF=y
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+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
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+CONFIG_TPL_SYS_MALLOC_SIMPLE=y
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+CONFIG_CMD_BOOTZ=y
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+CONFIG_CMD_GPT=y
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+CONFIG_CMD_MMC=y
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+CONFIG_CMD_USB=y
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+# CONFIG_CMD_SETEXPR is not set
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+CONFIG_CMD_TIME=y
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+CONFIG_SPL_OF_CONTROL=y
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+CONFIG_TPL_OF_CONTROL=y
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+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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+CONFIG_TPL_OF_PLATDATA=y
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+CONFIG_ENV_IS_IN_MMC=y
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+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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+CONFIG_SYS_MMC_ENV_DEV=1
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+CONFIG_NET_RANDOM_ETHADDR=y
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+CONFIG_TPL_DM=y
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+CONFIG_REGMAP=y
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+CONFIG_SPL_REGMAP=y
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+CONFIG_TPL_REGMAP=y
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+CONFIG_SYSCON=y
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+CONFIG_SPL_SYSCON=y
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+CONFIG_TPL_SYSCON=y
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+CONFIG_CLK=y
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+CONFIG_SPL_CLK=y
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+CONFIG_FASTBOOT_BUF_ADDR=0x800800
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+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
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+CONFIG_ROCKCHIP_GPIO=y
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+CONFIG_SYS_I2C_ROCKCHIP=y
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+CONFIG_MMC_DW=y
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+CONFIG_MMC_DW_ROCKCHIP=y
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+CONFIG_SF_DEFAULT_SPEED=20000000
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+CONFIG_ETH_DESIGNWARE=y
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+CONFIG_GMAC_ROCKCHIP=y
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+CONFIG_PINCTRL=y
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+CONFIG_SPL_PINCTRL=y
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+CONFIG_DM_PMIC=y
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+CONFIG_PMIC_RK8XX=y
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+CONFIG_SPL_PMIC_RK8XX=y
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+CONFIG_SPL_DM_REGULATOR=y
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+CONFIG_REGULATOR_PWM=y
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+CONFIG_DM_REGULATOR_FIXED=y
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+CONFIG_SPL_DM_REGULATOR_FIXED=y
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+CONFIG_REGULATOR_RK8XX=y
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+CONFIG_PWM_ROCKCHIP=y
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+CONFIG_RAM=y
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+CONFIG_SPL_RAM=y
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+CONFIG_TPL_RAM=y
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+CONFIG_BAUDRATE=1500000
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+CONFIG_DEBUG_UART_SHIFT=2
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+CONFIG_SYS_NS16550_MEM32=y
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+CONFIG_SYSINFO=y
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+CONFIG_SYSRESET=y
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+# CONFIG_TPL_SYSRESET is not set
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+CONFIG_USB=y
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+CONFIG_USB_XHCI_HCD=y
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+CONFIG_USB_XHCI_DWC3=y
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+CONFIG_USB_EHCI_HCD=y
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+CONFIG_USB_EHCI_GENERIC=y
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+CONFIG_USB_OHCI_HCD=y
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+CONFIG_USB_OHCI_GENERIC=y
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+CONFIG_USB_DWC2=y
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+CONFIG_USB_DWC3=y
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+# CONFIG_USB_DWC3_GADGET is not set
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+CONFIG_USB_GADGET=y
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+CONFIG_USB_GADGET_DWC2_OTG=y
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+CONFIG_SPL_TINY_MEMSET=y
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+CONFIG_TPL_TINY_MEMSET=y
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+CONFIG_ERRNO_STR=y
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