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27 lines
969 B
Diff
27 lines
969 B
Diff
From 596c3a7300c0419dba71d58cbd4136e0d1e12a4e Mon Sep 17 00:00:00 2001
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From: Shunli Wang <shunli.wang@mediatek.com>
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Date: Tue, 5 Jan 2016 14:30:22 +0800
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Subject: [PATCH 06/57] reset: mediatek: mt2701 reset driver
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In infrasys and perifsys, there are many reset
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control bits for kinds of modules. These bits are
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used as actual reset controllers to be registered
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into kernel's generic reset controller framework.
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Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
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Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
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---
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drivers/clk/mediatek/clk-mt2701.c | 4 ++++
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1 file changed, 4 insertions(+)
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--- a/drivers/clk/mediatek/clk-mt2701.c
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+++ b/drivers/clk/mediatek/clk-mt2701.c
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@@ -772,6 +772,8 @@ static void mtk_infrasys_init_early(stru
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if (r)
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pr_err("%s(): could not register clock provider: %d\n",
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__func__, r);
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+
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+ mtk_register_reset_controller(node, 2, 0x30);
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}
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CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt2701-infracfg",
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mtk_infrasys_init_early);
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