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190 lines
6.8 KiB
Diff
190 lines
6.8 KiB
Diff
From acfa4eba7a4391d443b33a3d90a07eae0ef2ebca Mon Sep 17 00:00:00 2001
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From: Sean Wang <sean.wang@mediatek.com>
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Date: Thu, 5 Oct 2017 11:50:22 +0800
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Subject: [PATCH 147/224] dt-bindings: clock: mediatek: document clk bindings
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for MediaTek MT7622 SoC
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This patch adds the binding documentation for apmixedsys, ethsys, hifsys,
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infracfg, pericfg, topckgen and audsys for MT7622.
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Signed-off-by: Chen Zhong <chen.zhong@mediatek.com>
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Signed-off-by: Sean Wang <sean.wang@mediatek.com>
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Acked-by: Rob Herring <robh@kernel.org>
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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---
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.../bindings/arm/mediatek/mediatek,apmixedsys.txt | 1 +
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.../bindings/arm/mediatek/mediatek,audsys.txt | 22 ++++++++++++++++++++++
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.../bindings/arm/mediatek/mediatek,ethsys.txt | 1 +
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.../bindings/arm/mediatek/mediatek,hifsys.txt | 1 +
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.../bindings/arm/mediatek/mediatek,infracfg.txt | 1 +
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.../bindings/arm/mediatek/mediatek,pciesys.txt | 22 ++++++++++++++++++++++
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.../bindings/arm/mediatek/mediatek,pericfg.txt | 1 +
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.../bindings/arm/mediatek/mediatek,sgmiisys.txt | 22 ++++++++++++++++++++++
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.../bindings/arm/mediatek/mediatek,ssusbsys.txt | 22 ++++++++++++++++++++++
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.../bindings/arm/mediatek/mediatek,topckgen.txt | 1 +
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10 files changed, 94 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
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create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
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create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
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create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
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--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
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+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
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@@ -9,6 +9,7 @@ Required Properties:
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- "mediatek,mt2701-apmixedsys"
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- "mediatek,mt2712-apmixedsys", "syscon"
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- "mediatek,mt6797-apmixedsys"
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+ - "mediatek,mt7622-apmixedsys"
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- "mediatek,mt8135-apmixedsys"
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- "mediatek,mt8173-apmixedsys"
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- #clock-cells: Must be 1
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
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@@ -0,0 +1,22 @@
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+MediaTek AUDSYS controller
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+============================
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+
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+The MediaTek AUDSYS controller provides various clocks to the system.
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+
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+Required Properties:
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+
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+- compatible: Should be one of:
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+ - "mediatek,mt7622-audsys", "syscon"
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+- #clock-cells: Must be 1
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+
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+The AUDSYS controller uses the common clk binding from
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+Documentation/devicetree/bindings/clock/clock-bindings.txt
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+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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+
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+Example:
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+
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+audsys: audsys@11220000 {
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+ compatible = "mediatek,mt7622-audsys", "syscon";
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+ reg = <0 0x11220000 0 0x1000>;
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+ #clock-cells = <1>;
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+};
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--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
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+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
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@@ -7,6 +7,7 @@ Required Properties:
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- compatible: Should be:
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- "mediatek,mt2701-ethsys", "syscon"
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+ - "mediatek,mt7622-ethsys", "syscon"
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- #clock-cells: Must be 1
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The ethsys controller uses the common clk binding from
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--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
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+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
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@@ -8,6 +8,7 @@ Required Properties:
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- compatible: Should be:
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- "mediatek,mt2701-hifsys", "syscon"
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+ - "mediatek,mt7622-hifsys", "syscon"
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- #clock-cells: Must be 1
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The hifsys controller uses the common clk binding from
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--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
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+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
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@@ -10,6 +10,7 @@ Required Properties:
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- "mediatek,mt2701-infracfg", "syscon"
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- "mediatek,mt2712-infracfg", "syscon"
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- "mediatek,mt6797-infracfg", "syscon"
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+ - "mediatek,mt7622-infracfg", "syscon"
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- "mediatek,mt8135-infracfg", "syscon"
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- "mediatek,mt8173-infracfg", "syscon"
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- #clock-cells: Must be 1
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
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@@ -0,0 +1,22 @@
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+MediaTek PCIESYS controller
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+============================
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+
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+The MediaTek PCIESYS controller provides various clocks to the system.
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+
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+Required Properties:
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+
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+- compatible: Should be:
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+ - "mediatek,mt7622-pciesys", "syscon"
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+- #clock-cells: Must be 1
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+
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+The PCIESYS controller uses the common clk binding from
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+Documentation/devicetree/bindings/clock/clock-bindings.txt
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+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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+
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+Example:
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+
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+pciesys: pciesys@1a100800 {
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+ compatible = "mediatek,mt7622-pciesys", "syscon";
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+ reg = <0 0x1a100800 0 0x1000>;
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+ #clock-cells = <1>;
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+};
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--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
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+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
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@@ -9,6 +9,7 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-pericfg", "syscon"
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- "mediatek,mt2712-pericfg", "syscon"
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+ - "mediatek,mt7622-pericfg", "syscon"
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- "mediatek,mt8135-pericfg", "syscon"
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- "mediatek,mt8173-pericfg", "syscon"
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- #clock-cells: Must be 1
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
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@@ -0,0 +1,22 @@
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+MediaTek SGMIISYS controller
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+============================
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+
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+The MediaTek SGMIISYS controller provides various clocks to the system.
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+
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+Required Properties:
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+
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+- compatible: Should be:
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+ - "mediatek,mt7622-sgmiisys", "syscon"
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+- #clock-cells: Must be 1
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+
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+The SGMIISYS controller uses the common clk binding from
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+Documentation/devicetree/bindings/clock/clock-bindings.txt
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+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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+
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+Example:
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+
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+sgmiisys: sgmiisys@1b128000 {
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+ compatible = "mediatek,mt7622-sgmiisys", "syscon";
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+ reg = <0 0x1b128000 0 0x1000>;
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+ #clock-cells = <1>;
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+};
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
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@@ -0,0 +1,22 @@
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+MediaTek SSUSBSYS controller
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+============================
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+
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+The MediaTek SSUSBSYS controller provides various clocks to the system.
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+
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+Required Properties:
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+
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+- compatible: Should be:
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+ - "mediatek,mt7622-ssusbsys", "syscon"
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+- #clock-cells: Must be 1
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+
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+The SSUSBSYS controller uses the common clk binding from
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+Documentation/devicetree/bindings/clock/clock-bindings.txt
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+The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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+
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+Example:
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+
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+ssusbsys: ssusbsys@1a000000 {
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+ compatible = "mediatek,mt7622-ssusbsys", "syscon";
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+ reg = <0 0x1a000000 0 0x1000>;
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+ #clock-cells = <1>;
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+};
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--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
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+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
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@@ -9,6 +9,7 @@ Required Properties:
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- "mediatek,mt2701-topckgen"
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- "mediatek,mt2712-topckgen", "syscon"
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- "mediatek,mt6797-topckgen"
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+ - "mediatek,mt7622-topckgen"
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- "mediatek,mt8135-topckgen"
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- "mediatek,mt8173-topckgen"
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- #clock-cells: Must be 1
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