mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
145 lines
4.3 KiB
Diff
145 lines
4.3 KiB
Diff
From 7cc8226e45b2c6b9f06ce82ba6995b8f911afe25 Mon Sep 17 00:00:00 2001
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From: Zhi Mao <zhi.mao@mediatek.com>
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Date: Wed, 25 Oct 2017 18:11:01 +0800
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Subject: [PATCH 161/224] pwm: mediatek: Add MT2712/MT7622 support
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Add support for MT2712 and MT7622. Due to register offset address of
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pwm7 for MT2712 is not fixed 0x40, add mtk_pwm_reg_offset array for PWM
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register offset.
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Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
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Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
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Signed-off-by: Zhi Mao <zhi.mao@mediatek.com>
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Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
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---
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drivers/pwm/pwm-mediatek.c | 53 ++++++++++++++++++++++++++++++++++++++--------
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1 file changed, 44 insertions(+), 9 deletions(-)
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--- a/drivers/pwm/pwm-mediatek.c
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+++ b/drivers/pwm/pwm-mediatek.c
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@@ -16,6 +16,7 @@
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/of.h>
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+#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/slab.h>
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@@ -40,11 +41,19 @@ enum {
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MTK_CLK_PWM3,
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MTK_CLK_PWM4,
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MTK_CLK_PWM5,
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+ MTK_CLK_PWM6,
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+ MTK_CLK_PWM7,
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+ MTK_CLK_PWM8,
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MTK_CLK_MAX,
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};
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-static const char * const mtk_pwm_clk_name[] = {
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- "main", "top", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5"
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+static const char * const mtk_pwm_clk_name[MTK_CLK_MAX] = {
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+ "main", "top", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7",
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+ "pwm8"
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+};
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+
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+struct mtk_pwm_platform_data {
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+ unsigned int num_pwms;
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};
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/**
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@@ -59,6 +68,10 @@ struct mtk_pwm_chip {
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struct clk *clks[MTK_CLK_MAX];
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};
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+static const unsigned int mtk_pwm_reg_offset[] = {
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+ 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
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+};
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+
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static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct mtk_pwm_chip, chip);
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@@ -103,14 +116,14 @@ static void mtk_pwm_clk_disable(struct p
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static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num,
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unsigned int offset)
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{
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- return readl(chip->regs + 0x10 + (num * 0x40) + offset);
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+ return readl(chip->regs + mtk_pwm_reg_offset[num] + offset);
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}
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static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip,
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unsigned int num, unsigned int offset,
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u32 value)
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{
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- writel(value, chip->regs + 0x10 + (num * 0x40) + offset);
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+ writel(value, chip->regs + mtk_pwm_reg_offset[num] + offset);
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}
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static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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@@ -185,6 +198,7 @@ static const struct pwm_ops mtk_pwm_ops
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static int mtk_pwm_probe(struct platform_device *pdev)
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{
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+ const struct mtk_pwm_platform_data *data;
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struct mtk_pwm_chip *pc;
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struct resource *res;
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unsigned int i;
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@@ -194,15 +208,22 @@ static int mtk_pwm_probe(struct platform
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if (!pc)
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return -ENOMEM;
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+ data = of_device_get_match_data(&pdev->dev);
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+ if (data == NULL)
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+ return -EINVAL;
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+
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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pc->regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(pc->regs))
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return PTR_ERR(pc->regs);
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- for (i = 0; i < MTK_CLK_MAX; i++) {
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+ for (i = 0; i < data->num_pwms + 2; i++) {
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pc->clks[i] = devm_clk_get(&pdev->dev, mtk_pwm_clk_name[i]);
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- if (IS_ERR(pc->clks[i]))
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+ if (IS_ERR(pc->clks[i])) {
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+ dev_err(&pdev->dev, "clock: %s fail: %ld\n",
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+ mtk_pwm_clk_name[i], PTR_ERR(pc->clks[i]));
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return PTR_ERR(pc->clks[i]);
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+ }
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}
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platform_set_drvdata(pdev, pc);
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@@ -210,7 +231,7 @@ static int mtk_pwm_probe(struct platform
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pc->chip.dev = &pdev->dev;
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pc->chip.ops = &mtk_pwm_ops;
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pc->chip.base = -1;
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- pc->chip.npwm = 5;
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+ pc->chip.npwm = data->num_pwms;
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ret = pwmchip_add(&pc->chip);
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if (ret < 0) {
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@@ -228,9 +249,23 @@ static int mtk_pwm_remove(struct platfor
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return pwmchip_remove(&pc->chip);
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}
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+static const struct mtk_pwm_platform_data mt2712_pwm_data = {
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+ .num_pwms = 8,
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+};
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+
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+static const struct mtk_pwm_platform_data mt7622_pwm_data = {
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+ .num_pwms = 6,
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+};
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+
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+static const struct mtk_pwm_platform_data mt7623_pwm_data = {
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+ .num_pwms = 5,
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+};
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+
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static const struct of_device_id mtk_pwm_of_match[] = {
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- { .compatible = "mediatek,mt7623-pwm" },
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- { }
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+ { .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data },
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+ { .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data },
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+ { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
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+ { },
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};
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MODULE_DEVICE_TABLE(of, mtk_pwm_of_match);
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