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https://github.com/Ysurac/openmptcprouter.git
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77 lines
2.5 KiB
Diff
77 lines
2.5 KiB
Diff
From 6468d187f12604f38f0a3acde430fdc5c5390771 Mon Sep 17 00:00:00 2001
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From: Ryder Lee <ryder.lee@mediatek.com>
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Date: Tue, 23 Jul 2019 11:32:50 +0800
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Subject: [PATCH] arm: dts: mt7623: add Mali-450 device nodes
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Add nodes for Mali-450 and iommu larb3.
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Signed-off-by: Sean Wang <sean.wang@mediatek.com>
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Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
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---
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arch/arm/boot/dts/mt7623.dtsi | 39 ++++++++++++++++++++++++++++++++++-
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1 file changed, 38 insertions(+), 1 deletion(-)
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diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
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index 8d0807fd9460..f7905561b30e 100644
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--- a/arch/arm/boot/dts/mt7623.dtsi
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+++ b/arch/arm/boot/dts/mt7623.dtsi
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@@ -3,6 +3,7 @@
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* Copyright (c) 2017-2018 MediaTek Inc.
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* Author: John Crispin <john@phrozen.org>
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* Sean Wang <sean.wang@mediatek.com>
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+ * Ryder Lee <ryder.lee@mediatek.com>
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*
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*/
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@@ -371,7 +372,7 @@
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interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_M4U>;
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clock-names = "bclk";
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- mediatek,larbs = <&larb0 &larb1 &larb2>;
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+ mediatek,larbs = <&larb0 &larb1 &larb2 &larb3>;
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#iommu-cells = <1>;
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};
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@@ -794,6 +795,42 @@
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#reset-cells = <1>;
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};
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+ larb3: larb@13010000 {
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+ compatible = "mediatek,mt7623-smi-larb",
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+ "mediatek,mt2701-smi-larb";
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+ reg = <0 0x13010000 0 0x1000>;
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+ mediatek,smi = <&smi_common>;
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+ mediatek,larb-id = <3>;
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+ clocks = <&clk26m>, <&clk26m>;
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+ clock-names = "apb", "smi";
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+ power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;
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+ };
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+
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+ mali: gpu@13040000 {
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+ compatible = "mediatek,mt7623-mali", "arm,mali-450";
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+ reg = <0 0x13040000 0 0x30000>;
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+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_SPI 178 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
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+ interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
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+ "ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3",
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+ "pp";
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+ clocks = <&topckgen CLK_TOP_MMPLL>,
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+ <&g3dsys CLK_G3DSYS_CORE>;
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+ clock-names = "bus", "core";
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+ power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;
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+ mediatek,larb = <&larb3>;
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+ resets = <&g3dsys MT2701_G3DSYS_CORE_RST>;
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+ };
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+
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mmsys: syscon@14000000 {
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compatible = "mediatek,mt7623-mmsys",
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"mediatek,mt2701-mmsys",
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