mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
109 lines
3.2 KiB
Diff
109 lines
3.2 KiB
Diff
From ab7ad2d077ef18d6d853c8838bc116fbbd0ac154 Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Thu, 20 Dec 2018 16:12:52 +0800
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Subject: clk: MediaTek: bind ethsys reset controller
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The ethsys contains not only the clock gating controller, but also the
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reset controller for the whole ethernet subsystem and its components.
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This patch adds binding of the reset controller so that the ethernet node
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can have references on it.
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c
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index c6b09d8e..87ad4f79 100644
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--- a/drivers/clk/mediatek/clk-mt7623.c
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+++ b/drivers/clk/mediatek/clk-mt7623.c
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@@ -8,6 +8,7 @@
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#include <common.h>
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#include <dm.h>
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+#include <asm/arch-mediatek/reset.h>
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#include <asm/io.h>
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#include <dt-bindings/clock/mt7623-clk.h>
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@@ -782,6 +783,19 @@ static int mt7623_ethsys_probe(struct udevice *dev)
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return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, eth_cgs);
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}
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+static int mt7623_ethsys_bind(struct udevice *dev)
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+{
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+ int ret = 0;
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+
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+#if CONFIG_IS_ENABLED(RESET_MEDIATEK)
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+ ret = mediatek_reset_bind(dev, ETHSYS_RST_CTRL_OFS, 1);
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+ if (ret)
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+ debug("Warning: failed to bind ethsys reset controller\n");
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+#endif
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+
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+ return ret;
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+}
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+
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static const struct udevice_id mt7623_apmixed_compat[] = {
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{ .compatible = "mediatek,mt7623-apmixedsys" },
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{ }
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@@ -865,6 +879,7 @@ U_BOOT_DRIVER(mtk_clk_ethsys) = {
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.id = UCLASS_CLK,
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.of_match = mt7623_ethsys_compat,
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.probe = mt7623_ethsys_probe,
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+ .bind = mt7623_ethsys_bind,
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.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
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.ops = &mtk_clk_gate_ops,
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};
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diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c
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index 2601b6cf..6a9f6013 100644
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--- a/drivers/clk/mediatek/clk-mt7629.c
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+++ b/drivers/clk/mediatek/clk-mt7629.c
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@@ -8,6 +8,7 @@
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#include <common.h>
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#include <dm.h>
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+#include <asm/arch-mediatek/reset.h>
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#include <asm/io.h>
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#include <dt-bindings/clock/mt7629-clk.h>
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@@ -602,6 +603,19 @@ static int mt7629_ethsys_probe(struct udevice *dev)
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return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, eth_cgs);
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}
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+static int mt7629_ethsys_bind(struct udevice *dev)
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+{
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+ int ret = 0;
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+
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+#if CONFIG_IS_ENABLED(RESET_MEDIATEK)
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+ ret = mediatek_reset_bind(dev, ETHSYS_RST_CTRL_OFS, 1);
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+ if (ret)
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+ debug("Warning: failed to bind ethsys reset controller\n");
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+#endif
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+
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+ return ret;
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+}
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+
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static int mt7629_sgmiisys_probe(struct udevice *dev)
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{
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return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, sgmii_cgs);
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@@ -695,6 +709,7 @@ U_BOOT_DRIVER(mtk_clk_ethsys) = {
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.id = UCLASS_CLK,
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.of_match = mt7629_ethsys_compat,
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.probe = mt7629_ethsys_probe,
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+ .bind = mt7629_ethsys_bind,
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.priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
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.ops = &mtk_clk_gate_ops,
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};
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diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
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index 74152ed9..7847388b 100644
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--- a/drivers/clk/mediatek/clk-mtk.h
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+++ b/drivers/clk/mediatek/clk-mtk.h
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@@ -23,6 +23,8 @@
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#define CLK_PARENT_TOPCKGEN BIT(5)
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#define CLK_PARENT_MASK GENMASK(5, 4)
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+#define ETHSYS_RST_CTRL_OFS 0x34
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+
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/* struct mtk_pll_data - hardware-specific PLLs data */
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struct mtk_pll_data {
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const int id;
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--
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1.8.3.1
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