mirror of
https://github.com/Ysurac/openmptcprouter.git
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118 lines
3.3 KiB
Diff
118 lines
3.3 KiB
Diff
From 9f4c480f24e2ce1d464ff9d5f8a249a485acdc7f Mon Sep 17 00:00:00 2001
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From: Peter Geis <pgwipeout@gmail.com>
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Date: Fri, 8 Apr 2022 11:12:35 -0400
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Subject: [PATCH] arm64: dts: rockchip: add rk356x dwc3 usb3 nodes
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Add the dwc3 device nodes to the rk356x device trees.
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The rk3566 has one usb2 capable dwc3 otg controller and one usb3 capable
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dwc3 host controller.
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The rk3568 has one usb3 capable dwc3 otg controller and one usb3 capable
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dwc3 host controller.
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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Tested-by: Frank Wunderlich <frank-w@public-files.de>
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Link: https://lore.kernel.org/r/20220408151237.3165046-4-pgwipeout@gmail.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk3566.dtsi | 11 ++++++++
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arch/arm64/boot/dts/rockchip/rk3568.dtsi | 9 ++++++
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arch/arm64/boot/dts/rockchip/rk356x.dtsi | 35 +++++++++++++++++++++++-
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3 files changed, 54 insertions(+), 1 deletion(-)
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--- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
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@@ -6,6 +6,10 @@
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compatible = "rockchip,rk3566";
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};
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+&pipegrf {
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+ compatible = "rockchip,rk3566-pipe-grf", "syscon";
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+};
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+
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&power {
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power-domain@RK3568_PD_PIPE {
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reg = <RK3568_PD_PIPE>;
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@@ -18,3 +22,10 @@
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#power-domain-cells = <0>;
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};
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};
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+
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+&usb_host0_xhci {
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+ phys = <&usb2phy0_otg>;
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+ phy-names = "usb2-phy";
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+ extcon = <&usb2phy0>;
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+ maximum-speed = "high-speed";
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+};
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--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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@@ -113,6 +113,10 @@
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};
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};
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+&pipegrf {
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+ compatible = "rockchip,rk3568-pipe-grf", "syscon";
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+};
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+
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&power {
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power-domain@RK3568_PD_PIPE {
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reg = <RK3568_PD_PIPE>;
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@@ -128,3 +132,8 @@
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#power-domain-cells = <0>;
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};
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};
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+
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+&usb_host0_xhci {
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+ phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
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+ phy-names = "usb2-phy", "usb3-phy";
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+};
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -224,6 +224,40 @@
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status = "disabled";
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};
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+ usb_host0_xhci: usb@fcc00000 {
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+ compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
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+ reg = <0x0 0xfcc00000 0x0 0x400000>;
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+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
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+ <&cru ACLK_USB3OTG0>;
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+ clock-names = "ref_clk", "suspend_clk",
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+ "bus_clk";
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+ dr_mode = "host";
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+ phy_type = "utmi_wide";
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+ power-domains = <&power RK3568_PD_PIPE>;
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+ resets = <&cru SRST_USB3OTG0>;
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+ snps,dis_u2_susphy_quirk;
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+ status = "disabled";
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+ };
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+
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+ usb_host1_xhci: usb@fd000000 {
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+ compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
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+ reg = <0x0 0xfd000000 0x0 0x400000>;
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+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
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+ <&cru ACLK_USB3OTG1>;
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+ clock-names = "ref_clk", "suspend_clk",
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+ "bus_clk";
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+ dr_mode = "host";
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+ phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>;
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+ phy-names = "usb2-phy", "usb3-phy";
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+ phy_type = "utmi_wide";
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+ power-domains = <&power RK3568_PD_PIPE>;
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+ resets = <&cru SRST_USB3OTG1>;
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+ snps,dis_u2_susphy_quirk;
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+ status = "disabled";
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+ };
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+
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gic: interrupt-controller@fd400000 {
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compatible = "arm,gic-v3";
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reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
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@@ -291,7 +325,6 @@
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};
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pipegrf: syscon@fdc50000 {
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- compatible = "rockchip,rk3568-pipe-grf", "syscon";
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reg = <0x0 0xfdc50000 0x0 0x1000>;
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};
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