mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-03-09 15:40:20 +00:00
103 lines
3.5 KiB
Diff
103 lines
3.5 KiB
Diff
From 4501501b8f55b277f219eaf7e863d91ddb1d8af7 Mon Sep 17 00:00:00 2001
|
|
From: chunhui dai <chunhui.dai@mediatek.com>
|
|
Date: Wed, 31 Oct 2018 17:59:50 +0800
|
|
Subject: [PATCH 45/77] using different round rate for mt7623
|
|
|
|
Change-Id: Ifac315b09d691fe2c056212dd59ae50212417d58
|
|
CR-Id:
|
|
Feature:
|
|
---
|
|
drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 14 --------------
|
|
drivers/gpu/drm/mediatek/mtk_hdmi_phy.h | 2 --
|
|
drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 11 +++++++++++
|
|
drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 14 ++++++++++++++
|
|
4 files changed, 25 insertions(+), 16 deletions(-)
|
|
|
|
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
|
|
index 40e08df57f48..f014d65fa5ad 100644
|
|
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
|
|
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
|
|
@@ -15,20 +15,6 @@ static const struct phy_ops mtk_hdmi_phy_dev_ops = {
|
|
.owner = THIS_MODULE,
|
|
};
|
|
|
|
-long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
|
- unsigned long *parent_rate)
|
|
-{
|
|
- struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
|
|
-
|
|
- hdmi_phy->pll_rate = rate;
|
|
- if (rate <= 74250000)
|
|
- *parent_rate = rate;
|
|
- else
|
|
- *parent_rate = rate / 2;
|
|
-
|
|
- return rate;
|
|
-}
|
|
-
|
|
unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
|
|
unsigned long parent_rate)
|
|
{
|
|
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
|
|
index a173a27d7a40..76e352d088d0 100644
|
|
--- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
|
|
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
|
|
@@ -49,8 +49,6 @@ void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
|
|
void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
|
|
u32 val, u32 mask);
|
|
struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw);
|
|
-long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
|
- unsigned long *parent_rate);
|
|
unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
|
|
unsigned long parent_rate);
|
|
|
|
diff --git a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
|
|
index 534bcbc9f3b7..2f87d0320882 100644
|
|
--- a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
|
|
+++ b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
|
|
@@ -154,6 +154,17 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
return 0;
|
|
}
|
|
|
|
+static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
|
+ unsigned long *parent_rate)
|
|
+{
|
|
+ struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
|
|
+
|
|
+ hdmi_phy->pll_rate = rate;
|
|
+ *parent_rate = rate;
|
|
+
|
|
+ return rate;
|
|
+}
|
|
+
|
|
static const struct clk_ops mtk_hdmi_phy_pll_ops = {
|
|
.prepare = mtk_hdmi_pll_prepare,
|
|
.unprepare = mtk_hdmi_pll_unprepare,
|
|
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
|
|
index ed5916b27658..d8cb252c6781 100644
|
|
--- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
|
|
+++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
|
|
@@ -285,6 +285,20 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
return 0;
|
|
}
|
|
|
|
+static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
|
+ unsigned long *parent_rate)
|
|
+{
|
|
+ struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
|
|
+
|
|
+ hdmi_phy->pll_rate = rate;
|
|
+ if (rate <= 74250000)
|
|
+ *parent_rate = rate;
|
|
+ else
|
|
+ *parent_rate = rate / 2;
|
|
+
|
|
+ return rate;
|
|
+}
|
|
+
|
|
static const struct clk_ops mtk_hdmi_phy_pll_ops = {
|
|
.prepare = mtk_hdmi_pll_prepare,
|
|
.unprepare = mtk_hdmi_pll_unprepare,
|
|
--
|
|
2.19.1
|
|
|