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170 lines
5.1 KiB
Diff
170 lines
5.1 KiB
Diff
From a8f2332d49ab927de1081a230136316c846fde08 Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <mripard@kernel.org>
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Date: Fri, 21 Jun 2024 16:20:48 +0100
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Subject: [PATCH 594/697] drm/vc4: hvs: Create cob_init function
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Just like the HVS itself, the COB parameters will be fairly different in
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the BCM2712.
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Let's move the COB parameters computation and its initialisation to a
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separate function that will be easier to extend in the future.
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Signed-off-by: Maxime Ripard <mripard@kernel.org>
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Reviewed-by: Maxime Ripard <mripard@kernel.org>
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Link: https://patchwork.freedesktop.org/patch/msgid/20240621152055.4180873-25-dave.stevenson@raspberrypi.com
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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---
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drivers/gpu/drm/vc4/vc4_hvs.c | 128 ++++++++++++++++++++--------------
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1 file changed, 74 insertions(+), 54 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_hvs.c
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+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
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@@ -940,6 +940,77 @@ static int vc4_hvs_hw_init(struct vc4_hv
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return 0;
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}
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+static int vc4_hvs_cob_init(struct vc4_hvs *hvs)
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+{
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+ struct vc4_dev *vc4 = hvs->vc4;
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+ u32 reg, top;
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+
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+ /*
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+ * Recompute Composite Output Buffer (COB) allocations for the
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+ * displays
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+ */
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+ switch (vc4->gen) {
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+ case VC4_GEN_4:
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+ /* The COB is 20736 pixels, or just over 10 lines at 2048 wide.
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+ * The bottom 2048 pixels are full 32bpp RGBA (intended for the
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+ * TXP composing RGBA to memory), whilst the remainder are only
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+ * 24bpp RGB.
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+ *
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+ * Assign 3 lines to channels 1 & 2, and just over 4 lines to
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+ * channel 0.
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+ */
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+ #define VC4_COB_SIZE 20736
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+ #define VC4_COB_LINE_WIDTH 2048
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+ #define VC4_COB_NUM_LINES 3
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+ reg = 0;
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+ top = VC4_COB_LINE_WIDTH * VC4_COB_NUM_LINES;
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+ reg |= (top - 1) << 16;
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+ HVS_WRITE(SCALER_DISPBASE2, reg);
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+ reg = top;
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+ top += VC4_COB_LINE_WIDTH * VC4_COB_NUM_LINES;
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+ reg |= (top - 1) << 16;
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+ HVS_WRITE(SCALER_DISPBASE1, reg);
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+ reg = top;
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+ top = VC4_COB_SIZE;
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+ reg |= (top - 1) << 16;
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+ HVS_WRITE(SCALER_DISPBASE0, reg);
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+ break;
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+
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+ case VC4_GEN_5:
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+ /* The COB is 44416 pixels, or 10.8 lines at 4096 wide.
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+ * The bottom 4096 pixels are full RGBA (intended for the TXP
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+ * composing RGBA to memory), whilst the remainder are only
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+ * RGB. Addressing is always pixel wide.
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+ *
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+ * Assign 3 lines of 4096 to channels 1 & 2, and just over 4
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+ * lines. to channel 0.
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+ */
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+ #define VC5_COB_SIZE 44416
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+ #define VC5_COB_LINE_WIDTH 4096
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+ #define VC5_COB_NUM_LINES 3
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+ reg = 0;
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+ top = VC5_COB_LINE_WIDTH * VC5_COB_NUM_LINES;
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+ reg |= top << 16;
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+ HVS_WRITE(SCALER_DISPBASE2, reg);
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+ top += 16;
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+ reg = top;
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+ top += VC5_COB_LINE_WIDTH * VC5_COB_NUM_LINES;
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+ reg |= top << 16;
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+ HVS_WRITE(SCALER_DISPBASE1, reg);
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+ top += 16;
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+ reg = top;
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+ top = VC5_COB_SIZE;
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+ reg |= top << 16;
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+ HVS_WRITE(SCALER_DISPBASE0, reg);
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+ break;
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+
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+ default:
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+ return -EINVAL;
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+ }
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+
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+ return 0;
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+}
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+
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static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
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{
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struct platform_device *pdev = to_platform_device(dev);
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@@ -947,7 +1018,6 @@ static int vc4_hvs_bind(struct device *d
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struct vc4_dev *vc4 = to_vc4_dev(drm);
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struct vc4_hvs *hvs = NULL;
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int ret;
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- u32 reg, top;
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hvs = __vc4_hvs_alloc(vc4, NULL);
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if (IS_ERR(hvs))
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@@ -1017,59 +1087,9 @@ static int vc4_hvs_bind(struct device *d
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if (ret)
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return ret;
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- /* Recompute Composite Output Buffer (COB) allocations for the displays
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- */
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- if (vc4->gen == VC4_GEN_4) {
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- /* The COB is 20736 pixels, or just over 10 lines at 2048 wide.
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- * The bottom 2048 pixels are full 32bpp RGBA (intended for the
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- * TXP composing RGBA to memory), whilst the remainder are only
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- * 24bpp RGB.
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- *
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- * Assign 3 lines to channels 1 & 2, and just over 4 lines to
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- * channel 0.
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- */
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- #define VC4_COB_SIZE 20736
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- #define VC4_COB_LINE_WIDTH 2048
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- #define VC4_COB_NUM_LINES 3
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- reg = 0;
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- top = VC4_COB_LINE_WIDTH * VC4_COB_NUM_LINES;
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- reg |= (top - 1) << 16;
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- HVS_WRITE(SCALER_DISPBASE2, reg);
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- reg = top;
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- top += VC4_COB_LINE_WIDTH * VC4_COB_NUM_LINES;
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- reg |= (top - 1) << 16;
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- HVS_WRITE(SCALER_DISPBASE1, reg);
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- reg = top;
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- top = VC4_COB_SIZE;
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- reg |= (top - 1) << 16;
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- HVS_WRITE(SCALER_DISPBASE0, reg);
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- } else {
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- /* The COB is 44416 pixels, or 10.8 lines at 4096 wide.
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- * The bottom 4096 pixels are full RGBA (intended for the TXP
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- * composing RGBA to memory), whilst the remainder are only
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- * RGB. Addressing is always pixel wide.
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- *
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- * Assign 3 lines of 4096 to channels 1 & 2, and just over 4
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- * lines. to channel 0.
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- */
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- #define VC5_COB_SIZE 44416
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- #define VC5_COB_LINE_WIDTH 4096
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- #define VC5_COB_NUM_LINES 3
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- reg = 0;
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- top = VC5_COB_LINE_WIDTH * VC5_COB_NUM_LINES;
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- reg |= top << 16;
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- HVS_WRITE(SCALER_DISPBASE2, reg);
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- top += 16;
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- reg = top;
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- top += VC5_COB_LINE_WIDTH * VC5_COB_NUM_LINES;
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- reg |= top << 16;
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- HVS_WRITE(SCALER_DISPBASE1, reg);
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- top += 16;
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- reg = top;
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- top = VC5_COB_SIZE;
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- reg |= top << 16;
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- HVS_WRITE(SCALER_DISPBASE0, reg);
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- }
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+ ret = vc4_hvs_cob_init(hvs);
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+ if (ret)
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+ return ret;
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ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
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vc4_hvs_irq_handler, 0, "vc4 hvs", drm);
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