mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-02-15 04:42:02 +00:00
94 lines
2.6 KiB
Diff
94 lines
2.6 KiB
Diff
--- a/arch/arm64/Kconfig
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+++ b/arch/arm64/Kconfig
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@@ -1132,6 +1132,14 @@ config SOCIONEXT_SYNQUACER_PREITS
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If unsure, say Y.
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+config ROCKCHIP_ERRATUM_114514
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+ bool "Rockchip RK3568 force no_local_cache"
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+ default y
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+ help
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+ They consider this as a SoC implement design instead of a bug.
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+
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+ If unsure, say Y.
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+
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endmenu # "ARM errata workarounds via the alternatives framework"
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choice
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--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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@@ -64,7 +64,7 @@
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compatible = "rockchip,rk3568-pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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- bus-range = <0x0 0xf>;
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+ bus-range = <0x10 0x1f>;
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clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
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<&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
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<&cru CLK_PCIE30X1_AUX_NDFT>;
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@@ -87,7 +87,7 @@
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num-ib-windows = <6>;
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num-ob-windows = <2>;
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max-link-speed = <3>;
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- msi-map = <0x0 &gic 0x1000 0x1000>;
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+ msi-map = <0x1000 &its 0x1000 0x1000>;
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num-lanes = <1>;
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phys = <&pcie30phy>;
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phy-names = "pcie-phy";
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@@ -116,7 +116,7 @@
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compatible = "rockchip,rk3568-pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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- bus-range = <0x0 0xf>;
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+ bus-range = <0x20 0x2f>;
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clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
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<&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
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<&cru CLK_PCIE30X2_AUX_NDFT>;
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@@ -139,7 +139,7 @@
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num-ib-windows = <6>;
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num-ob-windows = <2>;
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max-link-speed = <3>;
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- msi-map = <0x0 &gic 0x2000 0x1000>;
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+ msi-map = <0x2000 &its 0x2000 0x1000>;
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num-lanes = <2>;
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phys = <&pcie30phy>;
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phy-names = "pcie-phy";
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -315,14 +315,21 @@
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gic: interrupt-controller@fd400000 {
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compatible = "arm,gic-v3";
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+ #interrupt-cells = <3>;
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+ interrupt-controller;
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+
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reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
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- <0x0 0xfd460000 0 0x80000>; /* GICR */
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+ <0x0 0xfd460000 0 0xc0000>; /* GICR */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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- interrupt-controller;
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- #interrupt-cells = <3>;
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- mbi-alias = <0x0 0xfd410000>;
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- mbi-ranges = <296 24>;
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- msi-controller;
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+ its: interrupt-controller@fd440000 {
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+ compatible = "arm,gic-v3-its";
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+ msi-controller;
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+ #msi-cells = <1>;
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+ reg = <0x0 0xfd440000 0x0 0x20000>;
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+ };
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};
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usb_host0_ehci: usb@fd800000 {
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@@ -977,7 +984,7 @@
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num-ib-windows = <6>;
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num-ob-windows = <2>;
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max-link-speed = <2>;
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- msi-map = <0x0 &gic 0x0 0x1000>;
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+ msi-map = <0x0 &its 0x0 0x1000>;
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num-lanes = <1>;
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phys = <&combphy2 PHY_TYPE_PCIE>;
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phy-names = "pcie-phy";
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