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https://github.com/Ysurac/openmptcprouter.git
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120 lines
2.9 KiB
Diff
120 lines
2.9 KiB
Diff
From 7388400b8bd42f71d040dbf2fdbdcb834fcc0ede Mon Sep 17 00:00:00 2001
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From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
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Date: Sat, 30 Jan 2021 10:50:13 +0530
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Subject: [PATCH] arm64: dts: qcom: Enable Q6v5 WCSS for ipq8074 SoC
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Enable remoteproc WCSS PIL driver with glink and ssr subdevices.
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Also enables smp2p and mailboxes required for IPC.
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Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
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Signed-off-by: Sricharan R <sricharan@codeaurora.org>
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Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 81 +++++++++++++++++++++++++++
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1 file changed, 81 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -140,6 +140,32 @@
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};
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};
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+ wcss: smp2p-wcss {
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+ compatible = "qcom,smp2p";
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+ qcom,smem = <435>, <428>;
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <0 322 1>;
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+
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+ mboxes = <&apcs_glb 9>;
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+
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+ qcom,local-pid = <0>;
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+ qcom,remote-pid = <1>;
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+
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+ wcss_smp2p_out: master-kernel {
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+ qcom,entry-name = "master-kernel";
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+ qcom,smp2p-feature-ssr-ack;
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+ #qcom,smem-state-cells = <1>;
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+ };
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+
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+ wcss_smp2p_in: slave-kernel {
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+ qcom,entry-name = "slave-kernel";
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+
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+ interrupt-controller;
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+ #interrupt-cells = <2>;
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+ };
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+ };
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+
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soc: soc {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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@@ -409,6 +435,11 @@
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#hwlock-cells = <1>;
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};
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+ tcsr_q6: syscon@1945000 {
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+ compatible = "syscon";
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+ reg = <0x01945000 0xe000>;
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+ };
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+
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spmi_bus: spmi@200f000 {
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compatible = "qcom,spmi-pmic-arb";
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reg = <0x0200f000 0x001000>,
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@@ -917,6 +948,56 @@
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"axi_s_sticky";
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status = "disabled";
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};
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+
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+ q6v5_wcss: q6v5_wcss@cd00000 {
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+ compatible = "qcom,ipq8074-wcss-pil";
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+ reg = <0x0cd00000 0x4040>,
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+ <0x004ab000 0x20>;
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+ reg-names = "qdsp6",
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+ "rmb";
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+ qca,auto-restart;
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+ qca,extended-intc;
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+ interrupts-extended = <&intc 0 325 1>,
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+ <&wcss_smp2p_in 0 0>,
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+ <&wcss_smp2p_in 1 0>,
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+ <&wcss_smp2p_in 2 0>,
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+ <&wcss_smp2p_in 3 0>;
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+ interrupt-names = "wdog",
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+ "fatal",
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+ "ready",
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+ "handover",
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+ "stop-ack";
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+
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+ resets = <&gcc GCC_WCSSAON_RESET>,
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+ <&gcc GCC_WCSS_BCR>,
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+ <&gcc GCC_WCSS_Q6_BCR>;
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+
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+ reset-names = "wcss_aon_reset",
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+ "wcss_reset",
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+ "wcss_q6_reset";
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+
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+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
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+ clock-names = "prng";
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+
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+ qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>;
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+
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+ qcom,smem-states = <&wcss_smp2p_out 0>,
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+ <&wcss_smp2p_out 1>;
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+ qcom,smem-state-names = "shutdown",
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+ "stop";
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+
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+ memory-region = <&q6_region>;
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+
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+ glink-edge {
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+ interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
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+ qcom,remote-pid = <1>;
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+ mboxes = <&apcs_glb 8>;
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+
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+ rpm_requests {
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+ qcom,glink-channels = "IPCRTR";
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+ };
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+ };
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+ };
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};
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timer {
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