mirror of
https://github.com/Ysurac/openmptcprouter.git
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251 lines
7.1 KiB
Diff
251 lines
7.1 KiB
Diff
From a82fe567148fa2fd31340f0eda5c9760ff4169d1 Mon Sep 17 00:00:00 2001
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From: Matthias Reichl <hias@horus.com>
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Date: Sun, 7 May 2017 15:30:50 +0200
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Subject: [PATCH 123/277] ASoC: bcm2835: Support left/right justified and DSP
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modes
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DSP modes and left/right justified modes can be supported
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on bcm2835 by configuring the frame sync polarity and
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frame sync length registers and by adjusting the
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channel data position registers.
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Clock and frame sync polarity handling in hw_params has
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been refactored to make the interaction between logical
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rising/falling edge frame start and physical configuration
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(changed by normal/inverted polarity modes) clearer.
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Modes where the first active data bit is transmitted immediately
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after frame start (eg DSP mode B with slot 0 active)
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only work reliable if bcm2835 is configured as frame master.
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In frame slave mode channel swap (or shift, this isn't quite
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clear yet) can occur.
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Currently the driver only warns if an unstable configuration
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is detected but doensn't prevent using them.
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Signed-off-by: Matthias Reichl <hias@horus.com>
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---
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sound/soc/bcm/bcm2835-i2s.c | 152 +++++++++++++++++++++++++++++---------------
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1 file changed, 99 insertions(+), 53 deletions(-)
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diff --git a/sound/soc/bcm/bcm2835-i2s.c b/sound/soc/bcm/bcm2835-i2s.c
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index dcacf7f83c93..3a706fda4f39 100644
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--- a/sound/soc/bcm/bcm2835-i2s.c
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+++ b/sound/soc/bcm/bcm2835-i2s.c
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@@ -344,6 +344,9 @@ static int bcm2835_i2s_hw_params(struct snd_pcm_substream *substream,
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unsigned int rx_mask, tx_mask;
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unsigned int rx_ch1_pos, rx_ch2_pos, tx_ch1_pos, tx_ch2_pos;
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unsigned int mode, format;
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+ bool bit_clock_master = false;
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+ bool frame_sync_master = false;
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+ bool frame_start_falling_edge = false;
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uint32_t csreg;
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int ret = 0;
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@@ -387,16 +390,39 @@ static int bcm2835_i2s_hw_params(struct snd_pcm_substream *substream,
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if (data_length > slot_width)
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return -EINVAL;
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- /* Clock should only be set up here if CPU is clock master */
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+ /* Check if CPU is bit clock master */
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switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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case SND_SOC_DAIFMT_CBS_CFM:
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- ret = clk_set_rate(dev->clk, bclk_rate);
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- if (ret)
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- return ret;
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+ bit_clock_master = true;
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+ break;
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+ case SND_SOC_DAIFMT_CBM_CFS:
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+ case SND_SOC_DAIFMT_CBM_CFM:
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+ bit_clock_master = false;
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break;
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default:
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+ return -EINVAL;
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+ }
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+
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+ /* Check if CPU is frame sync master */
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+ switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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+ case SND_SOC_DAIFMT_CBS_CFS:
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+ case SND_SOC_DAIFMT_CBM_CFS:
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+ frame_sync_master = true;
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+ break;
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+ case SND_SOC_DAIFMT_CBS_CFM:
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+ case SND_SOC_DAIFMT_CBM_CFM:
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+ frame_sync_master = false;
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break;
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+ default:
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+ return -EINVAL;
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+ }
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+
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+ /* Clock should only be set up here if CPU is clock master */
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+ if (bit_clock_master) {
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+ ret = clk_set_rate(dev->clk, bclk_rate);
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+ if (ret)
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+ return ret;
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}
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/* Setup the frame format */
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@@ -427,13 +453,41 @@ static int bcm2835_i2s_hw_params(struct snd_pcm_substream *substream,
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/* Setup frame sync signal for 50% duty cycle */
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framesync_length = frame_length / 2;
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+ frame_start_falling_edge = true;
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+ break;
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+ case SND_SOC_DAIFMT_LEFT_J:
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+ if (slots & 1)
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+ return -EINVAL;
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+
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+ odd_slot_offset = slots >> 1;
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+ data_delay = 0;
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+ framesync_length = frame_length / 2;
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+ frame_start_falling_edge = false;
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+ break;
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+ case SND_SOC_DAIFMT_RIGHT_J:
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+ if (slots & 1)
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+ return -EINVAL;
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+
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+ /* Odd frame lengths aren't supported */
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+ if (frame_length & 1)
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+ return -EINVAL;
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+
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+ odd_slot_offset = slots >> 1;
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+ data_delay = slot_width - data_length;
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+ framesync_length = frame_length / 2;
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+ frame_start_falling_edge = false;
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+ break;
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+ case SND_SOC_DAIFMT_DSP_A:
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+ data_delay = 1;
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+ framesync_length = 1;
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+ frame_start_falling_edge = false;
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+ break;
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+ case SND_SOC_DAIFMT_DSP_B:
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+ data_delay = 0;
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+ framesync_length = 1;
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+ frame_start_falling_edge = false;
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break;
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default:
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- /*
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- * TODO
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- * Others are possible but are not implemented at the moment.
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- */
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- dev_err(dev->dev, "%s:bad format\n", __func__);
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return -EINVAL;
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}
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@@ -442,6 +496,15 @@ static int bcm2835_i2s_hw_params(struct snd_pcm_substream *substream,
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bcm2835_i2s_calc_channel_pos(&tx_ch1_pos, &tx_ch2_pos,
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tx_mask, slot_width, data_delay, odd_slot_offset);
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+ /*
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+ * Transmitting data immediately after frame start, eg
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+ * in left-justified or DSP mode A, only works stable
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+ * if bcm2835 is the frame clock master.
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+ */
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+ if ((!rx_ch1_pos || !tx_ch1_pos) && !frame_sync_master)
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+ dev_warn(dev->dev,
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+ "Unstable slave config detected, L/R may be swapped");
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+
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/*
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* Set format for both streams.
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* We cannot set another frame length
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@@ -472,62 +535,38 @@ static int bcm2835_i2s_hw_params(struct snd_pcm_substream *substream,
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mode |= BCM2835_I2S_FLEN(frame_length - 1);
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mode |= BCM2835_I2S_FSLEN(framesync_length);
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- /* Master or slave? */
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- switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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- case SND_SOC_DAIFMT_CBS_CFS:
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- /* CPU is master */
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- break;
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- case SND_SOC_DAIFMT_CBM_CFS:
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- /*
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- * CODEC is bit clock master
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- * CPU is frame master
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- */
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+ /* CLKM selects bcm2835 clock slave mode */
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+ if (!bit_clock_master)
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mode |= BCM2835_I2S_CLKM;
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- break;
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- case SND_SOC_DAIFMT_CBS_CFM:
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- /*
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- * CODEC is frame master
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- * CPU is bit clock master
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- */
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+
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+ /* FSM selects bcm2835 frame sync slave mode */
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+ if (!frame_sync_master)
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mode |= BCM2835_I2S_FSM;
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+
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+ /* CLKI selects normal clocking mode, sampling on rising edge */
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+ switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) {
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+ case SND_SOC_DAIFMT_NB_NF:
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+ case SND_SOC_DAIFMT_NB_IF:
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+ mode |= BCM2835_I2S_CLKI;
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break;
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- case SND_SOC_DAIFMT_CBM_CFM:
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- /* CODEC is master */
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- mode |= BCM2835_I2S_CLKM;
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- mode |= BCM2835_I2S_FSM;
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+ case SND_SOC_DAIFMT_IB_NF:
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+ case SND_SOC_DAIFMT_IB_IF:
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break;
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default:
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- dev_err(dev->dev, "%s:bad master\n", __func__);
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return -EINVAL;
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}
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- /*
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- * Invert clocks?
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- *
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- * The BCM approach seems to be inverted to the classical I2S approach.
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- */
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+ /* FSI selects frame start on falling edge */
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switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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- /* None. Therefore, both for BCM */
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- mode |= BCM2835_I2S_CLKI;
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- mode |= BCM2835_I2S_FSI;
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- break;
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- case SND_SOC_DAIFMT_IB_IF:
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- /* Both. Therefore, none for BCM */
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+ case SND_SOC_DAIFMT_IB_NF:
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+ if (frame_start_falling_edge)
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+ mode |= BCM2835_I2S_FSI;
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break;
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case SND_SOC_DAIFMT_NB_IF:
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- /*
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- * Invert only frame sync. Therefore,
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- * invert only bit clock for BCM
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- */
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- mode |= BCM2835_I2S_CLKI;
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- break;
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- case SND_SOC_DAIFMT_IB_NF:
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- /*
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- * Invert only bit clock. Therefore,
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- * invert only frame sync for BCM
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- */
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- mode |= BCM2835_I2S_FSI;
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+ case SND_SOC_DAIFMT_IB_IF:
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+ if (!frame_start_falling_edge)
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+ mode |= BCM2835_I2S_FSI;
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break;
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default:
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return -EINVAL;
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@@ -563,6 +602,13 @@ static int bcm2835_i2s_hw_params(struct snd_pcm_substream *substream,
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dev_dbg(dev->dev, "sampling rate: %d bclk rate: %d\n",
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params_rate(params), bclk_rate);
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+ dev_dbg(dev->dev, "CLKM: %d CLKI: %d FSM: %d FSI: %d frame start: %s edge\n",
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+ !!(mode & BCM2835_I2S_CLKM),
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+ !!(mode & BCM2835_I2S_CLKI),
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+ !!(mode & BCM2835_I2S_FSM),
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+ !!(mode & BCM2835_I2S_FSI),
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+ (mode & BCM2835_I2S_FSI) ? "falling" : "rising");
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+
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return ret;
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}
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--
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2.16.1
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