mirror of
https://github.com/Ysurac/openmptcprouter.git
synced 2025-02-13 03:41:54 +00:00
7720 lines
292 KiB
Diff
7720 lines
292 KiB
Diff
From 7d933370e999abf6a25624597f3cb1a15a62d3e2 Mon Sep 17 00:00:00 2001
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From: DENG Qingfang <dengqf6@mail2.sysu.edu.cn>
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Date: Wed, 4 Mar 2020 20:46:10 +0800
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Subject: [PATCH 1/4] mvebu: copy files and patches to 5.4
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Signed-off-by: DENG Qingfang <dengqf6@mail2.sysu.edu.cn>
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---
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target/linux/mvebu/config-5.4 | 498 +++++++++++
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target/linux/mvebu/cortexa53/config-5.4 | 169 ++++
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target/linux/mvebu/cortexa72/config-5.4 | 176 ++++
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.../arm/boot/dts/armada-385-linksys-venom.dts | 213 +++++
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.../marvell/armada-3720-espressobin-emmc.dts | 28 +
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.../armada-3720-espressobin-v7-emmc.dts | 43 +
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.../marvell/armada-3720-espressobin-v7.dts | 31 +
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.../boot/dts/marvell/armada-3720-uDPU.dts | 162 ++++
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.../patches-5.4/002-add_powertables.patch | 770 ++++++++++++++++++
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.../patches-5.4/003-add_switch_nodes.patch | 40 +
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.../004-add_sata_disk_activity_trigger.patch | 39 +
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...5-linksys_hardcode_nand_ecc_settings.patch | 17 +
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...Mangle-bootloader-s-kernel-arguments.patch | 201 +++++
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.../patches-5.4/100-find_active_root.patch | 60 ++
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.../patches-5.4/102-revert_i2c_delay.patch | 15 +
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.../205-armada-385-rd-mtd-partitions.patch | 19 +
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.../206-ARM-mvebu-385-ap-Add-partitions.patch | 35 +
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.../210-clearfog_switch_node.patch | 21 +
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.../220-disable-untested-dsa-boards.patch | 30 +
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...-armada-xp-linksys-mamba-broken-idle.patch | 10 +
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.../patches-5.4/240-linksys-status-led.patch | 50 ++
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.../300-mvneta-tx-queue-workaround.patch | 35 +
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...dicate-failure-to-enter-deeper-sleep.patch | 40 +
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...-pci-mvebu-time-out-reset-on-link-up.patch | 60 ++
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...da388-clearfog-emmc-on-clearfog-base.patch | 87 ++
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...rmada388-clearfog-document-MPP-usage.patch | 124 +++
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...l-armada37xx-Add-emmc-sdio-pinctrl-d.patch | 40 +
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...l-armada-37xx-Enable-emmc-on-espress.patch | 49 ++
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...ts-marvell-armada37xx-Add-eth0-alias.patch | 20 +
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...da-3720-espressobin-correct-spi-node.patch | 58 ++
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...l-armada-3720-espressobin-add-ports-.patch | 26 +
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...rdvark-Convert-to-use-pci_host_probe.patch | 44 +
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...-device-to-the-same-MAX-payload-size.patch | 138 ++++
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...ardvark-disable-LOS-state-by-default.patch | 55 ++
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...ark-allow-to-specify-link-capability.patch | 43 +
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...-3720-espressobin-set-max-link-to-ge.patch | 73 ++
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...vneta-Add-support-for-2500Mbps-SGMII.patch | 104 +++
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.../532-net-mvneta-correct-typo.patch | 33 +
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...net-mvneta-Dont-advertise-2.5G-modes.patch | 55 ++
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...et-mvneta-remove-redundant-check-for.patch | 30 +
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...-net-marvell-neta-add-comphy-support.patch | 159 ++++
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...eta-disable-comphy-when-setting-mode.patch | 78 ++
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...537-net-mvneta-add-2500baset-support.patch | 34 +
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.../538-phy-add-QSGMII-and-PCIE-modes.patch | 28 +
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.../539-phy-core-add-PHY_MODE_ETHERNET.patch | 24 +
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...fix-build-breakage-add-PHY_MODE_SATA.patch | 45 +
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...phy_set_mode-to-accept-phy-mode-and-.patch | 134 +++
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.../542-phy-add-A3700-COMPHY-support.patch | 381 +++++++++
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...rvell-armada-37xx-declare-the-COMPHY.patch | 58 ++
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...rm64-dts-uDPU-fix-comphy-definitions.patch | 35 +
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...-arm64-dts-uDPU-remove-i2c-fast-mode.patch | 30 +
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...ts-uDPU-SFP-cages-support-3W-modules.patch | 33 +
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52 files changed, 4780 insertions(+)
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create mode 100644 target/linux/mvebu/config-5.4
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create mode 100644 target/linux/mvebu/cortexa53/config-5.4
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create mode 100644 target/linux/mvebu/cortexa72/config-5.4
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create mode 100644 target/linux/mvebu/files-5.4/arch/arm/boot/dts/armada-385-linksys-venom.dts
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create mode 100644 target/linux/mvebu/files-5.4/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts
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create mode 100644 target/linux/mvebu/files-5.4/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts
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create mode 100644 target/linux/mvebu/files-5.4/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts
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create mode 100644 target/linux/mvebu/files-5.4/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts
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create mode 100644 target/linux/mvebu/patches-5.4/002-add_powertables.patch
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create mode 100644 target/linux/mvebu/patches-5.4/003-add_switch_nodes.patch
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create mode 100644 target/linux/mvebu/patches-5.4/004-add_sata_disk_activity_trigger.patch
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create mode 100644 target/linux/mvebu/patches-5.4/005-linksys_hardcode_nand_ecc_settings.patch
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create mode 100644 target/linux/mvebu/patches-5.4/006-mvebu-Mangle-bootloader-s-kernel-arguments.patch
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create mode 100644 target/linux/mvebu/patches-5.4/100-find_active_root.patch
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create mode 100644 target/linux/mvebu/patches-5.4/102-revert_i2c_delay.patch
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create mode 100644 target/linux/mvebu/patches-5.4/205-armada-385-rd-mtd-partitions.patch
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create mode 100644 target/linux/mvebu/patches-5.4/206-ARM-mvebu-385-ap-Add-partitions.patch
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create mode 100644 target/linux/mvebu/patches-5.4/210-clearfog_switch_node.patch
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create mode 100644 target/linux/mvebu/patches-5.4/220-disable-untested-dsa-boards.patch
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create mode 100644 target/linux/mvebu/patches-5.4/230-armada-xp-linksys-mamba-broken-idle.patch
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create mode 100644 target/linux/mvebu/patches-5.4/240-linksys-status-led.patch
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create mode 100644 target/linux/mvebu/patches-5.4/300-mvneta-tx-queue-workaround.patch
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create mode 100644 target/linux/mvebu/patches-5.4/400-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch
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create mode 100644 target/linux/mvebu/patches-5.4/401-pci-mvebu-time-out-reset-on-link-up.patch
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create mode 100644 target/linux/mvebu/patches-5.4/412-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch
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create mode 100644 target/linux/mvebu/patches-5.4/415-ARM-dts-armada388-clearfog-document-MPP-usage.patch
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create mode 100644 target/linux/mvebu/patches-5.4/513-arm64-dts-marvell-armada37xx-Add-emmc-sdio-pinctrl-d.patch
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create mode 100644 target/linux/mvebu/patches-5.4/514-arm64-dts-marvell-armada-37xx-Enable-emmc-on-espress.patch
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create mode 100644 target/linux/mvebu/patches-5.4/520-arm64-dts-marvell-armada37xx-Add-eth0-alias.patch
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create mode 100644 target/linux/mvebu/patches-5.4/521-arm64-dts-armada-3720-espressobin-correct-spi-node.patch
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create mode 100644 target/linux/mvebu/patches-5.4/522-arm64-dts-marvell-armada-3720-espressobin-add-ports-.patch
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create mode 100644 target/linux/mvebu/patches-5.4/523-Revert-PCI-aardvark-Convert-to-use-pci_host_probe.patch
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create mode 100644 target/linux/mvebu/patches-5.4/524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch
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create mode 100644 target/linux/mvebu/patches-5.4/526-PCI-aardvark-disable-LOS-state-by-default.patch
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create mode 100644 target/linux/mvebu/patches-5.4/527-PCI-aardvark-allow-to-specify-link-capability.patch
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create mode 100644 target/linux/mvebu/patches-5.4/528-arm64-dts-armada-3720-espressobin-set-max-link-to-ge.patch
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create mode 100644 target/linux/mvebu/patches-5.4/531-net-mvneta-Add-support-for-2500Mbps-SGMII.patch
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create mode 100644 target/linux/mvebu/patches-5.4/532-net-mvneta-correct-typo.patch
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create mode 100644 target/linux/mvebu/patches-5.4/533-net-mvneta-Dont-advertise-2.5G-modes.patch
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create mode 100644 target/linux/mvebu/patches-5.4/534-net-mvneta-remove-redundant-check-for.patch
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create mode 100644 target/linux/mvebu/patches-5.4/535-net-marvell-neta-add-comphy-support.patch
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create mode 100644 target/linux/mvebu/patches-5.4/536-net-marvell-neta-disable-comphy-when-setting-mode.patch
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create mode 100644 target/linux/mvebu/patches-5.4/537-net-mvneta-add-2500baset-support.patch
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create mode 100644 target/linux/mvebu/patches-5.4/538-phy-add-QSGMII-and-PCIE-modes.patch
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create mode 100644 target/linux/mvebu/patches-5.4/539-phy-core-add-PHY_MODE_ETHERNET.patch
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create mode 100644 target/linux/mvebu/patches-5.4/540-phy-fix-build-breakage-add-PHY_MODE_SATA.patch
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create mode 100644 target/linux/mvebu/patches-5.4/541-phy-core-rework-phy_set_mode-to-accept-phy-mode-and-.patch
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create mode 100644 target/linux/mvebu/patches-5.4/542-phy-add-A3700-COMPHY-support.patch
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create mode 100644 target/linux/mvebu/patches-5.4/543-arm64-dts-marvell-armada-37xx-declare-the-COMPHY.patch
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create mode 100644 target/linux/mvebu/patches-5.4/544-arm64-dts-uDPU-fix-comphy-definitions.patch
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create mode 100644 target/linux/mvebu/patches-5.4/545-arm64-dts-uDPU-remove-i2c-fast-mode.patch
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create mode 100644 target/linux/mvebu/patches-5.4/546-arm64-dts-uDPU-SFP-cages-support-3W-modules.patch
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diff --git a/target/linux/mvebu/config-5.4 b/target/linux/mvebu/config-5.4
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new file mode 100644
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index 00000000000..24093fd386a
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--- /dev/null
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+++ b/target/linux/mvebu/config-5.4
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@@ -0,0 +1,498 @@
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+CONFIG_AHCI_MVEBU=y
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+CONFIG_ALIGNMENT_TRAP=y
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+CONFIG_ARCH_CLOCKSOURCE_DATA=y
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+CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
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+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
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+CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
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+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
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+CONFIG_ARCH_HAS_KCOV=y
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+CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
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+CONFIG_ARCH_HAS_PHYS_TO_DMA=y
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+CONFIG_ARCH_HAS_SET_MEMORY=y
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+CONFIG_ARCH_HAS_SG_CHAIN=y
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+CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
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+CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
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+CONFIG_ARCH_HAS_TICK_BROADCAST=y
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+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
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+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
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+CONFIG_ARCH_MULTIPLATFORM=y
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+CONFIG_ARCH_MULTI_V6_V7=y
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+CONFIG_ARCH_MULTI_V7=y
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+CONFIG_ARCH_MVEBU=y
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+CONFIG_ARCH_NR_GPIO=0
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+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
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+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
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+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
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+CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
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+CONFIG_ARCH_SUPPORTS_UPROBES=y
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+CONFIG_ARCH_SUSPEND_POSSIBLE=y
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+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
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+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
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+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
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+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
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+CONFIG_ARM=y
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+CONFIG_ARMADA_370_CLK=y
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+CONFIG_ARMADA_370_XP_IRQ=y
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+CONFIG_ARMADA_370_XP_TIMER=y
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+CONFIG_ARMADA_38X_CLK=y
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+CONFIG_ARMADA_THERMAL=y
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+CONFIG_ARMADA_XP_CLK=y
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+CONFIG_ARM_APPENDED_DTB=y
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+# CONFIG_ARM_ARMADA_37XX_CPUFREQ is not set
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+CONFIG_ARM_ATAG_DTB_COMPAT=y
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+# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
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+# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
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+CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y
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+CONFIG_ARM_CPU_SUSPEND=y
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+CONFIG_ARM_CRYPTO=y
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+CONFIG_ARM_ERRATA_720789=y
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+CONFIG_ARM_ERRATA_764369=y
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+CONFIG_ARM_GIC=y
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+CONFIG_ARM_GLOBAL_TIMER=y
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+CONFIG_ARM_HAS_SG_CHAIN=y
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+CONFIG_ARM_HEAVY_MB=y
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+CONFIG_ARM_L1_CACHE_SHIFT=6
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+CONFIG_ARM_L1_CACHE_SHIFT_6=y
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+# CONFIG_ARM_LPAE is not set
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+CONFIG_ARM_MVEBU_V7_CPUIDLE=y
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+CONFIG_ARM_PATCH_IDIV=y
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+CONFIG_ARM_PATCH_PHYS_VIRT=y
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+CONFIG_ARM_THUMB=y
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+# CONFIG_ARM_THUMBEE is not set
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+CONFIG_ARM_UNWIND=y
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+CONFIG_ARM_VIRT_EXT=y
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+CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
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+CONFIG_ATA=y
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+CONFIG_ATAGS=y
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+CONFIG_AUTO_ZRELADDR=y
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+CONFIG_BLK_DEV_LOOP=y
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+CONFIG_BLK_DEV_SD=y
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+CONFIG_BLK_MQ_PCI=y
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+CONFIG_BLK_SCSI_REQUEST=y
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+CONFIG_BOUNCE=y
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+# CONFIG_CACHE_FEROCEON_L2 is not set
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+CONFIG_CACHE_L2X0=y
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+CONFIG_CLKDEV_LOOKUP=y
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+CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
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+CONFIG_CLKSRC_MMIO=y
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+CONFIG_CLONE_BACKWARDS=y
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+CONFIG_COMMON_CLK=y
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+CONFIG_CPUFREQ_DT=y
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+CONFIG_CPUFREQ_DT_PLATDEV=y
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+CONFIG_CPU_32v6K=y
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+CONFIG_CPU_32v7=y
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+CONFIG_CPU_ABRT_EV7=y
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+# CONFIG_CPU_BIG_ENDIAN is not set
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+# CONFIG_CPU_BPREDICT_DISABLE is not set
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+CONFIG_CPU_CACHE_V7=y
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+CONFIG_CPU_CACHE_VIPT=y
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+CONFIG_CPU_COPY_V6=y
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+CONFIG_CPU_CP15=y
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+CONFIG_CPU_CP15_MMU=y
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+CONFIG_CPU_FREQ=y
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+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
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+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
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+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
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+CONFIG_CPU_FREQ_GOV_COMMON=y
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+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
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+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
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+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
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+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
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+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
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+CONFIG_CPU_FREQ_STAT=y
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+CONFIG_CPU_HAS_ASID=y
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+# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
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+# CONFIG_CPU_ICACHE_DISABLE is not set
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+CONFIG_CPU_IDLE=y
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+CONFIG_CPU_IDLE_GOV_LADDER=y
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+CONFIG_CPU_PABRT_V7=y
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+CONFIG_CPU_PJ4B=y
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+CONFIG_CPU_PM=y
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+CONFIG_CPU_RMAP=y
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+CONFIG_CPU_SPECTRE=y
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+CONFIG_CPU_THERMAL=y
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+CONFIG_CPU_THUMB_CAPABLE=y
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+CONFIG_CPU_TLB_V7=y
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+CONFIG_CPU_V7=y
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+CONFIG_CRC16=y
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+CONFIG_CRYPTO_ACOMP2=y
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+CONFIG_CRYPTO_AEAD=y
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+CONFIG_CRYPTO_AEAD2=y
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+CONFIG_CRYPTO_AES_ARM=y
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+CONFIG_CRYPTO_AES_ARM_BS=y
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+# CONFIG_CRYPTO_AES_ARM_CE is not set
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+# CONFIG_CRYPTO_CHACHA20_NEON is not set
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+CONFIG_CRYPTO_CRC32=y
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+CONFIG_CRYPTO_CRC32C=y
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+# CONFIG_CRYPTO_CRC32_ARM_CE is not set
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+CONFIG_CRYPTO_CRYPTD=y
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+CONFIG_CRYPTO_DEFLATE=y
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+CONFIG_CRYPTO_DES=y
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+CONFIG_CRYPTO_DEV_MARVELL_CESA=y
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+# CONFIG_CRYPTO_GHASH_ARM_CE is not set
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+CONFIG_CRYPTO_HASH=y
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+CONFIG_CRYPTO_HASH2=y
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+CONFIG_CRYPTO_HW=y
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+CONFIG_CRYPTO_LZO=y
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+CONFIG_CRYPTO_MANAGER=y
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+CONFIG_CRYPTO_MANAGER2=y
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+CONFIG_CRYPTO_NULL2=y
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+CONFIG_CRYPTO_RNG2=y
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+CONFIG_CRYPTO_SHA1=y
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+CONFIG_CRYPTO_SHA1_ARM=y
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+# CONFIG_CRYPTO_SHA1_ARM_CE is not set
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+CONFIG_CRYPTO_SHA1_ARM_NEON=y
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+CONFIG_CRYPTO_SHA256_ARM=y
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+# CONFIG_CRYPTO_SHA2_ARM_CE is not set
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+CONFIG_CRYPTO_SHA512_ARM=y
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+CONFIG_CRYPTO_SIMD=y
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+CONFIG_CRYPTO_WORKQUEUE=y
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+CONFIG_DCACHE_WORD_ACCESS=y
|
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+CONFIG_DEBUG_ALIGN_RODATA=y
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+CONFIG_DEBUG_INFO=y
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+CONFIG_DEBUG_LL=y
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+CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
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+CONFIG_DEBUG_MVEBU_UART0=y
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+# CONFIG_DEBUG_MVEBU_UART0_ALTERNATE is not set
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+# CONFIG_DEBUG_MVEBU_UART1_ALTERNATE is not set
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+CONFIG_DEBUG_UART_8250=y
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+# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set
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+CONFIG_DEBUG_UART_8250_SHIFT=2
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+# CONFIG_DEBUG_UART_8250_WORD is not set
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+CONFIG_DEBUG_UART_PHYS=0xd0012000
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+CONFIG_DEBUG_UART_VIRT=0xfec12000
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+CONFIG_DEBUG_UNCOMPRESS=y
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+CONFIG_DEBUG_USER=y
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+CONFIG_DMADEVICES=y
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+CONFIG_DMA_ENGINE=y
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+CONFIG_DMA_ENGINE_RAID=y
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+CONFIG_DMA_OF=y
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+CONFIG_DTC=y
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+CONFIG_EARLY_PRINTK=y
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+CONFIG_EDAC_ATOMIC_SCRUB=y
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+CONFIG_EDAC_SUPPORT=y
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+CONFIG_EXT4_FS=y
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+CONFIG_EXTCON=y
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+# CONFIG_F2FS_CHECK_FS is not set
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+CONFIG_F2FS_FS=y
|
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+# CONFIG_F2FS_FS_SECURITY is not set
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+CONFIG_F2FS_FS_XATTR=y
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+CONFIG_F2FS_STAT_FS=y
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+CONFIG_FIXED_PHY=y
|
|
+CONFIG_FIX_EARLYCON_MEM=y
|
|
+CONFIG_FS_IOMAP=y
|
|
+CONFIG_FS_MBCACHE=y
|
|
+CONFIG_GENERIC_ALLOCATOR=y
|
|
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
|
|
+CONFIG_GENERIC_BUG=y
|
|
+CONFIG_GENERIC_CLOCKEVENTS=y
|
|
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
|
|
+CONFIG_GENERIC_CPU_AUTOPROBE=y
|
|
+CONFIG_GENERIC_EARLY_IOREMAP=y
|
|
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
|
|
+CONFIG_GENERIC_IRQ_CHIP=y
|
|
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
|
|
+CONFIG_GENERIC_IRQ_MIGRATION=y
|
|
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
|
|
+CONFIG_GENERIC_IRQ_SHOW=y
|
|
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
|
|
+CONFIG_GENERIC_MSI_IRQ=y
|
|
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
|
|
+CONFIG_GENERIC_PCI_IOMAP=y
|
|
+CONFIG_GENERIC_PHY=y
|
|
+CONFIG_GENERIC_SCHED_CLOCK=y
|
|
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
|
|
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
|
|
+CONFIG_GENERIC_STRNLEN_USER=y
|
|
+CONFIG_GLOB=y
|
|
+CONFIG_GPIOLIB=y
|
|
+CONFIG_GPIOLIB_IRQCHIP=y
|
|
+CONFIG_GPIO_GENERIC=y
|
|
+CONFIG_GPIO_GENERIC_PLATFORM=y
|
|
+CONFIG_GPIO_MVEBU=y
|
|
+CONFIG_GPIO_PCA953X=y
|
|
+CONFIG_GPIO_PCA953X_IRQ=y
|
|
+CONFIG_GPIO_SYSFS=y
|
|
+CONFIG_HANDLE_DOMAIN_IRQ=y
|
|
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
|
|
+CONFIG_HARDIRQS_SW_RESEND=y
|
|
+CONFIG_HAS_DMA=y
|
|
+CONFIG_HAS_IOMEM=y
|
|
+CONFIG_HAS_IOPORT_MAP=y
|
|
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
|
|
+CONFIG_HAVE_ARCH_BITREVERSE=y
|
|
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
|
|
+CONFIG_HAVE_ARCH_KGDB=y
|
|
+CONFIG_HAVE_ARCH_PFN_VALID=y
|
|
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
|
|
+CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y
|
|
+CONFIG_HAVE_ARCH_TRACEHOOK=y
|
|
+CONFIG_HAVE_ARM_SCU=y
|
|
+CONFIG_HAVE_ARM_SMCCC=y
|
|
+CONFIG_HAVE_ARM_TWD=y
|
|
+CONFIG_HAVE_CLK=y
|
|
+CONFIG_HAVE_CLK_PREPARE=y
|
|
+CONFIG_HAVE_CONTEXT_TRACKING=y
|
|
+CONFIG_HAVE_C_RECORDMCOUNT=y
|
|
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
|
|
+CONFIG_HAVE_DMA_CONTIGUOUS=y
|
|
+CONFIG_HAVE_DYNAMIC_FTRACE=y
|
|
+CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y
|
|
+CONFIG_HAVE_EBPF_JIT=y
|
|
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
|
|
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
|
|
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
|
|
+CONFIG_HAVE_FUNCTION_TRACER=y
|
|
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
|
|
+CONFIG_HAVE_IDE=y
|
|
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
|
|
+CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y
|
|
+CONFIG_HAVE_MEMBLOCK=y
|
|
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
|
|
+CONFIG_HAVE_NET_DSA=y
|
|
+CONFIG_HAVE_OPROFILE=y
|
|
+CONFIG_HAVE_OPTPROBES=y
|
|
+CONFIG_HAVE_PERF_EVENTS=y
|
|
+CONFIG_HAVE_PERF_REGS=y
|
|
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
|
|
+CONFIG_HAVE_PROC_CPU=y
|
|
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
|
|
+CONFIG_HAVE_RSEQ=y
|
|
+CONFIG_HAVE_SMP=y
|
|
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
|
|
+CONFIG_HAVE_UID16=y
|
|
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
|
|
+CONFIG_HIGHMEM=y
|
|
+# CONFIG_HIGHPTE is not set
|
|
+CONFIG_HOTPLUG_CPU=y
|
|
+CONFIG_HWBM=y
|
|
+CONFIG_HWMON=y
|
|
+CONFIG_HW_RANDOM=y
|
|
+CONFIG_HZ_FIXED=0
|
|
+CONFIG_HZ_PERIODIC=y
|
|
+CONFIG_I2C=y
|
|
+CONFIG_I2C_BOARDINFO=y
|
|
+CONFIG_I2C_CHARDEV=y
|
|
+CONFIG_I2C_MV64XXX=y
|
|
+# CONFIG_I2C_PXA is not set
|
|
+CONFIG_INITRAMFS_SOURCE=""
|
|
+CONFIG_IRQCHIP=y
|
|
+CONFIG_IRQ_DOMAIN=y
|
|
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
|
|
+CONFIG_IRQ_FORCED_THREADING=y
|
|
+CONFIG_IRQ_WORK=y
|
|
+# CONFIG_IWMMXT is not set
|
|
+CONFIG_JBD2=y
|
|
+CONFIG_LEDS_GPIO=y
|
|
+CONFIG_LEDS_PCA963X=y
|
|
+CONFIG_LEDS_TLC591XX=y
|
|
+CONFIG_LEDS_TRIGGER_DISK=y
|
|
+CONFIG_LIBFDT=y
|
|
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
|
|
+CONFIG_LOCK_SPIN_ON_OWNER=y
|
|
+CONFIG_LZO_COMPRESS=y
|
|
+CONFIG_LZO_DECOMPRESS=y
|
|
+CONFIG_MACH_ARMADA_370=y
|
|
+# CONFIG_MACH_ARMADA_375 is not set
|
|
+CONFIG_MACH_ARMADA_38X=y
|
|
+# CONFIG_MACH_ARMADA_39X is not set
|
|
+CONFIG_MACH_ARMADA_XP=y
|
|
+# CONFIG_MACH_DOVE is not set
|
|
+CONFIG_MACH_MVEBU_ANY=y
|
|
+CONFIG_MACH_MVEBU_V7=y
|
|
+CONFIG_MAGIC_SYSRQ=y
|
|
+CONFIG_MANGLE_BOOTARGS=y
|
|
+CONFIG_MARVELL_PHY=y
|
|
+CONFIG_MDIO_BUS=y
|
|
+CONFIG_MDIO_DEVICE=y
|
|
+CONFIG_MDIO_I2C=y
|
|
+CONFIG_MEMFD_CREATE=y
|
|
+CONFIG_MEMORY=y
|
|
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
|
|
+CONFIG_MIGHT_HAVE_PCI=y
|
|
+CONFIG_MIGRATION=y
|
|
+CONFIG_MMC=y
|
|
+CONFIG_MMC_BLOCK=y
|
|
+CONFIG_MMC_MVSDIO=y
|
|
+CONFIG_MMC_SDHCI=y
|
|
+# CONFIG_MMC_SDHCI_PCI is not set
|
|
+CONFIG_MMC_SDHCI_PLTFM=y
|
|
+CONFIG_MMC_SDHCI_PXAV3=y
|
|
+# CONFIG_MMC_TIFM_SD is not set
|
|
+CONFIG_MODULES_USE_ELF_REL=y
|
|
+CONFIG_MTD_CFI_STAA=y
|
|
+CONFIG_MTD_M25P80=y
|
|
+CONFIG_MTD_NAND=y
|
|
+CONFIG_MTD_NAND_ECC=y
|
|
+CONFIG_MTD_NAND_MARVELL=y
|
|
+CONFIG_MTD_SPI_NOR=y
|
|
+CONFIG_MTD_SPLIT_FIRMWARE=y
|
|
+CONFIG_MTD_UBI=y
|
|
+CONFIG_MTD_UBI_BEB_LIMIT=20
|
|
+CONFIG_MTD_UBI_BLOCK=y
|
|
+# CONFIG_MTD_UBI_FASTMAP is not set
|
|
+# CONFIG_MTD_UBI_GLUEBI is not set
|
|
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
|
|
+CONFIG_MUTEX_SPIN_ON_OWNER=y
|
|
+CONFIG_MVEBU_CLK_COMMON=y
|
|
+CONFIG_MVEBU_CLK_COREDIV=y
|
|
+CONFIG_MVEBU_CLK_CPU=y
|
|
+CONFIG_MVEBU_DEVBUS=y
|
|
+CONFIG_MVEBU_MBUS=y
|
|
+CONFIG_MVMDIO=y
|
|
+CONFIG_MVNETA=y
|
|
+CONFIG_MVNETA_BM=y
|
|
+CONFIG_MVNETA_BM_ENABLE=y
|
|
+CONFIG_MVPP2=y
|
|
+CONFIG_MVSW61XX_PHY=y
|
|
+CONFIG_MV_XOR=y
|
|
+CONFIG_NEED_DMA_MAP_STATE=y
|
|
+CONFIG_NEON=y
|
|
+CONFIG_NET_DSA=y
|
|
+CONFIG_NET_DSA_MV88E6XXX=y
|
|
+CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y
|
|
+# CONFIG_NET_DSA_MV88E6XXX_PTP is not set
|
|
+CONFIG_NET_DSA_TAG_DSA=y
|
|
+CONFIG_NET_DSA_TAG_EDSA=y
|
|
+CONFIG_NET_FLOW_LIMIT=y
|
|
+CONFIG_NET_SWITCHDEV=y
|
|
+CONFIG_NLS=y
|
|
+CONFIG_NOP_USB_XCEIV=y
|
|
+CONFIG_NO_BOOTMEM=y
|
|
+CONFIG_NR_CPUS=4
|
|
+CONFIG_NVMEM=y
|
|
+CONFIG_OF=y
|
|
+CONFIG_OF_ADDRESS=y
|
|
+CONFIG_OF_EARLY_FLATTREE=y
|
|
+CONFIG_OF_FLATTREE=y
|
|
+CONFIG_OF_GPIO=y
|
|
+CONFIG_OF_IRQ=y
|
|
+CONFIG_OF_KOBJ=y
|
|
+CONFIG_OF_MDIO=y
|
|
+CONFIG_OF_NET=y
|
|
+CONFIG_OF_RESERVED_MEM=y
|
|
+CONFIG_OLD_SIGACTION=y
|
|
+CONFIG_OLD_SIGSUSPEND3=y
|
|
+CONFIG_ORION_WATCHDOG=y
|
|
+CONFIG_OUTER_CACHE=y
|
|
+CONFIG_OUTER_CACHE_SYNC=y
|
|
+CONFIG_PADATA=y
|
|
+CONFIG_PAGE_OFFSET=0xC0000000
|
|
+CONFIG_PCI=y
|
|
+CONFIG_PCI_DOMAINS=y
|
|
+CONFIG_PCI_DOMAINS_GENERIC=y
|
|
+CONFIG_PCI_MSI=y
|
|
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
|
|
+CONFIG_PCI_MVEBU=y
|
|
+# CONFIG_PCI_V3_SEMI is not set
|
|
+CONFIG_PERF_USE_VMALLOC=y
|
|
+CONFIG_PGTABLE_LEVELS=2
|
|
+CONFIG_PHYLIB=y
|
|
+CONFIG_PHYLINK=y
|
|
+# CONFIG_PHY_MVEBU_A3700_COMPHY is not set
|
|
+# CONFIG_PHY_MVEBU_CP110_COMPHY is not set
|
|
+CONFIG_PINCTRL=y
|
|
+CONFIG_PINCTRL_ARMADA_370=y
|
|
+CONFIG_PINCTRL_ARMADA_38X=y
|
|
+CONFIG_PINCTRL_ARMADA_XP=y
|
|
+CONFIG_PINCTRL_MVEBU=y
|
|
+# CONFIG_PINCTRL_SINGLE is not set
|
|
+CONFIG_PJ4B_ERRATA_4742=y
|
|
+# CONFIG_PL310_ERRATA_588369 is not set
|
|
+# CONFIG_PL310_ERRATA_727915 is not set
|
|
+CONFIG_PL310_ERRATA_753970=y
|
|
+# CONFIG_PL310_ERRATA_769419 is not set
|
|
+CONFIG_PLAT_ORION=y
|
|
+CONFIG_PM_OPP=y
|
|
+CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=11
|
|
+CONFIG_PWM=y
|
|
+CONFIG_PWM_SYSFS=y
|
|
+CONFIG_RATIONAL=y
|
|
+CONFIG_RCU_NEED_SEGCBLIST=y
|
|
+CONFIG_RCU_STALL_COMMON=y
|
|
+CONFIG_REFCOUNT_FULL=y
|
|
+CONFIG_REGMAP=y
|
|
+CONFIG_REGMAP_I2C=y
|
|
+CONFIG_REGMAP_MMIO=y
|
|
+CONFIG_REGMAP_SPI=y
|
|
+CONFIG_REGULATOR=y
|
|
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
|
+CONFIG_RFS_ACCEL=y
|
|
+CONFIG_RPS=y
|
|
+CONFIG_RTC_CLASS=y
|
|
+CONFIG_RTC_DRV_ARMADA38X=y
|
|
+CONFIG_RTC_DRV_MV=y
|
|
+CONFIG_RTC_I2C_AND_SPI=y
|
|
+CONFIG_RTC_MC146818_LIB=y
|
|
+CONFIG_RWSEM_SPIN_ON_OWNER=y
|
|
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
|
|
+CONFIG_SATA_AHCI_PLATFORM=y
|
|
+CONFIG_SATA_MV=y
|
|
+CONFIG_SATA_PMP=y
|
|
+CONFIG_SCSI=y
|
|
+CONFIG_SENSORS_PWM_FAN=y
|
|
+CONFIG_SENSORS_TMP421=y
|
|
+CONFIG_SERIAL_8250_DW=y
|
|
+CONFIG_SERIAL_8250_FSL=y
|
|
+CONFIG_SERIAL_MVEBU_CONSOLE=y
|
|
+CONFIG_SERIAL_MVEBU_UART=y
|
|
+CONFIG_SFP=y
|
|
+CONFIG_SGL_ALLOC=y
|
|
+CONFIG_SG_POOL=y
|
|
+CONFIG_SMP=y
|
|
+CONFIG_SMP_ON_UP=y
|
|
+CONFIG_SOC_BUS=y
|
|
+CONFIG_SPARSE_IRQ=y
|
|
+CONFIG_SPI=y
|
|
+# CONFIG_SPI_ARMADA_3700 is not set
|
|
+CONFIG_SPI_MASTER=y
|
|
+CONFIG_SPI_MEM=y
|
|
+CONFIG_SPI_ORION=y
|
|
+CONFIG_SRAM=y
|
|
+CONFIG_SRAM_EXEC=y
|
|
+CONFIG_SRCU=y
|
|
+CONFIG_SWCONFIG=y
|
|
+CONFIG_SWPHY=y
|
|
+CONFIG_SWP_EMULATE=y
|
|
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
|
|
+CONFIG_THERMAL=y
|
|
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
|
|
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
|
|
+CONFIG_THERMAL_GOV_STEP_WISE=y
|
|
+CONFIG_THERMAL_HWMON=y
|
|
+CONFIG_THERMAL_OF=y
|
|
+# CONFIG_THUMB2_KERNEL is not set
|
|
+CONFIG_TICK_CPU_ACCOUNTING=y
|
|
+CONFIG_TIMER_OF=y
|
|
+CONFIG_TIMER_PROBE=y
|
|
+CONFIG_TREE_RCU=y
|
|
+CONFIG_TREE_SRCU=y
|
|
+CONFIG_UBIFS_FS=y
|
|
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
|
|
+CONFIG_UBIFS_FS_LZO=y
|
|
+CONFIG_UBIFS_FS_ZLIB=y
|
|
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
|
|
+CONFIG_USB=y
|
|
+CONFIG_USB_COMMON=y
|
|
+CONFIG_USB_EHCI_HCD=y
|
|
+CONFIG_USB_EHCI_HCD_ORION=y
|
|
+CONFIG_USB_EHCI_HCD_PLATFORM=y
|
|
+CONFIG_USB_LEDS_TRIGGER_USBPORT=y
|
|
+CONFIG_USB_PHY=y
|
|
+CONFIG_USB_STORAGE=y
|
|
+CONFIG_USB_SUPPORT=y
|
|
+CONFIG_USB_XHCI_HCD=y
|
|
+CONFIG_USB_XHCI_MVEBU=y
|
|
+CONFIG_USB_XHCI_PLATFORM=y
|
|
+CONFIG_USE_OF=y
|
|
+CONFIG_VFP=y
|
|
+CONFIG_VFPv3=y
|
|
+CONFIG_WATCHDOG_CORE=y
|
|
+CONFIG_XPS=y
|
|
+CONFIG_XZ_DEC_ARM=y
|
|
+CONFIG_XZ_DEC_BCJ=y
|
|
+CONFIG_ZBOOT_ROM_BSS=0x0
|
|
+CONFIG_ZBOOT_ROM_TEXT=0x0
|
|
+CONFIG_ZLIB_DEFLATE=y
|
|
+CONFIG_ZLIB_INFLATE=y
|
|
diff --git a/target/linux/mvebu/cortexa53/config-5.4 b/target/linux/mvebu/cortexa53/config-5.4
|
|
new file mode 100644
|
|
index 00000000000..7f3c2b21de0
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/cortexa53/config-5.4
|
|
@@ -0,0 +1,169 @@
|
|
+CONFIG_64BIT=y
|
|
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
|
|
+CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
|
|
+CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
|
|
+CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
|
|
+CONFIG_ARCH_HAS_PTE_SPECIAL=y
|
|
+CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
|
|
+CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
|
|
+CONFIG_ARCH_INLINE_READ_LOCK=y
|
|
+CONFIG_ARCH_INLINE_READ_LOCK_BH=y
|
|
+CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y
|
|
+CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y
|
|
+CONFIG_ARCH_INLINE_READ_UNLOCK=y
|
|
+CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y
|
|
+CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y
|
|
+CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y
|
|
+CONFIG_ARCH_INLINE_SPIN_LOCK=y
|
|
+CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y
|
|
+CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y
|
|
+CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y
|
|
+CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y
|
|
+CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y
|
|
+CONFIG_ARCH_INLINE_SPIN_UNLOCK=y
|
|
+CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y
|
|
+CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y
|
|
+CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y
|
|
+CONFIG_ARCH_INLINE_WRITE_LOCK=y
|
|
+CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y
|
|
+CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y
|
|
+CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y
|
|
+CONFIG_ARCH_INLINE_WRITE_UNLOCK=y
|
|
+CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y
|
|
+CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y
|
|
+CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y
|
|
+CONFIG_ARCH_MMAP_RND_BITS=18
|
|
+CONFIG_ARCH_MMAP_RND_BITS_MAX=24
|
|
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
|
|
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
|
|
+CONFIG_ARCH_PROC_KCORE_TEXT=y
|
|
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
|
|
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
|
|
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
|
|
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
|
|
+CONFIG_ARCH_SUPPORTS_INT128=y
|
|
+CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
|
|
+CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
|
|
+CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
|
|
+CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
|
|
+CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
|
|
+CONFIG_ARCH_WANT_FRAME_POINTERS=y
|
|
+CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
|
|
+CONFIG_ARM64=y
|
|
+# CONFIG_ARM64_16K_PAGES is not set
|
|
+CONFIG_ARM64_4K_PAGES=y
|
|
+# CONFIG_ARM64_64K_PAGES is not set
|
|
+CONFIG_ARM64_CONT_SHIFT=4
|
|
+# CONFIG_ARM64_CRYPTO is not set
|
|
+# CONFIG_ARM64_HW_AFDBM is not set
|
|
+# CONFIG_ARM64_LSE_ATOMICS is not set
|
|
+CONFIG_ARM64_PAGE_SHIFT=12
|
|
+# CONFIG_ARM64_PAN is not set
|
|
+CONFIG_ARM64_PA_BITS=48
|
|
+CONFIG_ARM64_PA_BITS_48=y
|
|
+# CONFIG_ARM64_PMEM is not set
|
|
+# CONFIG_ARM64_PTDUMP_DEBUGFS is not set
|
|
+# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set
|
|
+CONFIG_ARM64_SSBD=y
|
|
+CONFIG_ARM64_SVE=y
|
|
+# CONFIG_ARM64_UAO is not set
|
|
+CONFIG_ARM64_VA_BITS=39
|
|
+CONFIG_ARM64_VA_BITS_39=y
|
|
+# CONFIG_ARM64_VA_BITS_48 is not set
|
|
+# CONFIG_ARM64_VHE is not set
|
|
+CONFIG_ARMADA_37XX_CLK=y
|
|
+CONFIG_ARMADA_AP806_SYSCON=y
|
|
+CONFIG_ARMADA_CP110_SYSCON=y
|
|
+CONFIG_ARM_AMBA=y
|
|
+CONFIG_ARM_ARCH_TIMER=y
|
|
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
|
|
+CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
|
|
+CONFIG_ARM_GIC_V2M=y
|
|
+CONFIG_ARM_GIC_V3=y
|
|
+CONFIG_ARM_GIC_V3_ITS=y
|
|
+CONFIG_ARM_GIC_V3_ITS_PCI=y
|
|
+# CONFIG_ARM_PL172_MPMC is not set
|
|
+CONFIG_ARM_PSCI_FW=y
|
|
+# CONFIG_ARM_SP805_WATCHDOG is not set
|
|
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
|
|
+# CONFIG_DEBUG_ALIGN_RODATA is not set
|
|
+CONFIG_DMA_DIRECT_OPS=y
|
|
+# CONFIG_FLATMEM_MANUAL is not set
|
|
+CONFIG_FRAME_POINTER=y
|
|
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
|
|
+CONFIG_GENERIC_CSUM=y
|
|
+CONFIG_GENERIC_PINCONF=y
|
|
+CONFIG_GENERIC_TIME_VSYSCALL=y
|
|
+CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
|
|
+CONFIG_HAVE_ARCH_HUGE_VMAP=y
|
|
+CONFIG_HAVE_ARCH_KASAN=y
|
|
+CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
|
|
+CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
|
|
+CONFIG_HAVE_ARCH_VMAP_STACK=y
|
|
+CONFIG_HAVE_CMPXCHG_DOUBLE=y
|
|
+CONFIG_HAVE_CMPXCHG_LOCAL=y
|
|
+CONFIG_HAVE_DEBUG_BUGVERBOSE=y
|
|
+CONFIG_HAVE_GENERIC_GUP=y
|
|
+CONFIG_HAVE_MEMORY_PRESENT=y
|
|
+CONFIG_HAVE_PATA_PLATFORM=y
|
|
+CONFIG_HAVE_RCU_TABLE_FREE=y
|
|
+CONFIG_HOLES_IN_ZONE=y
|
|
+# CONFIG_HUGETLBFS is not set
|
|
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
|
|
+CONFIG_INLINE_READ_LOCK=y
|
|
+CONFIG_INLINE_READ_LOCK_BH=y
|
|
+CONFIG_INLINE_READ_LOCK_IRQ=y
|
|
+CONFIG_INLINE_READ_LOCK_IRQSAVE=y
|
|
+CONFIG_INLINE_READ_UNLOCK_BH=y
|
|
+CONFIG_INLINE_READ_UNLOCK_IRQRESTORE=y
|
|
+CONFIG_INLINE_SPIN_LOCK=y
|
|
+CONFIG_INLINE_SPIN_LOCK_BH=y
|
|
+CONFIG_INLINE_SPIN_LOCK_IRQ=y
|
|
+CONFIG_INLINE_SPIN_LOCK_IRQSAVE=y
|
|
+CONFIG_INLINE_SPIN_TRYLOCK=y
|
|
+CONFIG_INLINE_SPIN_TRYLOCK_BH=y
|
|
+CONFIG_INLINE_SPIN_UNLOCK_BH=y
|
|
+CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE=y
|
|
+CONFIG_INLINE_WRITE_LOCK=y
|
|
+CONFIG_INLINE_WRITE_LOCK_BH=y
|
|
+CONFIG_INLINE_WRITE_LOCK_IRQ=y
|
|
+CONFIG_INLINE_WRITE_LOCK_IRQSAVE=y
|
|
+CONFIG_INLINE_WRITE_UNLOCK_BH=y
|
|
+CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE=y
|
|
+CONFIG_MFD_SYSCON=y
|
|
+CONFIG_MMC_SDHCI_XENON=y
|
|
+CONFIG_MODULES_USE_ELF_RELA=y
|
|
+CONFIG_MVEBU_GICP=y
|
|
+CONFIG_MVEBU_ICU=y
|
|
+CONFIG_MVEBU_ODMI=y
|
|
+CONFIG_MVEBU_PIC=y
|
|
+CONFIG_NEED_SG_DMA_LENGTH=y
|
|
+# CONFIG_NUMA is not set
|
|
+CONFIG_PARTITION_PERCPU=y
|
|
+CONFIG_PCI_AARDVARK=y
|
|
+CONFIG_PGTABLE_LEVELS=3
|
|
+CONFIG_PHYS_ADDR_T_64BIT=y
|
|
+CONFIG_PHY_MVEBU_A3700_COMPHY=y
|
|
+CONFIG_PINCTRL_ARMADA_37XX=y
|
|
+CONFIG_PINCTRL_ARMADA_AP806=y
|
|
+CONFIG_PINCTRL_ARMADA_CP110=y
|
|
+CONFIG_POWER_RESET=y
|
|
+CONFIG_POWER_SUPPLY=y
|
|
+CONFIG_QUEUED_RWLOCKS=y
|
|
+CONFIG_QUEUED_SPINLOCKS=y
|
|
+# CONFIG_RANDOMIZE_BASE is not set
|
|
+CONFIG_REGULATOR_GPIO=y
|
|
+# CONFIG_SERIAL_AMBA_PL011 is not set
|
|
+CONFIG_SPARSEMEM=y
|
|
+CONFIG_SPARSEMEM_EXTREME=y
|
|
+CONFIG_SPARSEMEM_MANUAL=y
|
|
+CONFIG_SPARSEMEM_VMEMMAP=y
|
|
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
|
|
+CONFIG_SPI_ARMADA_3700=y
|
|
+CONFIG_SWIOTLB=y
|
|
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
|
|
+CONFIG_SYS_SUPPORTS_HUGETLBFS=y
|
|
+CONFIG_THREAD_INFO_IN_TASK=y
|
|
+CONFIG_UNMAP_KERNEL_AT_EL0=y
|
|
+CONFIG_VMAP_STACK=y
|
|
+CONFIG_ZONE_DMA32=y
|
|
diff --git a/target/linux/mvebu/cortexa72/config-5.4 b/target/linux/mvebu/cortexa72/config-5.4
|
|
new file mode 100644
|
|
index 00000000000..c78eb843724
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/cortexa72/config-5.4
|
|
@@ -0,0 +1,176 @@
|
|
+CONFIG_64BIT=y
|
|
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
|
|
+CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
|
|
+CONFIG_ARCH_HAS_FAST_MULTIPLIER=y
|
|
+CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
|
|
+CONFIG_ARCH_HAS_PTE_SPECIAL=y
|
|
+CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y
|
|
+CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y
|
|
+CONFIG_ARCH_INLINE_READ_LOCK=y
|
|
+CONFIG_ARCH_INLINE_READ_LOCK_BH=y
|
|
+CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y
|
|
+CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y
|
|
+CONFIG_ARCH_INLINE_READ_UNLOCK=y
|
|
+CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y
|
|
+CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y
|
|
+CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y
|
|
+CONFIG_ARCH_INLINE_SPIN_LOCK=y
|
|
+CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y
|
|
+CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y
|
|
+CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y
|
|
+CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y
|
|
+CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y
|
|
+CONFIG_ARCH_INLINE_SPIN_UNLOCK=y
|
|
+CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y
|
|
+CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y
|
|
+CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y
|
|
+CONFIG_ARCH_INLINE_WRITE_LOCK=y
|
|
+CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y
|
|
+CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y
|
|
+CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y
|
|
+CONFIG_ARCH_INLINE_WRITE_UNLOCK=y
|
|
+CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y
|
|
+CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y
|
|
+CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y
|
|
+CONFIG_ARCH_MMAP_RND_BITS=18
|
|
+CONFIG_ARCH_MMAP_RND_BITS_MAX=24
|
|
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
|
|
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
|
|
+CONFIG_ARCH_PROC_KCORE_TEXT=y
|
|
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
|
|
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
|
|
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
|
|
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
|
|
+CONFIG_ARCH_SUPPORTS_INT128=y
|
|
+CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y
|
|
+CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
|
|
+CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
|
|
+CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
|
|
+CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
|
|
+CONFIG_ARCH_WANT_FRAME_POINTERS=y
|
|
+CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
|
|
+CONFIG_ARM64=y
|
|
+# CONFIG_ARM64_16K_PAGES is not set
|
|
+CONFIG_ARM64_4K_PAGES=y
|
|
+# CONFIG_ARM64_64K_PAGES is not set
|
|
+CONFIG_ARM64_CONT_SHIFT=4
|
|
+# CONFIG_ARM64_CRYPTO is not set
|
|
+# CONFIG_ARM64_HW_AFDBM is not set
|
|
+# CONFIG_ARM64_LSE_ATOMICS is not set
|
|
+CONFIG_ARM64_PAGE_SHIFT=12
|
|
+# CONFIG_ARM64_PAN is not set
|
|
+CONFIG_ARM64_PA_BITS=48
|
|
+CONFIG_ARM64_PA_BITS_48=y
|
|
+# CONFIG_ARM64_PMEM is not set
|
|
+# CONFIG_ARM64_PTDUMP_DEBUGFS is not set
|
|
+# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set
|
|
+CONFIG_ARM64_SSBD=y
|
|
+CONFIG_ARM64_SVE=y
|
|
+# CONFIG_ARM64_UAO is not set
|
|
+CONFIG_ARM64_VA_BITS=39
|
|
+CONFIG_ARM64_VA_BITS_39=y
|
|
+# CONFIG_ARM64_VA_BITS_48 is not set
|
|
+# CONFIG_ARM64_VHE is not set
|
|
+CONFIG_ARMADA_37XX_CLK=y
|
|
+CONFIG_ARMADA_AP806_SYSCON=y
|
|
+CONFIG_ARMADA_CP110_SYSCON=y
|
|
+CONFIG_ARM_AMBA=y
|
|
+CONFIG_ARM_ARCH_TIMER=y
|
|
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
|
|
+CONFIG_ARM_GIC_V2M=y
|
|
+CONFIG_ARM_GIC_V3=y
|
|
+CONFIG_ARM_GIC_V3_ITS=y
|
|
+CONFIG_ARM_GIC_V3_ITS_PCI=y
|
|
+# CONFIG_ARM_PL172_MPMC is not set
|
|
+CONFIG_ARM_PSCI_FW=y
|
|
+# CONFIG_ARM_SP805_WATCHDOG is not set
|
|
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
|
|
+# CONFIG_DEBUG_ALIGN_RODATA is not set
|
|
+CONFIG_DMA_DIRECT_OPS=y
|
|
+# CONFIG_FLATMEM_MANUAL is not set
|
|
+CONFIG_FRAME_POINTER=y
|
|
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
|
|
+CONFIG_GENERIC_CSUM=y
|
|
+CONFIG_GENERIC_PINCONF=y
|
|
+CONFIG_GENERIC_TIME_VSYSCALL=y
|
|
+CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y
|
|
+CONFIG_HAVE_ARCH_HUGE_VMAP=y
|
|
+CONFIG_HAVE_ARCH_KASAN=y
|
|
+CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y
|
|
+CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
|
|
+CONFIG_HAVE_ARCH_VMAP_STACK=y
|
|
+CONFIG_HAVE_CMPXCHG_DOUBLE=y
|
|
+CONFIG_HAVE_CMPXCHG_LOCAL=y
|
|
+CONFIG_HAVE_DEBUG_BUGVERBOSE=y
|
|
+CONFIG_HAVE_GENERIC_GUP=y
|
|
+CONFIG_HAVE_MEMORY_PRESENT=y
|
|
+CONFIG_HAVE_PATA_PLATFORM=y
|
|
+CONFIG_HAVE_RCU_TABLE_FREE=y
|
|
+CONFIG_HOLES_IN_ZONE=y
|
|
+# CONFIG_HUGETLBFS is not set
|
|
+CONFIG_HW_RANDOM_OMAP=y
|
|
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
|
|
+CONFIG_INLINE_READ_LOCK=y
|
|
+CONFIG_INLINE_READ_LOCK_BH=y
|
|
+CONFIG_INLINE_READ_LOCK_IRQ=y
|
|
+CONFIG_INLINE_READ_LOCK_IRQSAVE=y
|
|
+CONFIG_INLINE_READ_UNLOCK_BH=y
|
|
+CONFIG_INLINE_READ_UNLOCK_IRQRESTORE=y
|
|
+CONFIG_INLINE_SPIN_LOCK=y
|
|
+CONFIG_INLINE_SPIN_LOCK_BH=y
|
|
+CONFIG_INLINE_SPIN_LOCK_IRQ=y
|
|
+CONFIG_INLINE_SPIN_LOCK_IRQSAVE=y
|
|
+CONFIG_INLINE_SPIN_TRYLOCK=y
|
|
+CONFIG_INLINE_SPIN_TRYLOCK_BH=y
|
|
+CONFIG_INLINE_SPIN_UNLOCK_BH=y
|
|
+CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE=y
|
|
+CONFIG_INLINE_WRITE_LOCK=y
|
|
+CONFIG_INLINE_WRITE_LOCK_BH=y
|
|
+CONFIG_INLINE_WRITE_LOCK_IRQ=y
|
|
+CONFIG_INLINE_WRITE_LOCK_IRQSAVE=y
|
|
+CONFIG_INLINE_WRITE_UNLOCK_BH=y
|
|
+CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE=y
|
|
+CONFIG_MARVELL_10G_PHY=y
|
|
+CONFIG_MFD_SYSCON=y
|
|
+CONFIG_MMC_SDHCI_XENON=y
|
|
+CONFIG_MODULES_USE_ELF_RELA=y
|
|
+CONFIG_MVEBU_GICP=y
|
|
+CONFIG_MVEBU_ICU=y
|
|
+CONFIG_MVEBU_ODMI=y
|
|
+CONFIG_MVEBU_PIC=y
|
|
+CONFIG_MV_XOR_V2=y
|
|
+CONFIG_NEED_SG_DMA_LENGTH=y
|
|
+# CONFIG_NUMA is not set
|
|
+CONFIG_PARTITION_PERCPU=y
|
|
+CONFIG_PCIEAER=y
|
|
+CONFIG_PCIEPORTBUS=y
|
|
+CONFIG_PCIE_ARMADA_8K=y
|
|
+CONFIG_PCIE_DW=y
|
|
+CONFIG_PCIE_DW_HOST=y
|
|
+# CONFIG_PCI_AARDVARK is not set
|
|
+CONFIG_PGTABLE_LEVELS=3
|
|
+CONFIG_PHYS_ADDR_T_64BIT=y
|
|
+CONFIG_PHY_MVEBU_CP110_COMPHY=y
|
|
+CONFIG_PINCTRL_ARMADA_37XX=y
|
|
+CONFIG_PINCTRL_ARMADA_AP806=y
|
|
+CONFIG_PINCTRL_ARMADA_CP110=y
|
|
+CONFIG_POWER_RESET=y
|
|
+CONFIG_POWER_SUPPLY=y
|
|
+CONFIG_QUEUED_RWLOCKS=y
|
|
+CONFIG_QUEUED_SPINLOCKS=y
|
|
+# CONFIG_RANDOMIZE_BASE is not set
|
|
+CONFIG_RAS=y
|
|
+CONFIG_REGULATOR_GPIO=y
|
|
+# CONFIG_SERIAL_AMBA_PL011 is not set
|
|
+CONFIG_SPARSEMEM=y
|
|
+CONFIG_SPARSEMEM_EXTREME=y
|
|
+CONFIG_SPARSEMEM_MANUAL=y
|
|
+CONFIG_SPARSEMEM_VMEMMAP=y
|
|
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
|
|
+CONFIG_SWIOTLB=y
|
|
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
|
|
+CONFIG_SYS_SUPPORTS_HUGETLBFS=y
|
|
+CONFIG_THREAD_INFO_IN_TASK=y
|
|
+CONFIG_UNMAP_KERNEL_AT_EL0=y
|
|
+CONFIG_VMAP_STACK=y
|
|
+CONFIG_ZONE_DMA32=y
|
|
diff --git a/target/linux/mvebu/files-5.4/arch/arm/boot/dts/armada-385-linksys-venom.dts b/target/linux/mvebu/files-5.4/arch/arm/boot/dts/armada-385-linksys-venom.dts
|
|
new file mode 100644
|
|
index 00000000000..c152c14c6b9
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/files-5.4/arch/arm/boot/dts/armada-385-linksys-venom.dts
|
|
@@ -0,0 +1,213 @@
|
|
+/*
|
|
+ * Device Tree file for the Linksys WRT32X (Venom)
|
|
+ *
|
|
+ * Copyright (C) 2017 Imre Kaloz <kaloz@openwrt.org>
|
|
+ *
|
|
+ *
|
|
+ * This file is dual-licensed: you can use it either under the terms
|
|
+ * of the GPL or the X11 license, at your option. Note that this dual
|
|
+ * licensing only applies to this file, and not this project as a
|
|
+ * whole.
|
|
+ *
|
|
+ * a) This file is licensed under the terms of the GNU General Public
|
|
+ * License version 2. This program is licensed "as is" without
|
|
+ * any warranty of any kind, whether express or implied.
|
|
+ *
|
|
+ * Or, alternatively,
|
|
+ *
|
|
+ * b) Permission is hereby granted, free of charge, to any person
|
|
+ * obtaining a copy of this software and associated documentation
|
|
+ * files (the "Software"), to deal in the Software without
|
|
+ * restriction, including without limitation the rights to use,
|
|
+ * copy, modify, merge, publish, distribute, sublicense, and/or
|
|
+ * sell copies of the Software, and to permit persons to whom the
|
|
+ * Software is furnished to do so, subject to the following
|
|
+ * conditions:
|
|
+ *
|
|
+ * The above copyright notice and this permission notice shall be
|
|
+ * included in all copies or substantial portions of the Software.
|
|
+ *
|
|
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
|
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
|
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
|
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
|
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
|
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
|
+ * OTHER DEALINGS IN THE SOFTWARE.
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+#include <dt-bindings/gpio/gpio.h>
|
|
+#include <dt-bindings/input/input.h>
|
|
+#include "armada-385-linksys.dtsi"
|
|
+
|
|
+/ {
|
|
+ model = "Linksys WRT32X";
|
|
+ compatible = "linksys,venom", "linksys,armada385", "marvell,armada385",
|
|
+ "marvell,armada380";
|
|
+
|
|
+ chosen {
|
|
+ bootargs = "console=ttyS0,115200";
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ append-rootblock = "root=/dev/mtdblock";
|
|
+ };
|
|
+};
|
|
+
|
|
+&expander0 {
|
|
+ wan_amber@0 {
|
|
+ label = "venom:amber:wan";
|
|
+ reg = <0x0>;
|
|
+ };
|
|
+
|
|
+ wan_blue@1 {
|
|
+ label = "venom:blue:wan";
|
|
+ reg = <0x1>;
|
|
+ };
|
|
+
|
|
+ usb2@5 {
|
|
+ label = "venom:blue:usb2";
|
|
+ reg = <0x5>;
|
|
+ };
|
|
+
|
|
+ usb3_1@6 {
|
|
+ label = "venom:blue:usb3_1";
|
|
+ reg = <0x6>;
|
|
+ };
|
|
+
|
|
+ usb3_2@7 {
|
|
+ label = "venom:blue:usb3_2";
|
|
+ reg = <0x7>;
|
|
+ };
|
|
+
|
|
+ wps_blue@8 {
|
|
+ label = "venom:blue:wps";
|
|
+ reg = <0x8>;
|
|
+ };
|
|
+
|
|
+ wps_amber@9 {
|
|
+ label = "venom:amber:wps";
|
|
+ reg = <0x9>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&gpio_leds {
|
|
+ power {
|
|
+ gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
|
|
+ label = "venom:blue:power";
|
|
+ };
|
|
+
|
|
+ sata {
|
|
+ gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
|
|
+ label = "venom:blue:sata";
|
|
+ };
|
|
+
|
|
+ wlan_2g {
|
|
+ gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
|
|
+ label = "venom:blue:wlan_2g";
|
|
+ };
|
|
+
|
|
+ wlan_5g {
|
|
+ gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
|
|
+ label = "venom:blue:wlan_5g";
|
|
+ };
|
|
+};
|
|
+
|
|
+&gpio_leds_pins {
|
|
+ marvell,pins = "mpp21", "mpp45", "mpp46", "mpp56";
|
|
+};
|
|
+
|
|
+&nand {
|
|
+ /* Spansion S34ML02G2 256MiB, OEM Layout */
|
|
+ partitions {
|
|
+ compatible = "fixed-partitions";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+
|
|
+ partition@0 {
|
|
+ label = "u-boot";
|
|
+ reg = <0x0000000 0x200000>; /* 2MB */
|
|
+ read-only;
|
|
+ };
|
|
+
|
|
+ partition@200000 {
|
|
+ label = "u_env";
|
|
+ reg = <0x200000 0x20000>; /* 128KB */
|
|
+ };
|
|
+
|
|
+ partition@220000 {
|
|
+ label = "s_env";
|
|
+ reg = <0x220000 0x40000>; /* 256KB */
|
|
+ };
|
|
+
|
|
+ partition@180000 {
|
|
+ label = "unused_area";
|
|
+ reg = <0x260000 0x5c0000>; /* 5.75MB */
|
|
+ };
|
|
+
|
|
+ partition@7e0000 {
|
|
+ label = "devinfo";
|
|
+ reg = <0x7e0000 0x40000>; /* 256KB */
|
|
+ read-only;
|
|
+ };
|
|
+
|
|
+ /* kernel1 overlaps with rootfs1 by design */
|
|
+ partition@900000 {
|
|
+ label = "kernel1";
|
|
+ reg = <0x900000 0x7b00000>; /* 123MB */
|
|
+ };
|
|
+
|
|
+ partition@c00000 {
|
|
+ label = "rootfs1";
|
|
+ reg = <0xc00000 0x7800000>; /* 120MB */
|
|
+ };
|
|
+
|
|
+ /* kernel2 overlaps with rootfs2 by design */
|
|
+ partition@8400000 {
|
|
+ label = "kernel2";
|
|
+ reg = <0x8400000 0x7b00000>; /* 123MB */
|
|
+ };
|
|
+
|
|
+ partition@8700000 {
|
|
+ label = "rootfs2";
|
|
+ reg = <0x8700000 0x7800000>; /* 120MB */
|
|
+ };
|
|
+
|
|
+ /* last MB is for the BBT, not writable */
|
|
+ partition@ff00000 {
|
|
+ label = "BBT";
|
|
+ reg = <0xff00000 0x100000>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+
|
|
+&pcie1 {
|
|
+ mwlwifi {
|
|
+ marvell,chainmask = <4 4>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&pcie2 {
|
|
+ mwlwifi {
|
|
+ marvell,chainmask = <4 4>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&sdhci {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&sdhci_pins>;
|
|
+ no-1-8-v;
|
|
+ non-removable;
|
|
+ wp-inverted;
|
|
+ bus-width = <8>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&usb3_1_vbus {
|
|
+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
|
|
+};
|
|
+
|
|
+&usb3_1_vbus_pins {
|
|
+ marvell,pins = "mpp44";
|
|
+};
|
|
diff --git a/target/linux/mvebu/files-5.4/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts b/target/linux/mvebu/files-5.4/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts
|
|
new file mode 100644
|
|
index 00000000000..ef90a1bd387
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/files-5.4/arch/arm64/boot/dts/marvell/armada-3720-espressobin-emmc.dts
|
|
@@ -0,0 +1,28 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
+/*
|
|
+ * Device Tree file for Globalscale Marvell ESPRESSOBin Board with eMMC
|
|
+ * Copyright (C) 2018 Marvell
|
|
+ *
|
|
+ * Romain Perier <romain.perier@free-electrons.com>
|
|
+ * Konstantin Porotchkin <kostap@marvell.com>
|
|
+ *
|
|
+ */
|
|
+
|
|
+#include "armada-3720-espressobin.dts"
|
|
+
|
|
+/ {
|
|
+ model = "Globalscale Marvell ESPRESSOBin Board (eMMC)";
|
|
+ compatible = "globalscale,espressobin-emmc", "globalscale,espressobin",
|
|
+ "marvell,armada3720", "marvell,armada3710";
|
|
+};
|
|
+
|
|
+&sdhci0 {
|
|
+ status = "okay";
|
|
+
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ mmccard: mmccard@0 {
|
|
+ compatible = "mmc-card";
|
|
+ reg = <0>;
|
|
+ };
|
|
+};
|
|
diff --git a/target/linux/mvebu/files-5.4/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts b/target/linux/mvebu/files-5.4/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts
|
|
new file mode 100644
|
|
index 00000000000..2b565ca8d82
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/files-5.4/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7-emmc.dts
|
|
@@ -0,0 +1,43 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
+/*
|
|
+ * Device Tree file for Globalscale Marvell ESPRESSOBin Board V7 with eMMC
|
|
+ * Copyright (C) 2018 Marvell
|
|
+ *
|
|
+ * Romain Perier <romain.perier@free-electrons.com>
|
|
+ * Konstantin Porotchkin <kostap@marvell.com>
|
|
+ *
|
|
+ */
|
|
+
|
|
+#include "armada-3720-espressobin.dts"
|
|
+
|
|
+/ {
|
|
+ model = "Globalscale Marvell ESPRESSOBin Board V7 (eMMC)";
|
|
+ compatible = "globalscale,espressobin-v7-emmc", "globalscale,espressobin-v7",
|
|
+ "globalscale,espressobin", "marvell,armada3720",
|
|
+ "marvell,armada3710";
|
|
+};
|
|
+
|
|
+&ports {
|
|
+ port@1 {
|
|
+ reg = <1>;
|
|
+ label = "lan1";
|
|
+ phy-handle = <&switch0phy0>;
|
|
+ };
|
|
+
|
|
+ port@3 {
|
|
+ reg = <3>;
|
|
+ label = "wan";
|
|
+ phy-handle = <&switch0phy2>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&sdhci0 {
|
|
+ status = "okay";
|
|
+
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ mmccard: mmccard@0 {
|
|
+ compatible = "mmc-card";
|
|
+ reg = <0>;
|
|
+ };
|
|
+};
|
|
diff --git a/target/linux/mvebu/files-5.4/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts b/target/linux/mvebu/files-5.4/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts
|
|
new file mode 100644
|
|
index 00000000000..8a408c3c48f
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/files-5.4/arch/arm64/boot/dts/marvell/armada-3720-espressobin-v7.dts
|
|
@@ -0,0 +1,31 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
+/*
|
|
+ * Device Tree file for Globalscale Marvell ESPRESSOBin Board V7
|
|
+ * Copyright (C) 2018 Marvell
|
|
+ *
|
|
+ * Romain Perier <romain.perier@free-electrons.com>
|
|
+ * Konstantin Porotchkin <kostap@marvell.com>
|
|
+ *
|
|
+ */
|
|
+
|
|
+#include "armada-3720-espressobin.dts"
|
|
+
|
|
+/ {
|
|
+ model = "Globalscale Marvell ESPRESSOBin Board V7";
|
|
+ compatible = "globalscale,espressobin-v7", "globalscale,espressobin",
|
|
+ "marvell,armada3720", "marvell,armada3710";
|
|
+};
|
|
+
|
|
+&ports {
|
|
+ port@1 {
|
|
+ reg = <1>;
|
|
+ label = "lan1";
|
|
+ phy-handle = <&switch0phy0>;
|
|
+ };
|
|
+
|
|
+ port@3 {
|
|
+ reg = <3>;
|
|
+ label = "wan";
|
|
+ phy-handle = <&switch0phy2>;
|
|
+ };
|
|
+};
|
|
diff --git a/target/linux/mvebu/files-5.4/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts b/target/linux/mvebu/files-5.4/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts
|
|
new file mode 100644
|
|
index 00000000000..5b722b4f832
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/files-5.4/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts
|
|
@@ -0,0 +1,162 @@
|
|
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
+/*
|
|
+ * Device tree for the uDPU board.
|
|
+ * Based on Marvell Armada 3720 development board (DB-88F3720-DDR3)
|
|
+ * Copyright (C) 2016 Marvell
|
|
+ * Copyright (C) 2019 Methode Electronics
|
|
+ * Copyright (C) 2019 Telus
|
|
+ *
|
|
+ * Vladimir Vid <vladimir.vid@sartura.hr>
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+
|
|
+#include <dt-bindings/gpio/gpio.h>
|
|
+#include "armada-372x.dtsi"
|
|
+
|
|
+/ {
|
|
+ model = "Methode uDPU Board";
|
|
+ compatible = "methode,udpu", "marvell,armada3720";
|
|
+
|
|
+ chosen {
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ };
|
|
+
|
|
+ memory@0 {
|
|
+ device_type = "memory";
|
|
+ reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
|
|
+ };
|
|
+
|
|
+ leds {
|
|
+ pinctrl-names = "default";
|
|
+ compatible = "gpio-leds";
|
|
+
|
|
+ power1 {
|
|
+ label = "udpu:green:power";
|
|
+ gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
|
|
+ };
|
|
+
|
|
+ power2 {
|
|
+ label = "udpu:red:power";
|
|
+ gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
|
|
+ };
|
|
+
|
|
+ network1 {
|
|
+ label = "udpu:green:network";
|
|
+ gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
|
|
+ };
|
|
+
|
|
+ network2 {
|
|
+ label = "udpu:red:network";
|
|
+ gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
|
|
+ };
|
|
+
|
|
+ alarm1 {
|
|
+ label = "udpu:green:alarm";
|
|
+ gpios = <&gpionb 15 GPIO_ACTIVE_LOW>;
|
|
+ };
|
|
+
|
|
+ alarm2 {
|
|
+ label = "udpu:red:alarm";
|
|
+ gpios = <&gpionb 16 GPIO_ACTIVE_LOW>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sfp_eth0: sfp-eth0 {
|
|
+ compatible = "sff,sfp";
|
|
+ i2c-bus = <&i2c0>;
|
|
+ los-gpio = <&gpiosb 2 GPIO_ACTIVE_HIGH>;
|
|
+ mod-def0-gpio = <&gpiosb 3 GPIO_ACTIVE_LOW>;
|
|
+ tx-disable-gpio = <&gpiosb 4 GPIO_ACTIVE_HIGH>;
|
|
+ tx-fault-gpio = <&gpiosb 5 GPIO_ACTIVE_HIGH>;
|
|
+ };
|
|
+
|
|
+ sfp_eth1: sfp-eth1 {
|
|
+ compatible = "sff,sfp";
|
|
+ i2c-bus = <&i2c1>;
|
|
+ los-gpio = <&gpiosb 7 GPIO_ACTIVE_HIGH>;
|
|
+ mod-def0-gpio = <&gpiosb 8 GPIO_ACTIVE_LOW>;
|
|
+ tx-disable-gpio = <&gpiosb 9 GPIO_ACTIVE_HIGH>;
|
|
+ tx-fault-gpio = <&gpiosb 10 GPIO_ACTIVE_HIGH>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&sdhci0 {
|
|
+ status = "okay";
|
|
+ bus-width = <8>;
|
|
+ mmc-ddr-1_8v;
|
|
+ mmc-hs400-1_8v;
|
|
+ marvell,pad-type = "fixed-1-8v";
|
|
+ non-removable;
|
|
+ no-sd;
|
|
+ no-sdio;
|
|
+};
|
|
+
|
|
+&spi0 {
|
|
+ status = "okay";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&spi_quad_pins>;
|
|
+
|
|
+ flash@0 {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <54000000>;
|
|
+
|
|
+ partitions {
|
|
+ compatible = "fixed-partitions";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ /* only bootloader is located on the SPI */
|
|
+ partition@0 {
|
|
+ label = "uboot";
|
|
+ reg = <0 0x400000>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&i2c0 {
|
|
+ status = "okay";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c1_pins>;
|
|
+};
|
|
+
|
|
+&i2c1 {
|
|
+ status = "okay";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c2_pins>;
|
|
+
|
|
+ lm75@48 {
|
|
+ status = "okay";
|
|
+ compatible = "lm75";
|
|
+ reg = <0x48>;
|
|
+ };
|
|
+
|
|
+ lm75@49 {
|
|
+ status = "okay";
|
|
+ compatible = "lm75";
|
|
+ reg = <0x49>;
|
|
+ };
|
|
+};
|
|
+
|
|
+ð0 {
|
|
+ status = "okay";
|
|
+ phy-mode = "sgmii";
|
|
+ managed = "in-band-status";
|
|
+ sfp = <&sfp_eth0>;
|
|
+};
|
|
+
|
|
+ð1 {
|
|
+ status = "okay";
|
|
+ phy-mode = "sgmii";
|
|
+ managed = "in-band-status";
|
|
+ sfp = <&sfp_eth1>;
|
|
+};
|
|
+
|
|
+&usb3 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart0 {
|
|
+ status = "okay";
|
|
+};
|
|
diff --git a/target/linux/mvebu/patches-5.4/002-add_powertables.patch b/target/linux/mvebu/patches-5.4/002-add_powertables.patch
|
|
new file mode 100644
|
|
index 00000000000..c2fb748d5d0
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/002-add_powertables.patch
|
|
@@ -0,0 +1,770 @@
|
|
+--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
|
|
++++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
|
|
+@@ -212,11 +212,19 @@
|
|
+ &pcie1 {
|
|
+ /* Marvell 88W8864, 5GHz-only */
|
|
+ status = "okay";
|
|
++
|
|
++ mwlwifi {
|
|
++ marvell,2ghz = <0>;
|
|
++ };
|
|
+ };
|
|
+
|
|
+ &pcie2 {
|
|
+ /* Marvell 88W8864, 2GHz-only */
|
|
+ status = "okay";
|
|
++
|
|
++ mwlwifi {
|
|
++ marvell,5ghz = <0>;
|
|
++ };
|
|
+ };
|
|
+
|
|
+ &pinctrl {
|
|
+--- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts
|
|
++++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
|
|
+@@ -142,3 +142,205 @@
|
|
+ };
|
|
+ };
|
|
+ };
|
|
++
|
|
++&pcie1 {
|
|
++ mwlwifi {
|
|
++ marvell,chainmask = <2 2>;
|
|
++ marvell,powertable {
|
|
++ AU =
|
|
++ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <100 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
|
|
++ <104 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
|
|
++ <108 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
|
|
++ <112 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
|
|
++ <116 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
|
|
++ <120 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
|
|
++ <124 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
|
|
++ <128 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
|
|
++ <132 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
|
|
++ <136 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
|
|
++ <140 0 0x17 0x17 0x17 0x17 0x17 0x17 0x17 0x15 0x17 0x17 0x17 0x14 0x17 0x17 0x17 0x14 0 0xf>,
|
|
++ <149 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
|
|
++ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
|
|
++ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
|
|
++ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>,
|
|
++ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x1a 0x1a 0x17 0x14 0 0xf>;
|
|
++ CA =
|
|
++ <36 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
|
|
++ <40 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
|
|
++ <44 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
|
|
++ <48 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0 0xf>,
|
|
++ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
|
|
++ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
|
|
++ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
|
|
++ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
|
|
++ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>;
|
|
++ CN =
|
|
++ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <149 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <165 0 0x15 0x15 0x15 0x15 0x16 0x16 0x16 0x15 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0 0xf>;
|
|
++ ETSI =
|
|
++ <36 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <40 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <44 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <48 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <52 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <56 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <60 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <64 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <100 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <104 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <108 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <112 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <116 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <120 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <124 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <128 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <132 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <136 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <140 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>,
|
|
++ <149 0 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0 0xf>;
|
|
++ FCC =
|
|
++ <36 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <40 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <44 0 0x19 0x19 0x18 0x17 0x19 0x19 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <48 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x17 0x17 0x17 0x14 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <149 0 0x1a 0x1a 0x18 0x17 0x19 0x19 0x17 0x15 0x18 0x18 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
|
|
++ <153 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
|
|
++ <157 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
|
|
++ <161 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>,
|
|
++ <165 0 0x1a 0x1a 0x18 0x17 0x1a 0x1a 0x17 0x15 0x1a 0x1a 0x17 0x14 0x15 0x15 0x15 0x14 0 0xf>;
|
|
++ };
|
|
++ };
|
|
++};
|
|
++
|
|
++&pcie2 {
|
|
++ mwlwifi {
|
|
++ marvell,chainmask = <2 2>;
|
|
++ marvell,powertable {
|
|
++ AU =
|
|
++ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
|
|
++ CA =
|
|
++ <1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x00 0x00 0x00 0x00 0 0xf>,
|
|
++ <2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
|
|
++ <3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
|
|
++ <4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
|
|
++ <5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
|
|
++ <6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
|
|
++ <7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
|
|
++ <8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
|
|
++ <9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
|
|
++ <10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x00 0x00 0x00 0x00 0 0xf>,
|
|
++ <11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x00 0x00 0x00 0x00 0 0xf>;
|
|
++ CN =
|
|
++ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <14 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
|
|
++ ETSI =
|
|
++ <1 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <2 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <3 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <4 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <5 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <6 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <7 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <8 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <9 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <10 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <11 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <12 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <13 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0x0 0x0 0x0 0x0 0 0xf>;
|
|
++ FCC =
|
|
++ <1 0 0x19 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <2 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <3 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <4 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <5 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <6 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <7 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <8 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <9 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <10 0 0x1a 0x19 0x18 0x17 0x19 0x19 0x17 0x16 0x14 0x14 0x14 0x14 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <11 0 0x19 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x0 0x0 0x0 0x0 0 0xf>;
|
|
++ };
|
|
++ };
|
|
++};
|
|
+--- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts
|
|
++++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
|
|
+@@ -142,3 +142,205 @@
|
|
+ };
|
|
+ };
|
|
+ };
|
|
++
|
|
++&pcie1 {
|
|
++ mwlwifi {
|
|
++ marvell,chainmask = <4 4>;
|
|
++ marvell,powertable {
|
|
++ AU =
|
|
++ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
|
|
++ <153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
|
|
++ <157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
|
|
++ <161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
|
|
++ <165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>;
|
|
++ CA =
|
|
++ <36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
|
|
++ <40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
|
|
++ <44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
|
|
++ <48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
|
|
++ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
|
++ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
|
++ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
|
++ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
|
++ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
|
|
++ CN =
|
|
++ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>;
|
|
++ ETSI =
|
|
++ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>;
|
|
++ FCC =
|
|
++ <36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>,
|
|
++ <40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
|
|
++ <44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
|
|
++ <48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
|
|
++ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
|
++ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
|
++ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
|
++ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
|
++ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
|
|
++ };
|
|
++ };
|
|
++};
|
|
++
|
|
++&pcie2 {
|
|
++ mwlwifi {
|
|
++ marvell,chainmask = <4 4>;
|
|
++ marvell,powertable {
|
|
++ AU =
|
|
++ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
|
|
++ CA =
|
|
++ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
|
|
++ CN =
|
|
++ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
|
|
++ ETSI =
|
|
++ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
|
|
++ FCC =
|
|
++ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
|
|
++ };
|
|
++ };
|
|
++};
|
|
+--- a/arch/arm/boot/dts/armada-385-linksys-shelby.dts
|
|
++++ b/arch/arm/boot/dts/armada-385-linksys-shelby.dts
|
|
+@@ -142,3 +142,205 @@
|
|
+ };
|
|
+ };
|
|
+ };
|
|
++
|
|
++&pcie1 {
|
|
++ mwlwifi {
|
|
++ marvell,chainmask = <4 4>;
|
|
++ marvell,powertable {
|
|
++ AU =
|
|
++ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <149 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
|
|
++ <153 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
|
|
++ <157 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
|
|
++ <161 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>,
|
|
++ <165 0 0x19 0x19 0x19 0x17 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0x19 0x19 0x16 0x15 0 0xf>;
|
|
++ CA =
|
|
++ <36 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
|
|
++ <40 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
|
|
++ <44 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
|
|
++ <48 0 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
|
|
++ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
|
++ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
|
++ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
|
++ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
|
++ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
|
|
++ CN =
|
|
++ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <149 0 0x14 0x14 0x14 0x14 0x13 0x13 0x13 0x13 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <165 0 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x13 0x14 0x14 0x14 0x14 0x10 0x10 0x10 0x10 0 0xf>;
|
|
++ ETSI =
|
|
++ <36 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <40 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <44 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <48 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <52 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <56 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <60 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <64 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <100 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <104 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <108 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <112 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <116 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <120 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <124 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <128 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <132 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <136 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <140 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>,
|
|
++ <149 0 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xd 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0xe 0 0xf>;
|
|
++ FCC =
|
|
++ <36 0 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0 0xf>,
|
|
++ <40 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
|
|
++ <44 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
|
|
++ <48 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0xf 0xf 0xf 0xf 0 0xf>,
|
|
++ <52 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <56 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <60 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <64 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <100 0 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <104 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x12 0x12 0x12 0x12 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <108 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <112 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <116 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <120 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <124 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <128 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <132 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <136 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <140 0 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0 0xf>,
|
|
++ <149 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
|
++ <153 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
|
++ <157 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
|
++ <161 0 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>,
|
|
++ <165 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0 0xf>;
|
|
++ };
|
|
++ };
|
|
++};
|
|
++
|
|
++&pcie2 {
|
|
++ mwlwifi {
|
|
++ marvell,chainmask = <4 4>;
|
|
++ marvell,powertable {
|
|
++ AU =
|
|
++ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
|
|
++ CA =
|
|
++ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
|
|
++ CN =
|
|
++ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <14 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
|
|
++ ETSI =
|
|
++ <1 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <2 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <3 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <4 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <5 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <6 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <7 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <8 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <9 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <10 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <11 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <12 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <13 0 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0xa 0x0 0x0 0x0 0x0 0 0xf>;
|
|
++ FCC =
|
|
++ <1 0 0x17 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0xe 0xe 0xe 0xe 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <2 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <3 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <4 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <5 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <6 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <7 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <8 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <9 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <10 0 0x18 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x11 0x11 0x11 0x11 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <11 0 0x17 0x12 0x12 0x12 0x13 0x13 0x13 0x13 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>;
|
|
++ };
|
|
++ };
|
|
++};
|
|
+--- a/arch/arm/boot/dts/armada-385-linksys-rango.dts
|
|
++++ b/arch/arm/boot/dts/armada-385-linksys-rango.dts
|
|
+@@ -157,6 +157,18 @@
|
|
+ };
|
|
+ };
|
|
+
|
|
++&pcie1 {
|
|
++ mwlwifi {
|
|
++ marvell,chainmask = <4 4>;
|
|
++ };
|
|
++};
|
|
++
|
|
++&pcie2 {
|
|
++ mwlwifi {
|
|
++ marvell,chainmask = <4 4>;
|
|
++ };
|
|
++};
|
|
++
|
|
+ &sdhci {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&sdhci_pins>;
|
|
+--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
|
++++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
|
+@@ -272,12 +272,100 @@
|
|
+ pcie@2,0 {
|
|
+ /* Port 0, Lane 1 */
|
|
+ status = "okay";
|
|
++
|
|
++ mwlwifi {
|
|
++ marvell,5ghz = <0>;
|
|
++ marvell,chainmask = <4 4>;
|
|
++ marvell,powertable {
|
|
++ FCC =
|
|
++ <1 0 0x17 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0xf 0xf 0xf 0xf 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <2 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <3 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <4 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <5 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <6 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <7 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <8 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <9 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <10 0 0x17 0x16 0x16 0x16 0x16 0x16 0x16 0x14 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <11 0 0x17 0x11 0x11 0x11 0x11 0x11 0x11 0x11 0x10 0x10 0x10 0x10 0x0 0x0 0x0 0x0 0 0xf>;
|
|
++
|
|
++ ETSI =
|
|
++ <1 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <2 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <3 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <4 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <5 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <6 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <7 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <8 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <9 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <10 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <11 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <12 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>,
|
|
++ <13 0 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0xb 0x0 0x0 0x0 0x0 0 0xf>;
|
|
++ };
|
|
++ };
|
|
+ };
|
|
+
|
|
+ /* Second mini-PCIe port */
|
|
+ pcie@3,0 {
|
|
+ /* Port 0, Lane 3 */
|
|
+ status = "okay";
|
|
++
|
|
++ mwlwifi {
|
|
++ marvell,2ghz = <0>;
|
|
++ marvell,chainmask = <4 4>;
|
|
++ marvell,powertable {
|
|
++ FCC =
|
|
++ <36 0 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
|
|
++ <40 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
|
|
++ <44 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
|
|
++ <48 0 0x8 0x8 0x8 0x8 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0x9 0 0xf>,
|
|
++ <52 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
|
|
++ <56 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
|
|
++ <60 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
|
|
++ <64 0 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0xf 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0x12 0 0xf>,
|
|
++ <100 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <104 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <108 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <112 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <116 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <120 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <124 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <128 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <132 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <136 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <140 0 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <149 0 0x16 0x16 0x16 0x16 0x14 0x14 0x14 0x14 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <153 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <157 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <161 0 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>,
|
|
++ <165 0 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x16 0x15 0x15 0x15 0x15 0x14 0x14 0x14 0x14 0 0xf>;
|
|
++
|
|
++ ETSI =
|
|
++ <36 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
|
++ <40 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
|
++ <44 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
|
++ <48 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
|
++ <52 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
|
++ <56 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
|
++ <60 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
|
++ <64 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
|
++ <100 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
|
++ <104 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
|
++ <108 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
|
++ <112 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
|
++ <116 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
|
++ <120 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
|
++ <124 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
|
++ <128 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
|
++ <132 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
|
++ <136 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
|
++ <140 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>,
|
|
++ <149 0 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xc 0xd 0xd 0xd 0xd 0xc 0xc 0xc 0xc 0 0xf>;
|
|
++ };
|
|
++ };
|
|
+ };
|
|
+ };
|
|
+
|
|
diff --git a/target/linux/mvebu/patches-5.4/003-add_switch_nodes.patch b/target/linux/mvebu/patches-5.4/003-add_switch_nodes.patch
|
|
new file mode 100644
|
|
index 00000000000..b2086389163
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/003-add_switch_nodes.patch
|
|
@@ -0,0 +1,40 @@
|
|
+--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
|
++++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
|
+@@ -257,6 +257,16 @@
|
|
+ };
|
|
+ };
|
|
+ };
|
|
++
|
|
++ mvsw61xx {
|
|
++ compatible = "marvell,88e6172";
|
|
++ status = "okay";
|
|
++ reg = <0x10>;
|
|
++
|
|
++ mii-bus = <&mdio>;
|
|
++ cpu-port-0 = <5>;
|
|
++ cpu-port-1 = <6>;
|
|
++ };
|
|
+ };
|
|
+
|
|
+ &pciec {
|
|
+--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
|
|
++++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
|
|
+@@ -82,6 +82,18 @@
|
|
+ linux,default-trigger = "disk-activity";
|
|
+ };
|
|
+ };
|
|
++
|
|
++ mvsw61xx {
|
|
++ #address-cells = <1>;
|
|
++ #size-cells = <0>;
|
|
++ compatible = "marvell,88e6176";
|
|
++ status = "okay";
|
|
++ reg = <0x10>;
|
|
++
|
|
++ mii-bus = <&mdio>;
|
|
++ cpu-port-0 = <5>;
|
|
++ cpu-port-1 = <6>;
|
|
++ };
|
|
+ };
|
|
+
|
|
+ &ahci0 {
|
|
diff --git a/target/linux/mvebu/patches-5.4/004-add_sata_disk_activity_trigger.patch b/target/linux/mvebu/patches-5.4/004-add_sata_disk_activity_trigger.patch
|
|
new file mode 100644
|
|
index 00000000000..2cb8f254906
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/004-add_sata_disk_activity_trigger.patch
|
|
@@ -0,0 +1,39 @@
|
|
+From 172230195068703b78ad5733a09492f5d6814c09 Mon Sep 17 00:00:00 2001
|
|
+From: Ansuel Smith <ansuelsmth@gmail.com>
|
|
+Date: Tue, 28 Feb 2017 14:15:50 +0100
|
|
+Subject: [PATCH] ARM: dts: armada: Add default trigger for sata led
|
|
+
|
|
+In others board we have the sata led set to function
|
|
+with the sata led trigger by default.
|
|
+This patch makes the same for these board that have sata
|
|
+led but get disabled by not associating it to any trigger.
|
|
+
|
|
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
|
|
+Acked-by: Jason Cooper <jason@lakedaemon.net>
|
|
+Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
|
|
+---
|
|
+ arch/arm/boot/dts/armada-385-linksys-caiman.dts | 1 +
|
|
+ arch/arm/boot/dts/armada-385-linksys-cobra.dts | 1 +
|
|
+ arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 1 +
|
|
+ 3 files changed, 3 insertions(+)
|
|
+
|
|
+--- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts
|
|
++++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
|
|
+@@ -68,6 +68,7 @@
|
|
+
|
|
+ sata {
|
|
+ label = "caiman:white:sata";
|
|
++ linux,default-trigger = "disk-activity";
|
|
+ };
|
|
+ };
|
|
+
|
|
+--- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts
|
|
++++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
|
|
+@@ -68,6 +68,7 @@
|
|
+
|
|
+ sata {
|
|
+ label = "cobra:white:sata";
|
|
++ linux,default-trigger = "disk-activity";
|
|
+ };
|
|
+ };
|
|
+
|
|
diff --git a/target/linux/mvebu/patches-5.4/005-linksys_hardcode_nand_ecc_settings.patch b/target/linux/mvebu/patches-5.4/005-linksys_hardcode_nand_ecc_settings.patch
|
|
new file mode 100644
|
|
index 00000000000..dfe13bae7b5
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/005-linksys_hardcode_nand_ecc_settings.patch
|
|
@@ -0,0 +1,17 @@
|
|
+Newer Linksys boards might come with a Winbond W29N02GV which can be
|
|
+configured in different ways. Make sure we configure it the same way
|
|
+as the older chips so everything keeps working.
|
|
+
|
|
+Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
|
|
+
|
|
+--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
|
|
++++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
|
|
+@@ -160,6 +160,8 @@
|
|
+ reg = <0>;
|
|
+ label = "pxa3xx_nand-0";
|
|
+ nand-rb = <0>;
|
|
++ nand-ecc-strength = <4>;
|
|
++ nand-ecc-step-size = <512>;
|
|
+ marvell,nand-keep-config;
|
|
+ nand-on-flash-bbt;
|
|
+ };
|
|
diff --git a/target/linux/mvebu/patches-5.4/006-mvebu-Mangle-bootloader-s-kernel-arguments.patch b/target/linux/mvebu/patches-5.4/006-mvebu-Mangle-bootloader-s-kernel-arguments.patch
|
|
new file mode 100644
|
|
index 00000000000..0cb9e996027
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/006-mvebu-Mangle-bootloader-s-kernel-arguments.patch
|
|
@@ -0,0 +1,201 @@
|
|
+From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001
|
|
+From: Adrian Panella <ianchi74@outlook.com>
|
|
+Date: Thu, 9 Mar 2017 09:37:17 +0100
|
|
+Subject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments
|
|
+
|
|
+The command-line arguments provided by the boot loader will be
|
|
+appended to a new device tree property: bootloader-args.
|
|
+If there is a property "append-rootblock" in DT under /chosen
|
|
+and a root= option in bootloaders command line it will be parsed
|
|
+and added to DT bootargs with the form: <append-rootblock>XX.
|
|
+Only command line ATAG will be processed, the rest of the ATAGs
|
|
+sent by bootloader will be ignored.
|
|
+This is usefull in dual boot systems, to get the current root partition
|
|
+without afecting the rest of the system.
|
|
+
|
|
+Signed-off-by: Adrian Panella <ianchi74@outlook.com>
|
|
+
|
|
+This patch has been modified to be mvebu specific. The original patch
|
|
+did not pass the bootloader cmdline on if no append-rootblock stanza
|
|
+was found, resulting in blank cmdline and failure to boot.
|
|
+
|
|
+Signed-off-by: Michael Gray <michael.gray@lantisproject.com>
|
|
+---
|
|
+ arch/arm/Kconfig | 11 +++++
|
|
+ arch/arm/boot/compressed/atags_to_fdt.c | 72 ++++++++++++++++++++++++++++++++-
|
|
+ init/main.c | 16 ++++++++
|
|
+ 3 files changed, 98 insertions(+), 1 deletion(-)
|
|
+
|
|
+--- a/arch/arm/Kconfig
|
|
++++ b/arch/arm/Kconfig
|
|
+@@ -1926,6 +1926,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
|
|
+ The command-line arguments provided by the boot loader will be
|
|
+ appended to the the device tree bootargs property.
|
|
+
|
|
++config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
|
|
++ bool "Append rootblock parsing bootloader's kernel arguments"
|
|
++ help
|
|
++ The command-line arguments provided by the boot loader will be
|
|
++ appended to a new device tree property: bootloader-args.
|
|
++ If there is a property "append-rootblock" in DT under /chosen
|
|
++ and a root= option in bootloaders command line it will be parsed
|
|
++ and added to DT bootargs with the form: <append-rootblock>XX.
|
|
++ Only command line ATAG will be processed, the rest of the ATAGs
|
|
++ sent by bootloader will be ignored.
|
|
++
|
|
+ endchoice
|
|
+
|
|
+ config CMDLINE
|
|
+--- a/arch/arm/boot/compressed/atags_to_fdt.c
|
|
++++ b/arch/arm/boot/compressed/atags_to_fdt.c
|
|
+@@ -4,6 +4,8 @@
|
|
+
|
|
+ #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)
|
|
+ #define do_extend_cmdline 1
|
|
++#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
|
|
++#define do_extend_cmdline 1
|
|
+ #else
|
|
+ #define do_extend_cmdline 0
|
|
+ #endif
|
|
+@@ -67,6 +69,65 @@ static uint32_t get_cell_size(const void
|
|
+ return cell_size;
|
|
+ }
|
|
+
|
|
++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
|
|
++
|
|
++static char *append_rootblock(char *dest, const char *str, int len, void *fdt)
|
|
++{
|
|
++ char *ptr, *end;
|
|
++ char *root="root=";
|
|
++ int i, l;
|
|
++ const char *rootblock;
|
|
++
|
|
++ //ARM doesn't have __HAVE_ARCH_STRSTR, so search manually
|
|
++ ptr = str - 1;
|
|
++
|
|
++ do {
|
|
++ //first find an 'r' at the begining or after a space
|
|
++ do {
|
|
++ ptr++;
|
|
++ ptr = strchr(ptr, 'r');
|
|
++ if(!ptr) return dest;
|
|
++
|
|
++ } while (ptr != str && *(ptr-1) != ' ');
|
|
++
|
|
++ //then check for the rest
|
|
++ for(i = 1; i <= 4; i++)
|
|
++ if(*(ptr+i) != *(root+i)) break;
|
|
++
|
|
++ } while (i != 5);
|
|
++
|
|
++ end = strchr(ptr, ' ');
|
|
++ end = end ? (end - 1) : (strchr(ptr, 0) - 1);
|
|
++
|
|
++ //find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX )
|
|
++ for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++);
|
|
++ ptr = end + 1;
|
|
++
|
|
++ /* if append-rootblock property is set use it to append to command line */
|
|
++ rootblock = getprop(fdt, "/chosen", "append-rootblock", &l);
|
|
++ if(rootblock != NULL) {
|
|
++ if(*dest != ' ') {
|
|
++ *dest = ' ';
|
|
++ dest++;
|
|
++ len++;
|
|
++ }
|
|
++ if (len + l + i <= COMMAND_LINE_SIZE) {
|
|
++ memcpy(dest, rootblock, l);
|
|
++ dest += l - 1;
|
|
++ memcpy(dest, ptr, i);
|
|
++ dest += i;
|
|
++ }
|
|
++ } else {
|
|
++ len = strlen(str);
|
|
++ if (len + 1 < COMMAND_LINE_SIZE) {
|
|
++ memcpy(dest, str, len);
|
|
++ dest += len;
|
|
++ }
|
|
++ }
|
|
++ return dest;
|
|
++}
|
|
++#endif
|
|
++
|
|
+ static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
|
|
+ {
|
|
+ char cmdline[COMMAND_LINE_SIZE];
|
|
+@@ -86,12 +147,21 @@ static void merge_fdt_bootargs(void *fdt
|
|
+
|
|
+ /* and append the ATAG_CMDLINE */
|
|
+ if (fdt_cmdline) {
|
|
++
|
|
++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
|
|
++ //save original bootloader args
|
|
++ //and append ubi.mtd with root partition number to current cmdline
|
|
++ setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline);
|
|
++ ptr = append_rootblock(ptr, fdt_cmdline, len, fdt);
|
|
++
|
|
++#else
|
|
+ len = strlen(fdt_cmdline);
|
|
+ if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
|
|
+ *ptr++ = ' ';
|
|
+ memcpy(ptr, fdt_cmdline, len);
|
|
+ ptr += len;
|
|
+ }
|
|
++#endif
|
|
+ }
|
|
+ *ptr = '\0';
|
|
+
|
|
+@@ -148,7 +218,9 @@ int atags_to_fdt(void *atag_list, void *
|
|
+ else
|
|
+ setprop_string(fdt, "/chosen", "bootargs",
|
|
+ atag->u.cmdline.cmdline);
|
|
+- } else if (atag->hdr.tag == ATAG_MEM) {
|
|
++ }
|
|
++#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
|
|
++ else if (atag->hdr.tag == ATAG_MEM) {
|
|
+ if (memcount >= sizeof(mem_reg_property)/4)
|
|
+ continue;
|
|
+ if (!atag->u.mem.size)
|
|
+@@ -187,6 +259,10 @@ int atags_to_fdt(void *atag_list, void *
|
|
+ setprop(fdt, "/memory", "reg", mem_reg_property,
|
|
+ 4 * memcount * memsize);
|
|
+ }
|
|
++#else
|
|
++
|
|
++ }
|
|
++#endif
|
|
+
|
|
+ return fdt_pack(fdt);
|
|
+ }
|
|
+--- a/init/main.c
|
|
++++ b/init/main.c
|
|
+@@ -102,6 +102,10 @@
|
|
+ #define CREATE_TRACE_POINTS
|
|
+ #include <trace/events/initcall.h>
|
|
+
|
|
++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
|
|
++#include <linux/of.h>
|
|
++#endif
|
|
++
|
|
+ static int kernel_init(void *);
|
|
+
|
|
+ extern void init_IRQ(void);
|
|
+@@ -591,6 +595,18 @@ asmlinkage __visible void __init start_k
|
|
+ page_alloc_init();
|
|
+
|
|
+ pr_notice("Kernel command line: %s\n", boot_command_line);
|
|
++
|
|
++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
|
|
++ //Show bootloader's original command line for reference
|
|
++ if(of_chosen) {
|
|
++ const char *prop = of_get_property(of_chosen, "bootloader-args", NULL);
|
|
++ if(prop)
|
|
++ pr_notice("Bootloader command line (ignored): %s\n", prop);
|
|
++ else
|
|
++ pr_notice("Bootloader command line not present\n");
|
|
++ }
|
|
++#endif
|
|
++
|
|
+ /* parameters may set static keys */
|
|
+ jump_label_init();
|
|
+ parse_early_param();
|
|
diff --git a/target/linux/mvebu/patches-5.4/100-find_active_root.patch b/target/linux/mvebu/patches-5.4/100-find_active_root.patch
|
|
new file mode 100644
|
|
index 00000000000..f52a5108b85
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/100-find_active_root.patch
|
|
@@ -0,0 +1,60 @@
|
|
+The WRT1900AC among other Linksys routers uses a dual-firmware layout.
|
|
+Dynamically rename the active partition to "ubi".
|
|
+
|
|
+Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
|
|
+
|
|
+--- a/drivers/mtd/ofpart.c
|
|
++++ b/drivers/mtd/ofpart.c
|
|
+@@ -25,6 +25,8 @@ static bool node_has_compatible(struct d
|
|
+ return of_get_property(pp, "compatible", NULL);
|
|
+ }
|
|
+
|
|
++static int mangled_rootblock;
|
|
++
|
|
+ static int parse_fixed_partitions(struct mtd_info *master,
|
|
+ const struct mtd_partition **pparts,
|
|
+ struct mtd_part_parser_data *data)
|
|
+@@ -33,6 +35,7 @@ static int parse_fixed_partitions(struct
|
|
+ struct device_node *mtd_node;
|
|
+ struct device_node *ofpart_node;
|
|
+ const char *partname;
|
|
++ const char *owrtpart = "ubi";
|
|
+ struct device_node *pp;
|
|
+ int nr_parts, i, ret = 0;
|
|
+ bool dedicated = true;
|
|
+@@ -110,9 +113,13 @@ static int parse_fixed_partitions(struct
|
|
+ parts[i].size = of_read_number(reg + a_cells, s_cells);
|
|
+ parts[i].of_node = pp;
|
|
+
|
|
+- partname = of_get_property(pp, "label", &len);
|
|
+- if (!partname)
|
|
+- partname = of_get_property(pp, "name", &len);
|
|
++ if (mangled_rootblock && (i == mangled_rootblock)) {
|
|
++ partname = owrtpart;
|
|
++ } else {
|
|
++ partname = of_get_property(pp, "label", &len);
|
|
++ if (!partname)
|
|
++ partname = of_get_property(pp, "name", &len);
|
|
++ }
|
|
+ parts[i].name = partname;
|
|
+
|
|
+ if (of_get_property(pp, "read-only", &len))
|
|
+@@ -219,6 +226,18 @@ static int __init ofpart_parser_init(voi
|
|
+ return 0;
|
|
+ }
|
|
+
|
|
++static int __init active_root(char *str)
|
|
++{
|
|
++ get_option(&str, &mangled_rootblock);
|
|
++
|
|
++ if (!mangled_rootblock)
|
|
++ return 1;
|
|
++
|
|
++ return 1;
|
|
++}
|
|
++
|
|
++__setup("mangled_rootblock=", active_root);
|
|
++
|
|
+ static void __exit ofpart_parser_exit(void)
|
|
+ {
|
|
+ deregister_mtd_parser(&ofpart_parser);
|
|
diff --git a/target/linux/mvebu/patches-5.4/102-revert_i2c_delay.patch b/target/linux/mvebu/patches-5.4/102-revert_i2c_delay.patch
|
|
new file mode 100644
|
|
index 00000000000..930c0f94942
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/102-revert_i2c_delay.patch
|
|
@@ -0,0 +1,15 @@
|
|
+--- a/arch/arm/boot/dts/armada-xp.dtsi
|
|
++++ b/arch/arm/boot/dts/armada-xp.dtsi
|
|
+@@ -237,12 +237,10 @@
|
|
+ };
|
|
+
|
|
+ &i2c0 {
|
|
+- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
|
|
+ reg = <0x11000 0x100>;
|
|
+ };
|
|
+
|
|
+ &i2c1 {
|
|
+- compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
|
|
+ reg = <0x11100 0x100>;
|
|
+ };
|
|
+
|
|
diff --git a/target/linux/mvebu/patches-5.4/205-armada-385-rd-mtd-partitions.patch b/target/linux/mvebu/patches-5.4/205-armada-385-rd-mtd-partitions.patch
|
|
new file mode 100644
|
|
index 00000000000..31bd53b1f3b
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/205-armada-385-rd-mtd-partitions.patch
|
|
@@ -0,0 +1,19 @@
|
|
+--- a/arch/arm/boot/dts/armada-388-rd.dts
|
|
++++ b/arch/arm/boot/dts/armada-388-rd.dts
|
|
+@@ -103,6 +103,16 @@
|
|
+ compatible = "st,m25p128", "jedec,spi-nor";
|
|
+ reg = <0>; /* Chip select 0 */
|
|
+ spi-max-frequency = <108000000>;
|
|
++
|
|
++ partition@0 {
|
|
++ label = "uboot";
|
|
++ reg = <0 0x400000>;
|
|
++ };
|
|
++
|
|
++ partition@1 {
|
|
++ label = "firmware";
|
|
++ reg = <0x400000 0xc00000>;
|
|
++ };
|
|
+ };
|
|
+ };
|
|
+
|
|
diff --git a/target/linux/mvebu/patches-5.4/206-ARM-mvebu-385-ap-Add-partitions.patch b/target/linux/mvebu/patches-5.4/206-ARM-mvebu-385-ap-Add-partitions.patch
|
|
new file mode 100644
|
|
index 00000000000..2057e31c7e9
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/206-ARM-mvebu-385-ap-Add-partitions.patch
|
|
@@ -0,0 +1,35 @@
|
|
+From 9861f93a59142a3131870df2521eb2deb73026d7 Mon Sep 17 00:00:00 2001
|
|
+From: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
+Date: Tue, 13 Jan 2015 11:14:09 +0100
|
|
+Subject: [PATCH 2/2] ARM: mvebu: 385-ap: Add partitions
|
|
+
|
|
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
+---
|
|
+ arch/arm/boot/dts/armada-385-db-ap.dts | 15 +++++++++++++++
|
|
+ 1 file changed, 15 insertions(+)
|
|
+
|
|
+--- a/arch/arm/boot/dts/armada-385-db-ap.dts
|
|
++++ b/arch/arm/boot/dts/armada-385-db-ap.dts
|
|
+@@ -218,19 +218,19 @@
|
|
+ #size-cells = <1>;
|
|
+
|
|
+ partition@0 {
|
|
+- label = "U-Boot";
|
|
++ label = "u-boot";
|
|
+ reg = <0x00000000 0x00800000>;
|
|
+ read-only;
|
|
+ };
|
|
+
|
|
+ partition@800000 {
|
|
+- label = "uImage";
|
|
++ label = "kernel";
|
|
+ reg = <0x00800000 0x00400000>;
|
|
+ read-only;
|
|
+ };
|
|
+
|
|
+ partition@c00000 {
|
|
+- label = "Root";
|
|
++ label = "ubi";
|
|
+ reg = <0x00c00000 0x3f400000>;
|
|
+ };
|
|
+ };
|
|
diff --git a/target/linux/mvebu/patches-5.4/210-clearfog_switch_node.patch b/target/linux/mvebu/patches-5.4/210-clearfog_switch_node.patch
|
|
new file mode 100644
|
|
index 00000000000..f9677a82f2e
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/210-clearfog_switch_node.patch
|
|
@@ -0,0 +1,21 @@
|
|
+--- a/arch/arm/boot/dts/armada-388-clearfog.dts
|
|
++++ b/arch/arm/boot/dts/armada-388-clearfog.dts
|
|
+@@ -88,6 +88,18 @@
|
|
+ };
|
|
+ };
|
|
+
|
|
++ mvsw61xx {
|
|
++ #address-cells = <1>;
|
|
++ #size-cells = <0>;
|
|
++ compatible = "marvell,88e6176";
|
|
++ status = "okay";
|
|
++ reg = <0x4>;
|
|
++ is-indirect;
|
|
++
|
|
++ mii-bus = <&mdio>;
|
|
++ cpu-port-0 = <5>;
|
|
++ };
|
|
++
|
|
+ gpio-keys {
|
|
+ compatible = "gpio-keys";
|
|
+ pinctrl-0 = <&rear_button_pins>;
|
|
diff --git a/target/linux/mvebu/patches-5.4/220-disable-untested-dsa-boards.patch b/target/linux/mvebu/patches-5.4/220-disable-untested-dsa-boards.patch
|
|
new file mode 100644
|
|
index 00000000000..9cc7a113f6c
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/220-disable-untested-dsa-boards.patch
|
|
@@ -0,0 +1,30 @@
|
|
+--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
|
|
++++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
|
|
+@@ -171,6 +171,7 @@
|
|
+ status = "okay";
|
|
+
|
|
+ switch@0 {
|
|
++ status = "disabled";
|
|
+ compatible = "marvell,mv88e6085";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+--- a/arch/arm/boot/dts/armada-388-clearfog.dts
|
|
++++ b/arch/arm/boot/dts/armada-388-clearfog.dts
|
|
+@@ -161,6 +161,7 @@
|
|
+ status = "okay";
|
|
+
|
|
+ switch@4 {
|
|
++ status = "disabled";
|
|
+ compatible = "marvell,mv88e6085";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
|
++++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
|
+@@ -413,6 +413,7 @@
|
|
+ status = "okay";
|
|
+
|
|
+ switch@0 {
|
|
++ status = "disabled";
|
|
+ compatible = "marvell,mv88e6085";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
diff --git a/target/linux/mvebu/patches-5.4/230-armada-xp-linksys-mamba-broken-idle.patch b/target/linux/mvebu/patches-5.4/230-armada-xp-linksys-mamba-broken-idle.patch
|
|
new file mode 100644
|
|
index 00000000000..935c8fe0935
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/230-armada-xp-linksys-mamba-broken-idle.patch
|
|
@@ -0,0 +1,10 @@
|
|
+--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
|
++++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
|
+@@ -543,3 +543,7 @@
|
|
+ };
|
|
+ };
|
|
+ };
|
|
++
|
|
++&coherencyfab {
|
|
++ broken-idle;
|
|
++};
|
|
diff --git a/target/linux/mvebu/patches-5.4/240-linksys-status-led.patch b/target/linux/mvebu/patches-5.4/240-linksys-status-led.patch
|
|
new file mode 100644
|
|
index 00000000000..e5e83572c9e
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/240-linksys-status-led.patch
|
|
@@ -0,0 +1,50 @@
|
|
+--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
|
|
++++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
|
|
+@@ -14,6 +14,13 @@
|
|
+ compatible = "linksys,armada385", "marvell,armada385",
|
|
+ "marvell,armada380";
|
|
+
|
|
++ aliases {
|
|
++ led-boot = &led_power;
|
|
++ led-failsafe = &led_power;
|
|
++ led-running = &led_power;
|
|
++ led-upgrade = &led_power;
|
|
++ };
|
|
++
|
|
+ chosen {
|
|
+ stdout-path = "serial0:115200n8";
|
|
+ };
|
|
+@@ -71,7 +78,7 @@
|
|
+ pinctrl-0 = <&gpio_leds_pins>;
|
|
+ pinctrl-names = "default";
|
|
+
|
|
+- power {
|
|
++ led_power: power {
|
|
+ gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
|
|
+ default-state = "on";
|
|
+ };
|
|
+--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
|
++++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
|
+@@ -26,6 +26,13 @@
|
|
+ compatible = "linksys,mamba", "marvell,armadaxp-mv78230",
|
|
+ "marvell,armadaxp", "marvell,armada-370-xp";
|
|
+
|
|
++ aliases {
|
|
++ led-boot = &led_power;
|
|
++ led-failsafe = &led_power;
|
|
++ led-running = &led_power;
|
|
++ led-upgrade = &led_power;
|
|
++ };
|
|
++
|
|
+ chosen {
|
|
+ bootargs = "console=ttyS0,115200";
|
|
+ stdout-path = &uart0;
|
|
+@@ -197,7 +204,7 @@
|
|
+ pinctrl-0 = <&power_led_pin>;
|
|
+ pinctrl-names = "default";
|
|
+
|
|
+- power {
|
|
++ led_power: power {
|
|
+ label = "mamba:white:power";
|
|
+ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
|
|
+ default-state = "on";
|
|
diff --git a/target/linux/mvebu/patches-5.4/300-mvneta-tx-queue-workaround.patch b/target/linux/mvebu/patches-5.4/300-mvneta-tx-queue-workaround.patch
|
|
new file mode 100644
|
|
index 00000000000..4a5ea361449
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/300-mvneta-tx-queue-workaround.patch
|
|
@@ -0,0 +1,35 @@
|
|
+The hardware queue scheduling is apparently configured with fixed
|
|
+priorities, which creates a nasty fairness issue where traffic from one
|
|
+CPU can starve traffic from all other CPUs.
|
|
+
|
|
+Work around this issue by forcing all tx packets to go through one CPU,
|
|
+until this issue is fixed properly.
|
|
+
|
|
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
|
|
+---
|
|
+--- a/drivers/net/ethernet/marvell/mvneta.c
|
|
++++ b/drivers/net/ethernet/marvell/mvneta.c
|
|
+@@ -4272,6 +4272,15 @@ static int mvneta_ethtool_set_eee(struct
|
|
+ return phylink_ethtool_set_eee(pp->phylink, eee);
|
|
+ }
|
|
+
|
|
++static u16 mvneta_select_queue(struct net_device *dev, struct sk_buff *skb,
|
|
++ struct net_device *sb_dev,
|
|
++ select_queue_fallback_t fallback)
|
|
++{
|
|
++ /* XXX: hardware queue scheduling is broken,
|
|
++ * use only one queue until it is fixed */
|
|
++ return 0;
|
|
++}
|
|
++
|
|
+ static const struct net_device_ops mvneta_netdev_ops = {
|
|
+ .ndo_open = mvneta_open,
|
|
+ .ndo_stop = mvneta_stop,
|
|
+@@ -4282,6 +4291,7 @@ static const struct net_device_ops mvnet
|
|
+ .ndo_fix_features = mvneta_fix_features,
|
|
+ .ndo_get_stats64 = mvneta_get_stats64,
|
|
+ .ndo_do_ioctl = mvneta_ioctl,
|
|
++ .ndo_select_queue = mvneta_select_queue,
|
|
+ };
|
|
+
|
|
+ static const struct ethtool_ops mvneta_eth_tool_ops = {
|
|
diff --git a/target/linux/mvebu/patches-5.4/400-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch b/target/linux/mvebu/patches-5.4/400-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch
|
|
new file mode 100644
|
|
index 00000000000..29f36be460d
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/400-cpuidle-mvebu-indicate-failure-to-enter-deeper-sleep.patch
|
|
@@ -0,0 +1,40 @@
|
|
+From c28b2d367da8a471482e6a4aa8337ab6369a80c2 Mon Sep 17 00:00:00 2001
|
|
+From: Russell King <rmk+kernel@arm.linux.org.uk>
|
|
+Date: Sat, 3 Oct 2015 09:13:05 +0100
|
|
+Subject: cpuidle: mvebu: indicate failure to enter deeper sleep states
|
|
+
|
|
+The cpuidle ->enter method expects the return value to be the sleep
|
|
+state we entered. Returning negative numbers or other codes is not
|
|
+permissible since coupled CPU idle was merged.
|
|
+
|
|
+At least some of the mvebu_v7_cpu_suspend() implementations return the
|
|
+value from cpu_suspend(), which returns zero if the CPU vectors back
|
|
+into the kernel via cpu_resume() (the success case), or the non-zero
|
|
+return value of the suspend actor, or one (failure cases).
|
|
+
|
|
+We do not want to be returning the failure case value back to CPU idle
|
|
+as that indicates that we successfully entered one of the deeper idle
|
|
+states. Always return zero instead, indicating that we slept for the
|
|
+shortest amount of time.
|
|
+
|
|
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
|
+---
|
|
+ drivers/cpuidle/cpuidle-mvebu-v7.c | 6 +++++-
|
|
+ 1 file changed, 5 insertions(+), 1 deletion(-)
|
|
+
|
|
+--- a/drivers/cpuidle/cpuidle-mvebu-v7.c
|
|
++++ b/drivers/cpuidle/cpuidle-mvebu-v7.c
|
|
+@@ -39,8 +39,12 @@ static int mvebu_v7_enter_idle(struct cp
|
|
+ ret = mvebu_v7_cpu_suspend(deepidle);
|
|
+ cpu_pm_exit();
|
|
+
|
|
++ /*
|
|
++ * If we failed to enter the desired state, indicate that we
|
|
++ * slept lightly.
|
|
++ */
|
|
+ if (ret)
|
|
+- return ret;
|
|
++ return 0;
|
|
+
|
|
+ return index;
|
|
+ }
|
|
diff --git a/target/linux/mvebu/patches-5.4/401-pci-mvebu-time-out-reset-on-link-up.patch b/target/linux/mvebu/patches-5.4/401-pci-mvebu-time-out-reset-on-link-up.patch
|
|
new file mode 100644
|
|
index 00000000000..2bbb6471538
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/401-pci-mvebu-time-out-reset-on-link-up.patch
|
|
@@ -0,0 +1,60 @@
|
|
+From 287b9df160b6159f8d385424904f8bac501280c1 Mon Sep 17 00:00:00 2001
|
|
+From: Russell King <rmk+kernel@armlinux.org.uk>
|
|
+Date: Sat, 9 Jul 2016 10:58:16 +0100
|
|
+Subject: pci: mvebu: time out reset on link up
|
|
+
|
|
+If the port reports that the link is up while we are resetting, there's
|
|
+little point in waiting for the full duration.
|
|
+
|
|
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
|
+---
|
|
+ drivers/pci/controller/pci-mvebu.c | 20 ++++++++++++++------
|
|
+ 1 file changed, 14 insertions(+), 6 deletions(-)
|
|
+
|
|
+--- a/drivers/pci/controller/pci-mvebu.c
|
|
++++ b/drivers/pci/controller/pci-mvebu.c
|
|
+@@ -1112,6 +1112,7 @@ static int mvebu_pcie_powerup(struct mve
|
|
+
|
|
+ if (port->reset_gpio) {
|
|
+ u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000;
|
|
++ unsigned int i;
|
|
+
|
|
+ of_property_read_u32(port->dn, "reset-delay-us",
|
|
+ &reset_udelay);
|
|
+@@ -1119,7 +1120,13 @@ static int mvebu_pcie_powerup(struct mve
|
|
+ udelay(100);
|
|
+
|
|
+ gpiod_set_value_cansleep(port->reset_gpio, 0);
|
|
+- msleep(reset_udelay / 1000);
|
|
++ for (i = 0; i < reset_udelay; i += 1000) {
|
|
++ if (mvebu_pcie_link_up(port))
|
|
++ break;
|
|
++ msleep(1);
|
|
++ }
|
|
++
|
|
++ printk("%s: reset completed in %dus\n", port->name, i);
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+@@ -1283,15 +1290,16 @@ static int mvebu_pcie_probe(struct platf
|
|
+ if (!child)
|
|
+ continue;
|
|
+
|
|
+- ret = mvebu_pcie_powerup(port);
|
|
+- if (ret < 0)
|
|
+- continue;
|
|
+-
|
|
+ port->base = mvebu_pcie_map_registers(pdev, child, port);
|
|
+ if (IS_ERR(port->base)) {
|
|
+ dev_err(dev, "%s: cannot map registers\n", port->name);
|
|
+ port->base = NULL;
|
|
+- mvebu_pcie_powerdown(port);
|
|
++ continue;
|
|
++ }
|
|
++
|
|
++ ret = mvebu_pcie_powerup(port);
|
|
++ if (ret < 0) {
|
|
++ port->base = NULL;
|
|
+ continue;
|
|
+ }
|
|
+
|
|
diff --git a/target/linux/mvebu/patches-5.4/412-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch b/target/linux/mvebu/patches-5.4/412-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch
|
|
new file mode 100644
|
|
index 00000000000..dd2bef7f632
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/412-ARM-dts-armada388-clearfog-emmc-on-clearfog-base.patch
|
|
@@ -0,0 +1,87 @@
|
|
+From 8137da20701c776ad3481115305a5e8e410871ba Mon Sep 17 00:00:00 2001
|
|
+From: Russell King <rmk+kernel@armlinux.org.uk>
|
|
+Date: Tue, 29 Nov 2016 10:15:45 +0000
|
|
+Subject: ARM: dts: armada388-clearfog: emmc on clearfog base
|
|
+
|
|
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
|
+---
|
|
+ arch/arm/boot/dts/armada-388-clearfog-base.dts | 1 +
|
|
+ .../dts/armada-38x-solidrun-microsom-emmc.dtsi | 62 ++++++++++++++++++++++
|
|
+ 2 files changed, 63 insertions(+)
|
|
+ create mode 100644 arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi
|
|
+
|
|
+--- a/arch/arm/boot/dts/armada-388-clearfog-base.dts
|
|
++++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts
|
|
+@@ -7,6 +7,7 @@
|
|
+
|
|
+ /dts-v1/;
|
|
+ #include "armada-388-clearfog.dtsi"
|
|
++#include "armada-38x-solidrun-microsom-emmc.dtsi"
|
|
+
|
|
+ / {
|
|
+ model = "SolidRun Clearfog Base A1";
|
|
+--- /dev/null
|
|
++++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom-emmc.dtsi
|
|
+@@ -0,0 +1,62 @@
|
|
++/*
|
|
++ * Device Tree file for SolidRun Armada 38x Microsom add-on for eMMC
|
|
++ *
|
|
++ * Copyright (C) 2015 Russell King
|
|
++ *
|
|
++ * This board is in development; the contents of this file work with
|
|
++ * the A1 rev 2.0 of the board, which does not represent final
|
|
++ * production board. Things will change, don't expect this file to
|
|
++ * remain compatible info the future.
|
|
++ *
|
|
++ * This file is dual-licensed: you can use it either under the terms
|
|
++ * of the GPL or the X11 license, at your option. Note that this dual
|
|
++ * licensing only applies to this file, and not this project as a
|
|
++ * whole.
|
|
++ *
|
|
++ * a) This file is free software; you can redistribute it and/or
|
|
++ * modify it under the terms of the GNU General Public License
|
|
++ * version 2 as published by the Free Software Foundation.
|
|
++ *
|
|
++ * This file is distributed in the hope that it will be useful
|
|
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
++ * GNU General Public License for more details.
|
|
++ *
|
|
++ * Or, alternatively
|
|
++ *
|
|
++ * b) Permission is hereby granted, free of charge, to any person
|
|
++ * obtaining a copy of this software and associated documentation
|
|
++ * files (the "Software"), to deal in the Software without
|
|
++ * restriction, including without limitation the rights to use
|
|
++ * copy, modify, merge, publish, distribute, sublicense, and/or
|
|
++ * sell copies of the Software, and to permit persons to whom the
|
|
++ * Software is furnished to do so, subject to the following
|
|
++ * conditions:
|
|
++ *
|
|
++ * The above copyright notice and this permission notice shall be
|
|
++ * included in all copies or substantial portions of the Software.
|
|
++ *
|
|
++ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
|
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
|
++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
|
++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
|
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
|
++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
|
++ * OTHER DEALINGS IN THE SOFTWARE.
|
|
++ */
|
|
++/ {
|
|
++ soc {
|
|
++ internal-regs {
|
|
++ sdhci@d8000 {
|
|
++ bus-width = <4>;
|
|
++ no-1-8-v;
|
|
++ non-removable;
|
|
++ pinctrl-0 = <µsom_sdhci_pins>;
|
|
++ pinctrl-names = "default";
|
|
++ status = "okay";
|
|
++ wp-inverted;
|
|
++ };
|
|
++ };
|
|
++ };
|
|
++};
|
|
diff --git a/target/linux/mvebu/patches-5.4/415-ARM-dts-armada388-clearfog-document-MPP-usage.patch b/target/linux/mvebu/patches-5.4/415-ARM-dts-armada388-clearfog-document-MPP-usage.patch
|
|
new file mode 100644
|
|
index 00000000000..d64bd8084ea
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/415-ARM-dts-armada388-clearfog-document-MPP-usage.patch
|
|
@@ -0,0 +1,124 @@
|
|
+From 09a0122c74ec076e08512f1b00b7ccb8a450282f Mon Sep 17 00:00:00 2001
|
|
+From: Russell King <rmk+kernel@arm.linux.org.uk>
|
|
+Date: Tue, 29 Nov 2016 10:15:43 +0000
|
|
+Subject: ARM: dts: armada388-clearfog: document MPP usage
|
|
+
|
|
+Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
|
+---
|
|
+ arch/arm/boot/dts/armada-388-clearfog-base.dts | 51 ++++++++++++++++++++++++++
|
|
+ arch/arm/boot/dts/armada-388-clearfog.dts | 50 +++++++++++++++++++++++++
|
|
+ 2 files changed, 101 insertions(+)
|
|
+
|
|
+--- a/arch/arm/boot/dts/armada-388-clearfog-base.dts
|
|
++++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts
|
|
+@@ -67,3 +67,54 @@
|
|
+ marvell,function = "gpio";
|
|
+ };
|
|
+ };
|
|
++
|
|
++/*
|
|
++MPP
|
|
++18: pu gpio pca9655 int
|
|
++19: gpio phy reset
|
|
++20: pu gpio sd0 detect
|
|
++21: sd0:cmd
|
|
++22: pd gpio mikro int
|
|
++23:
|
|
++
|
|
++24: ua1:rxd mikro rx
|
|
++25: ua1:txd mikro tx
|
|
++26: pu i2c1:sck
|
|
++27: pu i2c1:sda
|
|
++28: sd0:clk
|
|
++29: pd gpio mikro rst
|
|
++30:
|
|
++31:
|
|
++
|
|
++32:
|
|
++33:
|
|
++34:
|
|
++35:
|
|
++36:
|
|
++37: sd0:d3
|
|
++38: sd0:d0
|
|
++39: sd0:d1
|
|
++
|
|
++40: sd0:d2
|
|
++41:
|
|
++42:
|
|
++43: spi1:cs2 mikro cs
|
|
++44: gpio rear button sw3
|
|
++45: ref:clk_out0 phy#0 clock
|
|
++46: ref:clk_out1 phy#1 clock
|
|
++47:
|
|
++
|
|
++48: gpio J18 spare gpio
|
|
++49: gpio U10 I2C_IRQ(GNSS)
|
|
++50: gpio board id?
|
|
++51:
|
|
++52:
|
|
++53:
|
|
++54: gpio mikro pwm
|
|
++55:
|
|
++
|
|
++56: pu spi1:mosi mikro mosi
|
|
++57: pd spi1:sck mikro sck
|
|
++58: spi1:miso mikro miso
|
|
++59:
|
|
++*/
|
|
+--- a/arch/arm/boot/dts/armada-388-clearfog.dts
|
|
++++ b/arch/arm/boot/dts/armada-388-clearfog.dts
|
|
+@@ -249,3 +249,53 @@
|
|
+ */
|
|
+ pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
|
|
+ };
|
|
++/*
|
|
+++#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011
|
|
++MPP18: gpio ? (pca9655 int?)
|
|
++MPP19: gpio ? (clkreq?)
|
|
++MPP20: gpio ? (sd0 detect)
|
|
++MPP21: sd0:cmd x sd0
|
|
++MPP22: gpio x mikro int
|
|
++MPP23: gpio x switch irq
|
|
+++#define A38x_CUSTOMER_BOARD_1_MPP24_31 0x22043333
|
|
++MPP24: ua1:rxd x mikro rx
|
|
++MPP25: ua1:txd x mikro tx
|
|
++MPP26: i2c1:sck x mikro sck
|
|
++MPP27: i2c1:sda x mikro sda
|
|
++MPP28: sd0:clk x sd0
|
|
++MPP29: gpio x mikro rst
|
|
++MPP30: ge1:txd2 ? (config)
|
|
++MPP31: ge1:txd3 ? (config)
|
|
+++#define A38x_CUSTOMER_BOARD_1_MPP32_39 0x44400002
|
|
++MPP32: ge1:txctl ? (unused)
|
|
++MPP33: gpio ? (pic_com0)
|
|
++MPP34: gpio x rear button (pic_com1)
|
|
++MPP35: gpio ? (pic_com2)
|
|
++MPP36: gpio ? (unused)
|
|
++MPP37: sd0:d3 x sd0
|
|
++MPP38: sd0:d0 x sd0
|
|
++MPP39: sd0:d1 x sd0
|
|
+++#define A38x_CUSTOMER_BOARD_1_MPP40_47 0x41144004
|
|
++MPP40: sd0:d2 x sd0
|
|
++MPP41: gpio x switch reset
|
|
++MPP42: gpio ? sw1-1
|
|
++MPP43: spi1:cs2 x mikro cs
|
|
++MPP44: sata3:prsnt ? (unused)
|
|
++MPP45: ref:clk_out0 ?
|
|
++MPP46: ref:clk_out1 x switch clk
|
|
++MPP47: 4 ? (unused)
|
|
+++#define A38x_CUSTOMER_BOARD_1_MPP48_55 0x40333333
|
|
++MPP48: tdm:pclk
|
|
++MPP49: tdm:fsync
|
|
++MPP50: tdm:drx
|
|
++MPP51: tdm:dtx
|
|
++MPP52: tdm:int
|
|
++MPP53: tdm:rst
|
|
++MPP54: gpio ? (pwm)
|
|
++MPP55: spi1:cs1 x slic
|
|
+++#define A38x_CUSTOMER_BOARD_1_MPP56_63 0x00004444
|
|
++MPP56: spi1:mosi x mikro mosi
|
|
++MPP57: spi1:sck x mikro sck
|
|
++MPP58: spi1:miso x mikro miso
|
|
++MPP59: spi1:cs0 x w25q32
|
|
++*/
|
|
diff --git a/target/linux/mvebu/patches-5.4/513-arm64-dts-marvell-armada37xx-Add-emmc-sdio-pinctrl-d.patch b/target/linux/mvebu/patches-5.4/513-arm64-dts-marvell-armada37xx-Add-emmc-sdio-pinctrl-d.patch
|
|
new file mode 100644
|
|
index 00000000000..880b0d92417
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/513-arm64-dts-marvell-armada37xx-Add-emmc-sdio-pinctrl-d.patch
|
|
@@ -0,0 +1,40 @@
|
|
+From eefe328439642101774f0f5c4ea0dc6ba1cfb687 Mon Sep 17 00:00:00 2001
|
|
+From: Ding Tao <miyatsu@qq.com>
|
|
+Date: Fri, 26 Oct 2018 11:50:27 +0000
|
|
+Subject: [PATCH] arm64: dts: marvell: armada37xx: Add emmc/sdio pinctrl
|
|
+ definition
|
|
+
|
|
+Add emmc/sdio pinctrl definition for marvell armada37xx SoCs.
|
|
+
|
|
+Signed-off-by: Ding Tao <miyatsu@qq.com>
|
|
+Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
|
|
+---
|
|
+ arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 10 ++++++++++
|
|
+ 1 file changed, 10 insertions(+)
|
|
+
|
|
+--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
|
|
++++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
|
|
+@@ -221,6 +221,11 @@
|
|
+ groups = "uart2";
|
|
+ function = "uart";
|
|
+ };
|
|
++
|
|
++ mmc_pins: mmc-pins {
|
|
++ groups = "emmc_nb";
|
|
++ function = "emmc";
|
|
++ };
|
|
+ };
|
|
+
|
|
+ nb_pm: syscon@14000 {
|
|
+@@ -253,6 +258,11 @@
|
|
+ function = "mii";
|
|
+ };
|
|
+
|
|
++ sdio_pins: sdio-pins {
|
|
++ groups = "sdio_sb";
|
|
++ function = "sdio";
|
|
++ };
|
|
++
|
|
+ };
|
|
+
|
|
+ eth0: ethernet@30000 {
|
|
diff --git a/target/linux/mvebu/patches-5.4/514-arm64-dts-marvell-armada-37xx-Enable-emmc-on-espress.patch b/target/linux/mvebu/patches-5.4/514-arm64-dts-marvell-armada-37xx-Enable-emmc-on-espress.patch
|
|
new file mode 100644
|
|
index 00000000000..77af3d1219d
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/514-arm64-dts-marvell-armada-37xx-Enable-emmc-on-espress.patch
|
|
@@ -0,0 +1,49 @@
|
|
+From 43ebc7c1b3ed8198b9acf3019eca16e722f7331c Mon Sep 17 00:00:00 2001
|
|
+From: Ding Tao <miyatsu@qq.com>
|
|
+Date: Fri, 26 Oct 2018 11:50:28 +0000
|
|
+Subject: [PATCH] arm64: dts: marvell: armada-37xx: Enable emmc on espressobin
|
|
+
|
|
+The ESPRESSObin board has a emmc interface available on U11: declare it
|
|
+and let the bootloader enable it if the emmc is present.
|
|
+
|
|
+[gregory.clement@bootlin.com: disable the emmc by default]
|
|
+Signed-off-by: Ding Tao <miyatsu@qq.com>
|
|
+Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
|
|
+---
|
|
+ .../dts/marvell/armada-3720-espressobin.dts | 22 +++++++++++++++++++
|
|
+ 1 file changed, 22 insertions(+)
|
|
+
|
|
+--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
|
++++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
|
+@@ -60,9 +60,31 @@
|
|
+ cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
|
|
+ marvell,pad-type = "sd";
|
|
+ vqmmc-supply = <&vcc_sd_reg1>;
|
|
++
|
|
++ pinctrl-names = "default";
|
|
++ pinctrl-0 = <&sdio_pins>;
|
|
+ status = "okay";
|
|
+ };
|
|
+
|
|
++/* U11 */
|
|
++&sdhci0 {
|
|
++ non-removable;
|
|
++ bus-width = <8>;
|
|
++ mmc-ddr-1_8v;
|
|
++ mmc-hs400-1_8v;
|
|
++ marvell,xenon-emmc;
|
|
++ marvell,xenon-tun-count = <9>;
|
|
++ marvell,pad-type = "fixed-1-8v";
|
|
++
|
|
++ pinctrl-names = "default";
|
|
++ pinctrl-0 = <&mmc_pins>;
|
|
++/*
|
|
++ * This eMMC is not populated on all boards, so disable it by
|
|
++ * default and let the bootloader enable it, if it is present
|
|
++ */
|
|
++ status = "disabled";
|
|
++};
|
|
++
|
|
+ &spi0 {
|
|
+ status = "okay";
|
|
+
|
|
diff --git a/target/linux/mvebu/patches-5.4/520-arm64-dts-marvell-armada37xx-Add-eth0-alias.patch b/target/linux/mvebu/patches-5.4/520-arm64-dts-marvell-armada37xx-Add-eth0-alias.patch
|
|
new file mode 100644
|
|
index 00000000000..e989f59d5cd
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/520-arm64-dts-marvell-armada37xx-Add-eth0-alias.patch
|
|
@@ -0,0 +1,20 @@
|
|
+From be893f672e340b56ca60f2f6c32fdd713a5852f5 Mon Sep 17 00:00:00 2001
|
|
+From: Kevin Mihelich <kevin@archlinuxarm.org>
|
|
+Date: Tue, 4 Jul 2017 19:25:28 -0600
|
|
+Subject: arm64: dts: marvell: armada37xx: Add eth0 alias
|
|
+
|
|
+Signed-off-by: Kevin Mihelich <kevin@archlinuxarm.org>
|
|
+---
|
|
+ arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 1 +
|
|
+ 1 file changed, 1 insertion(+)
|
|
+
|
|
+--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
|
|
++++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
|
|
+@@ -18,6 +18,7 @@
|
|
+ #size-cells = <2>;
|
|
+
|
|
+ aliases {
|
|
++ ethernet0 = ð0;
|
|
+ serial0 = &uart0;
|
|
+ serial1 = &uart1;
|
|
+ };
|
|
diff --git a/target/linux/mvebu/patches-5.4/521-arm64-dts-armada-3720-espressobin-correct-spi-node.patch b/target/linux/mvebu/patches-5.4/521-arm64-dts-armada-3720-espressobin-correct-spi-node.patch
|
|
new file mode 100644
|
|
index 00000000000..0f39b2a3c2c
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/521-arm64-dts-armada-3720-espressobin-correct-spi-node.patch
|
|
@@ -0,0 +1,58 @@
|
|
+From 3217cdfe8a3eae76fafbebbe407be5985a7fd4c2 Mon Sep 17 00:00:00 2001
|
|
+From: Tomasz Maciej Nowak <tmn505@gmail.com>
|
|
+Date: Mon, 31 Dec 2018 14:18:50 +0100
|
|
+Subject: [PATCH] arm64: dts: armada-3720-espressobin: correct spi node
|
|
+
|
|
+The manufacturer of this board, ships it with various SPI NOR chips and
|
|
+increments U-Boot bootloader version along the time. There is no way to
|
|
+tell which is placed on the board since no revision bump takes place.
|
|
+This creates two issues.
|
|
+
|
|
+The first, cosmetic. Since the SPI chip may differ, there's message on
|
|
+boot stating that kernel expected w25q32dw and found different one. To
|
|
+correct this, remove optional device-specific compatible string. Being
|
|
+here lets replace bogus "spi-flash" string with proper one.
|
|
+
|
|
+The second is linked to partitions layout, it changed after commit [1]
|
|
+in Marvells downstream U-Boot fork, shifting environment location to the
|
|
+end of boot device. Since the new boards can have U-Boot with this
|
|
+change it can lead to improper results writing or reading from these
|
|
+partitions. We can't tell if users will update bootloader to recent
|
|
+version, so let's drop current layout.
|
|
+
|
|
+1. https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/81e7251252aefe1a6b829ed05f3586320cb45372
|
|
+
|
|
+Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
|
|
+---
|
|
+ .../dts/marvell/armada-3720-espressobin.dts | 18 +-----------------
|
|
+ 1 file changed, 1 insertion(+), 17 deletions(-)
|
|
+
|
|
+--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
|
++++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
|
+@@ -90,25 +90,9 @@
|
|
+
|
|
+ flash@0 {
|
|
+ reg = <0>;
|
|
+- compatible = "winbond,w25q32dw", "jedec,spi-flash";
|
|
++ compatible = "jedec,spi-nor";
|
|
+ spi-max-frequency = <104000000>;
|
|
+ m25p,fast-read;
|
|
+-
|
|
+- partitions {
|
|
+- compatible = "fixed-partitions";
|
|
+- #address-cells = <1>;
|
|
+- #size-cells = <1>;
|
|
+-
|
|
+- partition@0 {
|
|
+- label = "uboot";
|
|
+- reg = <0 0x180000>;
|
|
+- };
|
|
+-
|
|
+- partition@180000 {
|
|
+- label = "ubootenv";
|
|
+- reg = <0x180000 0x10000>;
|
|
+- };
|
|
+- };
|
|
+ };
|
|
+ };
|
|
+
|
|
diff --git a/target/linux/mvebu/patches-5.4/522-arm64-dts-marvell-armada-3720-espressobin-add-ports-.patch b/target/linux/mvebu/patches-5.4/522-arm64-dts-marvell-armada-3720-espressobin-add-ports-.patch
|
|
new file mode 100644
|
|
index 00000000000..cea0d1db44f
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/522-arm64-dts-marvell-armada-3720-espressobin-add-ports-.patch
|
|
@@ -0,0 +1,26 @@
|
|
+From 6ea9a1ee9367fb35acff1c08a0dc4213ff4687a0 Mon Sep 17 00:00:00 2001
|
|
+From: Tomasz Maciej Nowak <tmn505@gmail.com>
|
|
+Date: Tue, 9 Apr 2019 15:53:42 +0200
|
|
+Subject: [PATCH] arm64: dts: marvell: armada-3720-espressobin: add ports
|
|
+ phandle
|
|
+
|
|
+Instead of referencing the whole mdio node, add ports phandle to adjust
|
|
+port labels in dts for different hardware iterations of ESPRESSObin
|
|
+boards.
|
|
+
|
|
+Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
|
|
+---
|
|
+ arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts | 2 +-
|
|
+ 1 file changed, 1 insertion(+), 1 deletion(-)
|
|
+
|
|
+--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
|
++++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
|
+@@ -132,7 +132,7 @@
|
|
+
|
|
+ dsa,member = <0 0>;
|
|
+
|
|
+- ports {
|
|
++ ports: ports {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
diff --git a/target/linux/mvebu/patches-5.4/523-Revert-PCI-aardvark-Convert-to-use-pci_host_probe.patch b/target/linux/mvebu/patches-5.4/523-Revert-PCI-aardvark-Convert-to-use-pci_host_probe.patch
|
|
new file mode 100644
|
|
index 00000000000..3fd561db3a6
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/523-Revert-PCI-aardvark-Convert-to-use-pci_host_probe.patch
|
|
@@ -0,0 +1,44 @@
|
|
+From 5e79c0c381eb085a2aa2da175eedea1950f07520 Mon Sep 17 00:00:00 2001
|
|
+From: Tomasz Maciej Nowak <tomek_n@o2.pl>
|
|
+Date: Tue, 30 Apr 2019 15:37:34 +0200
|
|
+Subject: [PATCH] Revert "PCI: aardvark: Convert to use pci_host_probe()"
|
|
+
|
|
+This reverts commit c8e144f8ab00e6c4a070a932ef9c57db09aa41cf.
|
|
+---
|
|
+ drivers/pci/controller/pci-aardvark.c | 12 +++++++++++-
|
|
+ 1 file changed, 11 insertions(+), 1 deletion(-)
|
|
+
|
|
+--- a/drivers/pci/controller/pci-aardvark.c
|
|
++++ b/drivers/pci/controller/pci-aardvark.c
|
|
+@@ -843,6 +843,7 @@ static int advk_pcie_probe(struct platfo
|
|
+ struct device *dev = &pdev->dev;
|
|
+ struct advk_pcie *pcie;
|
|
+ struct resource *res;
|
|
++ struct pci_bus *bus, *child;
|
|
+ struct pci_host_bridge *bridge;
|
|
+ int ret, irq;
|
|
+
|
|
+@@ -896,13 +897,22 @@ static int advk_pcie_probe(struct platfo
|
|
+ bridge->map_irq = of_irq_parse_and_map_pci;
|
|
+ bridge->swizzle_irq = pci_common_swizzle;
|
|
+
|
|
+- ret = pci_host_probe(bridge);
|
|
++ ret = pci_scan_root_bus_bridge(bridge);
|
|
+ if (ret < 0) {
|
|
+ advk_pcie_remove_msi_irq_domain(pcie);
|
|
+ advk_pcie_remove_irq_domain(pcie);
|
|
+ return ret;
|
|
+ }
|
|
+
|
|
++ bus = bridge->bus;
|
|
++
|
|
++ pci_bus_size_bridges(bus);
|
|
++ pci_bus_assign_resources(bus);
|
|
++
|
|
++ list_for_each_entry(child, &bus->children, node)
|
|
++ pcie_bus_configure_settings(child);
|
|
++
|
|
++ pci_bus_add_devices(bus);
|
|
+ return 0;
|
|
+ }
|
|
+
|
|
diff --git a/target/linux/mvebu/patches-5.4/524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch b/target/linux/mvebu/patches-5.4/524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch
|
|
new file mode 100644
|
|
index 00000000000..204d6e2aec4
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch
|
|
@@ -0,0 +1,138 @@
|
|
+From patchwork Thu Sep 28 12:58:34 2017
|
|
+Content-Type: text/plain; charset="utf-8"
|
|
+MIME-Version: 1.0
|
|
+Content-Transfer-Encoding: 7bit
|
|
+Subject: [v2,
|
|
+ 3/7] PCI: aardvark: set host and device to the same MAX payload size
|
|
+X-Patchwork-Submitter: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
|
+X-Patchwork-Id: 819587
|
|
+Message-Id: <20170928125838.11887-4-thomas.petazzoni@free-electrons.com>
|
|
+To: Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org
|
|
+Cc: Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
|
|
+ Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Gregory Clement
|
|
+ <gregory.clement@free-electrons.com>,
|
|
+ Nadav Haklai <nadavh@marvell.com>, Hanna Hawa <hannah@marvell.com>,
|
|
+ Yehuda Yitschak <yehuday@marvell.com>,
|
|
+ linux-arm-kernel@lists.infradead.org, Antoine Tenart
|
|
+ <antoine.tenart@free-electrons.com>, =?utf-8?q?Miqu=C3=A8l_Raynal?=
|
|
+ <miquel.raynal@free-electrons.com>, Victor Gu <xigu@marvell.com>,
|
|
+ Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
|
+Date: Thu, 28 Sep 2017 14:58:34 +0200
|
|
+From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
|
+List-Id: <linux-pci.vger.kernel.org>
|
|
+
|
|
+From: Victor Gu <xigu@marvell.com>
|
|
+
|
|
+Since the Aardvark does not implement a PCIe root bus, the Linux PCIe
|
|
+subsystem will not align the MAX payload size between the host and the
|
|
+device. This patch ensures that the host and device have the same MAX
|
|
+payload size, fixing a number of problems with various PCIe devices.
|
|
+
|
|
+This is part of fixing bug
|
|
+https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
|
|
+reported as the user to be important to get a Intel 7260 mini-PCIe
|
|
+WiFi card working.
|
|
+
|
|
+Fixes: Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
|
|
+Signed-off-by: Victor Gu <xigu@marvell.com>
|
|
+Reviewed-by: Evan Wang <xswang@marvell.com>
|
|
+Reviewed-by: Nadav Haklai <nadavh@marvell.com>
|
|
+[Thomas: tweak commit log.]
|
|
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
|
+---
|
|
+ drivers/pci/controller/pci-aardvark.c | 60 ++++++++++++++++++++++++++++++++++++++++-
|
|
+ 1 file changed, 59 insertions(+), 1 deletion(-)
|
|
+
|
|
+--- a/drivers/pci/controller/pci-aardvark.c
|
|
++++ b/drivers/pci/controller/pci-aardvark.c
|
|
+@@ -29,9 +29,11 @@
|
|
+ #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
|
|
+ #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
|
|
+ #define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
|
|
++#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ 0x2
|
|
+ #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11)
|
|
+ #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT 12
|
|
+ #define PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ 0x2
|
|
++#define PCIE_CORE_MPS_UNIT_BYTE 128
|
|
+ #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
|
|
+ #define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
|
|
+ #define PCIE_CORE_LINK_TRAINING BIT(5)
|
|
+@@ -253,7 +255,8 @@ static void advk_pcie_setup_hw(struct ad
|
|
+
|
|
+ /* Set PCIe Device Control and Status 1 PF0 register */
|
|
+ reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
|
|
+- (7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
|
|
++ (PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ <<
|
|
++ PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |
|
|
+ PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
|
|
+ (PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<
|
|
+ PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);
|
|
+@@ -838,6 +841,58 @@ out_release_res:
|
|
+ return err;
|
|
+ }
|
|
+
|
|
++static int advk_pcie_find_smpss(struct pci_dev *dev, void *data)
|
|
++{
|
|
++ u8 *smpss = data;
|
|
++
|
|
++ if (!dev)
|
|
++ return 0;
|
|
++
|
|
++ if (!pci_is_pcie(dev))
|
|
++ return 0;
|
|
++
|
|
++ if (*smpss > dev->pcie_mpss)
|
|
++ *smpss = dev->pcie_mpss;
|
|
++
|
|
++ return 0;
|
|
++}
|
|
++
|
|
++static int advk_pcie_bus_configure_mps(struct pci_dev *dev, void *data)
|
|
++{
|
|
++ int mps;
|
|
++
|
|
++ if (!dev)
|
|
++ return 0;
|
|
++
|
|
++ if (!pci_is_pcie(dev))
|
|
++ return 0;
|
|
++
|
|
++ mps = PCIE_CORE_MPS_UNIT_BYTE << *(u8 *)data;
|
|
++ pcie_set_mps(dev, mps);
|
|
++
|
|
++ return 0;
|
|
++}
|
|
++
|
|
++static void advk_pcie_configure_mps(struct pci_bus *bus, struct advk_pcie *pcie)
|
|
++{
|
|
++ u8 smpss = PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ;
|
|
++ u32 reg;
|
|
++
|
|
++ /* Find the minimal supported MAX payload size */
|
|
++ advk_pcie_find_smpss(bus->self, &smpss);
|
|
++ pci_walk_bus(bus, advk_pcie_find_smpss, &smpss);
|
|
++
|
|
++ /* Configure RC MAX payload size */
|
|
++ reg = advk_readl(pcie, PCIE_CORE_DEV_CTRL_STATS_REG);
|
|
++ reg &= ~PCI_EXP_DEVCTL_PAYLOAD;
|
|
++ reg |= smpss << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT;
|
|
++ advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
|
|
++
|
|
++ /* Configure device MAX payload size */
|
|
++ advk_pcie_bus_configure_mps(bus->self, &smpss);
|
|
++ pci_walk_bus(bus, advk_pcie_bus_configure_mps, &smpss);
|
|
++}
|
|
++
|
|
+ static int advk_pcie_probe(struct platform_device *pdev)
|
|
+ {
|
|
+ struct device *dev = &pdev->dev;
|
|
+@@ -912,6 +967,9 @@ static int advk_pcie_probe(struct platfo
|
|
+ list_for_each_entry(child, &bus->children, node)
|
|
+ pcie_bus_configure_settings(child);
|
|
+
|
|
++ /* Configure the MAX pay load size */
|
|
++ advk_pcie_configure_mps(bus, pcie);
|
|
++
|
|
+ pci_bus_add_devices(bus);
|
|
+ return 0;
|
|
+ }
|
|
diff --git a/target/linux/mvebu/patches-5.4/526-PCI-aardvark-disable-LOS-state-by-default.patch b/target/linux/mvebu/patches-5.4/526-PCI-aardvark-disable-LOS-state-by-default.patch
|
|
new file mode 100644
|
|
index 00000000000..b6fcec81f8f
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/526-PCI-aardvark-disable-LOS-state-by-default.patch
|
|
@@ -0,0 +1,55 @@
|
|
+From patchwork Thu Sep 28 12:58:36 2017
|
|
+Content-Type: text/plain; charset="utf-8"
|
|
+MIME-Version: 1.0
|
|
+Content-Transfer-Encoding: 7bit
|
|
+Subject: [v2,5/7] PCI: aardvark: disable LOS state by default
|
|
+X-Patchwork-Submitter: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
|
+X-Patchwork-Id: 819590
|
|
+Message-Id: <20170928125838.11887-6-thomas.petazzoni@free-electrons.com>
|
|
+To: Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org
|
|
+Cc: Jason Cooper <jason@lakedaemon.net>, Andrew Lunn <andrew@lunn.ch>,
|
|
+ Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>, Gregory Clement
|
|
+ <gregory.clement@free-electrons.com>,
|
|
+ Nadav Haklai <nadavh@marvell.com>, Hanna Hawa <hannah@marvell.com>,
|
|
+ Yehuda Yitschak <yehuday@marvell.com>,
|
|
+ linux-arm-kernel@lists.infradead.org, Antoine Tenart
|
|
+ <antoine.tenart@free-electrons.com>, =?utf-8?q?Miqu=C3=A8l_Raynal?=
|
|
+ <miquel.raynal@free-electrons.com>, Victor Gu <xigu@marvell.com>,
|
|
+ Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
|
+Date: Thu, 28 Sep 2017 14:58:36 +0200
|
|
+From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
|
+List-Id: <linux-pci.vger.kernel.org>
|
|
+
|
|
+From: Victor Gu <xigu@marvell.com>
|
|
+
|
|
+Some PCIe devices do not support LOS, and will cause timeouts if the
|
|
+root complex forces the LOS state. This patch disables the LOS state
|
|
+by default.
|
|
+
|
|
+This is part of fixing bug
|
|
+https://bugzilla.kernel.org/show_bug.cgi?id=196339, this commit was
|
|
+reported as the user to be important to get a Intel 7260 mini-PCIe
|
|
+WiFi card working.
|
|
+
|
|
+Fixes: 8c39d710363c1 ("PCI: aardvark: Add Aardvark PCI host controller driver")
|
|
+Signed-off-by: Victor Gu <xigu@marvell.com>
|
|
+Reviewed-by: Evan Wang <xswang@marvell.com>
|
|
+Reviewed-by: Nadav Haklai <nadavh@marvell.com>
|
|
+[Thomas: tweak commit log.]
|
|
+Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
|
+---
|
|
+ drivers/pci/controller/pci-aardvark.c | 3 +--
|
|
+ 1 file changed, 1 insertion(+), 2 deletions(-)
|
|
+
|
|
+--- a/drivers/pci/controller/pci-aardvark.c
|
|
++++ b/drivers/pci/controller/pci-aardvark.c
|
|
+@@ -324,8 +324,7 @@ static void advk_pcie_setup_hw(struct ad
|
|
+
|
|
+ advk_pcie_wait_for_link(pcie);
|
|
+
|
|
+- reg = PCIE_CORE_LINK_L0S_ENTRY |
|
|
+- (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
|
|
++ reg = (1 << PCIE_CORE_LINK_WIDTH_SHIFT);
|
|
+ advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
|
|
+
|
|
+ reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
|
|
diff --git a/target/linux/mvebu/patches-5.4/527-PCI-aardvark-allow-to-specify-link-capability.patch b/target/linux/mvebu/patches-5.4/527-PCI-aardvark-allow-to-specify-link-capability.patch
|
|
new file mode 100644
|
|
index 00000000000..0ac34761473
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/527-PCI-aardvark-allow-to-specify-link-capability.patch
|
|
@@ -0,0 +1,43 @@
|
|
+From f70b629e488cc3f2a325ac35476f4f7ae502c5d0 Mon Sep 17 00:00:00 2001
|
|
+From: Tomasz Maciej Nowak <tmn505@gmail.com>
|
|
+Date: Thu, 14 Jun 2018 14:24:40 +0200
|
|
+Subject: [PATCH 1/2] PCI: aardvark: allow to specify link capability
|
|
+
|
|
+Use DT of_pci_get_max_link_speed() facility to allow specifying link
|
|
+capability. If none or unspecified value is given it falls back to gen2,
|
|
+which is default for Armada 3700 SoC.
|
|
+
|
|
+Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
|
|
+---
|
|
+ drivers/pci/controller/pci-aardvark.c | 11 +++++++++--
|
|
+ 1 file changed, 9 insertions(+), 2 deletions(-)
|
|
+
|
|
+--- a/drivers/pci/controller/pci-aardvark.c
|
|
++++ b/drivers/pci/controller/pci-aardvark.c
|
|
+@@ -233,6 +233,8 @@ static int advk_pcie_wait_for_link(struc
|
|
+
|
|
+ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
|
|
+ {
|
|
++ struct device *dev = &pcie->pdev->dev;
|
|
++ struct device_node *node = dev->of_node;
|
|
+ u32 reg;
|
|
+
|
|
+ /* Set to Direct mode */
|
|
+@@ -267,10 +269,15 @@ static void advk_pcie_setup_hw(struct ad
|
|
+ PCIE_CORE_CTRL2_TD_ENABLE;
|
|
+ advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
|
|
+
|
|
+- /* Set GEN2 */
|
|
++ /* Set GEN */
|
|
+ reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
|
|
+ reg &= ~PCIE_GEN_SEL_MSK;
|
|
+- reg |= SPEED_GEN_2;
|
|
++ if (of_pci_get_max_link_speed(node) == 1)
|
|
++ reg |= SPEED_GEN_1;
|
|
++ else if (of_pci_get_max_link_speed(node) == 3)
|
|
++ reg |= SPEED_GEN_3;
|
|
++ else
|
|
++ reg |= SPEED_GEN_2;
|
|
+ advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
|
|
+
|
|
+ /* Set lane X1 */
|
|
diff --git a/target/linux/mvebu/patches-5.4/528-arm64-dts-armada-3720-espressobin-set-max-link-to-ge.patch b/target/linux/mvebu/patches-5.4/528-arm64-dts-armada-3720-espressobin-set-max-link-to-ge.patch
|
|
new file mode 100644
|
|
index 00000000000..88080d64caa
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/528-arm64-dts-armada-3720-espressobin-set-max-link-to-ge.patch
|
|
@@ -0,0 +1,73 @@
|
|
+From 33f8fdcedb01680427328d710594facef7a0092c Mon Sep 17 00:00:00 2001
|
|
+From: Tomasz Maciej Nowak <tmn505@gmail.com>
|
|
+Date: Thu, 14 Jun 2018 14:40:26 +0200
|
|
+Subject: [PATCH 2/2] arm64: dts: armada-3720-espressobin: set max link to gen1
|
|
+
|
|
+Since the beginning there's been an issue with initializing the Atheros
|
|
+based MiniPCIe wireless cards. Here's an example of kerenel log:
|
|
+
|
|
+ OF: PCI: host bridge /soc/pcie@d0070000 ranges:
|
|
+ OF: PCI: MEM 0xe8000000..0xe8ffffff -> 0xe8000000
|
|
+ OF: PCI: IO 0xe9000000..0xe900ffff -> 0xe9000000
|
|
+ advk-pcie d0070000.pcie: link up
|
|
+ advk-pcie d0070000.pcie: PCI host bridge to bus 0000:00
|
|
+ pci_bus 0000:00: root bus resource [bus 00-ff]
|
|
+ pci_bus 0000:00: root bus resource [mem0xe8000000-0xe8ffffff]
|
|
+ pci_bus 0000:00: root bus resource [io 0x0000-0xffff](bus address [0xe9000000-0xe900ffff])
|
|
+ pci 0000:00:00.0: BAR 0: assigned [mem0xe8000000-0xe801ffff 64bit]
|
|
+ pci 0000:00:00.0: BAR 6: assigned [mem0xe8020000-0xe802ffff pref]
|
|
+ [...]
|
|
+ advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x3c
|
|
+ advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x44
|
|
+ advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x4
|
|
+ ath9k 0000:00:00.0: enabling device (0000 -> 0002)
|
|
+ advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x3c
|
|
+ advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0xc
|
|
+ advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x4
|
|
+ advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x40
|
|
+ ath9k 0000:00:00.0: request_irq failed
|
|
+ advk-pcie d0070000.pcie: Posted PIO Response Status: CA,0xe00 @ 0x4
|
|
+ ath9k: probe of 0000:00:00.0 failed with error -22
|
|
+
|
|
+The same happens for ath5k cards, while ath10k card didn't appear at
|
|
+all (not detected):
|
|
+
|
|
+ OF: PCI: host bridge /soc/pcie@d0070000 ranges:
|
|
+ OF: PCI: MEM 0xe8000000..0xe8ffffff -> 0xe8000000
|
|
+ OF: PCI: IO 0xe9000000..0xe900ffff -> 0xe9000000
|
|
+ advk-pcie d0070000.pcie: link never came up
|
|
+ advk-pcie d0070000.pcie: PCI host bridge to bus 0000:00
|
|
+ pci_bus 0000:00: root bus resource [bus 00-ff]
|
|
+ pci_bus 0000:00: root bus resource [mem0xe8000000-0xe8ffffff]
|
|
+ pci_bus 0000:00: root bus resource [io 0x0000-0xffff](bus address [0xe9000000-0xe900ffff])
|
|
+ advk-pcie d0070000.pcie: config read/write timed out
|
|
+
|
|
+Following the issue on esppressobin.net forum [1] the workaround seems
|
|
+to be limiting the speed of PCIe bridge to 1st generation. This fixed
|
|
+the initialisation of all tested Atheros wireless cards.
|
|
+The patch in the forum thread swaped registers which would limit speed
|
|
+for all Armada 3700 based boards. The approach in this patch, in
|
|
+conjunction with "PCI: aardvark: allow to specify link capability" patch
|
|
+is less invasive, it only touches the affected board.
|
|
+
|
|
+For the record, the iwlwifi and mt76 cards were not affected by this
|
|
+issue.
|
|
+
|
|
+1. http://espressobin.net/forums/topic/which-pcie-wlan-cards-are-supported
|
|
+
|
|
+Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
|
|
+---
|
|
+ arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts | 2 ++
|
|
+ 1 file changed, 2 insertions(+)
|
|
+
|
|
+--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
|
++++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
|
+@@ -46,6 +46,8 @@
|
|
+ /* J9 */
|
|
+ &pcie0 {
|
|
+ status = "okay";
|
|
++
|
|
++ max-link-speed = <1>;
|
|
+ };
|
|
+
|
|
+ /* J6 */
|
|
diff --git a/target/linux/mvebu/patches-5.4/531-net-mvneta-Add-support-for-2500Mbps-SGMII.patch b/target/linux/mvebu/patches-5.4/531-net-mvneta-Add-support-for-2500Mbps-SGMII.patch
|
|
new file mode 100644
|
|
index 00000000000..a5553a3e96c
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/531-net-mvneta-Add-support-for-2500Mbps-SGMII.patch
|
|
@@ -0,0 +1,104 @@
|
|
+From da58a931f248f423f917c3a0b3c94303aa30a738 Mon Sep 17 00:00:00 2001
|
|
+From: Maxime Chevallier <maxime.chevallier@bootlin.com>
|
|
+Date: Tue, 25 Sep 2018 15:59:39 +0200
|
|
+Subject: [PATCH] net: mvneta: Add support for 2500Mbps SGMII
|
|
+
|
|
+The mvneta controller can handle speeds up to 2500Mbps on the SGMII
|
|
+interface. This relies on serdes configuration, the lane must be
|
|
+configured at 3.125Gbps and we can't use in-band autoneg at that speed.
|
|
+
|
|
+The main issue when supporting that speed on this particular controller
|
|
+is that the link partner can send ethernet frames with a shortened
|
|
+preamble, which if not explicitly enabled in the controller will cause
|
|
+unexpected behaviours.
|
|
+
|
|
+This was tested on Armada 385, with the comphy configuration done in
|
|
+bootloader.
|
|
+
|
|
+Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
|
|
+Signed-off-by: David S. Miller <davem@davemloft.net>
|
|
+---
|
|
+ drivers/net/ethernet/marvell/mvneta.c | 27 +++++++++++++++++++++++----
|
|
+ 1 file changed, 23 insertions(+), 4 deletions(-)
|
|
+
|
|
+--- a/drivers/net/ethernet/marvell/mvneta.c
|
|
++++ b/drivers/net/ethernet/marvell/mvneta.c
|
|
+@@ -221,6 +221,8 @@
|
|
+ #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11)
|
|
+ #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
|
|
+ #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
|
|
++#define MVNETA_GMAC_CTRL_4 0x2c90
|
|
++#define MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE BIT(1)
|
|
+ #define MVNETA_MIB_COUNTERS_BASE 0x3000
|
|
+ #define MVNETA_MIB_LATE_COLLISION 0x7c
|
|
+ #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
|
|
+@@ -3359,6 +3361,7 @@ static void mvneta_validate(struct net_d
|
|
+ if (state->interface != PHY_INTERFACE_MODE_NA &&
|
|
+ state->interface != PHY_INTERFACE_MODE_QSGMII &&
|
|
+ state->interface != PHY_INTERFACE_MODE_SGMII &&
|
|
++ state->interface != PHY_INTERFACE_MODE_2500BASEX &&
|
|
+ !phy_interface_mode_is_8023z(state->interface) &&
|
|
+ !phy_interface_mode_is_rgmii(state->interface)) {
|
|
+ bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
|
|
+@@ -3371,9 +3374,15 @@ static void mvneta_validate(struct net_d
|
|
+
|
|
+ /* Asymmetric pause is unsupported */
|
|
+ phylink_set(mask, Pause);
|
|
+- /* Half-duplex at speeds higher than 100Mbit is unsupported */
|
|
+- phylink_set(mask, 1000baseT_Full);
|
|
+- phylink_set(mask, 1000baseX_Full);
|
|
++
|
|
++ /* We cannot use 1Gbps when using the 2.5G interface. */
|
|
++ if (state->interface == PHY_INTERFACE_MODE_2500BASEX) {
|
|
++ phylink_set(mask, 2500baseT_Full);
|
|
++ phylink_set(mask, 2500baseX_Full);
|
|
++ } else {
|
|
++ phylink_set(mask, 1000baseT_Full);
|
|
++ phylink_set(mask, 1000baseX_Full);
|
|
++ }
|
|
+
|
|
+ if (!phy_interface_mode_is_8023z(state->interface)) {
|
|
+ /* 10M and 100M are only supported in non-802.3z mode */
|
|
+@@ -3434,12 +3443,14 @@ static void mvneta_mac_config(struct net
|
|
+ struct mvneta_port *pp = netdev_priv(ndev);
|
|
+ u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
|
|
+ u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
|
|
++ u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4);
|
|
+ u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
|
|
+ u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
|
|
+
|
|
+ new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X;
|
|
+ new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE |
|
|
+ MVNETA_GMAC2_PORT_RESET);
|
|
++ new_ctrl4 = gmac_ctrl4 & ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE);
|
|
+ new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
|
|
+ new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE |
|
|
+ MVNETA_GMAC_INBAND_RESTART_AN |
|
|
+@@ -3472,7 +3483,7 @@ static void mvneta_mac_config(struct net
|
|
+ if (state->duplex)
|
|
+ new_an |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
|
|
+
|
|
+- if (state->speed == SPEED_1000)
|
|
++ if (state->speed == SPEED_1000 || state->speed == SPEED_2500)
|
|
+ new_an |= MVNETA_GMAC_CONFIG_GMII_SPEED;
|
|
+ else if (state->speed == SPEED_100)
|
|
+ new_an |= MVNETA_GMAC_CONFIG_MII_SPEED;
|
|
+@@ -3511,10 +3522,18 @@ static void mvneta_mac_config(struct net
|
|
+ MVNETA_GMAC_FORCE_LINK_DOWN);
|
|
+ }
|
|
+
|
|
++ /* When at 2.5G, the link partner can send frames with shortened
|
|
++ * preambles.
|
|
++ */
|
|
++ if (state->speed == SPEED_2500)
|
|
++ new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE;
|
|
++
|
|
+ if (new_ctrl0 != gmac_ctrl0)
|
|
+ mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0);
|
|
+ if (new_ctrl2 != gmac_ctrl2)
|
|
+ mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2);
|
|
++ if (new_ctrl4 != gmac_ctrl4)
|
|
++ mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4);
|
|
+ if (new_clk != gmac_clk)
|
|
+ mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk);
|
|
+ if (new_an != gmac_an)
|
|
diff --git a/target/linux/mvebu/patches-5.4/532-net-mvneta-correct-typo.patch b/target/linux/mvebu/patches-5.4/532-net-mvneta-correct-typo.patch
|
|
new file mode 100644
|
|
index 00000000000..b6e16c54a45
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/532-net-mvneta-correct-typo.patch
|
|
@@ -0,0 +1,33 @@
|
|
+From fbd1d5245372e48b494120a30fe0b34b304576c4 Mon Sep 17 00:00:00 2001
|
|
+From: Alexandre Belloni <alexandre.belloni@bootlin.com>
|
|
+Date: Fri, 9 Nov 2018 17:37:20 +0100
|
|
+Subject: [PATCH] net: mvneta: correct typo
|
|
+
|
|
+The reserved variable should be named reserved1.
|
|
+
|
|
+Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
|
|
+Signed-off-by: David S. Miller <davem@davemloft.net>
|
|
+---
|
|
+ drivers/net/ethernet/marvell/mvneta.c | 4 ++--
|
|
+ 1 file changed, 2 insertions(+), 2 deletions(-)
|
|
+
|
|
+--- a/drivers/net/ethernet/marvell/mvneta.c
|
|
++++ b/drivers/net/ethernet/marvell/mvneta.c
|
|
+@@ -495,7 +495,7 @@ struct mvneta_port {
|
|
+ #if defined(__LITTLE_ENDIAN)
|
|
+ struct mvneta_tx_desc {
|
|
+ u32 command; /* Options used by HW for packet transmitting.*/
|
|
+- u16 reserverd1; /* csum_l4 (for future use) */
|
|
++ u16 reserved1; /* csum_l4 (for future use) */
|
|
+ u16 data_size; /* Data size of transmitted packet in bytes */
|
|
+ u32 buf_phys_addr; /* Physical addr of transmitted buffer */
|
|
+ u32 reserved2; /* hw_cmd - (for future use, PMT) */
|
|
+@@ -520,7 +520,7 @@ struct mvneta_rx_desc {
|
|
+ #else
|
|
+ struct mvneta_tx_desc {
|
|
+ u16 data_size; /* Data size of transmitted packet in bytes */
|
|
+- u16 reserverd1; /* csum_l4 (for future use) */
|
|
++ u16 reserved1; /* csum_l4 (for future use) */
|
|
+ u32 command; /* Options used by HW for packet transmitting.*/
|
|
+ u32 reserved2; /* hw_cmd - (for future use, PMT) */
|
|
+ u32 buf_phys_addr; /* Physical addr of transmitted buffer */
|
|
diff --git a/target/linux/mvebu/patches-5.4/533-net-mvneta-Dont-advertise-2.5G-modes.patch b/target/linux/mvebu/patches-5.4/533-net-mvneta-Dont-advertise-2.5G-modes.patch
|
|
new file mode 100644
|
|
index 00000000000..01b101283cd
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/533-net-mvneta-Dont-advertise-2.5G-modes.patch
|
|
@@ -0,0 +1,55 @@
|
|
+From 83e65df6dfece9eb588735459428f221eb930c0c Mon Sep 17 00:00:00 2001
|
|
+From: Maxime Chevallier <maxime.chevallier@bootlin.com>
|
|
+Date: Fri, 9 Nov 2018 09:17:33 +0100
|
|
+Subject: [PATCH] net: mvneta: Don't advertise 2.5G modes
|
|
+
|
|
+Using 2.5G speed relies on the SerDes lanes being configured
|
|
+accordingly. The lanes have to be reconfigured to switch between
|
|
+1G and 2.5G, and for now only the bootloader does this configuration.
|
|
+
|
|
+In the case we add a Comphy driver to handle switching the lanes
|
|
+dynamically, it's better for now to stick with supporting only 1G and
|
|
+add advertisement for 2.5G once we really are capable of handling both
|
|
+speeds without problem.
|
|
+
|
|
+Since the interface mode is initialy taken from the DT, we want to make
|
|
+sure that adding comphy support won't break boards that don't update
|
|
+their dtb.
|
|
+
|
|
+Fixes: da58a931f248 ("net: mvneta: Add support for 2500Mbps SGMII")
|
|
+Reported-by: Andrew Lunn <andrew@lunn.ch>
|
|
+Reported-by: Russell King <linux@armlinux.org.uk>
|
|
+Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
|
|
+Signed-off-by: David S. Miller <davem@davemloft.net>
|
|
+---
|
|
+ drivers/net/ethernet/marvell/mvneta.c | 12 +++---------
|
|
+ 1 file changed, 3 insertions(+), 9 deletions(-)
|
|
+
|
|
+--- a/drivers/net/ethernet/marvell/mvneta.c
|
|
++++ b/drivers/net/ethernet/marvell/mvneta.c
|
|
+@@ -3361,7 +3361,6 @@ static void mvneta_validate(struct net_d
|
|
+ if (state->interface != PHY_INTERFACE_MODE_NA &&
|
|
+ state->interface != PHY_INTERFACE_MODE_QSGMII &&
|
|
+ state->interface != PHY_INTERFACE_MODE_SGMII &&
|
|
+- state->interface != PHY_INTERFACE_MODE_2500BASEX &&
|
|
+ !phy_interface_mode_is_8023z(state->interface) &&
|
|
+ !phy_interface_mode_is_rgmii(state->interface)) {
|
|
+ bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
|
|
+@@ -3375,14 +3374,9 @@ static void mvneta_validate(struct net_d
|
|
+ /* Asymmetric pause is unsupported */
|
|
+ phylink_set(mask, Pause);
|
|
+
|
|
+- /* We cannot use 1Gbps when using the 2.5G interface. */
|
|
+- if (state->interface == PHY_INTERFACE_MODE_2500BASEX) {
|
|
+- phylink_set(mask, 2500baseT_Full);
|
|
+- phylink_set(mask, 2500baseX_Full);
|
|
+- } else {
|
|
+- phylink_set(mask, 1000baseT_Full);
|
|
+- phylink_set(mask, 1000baseX_Full);
|
|
+- }
|
|
++ /* Half-duplex at speeds higher than 100Mbit is unsupported */
|
|
++ phylink_set(mask, 1000baseT_Full);
|
|
++ phylink_set(mask, 1000baseX_Full);
|
|
+
|
|
+ if (!phy_interface_mode_is_8023z(state->interface)) {
|
|
+ /* 10M and 100M are only supported in non-802.3z mode */
|
|
diff --git a/target/linux/mvebu/patches-5.4/534-net-mvneta-remove-redundant-check-for.patch b/target/linux/mvebu/patches-5.4/534-net-mvneta-remove-redundant-check-for.patch
|
|
new file mode 100644
|
|
index 00000000000..fd774e08398
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/534-net-mvneta-remove-redundant-check-for.patch
|
|
@@ -0,0 +1,30 @@
|
|
+From e4a3e9ff5ba9f6b67595ec2768ed4be2054c2aa5 Mon Sep 17 00:00:00 2001
|
|
+From: YueHaibing <yuehaibing@huawei.com>
|
|
+Date: Thu, 22 Nov 2018 14:42:00 +0800
|
|
+Subject: [PATCH] net: mvneta: remove redundant check for
|
|
+ eee->tx_lpi_timer < 0
|
|
+
|
|
+fixes the smatch warning:
|
|
+
|
|
+drivers/net/ethernet/marvell/mvneta.c:4252 mvneta_ethtool_set_eee() warn:
|
|
+ unsigned 'eee->tx_lpi_timer' is never less than zero.
|
|
+
|
|
+Signed-off-by: YueHaibing <yuehaibing@huawei.com>
|
|
+Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
|
|
+Signed-off-by: David S. Miller <davem@davemloft.net>
|
|
+---
|
|
+ drivers/net/ethernet/marvell/mvneta.c | 3 +--
|
|
+ 1 file changed, 1 insertion(+), 2 deletions(-)
|
|
+
|
|
+--- a/drivers/net/ethernet/marvell/mvneta.c
|
|
++++ b/drivers/net/ethernet/marvell/mvneta.c
|
|
+@@ -4268,8 +4268,7 @@ static int mvneta_ethtool_set_eee(struct
|
|
+
|
|
+ /* The Armada 37x documents do not give limits for this other than
|
|
+ * it being an 8-bit register. */
|
|
+- if (eee->tx_lpi_enabled &&
|
|
+- (eee->tx_lpi_timer < 0 || eee->tx_lpi_timer > 255))
|
|
++ if (eee->tx_lpi_enabled && eee->tx_lpi_timer > 255)
|
|
+ return -EINVAL;
|
|
+
|
|
+ lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
|
|
diff --git a/target/linux/mvebu/patches-5.4/535-net-marvell-neta-add-comphy-support.patch b/target/linux/mvebu/patches-5.4/535-net-marvell-neta-add-comphy-support.patch
|
|
new file mode 100644
|
|
index 00000000000..272beb6950f
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/535-net-marvell-neta-add-comphy-support.patch
|
|
@@ -0,0 +1,159 @@
|
|
+From a10c1c8191e04c21769656c2ca8e1c69a6218954 Mon Sep 17 00:00:00 2001
|
|
+From: Russell King <rmk+kernel@armlinux.org.uk>
|
|
+Date: Thu, 7 Feb 2019 16:19:26 +0000
|
|
+Subject: [PATCH] net: marvell: neta: add comphy support
|
|
+
|
|
+Add support for the common phy binding, so that we can reconfigure the
|
|
+comphy according to the desired ethernet speed. This will allow us to
|
|
+support 1000base-X and 2500base-X SFPs dynamically on SolidRun Clearfog.
|
|
+
|
|
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
|
+Signed-off-by: David S. Miller <davem@davemloft.net>
|
|
+---
|
|
+ drivers/net/ethernet/marvell/mvneta.c | 45 +++++++++++++++++++++++++++++++----
|
|
+ 1 file changed, 41 insertions(+), 4 deletions(-)
|
|
+
|
|
+--- a/drivers/net/ethernet/marvell/mvneta.c
|
|
++++ b/drivers/net/ethernet/marvell/mvneta.c
|
|
+@@ -27,6 +27,7 @@
|
|
+ #include <linux/of_irq.h>
|
|
+ #include <linux/of_mdio.h>
|
|
+ #include <linux/of_net.h>
|
|
++#include <linux/phy/phy.h>
|
|
+ #include <linux/phy.h>
|
|
+ #include <linux/phylink.h>
|
|
+ #include <linux/platform_device.h>
|
|
+@@ -438,6 +439,7 @@ struct mvneta_port {
|
|
+ struct device_node *dn;
|
|
+ unsigned int tx_csum_limit;
|
|
+ struct phylink *phylink;
|
|
++ struct phy *comphy;
|
|
+
|
|
+ struct mvneta_bm *bm_priv;
|
|
+ struct mvneta_bm_pool *pool_long;
|
|
+@@ -3168,6 +3170,8 @@ static void mvneta_start_dev(struct mvne
|
|
+ {
|
|
+ int cpu;
|
|
+
|
|
++ WARN_ON(phy_power_on(pp->comphy));
|
|
++
|
|
+ mvneta_max_rx_size_set(pp, pp->pkt_size);
|
|
+ mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
|
|
+
|
|
+@@ -3230,6 +3234,8 @@ static void mvneta_stop_dev(struct mvnet
|
|
+
|
|
+ mvneta_tx_reset(pp);
|
|
+ mvneta_rx_reset(pp);
|
|
++
|
|
++ WARN_ON(phy_power_off(pp->comphy));
|
|
+ }
|
|
+
|
|
+ static void mvneta_percpu_enable(void *arg)
|
|
+@@ -3355,6 +3361,7 @@ static int mvneta_set_mac_addr(struct ne
|
|
+ static void mvneta_validate(struct net_device *ndev, unsigned long *supported,
|
|
+ struct phylink_link_state *state)
|
|
+ {
|
|
++ struct mvneta_port *pp = netdev_priv(ndev);
|
|
+ __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
|
|
+
|
|
+ /* We only support QSGMII, SGMII, 802.3z and RGMII modes */
|
|
+@@ -3375,8 +3382,13 @@ static void mvneta_validate(struct net_d
|
|
+ phylink_set(mask, Pause);
|
|
+
|
|
+ /* Half-duplex at speeds higher than 100Mbit is unsupported */
|
|
+- phylink_set(mask, 1000baseT_Full);
|
|
+- phylink_set(mask, 1000baseX_Full);
|
|
++ if (pp->comphy || state->interface != PHY_INTERFACE_MODE_2500BASEX) {
|
|
++ phylink_set(mask, 1000baseT_Full);
|
|
++ phylink_set(mask, 1000baseX_Full);
|
|
++ }
|
|
++ if (pp->comphy || state->interface == PHY_INTERFACE_MODE_2500BASEX) {
|
|
++ phylink_set(mask, 2500baseX_Full);
|
|
++ }
|
|
+
|
|
+ if (!phy_interface_mode_is_8023z(state->interface)) {
|
|
+ /* 10M and 100M are only supported in non-802.3z mode */
|
|
+@@ -3390,6 +3402,11 @@ static void mvneta_validate(struct net_d
|
|
+ __ETHTOOL_LINK_MODE_MASK_NBITS);
|
|
+ bitmap_and(state->advertising, state->advertising, mask,
|
|
+ __ETHTOOL_LINK_MODE_MASK_NBITS);
|
|
++
|
|
++ /* We can only operate at 2500BaseX or 1000BaseX. If requested
|
|
++ * to advertise both, only report advertising at 2500BaseX.
|
|
++ */
|
|
++ phylink_helper_basex_speed(state);
|
|
+ }
|
|
+
|
|
+ static int mvneta_mac_link_state(struct net_device *ndev,
|
|
+@@ -3401,7 +3418,9 @@ static int mvneta_mac_link_state(struct
|
|
+ gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
|
|
+
|
|
+ if (gmac_stat & MVNETA_GMAC_SPEED_1000)
|
|
+- state->speed = SPEED_1000;
|
|
++ state->speed =
|
|
++ state->interface == PHY_INTERFACE_MODE_2500BASEX ?
|
|
++ SPEED_2500 : SPEED_1000;
|
|
+ else if (gmac_stat & MVNETA_GMAC_SPEED_100)
|
|
+ state->speed = SPEED_100;
|
|
+ else
|
|
+@@ -3516,12 +3535,20 @@ static void mvneta_mac_config(struct net
|
|
+ MVNETA_GMAC_FORCE_LINK_DOWN);
|
|
+ }
|
|
+
|
|
++
|
|
+ /* When at 2.5G, the link partner can send frames with shortened
|
|
+ * preambles.
|
|
+ */
|
|
+ if (state->speed == SPEED_2500)
|
|
+ new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE;
|
|
+
|
|
++ if (pp->comphy &&
|
|
++ (state->interface == PHY_INTERFACE_MODE_SGMII ||
|
|
++ state->interface == PHY_INTERFACE_MODE_1000BASEX ||
|
|
++ state->interface == PHY_INTERFACE_MODE_2500BASEX))
|
|
++ WARN_ON(phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET,
|
|
++ state->interface));
|
|
++
|
|
+ if (new_ctrl0 != gmac_ctrl0)
|
|
+ mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0);
|
|
+ if (new_ctrl2 != gmac_ctrl2)
|
|
+@@ -4434,7 +4461,7 @@ static int mvneta_port_power_up(struct m
|
|
+ if (phy_mode == PHY_INTERFACE_MODE_QSGMII)
|
|
+ mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
|
|
+ else if (phy_mode == PHY_INTERFACE_MODE_SGMII ||
|
|
+- phy_mode == PHY_INTERFACE_MODE_1000BASEX)
|
|
++ phy_interface_mode_is_8023z(phy_mode))
|
|
+ mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
|
|
+ else if (!phy_interface_mode_is_rgmii(phy_mode))
|
|
+ return -EINVAL;
|
|
+@@ -4451,6 +4478,7 @@ static int mvneta_probe(struct platform_
|
|
+ struct mvneta_port *pp;
|
|
+ struct net_device *dev;
|
|
+ struct phylink *phylink;
|
|
++ struct phy *comphy;
|
|
+ const char *dt_mac_addr;
|
|
+ char hw_mac_addr[ETH_ALEN];
|
|
+ const char *mac_from;
|
|
+@@ -4476,6 +4504,14 @@ static int mvneta_probe(struct platform_
|
|
+ goto err_free_irq;
|
|
+ }
|
|
+
|
|
++ comphy = devm_of_phy_get(&pdev->dev, dn, NULL);
|
|
++ if (comphy == ERR_PTR(-EPROBE_DEFER)) {
|
|
++ err = -EPROBE_DEFER;
|
|
++ goto err_free_irq;
|
|
++ } else if (IS_ERR(comphy)) {
|
|
++ comphy = NULL;
|
|
++ }
|
|
++
|
|
+ phylink = phylink_create(dev, pdev->dev.fwnode, phy_mode,
|
|
+ &mvneta_phylink_ops);
|
|
+ if (IS_ERR(phylink)) {
|
|
+@@ -4492,6 +4528,7 @@ static int mvneta_probe(struct platform_
|
|
+ pp = netdev_priv(dev);
|
|
+ spin_lock_init(&pp->lock);
|
|
+ pp->phylink = phylink;
|
|
++ pp->comphy = comphy;
|
|
+ pp->phy_interface = phy_mode;
|
|
+ pp->dn = dn;
|
|
+
|
|
diff --git a/target/linux/mvebu/patches-5.4/536-net-marvell-neta-disable-comphy-when-setting-mode.patch b/target/linux/mvebu/patches-5.4/536-net-marvell-neta-disable-comphy-when-setting-mode.patch
|
|
new file mode 100644
|
|
index 00000000000..bac9a55cf0d
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/536-net-marvell-neta-disable-comphy-when-setting-mode.patch
|
|
@@ -0,0 +1,78 @@
|
|
+From 031b922bfd60c771588911112f8632783de08e5c Mon Sep 17 00:00:00 2001
|
|
+From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <marek.behun@nic.cz>
|
|
+Date: Mon, 25 Feb 2019 17:43:03 +0100
|
|
+Subject: [PATCH] net: marvell: neta: disable comphy when setting mode
|
|
+MIME-Version: 1.0
|
|
+Content-Type: text/plain; charset=UTF-8
|
|
+Content-Transfer-Encoding: 8bit
|
|
+
|
|
+The comphy driver for Armada 3700 by Miquèl Raynal (which is currently
|
|
+in linux-next) does not actually set comphy mode when phy_set_mode_ext
|
|
+is called. The mode is set at next call of phy_power_on.
|
|
+
|
|
+Update the driver to semantics similar to mvpp2: helper
|
|
+mvneta_comphy_init sets comphy mode and powers it on.
|
|
+When mode is to be changed in mvneta_mac_config, first power the comphy
|
|
+off, then call mvneta_comphy_init (which sets the mode to new one).
|
|
+
|
|
+Only do this when new mode is different from old mode.
|
|
+
|
|
+This should also work for Armada 38x, since in that comphy driver
|
|
+methods power_on and power_off are unimplemented.
|
|
+
|
|
+Signed-off-by: Marek Behún <marek.behun@nic.cz>
|
|
+Signed-off-by: David S. Miller <davem@davemloft.net>
|
|
+---
|
|
+ drivers/net/ethernet/marvell/mvneta.c | 28 +++++++++++++++++++++++-----
|
|
+ 1 file changed, 23 insertions(+), 5 deletions(-)
|
|
+
|
|
+--- a/drivers/net/ethernet/marvell/mvneta.c
|
|
++++ b/drivers/net/ethernet/marvell/mvneta.c
|
|
+@@ -3166,11 +3166,26 @@ static int mvneta_setup_txqs(struct mvne
|
|
+ return 0;
|
|
+ }
|
|
+
|
|
++static int mvneta_comphy_init(struct mvneta_port *pp)
|
|
++{
|
|
++ int ret;
|
|
++
|
|
++ if (!pp->comphy)
|
|
++ return 0;
|
|
++
|
|
++ ret = phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET,
|
|
++ pp->phy_interface);
|
|
++ if (ret)
|
|
++ return ret;
|
|
++
|
|
++ return phy_power_on(pp->comphy);
|
|
++}
|
|
++
|
|
+ static void mvneta_start_dev(struct mvneta_port *pp)
|
|
+ {
|
|
+ int cpu;
|
|
+
|
|
+- WARN_ON(phy_power_on(pp->comphy));
|
|
++ WARN_ON(mvneta_comphy_init(pp));
|
|
+
|
|
+ mvneta_max_rx_size_set(pp, pp->pkt_size);
|
|
+ mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
|
|
+@@ -3542,12 +3557,15 @@ static void mvneta_mac_config(struct net
|
|
+ if (state->speed == SPEED_2500)
|
|
+ new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE;
|
|
+
|
|
+- if (pp->comphy &&
|
|
++ if (pp->comphy && pp->phy_interface != state->interface &&
|
|
+ (state->interface == PHY_INTERFACE_MODE_SGMII ||
|
|
+ state->interface == PHY_INTERFACE_MODE_1000BASEX ||
|
|
+- state->interface == PHY_INTERFACE_MODE_2500BASEX))
|
|
+- WARN_ON(phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET,
|
|
+- state->interface));
|
|
++ state->interface == PHY_INTERFACE_MODE_2500BASEX)) {
|
|
++ pp->phy_interface = state->interface;
|
|
++
|
|
++ WARN_ON(phy_power_off(pp->comphy));
|
|
++ WARN_ON(mvneta_comphy_init(pp));
|
|
++ }
|
|
+
|
|
+ if (new_ctrl0 != gmac_ctrl0)
|
|
+ mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0);
|
|
diff --git a/target/linux/mvebu/patches-5.4/537-net-mvneta-add-2500baset-support.patch b/target/linux/mvebu/patches-5.4/537-net-mvneta-add-2500baset-support.patch
|
|
new file mode 100644
|
|
index 00000000000..9186ceb0da4
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/537-net-mvneta-add-2500baset-support.patch
|
|
@@ -0,0 +1,34 @@
|
|
+From eda3d1b0228484fb52b7244a68fd4cc8a985ed10 Mon Sep 17 00:00:00 2001
|
|
+From: Maxime Chevallier <maxime.chevallier@bootlin.com>
|
|
+Date: Wed, 27 Mar 2019 17:31:06 +0100
|
|
+Subject: [PATCH] net: mvneta: Add 2500BaseT support
|
|
+
|
|
+Some PHYs will use the 2500BaseX PHY_INTERFACE_MODE when being linked
|
|
+with a partner using 2.5GBaseT.
|
|
+
|
|
+Since we can't autonegotiate this speed between the MAC and the PHY, we
|
|
+need to have the proper comphy support enabled, to make sure we can
|
|
+safely advertise 2.5G and 1G in BaseT and be able to switch between both
|
|
+corresponding PHY interface modes. This is now possible since comphy
|
|
+support was added to this driver.
|
|
+
|
|
+This commit adds the 2500BaseT mode to the list of supported modes when
|
|
+using 2500BaseX, and was tested on a setup with an Armada385 and a
|
|
+88E2010 PHY, both with and without the comphy node in the DT.
|
|
+
|
|
+Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
|
|
+Signed-off-by: David S. Miller <davem@davemloft.net>
|
|
+---
|
|
+ drivers/net/ethernet/marvell/mvneta.c | 1 +
|
|
+ 1 file changed, 1 insertion(+)
|
|
+
|
|
+--- a/drivers/net/ethernet/marvell/mvneta.c
|
|
++++ b/drivers/net/ethernet/marvell/mvneta.c
|
|
+@@ -3402,6 +3402,7 @@ static void mvneta_validate(struct net_d
|
|
+ phylink_set(mask, 1000baseX_Full);
|
|
+ }
|
|
+ if (pp->comphy || state->interface == PHY_INTERFACE_MODE_2500BASEX) {
|
|
++ phylink_set(mask, 2500baseT_Full);
|
|
+ phylink_set(mask, 2500baseX_Full);
|
|
+ }
|
|
+
|
|
diff --git a/target/linux/mvebu/patches-5.4/538-phy-add-QSGMII-and-PCIE-modes.patch b/target/linux/mvebu/patches-5.4/538-phy-add-QSGMII-and-PCIE-modes.patch
|
|
new file mode 100644
|
|
index 00000000000..b759b9fb254
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/538-phy-add-QSGMII-and-PCIE-modes.patch
|
|
@@ -0,0 +1,28 @@
|
|
+From c2a90025ad09d830c8d8ae69f485eac6aaaa2472 Mon Sep 17 00:00:00 2001
|
|
+From: Quentin Schulz <quentin.schulz@bootlin.com>
|
|
+Date: Thu, 4 Oct 2018 14:22:03 +0200
|
|
+Subject: [PATCH] phy: add QSGMII and PCIE modes
|
|
+
|
|
+Prepare for upcoming phys that'll handle QSGMII or PCIe.
|
|
+
|
|
+Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
|
|
+Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
|
|
+Signed-off-by: David S. Miller <davem@davemloft.net>
|
|
+---
|
|
+ include/linux/phy/phy.h | 2 ++
|
|
+ 1 file changed, 2 insertions(+)
|
|
+
|
|
+--- a/include/linux/phy/phy.h
|
|
++++ b/include/linux/phy/phy.h
|
|
+@@ -37,9 +37,11 @@ enum phy_mode {
|
|
+ PHY_MODE_USB_OTG,
|
|
+ PHY_MODE_SGMII,
|
|
+ PHY_MODE_2500SGMII,
|
|
++ PHY_MODE_QSGMII,
|
|
+ PHY_MODE_10GKR,
|
|
+ PHY_MODE_UFS_HS_A,
|
|
+ PHY_MODE_UFS_HS_B,
|
|
++ PHY_MODE_PCIE,
|
|
+ };
|
|
+
|
|
+ /**
|
|
diff --git a/target/linux/mvebu/patches-5.4/539-phy-core-add-PHY_MODE_ETHERNET.patch b/target/linux/mvebu/patches-5.4/539-phy-core-add-PHY_MODE_ETHERNET.patch
|
|
new file mode 100644
|
|
index 00000000000..68fecadce85
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/539-phy-core-add-PHY_MODE_ETHERNET.patch
|
|
@@ -0,0 +1,24 @@
|
|
+From 2af8caeee47846a84bc96abc3a72f7c991153040 Mon Sep 17 00:00:00 2001
|
|
+From: Grygorii Strashko <grygorii.strashko@ti.com>
|
|
+Date: Mon, 19 Nov 2018 19:24:21 -0600
|
|
+Subject: [PATCH] phy: core: add PHY_MODE_ETHERNET
|
|
+
|
|
+Add new PHY's mode to be used by Ethernet PHY interface drivers or
|
|
+multipurpose PHYs like serdes. It will be reused in further changes.
|
|
+
|
|
+Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
|
|
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
|
|
+---
|
|
+ include/linux/phy/phy.h | 1 +
|
|
+ 1 file changed, 1 insertion(+)
|
|
+
|
|
+--- a/include/linux/phy/phy.h
|
|
++++ b/include/linux/phy/phy.h
|
|
+@@ -42,6 +42,7 @@ enum phy_mode {
|
|
+ PHY_MODE_UFS_HS_A,
|
|
+ PHY_MODE_UFS_HS_B,
|
|
+ PHY_MODE_PCIE,
|
|
++ PHY_MODE_ETHERNET,
|
|
+ };
|
|
+
|
|
+ /**
|
|
diff --git a/target/linux/mvebu/patches-5.4/540-phy-fix-build-breakage-add-PHY_MODE_SATA.patch b/target/linux/mvebu/patches-5.4/540-phy-fix-build-breakage-add-PHY_MODE_SATA.patch
|
|
new file mode 100644
|
|
index 00000000000..83908af19e6
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/540-phy-fix-build-breakage-add-PHY_MODE_SATA.patch
|
|
@@ -0,0 +1,45 @@
|
|
+From e1706720408e72fb883f6b151c2b3b23d8e7e5b2 Mon Sep 17 00:00:00 2001
|
|
+From: John Hubbard <jhubbard@nvidia.com>
|
|
+Date: Sat, 12 Jan 2019 17:29:09 -0800
|
|
+Subject: [PATCH] phy: fix build breakage: add PHY_MODE_SATA
|
|
+
|
|
+Commit 49e54187ae0b ("ata: libahci_platform: comply to PHY framework") uses
|
|
+the PHY_MODE_SATA, but that enum had not yet been added. This caused a
|
|
+build failure for me, with today's linux.git.
|
|
+
|
|
+Also, there is a potentially conflicting (mis-named) PHY_MODE_SATA, hiding
|
|
+in the Marvell Berlin SATA PHY driver.
|
|
+
|
|
+Fix the build by:
|
|
+
|
|
+ 1) Renaming Marvell's defined value to a more scoped name,
|
|
+ in order to avoid any potential conflicts: PHY_BERLIN_MODE_SATA.
|
|
+
|
|
+ 2) Adding the missing enum, which was going to be added anyway as part
|
|
+ of [1].
|
|
+
|
|
+[1] https://lkml.kernel.org/r/20190108163124.6409-3-miquel.raynal@bootlin.com
|
|
+
|
|
+Fixes: 49e54187ae0b ("ata: libahci_platform: comply to PHY framework")
|
|
+
|
|
+Signed-off-by: John Hubbard <jhubbard@nvidia.com>
|
|
+Acked-by: Jens Axboe <axboe@kernel.dk>
|
|
+Acked-by: Olof Johansson <olof@lixom.net>
|
|
+Cc: Grzegorz Jaszczyk <jaz@semihalf.com>
|
|
+Cc: Miquel Raynal <miquel.raynal@bootlin.com>
|
|
+Cc: Hans de Goede <hdegoede@redhat.com>
|
|
+Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
|
|
+---
|
|
+ include/linux/phy/phy.h | 1 +
|
|
+ 1 file changed, 1 insertion(+)
|
|
+
|
|
+--- a/include/linux/phy/phy.h
|
|
++++ b/include/linux/phy/phy.h
|
|
+@@ -43,6 +43,7 @@ enum phy_mode {
|
|
+ PHY_MODE_UFS_HS_B,
|
|
+ PHY_MODE_PCIE,
|
|
+ PHY_MODE_ETHERNET,
|
|
++ PHY_MODE_SATA
|
|
+ };
|
|
+
|
|
+ /**
|
|
diff --git a/target/linux/mvebu/patches-5.4/541-phy-core-rework-phy_set_mode-to-accept-phy-mode-and-.patch b/target/linux/mvebu/patches-5.4/541-phy-core-rework-phy_set_mode-to-accept-phy-mode-and-.patch
|
|
new file mode 100644
|
|
index 00000000000..e02f203912d
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/541-phy-core-rework-phy_set_mode-to-accept-phy-mode-and-.patch
|
|
@@ -0,0 +1,134 @@
|
|
+From 79a5a18aa9d1062205cdcfa183d4cd5241d1b8da Mon Sep 17 00:00:00 2001
|
|
+From: Grygorii Strashko <grygorii.strashko@ti.com>
|
|
+Date: Mon, 19 Nov 2018 19:24:20 -0600
|
|
+Subject: [PATCH] phy: core: rework phy_set_mode to accept phy mode and submode
|
|
+
|
|
+Currently the attempt to add support for Ethernet interface mode PHY
|
|
+(MII/GMII/RGMII) will lead to the necessity of extending enum phy_mode and
|
|
+duplicate there values from phy_interface_t enum (or introduce more PHY
|
|
+callbacks) [1]. Both approaches are ineffective and would lead to fast
|
|
+bloating of enum phy_mode or struct phy_ops in the process of adding more
|
|
+PHYs for different subsystems which will make them unmaintainable.
|
|
+
|
|
+As discussed in [1] the solution could be to introduce dual level PHYs mode
|
|
+configuration - PHY mode and PHY submode. The PHY mode will define generic
|
|
+PHY type (subsystem - PCIE/ETHERNET/USB_) while the PHY submode - subsystem
|
|
+specific interface mode. The last is usually already defined in
|
|
+corresponding subsystem headers (phy_interface_t for Ethernet, enum
|
|
+usb_device_speed for USB).
|
|
+
|
|
+This patch is cumulative change which refactors PHY framework code to
|
|
+support dual level PHYs mode configuration - PHY mode and PHY submode. It
|
|
+extends .set_mode() callback to support additional parameter "int submode"
|
|
+and converts all corresponding PHY drivers to support new .set_mode()
|
|
+callback declaration.
|
|
+The new extended PHY API
|
|
+ int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode)
|
|
+is introduced to support dual level PHYs mode configuration and existing
|
|
+phy_set_mode() API is converted to macros, so PHY framework consumers do
|
|
+not need to be changed (~21 matches).
|
|
+
|
|
+[1] http://lkml.kernel.org/r/d63588f6-9ab0-848a-5ad4-8073143bd95d@ti.com
|
|
+Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
|
|
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
|
|
+---
|
|
+ drivers/phy/allwinner/phy-sun4i-usb.c | 3 ++-
|
|
+ drivers/phy/amlogic/phy-meson-gxl-usb2.c | 5 +++--
|
|
+ drivers/phy/amlogic/phy-meson-gxl-usb3.c | 5 +++--
|
|
+ drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 3 ++-
|
|
+ drivers/phy/mediatek/phy-mtk-tphy.c | 2 +-
|
|
+ drivers/phy/mediatek/phy-mtk-xsphy.c | 2 +-
|
|
+ drivers/phy/mscc/phy-ocelot-serdes.c | 2 +-
|
|
+ drivers/phy/phy-core.c | 6 +++---
|
|
+ drivers/phy/qualcomm/phy-qcom-qmp.c | 3 ++-
|
|
+ drivers/phy/qualcomm/phy-qcom-qusb2.c | 3 ++-
|
|
+ drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.c | 3 ++-
|
|
+ drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.c | 3 ++-
|
|
+ drivers/phy/qualcomm/phy-qcom-usb-hs.c | 3 ++-
|
|
+ drivers/phy/ti/phy-da8xx-usb.c | 3 ++-
|
|
+ drivers/phy/ti/phy-tusb1210.c | 2 +-
|
|
+ include/linux/phy/phy.h | 13 ++++++++++---
|
|
+ 16 files changed, 39 insertions(+), 22 deletions(-)
|
|
+
|
|
+--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
|
|
++++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
|
|
+@@ -512,7 +512,8 @@ static int mvebu_comphy_power_on(struct
|
|
+ return ret;
|
|
+ }
|
|
+
|
|
+-static int mvebu_comphy_set_mode(struct phy *phy, enum phy_mode mode)
|
|
++static int mvebu_comphy_set_mode(struct phy *phy,
|
|
++ enum phy_mode mode, int submode)
|
|
+ {
|
|
+ struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
|
|
+
|
|
+--- a/drivers/phy/phy-core.c
|
|
++++ b/drivers/phy/phy-core.c
|
|
+@@ -360,7 +360,7 @@ int phy_power_off(struct phy *phy)
|
|
+ }
|
|
+ EXPORT_SYMBOL_GPL(phy_power_off);
|
|
+
|
|
+-int phy_set_mode(struct phy *phy, enum phy_mode mode)
|
|
++int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode)
|
|
+ {
|
|
+ int ret;
|
|
+
|
|
+@@ -368,14 +368,14 @@ int phy_set_mode(struct phy *phy, enum p
|
|
+ return 0;
|
|
+
|
|
+ mutex_lock(&phy->mutex);
|
|
+- ret = phy->ops->set_mode(phy, mode);
|
|
++ ret = phy->ops->set_mode(phy, mode, submode);
|
|
+ if (!ret)
|
|
+ phy->attrs.mode = mode;
|
|
+ mutex_unlock(&phy->mutex);
|
|
+
|
|
+ return ret;
|
|
+ }
|
|
+-EXPORT_SYMBOL_GPL(phy_set_mode);
|
|
++EXPORT_SYMBOL_GPL(phy_set_mode_ext);
|
|
+
|
|
+ int phy_reset(struct phy *phy)
|
|
+ {
|
|
+--- a/include/linux/phy/phy.h
|
|
++++ b/include/linux/phy/phy.h
|
|
+@@ -62,7 +62,7 @@ struct phy_ops {
|
|
+ int (*exit)(struct phy *phy);
|
|
+ int (*power_on)(struct phy *phy);
|
|
+ int (*power_off)(struct phy *phy);
|
|
+- int (*set_mode)(struct phy *phy, enum phy_mode mode);
|
|
++ int (*set_mode)(struct phy *phy, enum phy_mode mode, int submode);
|
|
+ int (*reset)(struct phy *phy);
|
|
+ int (*calibrate)(struct phy *phy);
|
|
+ struct module *owner;
|
|
+@@ -166,7 +166,10 @@ int phy_init(struct phy *phy);
|
|
+ int phy_exit(struct phy *phy);
|
|
+ int phy_power_on(struct phy *phy);
|
|
+ int phy_power_off(struct phy *phy);
|
|
+-int phy_set_mode(struct phy *phy, enum phy_mode mode);
|
|
++int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode);
|
|
++#define phy_set_mode(phy, mode) \
|
|
++ phy_set_mode_ext(phy, mode, 0)
|
|
++
|
|
+ static inline enum phy_mode phy_get_mode(struct phy *phy)
|
|
+ {
|
|
+ return phy->attrs.mode;
|
|
+@@ -280,13 +283,17 @@ static inline int phy_power_off(struct p
|
|
+ return -ENOSYS;
|
|
+ }
|
|
+
|
|
+-static inline int phy_set_mode(struct phy *phy, enum phy_mode mode)
|
|
++static inline int phy_set_mode_ext(struct phy *phy, enum phy_mode mode,
|
|
++ int submode)
|
|
+ {
|
|
+ if (!phy)
|
|
+ return 0;
|
|
+ return -ENOSYS;
|
|
+ }
|
|
+
|
|
++#define phy_set_mode(phy, mode) \
|
|
++ phy_set_mode_ext(phy, mode, 0)
|
|
++
|
|
+ static inline enum phy_mode phy_get_mode(struct phy *phy)
|
|
+ {
|
|
+ return PHY_MODE_INVALID;
|
|
diff --git a/target/linux/mvebu/patches-5.4/542-phy-add-A3700-COMPHY-support.patch b/target/linux/mvebu/patches-5.4/542-phy-add-A3700-COMPHY-support.patch
|
|
new file mode 100644
|
|
index 00000000000..0964da03a8d
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/542-phy-add-A3700-COMPHY-support.patch
|
|
@@ -0,0 +1,381 @@
|
|
+From 9695375a3f4a604406f2e61f2b735eca1de931ed Mon Sep 17 00:00:00 2001
|
|
+From: Miquel Raynal <miquel.raynal@bootlin.com>
|
|
+Date: Tue, 8 Jan 2019 17:31:20 +0100
|
|
+Subject: [PATCH] phy: add A3700 COMPHY support
|
|
+
|
|
+Add a driver to support COMPHY, a hardware block providing shared
|
|
+serdes PHYs on Marvell Armada 3700. This driver uses SMC calls and
|
|
+rely on having an up-to-date firmware.
|
|
+
|
|
+SATA, PCie and USB3 host mode have been tested successfully with an
|
|
+ESPRESSObin. (HS)SGMII mode cannot be tested with this platform.
|
|
+
|
|
+Evan worked on the original driver structure and Grzegorz on the SMC
|
|
+calls rework. The structure of this driver has been copied from
|
|
+Antoine Tenart work on CP110 COMPHY driver.
|
|
+
|
|
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
|
|
+Co-developed-by: Evan Wang <xswang@marvell.com>
|
|
+Signed-off-by: Evan Wang <xswang@marvell.com>
|
|
+Co-developed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
|
|
+Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
|
|
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
|
|
+---
|
|
+ drivers/phy/marvell/Kconfig | 12 +
|
|
+ drivers/phy/marvell/Makefile | 1 +
|
|
+ drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 318 +++++++++++++++++++++++++++
|
|
+ 3 files changed, 331 insertions(+)
|
|
+ create mode 100644 drivers/phy/marvell/phy-mvebu-a3700-comphy.c
|
|
+
|
|
+--- a/drivers/phy/marvell/Kconfig
|
|
++++ b/drivers/phy/marvell/Kconfig
|
|
+@@ -21,6 +21,18 @@ config PHY_BERLIN_USB
|
|
+ help
|
|
+ Enable this to support the USB PHY on Marvell Berlin SoCs.
|
|
+
|
|
++config PHY_MVEBU_A3700_COMPHY
|
|
++ tristate "Marvell A3700 comphy driver"
|
|
++ depends on ARCH_MVEBU || COMPILE_TEST
|
|
++ depends on OF
|
|
++ depends on HAVE_ARM_SMCCC
|
|
++ default y
|
|
++ select GENERIC_PHY
|
|
++ help
|
|
++ This driver allows to control the comphy, a hardware block providing
|
|
++ shared serdes PHYs on Marvell Armada 3700. Its serdes lanes can be
|
|
++ used by various controllers: Ethernet, SATA, USB3, PCIe.
|
|
++
|
|
+ config PHY_MVEBU_CP110_COMPHY
|
|
+ tristate "Marvell CP110 comphy driver"
|
|
+ depends on ARCH_MVEBU || COMPILE_TEST
|
|
+--- a/drivers/phy/marvell/Makefile
|
|
++++ b/drivers/phy/marvell/Makefile
|
|
+@@ -2,6 +2,7 @@
|
|
+ obj-$(CONFIG_ARMADA375_USBCLUSTER_PHY) += phy-armada375-usb2.o
|
|
+ obj-$(CONFIG_PHY_BERLIN_SATA) += phy-berlin-sata.o
|
|
+ obj-$(CONFIG_PHY_BERLIN_USB) += phy-berlin-usb.o
|
|
++obj-$(CONFIG_PHY_MVEBU_A3700_COMPHY) += phy-mvebu-a3700-comphy.o
|
|
+ obj-$(CONFIG_PHY_MVEBU_CP110_COMPHY) += phy-mvebu-cp110-comphy.o
|
|
+ obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
|
|
+ obj-$(CONFIG_PHY_PXA_28NM_HSIC) += phy-pxa-28nm-hsic.o
|
|
+--- /dev/null
|
|
++++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
|
|
+@@ -0,0 +1,318 @@
|
|
++// SPDX-License-Identifier: GPL-2.0
|
|
++/*
|
|
++ * Copyright (C) 2018 Marvell
|
|
++ *
|
|
++ * Authors:
|
|
++ * Evan Wang <xswang@marvell.com>
|
|
++ * Miquèl Raynal <miquel.raynal@bootlin.com>
|
|
++ *
|
|
++ * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
|
|
++ * SMC call initial support done by Grzegorz Jaszczyk.
|
|
++ */
|
|
++
|
|
++#include <linux/arm-smccc.h>
|
|
++#include <linux/io.h>
|
|
++#include <linux/iopoll.h>
|
|
++#include <linux/mfd/syscon.h>
|
|
++#include <linux/module.h>
|
|
++#include <linux/phy.h>
|
|
++#include <linux/phy/phy.h>
|
|
++#include <linux/platform_device.h>
|
|
++
|
|
++#define MVEBU_A3700_COMPHY_LANES 3
|
|
++#define MVEBU_A3700_COMPHY_PORTS 2
|
|
++
|
|
++/* COMPHY Fast SMC function identifiers */
|
|
++#define COMPHY_SIP_POWER_ON 0x82000001
|
|
++#define COMPHY_SIP_POWER_OFF 0x82000002
|
|
++#define COMPHY_SIP_PLL_LOCK 0x82000003
|
|
++
|
|
++#define COMPHY_FW_MODE_SATA 0x1
|
|
++#define COMPHY_FW_MODE_SGMII 0x2
|
|
++#define COMPHY_FW_MODE_HS_SGMII 0x3
|
|
++#define COMPHY_FW_MODE_USB3H 0x4
|
|
++#define COMPHY_FW_MODE_USB3D 0x5
|
|
++#define COMPHY_FW_MODE_PCIE 0x6
|
|
++#define COMPHY_FW_MODE_RXAUI 0x7
|
|
++#define COMPHY_FW_MODE_XFI 0x8
|
|
++#define COMPHY_FW_MODE_SFI 0x9
|
|
++#define COMPHY_FW_MODE_USB3 0xa
|
|
++
|
|
++#define COMPHY_FW_SPEED_1_25G 0 /* SGMII 1G */
|
|
++#define COMPHY_FW_SPEED_2_5G 1
|
|
++#define COMPHY_FW_SPEED_3_125G 2 /* SGMII 2.5G */
|
|
++#define COMPHY_FW_SPEED_5G 3
|
|
++#define COMPHY_FW_SPEED_5_15625G 4 /* XFI 5G */
|
|
++#define COMPHY_FW_SPEED_6G 5
|
|
++#define COMPHY_FW_SPEED_10_3125G 6 /* XFI 10G */
|
|
++#define COMPHY_FW_SPEED_MAX 0x3F
|
|
++
|
|
++#define COMPHY_FW_MODE(mode) ((mode) << 12)
|
|
++#define COMPHY_FW_NET(mode, idx, speed) (COMPHY_FW_MODE(mode) | \
|
|
++ ((idx) << 8) | \
|
|
++ ((speed) << 2))
|
|
++#define COMPHY_FW_PCIE(mode, idx, speed, width) (COMPHY_FW_NET(mode, idx, speed) | \
|
|
++ ((width) << 18))
|
|
++
|
|
++struct mvebu_a3700_comphy_conf {
|
|
++ unsigned int lane;
|
|
++ enum phy_mode mode;
|
|
++ int submode;
|
|
++ unsigned int port;
|
|
++ u32 fw_mode;
|
|
++};
|
|
++
|
|
++#define MVEBU_A3700_COMPHY_CONF(_lane, _mode, _smode, _port, _fw) \
|
|
++ { \
|
|
++ .lane = _lane, \
|
|
++ .mode = _mode, \
|
|
++ .submode = _smode, \
|
|
++ .port = _port, \
|
|
++ .fw_mode = _fw, \
|
|
++ }
|
|
++
|
|
++#define MVEBU_A3700_COMPHY_CONF_GEN(_lane, _mode, _port, _fw) \
|
|
++ MVEBU_A3700_COMPHY_CONF(_lane, _mode, PHY_INTERFACE_MODE_NA, _port, _fw)
|
|
++
|
|
++#define MVEBU_A3700_COMPHY_CONF_ETH(_lane, _smode, _port, _fw) \
|
|
++ MVEBU_A3700_COMPHY_CONF(_lane, PHY_MODE_ETHERNET, _smode, _port, _fw)
|
|
++
|
|
++static const struct mvebu_a3700_comphy_conf mvebu_a3700_comphy_modes[] = {
|
|
++ /* lane 0 */
|
|
++ MVEBU_A3700_COMPHY_CONF_GEN(0, PHY_MODE_USB_HOST_SS, 0,
|
|
++ COMPHY_FW_MODE_USB3H),
|
|
++ MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII, 1,
|
|
++ COMPHY_FW_MODE_SGMII),
|
|
++ MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX, 1,
|
|
++ COMPHY_FW_MODE_HS_SGMII),
|
|
++ /* lane 1 */
|
|
++ MVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE, 0,
|
|
++ COMPHY_FW_MODE_PCIE),
|
|
++ MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII, 0,
|
|
++ COMPHY_FW_MODE_SGMII),
|
|
++ MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX, 0,
|
|
++ COMPHY_FW_MODE_HS_SGMII),
|
|
++ /* lane 2 */
|
|
++ MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA, 0,
|
|
++ COMPHY_FW_MODE_SATA),
|
|
++ MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_USB_HOST_SS, 0,
|
|
++ COMPHY_FW_MODE_USB3H),
|
|
++};
|
|
++
|
|
++struct mvebu_a3700_comphy_lane {
|
|
++ struct device *dev;
|
|
++ unsigned int id;
|
|
++ enum phy_mode mode;
|
|
++ int submode;
|
|
++ int port;
|
|
++};
|
|
++
|
|
++static int mvebu_a3700_comphy_smc(unsigned long function, unsigned long lane,
|
|
++ unsigned long mode)
|
|
++{
|
|
++ struct arm_smccc_res res;
|
|
++
|
|
++ arm_smccc_smc(function, lane, mode, 0, 0, 0, 0, 0, &res);
|
|
++
|
|
++ return res.a0;
|
|
++}
|
|
++
|
|
++static int mvebu_a3700_comphy_get_fw_mode(int lane, int port,
|
|
++ enum phy_mode mode,
|
|
++ int submode)
|
|
++{
|
|
++ int i, n = ARRAY_SIZE(mvebu_a3700_comphy_modes);
|
|
++
|
|
++ /* Unused PHY mux value is 0x0 */
|
|
++ if (mode == PHY_MODE_INVALID)
|
|
++ return -EINVAL;
|
|
++
|
|
++ for (i = 0; i < n; i++) {
|
|
++ if (mvebu_a3700_comphy_modes[i].lane == lane &&
|
|
++ mvebu_a3700_comphy_modes[i].port == port &&
|
|
++ mvebu_a3700_comphy_modes[i].mode == mode &&
|
|
++ mvebu_a3700_comphy_modes[i].submode == submode)
|
|
++ break;
|
|
++ }
|
|
++
|
|
++ if (i == n)
|
|
++ return -EINVAL;
|
|
++
|
|
++ return mvebu_a3700_comphy_modes[i].fw_mode;
|
|
++}
|
|
++
|
|
++static int mvebu_a3700_comphy_set_mode(struct phy *phy, enum phy_mode mode,
|
|
++ int submode)
|
|
++{
|
|
++ struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
|
|
++ int fw_mode;
|
|
++
|
|
++ if (submode == PHY_INTERFACE_MODE_1000BASEX)
|
|
++ submode = PHY_INTERFACE_MODE_SGMII;
|
|
++
|
|
++ fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, lane->port, mode,
|
|
++ submode);
|
|
++ if (fw_mode < 0) {
|
|
++ dev_err(lane->dev, "invalid COMPHY mode\n");
|
|
++ return fw_mode;
|
|
++ }
|
|
++
|
|
++ /* Just remember the mode, ->power_on() will do the real setup */
|
|
++ lane->mode = mode;
|
|
++ lane->submode = submode;
|
|
++
|
|
++ return 0;
|
|
++}
|
|
++
|
|
++static int mvebu_a3700_comphy_power_on(struct phy *phy)
|
|
++{
|
|
++ struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
|
|
++ u32 fw_param;
|
|
++ int fw_mode;
|
|
++
|
|
++ fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, lane->port,
|
|
++ lane->mode, lane->submode);
|
|
++ if (fw_mode < 0) {
|
|
++ dev_err(lane->dev, "invalid COMPHY mode\n");
|
|
++ return fw_mode;
|
|
++ }
|
|
++
|
|
++ switch (lane->mode) {
|
|
++ case PHY_MODE_USB_HOST_SS:
|
|
++ dev_dbg(lane->dev, "set lane %d to USB3 host mode\n", lane->id);
|
|
++ fw_param = COMPHY_FW_MODE(fw_mode);
|
|
++ break;
|
|
++ case PHY_MODE_SATA:
|
|
++ dev_dbg(lane->dev, "set lane %d to SATA mode\n", lane->id);
|
|
++ fw_param = COMPHY_FW_MODE(fw_mode);
|
|
++ break;
|
|
++ case PHY_MODE_ETHERNET:
|
|
++ switch (lane->submode) {
|
|
++ case PHY_INTERFACE_MODE_SGMII:
|
|
++ dev_dbg(lane->dev, "set lane %d to SGMII mode\n",
|
|
++ lane->id);
|
|
++ fw_param = COMPHY_FW_NET(fw_mode, lane->port,
|
|
++ COMPHY_FW_SPEED_1_25G);
|
|
++ break;
|
|
++ case PHY_INTERFACE_MODE_2500BASEX:
|
|
++ dev_dbg(lane->dev, "set lane %d to HS SGMII mode\n",
|
|
++ lane->id);
|
|
++ fw_param = COMPHY_FW_NET(fw_mode, lane->port,
|
|
++ COMPHY_FW_SPEED_3_125G);
|
|
++ break;
|
|
++ default:
|
|
++ dev_err(lane->dev, "unsupported PHY submode (%d)\n",
|
|
++ lane->submode);
|
|
++ return -ENOTSUPP;
|
|
++ }
|
|
++ break;
|
|
++ case PHY_MODE_PCIE:
|
|
++ dev_dbg(lane->dev, "set lane %d to PCIe mode\n", lane->id);
|
|
++ fw_param = COMPHY_FW_PCIE(fw_mode, lane->port,
|
|
++ COMPHY_FW_SPEED_5G,
|
|
++ phy->attrs.bus_width);
|
|
++ break;
|
|
++ default:
|
|
++ dev_err(lane->dev, "unsupported PHY mode (%d)\n", lane->mode);
|
|
++ return -ENOTSUPP;
|
|
++ }
|
|
++
|
|
++ return mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_ON, lane->id, fw_param);
|
|
++}
|
|
++
|
|
++static int mvebu_a3700_comphy_power_off(struct phy *phy)
|
|
++{
|
|
++ struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
|
|
++
|
|
++ return mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_OFF, lane->id, 0);
|
|
++}
|
|
++
|
|
++static const struct phy_ops mvebu_a3700_comphy_ops = {
|
|
++ .power_on = mvebu_a3700_comphy_power_on,
|
|
++ .power_off = mvebu_a3700_comphy_power_off,
|
|
++ .set_mode = mvebu_a3700_comphy_set_mode,
|
|
++ .owner = THIS_MODULE,
|
|
++};
|
|
++
|
|
++static struct phy *mvebu_a3700_comphy_xlate(struct device *dev,
|
|
++ struct of_phandle_args *args)
|
|
++{
|
|
++ struct mvebu_a3700_comphy_lane *lane;
|
|
++ struct phy *phy;
|
|
++
|
|
++ if (WARN_ON(args->args[0] >= MVEBU_A3700_COMPHY_PORTS))
|
|
++ return ERR_PTR(-EINVAL);
|
|
++
|
|
++ phy = of_phy_simple_xlate(dev, args);
|
|
++ if (IS_ERR(phy))
|
|
++ return phy;
|
|
++
|
|
++ lane = phy_get_drvdata(phy);
|
|
++ lane->port = args->args[0];
|
|
++
|
|
++ return phy;
|
|
++}
|
|
++
|
|
++static int mvebu_a3700_comphy_probe(struct platform_device *pdev)
|
|
++{
|
|
++ struct phy_provider *provider;
|
|
++ struct device_node *child;
|
|
++
|
|
++ for_each_available_child_of_node(pdev->dev.of_node, child) {
|
|
++ struct mvebu_a3700_comphy_lane *lane;
|
|
++ struct phy *phy;
|
|
++ int ret;
|
|
++ u32 lane_id;
|
|
++
|
|
++ ret = of_property_read_u32(child, "reg", &lane_id);
|
|
++ if (ret < 0) {
|
|
++ dev_err(&pdev->dev, "missing 'reg' property (%d)\n",
|
|
++ ret);
|
|
++ continue;
|
|
++ }
|
|
++
|
|
++ if (lane_id >= MVEBU_A3700_COMPHY_LANES) {
|
|
++ dev_err(&pdev->dev, "invalid 'reg' property\n");
|
|
++ continue;
|
|
++ }
|
|
++
|
|
++ lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL);
|
|
++ if (!lane)
|
|
++ return -ENOMEM;
|
|
++
|
|
++ phy = devm_phy_create(&pdev->dev, child,
|
|
++ &mvebu_a3700_comphy_ops);
|
|
++ if (IS_ERR(phy))
|
|
++ return PTR_ERR(phy);
|
|
++
|
|
++ lane->dev = &pdev->dev;
|
|
++ lane->mode = PHY_MODE_INVALID;
|
|
++ lane->submode = PHY_INTERFACE_MODE_NA;
|
|
++ lane->id = lane_id;
|
|
++ lane->port = -1;
|
|
++ phy_set_drvdata(phy, lane);
|
|
++ }
|
|
++
|
|
++ provider = devm_of_phy_provider_register(&pdev->dev,
|
|
++ mvebu_a3700_comphy_xlate);
|
|
++ return PTR_ERR_OR_ZERO(provider);
|
|
++}
|
|
++
|
|
++static const struct of_device_id mvebu_a3700_comphy_of_match_table[] = {
|
|
++ { .compatible = "marvell,comphy-a3700" },
|
|
++ { },
|
|
++};
|
|
++MODULE_DEVICE_TABLE(of, mvebu_a3700_comphy_of_match_table);
|
|
++
|
|
++static struct platform_driver mvebu_a3700_comphy_driver = {
|
|
++ .probe = mvebu_a3700_comphy_probe,
|
|
++ .driver = {
|
|
++ .name = "mvebu-a3700-comphy",
|
|
++ .of_match_table = mvebu_a3700_comphy_of_match_table,
|
|
++ },
|
|
++};
|
|
++module_platform_driver(mvebu_a3700_comphy_driver);
|
|
++
|
|
++MODULE_AUTHOR("Miquèl Raynal <miquel.raynal@bootlin.com>");
|
|
++MODULE_DESCRIPTION("Common PHY driver for A3700");
|
|
++MODULE_LICENSE("GPL v2");
|
|
diff --git a/target/linux/mvebu/patches-5.4/543-arm64-dts-marvell-armada-37xx-declare-the-COMPHY.patch b/target/linux/mvebu/patches-5.4/543-arm64-dts-marvell-armada-37xx-declare-the-COMPHY.patch
|
|
new file mode 100644
|
|
index 00000000000..393f8237944
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/543-arm64-dts-marvell-armada-37xx-declare-the-COMPHY.patch
|
|
@@ -0,0 +1,58 @@
|
|
+From 2ef303f0fe44feee4a3ca8bd62fca86c105927d2 Mon Sep 17 00:00:00 2001
|
|
+From: Miquel Raynal <miquel.raynal@bootlin.com>
|
|
+Date: Tue, 8 Jan 2019 17:31:24 +0100
|
|
+Subject: [PATCH] arm64: dts: marvell: armada-37xx: declare the COMPHY
|
|
+ node
|
|
+
|
|
+Describe the A3700 COMPHY node. It has three PHYs that can be
|
|
+configured as follow:
|
|
+* PCIe or GbE
|
|
+* USB3 or GbE
|
|
+* SATA or USB3
|
|
+Each of them has its own memory area.
|
|
+
|
|
+Suggested-by: Grzegorz Jaszczyk <jaz@semihalf.com>
|
|
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
|
|
+Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
|
|
+---
|
|
+ arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 29 ++++++++++++++++++++++++++++
|
|
+ 1 file changed, 29 insertions(+)
|
|
+
|
|
+--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
|
|
++++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
|
|
+@@ -235,6 +235,35 @@
|
|
+ reg = <0x14000 0x60>;
|
|
+ };
|
|
+
|
|
++ comphy: phy@18300 {
|
|
++ compatible = "marvell,comphy-a3700";
|
|
++ reg = <0x18300 0x300>,
|
|
++ <0x1F000 0x400>,
|
|
++ <0x5C000 0x400>,
|
|
++ <0xe0178 0x8>;
|
|
++ reg-names = "comphy",
|
|
++ "lane1_pcie_gbe",
|
|
++ "lane0_usb3_gbe",
|
|
++ "lane2_sata_usb3";
|
|
++ #address-cells = <1>;
|
|
++ #size-cells = <0>;
|
|
++
|
|
++ comphy0: phy@0 {
|
|
++ reg = <0>;
|
|
++ #phy-cells = <1>;
|
|
++ };
|
|
++
|
|
++ comphy1: phy@1 {
|
|
++ reg = <1>;
|
|
++ #phy-cells = <1>;
|
|
++ };
|
|
++
|
|
++ comphy2: phy@2 {
|
|
++ reg = <2>;
|
|
++ #phy-cells = <1>;
|
|
++ };
|
|
++ };
|
|
++
|
|
+ pinctrl_sb: pinctrl@18800 {
|
|
+ compatible = "marvell,armada3710-sb-pinctrl",
|
|
+ "syscon", "simple-mfd";
|
|
diff --git a/target/linux/mvebu/patches-5.4/544-arm64-dts-uDPU-fix-comphy-definitions.patch b/target/linux/mvebu/patches-5.4/544-arm64-dts-uDPU-fix-comphy-definitions.patch
|
|
new file mode 100644
|
|
index 00000000000..f72ea93b97e
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/544-arm64-dts-uDPU-fix-comphy-definitions.patch
|
|
@@ -0,0 +1,35 @@
|
|
+From 9c222a1d78a1700220e38feb270f00d2ddd3c5ab Mon Sep 17 00:00:00 2001
|
|
+From: Russell King <rmk+kernel@armlinux.org.uk>
|
|
+Date: Wed, 6 Nov 2019 13:44:21 +0000
|
|
+Subject: [PATCH 657/660] arm64: dts: uDPU: fix comphy definitions
|
|
+
|
|
+The uDPU uses both ethernet controllers, which ties up COMPHY 0 for
|
|
+eth1 and COMPHY 1 for eth0, with no USB3 comphy. The addition of
|
|
+COMPHY support made the kernel override the setup by the boot loader
|
|
+breaking this platform. Delete the USB3 COMPHY definition at platform
|
|
+level, and add phy specifications for the ethernet channels.
|
|
+
|
|
+Fixes: bd3d25b07342 ("arm64: dts: marvell: armada-37xx: link USB hosts with their PHYs")
|
|
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
|
+---
|
|
+ arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts | 2 ++
|
|
+ 1 file changed, 2 insertions(+)
|
|
+
|
|
+--- a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts
|
|
++++ b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts
|
|
+@@ -143,6 +143,7 @@
|
|
+ status = "okay";
|
|
+ phy-mode = "sgmii";
|
|
+ managed = "in-band-status";
|
|
++ phys = <&comphy1 0>;
|
|
+ sfp = <&sfp_eth0>;
|
|
+ };
|
|
+
|
|
+@@ -150,6 +151,7 @@
|
|
+ status = "okay";
|
|
+ phy-mode = "sgmii";
|
|
+ managed = "in-band-status";
|
|
++ phys = <&comphy0 1>;
|
|
+ sfp = <&sfp_eth1>;
|
|
+ };
|
|
+
|
|
diff --git a/target/linux/mvebu/patches-5.4/545-arm64-dts-uDPU-remove-i2c-fast-mode.patch b/target/linux/mvebu/patches-5.4/545-arm64-dts-uDPU-remove-i2c-fast-mode.patch
|
|
new file mode 100644
|
|
index 00000000000..b984eb4ba16
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/545-arm64-dts-uDPU-remove-i2c-fast-mode.patch
|
|
@@ -0,0 +1,30 @@
|
|
+From 662eb8fc87f982e63ccb9a9df25c7aeabf9fe341 Mon Sep 17 00:00:00 2001
|
|
+From: Russell King <rmk+kernel@armlinux.org.uk>
|
|
+Date: Thu, 14 Nov 2019 00:23:35 +0000
|
|
+Subject: [PATCH 658/660] arm64: dts: uDPU: remove i2c-fast-mode
|
|
+
|
|
+The I2C bus violates the timing specifications when run in fast mode
|
|
+on the uDPU, so switch to 100kHz mode.
|
|
+
|
|
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
|
+---
|
|
+ arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts | 2 ++
|
|
+ 1 file changed, 2 insertions(+)
|
|
+
|
|
+--- a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts
|
|
++++ b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts
|
|
+@@ -119,12 +119,14 @@
|
|
+ status = "okay";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c1_pins>;
|
|
++ /delete-property/mrvl,i2c-fast-mode;
|
|
+ };
|
|
+
|
|
+ &i2c1 {
|
|
+ status = "okay";
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&i2c2_pins>;
|
|
++ /delete-property/mrvl,i2c-fast-mode;
|
|
+
|
|
+ lm75@48 {
|
|
+ status = "okay";
|
|
diff --git a/target/linux/mvebu/patches-5.4/546-arm64-dts-uDPU-SFP-cages-support-3W-modules.patch b/target/linux/mvebu/patches-5.4/546-arm64-dts-uDPU-SFP-cages-support-3W-modules.patch
|
|
new file mode 100644
|
|
index 00000000000..d025f36a53c
|
|
--- /dev/null
|
|
+++ b/target/linux/mvebu/patches-5.4/546-arm64-dts-uDPU-SFP-cages-support-3W-modules.patch
|
|
@@ -0,0 +1,33 @@
|
|
+From 1cb114a20854e34324a2cb308f23054ff8227ffa Mon Sep 17 00:00:00 2001
|
|
+From: Russell King <rmk+kernel@armlinux.org.uk>
|
|
+Date: Tue, 19 Nov 2019 22:48:50 +0000
|
|
+Subject: [PATCH 659/660] arm64: dts: uDPU: SFP cages support 3W modules
|
|
+
|
|
+The SFP cages are designed to support up to 3W modules, such as G.hn,
|
|
+G.fast and MoCA modules. Although there is no way for such modules to
|
|
+declare to software that they consume 3W, we document in DT that this
|
|
+is the designed power level for these cages.
|
|
+
|
|
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
|
+---
|
|
+ arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts | 2 ++
|
|
+ 1 file changed, 2 insertions(+)
|
|
+
|
|
+--- a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts
|
|
++++ b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts
|
|
+@@ -69,6 +69,7 @@
|
|
+ mod-def0-gpio = <&gpiosb 3 GPIO_ACTIVE_LOW>;
|
|
+ tx-disable-gpio = <&gpiosb 4 GPIO_ACTIVE_HIGH>;
|
|
+ tx-fault-gpio = <&gpiosb 5 GPIO_ACTIVE_HIGH>;
|
|
++ maximum-power-milliwatt = <3000>;
|
|
+ };
|
|
+
|
|
+ sfp_eth1: sfp-eth1 {
|
|
+@@ -78,6 +79,7 @@
|
|
+ mod-def0-gpio = <&gpiosb 8 GPIO_ACTIVE_LOW>;
|
|
+ tx-disable-gpio = <&gpiosb 9 GPIO_ACTIVE_HIGH>;
|
|
+ tx-fault-gpio = <&gpiosb 10 GPIO_ACTIVE_HIGH>;
|
|
++ maximum-power-milliwatt = <3000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
|
|
From b526702f2900f8fc2126feedb43be3641a7a8484 Mon Sep 17 00:00:00 2001
|
|
From: DENG Qingfang <dengqf6@mail2.sysu.edu.cn>
|
|
Date: Wed, 4 Mar 2020 20:46:23 +0800
|
|
Subject: [PATCH 2/4] mvebu: set kernel testing version to 5.4
|
|
|
|
Signed-off-by: DENG Qingfang <dengqf6@mail2.sysu.edu.cn>
|
|
---
|
|
target/linux/mvebu/Makefile | 1 +
|
|
1 file changed, 1 insertion(+)
|
|
|
|
diff --git a/target/linux/mvebu/Makefile b/target/linux/mvebu/Makefile
|
|
index 1688065a5ce..05003689806 100644
|
|
--- a/target/linux/mvebu/Makefile
|
|
+++ b/target/linux/mvebu/Makefile
|
|
@@ -13,6 +13,7 @@ SUBTARGETS:=cortexa9 cortexa53 cortexa72
|
|
MAINTAINER:=Imre Kaloz <kaloz@openwrt.org>
|
|
|
|
KERNEL_PATCHVER:=4.19
|
|
+KERNEL_TESTING_PATCHVER:=5.4
|
|
|
|
include $(INCLUDE_DIR)/target.mk
|
|
|
|
|
|
From 745a16c12188efbcfb2f8c0797898cf1bab4839d Mon Sep 17 00:00:00 2001
|
|
From: DENG Qingfang <dengqf6@mail2.sysu.edu.cn>
|
|
Date: Wed, 4 Mar 2020 20:46:28 +0800
|
|
Subject: [PATCH 3/4] mvebu: refresh patches
|
|
|
|
Signed-off-by: DENG Qingfang <dengqf6@mail2.sysu.edu.cn>
|
|
---
|
|
.../boot/dts/marvell/armada-3720-uDPU.dts | 162 --------
|
|
.../patches-5.4/002-add_powertables.patch | 2 +-
|
|
.../patches-5.4/003-add_switch_nodes.patch | 6 +-
|
|
...Mangle-bootloader-s-kernel-arguments.patch | 10 +-
|
|
.../patches-5.4/100-find_active_root.patch | 12 +-
|
|
.../210-clearfog_switch_node.patch | 2 +-
|
|
.../220-disable-untested-dsa-boards.patch | 4 +-
|
|
...-armada-xp-linksys-mamba-broken-idle.patch | 2 +-
|
|
.../300-mvneta-tx-queue-workaround.patch | 7 +-
|
|
...-pci-mvebu-time-out-reset-on-link-up.patch | 6 +-
|
|
...rmada388-clearfog-document-MPP-usage.patch | 124 ------
|
|
...l-armada37xx-Add-emmc-sdio-pinctrl-d.patch | 40 --
|
|
...l-armada-37xx-Enable-emmc-on-espress.patch | 49 ---
|
|
...da-3720-espressobin-correct-spi-node.patch | 58 ---
|
|
...l-armada-3720-espressobin-add-ports-.patch | 2 +-
|
|
...rdvark-Convert-to-use-pci_host_probe.patch | 4 +-
|
|
...-device-to-the-same-MAX-payload-size.patch | 8 +-
|
|
...ardvark-disable-LOS-state-by-default.patch | 2 +-
|
|
...ark-allow-to-specify-link-capability.patch | 4 +-
|
|
...-3720-espressobin-set-max-link-to-ge.patch | 8 +-
|
|
...vneta-Add-support-for-2500Mbps-SGMII.patch | 104 -----
|
|
.../532-net-mvneta-correct-typo.patch | 33 --
|
|
...net-mvneta-Dont-advertise-2.5G-modes.patch | 55 ---
|
|
...et-mvneta-remove-redundant-check-for.patch | 30 --
|
|
...-net-marvell-neta-add-comphy-support.patch | 159 --------
|
|
...eta-disable-comphy-when-setting-mode.patch | 78 ----
|
|
...537-net-mvneta-add-2500baset-support.patch | 34 --
|
|
.../538-phy-add-QSGMII-and-PCIE-modes.patch | 28 --
|
|
.../539-phy-core-add-PHY_MODE_ETHERNET.patch | 24 --
|
|
...fix-build-breakage-add-PHY_MODE_SATA.patch | 45 ---
|
|
...phy_set_mode-to-accept-phy-mode-and-.patch | 134 ------
|
|
.../542-phy-add-A3700-COMPHY-support.patch | 381 ------------------
|
|
...rvell-armada-37xx-declare-the-COMPHY.patch | 58 ---
|
|
...rm64-dts-uDPU-fix-comphy-definitions.patch | 35 --
|
|
34 files changed, 39 insertions(+), 1671 deletions(-)
|
|
delete mode 100644 target/linux/mvebu/files-5.4/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts
|
|
delete mode 100644 target/linux/mvebu/patches-5.4/415-ARM-dts-armada388-clearfog-document-MPP-usage.patch
|
|
delete mode 100644 target/linux/mvebu/patches-5.4/513-arm64-dts-marvell-armada37xx-Add-emmc-sdio-pinctrl-d.patch
|
|
delete mode 100644 target/linux/mvebu/patches-5.4/514-arm64-dts-marvell-armada-37xx-Enable-emmc-on-espress.patch
|
|
delete mode 100644 target/linux/mvebu/patches-5.4/521-arm64-dts-armada-3720-espressobin-correct-spi-node.patch
|
|
delete mode 100644 target/linux/mvebu/patches-5.4/531-net-mvneta-Add-support-for-2500Mbps-SGMII.patch
|
|
delete mode 100644 target/linux/mvebu/patches-5.4/532-net-mvneta-correct-typo.patch
|
|
delete mode 100644 target/linux/mvebu/patches-5.4/533-net-mvneta-Dont-advertise-2.5G-modes.patch
|
|
delete mode 100644 target/linux/mvebu/patches-5.4/534-net-mvneta-remove-redundant-check-for.patch
|
|
delete mode 100644 target/linux/mvebu/patches-5.4/535-net-marvell-neta-add-comphy-support.patch
|
|
delete mode 100644 target/linux/mvebu/patches-5.4/536-net-marvell-neta-disable-comphy-when-setting-mode.patch
|
|
delete mode 100644 target/linux/mvebu/patches-5.4/537-net-mvneta-add-2500baset-support.patch
|
|
delete mode 100644 target/linux/mvebu/patches-5.4/538-phy-add-QSGMII-and-PCIE-modes.patch
|
|
delete mode 100644 target/linux/mvebu/patches-5.4/539-phy-core-add-PHY_MODE_ETHERNET.patch
|
|
delete mode 100644 target/linux/mvebu/patches-5.4/540-phy-fix-build-breakage-add-PHY_MODE_SATA.patch
|
|
delete mode 100644 target/linux/mvebu/patches-5.4/541-phy-core-rework-phy_set_mode-to-accept-phy-mode-and-.patch
|
|
delete mode 100644 target/linux/mvebu/patches-5.4/542-phy-add-A3700-COMPHY-support.patch
|
|
delete mode 100644 target/linux/mvebu/patches-5.4/543-arm64-dts-marvell-armada-37xx-declare-the-COMPHY.patch
|
|
delete mode 100644 target/linux/mvebu/patches-5.4/544-arm64-dts-uDPU-fix-comphy-definitions.patch
|
|
|
|
diff --git a/target/linux/mvebu/files-5.4/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts b/target/linux/mvebu/files-5.4/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts
|
|
deleted file mode 100644
|
|
index 5b722b4f832..00000000000
|
|
--- a/target/linux/mvebu/files-5.4/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts
|
|
+++ /dev/null
|
|
@@ -1,162 +0,0 @@
|
|
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
-/*
|
|
- * Device tree for the uDPU board.
|
|
- * Based on Marvell Armada 3720 development board (DB-88F3720-DDR3)
|
|
- * Copyright (C) 2016 Marvell
|
|
- * Copyright (C) 2019 Methode Electronics
|
|
- * Copyright (C) 2019 Telus
|
|
- *
|
|
- * Vladimir Vid <vladimir.vid@sartura.hr>
|
|
- */
|
|
-
|
|
-/dts-v1/;
|
|
-
|
|
-#include <dt-bindings/gpio/gpio.h>
|
|
-#include "armada-372x.dtsi"
|
|
-
|
|
-/ {
|
|
- model = "Methode uDPU Board";
|
|
- compatible = "methode,udpu", "marvell,armada3720";
|
|
-
|
|
- chosen {
|
|
- stdout-path = "serial0:115200n8";
|
|
- };
|
|
-
|
|
- memory@0 {
|
|
- device_type = "memory";
|
|
- reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
|
|
- };
|
|
-
|
|
- leds {
|
|
- pinctrl-names = "default";
|
|
- compatible = "gpio-leds";
|
|
-
|
|
- power1 {
|
|
- label = "udpu:green:power";
|
|
- gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
|
|
- };
|
|
-
|
|
- power2 {
|
|
- label = "udpu:red:power";
|
|
- gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
|
|
- };
|
|
-
|
|
- network1 {
|
|
- label = "udpu:green:network";
|
|
- gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
|
|
- };
|
|
-
|
|
- network2 {
|
|
- label = "udpu:red:network";
|
|
- gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
|
|
- };
|
|
-
|
|
- alarm1 {
|
|
- label = "udpu:green:alarm";
|
|
- gpios = <&gpionb 15 GPIO_ACTIVE_LOW>;
|
|
- };
|
|
-
|
|
- alarm2 {
|
|
- label = "udpu:red:alarm";
|
|
- gpios = <&gpionb 16 GPIO_ACTIVE_LOW>;
|
|
- };
|
|
- };
|
|
-
|
|
- sfp_eth0: sfp-eth0 {
|
|
- compatible = "sff,sfp";
|
|
- i2c-bus = <&i2c0>;
|
|
- los-gpio = <&gpiosb 2 GPIO_ACTIVE_HIGH>;
|
|
- mod-def0-gpio = <&gpiosb 3 GPIO_ACTIVE_LOW>;
|
|
- tx-disable-gpio = <&gpiosb 4 GPIO_ACTIVE_HIGH>;
|
|
- tx-fault-gpio = <&gpiosb 5 GPIO_ACTIVE_HIGH>;
|
|
- };
|
|
-
|
|
- sfp_eth1: sfp-eth1 {
|
|
- compatible = "sff,sfp";
|
|
- i2c-bus = <&i2c1>;
|
|
- los-gpio = <&gpiosb 7 GPIO_ACTIVE_HIGH>;
|
|
- mod-def0-gpio = <&gpiosb 8 GPIO_ACTIVE_LOW>;
|
|
- tx-disable-gpio = <&gpiosb 9 GPIO_ACTIVE_HIGH>;
|
|
- tx-fault-gpio = <&gpiosb 10 GPIO_ACTIVE_HIGH>;
|
|
- };
|
|
-};
|
|
-
|
|
-&sdhci0 {
|
|
- status = "okay";
|
|
- bus-width = <8>;
|
|
- mmc-ddr-1_8v;
|
|
- mmc-hs400-1_8v;
|
|
- marvell,pad-type = "fixed-1-8v";
|
|
- non-removable;
|
|
- no-sd;
|
|
- no-sdio;
|
|
-};
|
|
-
|
|
-&spi0 {
|
|
- status = "okay";
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&spi_quad_pins>;
|
|
-
|
|
- flash@0 {
|
|
- compatible = "jedec,spi-nor";
|
|
- reg = <0>;
|
|
- spi-max-frequency = <54000000>;
|
|
-
|
|
- partitions {
|
|
- compatible = "fixed-partitions";
|
|
- #address-cells = <1>;
|
|
- #size-cells = <1>;
|
|
- /* only bootloader is located on the SPI */
|
|
- partition@0 {
|
|
- label = "uboot";
|
|
- reg = <0 0x400000>;
|
|
- };
|
|
- };
|
|
- };
|
|
-};
|
|
-
|
|
-&i2c0 {
|
|
- status = "okay";
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&i2c1_pins>;
|
|
-};
|
|
-
|
|
-&i2c1 {
|
|
- status = "okay";
|
|
- pinctrl-names = "default";
|
|
- pinctrl-0 = <&i2c2_pins>;
|
|
-
|
|
- lm75@48 {
|
|
- status = "okay";
|
|
- compatible = "lm75";
|
|
- reg = <0x48>;
|
|
- };
|
|
-
|
|
- lm75@49 {
|
|
- status = "okay";
|
|
- compatible = "lm75";
|
|
- reg = <0x49>;
|
|
- };
|
|
-};
|
|
-
|
|
-ð0 {
|
|
- status = "okay";
|
|
- phy-mode = "sgmii";
|
|
- managed = "in-band-status";
|
|
- sfp = <&sfp_eth0>;
|
|
-};
|
|
-
|
|
-ð1 {
|
|
- status = "okay";
|
|
- phy-mode = "sgmii";
|
|
- managed = "in-band-status";
|
|
- sfp = <&sfp_eth1>;
|
|
-};
|
|
-
|
|
-&usb3 {
|
|
- status = "okay";
|
|
-};
|
|
-
|
|
-&uart0 {
|
|
- status = "okay";
|
|
-};
|
|
diff --git a/target/linux/mvebu/patches-5.4/002-add_powertables.patch b/target/linux/mvebu/patches-5.4/002-add_powertables.patch
|
|
index c2fb748d5d0..efbbbc7d786 100644
|
|
--- a/target/linux/mvebu/patches-5.4/002-add_powertables.patch
|
|
+++ b/target/linux/mvebu/patches-5.4/002-add_powertables.patch
|
|
@@ -667,7 +667,7 @@
|
|
pinctrl-0 = <&sdhci_pins>;
|
|
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
|
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
|
-@@ -272,12 +272,100 @@
|
|
+@@ -225,12 +225,100 @@
|
|
pcie@2,0 {
|
|
/* Port 0, Lane 1 */
|
|
status = "okay";
|
|
diff --git a/target/linux/mvebu/patches-5.4/003-add_switch_nodes.patch b/target/linux/mvebu/patches-5.4/003-add_switch_nodes.patch
|
|
index b2086389163..e13973767f9 100644
|
|
--- a/target/linux/mvebu/patches-5.4/003-add_switch_nodes.patch
|
|
+++ b/target/linux/mvebu/patches-5.4/003-add_switch_nodes.patch
|
|
@@ -1,8 +1,8 @@
|
|
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
|
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
|
-@@ -257,6 +257,16 @@
|
|
- };
|
|
- };
|
|
+@@ -210,6 +210,16 @@
|
|
+ compatible = "pwm-fan";
|
|
+ pwms = <&gpio0 24 4000>;
|
|
};
|
|
+
|
|
+ mvsw61xx {
|
|
diff --git a/target/linux/mvebu/patches-5.4/006-mvebu-Mangle-bootloader-s-kernel-arguments.patch b/target/linux/mvebu/patches-5.4/006-mvebu-Mangle-bootloader-s-kernel-arguments.patch
|
|
index 0cb9e996027..2f942ea3af6 100644
|
|
--- a/target/linux/mvebu/patches-5.4/006-mvebu-Mangle-bootloader-s-kernel-arguments.patch
|
|
+++ b/target/linux/mvebu/patches-5.4/006-mvebu-Mangle-bootloader-s-kernel-arguments.patch
|
|
@@ -28,7 +28,7 @@ Signed-off-by: Michael Gray <michael.gray@lantisproject.com>
|
|
|
|
--- a/arch/arm/Kconfig
|
|
+++ b/arch/arm/Kconfig
|
|
-@@ -1926,6 +1926,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
|
|
+@@ -1825,6 +1825,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
|
|
The command-line arguments provided by the boot loader will be
|
|
appended to the the device tree bootargs property.
|
|
|
|
@@ -145,7 +145,7 @@ Signed-off-by: Michael Gray <michael.gray@lantisproject.com>
|
|
}
|
|
*ptr = '\0';
|
|
|
|
-@@ -148,7 +218,9 @@ int atags_to_fdt(void *atag_list, void *
|
|
+@@ -166,7 +236,9 @@ int atags_to_fdt(void *atag_list, void *
|
|
else
|
|
setprop_string(fdt, "/chosen", "bootargs",
|
|
atag->u.cmdline.cmdline);
|
|
@@ -156,7 +156,7 @@ Signed-off-by: Michael Gray <michael.gray@lantisproject.com>
|
|
if (memcount >= sizeof(mem_reg_property)/4)
|
|
continue;
|
|
if (!atag->u.mem.size)
|
|
-@@ -187,6 +259,10 @@ int atags_to_fdt(void *atag_list, void *
|
|
+@@ -210,6 +282,10 @@ int atags_to_fdt(void *atag_list, void *
|
|
setprop(fdt, "/memory", "reg", mem_reg_property,
|
|
4 * memcount * memsize);
|
|
}
|
|
@@ -169,7 +169,7 @@ Signed-off-by: Michael Gray <michael.gray@lantisproject.com>
|
|
}
|
|
--- a/init/main.c
|
|
+++ b/init/main.c
|
|
-@@ -102,6 +102,10 @@
|
|
+@@ -103,6 +103,10 @@
|
|
#define CREATE_TRACE_POINTS
|
|
#include <trace/events/initcall.h>
|
|
|
|
@@ -180,7 +180,7 @@ Signed-off-by: Michael Gray <michael.gray@lantisproject.com>
|
|
static int kernel_init(void *);
|
|
|
|
extern void init_IRQ(void);
|
|
-@@ -591,6 +595,18 @@ asmlinkage __visible void __init start_k
|
|
+@@ -630,6 +634,18 @@ asmlinkage __visible void __init start_k
|
|
page_alloc_init();
|
|
|
|
pr_notice("Kernel command line: %s\n", boot_command_line);
|
|
diff --git a/target/linux/mvebu/patches-5.4/100-find_active_root.patch b/target/linux/mvebu/patches-5.4/100-find_active_root.patch
|
|
index f52a5108b85..854031b0d51 100644
|
|
--- a/target/linux/mvebu/patches-5.4/100-find_active_root.patch
|
|
+++ b/target/linux/mvebu/patches-5.4/100-find_active_root.patch
|
|
@@ -3,9 +3,9 @@ Dynamically rename the active partition to "ubi".
|
|
|
|
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
|
|
|
|
---- a/drivers/mtd/ofpart.c
|
|
-+++ b/drivers/mtd/ofpart.c
|
|
-@@ -25,6 +25,8 @@ static bool node_has_compatible(struct d
|
|
+--- a/drivers/mtd/parsers/ofpart.c
|
|
++++ b/drivers/mtd/parsers/ofpart.c
|
|
+@@ -21,6 +21,8 @@ static bool node_has_compatible(struct d
|
|
return of_get_property(pp, "compatible", NULL);
|
|
}
|
|
|
|
@@ -14,7 +14,7 @@ Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
|
|
static int parse_fixed_partitions(struct mtd_info *master,
|
|
const struct mtd_partition **pparts,
|
|
struct mtd_part_parser_data *data)
|
|
-@@ -33,6 +35,7 @@ static int parse_fixed_partitions(struct
|
|
+@@ -29,6 +31,7 @@ static int parse_fixed_partitions(struct
|
|
struct device_node *mtd_node;
|
|
struct device_node *ofpart_node;
|
|
const char *partname;
|
|
@@ -22,7 +22,7 @@ Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
|
|
struct device_node *pp;
|
|
int nr_parts, i, ret = 0;
|
|
bool dedicated = true;
|
|
-@@ -110,9 +113,13 @@ static int parse_fixed_partitions(struct
|
|
+@@ -106,9 +109,13 @@ static int parse_fixed_partitions(struct
|
|
parts[i].size = of_read_number(reg + a_cells, s_cells);
|
|
parts[i].of_node = pp;
|
|
|
|
@@ -39,7 +39,7 @@ Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
|
|
parts[i].name = partname;
|
|
|
|
if (of_get_property(pp, "read-only", &len))
|
|
-@@ -219,6 +226,18 @@ static int __init ofpart_parser_init(voi
|
|
+@@ -215,6 +222,18 @@ static int __init ofpart_parser_init(voi
|
|
return 0;
|
|
}
|
|
|
|
diff --git a/target/linux/mvebu/patches-5.4/210-clearfog_switch_node.patch b/target/linux/mvebu/patches-5.4/210-clearfog_switch_node.patch
|
|
index f9677a82f2e..d0e32e19df6 100644
|
|
--- a/target/linux/mvebu/patches-5.4/210-clearfog_switch_node.patch
|
|
+++ b/target/linux/mvebu/patches-5.4/210-clearfog_switch_node.patch
|
|
@@ -1,6 +1,6 @@
|
|
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
|
|
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
|
|
-@@ -88,6 +88,18 @@
|
|
+@@ -30,6 +30,18 @@
|
|
};
|
|
};
|
|
|
|
diff --git a/target/linux/mvebu/patches-5.4/220-disable-untested-dsa-boards.patch b/target/linux/mvebu/patches-5.4/220-disable-untested-dsa-boards.patch
|
|
index 9cc7a113f6c..029eb68e21d 100644
|
|
--- a/target/linux/mvebu/patches-5.4/220-disable-untested-dsa-boards.patch
|
|
+++ b/target/linux/mvebu/patches-5.4/220-disable-untested-dsa-boards.patch
|
|
@@ -10,7 +10,7 @@
|
|
#size-cells = <0>;
|
|
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
|
|
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
|
|
-@@ -161,6 +161,7 @@
|
|
+@@ -103,6 +103,7 @@
|
|
status = "okay";
|
|
|
|
switch@4 {
|
|
@@ -20,7 +20,7 @@
|
|
#size-cells = <0>;
|
|
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
|
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
|
-@@ -413,6 +413,7 @@
|
|
+@@ -366,6 +366,7 @@
|
|
status = "okay";
|
|
|
|
switch@0 {
|
|
diff --git a/target/linux/mvebu/patches-5.4/230-armada-xp-linksys-mamba-broken-idle.patch b/target/linux/mvebu/patches-5.4/230-armada-xp-linksys-mamba-broken-idle.patch
|
|
index 935c8fe0935..ee8786c0fce 100644
|
|
--- a/target/linux/mvebu/patches-5.4/230-armada-xp-linksys-mamba-broken-idle.patch
|
|
+++ b/target/linux/mvebu/patches-5.4/230-armada-xp-linksys-mamba-broken-idle.patch
|
|
@@ -1,6 +1,6 @@
|
|
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
|
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
|
|
-@@ -543,3 +543,7 @@
|
|
+@@ -496,3 +496,7 @@
|
|
};
|
|
};
|
|
};
|
|
diff --git a/target/linux/mvebu/patches-5.4/300-mvneta-tx-queue-workaround.patch b/target/linux/mvebu/patches-5.4/300-mvneta-tx-queue-workaround.patch
|
|
index 4a5ea361449..cc34ec0af7f 100644
|
|
--- a/target/linux/mvebu/patches-5.4/300-mvneta-tx-queue-workaround.patch
|
|
+++ b/target/linux/mvebu/patches-5.4/300-mvneta-tx-queue-workaround.patch
|
|
@@ -9,13 +9,12 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
|
|
---
|
|
--- a/drivers/net/ethernet/marvell/mvneta.c
|
|
+++ b/drivers/net/ethernet/marvell/mvneta.c
|
|
-@@ -4272,6 +4272,15 @@ static int mvneta_ethtool_set_eee(struct
|
|
+@@ -4333,6 +4333,14 @@ static int mvneta_ethtool_set_eee(struct
|
|
return phylink_ethtool_set_eee(pp->phylink, eee);
|
|
}
|
|
|
|
+static u16 mvneta_select_queue(struct net_device *dev, struct sk_buff *skb,
|
|
-+ struct net_device *sb_dev,
|
|
-+ select_queue_fallback_t fallback)
|
|
++ struct net_device *sb_dev)
|
|
+{
|
|
+ /* XXX: hardware queue scheduling is broken,
|
|
+ * use only one queue until it is fixed */
|
|
@@ -25,7 +24,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
|
|
static const struct net_device_ops mvneta_netdev_ops = {
|
|
.ndo_open = mvneta_open,
|
|
.ndo_stop = mvneta_stop,
|
|
-@@ -4282,6 +4291,7 @@ static const struct net_device_ops mvnet
|
|
+@@ -4343,6 +4351,7 @@ static const struct net_device_ops mvnet
|
|
.ndo_fix_features = mvneta_fix_features,
|
|
.ndo_get_stats64 = mvneta_get_stats64,
|
|
.ndo_do_ioctl = mvneta_ioctl,
|
|
diff --git a/target/linux/mvebu/patches-5.4/401-pci-mvebu-time-out-reset-on-link-up.patch b/target/linux/mvebu/patches-5.4/401-pci-mvebu-time-out-reset-on-link-up.patch
|
|
index 2bbb6471538..4058dc8ed58 100644
|
|
--- a/target/linux/mvebu/patches-5.4/401-pci-mvebu-time-out-reset-on-link-up.patch
|
|
+++ b/target/linux/mvebu/patches-5.4/401-pci-mvebu-time-out-reset-on-link-up.patch
|
|
@@ -13,7 +13,7 @@ Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
|
|
|
--- a/drivers/pci/controller/pci-mvebu.c
|
|
+++ b/drivers/pci/controller/pci-mvebu.c
|
|
-@@ -1112,6 +1112,7 @@ static int mvebu_pcie_powerup(struct mve
|
|
+@@ -928,6 +928,7 @@ static int mvebu_pcie_powerup(struct mve
|
|
|
|
if (port->reset_gpio) {
|
|
u32 reset_udelay = PCI_PM_D3COLD_WAIT * 1000;
|
|
@@ -21,7 +21,7 @@ Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
|
|
|
of_property_read_u32(port->dn, "reset-delay-us",
|
|
&reset_udelay);
|
|
-@@ -1119,7 +1120,13 @@ static int mvebu_pcie_powerup(struct mve
|
|
+@@ -935,7 +936,13 @@ static int mvebu_pcie_powerup(struct mve
|
|
udelay(100);
|
|
|
|
gpiod_set_value_cansleep(port->reset_gpio, 0);
|
|
@@ -36,7 +36,7 @@ Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
|
}
|
|
|
|
return 0;
|
|
-@@ -1283,15 +1290,16 @@ static int mvebu_pcie_probe(struct platf
|
|
+@@ -1099,15 +1106,16 @@ static int mvebu_pcie_probe(struct platf
|
|
if (!child)
|
|
continue;
|
|
|
|
diff --git a/target/linux/mvebu/patches-5.4/415-ARM-dts-armada388-clearfog-document-MPP-usage.patch b/target/linux/mvebu/patches-5.4/415-ARM-dts-armada388-clearfog-document-MPP-usage.patch
|
|
deleted file mode 100644
|
|
index d64bd8084ea..00000000000
|
|
--- a/target/linux/mvebu/patches-5.4/415-ARM-dts-armada388-clearfog-document-MPP-usage.patch
|
|
+++ /dev/null
|
|
@@ -1,124 +0,0 @@
|
|
-From 09a0122c74ec076e08512f1b00b7ccb8a450282f Mon Sep 17 00:00:00 2001
|
|
-From: Russell King <rmk+kernel@arm.linux.org.uk>
|
|
-Date: Tue, 29 Nov 2016 10:15:43 +0000
|
|
-Subject: ARM: dts: armada388-clearfog: document MPP usage
|
|
-
|
|
-Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
|
----
|
|
- arch/arm/boot/dts/armada-388-clearfog-base.dts | 51 ++++++++++++++++++++++++++
|
|
- arch/arm/boot/dts/armada-388-clearfog.dts | 50 +++++++++++++++++++++++++
|
|
- 2 files changed, 101 insertions(+)
|
|
-
|
|
---- a/arch/arm/boot/dts/armada-388-clearfog-base.dts
|
|
-+++ b/arch/arm/boot/dts/armada-388-clearfog-base.dts
|
|
-@@ -67,3 +67,54 @@
|
|
- marvell,function = "gpio";
|
|
- };
|
|
- };
|
|
-+
|
|
-+/*
|
|
-+MPP
|
|
-+18: pu gpio pca9655 int
|
|
-+19: gpio phy reset
|
|
-+20: pu gpio sd0 detect
|
|
-+21: sd0:cmd
|
|
-+22: pd gpio mikro int
|
|
-+23:
|
|
-+
|
|
-+24: ua1:rxd mikro rx
|
|
-+25: ua1:txd mikro tx
|
|
-+26: pu i2c1:sck
|
|
-+27: pu i2c1:sda
|
|
-+28: sd0:clk
|
|
-+29: pd gpio mikro rst
|
|
-+30:
|
|
-+31:
|
|
-+
|
|
-+32:
|
|
-+33:
|
|
-+34:
|
|
-+35:
|
|
-+36:
|
|
-+37: sd0:d3
|
|
-+38: sd0:d0
|
|
-+39: sd0:d1
|
|
-+
|
|
-+40: sd0:d2
|
|
-+41:
|
|
-+42:
|
|
-+43: spi1:cs2 mikro cs
|
|
-+44: gpio rear button sw3
|
|
-+45: ref:clk_out0 phy#0 clock
|
|
-+46: ref:clk_out1 phy#1 clock
|
|
-+47:
|
|
-+
|
|
-+48: gpio J18 spare gpio
|
|
-+49: gpio U10 I2C_IRQ(GNSS)
|
|
-+50: gpio board id?
|
|
-+51:
|
|
-+52:
|
|
-+53:
|
|
-+54: gpio mikro pwm
|
|
-+55:
|
|
-+
|
|
-+56: pu spi1:mosi mikro mosi
|
|
-+57: pd spi1:sck mikro sck
|
|
-+58: spi1:miso mikro miso
|
|
-+59:
|
|
-+*/
|
|
---- a/arch/arm/boot/dts/armada-388-clearfog.dts
|
|
-+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
|
|
-@@ -249,3 +249,53 @@
|
|
- */
|
|
- pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
|
|
- };
|
|
-+/*
|
|
-++#define A38x_CUSTOMER_BOARD_1_MPP16_23 0x00400011
|
|
-+MPP18: gpio ? (pca9655 int?)
|
|
-+MPP19: gpio ? (clkreq?)
|
|
-+MPP20: gpio ? (sd0 detect)
|
|
-+MPP21: sd0:cmd x sd0
|
|
-+MPP22: gpio x mikro int
|
|
-+MPP23: gpio x switch irq
|
|
-++#define A38x_CUSTOMER_BOARD_1_MPP24_31 0x22043333
|
|
-+MPP24: ua1:rxd x mikro rx
|
|
-+MPP25: ua1:txd x mikro tx
|
|
-+MPP26: i2c1:sck x mikro sck
|
|
-+MPP27: i2c1:sda x mikro sda
|
|
-+MPP28: sd0:clk x sd0
|
|
-+MPP29: gpio x mikro rst
|
|
-+MPP30: ge1:txd2 ? (config)
|
|
-+MPP31: ge1:txd3 ? (config)
|
|
-++#define A38x_CUSTOMER_BOARD_1_MPP32_39 0x44400002
|
|
-+MPP32: ge1:txctl ? (unused)
|
|
-+MPP33: gpio ? (pic_com0)
|
|
-+MPP34: gpio x rear button (pic_com1)
|
|
-+MPP35: gpio ? (pic_com2)
|
|
-+MPP36: gpio ? (unused)
|
|
-+MPP37: sd0:d3 x sd0
|
|
-+MPP38: sd0:d0 x sd0
|
|
-+MPP39: sd0:d1 x sd0
|
|
-++#define A38x_CUSTOMER_BOARD_1_MPP40_47 0x41144004
|
|
-+MPP40: sd0:d2 x sd0
|
|
-+MPP41: gpio x switch reset
|
|
-+MPP42: gpio ? sw1-1
|
|
-+MPP43: spi1:cs2 x mikro cs
|
|
-+MPP44: sata3:prsnt ? (unused)
|
|
-+MPP45: ref:clk_out0 ?
|
|
-+MPP46: ref:clk_out1 x switch clk
|
|
-+MPP47: 4 ? (unused)
|
|
-++#define A38x_CUSTOMER_BOARD_1_MPP48_55 0x40333333
|
|
-+MPP48: tdm:pclk
|
|
-+MPP49: tdm:fsync
|
|
-+MPP50: tdm:drx
|
|
-+MPP51: tdm:dtx
|
|
-+MPP52: tdm:int
|
|
-+MPP53: tdm:rst
|
|
-+MPP54: gpio ? (pwm)
|
|
-+MPP55: spi1:cs1 x slic
|
|
-++#define A38x_CUSTOMER_BOARD_1_MPP56_63 0x00004444
|
|
-+MPP56: spi1:mosi x mikro mosi
|
|
-+MPP57: spi1:sck x mikro sck
|
|
-+MPP58: spi1:miso x mikro miso
|
|
-+MPP59: spi1:cs0 x w25q32
|
|
-+*/
|
|
diff --git a/target/linux/mvebu/patches-5.4/513-arm64-dts-marvell-armada37xx-Add-emmc-sdio-pinctrl-d.patch b/target/linux/mvebu/patches-5.4/513-arm64-dts-marvell-armada37xx-Add-emmc-sdio-pinctrl-d.patch
|
|
deleted file mode 100644
|
|
index 880b0d92417..00000000000
|
|
--- a/target/linux/mvebu/patches-5.4/513-arm64-dts-marvell-armada37xx-Add-emmc-sdio-pinctrl-d.patch
|
|
+++ /dev/null
|
|
@@ -1,40 +0,0 @@
|
|
-From eefe328439642101774f0f5c4ea0dc6ba1cfb687 Mon Sep 17 00:00:00 2001
|
|
-From: Ding Tao <miyatsu@qq.com>
|
|
-Date: Fri, 26 Oct 2018 11:50:27 +0000
|
|
-Subject: [PATCH] arm64: dts: marvell: armada37xx: Add emmc/sdio pinctrl
|
|
- definition
|
|
-
|
|
-Add emmc/sdio pinctrl definition for marvell armada37xx SoCs.
|
|
-
|
|
-Signed-off-by: Ding Tao <miyatsu@qq.com>
|
|
-Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
|
|
----
|
|
- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 10 ++++++++++
|
|
- 1 file changed, 10 insertions(+)
|
|
-
|
|
---- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
|
|
-+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
|
|
-@@ -221,6 +221,11 @@
|
|
- groups = "uart2";
|
|
- function = "uart";
|
|
- };
|
|
-+
|
|
-+ mmc_pins: mmc-pins {
|
|
-+ groups = "emmc_nb";
|
|
-+ function = "emmc";
|
|
-+ };
|
|
- };
|
|
-
|
|
- nb_pm: syscon@14000 {
|
|
-@@ -253,6 +258,11 @@
|
|
- function = "mii";
|
|
- };
|
|
-
|
|
-+ sdio_pins: sdio-pins {
|
|
-+ groups = "sdio_sb";
|
|
-+ function = "sdio";
|
|
-+ };
|
|
-+
|
|
- };
|
|
-
|
|
- eth0: ethernet@30000 {
|
|
diff --git a/target/linux/mvebu/patches-5.4/514-arm64-dts-marvell-armada-37xx-Enable-emmc-on-espress.patch b/target/linux/mvebu/patches-5.4/514-arm64-dts-marvell-armada-37xx-Enable-emmc-on-espress.patch
|
|
deleted file mode 100644
|
|
index 77af3d1219d..00000000000
|
|
--- a/target/linux/mvebu/patches-5.4/514-arm64-dts-marvell-armada-37xx-Enable-emmc-on-espress.patch
|
|
+++ /dev/null
|
|
@@ -1,49 +0,0 @@
|
|
-From 43ebc7c1b3ed8198b9acf3019eca16e722f7331c Mon Sep 17 00:00:00 2001
|
|
-From: Ding Tao <miyatsu@qq.com>
|
|
-Date: Fri, 26 Oct 2018 11:50:28 +0000
|
|
-Subject: [PATCH] arm64: dts: marvell: armada-37xx: Enable emmc on espressobin
|
|
-
|
|
-The ESPRESSObin board has a emmc interface available on U11: declare it
|
|
-and let the bootloader enable it if the emmc is present.
|
|
-
|
|
-[gregory.clement@bootlin.com: disable the emmc by default]
|
|
-Signed-off-by: Ding Tao <miyatsu@qq.com>
|
|
-Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
|
|
----
|
|
- .../dts/marvell/armada-3720-espressobin.dts | 22 +++++++++++++++++++
|
|
- 1 file changed, 22 insertions(+)
|
|
-
|
|
---- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
|
-+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
|
-@@ -60,9 +60,31 @@
|
|
- cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
|
|
- marvell,pad-type = "sd";
|
|
- vqmmc-supply = <&vcc_sd_reg1>;
|
|
-+
|
|
-+ pinctrl-names = "default";
|
|
-+ pinctrl-0 = <&sdio_pins>;
|
|
- status = "okay";
|
|
- };
|
|
-
|
|
-+/* U11 */
|
|
-+&sdhci0 {
|
|
-+ non-removable;
|
|
-+ bus-width = <8>;
|
|
-+ mmc-ddr-1_8v;
|
|
-+ mmc-hs400-1_8v;
|
|
-+ marvell,xenon-emmc;
|
|
-+ marvell,xenon-tun-count = <9>;
|
|
-+ marvell,pad-type = "fixed-1-8v";
|
|
-+
|
|
-+ pinctrl-names = "default";
|
|
-+ pinctrl-0 = <&mmc_pins>;
|
|
-+/*
|
|
-+ * This eMMC is not populated on all boards, so disable it by
|
|
-+ * default and let the bootloader enable it, if it is present
|
|
-+ */
|
|
-+ status = "disabled";
|
|
-+};
|
|
-+
|
|
- &spi0 {
|
|
- status = "okay";
|
|
-
|
|
diff --git a/target/linux/mvebu/patches-5.4/521-arm64-dts-armada-3720-espressobin-correct-spi-node.patch b/target/linux/mvebu/patches-5.4/521-arm64-dts-armada-3720-espressobin-correct-spi-node.patch
|
|
deleted file mode 100644
|
|
index 0f39b2a3c2c..00000000000
|
|
--- a/target/linux/mvebu/patches-5.4/521-arm64-dts-armada-3720-espressobin-correct-spi-node.patch
|
|
+++ /dev/null
|
|
@@ -1,58 +0,0 @@
|
|
-From 3217cdfe8a3eae76fafbebbe407be5985a7fd4c2 Mon Sep 17 00:00:00 2001
|
|
-From: Tomasz Maciej Nowak <tmn505@gmail.com>
|
|
-Date: Mon, 31 Dec 2018 14:18:50 +0100
|
|
-Subject: [PATCH] arm64: dts: armada-3720-espressobin: correct spi node
|
|
-
|
|
-The manufacturer of this board, ships it with various SPI NOR chips and
|
|
-increments U-Boot bootloader version along the time. There is no way to
|
|
-tell which is placed on the board since no revision bump takes place.
|
|
-This creates two issues.
|
|
-
|
|
-The first, cosmetic. Since the SPI chip may differ, there's message on
|
|
-boot stating that kernel expected w25q32dw and found different one. To
|
|
-correct this, remove optional device-specific compatible string. Being
|
|
-here lets replace bogus "spi-flash" string with proper one.
|
|
-
|
|
-The second is linked to partitions layout, it changed after commit [1]
|
|
-in Marvells downstream U-Boot fork, shifting environment location to the
|
|
-end of boot device. Since the new boards can have U-Boot with this
|
|
-change it can lead to improper results writing or reading from these
|
|
-partitions. We can't tell if users will update bootloader to recent
|
|
-version, so let's drop current layout.
|
|
-
|
|
-1. https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/81e7251252aefe1a6b829ed05f3586320cb45372
|
|
-
|
|
-Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
|
|
----
|
|
- .../dts/marvell/armada-3720-espressobin.dts | 18 +-----------------
|
|
- 1 file changed, 1 insertion(+), 17 deletions(-)
|
|
-
|
|
---- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
|
-+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
|
-@@ -90,25 +90,9 @@
|
|
-
|
|
- flash@0 {
|
|
- reg = <0>;
|
|
-- compatible = "winbond,w25q32dw", "jedec,spi-flash";
|
|
-+ compatible = "jedec,spi-nor";
|
|
- spi-max-frequency = <104000000>;
|
|
- m25p,fast-read;
|
|
--
|
|
-- partitions {
|
|
-- compatible = "fixed-partitions";
|
|
-- #address-cells = <1>;
|
|
-- #size-cells = <1>;
|
|
--
|
|
-- partition@0 {
|
|
-- label = "uboot";
|
|
-- reg = <0 0x180000>;
|
|
-- };
|
|
--
|
|
-- partition@180000 {
|
|
-- label = "ubootenv";
|
|
-- reg = <0x180000 0x10000>;
|
|
-- };
|
|
-- };
|
|
- };
|
|
- };
|
|
-
|
|
diff --git a/target/linux/mvebu/patches-5.4/522-arm64-dts-marvell-armada-3720-espressobin-add-ports-.patch b/target/linux/mvebu/patches-5.4/522-arm64-dts-marvell-armada-3720-espressobin-add-ports-.patch
|
|
index cea0d1db44f..1a608f2b6ac 100644
|
|
--- a/target/linux/mvebu/patches-5.4/522-arm64-dts-marvell-armada-3720-espressobin-add-ports-.patch
|
|
+++ b/target/linux/mvebu/patches-5.4/522-arm64-dts-marvell-armada-3720-espressobin-add-ports-.patch
|
|
@@ -15,7 +15,7 @@ Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
|
|
|
|
--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
|
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
|
-@@ -132,7 +132,7 @@
|
|
+@@ -137,7 +137,7 @@
|
|
|
|
dsa,member = <0 0>;
|
|
|
|
diff --git a/target/linux/mvebu/patches-5.4/523-Revert-PCI-aardvark-Convert-to-use-pci_host_probe.patch b/target/linux/mvebu/patches-5.4/523-Revert-PCI-aardvark-Convert-to-use-pci_host_probe.patch
|
|
index 3fd561db3a6..e1318e825ad 100644
|
|
--- a/target/linux/mvebu/patches-5.4/523-Revert-PCI-aardvark-Convert-to-use-pci_host_probe.patch
|
|
+++ b/target/linux/mvebu/patches-5.4/523-Revert-PCI-aardvark-Convert-to-use-pci_host_probe.patch
|
|
@@ -10,7 +10,7 @@ This reverts commit c8e144f8ab00e6c4a070a932ef9c57db09aa41cf.
|
|
|
|
--- a/drivers/pci/controller/pci-aardvark.c
|
|
+++ b/drivers/pci/controller/pci-aardvark.c
|
|
-@@ -843,6 +843,7 @@ static int advk_pcie_probe(struct platfo
|
|
+@@ -999,6 +999,7 @@ static int advk_pcie_probe(struct platfo
|
|
struct device *dev = &pdev->dev;
|
|
struct advk_pcie *pcie;
|
|
struct resource *res;
|
|
@@ -18,7 +18,7 @@ This reverts commit c8e144f8ab00e6c4a070a932ef9c57db09aa41cf.
|
|
struct pci_host_bridge *bridge;
|
|
int ret, irq;
|
|
|
|
-@@ -896,13 +897,22 @@ static int advk_pcie_probe(struct platfo
|
|
+@@ -1054,13 +1055,22 @@ static int advk_pcie_probe(struct platfo
|
|
bridge->map_irq = of_irq_parse_and_map_pci;
|
|
bridge->swizzle_irq = pci_common_swizzle;
|
|
|
|
diff --git a/target/linux/mvebu/patches-5.4/524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch b/target/linux/mvebu/patches-5.4/524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch
|
|
index 204d6e2aec4..c6cfe3783c5 100644
|
|
--- a/target/linux/mvebu/patches-5.4/524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch
|
|
+++ b/target/linux/mvebu/patches-5.4/524-PCI-aardvark-set-host-and-device-to-the-same-MAX-payload-size.patch
|
|
@@ -45,7 +45,7 @@ Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
|
|
|
--- a/drivers/pci/controller/pci-aardvark.c
|
|
+++ b/drivers/pci/controller/pci-aardvark.c
|
|
-@@ -29,9 +29,11 @@
|
|
+@@ -33,9 +33,11 @@
|
|
#define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8
|
|
#define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4)
|
|
#define PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT 5
|
|
@@ -57,7 +57,7 @@ Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
|
#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
|
|
#define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
|
|
#define PCIE_CORE_LINK_TRAINING BIT(5)
|
|
-@@ -253,7 +255,8 @@ static void advk_pcie_setup_hw(struct ad
|
|
+@@ -276,7 +278,8 @@ static void advk_pcie_setup_hw(struct ad
|
|
|
|
/* Set PCIe Device Control and Status 1 PF0 register */
|
|
reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
|
|
@@ -67,7 +67,7 @@ Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
|
PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
|
|
(PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<
|
|
PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);
|
|
-@@ -838,6 +841,58 @@ out_release_res:
|
|
+@@ -994,6 +997,58 @@ out_release_res:
|
|
return err;
|
|
}
|
|
|
|
@@ -126,7 +126,7 @@ Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
|
static int advk_pcie_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
-@@ -912,6 +967,9 @@ static int advk_pcie_probe(struct platfo
|
|
+@@ -1070,6 +1125,9 @@ static int advk_pcie_probe(struct platfo
|
|
list_for_each_entry(child, &bus->children, node)
|
|
pcie_bus_configure_settings(child);
|
|
|
|
diff --git a/target/linux/mvebu/patches-5.4/526-PCI-aardvark-disable-LOS-state-by-default.patch b/target/linux/mvebu/patches-5.4/526-PCI-aardvark-disable-LOS-state-by-default.patch
|
|
index b6fcec81f8f..f865965ed47 100644
|
|
--- a/target/linux/mvebu/patches-5.4/526-PCI-aardvark-disable-LOS-state-by-default.patch
|
|
+++ b/target/linux/mvebu/patches-5.4/526-PCI-aardvark-disable-LOS-state-by-default.patch
|
|
@@ -43,7 +43,7 @@ Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
|
|
|
--- a/drivers/pci/controller/pci-aardvark.c
|
|
+++ b/drivers/pci/controller/pci-aardvark.c
|
|
-@@ -324,8 +324,7 @@ static void advk_pcie_setup_hw(struct ad
|
|
+@@ -347,8 +347,7 @@ static void advk_pcie_setup_hw(struct ad
|
|
|
|
advk_pcie_wait_for_link(pcie);
|
|
|
|
diff --git a/target/linux/mvebu/patches-5.4/527-PCI-aardvark-allow-to-specify-link-capability.patch b/target/linux/mvebu/patches-5.4/527-PCI-aardvark-allow-to-specify-link-capability.patch
|
|
index 0ac34761473..739292c1bfd 100644
|
|
--- a/target/linux/mvebu/patches-5.4/527-PCI-aardvark-allow-to-specify-link-capability.patch
|
|
+++ b/target/linux/mvebu/patches-5.4/527-PCI-aardvark-allow-to-specify-link-capability.patch
|
|
@@ -14,7 +14,7 @@ Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
|
|
|
|
--- a/drivers/pci/controller/pci-aardvark.c
|
|
+++ b/drivers/pci/controller/pci-aardvark.c
|
|
-@@ -233,6 +233,8 @@ static int advk_pcie_wait_for_link(struc
|
|
+@@ -256,6 +256,8 @@ static void advk_pcie_wait_for_retrain(s
|
|
|
|
static void advk_pcie_setup_hw(struct advk_pcie *pcie)
|
|
{
|
|
@@ -23,7 +23,7 @@ Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
|
|
u32 reg;
|
|
|
|
/* Set to Direct mode */
|
|
-@@ -267,10 +269,15 @@ static void advk_pcie_setup_hw(struct ad
|
|
+@@ -290,10 +292,15 @@ static void advk_pcie_setup_hw(struct ad
|
|
PCIE_CORE_CTRL2_TD_ENABLE;
|
|
advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
|
|
|
|
diff --git a/target/linux/mvebu/patches-5.4/528-arm64-dts-armada-3720-espressobin-set-max-link-to-ge.patch b/target/linux/mvebu/patches-5.4/528-arm64-dts-armada-3720-espressobin-set-max-link-to-ge.patch
|
|
index 88080d64caa..d3a8f58f18f 100644
|
|
--- a/target/linux/mvebu/patches-5.4/528-arm64-dts-armada-3720-espressobin-set-max-link-to-ge.patch
|
|
+++ b/target/linux/mvebu/patches-5.4/528-arm64-dts-armada-3720-espressobin-set-max-link-to-ge.patch
|
|
@@ -62,10 +62,10 @@ Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
|
|
|
|
--- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
|
+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
|
|
-@@ -46,6 +46,8 @@
|
|
- /* J9 */
|
|
- &pcie0 {
|
|
- status = "okay";
|
|
+@@ -49,6 +49,8 @@
|
|
+ phys = <&comphy1 0>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
|
|
+
|
|
+ max-link-speed = <1>;
|
|
};
|
|
diff --git a/target/linux/mvebu/patches-5.4/531-net-mvneta-Add-support-for-2500Mbps-SGMII.patch b/target/linux/mvebu/patches-5.4/531-net-mvneta-Add-support-for-2500Mbps-SGMII.patch
|
|
deleted file mode 100644
|
|
index a5553a3e96c..00000000000
|
|
--- a/target/linux/mvebu/patches-5.4/531-net-mvneta-Add-support-for-2500Mbps-SGMII.patch
|
|
+++ /dev/null
|
|
@@ -1,104 +0,0 @@
|
|
-From da58a931f248f423f917c3a0b3c94303aa30a738 Mon Sep 17 00:00:00 2001
|
|
-From: Maxime Chevallier <maxime.chevallier@bootlin.com>
|
|
-Date: Tue, 25 Sep 2018 15:59:39 +0200
|
|
-Subject: [PATCH] net: mvneta: Add support for 2500Mbps SGMII
|
|
-
|
|
-The mvneta controller can handle speeds up to 2500Mbps on the SGMII
|
|
-interface. This relies on serdes configuration, the lane must be
|
|
-configured at 3.125Gbps and we can't use in-band autoneg at that speed.
|
|
-
|
|
-The main issue when supporting that speed on this particular controller
|
|
-is that the link partner can send ethernet frames with a shortened
|
|
-preamble, which if not explicitly enabled in the controller will cause
|
|
-unexpected behaviours.
|
|
-
|
|
-This was tested on Armada 385, with the comphy configuration done in
|
|
-bootloader.
|
|
-
|
|
-Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
|
|
-Signed-off-by: David S. Miller <davem@davemloft.net>
|
|
----
|
|
- drivers/net/ethernet/marvell/mvneta.c | 27 +++++++++++++++++++++++----
|
|
- 1 file changed, 23 insertions(+), 4 deletions(-)
|
|
-
|
|
---- a/drivers/net/ethernet/marvell/mvneta.c
|
|
-+++ b/drivers/net/ethernet/marvell/mvneta.c
|
|
-@@ -221,6 +221,8 @@
|
|
- #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11)
|
|
- #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
|
|
- #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
|
|
-+#define MVNETA_GMAC_CTRL_4 0x2c90
|
|
-+#define MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE BIT(1)
|
|
- #define MVNETA_MIB_COUNTERS_BASE 0x3000
|
|
- #define MVNETA_MIB_LATE_COLLISION 0x7c
|
|
- #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
|
|
-@@ -3359,6 +3361,7 @@ static void mvneta_validate(struct net_d
|
|
- if (state->interface != PHY_INTERFACE_MODE_NA &&
|
|
- state->interface != PHY_INTERFACE_MODE_QSGMII &&
|
|
- state->interface != PHY_INTERFACE_MODE_SGMII &&
|
|
-+ state->interface != PHY_INTERFACE_MODE_2500BASEX &&
|
|
- !phy_interface_mode_is_8023z(state->interface) &&
|
|
- !phy_interface_mode_is_rgmii(state->interface)) {
|
|
- bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
|
|
-@@ -3371,9 +3374,15 @@ static void mvneta_validate(struct net_d
|
|
-
|
|
- /* Asymmetric pause is unsupported */
|
|
- phylink_set(mask, Pause);
|
|
-- /* Half-duplex at speeds higher than 100Mbit is unsupported */
|
|
-- phylink_set(mask, 1000baseT_Full);
|
|
-- phylink_set(mask, 1000baseX_Full);
|
|
-+
|
|
-+ /* We cannot use 1Gbps when using the 2.5G interface. */
|
|
-+ if (state->interface == PHY_INTERFACE_MODE_2500BASEX) {
|
|
-+ phylink_set(mask, 2500baseT_Full);
|
|
-+ phylink_set(mask, 2500baseX_Full);
|
|
-+ } else {
|
|
-+ phylink_set(mask, 1000baseT_Full);
|
|
-+ phylink_set(mask, 1000baseX_Full);
|
|
-+ }
|
|
-
|
|
- if (!phy_interface_mode_is_8023z(state->interface)) {
|
|
- /* 10M and 100M are only supported in non-802.3z mode */
|
|
-@@ -3434,12 +3443,14 @@ static void mvneta_mac_config(struct net
|
|
- struct mvneta_port *pp = netdev_priv(ndev);
|
|
- u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
|
|
- u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
|
|
-+ u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4);
|
|
- u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
|
|
- u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
|
|
-
|
|
- new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X;
|
|
- new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE |
|
|
- MVNETA_GMAC2_PORT_RESET);
|
|
-+ new_ctrl4 = gmac_ctrl4 & ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE);
|
|
- new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
|
|
- new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE |
|
|
- MVNETA_GMAC_INBAND_RESTART_AN |
|
|
-@@ -3472,7 +3483,7 @@ static void mvneta_mac_config(struct net
|
|
- if (state->duplex)
|
|
- new_an |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
|
|
-
|
|
-- if (state->speed == SPEED_1000)
|
|
-+ if (state->speed == SPEED_1000 || state->speed == SPEED_2500)
|
|
- new_an |= MVNETA_GMAC_CONFIG_GMII_SPEED;
|
|
- else if (state->speed == SPEED_100)
|
|
- new_an |= MVNETA_GMAC_CONFIG_MII_SPEED;
|
|
-@@ -3511,10 +3522,18 @@ static void mvneta_mac_config(struct net
|
|
- MVNETA_GMAC_FORCE_LINK_DOWN);
|
|
- }
|
|
-
|
|
-+ /* When at 2.5G, the link partner can send frames with shortened
|
|
-+ * preambles.
|
|
-+ */
|
|
-+ if (state->speed == SPEED_2500)
|
|
-+ new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE;
|
|
-+
|
|
- if (new_ctrl0 != gmac_ctrl0)
|
|
- mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0);
|
|
- if (new_ctrl2 != gmac_ctrl2)
|
|
- mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2);
|
|
-+ if (new_ctrl4 != gmac_ctrl4)
|
|
-+ mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4);
|
|
- if (new_clk != gmac_clk)
|
|
- mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk);
|
|
- if (new_an != gmac_an)
|
|
diff --git a/target/linux/mvebu/patches-5.4/532-net-mvneta-correct-typo.patch b/target/linux/mvebu/patches-5.4/532-net-mvneta-correct-typo.patch
|
|
deleted file mode 100644
|
|
index b6e16c54a45..00000000000
|
|
--- a/target/linux/mvebu/patches-5.4/532-net-mvneta-correct-typo.patch
|
|
+++ /dev/null
|
|
@@ -1,33 +0,0 @@
|
|
-From fbd1d5245372e48b494120a30fe0b34b304576c4 Mon Sep 17 00:00:00 2001
|
|
-From: Alexandre Belloni <alexandre.belloni@bootlin.com>
|
|
-Date: Fri, 9 Nov 2018 17:37:20 +0100
|
|
-Subject: [PATCH] net: mvneta: correct typo
|
|
-
|
|
-The reserved variable should be named reserved1.
|
|
-
|
|
-Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
|
|
-Signed-off-by: David S. Miller <davem@davemloft.net>
|
|
----
|
|
- drivers/net/ethernet/marvell/mvneta.c | 4 ++--
|
|
- 1 file changed, 2 insertions(+), 2 deletions(-)
|
|
-
|
|
---- a/drivers/net/ethernet/marvell/mvneta.c
|
|
-+++ b/drivers/net/ethernet/marvell/mvneta.c
|
|
-@@ -495,7 +495,7 @@ struct mvneta_port {
|
|
- #if defined(__LITTLE_ENDIAN)
|
|
- struct mvneta_tx_desc {
|
|
- u32 command; /* Options used by HW for packet transmitting.*/
|
|
-- u16 reserverd1; /* csum_l4 (for future use) */
|
|
-+ u16 reserved1; /* csum_l4 (for future use) */
|
|
- u16 data_size; /* Data size of transmitted packet in bytes */
|
|
- u32 buf_phys_addr; /* Physical addr of transmitted buffer */
|
|
- u32 reserved2; /* hw_cmd - (for future use, PMT) */
|
|
-@@ -520,7 +520,7 @@ struct mvneta_rx_desc {
|
|
- #else
|
|
- struct mvneta_tx_desc {
|
|
- u16 data_size; /* Data size of transmitted packet in bytes */
|
|
-- u16 reserverd1; /* csum_l4 (for future use) */
|
|
-+ u16 reserved1; /* csum_l4 (for future use) */
|
|
- u32 command; /* Options used by HW for packet transmitting.*/
|
|
- u32 reserved2; /* hw_cmd - (for future use, PMT) */
|
|
- u32 buf_phys_addr; /* Physical addr of transmitted buffer */
|
|
diff --git a/target/linux/mvebu/patches-5.4/533-net-mvneta-Dont-advertise-2.5G-modes.patch b/target/linux/mvebu/patches-5.4/533-net-mvneta-Dont-advertise-2.5G-modes.patch
|
|
deleted file mode 100644
|
|
index 01b101283cd..00000000000
|
|
--- a/target/linux/mvebu/patches-5.4/533-net-mvneta-Dont-advertise-2.5G-modes.patch
|
|
+++ /dev/null
|
|
@@ -1,55 +0,0 @@
|
|
-From 83e65df6dfece9eb588735459428f221eb930c0c Mon Sep 17 00:00:00 2001
|
|
-From: Maxime Chevallier <maxime.chevallier@bootlin.com>
|
|
-Date: Fri, 9 Nov 2018 09:17:33 +0100
|
|
-Subject: [PATCH] net: mvneta: Don't advertise 2.5G modes
|
|
-
|
|
-Using 2.5G speed relies on the SerDes lanes being configured
|
|
-accordingly. The lanes have to be reconfigured to switch between
|
|
-1G and 2.5G, and for now only the bootloader does this configuration.
|
|
-
|
|
-In the case we add a Comphy driver to handle switching the lanes
|
|
-dynamically, it's better for now to stick with supporting only 1G and
|
|
-add advertisement for 2.5G once we really are capable of handling both
|
|
-speeds without problem.
|
|
-
|
|
-Since the interface mode is initialy taken from the DT, we want to make
|
|
-sure that adding comphy support won't break boards that don't update
|
|
-their dtb.
|
|
-
|
|
-Fixes: da58a931f248 ("net: mvneta: Add support for 2500Mbps SGMII")
|
|
-Reported-by: Andrew Lunn <andrew@lunn.ch>
|
|
-Reported-by: Russell King <linux@armlinux.org.uk>
|
|
-Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
|
|
-Signed-off-by: David S. Miller <davem@davemloft.net>
|
|
----
|
|
- drivers/net/ethernet/marvell/mvneta.c | 12 +++---------
|
|
- 1 file changed, 3 insertions(+), 9 deletions(-)
|
|
-
|
|
---- a/drivers/net/ethernet/marvell/mvneta.c
|
|
-+++ b/drivers/net/ethernet/marvell/mvneta.c
|
|
-@@ -3361,7 +3361,6 @@ static void mvneta_validate(struct net_d
|
|
- if (state->interface != PHY_INTERFACE_MODE_NA &&
|
|
- state->interface != PHY_INTERFACE_MODE_QSGMII &&
|
|
- state->interface != PHY_INTERFACE_MODE_SGMII &&
|
|
-- state->interface != PHY_INTERFACE_MODE_2500BASEX &&
|
|
- !phy_interface_mode_is_8023z(state->interface) &&
|
|
- !phy_interface_mode_is_rgmii(state->interface)) {
|
|
- bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
|
|
-@@ -3375,14 +3374,9 @@ static void mvneta_validate(struct net_d
|
|
- /* Asymmetric pause is unsupported */
|
|
- phylink_set(mask, Pause);
|
|
-
|
|
-- /* We cannot use 1Gbps when using the 2.5G interface. */
|
|
-- if (state->interface == PHY_INTERFACE_MODE_2500BASEX) {
|
|
-- phylink_set(mask, 2500baseT_Full);
|
|
-- phylink_set(mask, 2500baseX_Full);
|
|
-- } else {
|
|
-- phylink_set(mask, 1000baseT_Full);
|
|
-- phylink_set(mask, 1000baseX_Full);
|
|
-- }
|
|
-+ /* Half-duplex at speeds higher than 100Mbit is unsupported */
|
|
-+ phylink_set(mask, 1000baseT_Full);
|
|
-+ phylink_set(mask, 1000baseX_Full);
|
|
-
|
|
- if (!phy_interface_mode_is_8023z(state->interface)) {
|
|
- /* 10M and 100M are only supported in non-802.3z mode */
|
|
diff --git a/target/linux/mvebu/patches-5.4/534-net-mvneta-remove-redundant-check-for.patch b/target/linux/mvebu/patches-5.4/534-net-mvneta-remove-redundant-check-for.patch
|
|
deleted file mode 100644
|
|
index fd774e08398..00000000000
|
|
--- a/target/linux/mvebu/patches-5.4/534-net-mvneta-remove-redundant-check-for.patch
|
|
+++ /dev/null
|
|
@@ -1,30 +0,0 @@
|
|
-From e4a3e9ff5ba9f6b67595ec2768ed4be2054c2aa5 Mon Sep 17 00:00:00 2001
|
|
-From: YueHaibing <yuehaibing@huawei.com>
|
|
-Date: Thu, 22 Nov 2018 14:42:00 +0800
|
|
-Subject: [PATCH] net: mvneta: remove redundant check for
|
|
- eee->tx_lpi_timer < 0
|
|
-
|
|
-fixes the smatch warning:
|
|
-
|
|
-drivers/net/ethernet/marvell/mvneta.c:4252 mvneta_ethtool_set_eee() warn:
|
|
- unsigned 'eee->tx_lpi_timer' is never less than zero.
|
|
-
|
|
-Signed-off-by: YueHaibing <yuehaibing@huawei.com>
|
|
-Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
|
|
-Signed-off-by: David S. Miller <davem@davemloft.net>
|
|
----
|
|
- drivers/net/ethernet/marvell/mvneta.c | 3 +--
|
|
- 1 file changed, 1 insertion(+), 2 deletions(-)
|
|
-
|
|
---- a/drivers/net/ethernet/marvell/mvneta.c
|
|
-+++ b/drivers/net/ethernet/marvell/mvneta.c
|
|
-@@ -4268,8 +4268,7 @@ static int mvneta_ethtool_set_eee(struct
|
|
-
|
|
- /* The Armada 37x documents do not give limits for this other than
|
|
- * it being an 8-bit register. */
|
|
-- if (eee->tx_lpi_enabled &&
|
|
-- (eee->tx_lpi_timer < 0 || eee->tx_lpi_timer > 255))
|
|
-+ if (eee->tx_lpi_enabled && eee->tx_lpi_timer > 255)
|
|
- return -EINVAL;
|
|
-
|
|
- lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0);
|
|
diff --git a/target/linux/mvebu/patches-5.4/535-net-marvell-neta-add-comphy-support.patch b/target/linux/mvebu/patches-5.4/535-net-marvell-neta-add-comphy-support.patch
|
|
deleted file mode 100644
|
|
index 272beb6950f..00000000000
|
|
--- a/target/linux/mvebu/patches-5.4/535-net-marvell-neta-add-comphy-support.patch
|
|
+++ /dev/null
|
|
@@ -1,159 +0,0 @@
|
|
-From a10c1c8191e04c21769656c2ca8e1c69a6218954 Mon Sep 17 00:00:00 2001
|
|
-From: Russell King <rmk+kernel@armlinux.org.uk>
|
|
-Date: Thu, 7 Feb 2019 16:19:26 +0000
|
|
-Subject: [PATCH] net: marvell: neta: add comphy support
|
|
-
|
|
-Add support for the common phy binding, so that we can reconfigure the
|
|
-comphy according to the desired ethernet speed. This will allow us to
|
|
-support 1000base-X and 2500base-X SFPs dynamically on SolidRun Clearfog.
|
|
-
|
|
-Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
|
|
-Signed-off-by: David S. Miller <davem@davemloft.net>
|
|
----
|
|
- drivers/net/ethernet/marvell/mvneta.c | 45 +++++++++++++++++++++++++++++++----
|
|
- 1 file changed, 41 insertions(+), 4 deletions(-)
|
|
-
|
|
---- a/drivers/net/ethernet/marvell/mvneta.c
|
|
-+++ b/drivers/net/ethernet/marvell/mvneta.c
|
|
-@@ -27,6 +27,7 @@
|
|
- #include <linux/of_irq.h>
|
|
- #include <linux/of_mdio.h>
|
|
- #include <linux/of_net.h>
|
|
-+#include <linux/phy/phy.h>
|
|
- #include <linux/phy.h>
|
|
- #include <linux/phylink.h>
|
|
- #include <linux/platform_device.h>
|
|
-@@ -438,6 +439,7 @@ struct mvneta_port {
|
|
- struct device_node *dn;
|
|
- unsigned int tx_csum_limit;
|
|
- struct phylink *phylink;
|
|
-+ struct phy *comphy;
|
|
-
|
|
- struct mvneta_bm *bm_priv;
|
|
- struct mvneta_bm_pool *pool_long;
|
|
-@@ -3168,6 +3170,8 @@ static void mvneta_start_dev(struct mvne
|
|
- {
|
|
- int cpu;
|
|
-
|
|
-+ WARN_ON(phy_power_on(pp->comphy));
|
|
-+
|
|
- mvneta_max_rx_size_set(pp, pp->pkt_size);
|
|
- mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
|
|
-
|
|
-@@ -3230,6 +3234,8 @@ static void mvneta_stop_dev(struct mvnet
|
|
-
|
|
- mvneta_tx_reset(pp);
|
|
- mvneta_rx_reset(pp);
|
|
-+
|
|
-+ WARN_ON(phy_power_off(pp->comphy));
|
|
- }
|
|
-
|
|
- static void mvneta_percpu_enable(void *arg)
|
|
-@@ -3355,6 +3361,7 @@ static int mvneta_set_mac_addr(struct ne
|
|
- static void mvneta_validate(struct net_device *ndev, unsigned long *supported,
|
|
- struct phylink_link_state *state)
|
|
- {
|
|
-+ struct mvneta_port *pp = netdev_priv(ndev);
|
|
- __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
|
|
-
|
|
- /* We only support QSGMII, SGMII, 802.3z and RGMII modes */
|
|
-@@ -3375,8 +3382,13 @@ static void mvneta_validate(struct net_d
|
|
- phylink_set(mask, Pause);
|
|
-
|
|
- /* Half-duplex at speeds higher than 100Mbit is unsupported */
|
|
-- phylink_set(mask, 1000baseT_Full);
|
|
-- phylink_set(mask, 1000baseX_Full);
|
|
-+ if (pp->comphy || state->interface != PHY_INTERFACE_MODE_2500BASEX) {
|
|
-+ phylink_set(mask, 1000baseT_Full);
|
|
-+ phylink_set(mask, 1000baseX_Full);
|
|
-+ }
|
|
-+ if (pp->comphy || state->interface == PHY_INTERFACE_MODE_2500BASEX) {
|
|
-+ phylink_set(mask, 2500baseX_Full);
|
|
-+ }
|
|
-
|
|
- if (!phy_interface_mode_is_8023z(state->interface)) {
|
|
- /* 10M and 100M are only supported in non-802.3z mode */
|
|
-@@ -3390,6 +3402,11 @@ static void mvneta_validate(struct net_d
|
|
- __ETHTOOL_LINK_MODE_MASK_NBITS);
|
|
- bitmap_and(state->advertising, state->advertising, mask,
|
|
- __ETHTOOL_LINK_MODE_MASK_NBITS);
|
|
-+
|
|
-+ /* We can only operate at 2500BaseX or 1000BaseX. If requested
|
|
-+ * to advertise both, only report advertising at 2500BaseX.
|
|
-+ */
|
|
-+ phylink_helper_basex_speed(state);
|
|
- }
|
|
-
|
|
- static int mvneta_mac_link_state(struct net_device *ndev,
|
|
-@@ -3401,7 +3418,9 @@ static int mvneta_mac_link_state(struct
|
|
- gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
|
|
-
|
|
- if (gmac_stat & MVNETA_GMAC_SPEED_1000)
|
|
-- state->speed = SPEED_1000;
|
|
-+ state->speed =
|
|
-+ state->interface == PHY_INTERFACE_MODE_2500BASEX ?
|
|
-+ SPEED_2500 : SPEED_1000;
|
|
- else if (gmac_stat & MVNETA_GMAC_SPEED_100)
|
|
- state->speed = SPEED_100;
|
|
- else
|
|
-@@ -3516,12 +3535,20 @@ static void mvneta_mac_config(struct net
|
|
- MVNETA_GMAC_FORCE_LINK_DOWN);
|
|
- }
|
|
-
|
|
-+
|
|
- /* When at 2.5G, the link partner can send frames with shortened
|
|
- * preambles.
|
|
- */
|
|
- if (state->speed == SPEED_2500)
|
|
- new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE;
|
|
-
|
|
-+ if (pp->comphy &&
|
|
-+ (state->interface == PHY_INTERFACE_MODE_SGMII ||
|
|
-+ state->interface == PHY_INTERFACE_MODE_1000BASEX ||
|
|
-+ state->interface == PHY_INTERFACE_MODE_2500BASEX))
|
|
-+ WARN_ON(phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET,
|
|
-+ state->interface));
|
|
-+
|
|
- if (new_ctrl0 != gmac_ctrl0)
|
|
- mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0);
|
|
- if (new_ctrl2 != gmac_ctrl2)
|
|
-@@ -4434,7 +4461,7 @@ static int mvneta_port_power_up(struct m
|
|
- if (phy_mode == PHY_INTERFACE_MODE_QSGMII)
|
|
- mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
|
|
- else if (phy_mode == PHY_INTERFACE_MODE_SGMII ||
|
|
-- phy_mode == PHY_INTERFACE_MODE_1000BASEX)
|
|
-+ phy_interface_mode_is_8023z(phy_mode))
|
|
- mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
|
|
- else if (!phy_interface_mode_is_rgmii(phy_mode))
|
|
- return -EINVAL;
|
|
-@@ -4451,6 +4478,7 @@ static int mvneta_probe(struct platform_
|
|
- struct mvneta_port *pp;
|
|
- struct net_device *dev;
|
|
- struct phylink *phylink;
|
|
-+ struct phy *comphy;
|
|
- const char *dt_mac_addr;
|
|
- char hw_mac_addr[ETH_ALEN];
|
|
- const char *mac_from;
|
|
-@@ -4476,6 +4504,14 @@ static int mvneta_probe(struct platform_
|
|
- goto err_free_irq;
|
|
- }
|
|
-
|
|
-+ comphy = devm_of_phy_get(&pdev->dev, dn, NULL);
|
|
-+ if (comphy == ERR_PTR(-EPROBE_DEFER)) {
|
|
-+ err = -EPROBE_DEFER;
|
|
-+ goto err_free_irq;
|
|
-+ } else if (IS_ERR(comphy)) {
|
|
-+ comphy = NULL;
|
|
-+ }
|
|
-+
|
|
- phylink = phylink_create(dev, pdev->dev.fwnode, phy_mode,
|
|
- &mvneta_phylink_ops);
|
|
- if (IS_ERR(phylink)) {
|
|
-@@ -4492,6 +4528,7 @@ static int mvneta_probe(struct platform_
|
|
- pp = netdev_priv(dev);
|
|
- spin_lock_init(&pp->lock);
|
|
- pp->phylink = phylink;
|
|
-+ pp->comphy = comphy;
|
|
- pp->phy_interface = phy_mode;
|
|
- pp->dn = dn;
|
|
-
|
|
diff --git a/target/linux/mvebu/patches-5.4/536-net-marvell-neta-disable-comphy-when-setting-mode.patch b/target/linux/mvebu/patches-5.4/536-net-marvell-neta-disable-comphy-when-setting-mode.patch
|
|
deleted file mode 100644
|
|
index bac9a55cf0d..00000000000
|
|
--- a/target/linux/mvebu/patches-5.4/536-net-marvell-neta-disable-comphy-when-setting-mode.patch
|
|
+++ /dev/null
|
|
@@ -1,78 +0,0 @@
|
|
-From 031b922bfd60c771588911112f8632783de08e5c Mon Sep 17 00:00:00 2001
|
|
-From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <marek.behun@nic.cz>
|
|
-Date: Mon, 25 Feb 2019 17:43:03 +0100
|
|
-Subject: [PATCH] net: marvell: neta: disable comphy when setting mode
|
|
-MIME-Version: 1.0
|
|
-Content-Type: text/plain; charset=UTF-8
|
|
-Content-Transfer-Encoding: 8bit
|
|
-
|
|
-The comphy driver for Armada 3700 by Miquèl Raynal (which is currently
|
|
-in linux-next) does not actually set comphy mode when phy_set_mode_ext
|
|
-is called. The mode is set at next call of phy_power_on.
|
|
-
|
|
-Update the driver to semantics similar to mvpp2: helper
|
|
-mvneta_comphy_init sets comphy mode and powers it on.
|
|
-When mode is to be changed in mvneta_mac_config, first power the comphy
|
|
-off, then call mvneta_comphy_init (which sets the mode to new one).
|
|
-
|
|
-Only do this when new mode is different from old mode.
|
|
-
|
|
-This should also work for Armada 38x, since in that comphy driver
|
|
-methods power_on and power_off are unimplemented.
|
|
-
|
|
-Signed-off-by: Marek Behún <marek.behun@nic.cz>
|
|
-Signed-off-by: David S. Miller <davem@davemloft.net>
|
|
----
|
|
- drivers/net/ethernet/marvell/mvneta.c | 28 +++++++++++++++++++++++-----
|
|
- 1 file changed, 23 insertions(+), 5 deletions(-)
|
|
-
|
|
---- a/drivers/net/ethernet/marvell/mvneta.c
|
|
-+++ b/drivers/net/ethernet/marvell/mvneta.c
|
|
-@@ -3166,11 +3166,26 @@ static int mvneta_setup_txqs(struct mvne
|
|
- return 0;
|
|
- }
|
|
-
|
|
-+static int mvneta_comphy_init(struct mvneta_port *pp)
|
|
-+{
|
|
-+ int ret;
|
|
-+
|
|
-+ if (!pp->comphy)
|
|
-+ return 0;
|
|
-+
|
|
-+ ret = phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET,
|
|
-+ pp->phy_interface);
|
|
-+ if (ret)
|
|
-+ return ret;
|
|
-+
|
|
-+ return phy_power_on(pp->comphy);
|
|
-+}
|
|
-+
|
|
- static void mvneta_start_dev(struct mvneta_port *pp)
|
|
- {
|
|
- int cpu;
|
|
-
|
|
-- WARN_ON(phy_power_on(pp->comphy));
|
|
-+ WARN_ON(mvneta_comphy_init(pp));
|
|
-
|
|
- mvneta_max_rx_size_set(pp, pp->pkt_size);
|
|
- mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
|
|
-@@ -3542,12 +3557,15 @@ static void mvneta_mac_config(struct net
|
|
- if (state->speed == SPEED_2500)
|
|
- new_ctrl4 |= MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE;
|
|
-
|
|
-- if (pp->comphy &&
|
|
-+ if (pp->comphy && pp->phy_interface != state->interface &&
|
|
- (state->interface == PHY_INTERFACE_MODE_SGMII ||
|
|
- state->interface == PHY_INTERFACE_MODE_1000BASEX ||
|
|
-- state->interface == PHY_INTERFACE_MODE_2500BASEX))
|
|
-- WARN_ON(phy_set_mode_ext(pp->comphy, PHY_MODE_ETHERNET,
|
|
-- state->interface));
|
|
-+ state->interface == PHY_INTERFACE_MODE_2500BASEX)) {
|
|
-+ pp->phy_interface = state->interface;
|
|
-+
|
|
-+ WARN_ON(phy_power_off(pp->comphy));
|
|
-+ WARN_ON(mvneta_comphy_init(pp));
|
|
-+ }
|
|
-
|
|
- if (new_ctrl0 != gmac_ctrl0)
|
|
- mvreg_write(pp, MVNETA_GMAC_CTRL_0, new_ctrl0);
|
|
diff --git a/target/linux/mvebu/patches-5.4/537-net-mvneta-add-2500baset-support.patch b/target/linux/mvebu/patches-5.4/537-net-mvneta-add-2500baset-support.patch
|
|
deleted file mode 100644
|
|
index 9186ceb0da4..00000000000
|
|
--- a/target/linux/mvebu/patches-5.4/537-net-mvneta-add-2500baset-support.patch
|
|
+++ /dev/null
|
|
@@ -1,34 +0,0 @@
|
|
-From eda3d1b0228484fb52b7244a68fd4cc8a985ed10 Mon Sep 17 00:00:00 2001
|
|
-From: Maxime Chevallier <maxime.chevallier@bootlin.com>
|
|
-Date: Wed, 27 Mar 2019 17:31:06 +0100
|
|
-Subject: [PATCH] net: mvneta: Add 2500BaseT support
|
|
-
|
|
-Some PHYs will use the 2500BaseX PHY_INTERFACE_MODE when being linked
|
|
-with a partner using 2.5GBaseT.
|
|
-
|
|
-Since we can't autonegotiate this speed between the MAC and the PHY, we
|
|
-need to have the proper comphy support enabled, to make sure we can
|
|
-safely advertise 2.5G and 1G in BaseT and be able to switch between both
|
|
-corresponding PHY interface modes. This is now possible since comphy
|
|
-support was added to this driver.
|
|
-
|
|
-This commit adds the 2500BaseT mode to the list of supported modes when
|
|
-using 2500BaseX, and was tested on a setup with an Armada385 and a
|
|
-88E2010 PHY, both with and without the comphy node in the DT.
|
|
-
|
|
-Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
|
|
-Signed-off-by: David S. Miller <davem@davemloft.net>
|
|
----
|
|
- drivers/net/ethernet/marvell/mvneta.c | 1 +
|
|
- 1 file changed, 1 insertion(+)
|
|
-
|
|
---- a/drivers/net/ethernet/marvell/mvneta.c
|
|
-+++ b/drivers/net/ethernet/marvell/mvneta.c
|
|
-@@ -3402,6 +3402,7 @@ static void mvneta_validate(struct net_d
|
|
- phylink_set(mask, 1000baseX_Full);
|
|
- }
|
|
- if (pp->comphy || state->interface == PHY_INTERFACE_MODE_2500BASEX) {
|
|
-+ phylink_set(mask, 2500baseT_Full);
|
|
- phylink_set(mask, 2500baseX_Full);
|
|
- }
|
|
-
|
|
diff --git a/target/linux/mvebu/patches-5.4/538-phy-add-QSGMII-and-PCIE-modes.patch b/target/linux/mvebu/patches-5.4/538-phy-add-QSGMII-and-PCIE-modes.patch
|
|
deleted file mode 100644
|
|
index b759b9fb254..00000000000
|
|
--- a/target/linux/mvebu/patches-5.4/538-phy-add-QSGMII-and-PCIE-modes.patch
|
|
+++ /dev/null
|
|
@@ -1,28 +0,0 @@
|
|
-From c2a90025ad09d830c8d8ae69f485eac6aaaa2472 Mon Sep 17 00:00:00 2001
|
|
-From: Quentin Schulz <quentin.schulz@bootlin.com>
|
|
-Date: Thu, 4 Oct 2018 14:22:03 +0200
|
|
-Subject: [PATCH] phy: add QSGMII and PCIE modes
|
|
-
|
|
-Prepare for upcoming phys that'll handle QSGMII or PCIe.
|
|
-
|
|
-Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
|
|
-Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
|
|
-Signed-off-by: David S. Miller <davem@davemloft.net>
|
|
----
|
|
- include/linux/phy/phy.h | 2 ++
|
|
- 1 file changed, 2 insertions(+)
|
|
-
|
|
---- a/include/linux/phy/phy.h
|
|
-+++ b/include/linux/phy/phy.h
|
|
-@@ -37,9 +37,11 @@ enum phy_mode {
|
|
- PHY_MODE_USB_OTG,
|
|
- PHY_MODE_SGMII,
|
|
- PHY_MODE_2500SGMII,
|
|
-+ PHY_MODE_QSGMII,
|
|
- PHY_MODE_10GKR,
|
|
- PHY_MODE_UFS_HS_A,
|
|
- PHY_MODE_UFS_HS_B,
|
|
-+ PHY_MODE_PCIE,
|
|
- };
|
|
-
|
|
- /**
|
|
diff --git a/target/linux/mvebu/patches-5.4/539-phy-core-add-PHY_MODE_ETHERNET.patch b/target/linux/mvebu/patches-5.4/539-phy-core-add-PHY_MODE_ETHERNET.patch
|
|
deleted file mode 100644
|
|
index 68fecadce85..00000000000
|
|
--- a/target/linux/mvebu/patches-5.4/539-phy-core-add-PHY_MODE_ETHERNET.patch
|
|
+++ /dev/null
|
|
@@ -1,24 +0,0 @@
|
|
-From 2af8caeee47846a84bc96abc3a72f7c991153040 Mon Sep 17 00:00:00 2001
|
|
-From: Grygorii Strashko <grygorii.strashko@ti.com>
|
|
-Date: Mon, 19 Nov 2018 19:24:21 -0600
|
|
-Subject: [PATCH] phy: core: add PHY_MODE_ETHERNET
|
|
-
|
|
-Add new PHY's mode to be used by Ethernet PHY interface drivers or
|
|
-multipurpose PHYs like serdes. It will be reused in further changes.
|
|
-
|
|
-Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
|
|
-Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
|
|
----
|
|
- include/linux/phy/phy.h | 1 +
|
|
- 1 file changed, 1 insertion(+)
|
|
-
|
|
---- a/include/linux/phy/phy.h
|
|
-+++ b/include/linux/phy/phy.h
|
|
-@@ -42,6 +42,7 @@ enum phy_mode {
|
|
- PHY_MODE_UFS_HS_A,
|
|
- PHY_MODE_UFS_HS_B,
|
|
- PHY_MODE_PCIE,
|
|
-+ PHY_MODE_ETHERNET,
|
|
- };
|
|
-
|
|
- /**
|
|
diff --git a/target/linux/mvebu/patches-5.4/540-phy-fix-build-breakage-add-PHY_MODE_SATA.patch b/target/linux/mvebu/patches-5.4/540-phy-fix-build-breakage-add-PHY_MODE_SATA.patch
|
|
deleted file mode 100644
|
|
index 83908af19e6..00000000000
|
|
--- a/target/linux/mvebu/patches-5.4/540-phy-fix-build-breakage-add-PHY_MODE_SATA.patch
|
|
+++ /dev/null
|
|
@@ -1,45 +0,0 @@
|
|
-From e1706720408e72fb883f6b151c2b3b23d8e7e5b2 Mon Sep 17 00:00:00 2001
|
|
-From: John Hubbard <jhubbard@nvidia.com>
|
|
-Date: Sat, 12 Jan 2019 17:29:09 -0800
|
|
-Subject: [PATCH] phy: fix build breakage: add PHY_MODE_SATA
|
|
-
|
|
-Commit 49e54187ae0b ("ata: libahci_platform: comply to PHY framework") uses
|
|
-the PHY_MODE_SATA, but that enum had not yet been added. This caused a
|
|
-build failure for me, with today's linux.git.
|
|
-
|
|
-Also, there is a potentially conflicting (mis-named) PHY_MODE_SATA, hiding
|
|
-in the Marvell Berlin SATA PHY driver.
|
|
-
|
|
-Fix the build by:
|
|
-
|
|
- 1) Renaming Marvell's defined value to a more scoped name,
|
|
- in order to avoid any potential conflicts: PHY_BERLIN_MODE_SATA.
|
|
-
|
|
- 2) Adding the missing enum, which was going to be added anyway as part
|
|
- of [1].
|
|
-
|
|
-[1] https://lkml.kernel.org/r/20190108163124.6409-3-miquel.raynal@bootlin.com
|
|
-
|
|
-Fixes: 49e54187ae0b ("ata: libahci_platform: comply to PHY framework")
|
|
-
|
|
-Signed-off-by: John Hubbard <jhubbard@nvidia.com>
|
|
-Acked-by: Jens Axboe <axboe@kernel.dk>
|
|
-Acked-by: Olof Johansson <olof@lixom.net>
|
|
-Cc: Grzegorz Jaszczyk <jaz@semihalf.com>
|
|
-Cc: Miquel Raynal <miquel.raynal@bootlin.com>
|
|
-Cc: Hans de Goede <hdegoede@redhat.com>
|
|
-Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
|
|
----
|
|
- include/linux/phy/phy.h | 1 +
|
|
- 1 file changed, 1 insertion(+)
|
|
-
|
|
---- a/include/linux/phy/phy.h
|
|
-+++ b/include/linux/phy/phy.h
|
|
-@@ -43,6 +43,7 @@ enum phy_mode {
|
|
- PHY_MODE_UFS_HS_B,
|
|
- PHY_MODE_PCIE,
|
|
- PHY_MODE_ETHERNET,
|
|
-+ PHY_MODE_SATA
|
|
- };
|
|
-
|
|
- /**
|
|
diff --git a/target/linux/mvebu/patches-5.4/541-phy-core-rework-phy_set_mode-to-accept-phy-mode-and-.patch b/target/linux/mvebu/patches-5.4/541-phy-core-rework-phy_set_mode-to-accept-phy-mode-and-.patch
|
|
deleted file mode 100644
|
|
index e02f203912d..00000000000
|
|
--- a/target/linux/mvebu/patches-5.4/541-phy-core-rework-phy_set_mode-to-accept-phy-mode-and-.patch
|
|
+++ /dev/null
|
|
@@ -1,134 +0,0 @@
|
|
-From 79a5a18aa9d1062205cdcfa183d4cd5241d1b8da Mon Sep 17 00:00:00 2001
|
|
-From: Grygorii Strashko <grygorii.strashko@ti.com>
|
|
-Date: Mon, 19 Nov 2018 19:24:20 -0600
|
|
-Subject: [PATCH] phy: core: rework phy_set_mode to accept phy mode and submode
|
|
-
|
|
-Currently the attempt to add support for Ethernet interface mode PHY
|
|
-(MII/GMII/RGMII) will lead to the necessity of extending enum phy_mode and
|
|
-duplicate there values from phy_interface_t enum (or introduce more PHY
|
|
-callbacks) [1]. Both approaches are ineffective and would lead to fast
|
|
-bloating of enum phy_mode or struct phy_ops in the process of adding more
|
|
-PHYs for different subsystems which will make them unmaintainable.
|
|
-
|
|
-As discussed in [1] the solution could be to introduce dual level PHYs mode
|
|
-configuration - PHY mode and PHY submode. The PHY mode will define generic
|
|
-PHY type (subsystem - PCIE/ETHERNET/USB_) while the PHY submode - subsystem
|
|
-specific interface mode. The last is usually already defined in
|
|
-corresponding subsystem headers (phy_interface_t for Ethernet, enum
|
|
-usb_device_speed for USB).
|
|
-
|
|
-This patch is cumulative change which refactors PHY framework code to
|
|
-support dual level PHYs mode configuration - PHY mode and PHY submode. It
|
|
-extends .set_mode() callback to support additional parameter "int submode"
|
|
-and converts all corresponding PHY drivers to support new .set_mode()
|
|
-callback declaration.
|
|
-The new extended PHY API
|
|
- int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode)
|
|
-is introduced to support dual level PHYs mode configuration and existing
|
|
-phy_set_mode() API is converted to macros, so PHY framework consumers do
|
|
-not need to be changed (~21 matches).
|
|
-
|
|
-[1] http://lkml.kernel.org/r/d63588f6-9ab0-848a-5ad4-8073143bd95d@ti.com
|
|
-Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
|
|
-Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
|
|
----
|
|
- drivers/phy/allwinner/phy-sun4i-usb.c | 3 ++-
|
|
- drivers/phy/amlogic/phy-meson-gxl-usb2.c | 5 +++--
|
|
- drivers/phy/amlogic/phy-meson-gxl-usb3.c | 5 +++--
|
|
- drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 3 ++-
|
|
- drivers/phy/mediatek/phy-mtk-tphy.c | 2 +-
|
|
- drivers/phy/mediatek/phy-mtk-xsphy.c | 2 +-
|
|
- drivers/phy/mscc/phy-ocelot-serdes.c | 2 +-
|
|
- drivers/phy/phy-core.c | 6 +++---
|
|
- drivers/phy/qualcomm/phy-qcom-qmp.c | 3 ++-
|
|
- drivers/phy/qualcomm/phy-qcom-qusb2.c | 3 ++-
|
|
- drivers/phy/qualcomm/phy-qcom-ufs-qmp-14nm.c | 3 ++-
|
|
- drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.c | 3 ++-
|
|
- drivers/phy/qualcomm/phy-qcom-usb-hs.c | 3 ++-
|
|
- drivers/phy/ti/phy-da8xx-usb.c | 3 ++-
|
|
- drivers/phy/ti/phy-tusb1210.c | 2 +-
|
|
- include/linux/phy/phy.h | 13 ++++++++++---
|
|
- 16 files changed, 39 insertions(+), 22 deletions(-)
|
|
-
|
|
---- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
|
|
-+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
|
|
-@@ -512,7 +512,8 @@ static int mvebu_comphy_power_on(struct
|
|
- return ret;
|
|
- }
|
|
-
|
|
--static int mvebu_comphy_set_mode(struct phy *phy, enum phy_mode mode)
|
|
-+static int mvebu_comphy_set_mode(struct phy *phy,
|
|
-+ enum phy_mode mode, int submode)
|
|
- {
|
|
- struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
|
|
-
|
|
---- a/drivers/phy/phy-core.c
|
|
-+++ b/drivers/phy/phy-core.c
|
|
-@@ -360,7 +360,7 @@ int phy_power_off(struct phy *phy)
|
|
- }
|
|
- EXPORT_SYMBOL_GPL(phy_power_off);
|
|
-
|
|
--int phy_set_mode(struct phy *phy, enum phy_mode mode)
|
|
-+int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode)
|
|
- {
|
|
- int ret;
|
|
-
|
|
-@@ -368,14 +368,14 @@ int phy_set_mode(struct phy *phy, enum p
|
|
- return 0;
|
|
-
|
|
- mutex_lock(&phy->mutex);
|
|
-- ret = phy->ops->set_mode(phy, mode);
|
|
-+ ret = phy->ops->set_mode(phy, mode, submode);
|
|
- if (!ret)
|
|
- phy->attrs.mode = mode;
|
|
- mutex_unlock(&phy->mutex);
|
|
-
|
|
- return ret;
|
|
- }
|
|
--EXPORT_SYMBOL_GPL(phy_set_mode);
|
|
-+EXPORT_SYMBOL_GPL(phy_set_mode_ext);
|
|
-
|
|
- int phy_reset(struct phy *phy)
|
|
- {
|
|
---- a/include/linux/phy/phy.h
|
|
-+++ b/include/linux/phy/phy.h
|
|
-@@ -62,7 +62,7 @@ struct phy_ops {
|
|
- int (*exit)(struct phy *phy);
|
|
- int (*power_on)(struct phy *phy);
|
|
- int (*power_off)(struct phy *phy);
|
|
-- int (*set_mode)(struct phy *phy, enum phy_mode mode);
|
|
-+ int (*set_mode)(struct phy *phy, enum phy_mode mode, int submode);
|
|
- int (*reset)(struct phy *phy);
|
|
- int (*calibrate)(struct phy *phy);
|
|
- struct module *owner;
|
|
-@@ -166,7 +166,10 @@ int phy_init(struct phy *phy);
|
|
- int phy_exit(struct phy *phy);
|
|
- int phy_power_on(struct phy *phy);
|
|
- int phy_power_off(struct phy *phy);
|
|
--int phy_set_mode(struct phy *phy, enum phy_mode mode);
|
|
-+int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode);
|
|
-+#define phy_set_mode(phy, mode) \
|
|
-+ phy_set_mode_ext(phy, mode, 0)
|
|
-+
|
|
- static inline enum phy_mode phy_get_mode(struct phy *phy)
|
|
- {
|
|
- return phy->attrs.mode;
|
|
-@@ -280,13 +283,17 @@ static inline int phy_power_off(struct p
|
|
- return -ENOSYS;
|
|
- }
|
|
-
|
|
--static inline int phy_set_mode(struct phy *phy, enum phy_mode mode)
|
|
-+static inline int phy_set_mode_ext(struct phy *phy, enum phy_mode mode,
|
|
-+ int submode)
|
|
- {
|
|
- if (!phy)
|
|
- return 0;
|
|
- return -ENOSYS;
|
|
- }
|
|
-
|
|
-+#define phy_set_mode(phy, mode) \
|
|
-+ phy_set_mode_ext(phy, mode, 0)
|
|
-+
|
|
- static inline enum phy_mode phy_get_mode(struct phy *phy)
|
|
- {
|
|
- return PHY_MODE_INVALID;
|
|
diff --git a/target/linux/mvebu/patches-5.4/542-phy-add-A3700-COMPHY-support.patch b/target/linux/mvebu/patches-5.4/542-phy-add-A3700-COMPHY-support.patch
|
|
deleted file mode 100644
|
|
index 0964da03a8d..00000000000
|
|
--- a/target/linux/mvebu/patches-5.4/542-phy-add-A3700-COMPHY-support.patch
|
|
+++ /dev/null
|
|
@@ -1,381 +0,0 @@
|
|
-From 9695375a3f4a604406f2e61f2b735eca1de931ed Mon Sep 17 00:00:00 2001
|
|
-From: Miquel Raynal <miquel.raynal@bootlin.com>
|
|
-Date: Tue, 8 Jan 2019 17:31:20 +0100
|
|
-Subject: [PATCH] phy: add A3700 COMPHY support
|
|
-
|
|
-Add a driver to support COMPHY, a hardware block providing shared
|
|
-serdes PHYs on Marvell Armada 3700. This driver uses SMC calls and
|
|
-rely on having an up-to-date firmware.
|
|
-
|
|
-SATA, PCie and USB3 host mode have been tested successfully with an
|
|
-ESPRESSObin. (HS)SGMII mode cannot be tested with this platform.
|
|
-
|
|
-Evan worked on the original driver structure and Grzegorz on the SMC
|
|
-calls rework. The structure of this driver has been copied from
|
|
-Antoine Tenart work on CP110 COMPHY driver.
|
|
-
|
|
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
|
|
-Co-developed-by: Evan Wang <xswang@marvell.com>
|
|
-Signed-off-by: Evan Wang <xswang@marvell.com>
|
|
-Co-developed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
|
|
-Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
|
|
-Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
|
|
----
|
|
- drivers/phy/marvell/Kconfig | 12 +
|
|
- drivers/phy/marvell/Makefile | 1 +
|
|
- drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 318 +++++++++++++++++++++++++++
|
|
- 3 files changed, 331 insertions(+)
|
|
- create mode 100644 drivers/phy/marvell/phy-mvebu-a3700-comphy.c
|
|
-
|
|
---- a/drivers/phy/marvell/Kconfig
|
|
-+++ b/drivers/phy/marvell/Kconfig
|
|
-@@ -21,6 +21,18 @@ config PHY_BERLIN_USB
|
|
- help
|
|
- Enable this to support the USB PHY on Marvell Berlin SoCs.
|
|
-
|
|
-+config PHY_MVEBU_A3700_COMPHY
|
|
-+ tristate "Marvell A3700 comphy driver"
|
|
-+ depends on ARCH_MVEBU || COMPILE_TEST
|
|
-+ depends on OF
|
|
-+ depends on HAVE_ARM_SMCCC
|
|
-+ default y
|
|
-+ select GENERIC_PHY
|
|
-+ help
|
|
-+ This driver allows to control the comphy, a hardware block providing
|
|
-+ shared serdes PHYs on Marvell Armada 3700. Its serdes lanes can be
|
|
-+ used by various controllers: Ethernet, SATA, USB3, PCIe.
|
|
-+
|
|
- config PHY_MVEBU_CP110_COMPHY
|
|
- tristate "Marvell CP110 comphy driver"
|
|
- depends on ARCH_MVEBU || COMPILE_TEST
|
|
---- a/drivers/phy/marvell/Makefile
|
|
-+++ b/drivers/phy/marvell/Makefile
|
|
-@@ -2,6 +2,7 @@
|
|
- obj-$(CONFIG_ARMADA375_USBCLUSTER_PHY) += phy-armada375-usb2.o
|
|
- obj-$(CONFIG_PHY_BERLIN_SATA) += phy-berlin-sata.o
|
|
- obj-$(CONFIG_PHY_BERLIN_USB) += phy-berlin-usb.o
|
|
-+obj-$(CONFIG_PHY_MVEBU_A3700_COMPHY) += phy-mvebu-a3700-comphy.o
|
|
- obj-$(CONFIG_PHY_MVEBU_CP110_COMPHY) += phy-mvebu-cp110-comphy.o
|
|
- obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
|
|
- obj-$(CONFIG_PHY_PXA_28NM_HSIC) += phy-pxa-28nm-hsic.o
|
|
---- /dev/null
|
|
-+++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
|
|
-@@ -0,0 +1,318 @@
|
|
-+// SPDX-License-Identifier: GPL-2.0
|
|
-+/*
|
|
-+ * Copyright (C) 2018 Marvell
|
|
-+ *
|
|
-+ * Authors:
|
|
-+ * Evan Wang <xswang@marvell.com>
|
|
-+ * Miquèl Raynal <miquel.raynal@bootlin.com>
|
|
-+ *
|
|
-+ * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
|
|
-+ * SMC call initial support done by Grzegorz Jaszczyk.
|
|
-+ */
|
|
-+
|
|
-+#include <linux/arm-smccc.h>
|
|
-+#include <linux/io.h>
|
|
-+#include <linux/iopoll.h>
|
|
-+#include <linux/mfd/syscon.h>
|
|
-+#include <linux/module.h>
|
|
-+#include <linux/phy.h>
|
|
-+#include <linux/phy/phy.h>
|
|
-+#include <linux/platform_device.h>
|
|
-+
|
|
-+#define MVEBU_A3700_COMPHY_LANES 3
|
|
-+#define MVEBU_A3700_COMPHY_PORTS 2
|
|
-+
|
|
-+/* COMPHY Fast SMC function identifiers */
|
|
-+#define COMPHY_SIP_POWER_ON 0x82000001
|
|
-+#define COMPHY_SIP_POWER_OFF 0x82000002
|
|
-+#define COMPHY_SIP_PLL_LOCK 0x82000003
|
|
-+
|
|
-+#define COMPHY_FW_MODE_SATA 0x1
|
|
-+#define COMPHY_FW_MODE_SGMII 0x2
|
|
-+#define COMPHY_FW_MODE_HS_SGMII 0x3
|
|
-+#define COMPHY_FW_MODE_USB3H 0x4
|
|
-+#define COMPHY_FW_MODE_USB3D 0x5
|
|
-+#define COMPHY_FW_MODE_PCIE 0x6
|
|
-+#define COMPHY_FW_MODE_RXAUI 0x7
|
|
-+#define COMPHY_FW_MODE_XFI 0x8
|
|
-+#define COMPHY_FW_MODE_SFI 0x9
|
|
-+#define COMPHY_FW_MODE_USB3 0xa
|
|
-+
|
|
-+#define COMPHY_FW_SPEED_1_25G 0 /* SGMII 1G */
|
|
-+#define COMPHY_FW_SPEED_2_5G 1
|
|
-+#define COMPHY_FW_SPEED_3_125G 2 /* SGMII 2.5G */
|
|
-+#define COMPHY_FW_SPEED_5G 3
|
|
-+#define COMPHY_FW_SPEED_5_15625G 4 /* XFI 5G */
|
|
-+#define COMPHY_FW_SPEED_6G 5
|
|
-+#define COMPHY_FW_SPEED_10_3125G 6 /* XFI 10G */
|
|
-+#define COMPHY_FW_SPEED_MAX 0x3F
|
|
-+
|
|
-+#define COMPHY_FW_MODE(mode) ((mode) << 12)
|
|
-+#define COMPHY_FW_NET(mode, idx, speed) (COMPHY_FW_MODE(mode) | \
|
|
-+ ((idx) << 8) | \
|
|
-+ ((speed) << 2))
|
|
-+#define COMPHY_FW_PCIE(mode, idx, speed, width) (COMPHY_FW_NET(mode, idx, speed) | \
|
|
-+ ((width) << 18))
|
|
-+
|
|
-+struct mvebu_a3700_comphy_conf {
|
|
-+ unsigned int lane;
|
|
-+ enum phy_mode mode;
|
|
-+ int submode;
|
|
-+ unsigned int port;
|
|
-+ u32 fw_mode;
|
|
-+};
|
|
-+
|
|
-+#define MVEBU_A3700_COMPHY_CONF(_lane, _mode, _smode, _port, _fw) \
|
|
-+ { \
|
|
-+ .lane = _lane, \
|
|
-+ .mode = _mode, \
|
|
-+ .submode = _smode, \
|
|
-+ .port = _port, \
|
|
-+ .fw_mode = _fw, \
|
|
-+ }
|
|
-+
|
|
-+#define MVEBU_A3700_COMPHY_CONF_GEN(_lane, _mode, _port, _fw) \
|
|
-+ MVEBU_A3700_COMPHY_CONF(_lane, _mode, PHY_INTERFACE_MODE_NA, _port, _fw)
|
|
-+
|
|
-+#define MVEBU_A3700_COMPHY_CONF_ETH(_lane, _smode, _port, _fw) \
|
|
-+ MVEBU_A3700_COMPHY_CONF(_lane, PHY_MODE_ETHERNET, _smode, _port, _fw)
|
|
-+
|
|
-+static const struct mvebu_a3700_comphy_conf mvebu_a3700_comphy_modes[] = {
|
|
-+ /* lane 0 */
|
|
-+ MVEBU_A3700_COMPHY_CONF_GEN(0, PHY_MODE_USB_HOST_SS, 0,
|
|
-+ COMPHY_FW_MODE_USB3H),
|
|
-+ MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII, 1,
|
|
-+ COMPHY_FW_MODE_SGMII),
|
|
-+ MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX, 1,
|
|
-+ COMPHY_FW_MODE_HS_SGMII),
|
|
-+ /* lane 1 */
|
|
-+ MVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE, 0,
|
|
-+ COMPHY_FW_MODE_PCIE),
|
|
-+ MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII, 0,
|
|
-+ COMPHY_FW_MODE_SGMII),
|
|
-+ MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX, 0,
|
|
-+ COMPHY_FW_MODE_HS_SGMII),
|
|
-+ /* lane 2 */
|
|
-+ MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA, 0,
|
|
-+ COMPHY_FW_MODE_SATA),
|
|
-+ MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_USB_HOST_SS, 0,
|
|
-+ COMPHY_FW_MODE_USB3H),
|
|
-+};
|
|
-+
|
|
-+struct mvebu_a3700_comphy_lane {
|
|
-+ struct device *dev;
|
|
-+ unsigned int id;
|
|
-+ enum phy_mode mode;
|
|
-+ int submode;
|
|
-+ int port;
|
|
-+};
|
|
-+
|
|
-+static int mvebu_a3700_comphy_smc(unsigned long function, unsigned long lane,
|
|
-+ unsigned long mode)
|
|
-+{
|
|
-+ struct arm_smccc_res res;
|
|
-+
|
|
-+ arm_smccc_smc(function, lane, mode, 0, 0, 0, 0, 0, &res);
|
|
-+
|
|
-+ return res.a0;
|
|
-+}
|
|
-+
|
|
-+static int mvebu_a3700_comphy_get_fw_mode(int lane, int port,
|
|
-+ enum phy_mode mode,
|
|
-+ int submode)
|
|
-+{
|
|
-+ int i, n = ARRAY_SIZE(mvebu_a3700_comphy_modes);
|
|
-+
|
|
-+ /* Unused PHY mux value is 0x0 */
|
|
-+ if (mode == PHY_MODE_INVALID)
|
|
-+ return -EINVAL;
|
|
-+
|
|
-+ for (i = 0; i < n; i++) {
|
|
-+ if (mvebu_a3700_comphy_modes[i].lane == lane &&
|
|
-+ mvebu_a3700_comphy_modes[i].port == port &&
|
|
-+ mvebu_a3700_comphy_modes[i].mode == mode &&
|
|
-+ mvebu_a3700_comphy_modes[i].submode == submode)
|
|
-+ break;
|
|
-+ }
|
|
-+
|
|
-+ if (i == n)
|
|
-+ return -EINVAL;
|
|
-+
|
|
-+ return mvebu_a3700_comphy_modes[i].fw_mode;
|
|
-+}
|
|
-+
|
|
-+static int mvebu_a3700_comphy_set_mode(struct phy *phy, enum phy_mode mode,
|
|
-+ int submode)
|
|
-+{
|
|
-+ struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
|
|
-+ int fw_mode;
|
|
-+
|
|
-+ if (submode == PHY_INTERFACE_MODE_1000BASEX)
|
|
-+ submode = PHY_INTERFACE_MODE_SGMII;
|
|
-+
|
|
-+ fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, lane->port, mode,
|
|
-+ submode);
|
|
-+ if (fw_mode < 0) {
|
|
-+ dev_err(lane->dev, "invalid COMPHY mode\n");
|
|
-+ return fw_mode;
|
|
-+ }
|
|
-+
|
|
-+ /* Just remember the mode, ->power_on() will do the real setup */
|
|
-+ lane->mode = mode;
|
|
-+ lane->submode = submode;
|
|
-+
|
|
-+ return 0;
|
|
-+}
|
|
-+
|
|
-+static int mvebu_a3700_comphy_power_on(struct phy *phy)
|
|
-+{
|
|
-+ struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
|
|
-+ u32 fw_param;
|
|
-+ int fw_mode;
|
|
-+
|
|
-+ fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, lane->port,
|
|
-+ lane->mode, lane->submode);
|
|
-+ if (fw_mode < 0) {
|
|
-+ dev_err(lane->dev, "invalid COMPHY mode\n");
|
|
-+ return fw_mode;
|
|
-+ }
|
|
-+
|
|
-+ switch (lane->mode) {
|
|
-+ case PHY_MODE_USB_HOST_SS:
|
|
-+ dev_dbg(lane->dev, "set lane %d to USB3 host mode\n", lane->id);
|
|
-+ fw_param = COMPHY_FW_MODE(fw_mode);
|
|
-+ break;
|
|
-+ case PHY_MODE_SATA:
|
|
-+ dev_dbg(lane->dev, "set lane %d to SATA mode\n", lane->id);
|
|
-+ fw_param = COMPHY_FW_MODE(fw_mode);
|
|
-+ break;
|
|
-+ case PHY_MODE_ETHERNET:
|
|
-+ switch (lane->submode) {
|
|
-+ case PHY_INTERFACE_MODE_SGMII:
|
|
-+ dev_dbg(lane->dev, "set lane %d to SGMII mode\n",
|
|
-+ lane->id);
|
|
-+ fw_param = COMPHY_FW_NET(fw_mode, lane->port,
|
|
-+ COMPHY_FW_SPEED_1_25G);
|
|
-+ break;
|
|
-+ case PHY_INTERFACE_MODE_2500BASEX:
|
|
-+ dev_dbg(lane->dev, "set lane %d to HS SGMII mode\n",
|
|
-+ lane->id);
|
|
-+ fw_param = COMPHY_FW_NET(fw_mode, lane->port,
|
|
-+ COMPHY_FW_SPEED_3_125G);
|
|
-+ break;
|
|
-+ default:
|
|
-+ dev_err(lane->dev, "unsupported PHY submode (%d)\n",
|
|
-+ lane->submode);
|
|
-+ return -ENOTSUPP;
|
|
-+ }
|
|
-+ break;
|
|
-+ case PHY_MODE_PCIE:
|
|
-+ dev_dbg(lane->dev, "set lane %d to PCIe mode\n", lane->id);
|
|
-+ fw_param = COMPHY_FW_PCIE(fw_mode, lane->port,
|
|
-+ COMPHY_FW_SPEED_5G,
|
|
-+ phy->attrs.bus_width);
|
|
-+ break;
|
|
-+ default:
|
|
-+ dev_err(lane->dev, "unsupported PHY mode (%d)\n", lane->mode);
|
|
-+ return -ENOTSUPP;
|
|
-+ }
|
|
-+
|
|
-+ return mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_ON, lane->id, fw_param);
|
|
-+}
|
|
-+
|
|
-+static int mvebu_a3700_comphy_power_off(struct phy *phy)
|
|
-+{
|
|
-+ struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
|
|
-+
|
|
-+ return mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_OFF, lane->id, 0);
|
|
-+}
|
|
-+
|
|
-+static const struct phy_ops mvebu_a3700_comphy_ops = {
|
|
-+ .power_on = mvebu_a3700_comphy_power_on,
|
|
-+ .power_off = mvebu_a3700_comphy_power_off,
|
|
-+ .set_mode = mvebu_a3700_comphy_set_mode,
|
|
-+ .owner = THIS_MODULE,
|
|
-+};
|
|
-+
|
|
-+static struct phy *mvebu_a3700_comphy_xlate(struct device *dev,
|
|
-+ struct of_phandle_args *args)
|
|
-+{
|
|
-+ struct mvebu_a3700_comphy_lane *lane;
|
|
-+ struct phy *phy;
|
|
-+
|
|
-+ if (WARN_ON(args->args[0] >= MVEBU_A3700_COMPHY_PORTS))
|
|
-+ return ERR_PTR(-EINVAL);
|
|
-+
|
|
-+ phy = of_phy_simple_xlate(dev, args);
|
|
-+ if (IS_ERR(phy))
|
|
-+ return phy;
|
|
-+
|
|
-+ lane = phy_get_drvdata(phy);
|
|
-+ lane->port = args->args[0];
|
|
-+
|
|
-+ return phy;
|
|
-+}
|
|
-+
|
|
-+static int mvebu_a3700_comphy_probe(struct platform_device *pdev)
|
|
-+{
|
|
-+ struct phy_provider *provider;
|
|
-+ struct device_node *child;
|
|
-+
|
|
-+ for_each_available_child_of_node(pdev->dev.of_node, child) {
|
|
-+ struct mvebu_a3700_comphy_lane *lane;
|
|
-+ struct phy *phy;
|
|
-+ int ret;
|
|
-+ u32 lane_id;
|
|
-+
|
|
-+ ret = of_property_read_u32(child, "reg", &lane_id);
|
|
-+ if (ret < 0) {
|
|
-+ dev_err(&pdev->dev, "missing 'reg' property (%d)\n",
|
|
-+ ret);
|
|
-+ continue;
|
|
-+ }
|
|
-+
|
|
-+ if (lane_id >= MVEBU_A3700_COMPHY_LANES) {
|
|
-+ dev_err(&pdev->dev, "invalid 'reg' property\n");
|
|
-+ continue;
|
|
-+ }
|
|
-+
|
|
-+ lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL);
|
|
-+ if (!lane)
|
|
-+ return -ENOMEM;
|
|
-+
|
|
-+ phy = devm_phy_create(&pdev->dev, child,
|
|
-+ &mvebu_a3700_comphy_ops);
|
|
-+ if (IS_ERR(phy))
|
|
-+ return PTR_ERR(phy);
|
|
-+
|
|
-+ lane->dev = &pdev->dev;
|
|
-+ lane->mode = PHY_MODE_INVALID;
|
|
-+ lane->submode = PHY_INTERFACE_MODE_NA;
|
|
-+ lane->id = lane_id;
|
|
-+ lane->port = -1;
|
|
-+ phy_set_drvdata(phy, lane);
|
|
-+ }
|
|
-+
|
|
-+ provider = devm_of_phy_provider_register(&pdev->dev,
|
|
-+ mvebu_a3700_comphy_xlate);
|
|
-+ return PTR_ERR_OR_ZERO(provider);
|
|
-+}
|
|
-+
|
|
-+static const struct of_device_id mvebu_a3700_comphy_of_match_table[] = {
|
|
-+ { .compatible = "marvell,comphy-a3700" },
|
|
-+ { },
|
|
-+};
|
|
-+MODULE_DEVICE_TABLE(of, mvebu_a3700_comphy_of_match_table);
|
|
-+
|
|
-+static struct platform_driver mvebu_a3700_comphy_driver = {
|
|
-+ .probe = mvebu_a3700_comphy_probe,
|
|
-+ .driver = {
|
|
-+ .name = "mvebu-a3700-comphy",
|
|
-+ .of_match_table = mvebu_a3700_comphy_of_match_table,
|
|
-+ },
|
|
-+};
|
|
-+module_platform_driver(mvebu_a3700_comphy_driver);
|
|
-+
|
|
-+MODULE_AUTHOR("Miquèl Raynal <miquel.raynal@bootlin.com>");
|
|
-+MODULE_DESCRIPTION("Common PHY driver for A3700");
|
|
-+MODULE_LICENSE("GPL v2");
|
|
diff --git a/target/linux/mvebu/patches-5.4/543-arm64-dts-marvell-armada-37xx-declare-the-COMPHY.patch b/target/linux/mvebu/patches-5.4/543-arm64-dts-marvell-armada-37xx-declare-the-COMPHY.patch
|
|
deleted file mode 100644
|
|
index 393f8237944..00000000000
|
|
--- a/target/linux/mvebu/patches-5.4/543-arm64-dts-marvell-armada-37xx-declare-the-COMPHY.patch
|
|
+++ /dev/null
|
|
@@ -1,58 +0,0 @@
|
|
-From 2ef303f0fe44feee4a3ca8bd62fca86c105927d2 Mon Sep 17 00:00:00 2001
|
|
-From: Miquel Raynal <miquel.raynal@bootlin.com>
|
|
-Date: Tue, 8 Jan 2019 17:31:24 +0100
|
|
-Subject: [PATCH] arm64: dts: marvell: armada-37xx: declare the COMPHY
|
|
- node
|
|
-
|
|
-Describe the A3700 COMPHY node. It has three PHYs that can be
|
|
-configured as follow:
|
|
-* PCIe or GbE
|
|
-* USB3 or GbE
|
|
-* SATA or USB3
|
|
-Each of them has its own memory area.
|
|
-
|
|
-Suggested-by: Grzegorz Jaszczyk <jaz@semihalf.com>
|
|
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
|
|
-Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
|
|
----
|
|
- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 29 ++++++++++++++++++++++++++++
|
|
- 1 file changed, 29 insertions(+)
|
|
-
|
|
---- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
|
|
-+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
|
|
-@@ -235,6 +235,35 @@
|
|
- reg = <0x14000 0x60>;
|
|
- };
|
|
-
|
|
-+ comphy: phy@18300 {
|
|
-+ compatible = "marvell,comphy-a3700";
|
|
-+ reg = <0x18300 0x300>,
|
|
-+ <0x1F000 0x400>,
|
|
-+ <0x5C000 0x400>,
|
|
-+ <0xe0178 0x8>;
|
|
-+ reg-names = "comphy",
|
|
-+ "lane1_pcie_gbe",
|
|
-+ "lane0_usb3_gbe",
|
|
-+ "lane2_sata_usb3";
|
|
-+ #address-cells = <1>;
|
|
-+ #size-cells = <0>;
|
|
-+
|
|
-+ comphy0: phy@0 {
|
|
-+ reg = <0>;
|
|
-+ #phy-cells = <1>;
|
|
-+ };
|
|
-+
|
|
-+ comphy1: phy@1 {
|
|
-+ reg = <1>;
|
|
-+ #phy-cells = <1>;
|
|
-+ };
|
|
-+
|
|
-+ comphy2: phy@2 {
|
|
-+ reg = <2>;
|
|
-+ #phy-cells = <1>;
|
|
-+ };
|
|
-+ };
|
|
-+
|
|
- pinctrl_sb: pinctrl@18800 {
|
|
- compatible = "marvell,armada3710-sb-pinctrl",
|
|
- "syscon", "simple-mfd";
|
|
diff --git a/target/linux/mvebu/patches-5.4/544-arm64-dts-uDPU-fix-comphy-definitions.patch b/target/linux/mvebu/patches-5.4/544-arm64-dts-uDPU-fix-comphy-definitions.patch
|
|
deleted file mode 100644
|
|
index f72ea93b97e..00000000000
|
|
--- a/target/linux/mvebu/patches-5.4/544-arm64-dts-uDPU-fix-comphy-definitions.patch
|
|
+++ /dev/null
|
|
@@ -1,35 +0,0 @@
|
|
-From 9c222a1d78a1700220e38feb270f00d2ddd3c5ab Mon Sep 17 00:00:00 2001
|
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-From: Russell King <rmk+kernel@armlinux.org.uk>
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-Date: Wed, 6 Nov 2019 13:44:21 +0000
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-Subject: [PATCH 657/660] arm64: dts: uDPU: fix comphy definitions
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-
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-The uDPU uses both ethernet controllers, which ties up COMPHY 0 for
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-eth1 and COMPHY 1 for eth0, with no USB3 comphy. The addition of
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-COMPHY support made the kernel override the setup by the boot loader
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-breaking this platform. Delete the USB3 COMPHY definition at platform
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-level, and add phy specifications for the ethernet channels.
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-
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-Fixes: bd3d25b07342 ("arm64: dts: marvell: armada-37xx: link USB hosts with their PHYs")
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-Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
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----
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- arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts | 2 ++
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- 1 file changed, 2 insertions(+)
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-
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---- a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts
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-+++ b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts
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-@@ -143,6 +143,7 @@
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- status = "okay";
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- phy-mode = "sgmii";
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- managed = "in-band-status";
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-+ phys = <&comphy1 0>;
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- sfp = <&sfp_eth0>;
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- };
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-
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-@@ -150,6 +151,7 @@
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- status = "okay";
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- phy-mode = "sgmii";
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- managed = "in-band-status";
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-+ phys = <&comphy0 1>;
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- sfp = <&sfp_eth1>;
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- };
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-
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From 192ccdd1402b8e010b3d811372cd1146a123d461 Mon Sep 17 00:00:00 2001
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From: DENG Qingfang <dengqf6@mail2.sysu.edu.cn>
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Date: Wed, 4 Mar 2020 20:46:33 +0800
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Subject: [PATCH 4/4] mvebu: refresh config
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Signed-off-by: DENG Qingfang <dengqf6@mail2.sysu.edu.cn>
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---
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target/linux/mvebu/config-5.4 | 61 ++++++++++++++++++-------
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target/linux/mvebu/cortexa53/config-5.4 | 1 +
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target/linux/mvebu/cortexa72/config-5.4 | 1 +
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3 files changed, 47 insertions(+), 16 deletions(-)
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diff --git a/target/linux/mvebu/config-5.4 b/target/linux/mvebu/config-5.4
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index 24093fd386a..41a826ef7f8 100644
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--- a/target/linux/mvebu/config-5.4
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+++ b/target/linux/mvebu/config-5.4
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@@ -1,20 +1,25 @@
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CONFIG_AHCI_MVEBU=y
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CONFIG_ALIGNMENT_TRAP=y
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+CONFIG_ARCH_32BIT_OFF_T=y
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CONFIG_ARCH_CLOCKSOURCE_DATA=y
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+CONFIG_ARCH_HAS_BINFMT_FLAT=y
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CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y
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CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
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CONFIG_ARCH_HAS_FORTIFY_SOURCE=y
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CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
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CONFIG_ARCH_HAS_KCOV=y
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+CONFIG_ARCH_HAS_KEEPINITRD=y
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CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y
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CONFIG_ARCH_HAS_PHYS_TO_DMA=y
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+CONFIG_ARCH_HAS_SETUP_DMA_OPS=y
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CONFIG_ARCH_HAS_SET_MEMORY=y
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-CONFIG_ARCH_HAS_SG_CHAIN=y
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CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y
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CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y
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+CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y
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CONFIG_ARCH_HAS_TICK_BROADCAST=y
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CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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+CONFIG_ARCH_KEEP_MEMBLOCK=y
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CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
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CONFIG_ARCH_MULTIPLATFORM=y
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CONFIG_ARCH_MULTI_V6_V7=y
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@@ -29,17 +34,20 @@ CONFIG_ARCH_SUPPORTS_UPROBES=y
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CONFIG_ARCH_SUSPEND_POSSIBLE=y
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CONFIG_ARCH_USE_BUILTIN_BSWAP=y
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CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
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+CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
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CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
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CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
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CONFIG_ARM=y
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CONFIG_ARMADA_370_CLK=y
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CONFIG_ARMADA_370_XP_IRQ=y
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CONFIG_ARMADA_370_XP_TIMER=y
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+# CONFIG_ARMADA_37XX_WATCHDOG is not set
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CONFIG_ARMADA_38X_CLK=y
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CONFIG_ARMADA_THERMAL=y
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CONFIG_ARMADA_XP_CLK=y
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CONFIG_ARM_APPENDED_DTB=y
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# CONFIG_ARM_ARMADA_37XX_CPUFREQ is not set
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+# CONFIG_ARM_ARMADA_8K_CPUFREQ is not set
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CONFIG_ARM_ATAG_DTB_COMPAT=y
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# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
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# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
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@@ -66,6 +74,7 @@ CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
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CONFIG_ATA=y
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CONFIG_ATAGS=y
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CONFIG_AUTO_ZRELADDR=y
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+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
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CONFIG_BLK_DEV_LOOP=y
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CONFIG_BLK_DEV_SD=y
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CONFIG_BLK_MQ_PCI=y
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@@ -78,6 +87,7 @@ CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
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CONFIG_CLKSRC_MMIO=y
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CONFIG_CLONE_BACKWARDS=y
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CONFIG_COMMON_CLK=y
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+CONFIG_COMPAT_32BIT_TIME=y
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CONFIG_CPUFREQ_DT=y
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CONFIG_CPUFREQ_DT_PLATDEV=y
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CONFIG_CPU_32v6K=y
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@@ -104,8 +114,10 @@ CONFIG_CPU_FREQ_STAT=y
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CONFIG_CPU_HAS_ASID=y
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# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
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# CONFIG_CPU_ICACHE_DISABLE is not set
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+# CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND is not set
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CONFIG_CPU_IDLE=y
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CONFIG_CPU_IDLE_GOV_LADDER=y
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+# CONFIG_CPU_IDLE_GOV_TEO is not set
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CONFIG_CPU_PABRT_V7=y
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CONFIG_CPU_PJ4B=y
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CONFIG_CPU_PM=y
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@@ -122,6 +134,7 @@ CONFIG_CRYPTO_AEAD2=y
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CONFIG_CRYPTO_AES_ARM=y
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CONFIG_CRYPTO_AES_ARM_BS=y
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# CONFIG_CRYPTO_AES_ARM_CE is not set
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+CONFIG_CRYPTO_ALGAPI=y
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# CONFIG_CRYPTO_CHACHA20_NEON is not set
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CONFIG_CRYPTO_CRC32=y
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CONFIG_CRYPTO_CRC32C=y
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@@ -130,10 +143,13 @@ CONFIG_CRYPTO_CRYPTD=y
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CONFIG_CRYPTO_DEFLATE=y
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CONFIG_CRYPTO_DES=y
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CONFIG_CRYPTO_DEV_MARVELL_CESA=y
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+CONFIG_CRYPTO_ESSIV=y
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# CONFIG_CRYPTO_GHASH_ARM_CE is not set
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CONFIG_CRYPTO_HASH=y
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CONFIG_CRYPTO_HASH2=y
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+CONFIG_CRYPTO_HASH_INFO=y
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CONFIG_CRYPTO_HW=y
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+CONFIG_CRYPTO_LIB_DES=y
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CONFIG_CRYPTO_LZO=y
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CONFIG_CRYPTO_MANAGER=y
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CONFIG_CRYPTO_MANAGER2=y
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@@ -147,7 +163,7 @@ CONFIG_CRYPTO_SHA256_ARM=y
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# CONFIG_CRYPTO_SHA2_ARM_CE is not set
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CONFIG_CRYPTO_SHA512_ARM=y
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CONFIG_CRYPTO_SIMD=y
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-CONFIG_CRYPTO_WORKQUEUE=y
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+CONFIG_CRYPTO_ZSTD=y
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CONFIG_DCACHE_WORD_ACCESS=y
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CONFIG_DEBUG_ALIGN_RODATA=y
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CONFIG_DEBUG_INFO=y
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@@ -165,9 +181,11 @@ CONFIG_DEBUG_UART_VIRT=0xfec12000
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CONFIG_DEBUG_UNCOMPRESS=y
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CONFIG_DEBUG_USER=y
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CONFIG_DMADEVICES=y
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+CONFIG_DMA_DECLARE_COHERENT=y
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CONFIG_DMA_ENGINE=y
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CONFIG_DMA_ENGINE_RAID=y
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CONFIG_DMA_OF=y
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+CONFIG_DMA_REMAP=y
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CONFIG_DTC=y
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CONFIG_EARLY_PRINTK=y
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CONFIG_EDAC_ATOMIC_SCRUB=y
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@@ -183,6 +201,7 @@ CONFIG_FIXED_PHY=y
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CONFIG_FIX_EARLYCON_MEM=y
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CONFIG_FS_IOMAP=y
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CONFIG_FS_MBCACHE=y
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+CONFIG_FW_LOADER_PAGED_BUF=y
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CONFIG_GENERIC_ALLOCATOR=y
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CONFIG_GENERIC_ARCH_TOPOLOGY=y
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CONFIG_GENERIC_BUG=y
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@@ -234,6 +253,7 @@ CONFIG_HAVE_ARM_TWD=y
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CONFIG_HAVE_CLK=y
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CONFIG_HAVE_CLK_PREPARE=y
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CONFIG_HAVE_CONTEXT_TRACKING=y
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+CONFIG_HAVE_COPY_THREAD_TLS=y
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CONFIG_HAVE_C_RECORDMCOUNT=y
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CONFIG_HAVE_DEBUG_KMEMLEAK=y
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CONFIG_HAVE_DMA_CONTIGUOUS=y
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@@ -244,15 +264,14 @@ CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
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CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
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CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
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CONFIG_HAVE_FUNCTION_TRACER=y
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-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
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CONFIG_HAVE_IDE=y
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CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
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CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y
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-CONFIG_HAVE_MEMBLOCK=y
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CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
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CONFIG_HAVE_NET_DSA=y
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CONFIG_HAVE_OPROFILE=y
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CONFIG_HAVE_OPTPROBES=y
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+CONFIG_HAVE_PCI=y
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CONFIG_HAVE_PERF_EVENTS=y
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CONFIG_HAVE_PERF_REGS=y
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CONFIG_HAVE_PERF_USER_STACK_DUMP=y
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@@ -284,6 +303,7 @@ CONFIG_IRQ_FORCED_THREADING=y
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CONFIG_IRQ_WORK=y
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# CONFIG_IWMMXT is not set
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CONFIG_JBD2=y
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+# CONFIG_KASAN_STACK is not set
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CONFIG_LEDS_GPIO=y
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CONFIG_LEDS_PCA963X=y
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CONFIG_LEDS_TLC591XX=y
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@@ -310,7 +330,6 @@ CONFIG_MDIO_I2C=y
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CONFIG_MEMFD_CREATE=y
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CONFIG_MEMORY=y
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CONFIG_MIGHT_HAVE_CACHE_L2X0=y
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-CONFIG_MIGHT_HAVE_PCI=y
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CONFIG_MIGRATION=y
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CONFIG_MMC=y
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CONFIG_MMC_BLOCK=y
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@@ -322,10 +341,10 @@ CONFIG_MMC_SDHCI_PXAV3=y
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# CONFIG_MMC_TIFM_SD is not set
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CONFIG_MODULES_USE_ELF_REL=y
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CONFIG_MTD_CFI_STAA=y
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-CONFIG_MTD_M25P80=y
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-CONFIG_MTD_NAND=y
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-CONFIG_MTD_NAND_ECC=y
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+CONFIG_MTD_NAND_CORE=y
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+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
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CONFIG_MTD_NAND_MARVELL=y
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+CONFIG_MTD_RAW_NAND=y
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CONFIG_MTD_SPI_NOR=y
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CONFIG_MTD_SPLIT_FIRMWARE=y
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CONFIG_MTD_UBI=y
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@@ -344,11 +363,12 @@ CONFIG_MVMDIO=y
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CONFIG_MVNETA=y
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CONFIG_MVNETA_BM=y
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CONFIG_MVNETA_BM_ENABLE=y
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-CONFIG_MVPP2=y
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+# CONFIG_MVPP2 is not set
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CONFIG_MVSW61XX_PHY=y
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CONFIG_MV_XOR=y
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CONFIG_NEED_DMA_MAP_STATE=y
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CONFIG_NEON=y
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+CONFIG_NET_DEVLINK=y
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CONFIG_NET_DSA=y
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CONFIG_NET_DSA_MV88E6XXX=y
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CONFIG_NET_DSA_MV88E6XXX_GLOBAL2=y
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@@ -359,7 +379,6 @@ CONFIG_NET_FLOW_LIMIT=y
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CONFIG_NET_SWITCHDEV=y
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CONFIG_NLS=y
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CONFIG_NOP_USB_XCEIV=y
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-CONFIG_NO_BOOTMEM=y
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CONFIG_NR_CPUS=4
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CONFIG_NVMEM=y
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CONFIG_OF=y
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@@ -380,17 +399,19 @@ CONFIG_OUTER_CACHE_SYNC=y
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CONFIG_PADATA=y
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CONFIG_PAGE_OFFSET=0xC0000000
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CONFIG_PCI=y
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+CONFIG_PCI_BRIDGE_EMUL=y
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CONFIG_PCI_DOMAINS=y
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CONFIG_PCI_DOMAINS_GENERIC=y
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CONFIG_PCI_MSI=y
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CONFIG_PCI_MSI_IRQ_DOMAIN=y
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CONFIG_PCI_MVEBU=y
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-# CONFIG_PCI_V3_SEMI is not set
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CONFIG_PERF_USE_VMALLOC=y
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CONFIG_PGTABLE_LEVELS=2
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CONFIG_PHYLIB=y
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CONFIG_PHYLINK=y
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# CONFIG_PHY_MVEBU_A3700_COMPHY is not set
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+# CONFIG_PHY_MVEBU_A3700_UTMI is not set
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+# CONFIG_PHY_MVEBU_A38X_COMPHY is not set
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# CONFIG_PHY_MVEBU_CP110_COMPHY is not set
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_ARMADA_370=y
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@@ -415,7 +436,6 @@ CONFIG_REFCOUNT_FULL=y
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CONFIG_REGMAP=y
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CONFIG_REGMAP_I2C=y
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CONFIG_REGMAP_MMIO=y
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-CONFIG_REGMAP_SPI=y
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CONFIG_REGULATOR=y
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CONFIG_REGULATOR_FIXED_VOLTAGE=y
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CONFIG_RFS_ACCEL=y
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@@ -424,9 +444,7 @@ CONFIG_RTC_CLASS=y
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CONFIG_RTC_DRV_ARMADA38X=y
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CONFIG_RTC_DRV_MV=y
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CONFIG_RTC_I2C_AND_SPI=y
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-CONFIG_RTC_MC146818_LIB=y
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CONFIG_RWSEM_SPIN_ON_OWNER=y
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-CONFIG_RWSEM_XCHGADD_ALGORITHM=y
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CONFIG_SATA_AHCI_PLATFORM=y
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CONFIG_SATA_MV=y
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CONFIG_SATA_PMP=y
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@@ -434,7 +452,9 @@ CONFIG_SCSI=y
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CONFIG_SENSORS_PWM_FAN=y
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CONFIG_SENSORS_TMP421=y
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CONFIG_SERIAL_8250_DW=y
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-CONFIG_SERIAL_8250_FSL=y
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+CONFIG_SERIAL_8250_DWLIB=y
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+# CONFIG_SERIAL_8250_FSL is not set
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+CONFIG_SERIAL_MCTRL_GPIO=y
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CONFIG_SERIAL_MVEBU_CONSOLE=y
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CONFIG_SERIAL_MVEBU_UART=y
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CONFIG_SFP=y
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@@ -469,12 +489,18 @@ CONFIG_TIMER_PROBE=y
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CONFIG_TREE_RCU=y
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CONFIG_TREE_SRCU=y
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CONFIG_UBIFS_FS=y
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-# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
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+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
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CONFIG_UBIFS_FS_LZO=y
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CONFIG_UBIFS_FS_ZLIB=y
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+CONFIG_UBIFS_FS_ZSTD=y
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+# CONFIG_UBSAN_ALIGNMENT is not set
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CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
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+CONFIG_UNIX_SCM=y
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+CONFIG_UNWINDER_ARM=y
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+# CONFIG_UNWINDER_FRAME_POINTER is not set
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CONFIG_USB=y
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CONFIG_USB_COMMON=y
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+# CONFIG_USB_EHCI_FSL is not set
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_HCD_ORION=y
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CONFIG_USB_EHCI_HCD_PLATFORM=y
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@@ -490,9 +516,12 @@ CONFIG_VFP=y
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CONFIG_VFPv3=y
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CONFIG_WATCHDOG_CORE=y
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CONFIG_XPS=y
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+CONFIG_XXHASH=y
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CONFIG_XZ_DEC_ARM=y
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CONFIG_XZ_DEC_BCJ=y
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CONFIG_ZBOOT_ROM_BSS=0x0
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|
CONFIG_ZBOOT_ROM_TEXT=0x0
|
|
CONFIG_ZLIB_DEFLATE=y
|
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CONFIG_ZLIB_INFLATE=y
|
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+CONFIG_ZSTD_COMPRESS=y
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+CONFIG_ZSTD_DECOMPRESS=y
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|
diff --git a/target/linux/mvebu/cortexa53/config-5.4 b/target/linux/mvebu/cortexa53/config-5.4
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index 7f3c2b21de0..16d861be110 100644
|
|
--- a/target/linux/mvebu/cortexa53/config-5.4
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+++ b/target/linux/mvebu/cortexa53/config-5.4
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@@ -144,6 +144,7 @@ CONFIG_PCI_AARDVARK=y
|
|
CONFIG_PGTABLE_LEVELS=3
|
|
CONFIG_PHYS_ADDR_T_64BIT=y
|
|
CONFIG_PHY_MVEBU_A3700_COMPHY=y
|
|
+CONFIG_PHY_MVEBU_A3700_UTMI=y
|
|
CONFIG_PINCTRL_ARMADA_37XX=y
|
|
CONFIG_PINCTRL_ARMADA_AP806=y
|
|
CONFIG_PINCTRL_ARMADA_CP110=y
|
|
diff --git a/target/linux/mvebu/cortexa72/config-5.4 b/target/linux/mvebu/cortexa72/config-5.4
|
|
index c78eb843724..5727ae5918d 100644
|
|
--- a/target/linux/mvebu/cortexa72/config-5.4
|
|
+++ b/target/linux/mvebu/cortexa72/config-5.4
|
|
@@ -138,6 +138,7 @@ CONFIG_MVEBU_GICP=y
|
|
CONFIG_MVEBU_ICU=y
|
|
CONFIG_MVEBU_ODMI=y
|
|
CONFIG_MVEBU_PIC=y
|
|
+CONFIG_MVPP2=y
|
|
CONFIG_MV_XOR_V2=y
|
|
CONFIG_NEED_SG_DMA_LENGTH=y
|
|
# CONFIG_NUMA is not set
|