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62 lines
1.9 KiB
Diff
62 lines
1.9 KiB
Diff
From 068ec703d7b8b920c18c16e9eb8120b7ab91a0e0 Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Thu, 21 Dec 2017 13:32:09 -0800
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Subject: [PATCH 203/277] drm/vc4: Flush the caches before the render jobs, as
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well.
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If the frame samples from a render target that was just written, its
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cache flush during the binning step may have occurred before the
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previous frame's RCL was completed. Flush the texture caches again
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before starting each RCL job to make sure that the sampling of the
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previous RCL's output is correct.
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Fixes flickering in the top left of 3DMMES Taiji.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Fixes: ca26d28bbaa3 ("drm/vc4: improve throughput by pipelining binning and rendering jobs")
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---
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drivers/gpu/drm/vc4/vc4_gem.c | 21 +++++++++++++++++++++
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1 file changed, 21 insertions(+)
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diff --git a/drivers/gpu/drm/vc4/vc4_gem.c b/drivers/gpu/drm/vc4/vc4_gem.c
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index 152ce55160fe..c94cce96544c 100644
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--- a/drivers/gpu/drm/vc4/vc4_gem.c
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+++ b/drivers/gpu/drm/vc4/vc4_gem.c
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@@ -436,6 +436,19 @@ vc4_flush_caches(struct drm_device *dev)
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VC4_SET_FIELD(0xf, V3D_SLCACTL_ICC));
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}
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+static void
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+vc4_flush_texture_caches(struct drm_device *dev)
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+{
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+ struct vc4_dev *vc4 = to_vc4_dev(dev);
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+
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+ V3D_WRITE(V3D_L2CACTL,
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+ V3D_L2CACTL_L2CCLR);
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+
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+ V3D_WRITE(V3D_SLCACTL,
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+ VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) |
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+ VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC));
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+}
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+
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/* Sets the registers for the next job to be actually be executed in
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* the hardware.
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*
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@@ -474,6 +487,14 @@ vc4_submit_next_render_job(struct drm_device *dev)
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if (!exec)
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return;
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+ /* A previous RCL may have written to one of our textures, and
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+ * our full cache flush at bin time may have occurred before
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+ * that RCL completed. Flush the texture cache now, but not
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+ * the instructions or uniforms (since we don't write those
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+ * from an RCL).
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+ */
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+ vc4_flush_texture_caches(dev);
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+
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submit_cl(dev, 1, exec->ct1ca, exec->ct1ea);
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}
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--
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2.16.1
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