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			81 lines
		
	
	
	
		
			3.2 KiB
		
	
	
	
		
			Diff
		
	
	
	
	
	
| Subject: [PATCH v2] PCI: aardvark: Implement workaround for PCIe Completion Timeout
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| Date:   Tue,  2 Aug 2022 14:38:16 +0200
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| Message-Id: <20220802123816.21817-1-pali@kernel.org>
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| X-Mailer: git-send-email 2.20.1
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| MIME-Version: 1.0
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| Content-Type: text/plain; charset=UTF-8
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| Content-Transfer-Encoding: 8bit
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| Precedence: bulk
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| List-ID: <linux-pci.vger.kernel.org>
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| X-Mailing-List: linux-pci@vger.kernel.org
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| 
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| Marvell Armada 3700 Functional Errata, Guidelines, and Restrictions
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| document describes in erratum 3.12 PCIe Completion Timeout (Ref #: 251),
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| that PCIe IP does not support a strong-ordered model for inbound posted vs.
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| outbound completion.
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| 
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| As a workaround for this erratum, DIS_ORD_CHK flag in Debug Mux Control
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| register must be set. It disables the ordering check in the core between
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| Completions and Posted requests received from the link.
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| 
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| Marvell also suggests to do full memory barrier at the beginning of
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| aardvark summary interrupt handler before calling interrupt handlers of
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| endpoint drivers in order to minimize the risk for the race condition
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| documented in the Erratum between the DMA done status reading and the
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| completion of writing to the host memory.
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| 
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| More details about this issue and suggested workarounds are in discussion:
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| https://lore.kernel.org/linux-pci/BN9PR18MB425154FE5019DCAF2028A1D5DB8D9@BN9PR18MB4251.namprd18.prod.outlook.com/t/#u
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| 
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| It was reported that enabling this workaround fixes instability issues and
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| "Unhandled fault" errors when using 60 GHz WiFi 802.11ad card with Qualcomm
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| QCA6335 chip under significant load which were caused by interrupt status
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| stuck in the outbound CMPLT queue traced back to this erratum.
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| 
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| This workaround fixes also kernel panic triggered after some minutes of
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| usage 5 GHz WiFi 802.11ax card with Mediatek MT7915 chip:
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| 
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|     Internal error: synchronous external abort: 96000210 [#1] SMP
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|     Kernel panic - not syncing: Fatal exception in interrupt
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| 
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| Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
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| Signed-off-by: Pali Rohár <pali@kernel.org>
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| Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver")
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| Cc: stable@vger.kernel.org
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| ---
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|  drivers/pci/controller/pci-aardvark.c | 10 ++++++++++
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|  1 file changed, 10 insertions(+)
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| 
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| --- a/drivers/pci/controller/pci-aardvark.c
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| +++ b/drivers/pci/controller/pci-aardvark.c
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| @@ -212,6 +212,8 @@ enum {
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|  };
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|  
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|  #define VENDOR_ID_REG				(LMI_BASE_ADDR + 0x44)
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| +#define DEBUG_MUX_CTRL_REG			(LMI_BASE_ADDR + 0x208)
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| +#define     DIS_ORD_CHK				BIT(30)
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|  
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|  /* PCIe core controller registers */
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|  #define CTRL_CORE_BASE_ADDR			0x18000
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| @@ -560,6 +562,11 @@ static void advk_pcie_setup_hw(struct ad
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|  		PCIE_CORE_CTRL2_TD_ENABLE;
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|  	advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
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|  
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| +	/* Disable ordering checks, workaround for erratum 3.12 "PCIe completion timeout" */
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| +	reg = advk_readl(pcie, DEBUG_MUX_CTRL_REG);
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| +	reg |= DIS_ORD_CHK;
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| +	advk_writel(pcie, reg, DEBUG_MUX_CTRL_REG);
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| +
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|  	/* Set lane X1 */
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|  	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
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|  	reg &= ~LANE_CNT_MSK;
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| @@ -1661,6 +1668,9 @@ static irqreturn_t advk_pcie_irq_handler
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|  	struct advk_pcie *pcie = arg;
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|  	u32 status;
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|  
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| +	/* Full memory barrier (ARM dsb sy), workaround for erratum 3.12 "PCIe completion timeout" */
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| +	mb();
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| +
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|  	status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);
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|  	if (!(status & PCIE_IRQ_CORE_INT))
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|  		return IRQ_NONE;
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