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120 lines
3.4 KiB
Diff
120 lines
3.4 KiB
Diff
From d6515baf44e1f6aa4809edf0d0ca314ce9e35a66 Mon Sep 17 00:00:00 2001
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From: Ryder Lee <ryder.lee@mediatek.com>
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Date: Wed, 5 Sep 2018 18:22:19 +0800
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Subject: [PATCH 41/77] arm: dts: mt7623: add iommu/smi device nodes
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Add iommu/smi device nodes for MT7623.
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Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
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---
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arch/arm/boot/dts/mt7623.dtsi | 59 +++++++++++++++++++++++++++++++++++
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1 file changed, 59 insertions(+)
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diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
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index 35b0fa4112b0..7864c3804377 100644
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--- a/arch/arm/boot/dts/mt7623.dtsi
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+++ b/arch/arm/boot/dts/mt7623.dtsi
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@@ -13,6 +13,7 @@
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#include <dt-bindings/power/mt2701-power.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/phy/phy.h>
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+#include <dt-bindings/memory/mt2701-larb-port.h>
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#include <dt-bindings/reset/mt2701-resets.h>
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#include <dt-bindings/thermal/thermal.h>
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@@ -288,6 +289,17 @@
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clock-names = "system-clk", "rtc-clk";
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};
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+ smi_common: smi@1000c000 {
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+ compatible = "mediatek,mt7623-smi-common",
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+ "mediatek,mt2701-smi-common";
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+ reg = <0 0x1000c000 0 0x1000>;
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+ clocks = <&infracfg CLK_INFRA_SMI>,
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+ <&mmsys CLK_MM_SMI_COMMON>,
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+ <&infracfg CLK_INFRA_SMI>;
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+ clock-names = "apb", "smi", "async";
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+ power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
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+ };
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+
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pwrap: pwrap@1000d000 {
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compatible = "mediatek,mt7623-pwrap",
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"mediatek,mt2701-pwrap";
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@@ -319,6 +331,17 @@
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reg = <0 0x10200100 0 0x1c>;
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};
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+ iommu: mmsys_iommu@10205000 {
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+ compatible = "mediatek,mt7623-m4u",
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+ "mediatek,mt2701-m4u";
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+ reg = <0 0x10205000 0 0x1000>;
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+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&infracfg CLK_INFRA_M4U>;
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+ clock-names = "bclk";
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+ mediatek,larbs = <&larb0 &larb1 &larb2>;
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+ #iommu-cells = <1>;
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+ };
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+
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efuse: efuse@10206000 {
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compatible = "mediatek,mt7623-efuse",
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"mediatek,mt8173-efuse";
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@@ -746,6 +769,18 @@
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#clock-cells = <1>;
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};
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+ larb0: larb@14010000 {
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+ compatible = "mediatek,mt7623-smi-larb",
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+ "mediatek,mt2701-smi-larb";
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+ reg = <0 0x14010000 0 0x1000>;
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+ mediatek,smi = <&smi_common>;
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+ mediatek,larb-id = <0>;
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+ clocks = <&mmsys CLK_MM_SMI_LARB0>,
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+ <&mmsys CLK_MM_SMI_LARB0>;
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+ clock-names = "apb", "smi";
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+ power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
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+ };
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+
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imgsys: syscon@15000000 {
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compatible = "mediatek,mt7623-imgsys",
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"mediatek,mt2701-imgsys",
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@@ -754,6 +789,18 @@
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#clock-cells = <1>;
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};
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+ larb2: larb@15001000 {
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+ compatible = "mediatek,mt7623-smi-larb",
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+ "mediatek,mt2701-smi-larb";
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+ reg = <0 0x15001000 0 0x1000>;
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+ mediatek,smi = <&smi_common>;
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+ mediatek,larb-id = <2>;
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+ clocks = <&imgsys CLK_IMG_SMI_COMM>,
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+ <&imgsys CLK_IMG_SMI_COMM>;
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+ clock-names = "apb", "smi";
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+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
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+ };
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+
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vdecsys: syscon@16000000 {
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compatible = "mediatek,mt7623-vdecsys",
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"mediatek,mt2701-vdecsys",
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@@ -762,6 +809,18 @@
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#clock-cells = <1>;
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};
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+ larb1: larb@16010000 {
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+ compatible = "mediatek,mt7623-smi-larb",
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+ "mediatek,mt2701-smi-larb";
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+ reg = <0 0x16010000 0 0x1000>;
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+ mediatek,smi = <&smi_common>;
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+ mediatek,larb-id = <1>;
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+ clocks = <&vdecsys CLK_VDEC_CKGEN>,
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+ <&vdecsys CLK_VDEC_LARB>;
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+ clock-names = "apb", "smi";
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+ power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
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+ };
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+
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hifsys: syscon@1a000000 {
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compatible = "mediatek,mt7623-hifsys",
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"mediatek,mt2701-hifsys",
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--
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2.19.1
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