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https://github.com/Ysurac/openmptcprouter.git
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139 lines
3.8 KiB
Diff
139 lines
3.8 KiB
Diff
From 1330875dc2a3742fd41127e78d5036f2d8f261da Mon Sep 17 00:00:00 2001
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From: Peter Geis <pgwipeout@gmail.com>
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Date: Wed, 28 Jul 2021 14:00:31 -0400
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Subject: [PATCH] arm64: dts: rockchip: add rk3568 tsadc nodes
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Add the thermal and tsadc nodes to the rk3568 device tree.
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There are two sensors, one for the cpu, one for the gpu.
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Signed-off-by: Peter Geis <pgwipeout@gmail.com>
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Link: https://lore.kernel.org/r/20210728180034.717953-6-pgwipeout@gmail.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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.../boot/dts/rockchip/rk3568-pinctrl.dtsi | 9 +++
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arch/arm64/boot/dts/rockchip/rk356x.dtsi | 70 +++++++++++++++++++
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2 files changed, 79 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
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@@ -3108,4 +3108,13 @@
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<4 RK_PA0 3 &pcfg_pull_none_drv_level_2>;
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};
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};
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+
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+ tsadc {
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+ /omit-if-no-ref/
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+ tsadc_pin: tsadc-pin {
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+ rockchip,pins =
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+ /* tsadc_pin */
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+ <0 RK_PA1 0 &pcfg_pull_none>;
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+ };
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+ };
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};
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -50,6 +50,7 @@
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compatible = "arm,cortex-a55";
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reg = <0x0 0x0>;
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clocks = <&scmi_clk 0>;
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+ #cooling-cells = <2>;
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enable-method = "psci";
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operating-points-v2 = <&cpu0_opp_table>;
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};
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@@ -58,6 +59,7 @@
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x100>;
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+ #cooling-cells = <2>;
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enable-method = "psci";
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operating-points-v2 = <&cpu0_opp_table>;
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};
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@@ -66,6 +68,7 @@
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x200>;
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+ #cooling-cells = <2>;
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enable-method = "psci";
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operating-points-v2 = <&cpu0_opp_table>;
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};
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@@ -74,6 +77,7 @@
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0 0x300>;
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+ #cooling-cells = <2>;
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enable-method = "psci";
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operating-points-v2 = <&cpu0_opp_table>;
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};
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@@ -780,6 +784,72 @@
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status = "disabled";
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};
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+ thermal_zones: thermal-zones {
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+ cpu_thermal: cpu-thermal {
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+ polling-delay-passive = <100>;
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+ polling-delay = <1000>;
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+
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+ thermal-sensors = <&tsadc 0>;
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+
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+ trips {
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+ cpu_alert0: cpu_alert0 {
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+ temperature = <70000>;
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+ hysteresis = <2000>;
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+ type = "passive";
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+ };
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+ cpu_alert1: cpu_alert1 {
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+ temperature = <75000>;
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+ hysteresis = <2000>;
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+ type = "passive";
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+ };
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+ cpu_crit: cpu_crit {
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+ temperature = <95000>;
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+ hysteresis = <2000>;
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+ type = "critical";
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+ };
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+ };
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+
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+ cooling-maps {
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+ map0 {
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+ trip = <&cpu_alert0>;
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+ cooling-device =
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+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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+ };
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+ };
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+ };
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+
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+ gpu_thermal: gpu-thermal {
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+ polling-delay-passive = <20>; /* milliseconds */
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+ polling-delay = <1000>; /* milliseconds */
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+
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+ thermal-sensors = <&tsadc 1>;
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+ };
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+ };
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+
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+ tsadc: tsadc@fe710000 {
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+ compatible = "rockchip,rk3568-tsadc";
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+ reg = <0x0 0xfe710000 0x0 0x100>;
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+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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+ assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
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+ assigned-clock-rates = <17000000>, <700000>;
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+ clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
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+ clock-names = "tsadc", "apb_pclk";
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+ resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>,
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+ <&cru SRST_TSADCPHY>;
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+ reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
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+ rockchip,grf = <&grf>;
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+ rockchip,hw-tshut-temp = <95000>;
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+ pinctrl-names = "init", "default", "sleep";
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+ pinctrl-0 = <&tsadc_pin>;
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+ pinctrl-1 = <&tsadc_shutorg>;
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+ pinctrl-2 = <&tsadc_pin>;
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+ #thermal-sensor-cells = <1>;
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+ status = "disabled";
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+ };
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+
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saradc: saradc@fe720000 {
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compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
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reg = <0x0 0xfe720000 0x0 0x100>;
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