mirror of
https://github.com/Ysurac/openmptcprouter.git
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97 lines
3.1 KiB
Diff
97 lines
3.1 KiB
Diff
From aaa552d84580e9213d0e2bf0f9243477d1227bdd Mon Sep 17 00:00:00 2001
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From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
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Date: Sat, 27 Nov 2021 15:19:08 +0100
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Subject: [PATCH] arm64: dts: rockchip: Add spi nodes on rk356x
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This adds the four spi nodes (spi0, spi1, spi2, spi3) to the
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rk356x dtsi. These are from the downstream device tree, though
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I have double-checked that their interrupts and DMA numbers are
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correct. I have also tested spi1 with an SPI device.
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Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
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Link: https://lore.kernel.org/r/20211127141910.12649-3-frattaroli.nicolas@gmail.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk356x.dtsi | 64 ++++++++++++++++++++++++
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1 file changed, 64 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -39,6 +39,10 @@
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serial7 = &uart7;
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serial8 = &uart8;
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serial9 = &uart9;
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+ spi0 = &spi0;
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+ spi1 = &spi1;
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+ spi2 = &spi2;
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+ spi3 = &spi3;
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};
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cpus {
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@@ -742,6 +746,66 @@
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clock-names = "tclk", "pclk";
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};
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+ spi0: spi@fe610000 {
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+ compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
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+ reg = <0x0 0xfe610000 0x0 0x1000>;
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+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
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+ clock-names = "spiclk", "apb_pclk";
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+ dmas = <&dmac0 20>, <&dmac0 21>;
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+ dma-names = "tx", "rx";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ spi1: spi@fe620000 {
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+ compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
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+ reg = <0x0 0xfe620000 0x0 0x1000>;
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+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
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+ clock-names = "spiclk", "apb_pclk";
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+ dmas = <&dmac0 22>, <&dmac0 23>;
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+ dma-names = "tx", "rx";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ spi2: spi@fe630000 {
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+ compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
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+ reg = <0x0 0xfe630000 0x0 0x1000>;
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+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
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+ clock-names = "spiclk", "apb_pclk";
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+ dmas = <&dmac0 24>, <&dmac0 25>;
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+ dma-names = "tx", "rx";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ spi3: spi@fe640000 {
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+ compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
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+ reg = <0x0 0xfe640000 0x0 0x1000>;
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+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
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+ clock-names = "spiclk", "apb_pclk";
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+ dmas = <&dmac0 26>, <&dmac0 27>;
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+ dma-names = "tx", "rx";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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uart1: serial@fe650000 {
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compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
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reg = <0x0 0xfe650000 0x0 0x100>;
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