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32 lines
1.2 KiB
Diff
32 lines
1.2 KiB
Diff
From 64b69474edf3b885c19a89bb165f978ba1b4be00 Mon Sep 17 00:00:00 2001
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From: Jonas Karlman <jonas@kwiboo.se>
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Date: Tue, 10 Jan 2023 22:55:50 +0000
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Subject: [PATCH] arm64: dts: rockchip: assign rate to clk_rtc_32k on rk356x
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clk_rtc_32k and its child clock clk_hdmi_cec detauls to a rate of 24 MHz
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and not to 32 kHz on RK356x.
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Fix this by assigning clk_rtc_32k a rate of 32768, also assign the parent
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to clk_rtc32k_frac.
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Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
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Link: https://lore.kernel.org/r/20230110225547.1563119-2-jonas@kwiboo.se
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk356x.dtsi | 5 +++--
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1 file changed, 3 insertions(+), 2 deletions(-)
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -367,8 +367,9 @@
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clock-names = "xin24m";
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#clock-cells = <1>;
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#reset-cells = <1>;
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- assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
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- assigned-clock-rates = <1200000000>, <200000000>;
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+ assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
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+ assigned-clock-rates = <32768>, <1200000000>, <200000000>;
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+ assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
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rockchip,grf = <&grf>;
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};
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