mirror of
https://github.com/Ysurac/openmptcprouter.git
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144 lines
5 KiB
Diff
144 lines
5 KiB
Diff
From 7c3cb768cdb12033a0eff65d6e6b3a6c5bbd85c7 Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Fri, 17 Feb 2023 15:33:23 +0100
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Subject: [PATCH] drm/vc4: crtc: Add support for BCM2712 PixelValves
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The PixelValves found on the BCM2712 are similar to the ones found in
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the previous generation.
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Compared to BCM2711, the pixelvalves only drive one HDMI controller each
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and HDMI1 PixelValve has a FIFO long enough to support 4k at 60Hz.
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/gpu/drm/vc4/vc4_crtc.c | 53 ++++++++++++++++++++++++++++++++--
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drivers/gpu/drm/vc4/vc4_drv.h | 2 ++
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drivers/gpu/drm/vc4/vc4_regs.h | 5 ++++
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3 files changed, 58 insertions(+), 2 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_crtc.c
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+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
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@@ -239,6 +239,11 @@ static u32 vc4_get_fifo_full_level(struc
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const struct vc4_crtc_data *crtc_data = vc4_crtc_to_vc4_crtc_data(vc4_crtc);
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const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
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struct vc4_dev *vc4 = to_vc4_dev(vc4_crtc->base.dev);
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+
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+ /*
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+ * NOTE: Could we use register 0x68 (PV_HW_CFG1) to get the FIFO
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+ * size?
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+ */
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u32 fifo_len_bytes = pv_data->fifo_depth;
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/*
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@@ -393,6 +398,12 @@ static void vc4_crtc_config_pv(struct dr
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vc4_crtc_pixelvalve_reset(crtc);
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+ /*
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+ * NOTE: The BCM2712 has a H_OTE (Horizontal Odd Timing Enable)
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+ * bit that, when set, will allow to specify the timings in
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+ * pixels instead of cycles, thus allowing to specify odd
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+ * timings.
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+ */
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CRTC_WRITE(PV_HORZA,
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VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
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PV_HORZA_HBP) |
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@@ -462,11 +473,17 @@ static void vc4_crtc_config_pv(struct dr
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if (is_dsi)
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CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
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- if (vc4->gen == VC4_GEN_5)
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+ if (vc4->gen >= VC4_GEN_5)
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CRTC_WRITE(PV_MUX_CFG,
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VC4_SET_FIELD(PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP,
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PV_MUX_CFG_RGB_PIXEL_MUX_MODE));
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+ if (vc4->gen >= VC4_GEN_6)
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+ CRTC_WRITE(PV_PIPE_INIT_CTRL,
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+ VC4_SET_FIELD(1, PV_PIPE_INIT_CTRL_PV_INIT_WIDTH) |
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+ VC4_SET_FIELD(1, PV_PIPE_INIT_CTRL_PV_INIT_IDLE) |
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+ PV_PIPE_INIT_CTRL_PV_INIT_EN);
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+
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CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR |
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vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) |
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VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
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@@ -565,7 +582,11 @@ int vc4_crtc_disable_at_boot(struct drm_
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if (!(of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
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"brcm,bcm2711-pixelvalve2") ||
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of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
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- "brcm,bcm2711-pixelvalve4")))
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+ "brcm,bcm2711-pixelvalve4") ||
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+ of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
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+ "brcm,bcm2712-pixelvalve0") ||
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+ of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
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+ "brcm,bcm2712-pixelvalve1")))
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return 0;
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if (!(CRTC_READ(PV_CONTROL) & PV_CONTROL_EN))
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@@ -1304,6 +1325,32 @@ const struct vc4_pv_data bcm2711_pv4_dat
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},
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};
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+const struct vc4_pv_data bcm2712_pv0_data = {
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+ .base = {
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+ .debugfs_name = "crtc0_regs",
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+ .hvs_available_channels = BIT(0),
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+ .hvs_output = 0,
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+ },
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+ .fifo_depth = 64,
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+ .pixels_per_clock = 2,
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+ .encoder_types = {
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+ [0] = VC4_ENCODER_TYPE_HDMI0,
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+ },
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+};
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+
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+const struct vc4_pv_data bcm2712_pv1_data = {
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+ .base = {
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+ .debugfs_name = "crtc1_regs",
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+ .hvs_available_channels = BIT(1),
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+ .hvs_output = 1,
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+ },
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+ .fifo_depth = 64,
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+ .pixels_per_clock = 2,
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+ .encoder_types = {
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+ [0] = VC4_ENCODER_TYPE_HDMI1,
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+ },
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+};
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+
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static const struct of_device_id vc4_crtc_dt_match[] = {
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{ .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data },
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{ .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data },
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@@ -1313,6 +1360,8 @@ static const struct of_device_id vc4_crt
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{ .compatible = "brcm,bcm2711-pixelvalve2", .data = &bcm2711_pv2_data },
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{ .compatible = "brcm,bcm2711-pixelvalve3", .data = &bcm2711_pv3_data },
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{ .compatible = "brcm,bcm2711-pixelvalve4", .data = &bcm2711_pv4_data },
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+ { .compatible = "brcm,bcm2712-pixelvalve0", .data = &bcm2712_pv0_data },
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+ { .compatible = "brcm,bcm2712-pixelvalve1", .data = &bcm2712_pv1_data },
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{}
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};
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--- a/drivers/gpu/drm/vc4/vc4_drv.h
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+++ b/drivers/gpu/drm/vc4/vc4_drv.h
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@@ -583,6 +583,8 @@ extern const struct vc4_pv_data bcm2711_
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extern const struct vc4_pv_data bcm2711_pv2_data;
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extern const struct vc4_pv_data bcm2711_pv3_data;
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extern const struct vc4_pv_data bcm2711_pv4_data;
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+extern const struct vc4_pv_data bcm2712_pv0_data;
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+extern const struct vc4_pv_data bcm2712_pv1_data;
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struct vc5_gamma_entry {
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u32 x_c_terms;
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--- a/drivers/gpu/drm/vc4/vc4_regs.h
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+++ b/drivers/gpu/drm/vc4/vc4_regs.h
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@@ -215,6 +215,11 @@
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# define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_SHIFT 2
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# define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP 8
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+#define PV_PIPE_INIT_CTRL 0x94
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+# define PV_PIPE_INIT_CTRL_PV_INIT_WIDTH_MASK VC4_MASK(11, 8)
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+# define PV_PIPE_INIT_CTRL_PV_INIT_IDLE_MASK VC4_MASK(7, 4)
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+# define PV_PIPE_INIT_CTRL_PV_INIT_EN BIT(0)
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+
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#define SCALER_CHANNELS_COUNT 3
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#define SCALER_DISPCTRL 0x00000000
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